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luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/bram_fifo.vhd
| 4 | 6,636 |
-------------------------------------------------------------------------------
-- $Id: bram_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity BRAM_FIFO is
generic (
C_DATA_BITS : integer := 32;
C_ADDR_BITS : integer := 9
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Level : out std_logic_vector(0 to C_ADDR_BITS);
Full : out std_logic;
HalfFull : out std_logic;
HalfEmpty : out std_logic;
Overflow : out std_logic;
Underflow : out std_logic;
Empty : out std_logic
);
end entity BRAM_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of BRAM_FIFO is
component RAMB16_S36_S36
port(
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(8 downto 0);
ADDRB : in std_logic_vector(8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal in_address, out_address : unsigned(9 downto 0) := (others => '0');
signal addra, addrb : std_logic_vector(9 downto 0);
signal addr_diff : unsigned(9 downto 0);
signal overflow_i, underflow_i : std_logic;
signal empty_i, full_i : std_logic;
begin -- architecture IMP
addra <= CONV_STD_LOGIC_VECTOR(in_address,in_address'length);
addrb <= CONV_STD_LOGIC_VECTOR(out_address,out_address'length);
U1: RAMB16_S36_S36
port map(
DOA => open,
DOB => Data_Out,
DOPA => open,
DOPB => open,
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
CLKA => Clk,
CLKB => Clk,
DIA => Data_In,
DIB => (others => '0'),
DIPA => (others => '0'),
DIPB => (others => '0'),
ENA => '1',
ENB => '1',
SSRA => Reset,
SSRB => Reset,
WEA => FIFO_Write,
WEB => '0'
);
in_address_PROCESS: process (Clk,FIFO_Write)
begin
if Reset = '1' then
in_address <= (others => '0');
elsif (Clk'event and Clk='1') then
if (FIFO_Write = '1' and Clear_FIFO = '0') then
in_address <= in_address + 1;
elsif (Clear_FIFO = '1') then
in_address <= (others => '0');
end if;
end if;
end process;
out_address_PROCESS: process (Clk)
begin
if Reset = '1' then
out_address <= (others => '1');
elsif (Clk'event and Clk='1') then
if (FIFO_Read = '1' and Clear_FIFO = '0') then
out_address <= out_address + 1;
elsif (Clear_FIFO = '1') then
out_address <= (others => '1');
end if;
end if;
end process;
overflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
overflow_i <= '0';
elsif Full_i = '1' and FIFO_Write = '1' then
overflow_i <= '1';
end if;
end if;
end process;
overflow <= overflow_i;
underflow_PROCESS: process (Clk)
begin
if (Clk'event and Clk='1') then
if (Clear_FIFO = '1') then
underflow_i <= '0';
elsif Empty_i = '1' and FIFO_Read = '1' then
underflow_i <= '1';
end if;
end if;
end process;
underflow <= underflow_i;
addr_diff <= in_address - out_address - 1;
FIFO_Level <= CONV_STD_LOGIC_VECTOR(addr_diff,addr_diff'length);
HalfFull <= addr_diff(8);
HalfEmpty <= not addr_diff(8);
Empty_i <= '1' when addr_diff = 0 else '0';
Full_i <= '1' when (addr_diff = 512) else '0';
Empty <= Empty_i;
Full <= Full_i;
end architecture IMP;
|
gpl-3.0
|
a4559aa66366a0dacc1d2665a3a7a9f1
| 0.441079 | 3.772598 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_tlb_v2_01_a/hdl/vhdl/tlb_dcr.vhd
| 1 | 3,163 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity tlb_dcr is
generic
(
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
o_invalidate : out std_logic;
-- dcr bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrABus : in std_logic_vector(C_DCR_AWIDTH - 1 downto 0);
i_dcrDBus : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic
);
end entity;
architecture imp of tlb_dcr is
constant C_INVALIDATE : std_logic_vector := X"147A11DA";
signal dcr_hit : std_logic;
signal pid_hit : std_logic;
signal inv_hit : std_logic;
signal pid : std_logic_vector(31 downto 0);
signal inv_count : std_logic_vector(31 downto 0);
signal invalidate : std_logic;
begin
o_invalidate <= invalidate;
dcr_hit <= pid_hit or inv_hit;
address_decode : process (i_dcrABus)
begin
pid_hit <= '0';
inv_hit <= '0';
if i_dcrABus = C_DCR_BASEADDR then
pid_hit <= '1';
elsif i_dcrABus = C_DCR_BASEADDR + 1 then
inv_hit <= '1';
end if;
end process;
read_mux : process (dcr_hit, pid, inv_count)
begin
if pid_hit = '1' and i_dcrRead = '1' then
o_dcrDBus <= pid;
elsif inv_hit = '1' and i_dcrRead = '1' then
o_dcrDBus <= inv_count;
else
o_dcrDBus <= i_dcrDBus;
end if;
end process;
write_regs : process (clk, rst)
variable cmd : std_logic_vector(7 downto 0);
variable data : std_logic_vector(15 downto 0);
begin
if rst = '1' then
invalidate <= '0';
pid <= (others => '0');
inv_count <= (others => '0');
elsif rising_edge(clk) then
invalidate <= '0';
if i_dcrWrite = '1' then
if pid_hit = '1' then
pid <= i_dcrDBus;
elsif inv_hit = '1' and i_dcrDBus = C_INVALIDATE then
invalidate <= '1';
end if;
end if;
if (i_dcrWrite = '0' or inv_hit = '0') and invalidate = '1' then
inv_count <= inv_count + 1;
end if;
end if;
end process;
sync_ack : process (clk, rst)
begin
if rst = '1' then
o_dcrAck <= '0';
elsif rising_edge(clk) then
o_dcrAck <= dcr_hit;
end if;
end process;
end architecture;
|
gpl-3.0
|
8d277dee0c1544a7bc4c9c623cf0c883
| 0.507113 | 3.553933 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_arbiter.vhd
| 1 | 12,083 |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_mst_arbiter
-- Architectures: lipif_mst_arbiter_rtl
-- Description:
--
-- Dependencies:
--
-- Revision:
-- 10.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
library UNISIM;
use UNISIM.VComponents.all;
entity lipif_mst_arbiter is
generic(
C_NUM_WIDTH : integer := 5;
C_ARBITRATION : integer := 0;
C_EN_SRL16 : boolean := true
);
port(
clk : in std_logic;
reset : in std_logic;
-- Control Signals to/from Read and Write Controllers
rd_rdy_i : in std_logic;
rd_init_o : out std_logic;
rd_ack_o : out std_logic;
rd_rearb_o : out std_logic;
rd_retry_i : in std_logic;
rd_abort_i : in std_logic;
wr_rdy_i : in std_logic;
wr_init_o : out std_logic;
wr_ack_o : out std_logic;
wr_rearb_o : out std_logic;
wr_retry_i : in std_logic;
wr_abort_i : in std_logic;
-- LIS-IPIC Read Qualifiers
M_rdReq_i : in std_logic;
M_rdAccept_o : out std_logic;
M_rdAddr_i : in std_logic_vector(31 downto 0);
M_rdNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_rdBE_i : in std_logic_vector(7 downto 0);
M_rdPriority_i : in std_logic_vector(1 downto 0);
M_rdType_i : in std_logic_vector(2 downto 0);
M_rdCompress_i : in std_logic;
M_rdGuarded_i : in std_logic;
M_rdLockErr_i : in std_logic;
-- LIS-IPIC Write Qualifiers
M_wrReq_i : in std_logic;
M_wrAccept_o : out std_logic;
M_wrAddr_i : in std_logic_vector(31 downto 0);
M_wrNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_wrBE_i : in std_logic_vector(7 downto 0);
M_wrPriority_i : in std_logic_vector(1 downto 0);
M_wrType_i : in std_logic_vector(2 downto 0);
M_wrCompress_i : in std_logic;
M_wrGuarded_i : in std_logic;
M_wrOrdered_i : in std_logic;
M_wrLockErr_i : in std_logic;
-- LIS-IPIC Shared Qualifiers
M_Error_o : out std_logic;
M_Lock_i : in std_logic;
-- PLB Signals
PLB_MAddrAck : in std_logic;
PLB_MRearbitrate : in std_logic;
PLB_MErr : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_compress : out std_logic;
M_guarded : out std_logic;
M_ordered : out std_logic;
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31)
);
end lipif_mst_arbiter;
architecture lipif_mst_arbiter_rtl of lipif_mst_arbiter is
constant C_QUAL_WIDTH : integer := 54;
signal arb_qual : std_logic_vector(C_QUAL_WIDTH-1 downto 0);
signal arb_qual_req : std_logic;
signal arb_qual_rdy : std_logic;
signal plb_qual : std_logic_vector(C_QUAL_WIDTH-1 downto 0);
signal plb_qual_req : std_logic;
signal plb_qual_rdy : std_logic;
signal arb_nxt_rnw : std_logic; -- Transfer direction priority for next request
signal xfer_rnw : std_logic; -- Last transfer direction
signal arb_ini_rd : std_logic; -- Latch read qualifiers and launch request
signal arb_ini_wr : std_logic; -- Latch write qualifiers and launch request
signal plb_rearb : std_logic; -- Current request needs rearbitration
signal plb_rnw : std_logic; -- Current request direction
begin
-- TODO: Error, Bus Locking
M_Error_o <= '0'; -- PLB_MErr
-- TIMING(18%): TODO
M_busLock <= M_Lock_i;
-- Generate control signals to control unit.
-- Ignore AddrAck when aborting
rd_ack_o <= PLB_MAddrAck and plb_rnw and not rd_abort_i;
rd_rearb_o <= plb_rearb and plb_rnw;
wr_ack_o <= PLB_MAddrAck and not plb_rnw and not wr_abort_i;
wr_rearb_o <= plb_rearb and not plb_rnw;
-- Mask PLB request signal with the transfer's rearbitration status.
-- TIMING(8%): Both plb_qual_req and plb_rearb are register outputs, which should
-- give enough time for one LUT to combine them.
M_request <= plb_qual_req and not plb_rearb;
-- Discard request when the control unit asserts an abort.
-- The unit is responsible for ensuring that it has the arbiter's focus.
plb_qual_rdy <= PLB_MAddrAck or rd_abort_i or wr_abort_i;
-- Assert abort signal to PLB when aborting a transfer prior to address ack
-- TIMING(43%): plb_rearb is direct register output, xx_abort generated by rd/wr
-- controller with 3-input AND gate ("mst_term and prim_valid and not prim_ack")
M_abort <= (rd_abort_i or wr_abort_i) and not plb_rearb;
-- Calculate next read/write priority based on arbitration scheme
arb_nxt_rnw <= '1' when (C_ARBITRATION=1 or (C_ARBITRATION=0 and xfer_rnw='0')) else '0';
-- Arbitrate between read and write units
arb_ini_rd <= M_rdReq_i and rd_rdy_i and arb_qual_rdy and (arb_nxt_rnw or not M_wrReq_i or not wr_rdy_i);
arb_ini_wr <= M_wrReq_i and wr_rdy_i and arb_qual_rdy and (not arb_nxt_rnw or not M_rdReq_i or not rd_rdy_i);
arb_qual_req <= arb_ini_rd or arb_ini_wr;
-- Pass accept signals to output
M_rdAccept_o <= arb_ini_rd;
rd_init_o <= arb_ini_rd;
M_wrAccept_o <= arb_ini_wr;
wr_init_o <= arb_ini_wr;
-- Keep track of current transfer direction
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
xfer_rnw <= '0';
else
if(arb_ini_rd='1') then
xfer_rnw <= '1';
elsif(arb_ini_wr='1') then
xfer_rnw <= '0';
end if;
end if;
end if;
end process;
-- Keep track of the rearbitration state of the current request
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
plb_rearb <= '0';
else
-- plb_rearb is set when slave requests rearbitration
if(PLB_MRearbitrate='1' and PLB_MAddrAck='0') then
plb_rearb <= '1';
-- plb_rearb is negated when the associated control unit
-- aborts the transfer or signals a retry
elsif((plb_rnw='1' and (rd_retry_i='1' or rd_abort_i='1')) or
(plb_rnw='0' and (wr_retry_i='1' or wr_abort_i='1'))) then
plb_rearb <= '0';
end if;
end if;
end if;
end process;
-- Generate request qualifiers and merge onto single bus for pipebuf
process(arb_ini_rd, M_rdAddr_i, M_rdNum_i, M_rdBE_i, M_rdPriority_i, M_rdType_i,
M_rdCompress_i, M_rdGuarded_i, M_rdLockErr_i,
arb_ini_wr, M_wrAddr_i, M_wrNum_i, M_wrBE_i, M_wrPriority_i, M_wrType_i,
M_wrCompress_i, M_wrGuarded_i, M_wrOrdered_i, M_wrLockErr_i)
variable be_cnt : std_logic_vector(3 downto 0);
begin
if(arb_ini_rd='1') then
-- TODO: C_EN_RECALC_ADDR
arb_qual(31 downto 0) <= M_rdAddr_i; -- M_ABus(0 to 31)
-- TODO: Can BE be optimized? Maybe by calculating after muxing?
-- size and BE dependant on requested transfer length
if(CONV_INTEGER(UNSIGNED(M_rdNum_i))<=1) then
arb_qual(39 downto 32) <= M_rdBE_i; -- M_BE(0 to 7)
arb_qual(43 downto 40) <= "0000"; -- M_size(0 to 3)
else
-- Check for transfer longer than 16 dwords
if(CONV_INTEGER(UNSIGNED(M_rdNum_i))>16) then
arb_qual(39 downto 32) <= (others=>'0'); -- M_BE(0 to 7)
else
be_cnt := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(UNSIGNED(M_rdNum_i))-1, 4);
arb_qual(39 downto 36) <= be_cnt; -- M_BE(0 to 3)
arb_qual(35 downto 32) <= "0000"; -- M_BE(4 to 7)
end if;
arb_qual(43 downto 40) <= "1011"; -- M_size(0 to 3)
end if;
arb_qual(45 downto 44) <= M_rdPriority_i; -- M_priority(0 to 1)
arb_qual(46) <= '1'; -- M_RNW
arb_qual(49 downto 47) <= M_rdType_i; -- M_type(0 to 2);
arb_qual(50) <= M_rdCompress_i; -- M_compress
arb_qual(51) <= M_rdGuarded_i; -- M_guarded
arb_qual(52) <= '0'; -- M_ordered
arb_qual(53) <= M_rdLockErr_i; -- M_lockErr
else
-- TODO: C_EN_RECALC_ADDR
arb_qual(31 downto 0) <= M_wrAddr_i; -- M_ABus(0 to 31)
-- TODO: Can BE be optimized? Maybe by calculating after muxing?
-- size and BE dependant on requested transfer length
if(CONV_INTEGER(UNSIGNED(M_wrNum_i))<=1) then
arb_qual(39 downto 32) <= M_wrBE_i; -- M_BE(0 to 7)
arb_qual(43 downto 40) <= "0000"; -- M_size(0 to 3)
else
-- Check for transfer longer than 16 dwords
if(CONV_INTEGER(UNSIGNED(M_wrNum_i))>16) then
arb_qual(39 downto 32) <= (others=>'0'); -- M_BE(0 to 7)
else
be_cnt := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(UNSIGNED(M_wrNum_i))-1, 4);
arb_qual(39 downto 36) <= be_cnt; -- M_BE(0 to 3)
arb_qual(35 downto 32) <= "0000"; -- M_BE(4 to 7)
end if;
arb_qual(43 downto 40) <= "1011"; -- M_size(0 to 3)
end if;
arb_qual(45 downto 44) <= M_wrPriority_i; -- M_priority(0 to 1)
arb_qual(46) <= '0'; -- M_RNW
arb_qual(49 downto 47) <= M_wrType_i; -- M_type(0 to 2);
arb_qual(50) <= M_wrCompress_i; -- M_compress
arb_qual(51) <= M_wrGuarded_i; -- M_guarded
arb_qual(52) <= M_wrOrdered_i; -- M_ordered
arb_qual(53) <= M_wrLockErr_i; -- M_lockErr
end if;
end process;
-- Instantiate pipeline buffer
arb_pipebuf_0: entity lisipif_master_v1_00_c.lipif_mst_pipebuf
generic map (
C_DATA_WIDTH => C_QUAL_WIDTH,
-- Since SRL outputs are slow (>3ns after clk), must use registers
-- to meet PLB timings.
-- The good news: Even takes up fewer slices when using registers!
C_EN_SRL16 => false
)
port map (
clk => clk,
reset => reset,
-- Previous (input) stage I/O
prevReq_i => arb_qual_req,
prevRdy_o => arb_qual_rdy,
prevData_i => arb_qual,
-- Next (output) stage I/O
nextReq_o => plb_qual_req,
nextRdy_i => plb_qual_rdy,
nextData_o => plb_qual
);
-- Forward request qualifiers to PLB
-- TIMING(18%): Direct register outputs
M_ABus <= plb_qual(31 downto 0);
M_BE <= plb_qual(39 downto 32);
M_size <= plb_qual(43 downto 40);
M_type <= plb_qual(49 downto 47);
M_compress <= plb_qual(50);
M_guarded <= plb_qual(51);
M_ordered <= plb_qual(52);
M_lockErr <= plb_qual(53);
-- TIMING(8%): Direct register outputs
M_priority <= plb_qual(45 downto 44);
M_RNW <= plb_qual(46);
-- Transfer direction of current request for local use
plb_rnw <= plb_qual(46);
end lipif_mst_arbiter_rtl;
|
gpl-3.0
|
19e706b9da22ddad251bfbf356221a67
| 0.542994 | 3.336002 | false | false | false | false |
bzero/freezing-spice
|
src/alu.vhd
| 3 | 2,129 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity alu is
port (alu_func : in alu_func_t;
op1 : in word;
op2 : in word;
result : out word);
end entity alu;
architecture behavioral of alu is
begin -- architecture behavioral
-- purpose: arithmetic and logic
-- type : combinational
-- inputs : alu_func, op1, op2
-- outputs: result
alu_proc : process (alu_func, op1, op2) is
variable so1, so2 : signed(31 downto 0);
variable uo1, uo2 : unsigned(31 downto 0);
begin -- process alu_proc
so1 := signed(op1);
so2 := signed(op2);
uo1 := unsigned(op1);
uo2 := unsigned(op2);
case (alu_func) is
when ALU_ADD => result <= std_logic_vector(so1 + so2);
when ALU_ADDU => result <= std_logic_vector(uo1 + uo2);
when ALU_SUB => result <= std_logic_vector(so1 - so2);
when ALU_SUBU => result <= std_logic_vector(uo1 - uo2);
when ALU_SLT =>
if so1 < so2 then
result <= "00000000000000000000000000000001";
else
result <= (others => '0');
end if;
when ALU_SLTU =>
if uo1 < uo2 then
result <= "00000000000000000000000000000001";
else
result <= (others => '0');
end if;
when ALU_AND => result <= op1 and op2;
when ALU_OR => result <= op1 or op2;
when ALU_XOR => result <= op1 xor op2;
when ALU_SLL => result <= std_logic_vector(shift_left(uo1, to_integer(uo2(4 downto 0))));
when ALU_SRA => result <= std_logic_vector(shift_right(so1, to_integer(uo2(4 downto 0))));
when ALU_SRL => result <= std_logic_vector(shift_right(uo1, to_integer(uo2(4 downto 0))));
when others => result <= op1;
end case;
end process alu_proc;
end architecture behavioral;
|
bsd-3-clause
|
cd9d9a2d78bf7740bbacfd1fcf389c6b
| 0.510568 | 3.87796 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/Mem/synth/Mem.vhd
| 1 | 14,331 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY Mem IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Mem;
ARCHITECTURE Mem_arch OF Mem IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Mem_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Mem_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Mem_arch : ARCHITECTURE IS "Mem,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Mem_arch: ARCHITECTURE IS "Mem,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Mem.mif,C_INIT_FILE=Mem.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=131072,C_READ_DEPTH_A=131072,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=131072,C_READ_DEPTH_B=131072,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=32,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.5485 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "Mem.mif",
C_INIT_FILE => "Mem.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 131072,
C_READ_DEPTH_A => 131072,
C_ADDRA_WIDTH => 17,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 131072,
C_READ_DEPTH_B => 131072,
C_ADDRB_WIDTH => 17,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "32",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.5485 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 17)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END Mem_arch;
|
mit
|
f8a1245043b5152e6939cde145c6d315
| 0.625358 | 3.02278 | false | false | false | false |
five-elephants/hw-neural-sampling
|
virtex5/jtag_access.vhdl
| 1 | 3,242 |
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use unisim.vcomponents.all;
use work.sampling.all;
entity jtag_access is
generic (
num_samplers : integer;
num_observers : natural
);
port (
clk, reset : in std_ulogic;
joint_counters : in joint_counter_array_t(1 to num_observers);
systime : in systime_t
);
end jtag_access;
architecture virtex5 of jtag_access is
constant data_register_width : positive :=
systime_t'length + (num_observers * joint_counter_width);
subtype data_register_t is std_ulogic_vector(data_register_width-1 downto 0);
signal jtag_reset : std_ulogic;
signal capture : std_ulogic;
signal shift, tdi, tdo, drck : std_ulogic;
signal capture_sync_d, capture_sync : std_ulogic;
signal data_register, data_register_jtag : data_register_t;
begin
------------------------------------------------------------
-- Virtex5 BSCAN instance
------------------------------------------------------------
bscan: bscan_virtex5
generic map (
jtag_chain => 1
)
port map (
capture => capture,
drck => drck,
reset => jtag_reset,
sel => open,
shift => shift,
tdi => tdi,
update => open,
tdo => tdo
);
------------------------------------------------------------
-- data register capturing
------------------------------------------------------------
------------------------------------------------------------
capture_clk_sync: process ( clk, reset )
begin
if reset = '1' then
capture_sync_d <= '0';
capture_sync <= '0';
elsif rising_edge(clk) then
capture_sync_d <= capture;
capture_sync <= capture_sync_d;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
data_register_flop: process ( clk, reset )
variable a, b : natural;
begin
if reset = '1' then
data_register <= (others => '0');
elsif rising_edge(clk) then
if capture_sync = '1' then
data_register(systime'left downto systime'right) <= std_ulogic_vector(systime);
for i in 1 to num_observers loop
a := systime'length + (i * joint_counter_width) -1;
b := systime'length + ((i-1) * joint_counter_width);
data_register(a downto b) <= std_ulogic_vector(joint_counters(i));
end loop;
end if;
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
-- output mux
------------------------------------------------------------
------------------------------------------------------------
dr_shifter: process ( drck, jtag_reset )
begin
if jtag_reset = '1' then
tdo <= '0';
data_register_jtag <= (others => '0');
elsif rising_edge(drck) then
if shift = '1' then
data_register_jtag <=
tdi
& data_register_jtag(data_register_jtag'left downto 1);
tdo <= data_register_jtag(0);
else
data_register_jtag <= data_register;
end if;
end if;
end process;
------------------------------------------------------------
end virtex5;
|
apache-2.0
|
506d621d14527be4c0cadbf9e0bc6604
| 0.467613 | 4.477901 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/irq_gen_v1_1/f141c1dc/hdl/vhdl/axi_lite_ipif.vhd
| 2 | 14,090 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library my_ipif;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_num_ce;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity work.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
gpl-2.0
|
1996490f8d463e27149f4a73533584df
| 0.479418 | 4.131965 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_core_v2_03_a/hdl/vhdl/osif_core.vhd
| 1 | 30,895 |
--!
--! \file osif_core.vhd
--!
--! OSIF logic and interface to IPIF
--!
--! The osif_core contains processes for OS request handling. Also, it
--! instantiates the DCR slave module, which manages communication
--! between the CPU and the OSIF.
--!
--! There are two sets of registers, one for each direction (logic to bus
--! and bus to logic). Each set has the a register for command, data,
--! and extended data; the bus to logic set has another handshake register
--! indicating an incoming request from the DCR bus.
--!
--! Communication with the user task goes through the osif_task2os and
--! osif_os2task data structures, which are converted to std_logic_vectors
--! at the module interface, because XPS cannot handle VHDL records. An
--! incoming request from a task to perform an operating system call
--! is signalled by the request line of the task2os record. Requests can be
--! divided into two categories:
--!
--! - those that are handled in hardware without microprocessor
--! involvement (like shared memory accesses), and
--! - those that have to be handled in the microprocessor
--!
--! The first are handled directly within osif_core (and its submodules),
--! whereas the latter cause an interrupt to the microprocessor, preempt
--! any running processes there and wake up a software thread, which then
--! acts on behalf of the hardware thread.
--!
--!
--!
--!
--!
--! Memory bus interface fifo_manager
--! Memory (master/slave)
--! Bus <----------------------------+ ^
--! (e.g. PLB) | |
--! | +----------------+
--! _______|____|____
--! | |
--! clk, reset ------------------>| command_decoder |
--! |_________________|
--! | |
--! | +----------------+
--! Hardware | _____|__________
--! Thread <-----------------------------+ | |
--! Hardware Thread Control Interface | dcr_slave_regs |
--! |________________|
--! ^
--! |
--! V
--! D C R
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 01.08.2006 Enno Luebbers File created (from opb_reconos_slot_v1_00_c)
-- 03.08.2006 Enno Luebbers Added PLB bus master (moved to v1.01.a),
-- removed BRAM interface
-- 04.08.2006 Enno Luebbers moved user_logic to toplevel
-- 07.08.2006 Enno Luebbers moved logic to separate modules
-- (bus_master, bus_slave_regs)
-- xx.10.2007 Enno Luebbers added local FIFO manager
-- 23.11.2007 Enno Luebbers moved slave registers to DCR
-- 08.12.2008 Enno Luebbers modularized (moved memory bus controller
-- to separate module)
-- 10.12.2008 Enno Luebbers moved and renamed from user_logic to osif_core
--
--*************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library osif_core_v2_03_a;
use osif_core_v2_03_a.all;
entity osif_core is
generic
(
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_THREAD_RESET_CYCLES : natural := 10; -- number of cycles the thread reset is held
C_FIFO_DWIDTH : integer := 32;
C_BURSTLEN_WIDTH : integer := 5; -- max 16x64 bit bursts
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_TLB_TAG_WIDTH : integer := 20;
C_TLB_DATA_WIDTH : integer := 21;
C_ENABLE_MMU : boolean := true;
C_MMU_STAT_REGS : boolean := false;
C_DCR_ILA : integer := 0 -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- FIFO manager access signals
-- left (read) FIFO
o_fifomgr_read_remove : out std_logic;
i_fifomgr_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifomgr_read_wait : in std_logic;
-- right (write) FIFO
o_fifomgr_write_add : out std_logic;
o_fifomgr_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifomgr_write_wait : in std_logic;
-- memory access signals
o_mem_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
i_mem_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
o_mem_localAddr : out std_logic_vector(0 to C_AWIDTH-1);
o_mem_targetAddr : out std_logic_vector(0 to C_AWIDTH-1);
o_mem_singleRdReq : out std_logic;
o_mem_singleWrReq : out std_logic;
o_mem_burstRdReq : out std_logic;
o_mem_burstWrReq : out std_logic;
o_mem_burstLen : out std_logic_vector(0 to C_BURSTLEN_WIDTH-1);
i_mem_busy : in std_logic;
i_mem_rdDone : in std_logic;
i_mem_wrDone : in std_logic;
-- bus macro control
o_bm_enable : out std_logic;
-- tlb interface
i_tlb_rdata : in std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_wdata : out std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_tag : out std_logic_vector(C_TLB_TAG_WIDTH - 1 downto 0);
i_tlb_match : in std_logic;
o_tlb_we : out std_logic;
i_tlb_busy : in std_logic;
o_tlb_request : out std_logic;
-- dcr bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0)
);
end entity osif_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of osif_core is
--#################################################################################################################
-------
-- OS signals
-------
-- between os and task
signal osif_os2task : osif_os2task_t;
signal osif_task2os : osif_task2os_t;
-- FIXME: is there a better way than a handshake register?
signal os2task_newcmd : std_logic := '0';
signal request_blocking : std_logic := '0';
signal request_unblocking : std_logic := '0';
-- signal os2task_reset : std_logic := '0';
signal task2os_error : std_logic := '0'; -- FIXME: this is being ignored
-- dirty flag signals indicating unread data in read registers
signal slv_busy : std_logic;
signal post_sw_request : std_logic;
--
signal cdec_post : std_logic;
signal mmu_post : std_logic;
signal mmu_exception : std_logic;
signal cdec_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := (others => '0'); -- task2os command
signal cdec_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal cdec_datax : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
---------
-- slave register signals (put on DCR)
---------
signal slv_bus2osif_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
signal slv_bus2osif_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal slv_bus2osif_done : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal slv_osif2bus_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := (others => '0'); -- task2os command
signal slv_osif2bus_flags : std_logic_vector(0 to C_OSIF_FLAGS_WIDTH-1);
signal slv_osif2bus_saved_state_enc : std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1);
signal slv_osif2bus_saved_step_enc : std_logic_vector(0 to C_OSIF_STEP_ENC_WIDTH-1);
signal slv_osif2bus_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal slv_osif2bus_datax : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal slv_osif2bus_signature : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- hwthread signature
---------
-- status registers
---------
signal thread_init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- thread data (passed at initialization)
---------
-- local FIFO handles (used for FIFO message routing)
---------
signal fifo_read_handle : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal fifo_write_handle : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
---------
-- thread reset counter
---------
signal reset_counter : natural range 0 to C_THREAD_RESET_CYCLES-1 := C_THREAD_RESET_CYCLES-1;
signal request_reset : std_logic;
signal thread_reset_i : std_logic;
---------
-- signals for cooperative multithreading
---------
signal thread_is_resuming : std_logic;
signal yield_request : std_logic; -- request from OS to yield
signal yield_flag : std_logic; -- if '!', thread can yield
signal saved_state_enc : reconos_state_enc_t;
signal saved_step_enc : reconos_step_enc_t;
signal resume_state_enc : reconos_state_enc_t;
signal resume_step_enc : reconos_step_enc_t;
-- mmu diagnosis
signal mmu_tlb_miss_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal mmu_tlb_hit_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal mmu_page_fault_count : std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
signal mmu_state_fault : std_logic;
signal mmu_state_access_violation : std_logic;
-- mmu configuration and state
signal mmu_setpgd : std_logic;
signal mmu_repeat : std_logic;
signal mmu_config_data : std_logic_vector(0 to 31);
signal cdec_srrq : std_logic;
signal cdec_swrq : std_logic;
signal cdec_brrq : std_logic;
signal cdec_bwrq : std_logic;
signal cdec_laddr : std_logic_vector(31 downto 0);
signal cdec_raddr : std_logic_vector(31 downto 0);
signal mmu_data : std_logic_vector(31 downto 0);
signal mmu_busy : std_logic;
signal mmu_wrDone : std_logic;
signal mmu_rdDone : std_logic;
begin
enable_mmu : if C_ENABLE_MMU generate
handle_mmu_exception : process(sys_clk, sys_reset, mmu_exception)
variable step : integer range 0 to 1;
begin
if sys_reset = '1' then
mmu_post <= '0';
step := 0;
elsif rising_edge(sys_clk) then
case step is
when 0 =>
if mmu_exception = '1' then
mmu_post <= '1';
step := 1;
end if;
when 1 =>
mmu_post <= '0';
if mmu_exception = '0' then
step := 0;
end if;
end case;
end if;
end process;
post_mux : process(mmu_state_fault, mmu_exception,cdec_command, cdec_data, cdec_datax, mmu_data, cdec_post, mmu_post)
begin
if mmu_exception = '0' then
slv_osif2bus_command <= cdec_command;
slv_osif2bus_data <= cdec_data;
slv_osif2bus_datax <= cdec_datax;
post_sw_request <= cdec_post;
else
if mmu_state_fault = '1' then
slv_osif2bus_command <= OSIF_CMD_MMU_FAULT;
else
slv_osif2bus_command <= OSIF_CMD_MMU_ACCESS_VIOLATION;
end if;
slv_osif2bus_data <= mmu_data;
slv_osif2bus_datax <= X"22221111";
post_sw_request <= mmu_post;
end if;
end process;
mmu_exception <= mmu_state_fault or mmu_state_access_violation;
--post_sw_request <= cdec_post or mmu_post;
interrupt <= post_sw_request or cdec_post;
i_mmu : entity osif_core_v2_03_a.mmu
generic map
(
--C_BASEADDR => C_BASEADDR,
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_MMU_STAT_REGS => C_MMU_STAT_REGS
)
port map
(
clk => sys_clk,
rst => sys_reset,
-- incoming memory interface
i_swrq => cdec_swrq, --
i_srrq => cdec_srrq, --
i_bwrq => cdec_bwrq, --
i_brrq => cdec_brrq, --
i_addr => cdec_raddr,--
i_laddr => cdec_laddr,--
o_data => mmu_data, --
o_busy => mmu_busy,--
o_rdone => mmu_rdDone,--
o_wdone => mmu_wrDone,--
-- outgoing memory interface
o_swrq => o_mem_singleWrReq,
o_srrq => o_mem_singleRdReq,
o_bwrq => o_mem_burstWrReq,
o_brrq => o_mem_burstRdReq,
o_addr => o_mem_targetAddr,
o_laddr => o_mem_localAddr,
i_data => i_mem_singleData,
i_busy => i_mem_busy,
i_rdone => i_mem_rdDone,
i_wdone => i_mem_wrDone,
-- configuration interface
i_cfg => mmu_config_data,
i_setpgd => mmu_setpgd,
i_repeat => mmu_repeat,
-- interrupts
o_state_fault => mmu_state_fault,
o_state_access_violation => mmu_state_access_violation,
-- tlb interface
i_tlb_match => i_tlb_match,
i_tlb_busy => i_tlb_busy,
--i_tlb_wdone => i_tlb_wdone,
o_tlb_we => o_tlb_we,
i_tlb_data => i_tlb_rdata,
o_tlb_data => o_tlb_wdata,
o_tlb_tag => o_tlb_tag,
o_tlb_request => o_tlb_request,
-- diagnosis
o_tlb_miss_count => mmu_tlb_miss_count,
o_tlb_hit_count => mmu_tlb_hit_count,
o_page_fault_count => mmu_page_fault_count
);
end generate;
disable_mmu : if not C_ENABLE_MMU generate
interrupt <= cdec_post;
o_mem_singleWrReq <= cdec_swrq;
o_mem_singleRdReq <= cdec_srrq;
o_mem_burstWrReq <= cdec_bwrq;
o_mem_burstRdReq <= cdec_brrq;
o_mem_targetAddr <= cdec_raddr;
o_mem_localAddr <= cdec_laddr;
mmu_data <= i_mem_singleData;
mmu_busy <= i_mem_busy;
mmu_rdDone <= i_mem_rdDone;
mmu_wrDone <= i_mem_wrDone;
mmu_config_data <= (others => '0');
mmu_setpgd <= '0';
mmu_repeat <= '0';
mmu_state_fault <= '0';
mmu_state_access_violation <= '0';
mmu_tlb_miss_count <= (others => '0');
mmu_tlb_hit_count <= (others => '0');
mmu_page_fault_count <= (others => '0');
o_tlb_we <= '0';
o_tlb_wdata <= (others => '0');
o_tlb_tag <= (others => '0');
o_tlb_request <= '0';
end generate;
-- ################### MODULE INSTANTIATIONS ####################
-----------------------------------------------------------------------
-- dcr_slave_regs_inst: DCR bus slave instatiation
--
-- Handles access to the various registers.
-- NOTE: While slv_bus2osif_* signals are latched by bus_slave_regs,
-- the slv_osif2bus_* signals MUST BE STABLE until the transaction
-- is complete (busy goes low for s/w OS requests or the shm bus
-- bus master transaction completes).
-----------------------------------------------------------------------
dcr_slave_regs_inst : entity osif_core_v2_03_a.dcr_slave_regs
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_NUM_REGS => 4,
C_ENABLE_MMU => C_ENABLE_MMU,
C_INCLUDE_ILA => C_DCR_ILA
)
port map (
clk => sys_clk,
reset => thread_reset_i, --sys_reset,
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON,
-- user registers
i_osif2bus_command => slv_osif2bus_command,
i_osif2bus_flags => slv_osif2bus_flags,
i_osif2bus_saved_state_enc => slv_osif2bus_saved_state_enc,
i_osif2bus_saved_step_enc => slv_osif2bus_saved_step_enc,
i_osif2bus_data => slv_osif2bus_data,
i_osif2bus_datax => slv_osif2bus_datax,
i_osif2bus_signature => slv_osif2bus_signature,
o_bus2osif_command => slv_bus2osif_command,
o_bus2osif_data => slv_bus2osif_data,
o_bus2osif_done => slv_bus2osif_done,
i_tlb_miss_count => mmu_tlb_miss_count,
i_tlb_hit_count => mmu_tlb_hit_count,
i_page_fault_count => mmu_page_fault_count,
-- additional user interface
o_newcmd => os2task_newcmd,
i_post => post_sw_request,
o_busy => slv_busy
--o_interrupt => interrupt
);
-----------------------------------------------------------------------
-- command_decoder_inst: command decoder instatiation
--
-- Handles decoding the commands from the HW thread.
-- NOTE: the command decoder is completely asynchronous. It also
-- handles the setting and releasing of the osif_os2task.busy
-- and .blocking signals.
-----------------------------------------------------------------------
command_decoder_inst : entity osif_core_v2_03_a.command_decoder
generic map (
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH
)
port map (
i_clk => sys_clk,
i_reset => thread_reset_i, -- Bus2IP_Reset,
i_osif => osif_task2os,
o_osif => osif_os2task,
o_sw_request => cdec_post,
i_request_blocking => request_blocking,
i_release_blocking => request_unblocking,
i_init_data => thread_init_data,
o_bm_my_addr => cdec_laddr,
o_bm_target_addr => cdec_raddr,
o_bm_read_req => cdec_srrq,
o_bm_write_req => cdec_swrq,
o_bm_burst_read_req => cdec_brrq,
o_bm_burst_write_req => cdec_bwrq,
o_bm_burst_length => o_mem_burstLen,
i_bm_busy => mmu_busy,
i_bm_read_done => mmu_rdDone,
i_bm_write_done => mmu_wrDone,
i_slv_busy => slv_busy,
i_slv_bus2osif_command => slv_bus2osif_command,
i_slv_bus2osif_data => slv_bus2osif_data,
i_slv_bus2osif_shm => mmu_data,
o_slv_osif2bus_command => cdec_command,
o_slv_osif2bus_data => cdec_data,
o_slv_osif2bus_datax => cdec_datax,
o_slv_osif2bus_shm => o_mem_singleData,
o_hwthread_signature => slv_osif2bus_signature,
o_fifo_read_remove => o_fifomgr_read_remove,
i_fifo_read_data => i_fifomgr_read_data,
i_fifo_read_wait => i_fifomgr_read_wait,
o_fifo_write_add => o_fifomgr_write_add,
o_fifo_write_data => o_fifomgr_write_data,
i_fifo_write_wait => i_fifomgr_write_wait,
i_fifo_read_handle => fifo_read_handle,
i_fifo_write_handle => fifo_write_handle,
i_resume => thread_is_resuming,
i_yield => yield_request,
o_yield => yield_flag,
o_saved_state_enc => saved_state_enc,
o_saved_step_enc => saved_step_enc,
i_resume_state_enc => resume_state_enc,
i_resume_step_enc => resume_step_enc
);
-- ################### CONCURRENT ASSIGNMENTS ####################
-----------------------------------------------------------------------
-- User task signal routing
--
-- The user task is supplied with a dedicated clock and reset signal,
-- just in case we want to use them later.
-----------------------------------------------------------------------
task_clk <= sys_clk; --Bus2IP_Clk;
thread_reset_i <= '1' when reset_counter > 0 else '0';
task_reset <= thread_reset_i;
-- OSIF record to vector conversion (because EDK cannot handle records)
osif_os2task_vec <= to_std_logic_vector(osif_os2task);
osif_task2os <= to_osif_task2os_t(osif_task2os_vec);
-- FIXME: ignoring task error
task2os_error <= osif_task2os.error;
-- flags and yield control
slv_osif2bus_flags <= yield_flag & "0000000";
slv_osif2bus_saved_state_enc <= saved_state_enc;
slv_osif2bus_saved_step_enc <= saved_step_enc;
-- drive debug signals
busy <= osif_os2task.busy;
blocking <= osif_os2task.blocking;
-- ################### PROCESSES ####################
-----------------------------------------------------------------------
-- handle_os2task_response: Handles incoming OS commands
--
-- Especially the OSIF_CMD_UNBLOCK command, which signals that a
-- blocking OS call has returned.
-----------------------------------------------------------------------
-- FIXME: does this have to be synchronous?
handle_os2task_response : process(sys_clk, sys_reset)
begin
if sys_reset = '1' then
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
o_bm_enable <= '0'; -- bus macros are disabled by default!
thread_init_data <= (others => '0');
thread_is_resuming <= '0'; -- per default, the thread is not resumed, but created/started
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
yield_request <= '0';
elsif rising_edge(sys_clk) then
-- also reset everything on a synchronous thread_reset!
if thread_reset_i = '1' then
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
-- o_bm_enable <= '0'; -- do not disable bus macros on a thread reset (would break signature read)
thread_init_data <= (others => '0');
thread_is_resuming <= '0'; -- per default, the thread is not resumed, but created/started
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
-- yield_request <= '0'; -- yield_request is persistent across resets!
end if;
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
mmu_setpgd <= '0';
mmu_repeat <= '0';
if os2task_newcmd = '1' then
case slv_bus2osif_command(0 to C_OSIF_CMD_WIDTH-1) is
when OSIF_CMD_UNBLOCK =>
request_unblocking <= '1';
when OSIF_CMD_SET_INIT_DATA =>
thread_init_data <= slv_bus2osif_data;
when OSIF_CMD_RESET =>
request_blocking <= '1';
request_reset <= '1';
when OSIF_CMD_BUSMACRO =>
if slv_bus2osif_data = OSIF_DATA_BUSMACRO_DISABLE then -- disable
o_bm_enable <= '0';
else
o_bm_enable <= '1'; -- enable
end if;
when OSIF_CMD_SET_FIFO_READ_HANDLE =>
fifo_read_handle <= slv_bus2osif_data;
when OSIF_CMD_SET_FIFO_WRITE_HANDLE =>
fifo_write_handle <= slv_bus2osif_data;
when OSIF_CMD_SET_RESUME_STATE =>
resume_state_enc <= slv_bus2osif_data(0 to C_OSIF_STATE_ENC_WIDTH-1);
resume_step_enc <= slv_bus2osif_data(C_OSIF_STATE_ENC_WIDTH to C_OSIF_STATE_ENC_WIDTH+C_OSIF_STEP_ENC_WIDTH-1);
thread_is_resuming <= '1';
-- FIXME: do we need this?
when OSIF_CMD_CLEAR_RESUME_STATE =>
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
thread_is_resuming <= '0';
when OSIF_CMD_REQUEST_YIELD =>
yield_request <= '1';
when OSIF_CMD_CLEAR_YIELD =>
yield_request <= '0';
when OSIF_CMD_MMU_SETPGD =>
mmu_setpgd <= '1';
mmu_config_data <= slv_bus2osif_data;
when OSIF_CMD_MMU_REPEAT =>
mmu_repeat <= '1';
when others =>
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- reset_proc: handles reset of software thread
-----------------------------------------------------------------------
reset_proc: process(sys_clk, sys_reset)
begin
if sys_reset = '1' then
reset_counter <= C_THREAD_RESET_CYCLES-1;
elsif rising_edge(sys_clk) then
if request_reset = '1' then
reset_counter <= C_THREAD_RESET_CYCLES-1;
elsif reset_counter > 0 then
reset_counter <= reset_counter - 1;
end if;
end if;
end process;
end IMP;
|
gpl-3.0
|
ce2d22a67bbd1d3ae9a02ace8446e5b3
| 0.471403 | 4.09585 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/LocalRst.vhd
| 1 | 1,674 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 13:59:06 04/04/2011
-- Design Name:
-- Module Name: LocalRst - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module generates a synchronous reset signal with a length specified
-- by the RESET_PERIOD parameter
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LocalRst is
Generic ( RESET_PERIOD : natural := 4);
Port ( RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SRST_O : out STD_LOGIC);
end LocalRst;
architecture Behavioral of LocalRst is
signal RstQ : std_logic_vector(RESET_PERIOD downto 0) := (others => '1');
begin
RstQ(0) <= '0';
RESET_LINE: for i in 1 to RESET_PERIOD generate
process(CLK_I, RST_I)
begin
if (RST_I = '1') then
RstQ(i) <= '1';
elsif Rising_Edge(CLK_I) then
RstQ(i) <= RstQ(i-1);
end if;
end process;
end generate;
SRST_O <= RstQ(RESET_PERIOD);
end Behavioral;
|
gpl-3.0
|
9629f8f06617e5af79d02e0d2c4dd3a4
| 0.543011 | 3.985714 | false | false | false | false |
makestuff/vhdl
|
serialio/serialio.vhdl
| 1 | 4,652 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serialio is
port(
reset_in : in std_logic;
clk_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
load_in : in std_logic;
turbo_in : in std_logic;
busy_out : out std_logic;
sData_out : out std_logic;
sData_in : in std_logic;
sClk_out : out std_logic
);
end entity;
architecture behavioural of serialio is
type StateType is (
STATE_WAIT_FOR_DATA, -- idle state: wait for CPU to load some data
STATE_SCLK_LOW, -- drive LSB on sData whilst holding sClk low
STATE_SCLK_HIGH -- drive LSB on sData whilst holding sClk high
);
signal state, state_next : StateType;
signal shiftOut, shiftOut_next : std_logic_vector(7 downto 0); -- outbound shift reg
signal shiftIn, shiftIn_next : std_logic_vector(6 downto 0); -- inbound shift reg
signal inReg, inReg_next : std_logic_vector(7 downto 0); -- receive side dbl.buf
signal sClk, sClk_next : std_logic; -- serial clock
signal cycleCount, cycleCount_next : unsigned(5 downto 0); -- num cycles per 1/2 bit
signal bitCount, bitCount_next : unsigned(2 downto 0); -- num bits remaining
constant CLK_400kHz : unsigned(5 downto 0) := "111011"; -- count for 400kHz clk
constant CLK_24MHz : unsigned(5 downto 0) := "000000"; -- count for 24MHz clk
begin
-- All change!
process(clk_in, reset_in)
begin
if ( reset_in = '1' ) then
state <= STATE_WAIT_FOR_DATA;
shiftOut <= (others => '0');
shiftIn <= (others => '0');
inReg <= (others => '0');
sClk <= '1';
bitCount <= "000";
cycleCount <= (others => '0');
elsif ( clk_in'event and clk_in = '1' ) then
state <= state_next;
shiftOut <= shiftOut_next;
shiftIn <= shiftIn_next;
inReg <= inReg_next;
sClk <= sClk_next;
bitCount <= bitCount_next;
cycleCount <= cycleCount_next;
end if;
end process;
-- Next state logic
process(state, data_in, load_in, turbo_in, shiftOut, shiftIn, inReg, sData_in, sClk, cycleCount, bitCount)
begin
state_next <= state;
shiftOut_next <= shiftOut;
shiftIn_next <= shiftIn;
inReg_next <= inReg;
sClk_next <= sClk;
cycleCount_next <= cycleCount;
bitCount_next <= bitCount;
busy_out <= '1';
case state is
-- Wait for the CPU to give us some data to clock out
when STATE_WAIT_FOR_DATA =>
busy_out <= '0';
sClk_next <= '1';
sData_out <= '1';
if ( load_in = '1' ) then
-- The CPU has loaded some data...prepare to clock it out
state_next <= STATE_SCLK_LOW;
sClk_next <= '0';
shiftOut_next <= data_in;
bitCount_next <= "111";
if ( turbo_in = '1' ) then
cycleCount_next <= CLK_24MHz;
else
cycleCount_next <= CLK_400kHz;
end if;
end if;
-- Drive bit on sData, and hold sClk low for four cycles
when STATE_SCLK_LOW =>
sClk_next <= '0'; -- keep sClk low by default
sData_out <= shiftOut(0);
cycleCount_next <= cycleCount - 1;
if ( cycleCount = 0 ) then
-- Time to move on to STATE_SCLK_HIGH
state_next <= STATE_SCLK_HIGH;
sClk_next <= '1';
shiftIn_next <= sData_in & shiftIn(6 downto 1);
if ( turbo_in = '1' ) then
cycleCount_next <= CLK_24MHz;
else
cycleCount_next <= CLK_400kHz;
end if;
if ( bitCount = 0 ) then
inReg_next <= sData_in & shiftIn(6 downto 0);
end if;
end if;
-- Carry on driving bit on sData, hold sClk high for four cycles
when STATE_SCLK_HIGH =>
sClk_next <= '1';
sData_out <= shiftOut(0);
cycleCount_next <= cycleCount - 1;
if ( cycleCount = 0 ) then
-- Time to move back to STATE_SCLK_LOW or STATE_WAIT_FOR_DATA
shiftOut_next <= "0" & shiftOut(7 downto 1);
bitCount_next <= bitCount - 1;
if ( turbo_in = '1' ) then
cycleCount_next <= CLK_24MHz;
else
cycleCount_next <= CLK_400kHz;
end if;
if ( bitCount = 0 ) then
-- This was the last bit...go back to idle state
busy_out <= '0';
bitCount_next <= "111";
if ( load_in = '1' ) then
state_next <= STATE_SCLK_LOW;
sClk_next <= '0';
shiftOut_next <= data_in;
else
state_next <= STATE_WAIT_FOR_DATA;
sClk_next <= '1';
end if;
else
-- This was not the last bit...do another clock
state_next <= STATE_SCLK_LOW;
sClk_next <= '0';
end if;
end if;
end case;
end process;
sClk_out <= sClk;
data_out <= inReg;
end architecture;
|
gpl-3.0
|
d679db28609e9586892444fa2e0d9973
| 0.591788 | 3.147497 | false | false | false | false |
luebbers/reconos
|
support/templates/coregen/fifo/fifo.vhd
| 1 | 5,272 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo.vhd when simulating
-- the core, fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY fifo IS
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
END fifo;
ARCHITECTURE fifo_a OF fifo IS
-- synopsys translate_off
component wrapped_fifo
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo use entity XilinxCoreLib.fifo_generator_v3_2(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_implementation_type => 0,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 1,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_fifo
port map (
clk => clk,
din => din,
rd_en => rd_en,
rst => rst,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
valid => valid);
-- synopsys translate_on
END fifo_a;
|
gpl-3.0
|
9f5d3d4b96b51b4793587f8c45a8a4da
| 0.558232 | 3.62586 | false | false | false | false |
williammacdowell/gcm
|
src/tb/key_expansion_tb.vhd
| 1 | 2,758 |
-------------------------------------------------------------------------------
-- Title : Testbench for design "key_expansion"
-- Project : AES-GCM
-------------------------------------------------------------------------------
-- File : key_expansion_tb.vhd
-- Author : Bill MacDowell <bill@bill-macdowell-laptop>
-- Company :
-- Created : 2017-04-10
-- Last update: 2017-04-10
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Stimulates the key expansion block and verifies the output
-- against test vectors in the FIPS spec
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-04-10 1.0 bill Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity key_expansion_tb is
end entity key_expansion_tb;
-------------------------------------------------------------------------------
architecture tb of key_expansion_tb is
-- component ports
signal clk : std_logic := '1';
signal rst : std_logic;
signal key_in : std_logic_vector(255 downto 0);
signal round : std_logic_vector(3 downto 0);
signal en_key_gen : std_logic;
signal key_out : std_logic_vector(128 downto 0);
begin -- architecture tb
-- component instantiation
DUT : entity work.key_expansion
port map (
clk => clk,
rst => rst,
key_in => key_in,
round => round,
en_key_gen => en_key_gen,
key_out => key_out);
-- clock generation
clk <= not clk after 1 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- hold it in reset for 2 ns
wait for 2 ns;
rst <= '1';
en_key_gen <= '0';
key_in <= (others => '0');
wait for 4 ns;
rst <= '0';
wait for 4 ns;
-- set up the input
en_key_gen <= '1';
key_in <= x"0914dff42d9810a33b6108d71f352c07857d77812b73aef015ca71be603deb10";
-- kill the sim after some time
wait for 10 us;
assert false report "Done!" severity failure;
end process WaveGen_Proc;
end architecture tb;
-------------------------------------------------------------------------------
configuration key_expansion_tb_tb_cfg of key_expansion_tb is
for tb
end for;
end key_expansion_tb_tb_cfg;
-------------------------------------------------------------------------------
|
gpl-3.0
|
c59c3335741a9315460aae0770ff09ac
| 0.431835 | 4.528736 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/wb_simple_uart.vhd
| 1 | 9,768 |
-------------------------------------------------------------------------------
-- Title : Simple Wishbone UART
-- Project : General Cores Collection (gencores) library
-------------------------------------------------------------------------------
-- File : wb_simple_uart.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2011-02-21
-- Last update: 2011-10-04
-- Platform : FPGA-generics
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple UART controller, providing two modes of operation
-- (both can be used simultenously):
-- - physical UART (encoding fixed to 8 data bits, no parity and one stop bit)
-- - virtual UART: TXed data is passed via a FIFO to the Wishbone host (and
-- vice versa).
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-02-21 1.0 twlostow Created
-- 2011-10-04 1.1 twlostow merged with VUART, added adapter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.UART_wbgen2_pkg.all;
entity wb_simple_uart is
generic(
g_with_virtual_uart : boolean;
g_with_physical_uart : boolean;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
);
end wb_simple_uart;
architecture syn of wb_simple_uart is
constant c_baud_acc_width : integer := 16;
component uart_baud_gen
generic (
g_baud_acc_width : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baudrate_i : in std_logic_vector(g_baud_acc_width downto 0);
baud_tick_o : out std_logic;
baud8_tick_o : out std_logic);
end component;
component uart_async_rx
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud8_tick_i : in std_logic;
rxd_i : in std_logic;
rx_ready_o : out std_logic;
rx_error_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0));
end component;
component uart_async_tx
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud_tick_i : in std_logic;
txd_o : out std_logic;
tx_start_p_i : in std_logic;
tx_data_i : in std_logic_vector(7 downto 0);
tx_busy_o : out std_logic);
end component;
component simple_uart_wb
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
rdr_rack_o : out std_logic;
host_rack_o : out std_logic;
regs_i : in t_uart_in_registers;
regs_o : out t_uart_out_registers
);
end component;
signal rx_ready_reg : std_logic;
signal rx_ready : std_logic;
signal uart_bcr : std_logic_vector(31 downto 0);
signal rdr_rack : std_logic;
signal host_rack : std_logic;
signal baud_tick : std_logic;
signal baud_tick8 : std_logic;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal regs_in : t_UART_in_registers;
signal regs_out : t_UART_out_registers;
signal fifo_empty, fifo_full, fifo_rd, fifo_wr : std_logic;
signal fifo_count : std_logic_vector(f_log2_size(g_vuart_fifo_size)-1 downto 0);
signal phys_rx_ready, phys_tx_busy : std_logic;
signal phys_rx_data : std_logic_vector(7 downto 0);
begin -- syn
gen_check_generics : if(not g_with_physical_uart and not g_with_virtual_uart) generate
assert false report "wb_simple_uart: dummy configuration (use virtual, physical or both uarts)" severity failure;
end generate gen_check_generics;
resized_addr(4 downto 0) <= wb_adr_i;
resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
U_Adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o);
U_WB_SLAVE : simple_uart_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
rdr_rack_o => rdr_rack,
host_rack_o => host_rack,
regs_o => regs_out,
regs_i => regs_in);
gen_phys_uart : if(g_with_physical_uart) generate
p_bcr_reg : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
uart_bcr <= (others => '0');
elsif(regs_out.bcr_wr_o = '1')then
uart_bcr <= regs_out.bcr_o;
end if;
end if;
end process;
U_BAUD_GEN : uart_baud_gen
generic map (
g_baud_acc_width => c_baud_acc_width)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
baudrate_i => uart_bcr(c_baud_acc_width downto 0),
baud_tick_o => baud_tick,
baud8_tick_o => baud_tick8);
U_TX : uart_async_tx
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
baud_tick_i => baud_tick,
txd_o => uart_txd_o,
tx_start_p_i => regs_out.tdr_tx_data_wr_o,
tx_data_i => regs_out.tdr_tx_data_o,
tx_busy_o => phys_tx_busy);
U_RX : uart_async_rx
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
baud8_tick_i => baud_tick8,
rxd_i => uart_rxd_i,
rx_ready_o => phys_rx_ready,
rx_error_o => open,
rx_data_o => phys_rx_data);
end generate gen_phys_uart;
gen_vuart : if(g_with_virtual_uart) generate
fifo_wr <= not fifo_full and regs_out.tdr_tx_data_wr_o;
fifo_rd <= not fifo_empty and not regs_in.host_rdr_rdy_i;
U_VUART_FIFO : generic_sync_fifo
generic map (
g_data_width => 8,
g_size => g_vuart_fifo_size,
g_with_count => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
d_i => regs_out.tdr_tx_data_o,
we_i => fifo_wr,
q_o => regs_in.host_rdr_data_i,
rd_i => fifo_rd,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => fifo_count);
regs_in.host_rdr_count_i(fifo_count'left downto 0) <= fifo_count;
regs_in.host_rdr_count_i(15 downto fifo_count'length) <= (others => '0');
p_vuart_rx_ready : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_in.host_rdr_rdy_i <= '0';
elsif(fifo_rd = '1') then
regs_in.host_rdr_rdy_i <= '1';
elsif(host_rack = '1') then
regs_in.host_rdr_rdy_i <= '0';
end if;
end if;
end process;
end generate gen_vuart;
p_drive_rx_ready : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
regs_in.sr_rx_rdy_i <= '0';
regs_in.rdr_rx_data_i <= (others => '0');
else
if(rdr_rack = '1' and phys_rx_ready = '0' and regs_out.host_tdr_data_wr_o = '0') then
regs_in.sr_rx_rdy_i <= '0';
elsif(phys_rx_ready = '1' and g_with_physical_uart) then
regs_in.sr_rx_rdy_i <= '1';
regs_in.rdr_rx_data_i <= phys_rx_data;
elsif(regs_out.host_tdr_data_wr_o = '1' and g_with_virtual_uart) then
regs_in.sr_rx_rdy_i <= '1';
regs_in.rdr_rx_data_i <= regs_out.host_tdr_data_o;
end if;
end if;
end if;
end process;
regs_in.sr_tx_busy_i <= phys_tx_busy when (g_with_physical_uart) else '0';
regs_in.host_tdr_rdy_i <= not regs_in.sr_rx_rdy_i;
end syn;
|
lgpl-3.0
|
c573f15cfd655665a26aa18efa1582f2
| 0.524263 | 3.013885 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/thermal_monitor_v1_03_a/hdl/vhdl/thermal_sensor.vhd
| 1 | 3,028 |
----------------------------------------------------------------------------------
-- Company: University of Paderborn
-- Engineer: Markus Happe
--
-- Create Date: 12:17:11 02/09/2011
-- Design Name:
-- Module Name: thermal_sensor - Behavioral
-- Project Name: Thermal Sensor Net
-- Target Devices: Virtex 6 ML605
-- Tool versions: 12.3
-- Description: thermal sensor: ring oscilator that can be used as a temperature sensor.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity thermal_sensor is
generic (C_COUNTER_WIDTH : integer := 18);
port ( -- clock
clk : in std_logic;
-- reset
rst : in std_logic;
-- enable ring oscilator
osc_en : in std_logic;
-- enable recording
rec_en : in std_logic;
-- data
data : out std_logic_vector(C_COUNTER_WIDTH - 1 downto 0);
-- debug output: ring oscillator output
osc_sig : out std_logic;
-- debug output: count signal
count_sig : out std_logic
);
end thermal_sensor;
architecture Behavioral of thermal_sensor is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
component ring_oscillator is
generic ( C_OSC_SIZE : integer := 11);
port ( rst : in std_logic;
osc_en : in std_logic;
osc_out : out std_logic);
end component;
signal osc_out : std_logic;
signal osc_out_old : std_logic;
signal osc_out_old_2 : std_logic;
signal rec_en_old : std_logic;
signal counter : std_logic_vector(C_COUNTER_WIDTH-1 downto 0);
begin
data <= counter;
-- ring oscillator
osc : component ring_oscillator
generic map (C_OSC_SIZE => 11)
port map ( rst => rst, osc_en => osc_en, osc_out => osc_out);
osc_sig <= osc_out;
-- process that counts the ring_oscilator and shift them out
count : process(clk, rst)
begin
if rst = '1' then
-- reset old signals and counter
rec_en_old <= rec_en;
osc_out_old <= osc_out;
osc_out_old_2 <= osc_out;
counter <= (others=>'0');
count_sig <= '0';
--counter <= b"00011100001111";
elsif rising_edge(clk) then
-- store old signals for rec_en and osc_out
rec_en_old <= rec_en;
osc_out_old <= osc_out;
osc_out_old_2 <= osc_out_old;
count_sig <= '0';
--counter <= b"10000000000001";--XXX
-- record a thermal measurement
if rec_en = '1' then
-- if the ring oscillator has a rising edge, increase counter by 1
--counter <= counter + 1;
--counter <= b"10000000000001";
if (osc_out_old='1' and osc_out_old_2='0') then
count_sig <= '1';
counter <= counter + 1;
end if;
-- reset counter if a new record has started
if rec_en_old = '0' then
counter <= (others=>'0');
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
afd81a3dbb8512cf4b2ada7d57906831
| 0.594122 | 3.398429 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/third.vhd
| 1 | 29,140 |
--!
--! \file third.vhd
--!
--! \author Ariane Keller
--! \date 23.03.2011
-- Demo file for the multibus. This file will be executed in slot 2.
-- It can also send and receive data to/from the Ethernet interface.
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library unisim;
use unisim.vcomponents.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity third is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_NR_SLOTS : integer := 3
);
port (
-- user defined signals: use the signal names defined in the system.ucf file!
-- user defined signals only work if they are before the reconos signals!
-- Signals for the Ethernet interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
-- SGMII-transceiver reference clock buffer input
MGTCLK_P : in std_logic;
MGTCLK_N : in std_logic;
-- Asynchronous reset
PRE_PHY_RESET : in std_logic;
PHY_RESET : out std_logic;
-- Signals for the Multibus
ready_2 : out std_logic;
req_2 : out std_logic_vector(0 to 3 - 1);
grant_2 : in std_logic_vector(0 to 3 - 1);
data_2 : out std_logic_vector(0 to 3 * 32 - 1);
sof_2 : out std_logic_vector(0 to C_NR_SLOTS - 1);
eof_2 : out std_logic_vector(0 to C_NR_SLOTS - 1);
src_rdy_2 : out std_logic_vector(0 to C_NR_SLOTS - 1);
dst_rdy_2 : in std_logic_vector(0 to C_NR_SLOTS - 1);
busdata_2 : in std_logic_vector(0 to 32 - 1);
bussof_2 : in std_logic;
buseof_2 : in std_logic;
bus_dst_rdy_2 : out std_logic;
bus_src_rdy_2 : in std_logic;
-- end user defined ports
-- normal reconOS signals
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- second ram
o_RAMAddr_x : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData_x : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData_x : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE_x : out std_logic;
o_RAMClk_x : out std_logic
);
end third;
architecture Behavioral of third is
-----------------start component declaration------------------------------
-- Component declaration for the LocalLink-level EMAC wrapper
component v6_emac_v1_4_locallink is
port(
-- 125MHz clock output from transceiver
CLK125_OUT : out std_logic;
-- 125MHz clock input from BUFG
CLK125 : in std_logic;
-- LocalLink receiver interface
RX_LL_CLOCK : in std_logic;
RX_LL_RESET : in std_logic;
RX_LL_DATA : out std_logic_vector(7 downto 0);
RX_LL_SOF_N : out std_logic;
RX_LL_EOF_N : out std_logic;
RX_LL_SRC_RDY_N : out std_logic;
RX_LL_DST_RDY_N : in std_logic;
RX_LL_FIFO_STATUS : out std_logic_vector(3 downto 0);
-- LocalLink transmitter interface
TX_LL_CLOCK : in std_logic;
TX_LL_RESET : in std_logic;
TX_LL_DATA : in std_logic_vector(7 downto 0);
TX_LL_SOF_N : in std_logic;
TX_LL_EOF_N : in std_logic;
TX_LL_SRC_RDY_N : in std_logic;
TX_LL_DST_RDY_N : out std_logic;
-- Client receiver interface
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client Transmitter Interface
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
EMACANINTERRUPT : out std_logic;
-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
RESETDONE : out std_logic;
-- SGMII transceiver clock buffer input
CLK_DS : in std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end component;
-- Component declaration for the ll_fifo. This is used on the transmit
-- and on the receive side to convert from a data width of 8 bits to 32 bits.
component ll_fifo
generic (
MEM_TYPE : integer := 0; -- 0 choose BRAM,
-- 1 choose Distributed RAM
BRAM_MACRO_NUM : integer := 16; -- Memory Depth. For BRAM only
DRAM_DEPTH : integer := 16; -- Memory Depth. For DRAM only
WR_DWIDTH : integer := 32; -- FIFO write data width,
-- Acceptable values are
-- 8, 16, 32, 64, 128.
RD_DWIDTH : integer := 8; -- FIFO read data width,
-- Acceptable values are
-- 8, 16, 32, 64, 128.
RD_REM_WIDTH : integer := 1; -- Remainder width of read data
WR_REM_WIDTH : integer := 2; -- Remainder width of write data
USE_LENGTH : boolean := false; -- Length FIFO option
glbtm : time := 1 ns -- Global timing delay for simulation
);
port (
-- Reset
areset_in : in std_logic;
-- clocks
write_clock_in : in std_logic;
read_clock_in : in std_logic;
-- Interface to downstream user application
data_out : out std_logic_vector(0 to RD_DWIDTH-1);
rem_out : out std_logic_vector(0 to RD_REM_WIDTH-1);
sof_out_n : out std_logic;
eof_out_n : out std_logic;
src_rdy_out_n : out std_logic;
dst_rdy_in_n : in std_logic;
-- Interface to upstream user application
data_in : in std_logic_vector(0 to WR_DWIDTH-1);
rem_in : in std_logic_vector(0 to WR_REM_WIDTH-1);
sof_in_n : in std_logic;
eof_in_n : in std_logic;
src_rdy_in_n : in std_logic;
dst_rdy_out_n : out std_logic;
-- FIFO status signals
fifostatus_out : out std_logic_vector(0 to 3)
);
end component;
-----------------end component declaration------------------------------
-----------------signal declaration ------------------------------------
-- Constants for the message boxes. SW_HW: communication from SW to HW
-- HW_SW: communication from HW to SW
constant C_MBOX_HANDLE_SW_HW : std_logic_vector(0 to 31) := X"00000000";
constant C_MBOX_HANDLE_HW_SW : std_logic_vector(0 to 31) := X"00000001";
-- State machines
type os_state is ( STATE_INIT,
STATE_SEND_BUS_COUNTER,
STATE_SEND_ETH_COUNTER,
STATE_GET_COMMAND,
STATE_DECODE);
signal os_sync_state : os_state := STATE_INIT;
type s_state is ( S_STATE_INIT,
S_STATE_WAIT,
S_STATE_LOCK,
S_STATE_SEND_FIRST,
S_STATE_INTERM);
signal send_to_0_state : s_state;
signal send_to_0_state_next : s_state;
signal send_to_1_state : s_state;
signal send_to_1_state_next : s_state;
signal send_to_2_state : s_state;
signal send_to_2_state_next : s_state;
signal send_to_eth_state : s_state;
signal send_to_eth_state_next : s_state;
type r_state is ( R_STATE_INIT,
R_STATE_COUNT);
signal receive_state : r_state;
signal receive_state_next : r_state;
signal receive_eth_state : r_state;
signal receive_eth_state_next : r_state;
-- Ethernet Signals
-- Synchronous reset registers in the LocalLink clock domain
signal ll_pre_reset_i : std_logic_vector(5 downto 0);
signal ll_reset_i : std_logic;
attribute async_reg : string;
attribute async_reg of ll_pre_reset_i : signal is "true";
-- Reset signal from the transceiver
signal resetdone_i : std_logic;
signal resetdone_r : std_logic;
attribute async_reg of resetdone_r : signal is "true";
-- Transceiver output clock (REFCLKOUT at 125MHz)
signal clk125_o : std_logic;
-- 125MHz clock input to wrappers
signal clk125 : std_logic;
attribute keep : boolean;
attribute keep of clk125 : signal is true;
-- Input 125MHz differential clock for transceiver
signal clk_ds : std_logic;
-- Global asynchronous reset
signal reset_i : std_logic;
-- LocalLink interface clocking signal
signal ll_clk_i : std_logic;
-- Signals between sending process and ll tx fifo
signal tx_ll_data_i : std_logic_vector(31 downto 0);
signal tx_ll_sof_n_i : std_logic;
signal tx_ll_eof_n_i : std_logic;
signal tx_ll_src_rdy_n_i : std_logic;
signal tx_ll_dst_rdy_n_i : std_logic;
--Signals between ll_tx fifo and eth_ll_fifo
signal eth_tx_ll_data_i : std_logic_vector(7 downto 0);
signal eth_tx_ll_sof_n_i : std_logic;
signal eth_tx_ll_eof_n_i : std_logic;
signal eth_tx_ll_src_rdy_n_i : std_logic;
signal eth_tx_ll_dst_rdy_n_i : std_logic;
--Signals from eth ll fifo to rx_ll fifo
signal rx_ll_data_i : std_logic_vector(7 downto 0);
signal rx_ll_sof_n_i : std_logic;
signal rx_ll_eof_n_i : std_logic;
signal rx_ll_src_rdy_n_i : std_logic;
signal rx_ll_dst_rdy_n_i : std_logic;
--Signals from rx_ll fifo to process
signal rx_data : std_logic_vector(31 downto 0);
signal rx_sof_out_n : std_logic;
signal rx_eof_out_n : std_logic;
signal rx_src_rdy_out_n : std_logic;
signal rx_dst_rdy_in_n : std_logic;
signal rx_rem : std_logic_vector(1 downto 0);
-- bus signals (for communication between hw threats)
signal to_0_data : std_logic_vector(0 to 32 - 1);
signal to_1_data : std_logic_vector(0 to 32 - 1);
signal to_2_data : std_logic_vector(0 to 32 - 1);
signal to_0_sof : std_logic;
signal to_1_sof : std_logic;
signal to_2_sof : std_logic;
signal to_1_eof : std_logic;
signal to_2_eof : std_logic;
signal to_0_eof : std_logic;
signal received_counter : natural;
signal received_counter_next : natural;
signal received_eth_counter : natural;
signal received_eth_counter_next: natural;
signal start_to_0 : std_logic;
signal s_0_counter : natural;
signal s_0_counter_next : natural;
signal start_to_1 : std_logic;
signal s_1_counter : natural;
signal s_1_counter_next : natural;
signal start_to_2 : std_logic;
signal s_2_counter : natural;
signal s_2_counter_next : natural;
signal start_to_eth : std_logic;
signal s_eth_counter : natural;
signal s_eth_counter_next : natural;
--end signal declaration
begin
-- Ethernet setup
reset_i <= PRE_PHY_RESET;
PHY_RESET <= not reset_i;
-- Generate the clock input to the transceiver
-- (clk_ds can be shared between multiple EMAC instances, including
-- multiple instantiations of the EMAC wrappers)
clkingen : IBUFDS_GTXE1 port map (
I => MGTCLK_P,
IB => MGTCLK_N,
CEB => '0',
O => clk_ds,
ODIV2 => open
);
-- The 125MHz clock from the transceiver is routed through a BUFG and
-- input to the MAC wrappers
-- (clk125 can be shared between multiple EMAC instances, including
-- multiple instantiations of the EMAC wrappers)
bufg_clk125 : BUFG port map (
I => clk125_o,
O => clk125
);
-- Clock the LocalLink interface with the globally-buffered 125MHz
-- clock from the transceiver
ll_clk_i <= clk125;
-- Synchronize resetdone_i from the GT in the transmitter clock domain
gen_resetdone_r : process(ll_clk_i, reset_i)
begin
if (reset_i = '1') then
resetdone_r <= '0';
elsif ll_clk_i'event and ll_clk_i = '1' then
resetdone_r <= resetdone_i;
end if;
end process gen_resetdone_r;
-- Create synchronous reset in the transmitter clock domain
gen_ll_reset : process (ll_clk_i, reset_i)
begin
if reset_i = '1' then
ll_pre_reset_i <= (others => '1');
ll_reset_i <= '1';
elsif ll_clk_i'event and ll_clk_i = '1' then
if resetdone_r = '1' then
ll_pre_reset_i(0) <= '0';
ll_pre_reset_i(5 downto 1) <= ll_pre_reset_i(4 downto 0);
ll_reset_i <= ll_pre_reset_i(5);
end if;
end if;
end process gen_ll_reset;
-- End Ethernet setup
--Default assignements
-- we don't need the memories in this example
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
o_RAMAddr_x <= (others => '0');
o_RAMData_x <= (others => '0');
o_RAMWE_x <= '0';
o_RAMClk_x <= '0';
data_2 <= to_0_data & to_1_data & to_2_data;
ready_2 <= '0'; -- unused
-----------------start components------------------------------
v6_emac_v1_4_locallink_inst : v6_emac_v1_4_locallink port map (
-- 125MHz clock output from transceiver
CLK125_OUT => clk125_o,
-- 125MHz clock input from BUFG
CLK125 => clk125,
-- LocalLink receiver interface
RX_LL_CLOCK => ll_clk_i,
RX_LL_RESET => ll_reset_i,
RX_LL_DATA => rx_ll_data_i,
RX_LL_SOF_N => rx_ll_sof_n_i,
RX_LL_EOF_N => rx_ll_eof_n_i,
RX_LL_SRC_RDY_N => rx_ll_src_rdy_n_i,
RX_LL_DST_RDY_N => rx_ll_dst_rdy_n_i,
RX_LL_FIFO_STATUS => open,
-- Client receiver signals
EMACCLIENTRXDVLD => open, --EMACCLIENTRXDVLD,
EMACCLIENTRXFRAMEDROP => open, --EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS => open, --EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD => open, --EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD => open, --EMACCLIENTRXSTATSBYTEVLD,
-- LocalLink transmitter interface
TX_LL_CLOCK => ll_clk_i,
TX_LL_RESET => ll_reset_i,
TX_LL_DATA => eth_tx_ll_data_i,
TX_LL_SOF_N => eth_tx_ll_sof_n_i,
TX_LL_EOF_N => eth_tx_ll_eof_n_i,
TX_LL_SRC_RDY_N => eth_tx_ll_src_rdy_n_i,
TX_LL_DST_RDY_N => eth_tx_ll_dst_rdy_n_i,
-- Client transmitter signals
CLIENTEMACTXIFGDELAY => (others => '0'), --CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS => open, --EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD => open, --EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD => open, --EMACCLIENTTXSTATSBYTEVLD,
-- MAC control interface
CLIENTEMACPAUSEREQ => '0', --CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL => (others => '0'), --CLIENTEMACPAUSEVAL,
-- EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS => open, --EMACCLIENTSYNCACQSTATUS,
EMACANINTERRUPT => open, --EMACANINTERRUPT,
-- SGMII interface
TXP => TXP,
TXN => TXN,
RXP => RXP,
RXN => RXN,
PHYAD => (others => '0'), --PHYAD,
RESETDONE => resetdone_i,
-- SGMII transceiver reference clock buffer input
CLK_DS => clk_ds,
-- Asynchronous reset
RESET => reset_i
);
TX_FIFO : ll_fifo
port map (
areset_in => reset,
write_clock_in => clk,
read_clock_in => ll_clk_i,
-- Interface to downstream user application
data_out => eth_tx_ll_data_i,
rem_out => open,
sof_out_n => eth_tx_ll_sof_n_i,
eof_out_n => eth_tx_ll_eof_n_i,
src_rdy_out_n => eth_tx_ll_src_rdy_n_i,
dst_rdy_in_n => eth_tx_ll_dst_rdy_n_i,
-- Interface to upstream user application
data_in => tx_ll_data_i,
rem_in => (others => '0'),
sof_in_n => tx_ll_sof_n_i,
eof_in_n => tx_ll_eof_n_i,
src_rdy_in_n => tx_ll_src_rdy_n_i,
dst_rdy_out_n => tx_ll_dst_rdy_n_i,
-- FIFO status signals
fifostatus_out => open
);
RX_FIFO_1 : ll_fifo
generic map(
WR_DWIDTH => 8, -- FIFO write data width,
RD_DWIDTH => 32, -- FIFO read data width,
RD_REM_WIDTH => 2, -- Remainder width of read data
WR_REM_WIDTH => 1 -- Remainder width of write data
)
port map (
areset_in => reset,
write_clock_in => ll_clk_i,
read_clock_in => clk,
data_out => rx_data,
rem_out => rx_rem,
sof_out_n => rx_sof_out_n,
eof_out_n => rx_eof_out_n,
src_rdy_out_n => rx_src_rdy_out_n,
dst_rdy_in_n => rx_dst_rdy_in_n,
data_in => rx_ll_data_i,
rem_in => (others => '0'),
sof_in_n => rx_ll_sof_n_i,
eof_in_n => rx_ll_eof_n_i,
src_rdy_in_n => rx_ll_src_rdy_n_i,
dst_rdy_out_n => rx_ll_dst_rdy_n_i,
-- FIFO status signals
fifostatus_out => open
);
------------------------ State machines------------------------------------
-- Counts the number of packets received on the Bus interface
receiving : process(busdata_2, bussof_2, buseof_2, bus_src_rdy_2,
receive_state, received_counter)
begin
bus_dst_rdy_2 <= '1';
receive_state_next <= receive_state;
received_counter_next <= received_counter;
case receive_state is
when R_STATE_INIT =>
received_counter_next <= 0;
receive_state_next <= R_STATE_COUNT;
when R_STATE_COUNT =>
if bussof_2 = '1' then
received_counter_next <= received_counter + 1;
end if;
end case;
end process;
-- Counts the number of packets received on the Ethernet interface
receiving_eth : process(rx_data, rx_sof_out_n, rx_eof_out_n,
rx_src_rdy_out_n, receive_eth_state,
received_eth_counter)
begin
rx_dst_rdy_in_n <= '0';
receive_eth_state_next <= receive_eth_state;
received_eth_counter_next <= received_eth_counter;
case receive_state is
when R_STATE_INIT =>
received_eth_counter_next <= 0;
receive_eth_state_next <= R_STATE_COUNT;
when R_STATE_COUNT =>
if rx_src_rdy_out_n = '0' then
if rx_sof_out_n = '0' then
received_eth_counter_next <= received_eth_counter + 1;
end if;
end if;
end case;
end process;
-- Sends packets to the thread in slot 0 as long as the "start_to_eth" is high.
send_to_0 : process(start_to_0, send_to_0_state, s_0_counter, grant_2)
begin
src_rdy_2(0) <= '0';
to_0_data <= (others => '0');
sof_2(0) <= '0';
eof_2(0) <= '0';
req_2(0) <= '0';
send_to_0_state_next <= send_to_0_state;
s_0_counter_next <= s_0_counter;
case send_to_0_state is
when S_STATE_INIT =>
send_to_0_state_next <= S_STATE_WAIT;
s_0_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_0 = '1' then
send_to_0_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_2(0) <= '1';
if grant_2(0) = '0' then
send_to_0_state_next <= S_STATE_LOCK;
else
send_to_0_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_2(0) <= '1';
sof_2(0) <= '1';
to_0_data <= (others => '1');
s_0_counter_next <= s_0_counter + 1;
send_to_0_state_next <= S_STATE_INTERM;
req_2(0) <= '1';
when S_STATE_INTERM =>
req_2(0) <= '1';
src_rdy_2(0) <= '1';
to_0_data <= (others => '0');
if s_0_counter = 15 then
s_0_counter_next <= 0;
send_to_0_state_next <= S_STATE_WAIT;
eof_2(0) <= '1';
else
s_0_counter_next <= s_0_counter + 1;
end if;
end case;
end process;
-- Sends packets to the thread in slot 1 as long as the "start_to_eth" is high.
send_to_1 : process(start_to_1, send_to_1_state, s_1_counter, grant_2)
begin
src_rdy_2(1) <= '0';
to_1_data <= (others => '0');
sof_2(1) <= '0';
eof_2(1) <= '0';
req_2(1) <= '0';
send_to_1_state_next <= send_to_1_state;
s_1_counter_next <= s_1_counter;
case send_to_1_state is
when S_STATE_INIT =>
send_to_1_state_next <= S_STATE_WAIT;
s_1_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_1 = '1' then
send_to_1_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_2(1) <= '1';
if grant_2(1) = '0' then
send_to_1_state_next <= S_STATE_LOCK;
else
send_to_1_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_2(1) <= '1';
sof_2(1) <= '1';
to_1_data <= (others => '1');
s_1_counter_next <= s_1_counter + 1;
send_to_1_state_next <= S_STATE_INTERM;
req_2(1) <= '1';
when S_STATE_INTERM =>
req_2(1) <= '1';
src_rdy_2(1) <= '1';
to_1_data <= (others => '0');
if s_1_counter = 15 then
s_1_counter_next <= 0;
send_to_1_state_next <= S_STATE_WAIT;
eof_2(1) <= '1';
else
s_1_counter_next <= s_1_counter + 1;
end if;
end case;
end process;
-- Sends packets to the thread in slot 2 as long as the "start_to_eth" is high.
send_to_2 : process(start_to_2, send_to_2_state, s_2_counter, grant_2)
begin
src_rdy_2(2) <= '0';
to_2_data <= (others => '0');
sof_2(2) <= '0';
eof_2(2) <= '0';
req_2(2) <= '0';
send_to_2_state_next <= send_to_2_state;
s_2_counter_next <= s_2_counter;
case send_to_2_state is
when S_STATE_INIT =>
send_to_2_state_next <= S_STATE_WAIT;
s_2_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_2 = '1' then
send_to_2_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_2(2) <= '1';
if grant_2(2) = '0' then
send_to_2_state_next <= S_STATE_LOCK;
else
send_to_2_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_2(2) <= '1';
sof_2(2) <= '1';
to_2_data <= (others => '1');
s_2_counter_next <= s_2_counter + 1;
send_to_2_state_next <= S_STATE_INTERM;
req_2(2) <= '1';
when S_STATE_INTERM =>
req_2(2) <= '1';
src_rdy_2(2) <= '1';
to_2_data <= (others => '0');
if s_2_counter = 15 then
s_2_counter_next <= 0;
send_to_2_state_next <= S_STATE_WAIT;
eof_2(2) <= '1';
else
s_2_counter_next <= s_2_counter + 1;
end if;
end case;
end process;
-- Sends packets to the Ethernet Interface as long as the "start_to_eth" is high.
send_to_eth : process(start_to_eth, send_to_eth_state, s_eth_counter, tx_ll_dst_rdy_n_i)
begin
tx_ll_src_rdy_n_i <= '1';
tx_ll_data_i <= (others => '0');
tx_ll_sof_n_i <= '1';
tx_ll_eof_n_i <= '1';
send_to_eth_state_next <= send_to_eth_state;
s_eth_counter_next <= s_eth_counter;
case send_to_eth_state is
when S_STATE_INIT =>
send_to_eth_state_next <= S_STATE_WAIT;
s_eth_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_eth = '1' then
send_to_eth_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
tx_ll_src_rdy_n_i <= '0';
tx_ll_sof_n_i <= '0';
tx_ll_data_i <= (others => '1');
if tx_ll_dst_rdy_n_i = '0' then
s_eth_counter_next <= s_eth_counter + 1;
send_to_eth_state_next <= S_STATE_INTERM;
end if;
when S_STATE_INTERM =>
tx_ll_src_rdy_n_i <= '0';
tx_ll_data_i <= (others => '1');
if tx_ll_dst_rdy_n_i = '0' then
if s_eth_counter = 15 then
s_eth_counter_next <= 0;
send_to_eth_state_next <= S_STATE_WAIT;
tx_ll_eof_n_i <= '0';
else
s_eth_counter_next <= s_eth_counter + 1;
end if;
end if;
when others =>
send_to_eth_state_next <= S_STATE_INIT;
end case;
end process;
-- memzing process
-- updates all the registers
proces_mem : process(clk, reset)
begin
if reset = '1' then
send_to_0_state <= S_STATE_INIT;
s_0_counter <= 0;
send_to_1_state <= S_STATE_INIT;
s_1_counter <= 0;
send_to_2_state <= S_STATE_INIT;
s_2_counter <= 0;
send_to_eth_state <= S_STATE_INIT;
s_eth_counter <= 0;
receive_state <= R_STATE_INIT;
received_counter <= 0;
receive_eth_state <= R_STATE_INIT;
received_eth_counter <= 0;
elsif rising_edge(clk) then
send_to_0_state <= send_to_0_state_next;
s_0_counter <= s_0_counter_next;
send_to_1_state <= send_to_1_state_next;
s_1_counter <= s_1_counter_next;
send_to_2_state <= send_to_2_state_next;
s_2_counter <= s_2_counter_next;
send_to_eth_state <= send_to_eth_state_next;
s_eth_counter <= s_eth_counter_next;
receive_state <= receive_state_next;
received_counter <= received_counter_next;
receive_eth_state <= receive_eth_state_next;
received_eth_counter <= received_eth_counter_next;
end if;
end process;
-- OS synchronization state machine (the reconOS state machine)
-- this has to have this special format!
state_proc : process(clk, reset)
variable success : boolean;
variable done : boolean;
variable sw_command : std_logic_vector(0 to C_OSIF_DATA_WIDTH - 1);
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"ABCDEF01");
os_sync_state <= STATE_INIT;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case os_sync_state is
when STATE_INIT =>
os_sync_state <= STATE_GET_COMMAND;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
when STATE_SEND_BUS_COUNTER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_HANDLE_HW_SW,
std_logic_vector(to_unsigned(received_counter,C_OSIF_DATA_WIDTH)));
if done then
os_sync_state <= STATE_GET_COMMAND;
end if;
when STATE_SEND_ETH_COUNTER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_HANDLE_HW_SW,
std_logic_vector(to_unsigned(received_eth_counter,C_OSIF_DATA_WIDTH)));
if done then
os_sync_state <= STATE_GET_COMMAND;
end if;
when STATE_GET_COMMAND =>
reconos_mbox_get(done, success, o_osif, i_osif, C_MBOX_HANDLE_SW_HW, sw_command);
if done and success then
os_sync_state <= STATE_DECODE;
end if;
when STATE_DECODE =>
--default: command not known
os_sync_state <= STATE_GET_COMMAND;
-- element 0 indicates whether this thread should send to slot 0,
-- element 1 indicates whether this thread should send to slot 1,
-- element 6 indicates whether the receive counter from the bus interface
-- should be reported
-- element 7 indicates whether the receive counter from the eth interface
-- should be reported. Note, 6 and 7 can only be specified exclusivly. E.g.
-- only one counter value can be reported with one request.
if sw_command(6) = '1' then
os_sync_state <= STATE_SEND_BUS_COUNTER;
elsif sw_command(7) = '1' then
os_sync_state <= STATE_SEND_ETH_COUNTER;
else
if sw_command(0) = '1' then
start_to_0 <= '1';
else
start_to_0 <= '0';
end if;
if sw_command(1) = '1' then
start_to_1 <= '1';
else
start_to_1 <= '0';
end if;
if sw_command(2) = '1' then
start_to_2 <= '1';
else
start_to_2 <= '0';
end if;
if sw_command(3) = '1' then
start_to_eth <= '1';
else
start_to_eth <= '0';
end if;
end if;
when others =>
os_sync_state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
76e9b8d1b7a73afb6571bc1013435575
| 0.557859 | 2.978941 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/blk_mem_gen_v8_2/38e122e0/hdl/blk_mem_gen_v8_2.vhd
| 1 | 19,921 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
gpl-2.0
|
b6521857c70afc4618efe289083dcec3
| 0.940615 | 1.886637 | false | false | false | false |
luebbers/reconos
|
demos/shared_tlb_demo/hw_task_v1_01_b/hdl/vhdl/hwt.vhd
| 1 | 5,011 |
----------------------------------------------------------------------------------
-- Company:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hwt is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
constant C_MBOX_GET : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0) := X"00000000";
constant C_MBOX_PUT : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0) := X"00000001";
type t_state is (
STATE_GET_ITERATIONS,
STATE_GET_ADDR,
-- STATE_DEBUG,
-- STATE_DEBUG2,
-- STATE_DEBUG3,
STATE_READ,
STATE_COMPUTE_ADDR_1,
STATE_COMPUTE_ADDR_2,
STATE_SEND_RESULT,
STATE_END
);
signal state : t_state;
-- signal addr : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
-- signal iterations : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
-- signal counter : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
-- signal seed : std_logic_vector(15 downto 0);
-- signal input : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
-- signal base_page : std_logic_vector(19 downto 0);
-- signal offset : std_logic_vector(11 downto 0);
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
variable addr : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
variable iterations : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
variable counter : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
variable seed : std_logic_vector(15 downto 0);
variable input : std_logic_vector(C_OSIF_DATA_WIDTH-1 downto 0);
variable base_page : std_logic_vector(19 downto 0);
variable offset : std_logic_vector(11 downto 0);
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_GET_ITERATIONS;
addr := (others => '0');
iterations := (others => '0');
counter := (others => '0');
seed := (others => '0');
input := (others => '0');
base_page := (others => '0');
offset := (others => '0');
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_GET_ITERATIONS =>
reconos_mbox_get(done, success, o_osif, i_osif, C_MBOX_GET, iterations);
if done then state <= STATE_GET_ADDR; end if;
when STATE_GET_ADDR =>
reconos_mbox_get(done, success, o_osif, i_osif, C_MBOX_GET, addr);
if done and success then
base_page := addr(31 downto 12); -- 0x480028
offset := addr(11 downto 0); -- 0x000
state <= STATE_READ;
end if;
-- when STATE_DEBUG =>
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_PUT, addr); -- 0x48028000
-- if done and success then state <= STATE_READ; end if;
when STATE_READ =>
reconos_read(done, o_osif, i_osif, addr, input);
if done then
if counter = iterations then
state <= STATE_SEND_RESULT;
else
state <= STATE_COMPUTE_ADDR_1;
counter := counter + 1;
end if;
end if;
-- when STATE_DEBUG2 =>
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_PUT, addr); -- 0x48028000
-- if done and success then state <= STATE_COMPUTE_ADDR_1; end if;
when STATE_COMPUTE_ADDR_1 =>
-- LFSR p(x) = x^16 + x^14 + x^13 + x^11 + 1
seed := seed xor input(15 downto 0); -- 0
seed := ('0' & seed(15 downto 1)) xor (seed(0) & '0' & seed(0) & seed(0) & '0' & seed(0) & b"0000000000"); -- 0
state <= STATE_COMPUTE_ADDR_2;
-- when STATE_DEBUG3 =>
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_PUT, addr); -- 0x48028000
-- if done and success then state <= STATE_COMPUTE_ADDR_2; end if;
when STATE_COMPUTE_ADDR_2 =>
addr := (base_page + seed(5 downto 0)) & offset; -- 0x480028 000
state <= STATE_READ;
when STATE_SEND_RESULT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_PUT, X"5555" & seed);
if done then state <= STATE_END; end if;
when STATE_END =>
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
b99a555e151c47069b6368124298bdd7
| 0.614049 | 2.944183 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_v8_0_9/hdl/dist_mem_gen_v8_0.vhd
| 3 | 17,706 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect key_block
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`protect end_protected
|
mit
|
5f45a0f423723f69d2a5ebe7daccbcbd
| 0.936123 | 1.884018 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/ip/ddr/ddr/example_design/rtl/example_top.vhd
| 1 | 33,641 |
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 2.3
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic (
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC_TEST : string := "OFF";
RANKS : integer := 1;
-- # of Ranks.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
TCQ : integer := 100;
DRAM_TYPE : string := "DDR2";
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
nCK_PER_CLK : integer := 4;
-- # of memory CKs per fabric CLK
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "EXTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
-- The 12 MSB bits of the temperature sensor transfer
-- function need to be connected to this port. This port
-- will be synchronized w.r.t. to fabric clock internally.
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant DATA_WIDTH : integer := 16;
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
-- Start of User Design top component
component ddr
-- generic (
-- #parameters_user_design_top_component#
-- RST_ACT_LOW : integer
-- );
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
sys_rst : in std_logic
);
end component ddr;
-- End of User Design top component
component mig_7series_v2_3_traffic_gen_top
generic (
TCQ : integer;
SIMULATION : string;
FAMILY : string;
MEM_TYPE : string;
TST_MEM_INSTR_MODE : string;
--BL_WIDTH : integer;
nCK_PER_CLK : integer;
NUM_DQ_PINS : integer;
MEM_BURST_LEN : integer;
MEM_COL_WIDTH : integer;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
MASK_SIZE : integer := 8;
DATA_MODE : std_logic_vector(3 downto 0);
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
CMDS_GAP_DELAY : std_logic_vector(5 downto 0) := "000000";
SEL_VICTIM_LINE : integer := 8;
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
EYE_TEST : string;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string
);
port (
clk : in std_logic;
rst : in std_logic;
tg_only_rst : in std_logic;
manual_clear_error : in std_logic;
memc_init_done : in std_logic;
memc_cmd_full : in std_logic;
memc_cmd_en : out std_logic;
memc_cmd_instr : out std_logic_vector(2 downto 0);
memc_cmd_bl : out std_logic_vector(5 downto 0);
memc_cmd_addr : out std_logic_vector(31 downto 0);
memc_wr_en : out std_logic;
memc_wr_end : out std_logic;
memc_wr_mask : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
memc_wr_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
memc_wr_full : in std_logic;
memc_rd_en : out std_logic;
memc_rd_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
memc_rd_empty : in std_logic;
qdr_wr_cmd_o : out std_logic;
qdr_rd_cmd_o : out std_logic;
vio_pause_traffic : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(3 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_instr_mode_value : in std_logic_vector(3 downto 0);
vio_bl_mode_value : in std_logic_vector(1 downto 0);
vio_fixed_bl_value : in std_logic_vector(9 downto 0);
vio_fixed_instr_value : in std_logic_vector(2 downto 0);
vio_data_mask_gen : in std_logic;
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(31 downto 0);
simple_data0 : in std_logic_vector(31 downto 0);
simple_data1 : in std_logic_vector(31 downto 0);
simple_data2 : in std_logic_vector(31 downto 0);
simple_data3 : in std_logic_vector(31 downto 0);
simple_data4 : in std_logic_vector(31 downto 0);
simple_data5 : in std_logic_vector(31 downto 0);
simple_data6 : in std_logic_vector(31 downto 0);
simple_data7 : in std_logic_vector(31 downto 0);
wdt_en_i : in std_logic;
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
cmp_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
dq_error_bytelane_cmp : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
error : out std_logic;
error_status : out std_logic_vector((64+(2*DATA_WIDTH))-1 downto 0);
cumlative_dq_lane_error : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
cmd_wdt_err_o : out std_logic;
wr_wdt_err_o : out std_logic;
rd_wdt_err_o : out std_logic;
mem_pattern_init_done : out std_logic
);
end component mig_7series_v2_3_traffic_gen_top;
-- Signal declarations
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(APP_MASK_WIDTH-1 downto 0);
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal error_status : std_logic_vector((64 + (4*PAYLOAD_WIDTH*nCK_PER_CLK))-1 downto 0);
signal cumlative_dq_lane_error : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal mem_pattern_init_done : std_logic_vector(0 downto 0);
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_data : std_logic_vector((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0);
signal cmp_data_r : std_logic_vector(63 downto 0);
signal cmp_data_valid : std_logic;
signal cmp_data_valid_r : std_logic;
signal cmp_error : std_logic;
signal tg_wr_data_counts : std_logic_vector(47 downto 0);
signal tg_rd_data_counts : std_logic_vector(47 downto 0);
signal dq_error_bytelane_cmp : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic_vector(0 downto 0);
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic_vector(0 downto 0);
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic_vector(0 downto 0);
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_bl_value : std_logic_vector(BL_WIDTH-1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic_vector(0 downto 0);
signal dbg_clear_error : std_logic_vector(0 downto 0);
signal vio_tg_rst : std_logic_vector(0 downto 0);
signal dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal dbg_po_f_inc : std_logic_vector(0 downto 0);
signal dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal dbg_po_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_dec : std_logic_vector(0 downto 0);
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic_vector(0 downto 0);
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
begin
--***************************************************************************
init_calib_complete <= init_calib_complete_i;
tg_compare_error <= tg_compare_error_i;
app_rdy_i <= not(app_rdy);
app_wdf_rdy_i <= not(app_wdf_rdy);
app_rd_data_valid_i <= not(app_rd_data_valid);
app_addr <= app_addr_i(ADDR_WIDTH-1 downto 0);
-- Start of User Design top instance
--***************************************************************************
-- The User design is instantiated below. The memory interface ports are
-- connected to the top-level and the application interface ports are
-- connected to the traffic generator module. This provides a reference
-- for connecting the memory controller to system.
--***************************************************************************
u_ddr : ddr
-- generic map (
-- #parameters_mapping_user_design_top_instance#
-- RST_ACT_LOW => RST_ACT_LOW
-- )
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
device_temp_i => device_temp_i,
sys_rst => sys_rst
);
-- End of User Design top instance
--***************************************************************************
-- The traffic generation module instantiated below drives traffic (patterns)
-- on the application interface of the memory controller
--***************************************************************************
tg_rst <= vio_tg_rst(0) or po_win_tg_rst;
u_traffic_gen_top : mig_7series_v2_3_traffic_gen_top
generic map (
TCQ => TCQ,
SIMULATION => SIMULATION,
FAMILY => "VIRTEX7",
MEM_TYPE => DRAM_TYPE,
TST_MEM_INSTR_MODE => TST_MEM_INSTR_MODE,
nCK_PER_CLK => nCK_PER_CLK,
NUM_DQ_PINS => PAYLOAD_WIDTH,
MEM_BURST_LEN => BURST_LENGTH,
MEM_COL_WIDTH => COL_WIDTH,
PORT_MODE => PORT_MODE,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => TG_ADDR_WIDTH,
DATA_WIDTH => APP_DATA_WIDTH,
BEGIN_ADDRESS => BEGIN_ADDRESS,
DATA_MODE => DATA_MODE,
END_ADDRESS => END_ADDRESS,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
CMD_WDT => CMD_WDT,
RD_WDT => RD_WDT,
WR_WDT => WR_WDT,
EYE_TEST => EYE_TEST
)
port map (
clk => clk,
rst => rst,
tg_only_rst => tg_rst,
manual_clear_error => manual_clear_error(0),
memc_init_done => init_calib_complete_i,
memc_cmd_full => app_rdy_i,
memc_cmd_en => app_en,
memc_cmd_instr => app_cmd,
memc_cmd_bl => open,
memc_cmd_addr => app_addr_i,
memc_wr_en => app_wdf_wren,
memc_wr_end => app_wdf_end,
memc_wr_mask => app_wdf_mask(((PAYLOAD_WIDTH*2*nCK_PER_CLK)/8)-1 downto 0),
memc_wr_data => app_wdf_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_wr_full => app_wdf_rdy_i,
memc_rd_en => open,
memc_rd_data => app_rd_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_rd_empty => app_rd_data_valid_i,
qdr_wr_cmd_o => open,
qdr_rd_cmd_o => open,
vio_pause_traffic => vio_pause_traffic(0),
vio_modify_enable => vio_modify_enable(0),
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_instr_mode_value => vio_instr_mode_value,
vio_bl_mode_value => vio_bl_mode_value,
vio_fixed_bl_value => vio_fixed_bl_value,
vio_fixed_instr_value=> vio_fixed_instr_value,
vio_data_mask_gen => vio_data_mask_gen(0),
fixed_addr_i => all_zeros1,
fixed_data_i => all_zeros1,
simple_data0 => all_zeros1,
simple_data1 => all_zeros1,
simple_data2 => all_zeros1,
simple_data3 => all_zeros1,
simple_data4 => all_zeros1,
simple_data5 => all_zeros1,
simple_data6 => all_zeros1,
simple_data7 => all_zeros1,
wdt_en_i => wdt_en_w(0),
bram_cmd_i => all_zeros2,
bram_valid_i => '0',
bram_rdy_o => open,
cmp_data => cmp_data,
cmp_data_valid => cmp_data_valid,
cmp_error => cmp_error,
wr_data_counts => tg_wr_data_counts,
rd_data_counts => tg_rd_data_counts,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
error => tg_compare_error_i,
error_status => error_status,
cumlative_dq_lane_error => cumlative_dq_lane_error,
cmd_wdt_err_o => cmd_wdt_err_w,
wr_wdt_err_o => wr_wdt_err_w,
rd_wdt_err_o => rd_wdt_err_w,
mem_pattern_init_done => mem_pattern_init_done(0)
);
--*****************************************************************
-- Default values are assigned to the debug inputs of the traffic
-- generator
--*****************************************************************
vio_modify_enable(0) <= '0';
vio_data_mode_value <= "0010";
vio_addr_mode_value <= "011";
vio_instr_mode_value <= "0010";
vio_bl_mode_value <= "10";
vio_fixed_bl_value <= "0000010000";
vio_data_mask_gen(0) <= '0';
vio_pause_traffic(0) <= '0';
vio_fixed_instr_value <= "001";
dbg_clear_error(0) <= '0';
po_win_tg_rst <= '0';
vio_tg_rst(0) <= '0';
wdt_en_w(0) <= '1';
dbg_sel_pi_incdec(0) <= '0';
dbg_sel_po_incdec(0) <= '0';
dbg_pi_f_inc(0) <= '0';
dbg_pi_f_dec(0) <= '0';
dbg_po_f_inc(0) <= '0';
dbg_po_f_dec(0) <= '0';
dbg_po_f_stg23_sel(0) <= '0';
end architecture arch_example_top;
|
gpl-3.0
|
d228897350fff81ca658d143fc0d2de7
| 0.461817 | 4.08116 | false | false | false | false |
BenBoZ/realtimestagram
|
src/lomo.vhd
| 2 | 8,509 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
--! <!------------------------------------------------------------------------------>
--! <!------------------------------------------------------------------------------>
--! \class vignette
--! \brief Creates a faded vignette around the image
--!
--! \image html vignette.png
--!
--! \dot
--! digraph vignette{
--!
--! graph [rankdir=LR, splines=ortho, sep=5];
--! edge [penwidth=2.2, arrowsize=.5]
--! node [height=0.25, style=filled, fontname=sans]
--!
--! /* single or multibit registers */
--!
--!
--! subgraph inputs {
--! node [fontcolor=white, fontname=serif, fillcolor=gray32, shape=box, tailport=e]
--! rank=same; clk rst enable hcount vcount pixel_i
--! }
--!
--! subgraph cluster_component {
--!
--! color=gray64
--! label="vignette";
--! fontcolor=black;
--! fontname=sans;
--!
--! subgraph operators{
--! node [ shape=circle, fillcolor=white, fontcolor=black, labelloc=c, fixedsize=true, tailport=e]
--! and0 [label="&"]
--!
--! mult0 [label="x"]
--! mult1 [label="x"]
--! }
--!
--! subgraph registers{
--! node [fontcolor=white, fontname=serif, fillcolor=gray32, shape=box, headport=w]
--! pixel_i_reg0 [label="p0"]
--! pixel_i_reg1 [label="p1"]
--! }
--!
--! subgraph function_blocks{
--! node [ height=1, shape=box, fillcolor=gray96, fontcolor=black, headport=w, tailport=e]
--! lut_x [label="lut x"]
--! lut_y [label="lut y"]
--! }
--! }
--!
--! subgraph output{
--! node [fontcolor=white, fontname=serif, fillcolor=gray32, shape=box, headport=w]
--! rank=same; pixel_o
--! }
--!
--! clk -> and0
--! enable -> and0
--! rst -> and0 [arrowhead=odot, arrowsize=0.6]
--!
--! and0 -> lut_x
--! hcount -> lut_x -> mult0
--!
--! and0 -> lut_y
--! vcount -> lut_y -> mult0
--!
--! pixel_i -> pixel_i_reg0 -> pixel_i_reg1 -> mult1
--! mult0 -> mult1 -> pixel_o
--! }
--! \enddot
--!
--! <!------------------------------------------------------------------------------>
--! <!------------------------------------------------------------------------------>
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Used for calculation of h_count and v_cunt port width
use ieee.math_real.all;
use work.curves_pkg.all;
--============================================================================--
--!
--!
--!
--!
entity lomo is
generic (
wordsize: integer; --! input image wordsize in bits
image_width: integer; --! width of input image
image_height: integer --! height of input image
);
port (
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
--! x-coordinate of input pixel
h_count: in std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0);
--! y-coordinate of input pixel
v_count: in std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0);
pixel_red_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_i: in std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_red_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_green_o: out std_logic_vector((wordsize-1) downto 0); --! the input pixel
pixel_blue_o: out std_logic_vector((wordsize-1) downto 0) --! the input pixel
);
end entity;
--============================================================================--
architecture behavioural of lomo is
-- signal declarations
signal lut_value_x: std_logic_vector((wordsize-1) downto 0); --! Value from LUT_x
signal lut_value_y: std_logic_vector((wordsize-1) downto 0); --! Value from LUT_y
signal lut_value_r_s: std_logic_vector((wordsize-1) downto 0); --! Value from LUT_y
signal lut_value_g_s: std_logic_vector((wordsize-1) downto 0); --! Value from LUT_y
signal lut_value_b_s: std_logic_vector((wordsize-1) downto 0); --! Value from LUT_y
signal lut_x_lut_y: natural range 0 to 2**(2*wordsize); --! LUT_x * LUT_y
signal p_r: natural range 0 to 2**(wordsize); --! buffered pix_in
signal p_g: natural range 0 to 2**(wordsize); --! buffered pix_in
signal p_b: natural range 0 to 2**(wordsize); --! buffered pix_in
constant lut_r: array_pixel := create_sigmoid_lut(2**wordsize, 5.0);
constant lut_g: array_pixel := create_sigmoid_lut(2**wordsize, 7.0);
constant lut_b: array_pixel := create_sigmoid_lut(2**wordsize, 2.0);
constant lut_x: array_pixel := create_sine_lut(image_width, 0.3);
constant lut_y: array_pixel := create_sine_lut(image_height, 0.3);
begin
--! \brief clocked process that outputs LUT-value on each rising edge if enable is true
--! \param[in] clk clock
--! \param[in] rst asynchronous reset
rgb_curve : process(clk, rst)
variable pixel_o_r_slv : std_logic_vector(3*wordsize-1 downto 0) := (others => '0');
variable pixel_o_g_slv : std_logic_vector(3*wordsize-1 downto 0) := (others => '0');
variable pixel_o_b_slv : std_logic_vector(3*wordsize-1 downto 0) := (others => '0');
begin
if rst = '1' then
lut_value_x <= (others => '0');
lut_value_y <= (others => '0');
lut_x_lut_y <= 0;
p_r <= 0;
p_g <= 0;
p_b <= 0;
lut_value_r_s <= (others => '0');
lut_value_g_s <= (others => '0');
lut_value_b_s <= (others => '0');
elsif rising_edge(clk) then
if enable = '1' then
-- Vignette calculation
lut_value_x <= lut_x(to_integer(unsigned(h_count)));
lut_value_y <= lut_y(to_integer(unsigned(v_count)));
lut_x_lut_y <= to_integer(unsigned(lut_value_x)) * to_integer(unsigned(lut_value_y));
-- Color channel adaption
lut_value_r_s <= lut_r(to_integer(unsigned(pixel_red_i)));
lut_value_g_s <= lut_g(to_integer(unsigned(pixel_green_i)));
lut_value_b_s <= lut_b(to_integer(unsigned(pixel_blue_i)));
p_r <= to_integer(unsigned(lut_value_r_s));
p_g <= to_integer(unsigned(lut_value_g_s));
p_b <= to_integer(unsigned(lut_value_b_s));
-- Apply vignette
pixel_o_r_slv := std_logic_vector(to_unsigned(lut_x_lut_y * p_r, 3*wordsize));
pixel_o_g_slv := std_logic_vector(to_unsigned(lut_x_lut_y * p_g, 3*wordsize));
pixel_o_b_slv := std_logic_vector(to_unsigned(lut_x_lut_y * p_b, 3*wordsize));
pixel_red_o <= pixel_o_r_slv(3*wordsize-1 downto 2*wordsize);
pixel_green_o <= pixel_o_g_slv(3*wordsize-1 downto 2*wordsize);
pixel_blue_o <= pixel_o_b_slv(3*wordsize-1 downto 2*wordsize);
else
pixel_red_o <= (others => '0');
pixel_green_o <= (others => '0');
pixel_blue_o <= (others => '0');
end if; -- end if enable = '1'
end if; -- end if rst = '1'
end process;
end architecture;
--============================================================================--
|
gpl-2.0
|
e877d831db57e602c7b41e9c7305f1bd
| 0.516982 | 3.593328 | false | false | false | false |
oetr/FPGA-I2C-Slave
|
debounce.vhd
| 1 | 2,024 |
------------------------------------------------------------
-- File : debounce.vhd
------------------------------------------------------------
-- Author : Peter Samarin <[email protected]>
------------------------------------------------------------
-- Copyright (c) 2019 Peter Samarin
------------------------------------------------------------
-- Description: debouncing circuit that forwards only
-- signals that have been stable for the whole duration of
-- the counter
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------
entity debounce is
generic (
WAIT_CYCLES : integer := 5);
port (
signal_in : in std_logic;
signal_out : out std_logic;
clk : in std_logic);
end entity debounce;
------------------------------------------------------------
architecture arch of debounce is
type state_t is (idle, check_input_stable);
signal state_reg : state_t := idle;
signal out_reg : std_logic := signal_in;
signal signal_in_reg : std_logic;
signal counter : integer range 0 to WAIT_CYCLES-1 := 0;
begin
process (clk) is
begin
if rising_edge(clk) then
case state_reg is
when idle =>
if out_reg /= signal_in then
signal_in_reg <= signal_in;
state_reg <= check_input_stable;
counter <= WAIT_CYCLES-1;
end if;
when check_input_stable =>
if counter = 0 then
if signal_in = signal_in_reg then
out_reg <= signal_in;
end if;
state_reg <= idle;
else
if signal_in /= signal_in_reg then
state_reg <= idle;
end if;
counter <= counter - 1;
end if;
end case;
end if;
end process;
-- output
signal_out <= out_reg;
end architecture arch;
|
mit
|
da77c5ec5f0ead761ade38c2a87d442a
| 0.439229 | 4.762353 | false | false | false | false |
luebbers/reconos
|
demos/sort_demo_thermal/hw/src/bubble_sorter.vhd
| 3 | 6,023 |
--
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
416c58dfe36b0df320c65ea5f4089e78
| 0.497759 | 3.890827 | false | false | false | false |
williammacdowell/gcm
|
src/fpga/key_expansion_ea.vhd
| 1 | 5,176 |
-------------------------------------------------------------------------------
-- Title : Key Expansion
-- Project : AES-GCM
-------------------------------------------------------------------------------
-- File : key_expansion_ea.vhd
-- Author : Bill MacDowell <bill@bill-macdowell-laptop>
-- Company :
-- Created : 2017-03-21
-- Last update: 2017-04-10
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This block expands a 256-bit AES key into a full key schedule
-- for each round. An input to this block specified the round, and 1 clock
-- later, the round key is provided as an output. The key schedule is stored in
-- a small memory, which is refreshed anytime the go bit goes high.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-03-20 1.0 bill Created
-------------------------------------------------------------------------------
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gcm_pkg.all;
entity key_expansion is
port(
clk : in std_logic;
rst : in std_logic;
key_in : in std_logic_vector(255 downto 0);
round : in std_logic_vector(3 downto 0);
en_key_gen : in std_logic;
key_out : out std_logic_vector(128 downto 0));
end entity key_expansion;
architecture rtl of key_expansion is
component s_box is
port (
clk : in std_logic;
rst : in std_logic;
byte_in : in std_logic_vector(7 downto 0);
byte_out : out std_logic_vector(7 downto 0));
end component s_box;
type t_key_expansion_state is (
idle,
working,
rot_and_sub_wrd,
sub_wrd,
simple_xor
);
signal state : t_key_expansion_state;
type t_keystore is array (63 downto 0) of std_logic_vector(31 downto 0);
signal keystore : t_keystore;
signal i : unsigned(7 downto 0);
signal last_i : unsigned(7 downto 0);
signal i_minus_8 : unsigned(7 downto 0);
signal rot_word_out : std_logic_vector(31 downto 0);
signal sub_word_out : std_logic_vector(31 downto 0);
signal round_const : std_logic_vector(31 downto 0);
signal sub_word_in : std_logic_vector(31 downto 0);
begin
GEN_SBOXES_WORD : for byte_idx in 0 to 3 generate
s_box_0 : s_box
port map (
clk => clk,
rst => rst,
byte_in => sub_word_in(8*byte_idx+7 downto 8*byte_idx),
byte_out => sub_word_out(8*byte_idx+7 downto 8*byte_idx));
end generate GEN_SBOXES_WORD;
key_expansion_proc : process (clk) is
begin
if clk'event and clk = '1' then
case state is
when idle =>
if en_key_gen = '1' then
-- First 7 words are just the key
for word_idx in 7 downto 0 loop
keystore(word_idx) <= key_in(32*word_idx+31 downto 32*word_idx);
end loop;
i <= x"08";
round_const <= x"01000000";
state <= working;
end if;
when working =>
i <= i + 1;
if i = 60 then
state <= idle;
elsif i(2 downto 0) = "000" then
state <= rot_and_sub_wrd;
elsif i(1 downto 0) = "00" then
state <= sub_wrd;
else
state <= simple_xor;
end if;
when rot_and_sub_wrd =>
keystore(to_integer(i)) <= sub_word_out xor round_const xor keystore(to_integer(i_minus_8));
round_const <= round_const(31 downto 1) & "0";
state <= working;
when sub_wrd =>
keystore(to_integer(i)) <= sub_word_out xor keystore(to_integer(i_minus_8));
state <= working;
when simple_xor =>
keystore(to_integer(i)) <= keystore(to_integer(last_i)) xor keystore(to_integer(i_minus_8));
state <= working;
when others => null;
end case;
if rst = '1' then
state <= idle;
keystore <= (others => (others => '0'));
i <= (others => '0');
round_const <= (others => '0');
end if;
end if;
end process;
comb_proc : process (i) is
begin
last_i <= i - 1;
i_minus_8 <= i - 8;
if last_i < 64 then
rot_word_out(31 downto 24) <= keystore(to_integer(last_i))(23 downto 16);
rot_word_out(23 downto 16) <= keystore(to_integer(last_i))(15 downto 8);
rot_word_out(15 downto 8) <= keystore(to_integer(last_i))(7 downto 0);
rot_word_out(7 downto 0) <= keystore(to_integer(last_i))(31 downto 24);
else
rot_word_out <= (others => '0');
end if;
-- TODO
if i(2 downto 0) = "000" then
sub_word_in <= rot_word_out;
elsif i(1 downto 0) = "00" then
sub_word_in <= keystore(to_integer(i));
end if;
end process;
end rtl;
|
gpl-3.0
|
5481954cdda00585a98760ee678c6af0
| 0.500193 | 3.710394 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/ADXL362Ctrl.vhd
| 1 | 44,750 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 16:48:39 02/20/2014
-- Design Name:
-- Module Name: ADXL362Ctrl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the controller for the Nexys4 onboard ADXL362 Accelerometer device.
-- The module uses the SPI Interface component to communicate with the ADXL362.
-- At initialization time, the module resets the ADXL362, then configures its internal registers.
-- After configuring its internal registers, the acceleration will be read on the three axes followed
-- by the temperature data: A set of 8 data bytes are read: XDATA_L, XDATA_H, YDATA_L, YDATA_H, ZDATA_L,
-- ZDATA_H, TEMP_L and TEMP_H, see the ADXL362 datasheet for details.
-- Reading is done continuously and an average is made from a number of reads. The number of reads
-- for which average is made should be a power of two and is determined by the NUM_READS_AVG parameter,
-- by default 16. The UPDATE_FREQUENCY_HZ parameter sets a counter to a period of 1/UPDATE_FREQUENCY_HZ.
-- The state machine will wait for this period of time before starting a number of NUM_READS_AVG times
-- data read procedure.
-- Before reading a set of data, the state machine reads and checks the status register to see when
-- new data is available at the ADXL362. Therefore the real sample time depends on the ADXL362 sample
-- frequency, set in the Filter Control Register, address 0x2C, in this project set by default to 200Hz.
--
-- The module consists of three state machines, named by the signals holding the states:
-- - SPI Send/Receive Control State Machine: StC_Spi_SendRec. This state machine creates a handshake transaction
-- with the SPI Interface component, using the Start and Done signals to:
-- - Send the number of bytes specified by the Cnt_Bytes_Sent counter (3 when configuring an ADXL362 internal
-- register, 2 when sending a Read Command). The bytes to be sent through the SPI interface are taken from the
-- command register, Cmd_Reg.
-- - Receive the number of bytes specified by the Cnt_Bytes_Rec counter (8 when reading acceleration and
-- temperature data, 1 when reading the status register), when reading is required (SPI_RnW = 1).
-- The acceleration and temperature data is stored in the data register, Data_Reg
--
-- - SPI Transaction State machine, StC_Spi_Trans. This state machine controls the previously described SPI
-- Send/Receive Control State Machine, using handshake with the the StartSpiSendRec (write) and SPI_SendRec_Done (read)
-- signals:
-- - Prepares and loads the command register, Cmd_Reg with the appropiate command string (configure a specific
-- register, read data or read status)
-- - Loads Cnt_Bytes_Sent and Cnt_Bytes_Rec with the number of bytes to be sent and/or received
-- - Activates StartSpiSendRec to start the SPI Send/Receive Control State Machine and wait for its answer
-- by reading the SPI_SendRec_Done signal
--
-- Note that between each SPI transaction (Register write or Register read) the SS signal has to be deactivated
-- for at least 10nS before a new command is issued
--
-- - ADXL 362 Control State Machine, StC_Adxl_Ctrl. This state machine controls the previously described SPI
-- Transaction State machine, also by using handshake with the StartSpiTr (write) and SPI_Trans_Done (read) signals:
-- 1. First, Cmd_Reg will be loaded with the reset command from the Cmd_Reg_Data ROM and the state machine starts
-- the SPI Transaction State Machine to send the reset command to the ADXL362 accelerometer
-- 2. The state machine waits for a period of time and then sends the remaining configuration register data from
-- Cmd_Reg_Data to the ADXL362 accelerometer
-- 3. After configuring ADXL362, the state machine waits for a period of time equal to 1/UPDATE_FREQUENCY_HZ
-- before starts reading
-- 4. After the period of time elapsed the state machine reads the status register and, when there is new data available, reads the
-- reads the X, Y and Z acceleration data, followed by temperature data.
-- A number of reads equal to NUM_READS_AVG is performed, i.e. Step 4 is repeated NUM_READS_AVG times.
-- 5. The data read is averaged in the ACCEL_X_SUM, ACCEL_Y_SUM, ACCEL_Z_SUM and ACCEL_TMP_SUM registers. The
-- NUM_READS_AVG is power of 2 in order to make averaging easier by removing the least significant bits. After
-- a number of reads equal to NUM_READS_AVG is done, the state machine updates the output data, ACCEL_X, ACCEL_Y,
-- ACCEL_Z and ACCEL_TMP, stored in 12-bit two's complement format and signals to the output by activating for one
-- clock period the Data_Ready signal.
-- After that the state machine proceeds to Step 3, in an infinite loop. The state machine restarts from Step 1 only
-- when the FPGA is reconfigured or the Reset signal is activated.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_signed.all;
use IEEE.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADXL362Ctrl is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
SCLK_FREQUENCY_HZ : integer := 1000000;
NUM_READS_AVG : integer := 16;
UPDATE_FREQUENCY_HZ : integer := 1000
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Accelerometer data signals
ACCEL_X : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Y : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Z : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_TMP : out STD_LOGIC_VECTOR (11 downto 0);
Data_Ready : out STD_LOGIC;
--SPI Interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC
);
end ADXL362Ctrl;
architecture Behavioral of ADXL362Ctrl is
-- SPI Interface component declaration
component SPI_If is
generic
(
SYSCLK_FREQUENCY_HZ : integer:= 100000000;
SCLK_FREQUENCY_HZ : integer:= 1000000
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
Din : in STD_LOGIC_VECTOR (7 downto 0); -- Data to be transmitted
Dout : out STD_LOGIC_VECTOR (7 downto 0); -- Data received;
Start : in STD_LOGIC; -- used to start the transmission
Done : out STD_LOGIC; -- Signaling that transmission ended
HOLD_SS : in STD_LOGIC; -- Signal that forces SS low in the case of multiple byte
-- transmit/receive mode
--SPI Interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC
);
end component;
--**************************************
-- Constant Definitions
--**************************************
-- To create the update frequency counter
constant UPDATE_DIV_RATE : integer := (SYSCLK_FREQUENCY_HZ / UPDATE_FREQUENCY_HZ);
constant SYS_CLK_PERIOD_PS : integer := ((1000000000 / SYSCLK_FREQUENCY_HZ) * 1000);
--ADXL 362 Read and Write Command
constant READ_CMD : STD_LOGIC_VECTOR (7 downto 0) := X"0B";
constant WRITE_CMD : STD_LOGIC_VECTOR (7 downto 0) := X"0A";
-- Data read will be always performed starting from Address X"0E",
-- representing XACC_H. A total number of 8 bytes will be read.
constant READ_STARTING_ADDR : STD_LOGIC_VECTOR (7 downto 0):= X"0E";
-- Status Register Read will be used to check when new data is available (Bit 0 is 1)
constant STATUS_REG_ADDR : STD_LOGIC_VECTOR (7 downto 0):= X"0B";
-- Number of bytes to write when configuring registers
constant NUMBYTES_CMD_CONFIG_REG : integer := 3;
-- Number of bytes to write when reading registers
constant NUMBYTES_CMD_READ : integer := 2;
-- Number of bytes to read when reading data from ADXL362
constant NUMBYTES_READ_DATA : integer := 8;
-- Number of bytes to read when reading status register from ADXL362
constant NUMBYTES_READ_STATUS : integer := 1;
-- number of command vectors to send, one command vector
-- represents ADXL362 register address followed by command byte,
-- i.e. one command vector will mean two bytes
constant NUM_COMMAND_VEC : integer := 4;
-- Number of reads to be performed for which average is calculated, default is 16
constant NUM_READS : natural := NUM_READS_AVG;
-- Number of extra bits when creating the average of the reads
constant NUM_READS_BITS : natural := natural(ceil(log(real(NUM_READS), 2.0)));
-- after each SPI transaction, SS needs to be inactive for at least 10ns before a new command is issued
constant SS_INACTIVE_PERIOD_NS : integer := 10000;
constant SS_INACTIVE_CLOCKS : integer := (SS_INACTIVE_PERIOD_NS/(SYS_CLK_PERIOD_PS/1000));
-- To specify encoding of the state machines
attribute FSM_ENCODING : string;
--SPI Interface Control Signals
signal Start : STD_LOGIC; -- Signal controlling the SPI interface, controlled by the SPI Send/Receive State Machine
signal Done : STD_LOGIC; -- Signaling that transmission ended, coming from the SPI interface
signal HOLD_SS : STD_LOGIC; -- Signal that forces SS low in the case of multiple byte
-- transmit/receive mode, controlled by the SPI Transaction State Machine
-- Create the initialization vector, i.e.
-- the register data to be written to initialize ADXL362
type rom_type is array (0 to ((2* NUM_COMMAND_VEC)-1)) of STD_LOGIC_VECTOR (7 downto 0);
constant Cmd_Reg_Data : rom_type := ( X"1F", X"52", -- Soft Reset Register Address and Reset Command
X"1F", X"00", -- Soft Reset Register Address, clear Command
X"2D", X"02", -- Power Control Register, Enable Measure Command
X"2C", X"14" -- Filter Control Register, 2g range, 1/4 Bandwidth, 200HZ Output Data Rate
);
--address the reg_data ROM
signal Cmd_Reg_Data_Addr: integer range 0 to (NUM_COMMAND_VEC - 1) := 0;
-- Enable Incrementing Cmd_Reg_Data_Addr, controlled by the ADXL Control State machine
signal EN_Advance_Cmd_Reg_Addr: STD_LOGIC := '0';
-- will enable incrementing by 2 Cmd_Reg_Data_Addr
signal Advance_Cmd_Reg_Addr: STD_LOGIC := '0';
-- signal that shows that all of the addresses were read
signal Cmd_Reg_Addr_Done : STD_LOGIC := '0';
-- SPI Transfer Send Data signals. Writing Commands will be always a 3-byte transfer,
-- therefore commands will be temporarry stored in a 3X8 shift register.
type command_reg_type is array (0 to 2) of STD_LOGIC_VECTOR (7 downto 0);
signal Cmd_Reg: command_reg_type := (X"00", X"00", WRITE_CMD);
-- command_reg control signals
signal Load_Cmd_Reg : STD_LOGIC := '0'; -- Controlled by the SPI Transaction State Machine,
-- the command register is load with the appropiate command
signal Shift_Cmd_Reg : STD_LOGIC := '0'; -- Controlled by the SPI Send/Receive State Machine,
-- advance to the next command when a byte was sent
-- to count the bytes to be sent
-- Cnt_Bytes_Sent will decrement at the same time when
-- cmd_reg is shifted, therefore its control signal is the same as
-- for Cmd_Reg: EN_Shift_Cmd_Reg
signal Cnt_Bytes_Sent : integer range 0 to 3 :=0;
-- Load Cnt_Bytes_Sent with the number of bytes to be sent
-- according to the command to be sent
signal Load_Cnt_Bytes_Sent : STD_LOGIC := '0'; -- controlled by the SPI Transaction State Machine
signal Reset_Cnt_Bytes : STD_LOGIC := '0'; -- Controlled by the Main State Machine
-- will reset both the sent and received byte counter
-- SPI Transfer Receive Data signals. Reading data will be a 8-byte transfer:
-- XACC_H, XACC_L, YACC_H, YACC_L, ZACC_H, ZACC_L, TEMP_H, TEMP_L
-- therefore an 8X8 shift register is created.
type data_reg_type is array (0 to (NUMBYTES_READ_DATA - 1)) of STD_LOGIC_VECTOR (7 downto 0);
signal Data_Reg: data_reg_type := (others => X"00");
-- data_reg control signals:
signal EN_Shift_Data_Reg : STD_LOGIC := '0'; -- Controlled by the SPI Send/Receive State Machine
-- Shift when a new byte was received
-- Data Reg will be shifted when a new byte comes, i.e. Shift_Data_Reg <= EN_Shift_Data_Reg AND Done;
signal Shift_Data_Reg : STD_LOGIC := '0';
-- to count the bytes to be received
-- Cnt_Bytes_Rec will decrement at the same time when Data_Reg is shifted,
-- therefore its control signal is the same as for Data_Reg: Shift_Data_Reg
signal Cnt_Bytes_Rec : integer range 0 to NUMBYTES_READ_DATA - 1 := 0;
-- Load Cnt_Bytes_Rec with the number of bytes to be received, controlled by the SPI Transaction State Machine
signal Load_Cnt_Bytes_Rec : STD_LOGIC := '0';
-- SPI Data to Send and Data Received registers
-- Data to send register will be loaded together with shifting
-- a new byte in Cmd_Reg, i.e. its control signal is Shift_Cmd_Reg
-- Data Received Register will be read when shifting Data_Reg
signal D_Send : STD_LOGIC_VECTOR (7 downto 0) := X"00";
signal D_Rec : STD_LOGIC_VECTOR (7 downto 0) := X"00";
-- SPI Send/Receive State Machine internal condition signals
signal StartSpiSendRec : STD_LOGIC := '0'; -- Start SPI transfer, controlled by the SPI Transaction State Machine
signal SPI_RnW : STD_LOGIC := '0'; -- Write 3 bytes or write 2 bytes followed by read 1 byte or 8 bytes
signal SPI_WR_Done : STD_LOGIC := '0'; -- Active when the write transfer is done, i.e. 2 or 3 bytes were written
signal SPI_RD_Done : STD_LOGIC := '0'; -- Active when the read transfer is done, i.e. 8 bytes were read
-- SPI Send/Receive State Machine status signals, used by the SPI Transaction State Machine
signal SPI_SendRec_Done : STD_LOGIC := '0';
-- Define Control Signals, Status signals and States for the SPI Send/Receive State Machine
-- From MSB: 6:Shift_Cmd_Reg, 5:EN_Shift_Data_Reg, 4:SPI_SendRec_Done, 3:Start, 2:STC(2), 1:STC(1), 0:STC(0)
-- bit 6543210
constant stSpiSendRecIdle : STD_LOGIC_VECTOR (6 downto 0) := "0000000"; -- Idle state, wait for StartSpiSendRec
constant stSpiPrepareCmd : STD_LOGIC_VECTOR (6 downto 0) := "1000001"; -- Load D_Send with the next byte and shift the command register
constant stSpiSendStartW : STD_LOGIC_VECTOR (6 downto 0) := "0001011"; -- Send the Start command to the SPI interface
constant stSpiWaitOnDoneW : STD_LOGIC_VECTOR (6 downto 0) := "0000111"; -- Wait until Done comes
constant stSpiSendStartR : STD_LOGIC_VECTOR (6 downto 0) := "0001110"; -- Send Start command again to the SPI interface if read was requested
constant stSpiWaitOnDoneR : STD_LOGIC_VECTOR (6 downto 0) := "0100100"; -- Wait until Done comes
constant stSpiSendRecDone : STD_LOGIC_VECTOR (6 downto 0) := "0010101"; -- Done state, return to Idle
--State Machine Signal Definitions
signal StC_Spi_SendRec, StN_Spi_SendRec : STD_LOGIC_VECTOR (6 downto 0) := stSpiSendRecIdle;
--Force User Encoding for the State Machine
attribute FSM_ENCODING of StC_Spi_SendRec: signal is "USER";
-- Self-blocking counter for SS_INACTIVE_CLOCKS periods while SS is inactive
signal Cnt_SS_Inactive : integer range 0 to (SS_INACTIVE_CLOCKS -1) := 0;
-- controlled by the SPI Transaction State Machine
signal Reset_Cnt_SS_Inactive : STD_LOGIC := '0';
-- Signaling that SS_INACTIVE_PERIOD passed
signal Cnt_SS_Inactive_done : STD_LOGIC := '0';
-- Signaling that SPI Transaction is done
signal SPI_Trans_Done : STD_LOGIC := '0';
-- SPI Transaction State Machine internal Condition Signals, controlled
-- by the ADXL 362 Control State Machine
signal StartSpiTr : STD_LOGIC := '0'; -- Start SPI transaction
-- Define Control Signals, Status signals and States for the SPI Transaction State Machine
-- From MSB: 9:Load_Cmd_Reg, 8:Load_Cnt_Bytes_Sent, 7:Load_Cnt_Bytes_Rec, 6:StartSpiSendRec,
-- 5:HOLD_SS, 4:Reset_Cnt_SS_Inactive, 3:SPI_Trans_Done, 2:STC(2), 1:STC(1), 0:STC(0)
-- bit 9876543210
constant stSpiTransIdle : STD_LOGIC_VECTOR (9 downto 0) := "0000000000"; -- Idle state, wait for StartSpiTr
constant stSpiPrepAndSendCmd : STD_LOGIC_VECTOR (9 downto 0) := "1111100001"; -- Load Cmd_Reg with the command string and activate StartSpiSendRec
constant stSpiWaitonDoneSR : STD_LOGIC_VECTOR (9 downto 0) := "0000110011"; -- Wait until SPI_SendRec_Done becomes active
constant stSpiWaitForSsInact : STD_LOGIC_VECTOR (9 downto 0) := "0000000010"; -- Wait for SS_INACTIVE_PERIOD
constant stSpiTransDone : STD_LOGIC_VECTOR (9 downto 0) := "0000001110"; -- Done state, return to Idle
--State Machine Signal Definitions
signal StC_Spi_Trans, StN_Spi_Trans : STD_LOGIC_VECTOR (9 downto 0) := stSpiTransIdle;
--Force User Encoding for the State Machine
attribute FSM_ENCODING of StC_Spi_Trans: signal is "USER";
-- Data from the ADXL 362 will be sampled at a period defined by UPDATE_DIV_RATE
-- Divider used to generate the Sample_Rate_Tick, used also for timing
signal Sample_Rate_Div : integer range 0 to (UPDATE_DIV_RATE - 1) := 0;
signal Reset_Sample_Rate_Div : STD_LOGIC := '0';
signal Sample_Rate_Tick : STD_LOGIC := '0';
-- A number of 16 reads will be performed from the ADXL 362,
-- and their average will be sent as data
signal Cnt_Num_Reads : integer range 0 to (NUM_READS - 1) := 0;
signal CE_Cnt_Num_Reads : STD_LOGIC := '0'; -- enable counting, controlled by the ADXL 362 Control State Machine
signal Reset_Cnt_Num_Reads : STD_LOGIC := '0';
--Signaling that a number of 16 reads were done
signal Cnt_Num_Reads_Done : STD_LOGIC := '0';
-- Summing of incoming data will be stored in these signals
-- These will be used as accumulators, on two's complement
signal ACCEL_X_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
signal ACCEL_Y_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
signal ACCEL_Z_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
signal ACCEL_TMP_SUM : STD_LOGIC_VECTOR ((11 + (NUM_READS_BITS)) downto 0) := (others => '0');
-- Enables Summing the incomming data
signal Enable_Sum : STD_LOGIC := '0';
-- Pipe Data_Ready to have stable data at the output when activates
signal Data_Ready_1 : STD_LOGIC := '0';
-- ADXL 362 Control State Machine - The Main State Machine Internal Condition Signal
signal Adxl_Data_Ready : STD_LOGIC := '0'; -- showing that data is ready, read from the ADXL 362 Status Register
signal Adxl_Conf_Err : STD_LOGIC := '0'; -- showing that a configuration error ocurred, read from the ADXL 362 Status Register
-- Define Control Signals, Status signals and States for the ADXL 362 Control State Machine
-- From MSB: 11:Reset_Cnt_Bytes, 10:EN_Advance_Cmd_Reg_Addr, 9:StartSpiTr, 8:Reset_Cnt_Num_Reads,
-- 7:CE_Cnt_Num_Reads, 6:Reset_Sample_Rate_Div, 5:Enable_Sum, 4:Data_Ready_1, 3:STC(3), 2:STC(2), 1:STC(1), 0:STC(0)
-- 11
-- bit 109876543210
constant stAdxlCtrlIdle : STD_LOGIC_VECTOR (11 downto 0) := "100100000000"; -- Idle state, wait for 10 clock periods before start
constant stAdxlSendResetCmd : STD_LOGIC_VECTOR (11 downto 0) := "011001000001"; -- Send the Reset Command for ADXL
constant stAdxlWaitResetDone : STD_LOGIC_VECTOR (11 downto 0) := "010000000011"; -- Wait for some time until ADXL initializes.
-- The sample rate divider is used for timing
constant stAdxlConf_Remaining : STD_LOGIC_VECTOR (11 downto 0) := "011001000010"; -- Clear the Reset Register,
-- then configure the remaining registers
constant stAdxlWaitSampleRateTick : STD_LOGIC_VECTOR (11 downto 0) := "000100000110"; -- wait until the sample time passes
constant stAdxlRead_Status : STD_LOGIC_VECTOR (11 downto 0) := "011001000111"; -- Read the status register from ADXL 362
constant stAdxlRead_Data : STD_LOGIC_VECTOR (11 downto 0) := "011000000101"; -- Read the data from ADXL 362
constant stAdxlFormatandSum : STD_LOGIC_VECTOR (11 downto 0) := "000010101101"; -- Store and sum the received data
-- If 16 reads were done, go to the Done state
constant stAdxlRead_Done : STD_LOGIC_VECTOR (11 downto 0) := "000001011111"; -- Done state, return to stAdxlWaitSampleRateTick
--State Machine Signal Definitions
signal StC_Adxl_Ctrl, StN_Adxl_Ctrl : STD_LOGIC_VECTOR (11 downto 0) := stAdxlCtrlIdle;
--Force User Encoding for the State Machine
attribute FSM_ENCODING of StC_Adxl_Ctrl: signal is "USER";
begin
--Instantiate the SPI interface first
SPI_Interface: SPI_If
generic map
(
SYSCLK_FREQUENCY_HZ => SYSCLK_FREQUENCY_HZ,
SCLK_FREQUENCY_HZ => SCLK_FREQUENCY_HZ
)
port map
(
SYSCLK => SYSCLK,
RESET => RESET,
Din => D_Send,
Dout => D_Rec,
Start => Start,
Done => Done,
HOLD_SS => HOLD_SS,
--SPI Interface Signals
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
SS => SS
);
-- Assign the control and status signals of the SPI Send/Receive State Machine
Shift_Cmd_Reg <= StC_Spi_SendRec(6); -- Shift Cmd_Reg when New data is loading into D_Send
EN_Shift_Data_Reg <= StC_Spi_SendRec(5); -- Enable shifting the data register from D_Rec, shifting is performed when a new byte comes, i.e Done becomes active
SPI_SendRec_Done <= StC_Spi_SendRec(4); -- Transfer of the number of bytes is done
Start <= StC_Spi_SendRec(3); -- Send the Start command to the SPI interface
--in the stSpiSendStartW (writing) or stSpiSendStartR (Reading) states
-- Load D_Send with the new data to be transmitted
Load_D_Send: process (SYSCLK, RESET, Cmd_Reg, Shift_Cmd_Reg)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
D_Send <= X"00";
elsif Shift_Cmd_Reg = '1' then
D_Send <= Cmd_Reg (2);
end if;
end if;
end process Load_D_Send;
-- Assign the control and status signals of the SPI Transaction State Machine
Load_Cmd_Reg <= StC_Spi_Trans(9); -- Load the Command Register when preparing the command to be sent to ADXL
Load_Cnt_Bytes_Sent <= StC_Spi_Trans(8); -- Also load the counter of bytes to be sent
Load_Cnt_Bytes_Rec <= StC_Spi_Trans(7); -- And, in the case of reception, the counter of bytes to be received
StartSpiSendRec <= StC_Spi_Trans(6); -- Also send the start command to the SPI Send/Receive State Machine
-- Note that the signals above are active at the same time, i.e identical. They will be optimized by the synthesizer
HOLD_SS <= StC_Spi_Trans(5); -- Each SPI send/receive will be multiple byte transfer, so activate HOLD_SS
Reset_Cnt_SS_Inactive <= StC_Spi_Trans(4); -- Keep the Cnt_SS_Inactive counter reset, until the transfer is done
-- in the next state the state machine will raise SS for a period of SS_INACTIVE_PERIOD_NS
SPI_Trans_Done <= StC_Spi_Trans(3); -- Signals that the SPI transfer is done
-- Assign the control and status signals of the ADXL 362 Control State Machine
Reset_Cnt_Bytes <= StC_Adxl_Ctrl(11); -- Reset the counters for bytes to send and receive. These counters are reset
-- at initializing, then reloaded at each new transaction
EN_Advance_Cmd_Reg_Addr <= StC_Adxl_Ctrl(10); -- Advance the address of the command vectors, to load a new command
StartSpiTr <= StC_Adxl_Ctrl(9); -- Send the Start command to the SPI Transaction State Machine
Reset_Cnt_Num_Reads <= StC_Adxl_Ctrl(8); -- Reset the counter, once at initialization time, then before starting data read,
-- i.e in the stAdxlRead_Status state
CE_Cnt_Num_Reads <= StC_Adxl_Ctrl(7); -- Increment Cnt_Num_Reads after a new set of data come i.e. in the stAdxlFormatandSum state
Reset_Sample_Rate_Div <= StC_Adxl_Ctrl(6); -- Reset the Sample_Rate_Div counter before entering in the sample period wait state
-- i.e. in the stAdxlConf_Remaining and the stAdxlRead_Done
Enable_Sum <= StC_Adxl_Ctrl(5); -- After new data set come, enable summing
Data_Ready_1 <= StC_Adxl_Ctrl(4); -- To signal external components that new data set is available, coming from 16 reads
-- Load and shift Cmd_Reg according to the active commands
Load_Shift_Cmd_Reg: process (SYSCLK, Cmd_Reg, Cmd_Reg_Data_Addr, StC_Adxl_Ctrl, Load_Cmd_Reg, Shift_Cmd_Reg)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Load_Cmd_Reg = '1' then -- Load with data
if (StC_Adxl_Ctrl = stAdxlSendResetCmd)
or (StC_Adxl_Ctrl = stAdxlConf_Remaining) then -- In this case load with command vectors
Cmd_Reg(2) <= WRITE_CMD;
Cmd_Reg(1) <= Cmd_Reg_Data (2 * Cmd_Reg_Data_Addr);
Cmd_Reg(0) <= Cmd_Reg_Data ((2 * Cmd_Reg_Data_Addr) + 1);
elsif (StC_Adxl_Ctrl = stAdxlRead_Status) then
Cmd_Reg(2) <= READ_CMD;
Cmd_Reg(1) <= STATUS_REG_ADDR;
Cmd_Reg(0) <= X"00";
elsif (StC_Adxl_Ctrl = stAdxlRead_Data) then -- In this case load with command vectors
Cmd_Reg(2) <= READ_CMD;
Cmd_Reg(1) <= READ_STARTING_ADDR;
Cmd_Reg(0) <= X"00";
end if;
elsif Shift_Cmd_Reg = '1' then -- shift to load D_send with the new command byte
Cmd_Reg(2) <= Cmd_Reg(1);
Cmd_Reg(1) <= Cmd_Reg(0);
Cmd_Reg(0) <= X"00";
end if;
end if;
end process Load_Shift_Cmd_Reg;
-- Create the address counter for the Cmd_Reg_Data command vectors
-- Increment by two the Cmd_Reg_Data_Addr after a SPI Register Write transaction is done
Advance_Cmd_Reg_Addr <= EN_Advance_Cmd_Reg_Addr AND SPI_Trans_Done;
Count_Addr: process (SYSCLK, RESET, Cmd_Reg_Data_Addr, StC_Adxl_Ctrl, Advance_Cmd_Reg_Addr)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' or StC_Adxl_Ctrl = stAdxlCtrlIdle then
Cmd_Reg_Data_Addr <= 0;
elsif Advance_Cmd_Reg_Addr = '1' then
if Cmd_Reg_Data_Addr = (NUM_COMMAND_VEC - 1) then -- Avoid to address Cmd_Reg_Data out of range
Cmd_Reg_Data_Addr <= 0;
else
Cmd_Reg_Data_Addr <= Cmd_Reg_Data_Addr + 1;
end if;
end if;
end if;
end process Count_Addr;
-- Signal when all of the addresses were read
Cmd_Reg_Addr_Done <= '1' when Cmd_Reg_Data_Addr = (NUM_COMMAND_VEC - 1) else '0';
-- Shift Data_Reg when a new byte comes
Shift_Data_Reg <= EN_Shift_Data_Reg AND Done;
-- Read incoming data
Read_Data: process (SYSCLK, Shift_Data_Reg, D_Rec, Data_Reg) -- When reading the status register, one byte is read, therefore
variable i: integer range 0 to 6 := 0; -- the status register data will be on Data_Reg(0)
begin -- When reading incoming data, exactly 8 reads are performed,
if SYSCLK'EVENT AND SYSCLK = '1' then -- therefore no initialization is required for Data_Reg
if Shift_Data_Reg = '1' then
for i in 0 to 6 loop
Data_Reg(i+1) <= Data_Reg(i);
end loop;
Data_Reg(0) <= D_Rec;
end if;
end if;
end process Read_Data;
-- Count the bytes to be send and to be received
Count_Bytes_Send: process (SYSCLK, Reset_Cnt_Bytes, Load_Cnt_Bytes_Sent, Shift_Cmd_Reg, Cnt_Bytes_Sent)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Cnt_Bytes = '1' then
Cnt_Bytes_Sent <= 0;
elsif Load_Cnt_Bytes_Sent = '1' then
if (StC_Adxl_Ctrl = stAdxlSendResetCmd)
or (StC_Adxl_Ctrl = stAdxlConf_Remaining) then -- In this case send 3 command bytes
-- Decrementing and shifting Cmd_Reg will be done BEFORE sending data
-- through the serial interface, therefore load NUMBYTES_CMD_CONFIG_REG or NUMBYTES_CMD_READ.
-- The condition to end SPI send operation is Cnt_Bytes_Sent = 0 AND Done = '1'
Cnt_Bytes_Sent <= NUMBYTES_CMD_CONFIG_REG;
elsif (StC_Adxl_Ctrl = stAdxlRead_Status)
or (StC_Adxl_Ctrl = stAdxlRead_Data) then -- In the case of read command, send 2 command bytes
Cnt_Bytes_Sent <= NUMBYTES_CMD_READ;
else
Cnt_Bytes_Sent <= 0;
end if;
elsif Shift_Cmd_Reg = '1' then -- When shifting Cmd_Reg, decrement the counter
if Cnt_Bytes_Sent = 0 then
Cnt_Bytes_Sent <= 0; -- Stay at 0, reload at the next SPI transaction
else
Cnt_Bytes_Sent <= Cnt_Bytes_Sent - 1;
end if;
end if;
end if;
end process Count_Bytes_Send;
Count_Bytes_Rec: process (SYSCLK, Reset_Cnt_Bytes, Load_Cnt_Bytes_Rec, Shift_Data_Reg, Cnt_Bytes_Rec)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Cnt_Bytes = '1' then
Cnt_Bytes_Rec <= 0;
elsif Load_Cnt_Bytes_Rec = '1' then
if (StC_Adxl_Ctrl = stAdxlRead_Status) then -- In this case we have to read 1 byte
-- Decrementing and shifting Data_Reg will be done AFTER sending data
-- through the serial interface, therefore load NUMBYTES_READ_STATUS - 1 or NUMBYTES_READ_DATA - 1.
-- The condition to end SPI receive operation is Cnt_Bytes_Rec = 0 AND Done = '1'
Cnt_Bytes_Rec <= NUMBYTES_READ_STATUS - 1;
elsif (StC_Adxl_Ctrl = stAdxlRead_Data) then -- In the case we have to read 8 bytes
Cnt_Bytes_Rec <= NUMBYTES_READ_DATA -1;
else
Cnt_Bytes_Rec <= 0;
end if;
elsif Shift_Data_Reg = '1' then -- When shifting Data_Reg, decrement the counter
if Cnt_Bytes_Rec = 0 then
Cnt_Bytes_Rec <= 0; -- Stay at 0, reload at the next SPI transaction
else
Cnt_Bytes_Rec <= Cnt_Bytes_Rec - 1;
end if;
end if;
end if;
end process Count_Bytes_Rec;
-- Create the Sample_Rate_Div counter and the Sample_Rate_Tick signal
Count_Sample_Rate_Div: process (SYSCLK, Reset_Sample_Rate_Div, Sample_Rate_Div)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Sample_Rate_Div = '1' then
Sample_Rate_Div <= 0;
elsif Sample_Rate_Div = (UPDATE_DIV_RATE - 1) then
Sample_Rate_Div <= 0;
else
Sample_Rate_Div <= Sample_Rate_Div + 1;
end if;
end if;
end process Count_Sample_Rate_Div;
Sample_Rate_Tick <= '1' when Sample_Rate_Div = (UPDATE_DIV_RATE - 1) else '0';
-- Create the Cnt_Num_Reads counter, self-blocking
Count_Num_Reads: process (SYSCLK, Reset_Cnt_Num_Reads, CE_Cnt_Num_Reads, Cnt_Num_Reads)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if Reset_Cnt_Num_Reads = '1' then
Cnt_Num_Reads <= 0;
elsif CE_Cnt_Num_Reads = '1' then
if Cnt_Num_Reads = (NUM_READS - 1) then
Cnt_Num_Reads <= (NUM_READS - 1);
else
Cnt_Num_Reads <= Cnt_Num_Reads + 1;
end if;
end if;
end if;
end process Count_Num_Reads;
Cnt_Num_Reads_Done <= '1' when Cnt_Num_Reads = (NUM_READS - 1) else '0';
-- Create the Cnt_SS_Inactive counter, also self_blocking
Count_SS_Inactive: process (SYSCLK, RESET, Reset_Cnt_SS_Inactive, Cnt_SS_Inactive)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' or Reset_Cnt_SS_Inactive = '1' then
Cnt_SS_Inactive <= 0;
elsif Cnt_SS_Inactive = (SS_INACTIVE_CLOCKS - 1) then
Cnt_SS_Inactive <= (SS_INACTIVE_CLOCKS - 1);
else
Cnt_SS_Inactive <= Cnt_SS_Inactive + 1;
end if;
end if;
end process Count_SS_Inactive;
Cnt_SS_Inactive_done <= '1' when Cnt_SS_Inactive = (SS_INACTIVE_CLOCKS - 1) else '0';
-- SPI Send/Receive State Machine internal condition signals
-- SPI_RnW will be controlled according to the states of the Adxl 362 Control state machine
Set_SPI_RnW: process (SYSCLK, StC_Adxl_Ctrl)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if (StC_Adxl_Ctrl = stAdxlRead_Status)
or (StC_Adxl_Ctrl = stAdxlRead_Data) then
SPI_RnW <= '1';
else
SPI_RnW <= '0';
end if;
end if;
end process Set_SPI_RnW;
-- SPI Send/Receive State machine internal condition signals
SPI_WR_Done <= '1' when Cnt_Bytes_Sent = 0 AND Done = '1' else '0';
SPI_RD_Done <= '1' when Cnt_Bytes_Rec = 0 AND Done = '1' else '0';
-- Spi Send/Receive State Machine register process
Register_StC_Spi_SendRec: process (SYSCLK, RESET, StN_Spi_SendRec)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
StC_Spi_SendRec <= stSpiSendRecIdle;
else
StC_Spi_SendRec <= StN_Spi_SendRec;
end if;
end if;
end process Register_StC_Spi_SendRec;
-- Spi Send/Receive State Machine transitions process
Cmb_StC_Spi_SendRec: process (StC_Spi_SendRec, StartSpiSendRec, StartSpiSendRec,
SPI_WR_Done, SPI_RD_Done, SPI_RnW, Done)
begin
StN_Spi_SendRec <= StC_Spi_SendRec; -- Default: Stay in the current state
case (StC_Spi_SendRec) is
when stSpiSendRecIdle => if (StartSpiSendRec = '1') then StN_Spi_SendRec <= stSpiPrepareCmd; end if;
when stSpiPrepareCmd => StN_Spi_SendRec <= stSpiSendStartW;
when stSpiSendStartW => StN_Spi_SendRec <= stSpiWaitOnDoneW;
when stSpiWaitOnDoneW => if (SPI_RnW = '1') then -- in the case of a read command proceed to reading data, if writing is done
if (SPI_WR_Done = '1') then StN_Spi_SendRec <= stSpiSendStartR;
elsif (Done = '1') then StN_Spi_SendRec <= stSpiPrepareCmd; -- Return to send the next command byte
end if;
else
if (SPI_WR_Done = '1') then StN_Spi_SendRec <= stSpiSendRecDone; -- Sending command bytes finished
elsif (Done = '1') then StN_Spi_SendRec <= stSpiPrepareCmd; -- Return to send the next command byte
end if;
end if;
when stSpiSendStartR => StN_Spi_SendRec <= stSpiWaitOnDoneR; --Send Start command to the SPI interface and wait until reads a byte
when stSpiWaitOnDoneR => if (SPI_RD_Done = '1') then StN_Spi_SendRec <= stSpiSendRecDone; -- If all of the bytes were read
elsif (Done = '1') then StN_Spi_SendRec <= stSpiSendStartR; -- Return and send another Start command to read
end if; -- the next byte
when stSpiSendRecDone => StN_Spi_SendRec <= stSpiSendRecIdle;
when others => StN_Spi_SendRec <= stSpiSendRecIdle;
end case;
end process Cmb_StC_Spi_SendRec;
-- SPI Transaction State Machine register process
Register_StC_Spi_Trans: process (SYSCLK, RESET, StN_Spi_Trans)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
StC_Spi_Trans <= stSpiTransIdle;
else
StC_Spi_Trans <= StN_Spi_Trans;
end if;
end if;
end process Register_StC_Spi_Trans;
-- SPI Transaction State Machine transitions process
Cmb_StC_Spi_Trans: process (StC_Spi_Trans, StartSpiTr, Cnt_SS_Inactive_done, SPI_SendRec_Done)
begin
StN_Spi_Trans <= StC_Spi_Trans; -- Default: Stay in the current state
case (StC_Spi_Trans) is
when stSpiTransIdle => if (StartSpiTr = '1') then StN_Spi_Trans <= stSpiPrepAndSendCmd; end if; -- Start SPI Transaction
when stSpiPrepAndSendCmd => StN_Spi_Trans <= stSpiWaitonDoneSR; -- Load Cmd_Reg, the Cnt_Bytes_Sent and Cnt_Bytes_Rec counters and send
-- the Start command to the Spi Send/Receive state machine
when stSpiWaitonDoneSR => if (SPI_SendRec_Done = '1') then StN_Spi_Trans <= stSpiWaitForSsInact; end if; -- SPI Send/Receive done,
-- Discativate SS for SS_INACTIVE_CLOCKS
when stSpiWaitForSsInact => if (Cnt_SS_Inactive_done = '1') then StN_Spi_Trans <= stSpiTransDone; end if; -- SS_INACTIVE_CLOCKS passed, go to
-- the Done state
when stSpiTransDone => StN_Spi_Trans <= stSpiTransIdle;
when others => StN_Spi_Trans <= stSpiTransIdle;
end case;
end process Cmb_StC_Spi_Trans;
-- The Status Register read will be on Data_Reg(0), bit 0 shows if new data is ready
-- Adxl_Data_Ready and Adxl_Conf_Err will be tested in the ADXL 362 Control State Machine, in the stAdxlRead_Status state
Adxl_Data_Ready <= Data_Reg(0)(0);
Adxl_Conf_Err <= Data_Reg(0)(7);
-- ADXL 362 Control State Machine register process
Register_StC_Adxl_Ctrl: process (SYSCLK, RESET, StN_Adxl_Ctrl)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
StC_Adxl_Ctrl <= stAdxlCtrlIdle;
else
StC_Adxl_Ctrl <= StN_Adxl_Ctrl;
end if;
end if;
end process Register_StC_Adxl_Ctrl;
-- ADXL 362 Control State Machine Transitions process
Cmb_StC_Adxl_Ctrl: process (StC_Adxl_Ctrl, Cnt_SS_Inactive_done, SPI_Trans_Done, Sample_Rate_Tick,
Cmd_Reg_Addr_Done, Adxl_Data_Ready, Adxl_Conf_Err, Cnt_Num_Reads_Done)
begin
StN_Adxl_Ctrl <= StC_Adxl_Ctrl; -- Default: Stay in the current state
case (StC_Adxl_Ctrl) is
when stAdxlCtrlIdle => if (Sample_Rate_Tick = '1') then StN_Adxl_Ctrl <= stAdxlSendResetCmd; end if; -- wait for some clock periods
-- before start
when stAdxlSendResetCmd => if (SPI_Trans_Done = '1') then StN_Adxl_Ctrl <= stAdxlWaitResetDone; end if; -- Send the Reset command to the ADXL 362
when stAdxlWaitResetDone => if (Sample_Rate_Tick = '1') then StN_Adxl_Ctrl <= stAdxlConf_Remaining; end if; -- wait for about 1mS for the
-- ADXL 362 to initialize
when stAdxlConf_Remaining => if ( Cmd_Reg_Addr_Done = '1' AND SPI_Trans_Done = '1') then -- all of the configuration register data were written
StN_Adxl_Ctrl <= stAdxlWaitSampleRateTick; -- into the ADXL 362
end if;
when stAdxlWaitSampleRateTick => if (Sample_Rate_Tick = '1') then StN_Adxl_Ctrl <= stAdxlRead_Status; end if; -- Read and check the
--status register
when stAdxlRead_Status => if SPI_Trans_Done = '1' then
if Adxl_Conf_Err = '1' then StN_Adxl_Ctrl <= stAdxlCtrlIdle; -- if error ocurred in configuration, go to the ilde state
-- and send reset command again
elsif Adxl_Data_Ready = '1' then StN_Adxl_Ctrl <= stAdxlRead_Data; -- If data is available, start data read
end if;
end if;
when stAdxlRead_Data => if (SPI_Trans_Done = '1') then StN_Adxl_Ctrl <= stAdxlFormatandSum; end if; -- If a set of data is read,
-- add it to the accumulators
when stAdxlFormatandSum => if (Cnt_Num_Reads_Done = '1') then
StN_Adxl_Ctrl <= stAdxlRead_Done; -- done 16 reads, go to the Done state
else
StN_Adxl_Ctrl <= stAdxlRead_Status; -- Proceed to the next read
end if;
when stAdxlRead_Done => StN_Adxl_Ctrl <= stAdxlWaitSampleRateTick; -- Wait for the next Sample_Rate_Tick, in an infinite loop
when others => StN_Adxl_Ctrl <= stAdxlCtrlIdle;
end case;
end process Cmb_StC_Adxl_Ctrl;
-- Create the accumulators
-- Data_Reg is shifted from 0 to 7, it means that after reading a set of data, Data_Reg will contain
-- Data_Reg(7) = XDATA_L,
-- Data_Reg(6) = XDATA_H,
-- Data_Reg(5) = YDATA_L,
-- Data_Reg(4) = YDATA_H,
-- Data_Reg(3) = ZDATA_L,
-- Data_Reg(2) = ZDATA_H,
-- Data_Reg(1) = TEMP_L,
-- Data_Reg(0) = TEMP_H
Sum_Data: process (SYSCLK, RESET, Data_Ready_1, Enable_Sum, Data_Reg,
ACCEL_X_SUM, ACCEL_Y_SUM, ACCEL_Z_SUM, ACCEL_TMP_SUM)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if (RESET = '1' OR Data_Ready_1 = '1') then
ACCEL_X_SUM <= (others => '0');
ACCEL_Y_SUM <= (others => '0');
ACCEL_Z_SUM <= (others => '0');
ACCEL_TMP_SUM <= (others => '0');
elsif Enable_Sum = '1' then
ACCEL_X_SUM <= ACCEL_X_SUM + (Data_Reg(6)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(7));
ACCEL_Y_SUM <= ACCEL_Y_SUM + (Data_Reg(4)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(5));
ACCEL_Z_SUM <= ACCEL_Z_SUM + (Data_Reg(2)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(3));
ACCEL_TMP_SUM <= ACCEL_TMP_SUM + (Data_Reg(0)((3 + (NUM_READS_BITS)) downto 0) & Data_Reg(1));
end if;
end if;
end process Sum_Data;
-- Register the output data
Register_Output_Data: process (SYSCLK, RESET, Data_Ready_1, ACCEL_X_SUM,
ACCEL_Y_SUM, ACCEL_Z_SUM, ACCEL_TMP_SUM)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
ACCEL_X <= (others => '0');
ACCEL_Y <= (others => '0');
ACCEL_Z <= (others => '0');
ACCEL_TMP <= (others => '0');
elsif Data_Ready_1 = '1' then -- Divide by NUM_READS to create the average and set the output data
ACCEL_X <= ACCEL_X_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS)); -- 12 bits
ACCEL_Y <= ACCEL_Y_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS));
ACCEL_Z <= ACCEL_Z_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS));
ACCEL_TMP <= ACCEL_TMP_SUM ((11 + (NUM_READS_BITS)) downto (NUM_READS_BITS));
end if;
end if;
end process Register_Output_Data;
-- Pipe Data_Ready from Data_Ready_1
-- to have stable output data when Data_Ready becomes active
Pipe_Data_Ready: process (SYSCLK, RESET, Data_Ready_1)
begin
if SYSCLK'EVENT AND SYSCLK = '1' then
if RESET = '1' then
Data_Ready <= '0';
else
Data_Ready <= Data_Ready_1;
end if;
end if;
end process Pipe_Data_Ready;
end Behavioral;
|
gpl-3.0
|
ea325961752a93fda9909923cfe6474c
| 0.620022 | 3.917192 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/sram_array.vhd
| 3 | 4,145 |
library ieee;
use ieee.std_logic_1164.all;
ENTITY sram_array IS
GENERIC(addr_width, data_width : positive);
PORT(
CS, WE : IN std_logic;
SELECT_ALL : IN std_logic; -- causes all cells to be selected (for 0 write)
ADDR : IN std_logic_vector(addr_width-1 DOWNTO 0);
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
DATA_OUT : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
CONSTANT row_addr_width : positive := addr_width / 2 + addr_width rem 2;
CONSTANT col_addr_width : natural := addr_width / 2;
CONSTANT rows : positive := 2 ** row_addr_width;
CONSTANT cols : positive := 2 ** col_addr_width;
END sram_array;
ARCHITECTURE primitive OF sram_array IS
SIGNAL MUXED_D_OUT : std_logic_vector(data_width-1 DOWNTO 0);
SIGNAL COLS_WE : std_logic_vector(cols-1 DOWNTO 0);
SIGNAL COLS_D_OUT : std_logic_vector(cols*data_width-1 DOWNTO 0);
SIGNAL ROWS_SEL : std_logic_vector(rows-1 DOWNTO 0);
SIGNAL ALL_D_IN : std_logic_vector(data_width-1 DOWNTO 0);
SIGNAL FWD_CS, FWD_WE : std_logic_vector(0 DOWNTO 0);
COMPONENT sram_cell
GENERIC (
width : positive);
PORT (
SEL, WE : in std_logic;
D_IN : in std_logic_vector(width-1 DOWNTO 0);
D_OUT : out std_logic_vector(width-1 DOWNTO 0));
END COMPONENT;
FOR ALL : sram_cell USE ENTITY WORK.sram_cell(primitive);
component mux
generic (
select_width, line_width : positive);
PORT (
INPUT : in std_logic_vector(2**select_width*line_width-1 downto 0);
SEL : in std_logic_vector(select_width-1 downto 0);
OUTPUT : out std_logic_vector(line_width-1 downto 0));
end component;
FOR ALL : mux USE ENTITY WORK.mux(recursive);
component demux
generic (
select_width, line_width : positive;
default_out : std_logic);
PORT (
INPUT : in std_logic_vector(line_width-1 downto 0);
SEL : in std_logic_vector(select_width-1 downto 0);
FLOOD : in std_logic;
OUTPUT : out std_logic_vector(2**select_width*line_width-1 downto 0));
end component;
FOR ALL : demux USE ENTITY WORK.demux(recursive);
BEGIN
-- VHDL-87 compliance crap
FWD_CS(0) <= CS;
FWD_WE(0) <= WE;
-- row logic
row_decoder: demux
GENERIC MAP (
select_width => row_addr_width,
line_width => 1,
default_out => '0')
PORT MAP (
INPUT => FWD_CS,
SEL => ADDR(addr_width-1 downto col_addr_width),
FLOOD => SELECT_ALL,
OUTPUT => ROWS_SEL);
-- column logic with only one column
check_col_addr_width_eq_0: IF col_addr_width = 0 GENERATE
no_d_out_mux: MUXED_D_OUT <= COLS_D_OUT;
no_we_demux: COLS_WE(0) <= WE OR SELECT_ALL;
END GENERATE;
-- column logic with more than one columns
check_col_addr_width_gt_0: if col_addr_width > 0 generate
we_demux: demux
generic map (
select_width => col_addr_width,
line_width => 1,
default_out => '0')
port map (
INPUT => FWD_WE,
SEL => ADDR(col_addr_width-1 downto 0),
FLOOD => SELECT_ALL,
OUTPUT => COLS_WE);
d_out_mux: mux
generic map (
select_width => col_addr_width,
line_width => data_width)
port map (
INPUT => COLS_D_OUT,
SEL => ADDR(col_addr_width-1 downto 0),
OUTPUT => MUXED_D_OUT);
end generate;
-- tristate for DATA_OUT port (only enabled at WE=0)
data_out_tristate: DATA_OUT <= MUXED_D_OUT when WE='0'
else (OTHERS => 'Z');
-- DATA_IN to ALL_D_IN signal
switch_data_in: ALL_D_IN <= DATA_IN;
-- generate cells
generate_rows: for row_index in 0 to rows-1 generate
generate_cols: for col_index in 0 to cols-1 generate
cell: sram_cell
generic map (
width => data_width)
port map (
SEL => ROWS_SEL(row_index),
WE => COLS_WE(col_index),
D_IN => ALL_D_IN,
D_OUT => COLS_D_OUT((col_index+1)*data_width-1 DOWNTO col_index*data_width));
end generate generate_cols;
end generate generate_rows;
END primitive;
|
bsd-3-clause
|
fe03e37c8fdf7b8b7ccf44d371ddd571
| 0.602171 | 3.294913 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.sim/sim_1/impl/func/test1_func_impl.vhd
| 1 | 420,761 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Apr 15 21:41:42 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -mode funcsim -nolib -force -file
-- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.sim/sim_1/impl/func/test1_func_impl.vhd
-- Design : top
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider_ClockDivider_clk_wiz is
port (
clkIn : in STD_LOGIC;
clk108M : out STD_LOGIC;
clk10M : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz";
end ClockDivider_ClockDivider_clk_wiz;
architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is
signal clk108M_ClockDivider : STD_LOGIC;
signal clk10M_ClockDivider : STD_LOGIC;
signal clkfbout_ClockDivider : STD_LOGIC;
signal clkfbout_buf_ClockDivider : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ClockDivider,
O => clkfbout_buf_ClockDivider
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk108M_ClockDivider,
O => clk108M
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk10M_ClockDivider,
O => clk10M
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 54.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 108,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ClockDivider,
CLKFBOUT => clkfbout_ClockDivider,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clkIn,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk108M_ClockDivider,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk10M_ClockDivider,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 2 downto 0 );
clkb : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \FrameBuffer_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\doutb[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(0),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
O => doutb(0)
);
\doutb[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(1),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1),
O => doutb(1)
);
\doutb[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(2),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2),
O => doutb(2)
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(3),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3),
O => doutb(3)
);
\doutb[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(4),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4),
O => doutb(4)
);
\doutb[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(5),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5),
O => doutb(5)
);
\doutb[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(6),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6),
O => doutb(6)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(7),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7),
O => doutb(7)
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(2),
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_wrapper_init is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end FrameBuffer_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute PWROPT_WRITE_MODE_CHANGE_A : string;
attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "READ_FIRST:NO_CHANGE_2";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"4646464646464646464646464646464646462020202020202020202020202020",
INIT_06 => X"2020202020202020202020505050505050505050505050505050505046464646",
INIT_07 => X"2041414120202020202020202020202020202047474747474747474747474747",
INIT_08 => X"5A20202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A",
INIT_0A => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_0B => X"47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A3A",
INIT_0C => X"413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0D => X"5A20202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0F => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_10 => X"3A3A3A474720202020503A3A3A3A3A5050505050503A3A3A3A3A3A50463A3A3A",
INIT_11 => X"3A3A3A3A3A4120202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_12 => X"5A20202020202020202020202020202020202020202020202020202020202041",
INIT_13 => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_14 => X"3A4646464646464646463A3A3A3A3A3A46462020202020202020202020202020",
INIT_15 => X"3A3A3A3A3A472020503A3A3A3A3A502020202020503A3A3A3A3A5050463A3A3A",
INIT_16 => X"3A3A3A3A3A3A41202020202020202020202020473A3A3A3A4747474747474747",
INIT_17 => X"5A2020202020202020202020202020202020202020202020202020202020413A",
INIT_18 => X"2020202020202020202020202020205A3A3A3A3A3A5A5A5A5A5A5A5A5A3A3A3A",
INIT_19 => X"464620202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_1A => X"473A3A3A3A3A4720503A3A3A3A3A502020202020503A3A3A3A50202046464646",
INIT_1B => X"3A3A3A3A3A3A3A41202020202020202020202047474747474720202020202020",
INIT_1C => X"5A20202020202020202020202020202020202020202020202020202020413A3A",
INIT_1D => X"202020202020202020202020202020205A3A3A3A3A3A5A20202020205A5A5A5A",
INIT_1E => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_1F => X"20473A3A3A3A3A47503A3A3A3A3A502020202020503A3A3A3A50202020202020",
INIT_20 => X"3A3A413A3A3A3A3A412020202020202020202020202020202020202020202020",
INIT_21 => X"20202020202020202020202020202020202020202020202020202020413A3A3A",
INIT_22 => X"2020202020202020202020202020202020205A3A3A3A3A3A5A20202020202020",
INIT_23 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020",
INIT_24 => X"20473A3A3A3A3A4720503A3A3A3A3A5050505050503A3A3A3A50202020202046",
INIT_25 => X"3A4120413A3A3A3A3A4120202020202020202020202020202020202020202020",
INIT_26 => X"202020202020202020202020202020202020202020202020202020413A3A3A3A",
INIT_27 => X"202020202020202020202020202020202020205A3A3A3A3A3A5A202020202020",
INIT_28 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020",
INIT_29 => X"20473A3A3A3A3A47202050503A3A3A3A3A3A3A3A3A3A3A3A3A50202020202046",
INIT_2A => X"41202020413A3A3A3A3A41202020202020202047474747474747474747202020",
INIT_2B => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D202020202020202020413A3A3A3A3A",
INIT_2C => X"20202020202020202020202020202020202020205A3A3A3A3A3A5A2020202020",
INIT_2D => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020",
INIT_2E => X"20473A3A3A3A3A47202020205050505050505050503A3A3A3A50202020202046",
INIT_2F => X"2020202020413A3A3A3A3A4120202020202020473A3A3A3A3A3A3A3A47202020",
INIT_30 => X"20202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D2020202020202020413A3A3A3A3A41",
INIT_31 => X"2020202020202020202020202020202020202020205A3A3A3A3A3A5A20202020",
INIT_32 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020",
INIT_33 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202046",
INIT_34 => X"414141414141413A3A3A3A3A41202020202020473A3A3A3A4747474747202020",
INIT_35 => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020202020413A3A3A3A3A4141",
INIT_36 => X"202020202020202020202020202020202020202020205A3A3A3A3A3A5A202020",
INIT_37 => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_38 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202020",
INIT_39 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A412020202020473A3A3A3A4720202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020413A3A3A3A3A3A3A3A",
INIT_3B => X"20202020202020202020202020202020202020202020205A3A3A3A3A3A5A2020",
INIT_3C => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_3D => X"473A3A3A3A3A4720202020202020202020202020503A3A3A3A50202020202020",
INIT_3E => X"4141414141414141413A3A3A3A3A4120202020473A3A3A3A4720202020202020",
INIT_3F => X"5A202020202020202020202020202020202020202020413A3A3A3A3A41414141",
INIT_40 => X"20202020202020202020202020205A5A5A5A5A20202020205A3A3A3A3A3A5A5A",
INIT_41 => X"2020202020202046463A3A3A3A3A3A3A46462020202020202020202020202020",
INIT_42 => X"3A3A3A3A3A4720202020202020202020202050503A3A3A3A3A3A505020202020",
INIT_43 => X"202020202020202020413A3A3A3A3A41202020473A3A3A3A4747474747474747",
INIT_44 => X"5A2020202020202020202020202020202020202020413A3A3A3A3A4120202020",
INIT_45 => X"20202020202020202020202020205A3A3A3A5A5A5A5A5A5A5A5A3A3A3A3A3A3A",
INIT_46 => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_47 => X"3A3A3A474720202020202020202020202020503A3A3A3A3A3A3A3A5020202020",
INIT_48 => X"20202020202020202020413A3A3A3A3A412020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_49 => X"5A20202020202020202020202020202020202020413A3A3A3A3A412020202020",
INIT_4A => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_4B => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_4C => X"474747202020202020202020202020202020503A3A3A3A3A3A3A3A5020202020",
INIT_4D => X"2020202020202020202020413A3A3A3A3A4120473A3A3A4747473A3A3A3A3A3A",
INIT_4E => X"5A202020202020202020202020202020202020413A3A3A3A3A41202020202020",
INIT_4F => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_50 => X"2020202020202046464646464646464646462020202020202020202020202020",
INIT_51 => X"2020202020202020202020202020202020205050505050505050505020202020",
INIT_52 => X"2020202020202020202020204141414141414147474747202020474747474747",
INIT_53 => X"5A20202020202020202020202020202020204141414141414120202020202020",
INIT_54 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A",
INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5B => X"2041475046206E41202020202020202020202020202020202020202020202020",
INIT_5C => X"6D656C706D692033206E6F697372655620656E696863614D2D5A206465736162",
INIT_5D => X"20202020202020202020202020202020202020202020202E6E6F697461746E65",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_61 => X"202E7475706E69207478657420726F662064616F6279656B2061206573552020",
INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6B => X"20202E2E2E65756E69746E6F63206F742079656B20796E612073736572502020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => wea(0),
I1 => addra(12),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addrb(12),
I1 => addrb(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute PWROPT_WRITE_MODE_CHANGE_A : string;
attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "READ_FIRST:NO_CHANGE_2";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_40 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_41 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_42 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_43 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_44 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_45 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_46 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_47 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_48 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_49 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_50 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_51 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_52 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_53 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_54 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_61 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT";
attribute PWROPT_WRITE_MODE_CHANGE_A : string;
attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "READ_FIRST:NO_CHANGE_2";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020",
INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074",
INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073",
INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 3) => addrb(10 downto 0),
ADDRBWRADDR(2 downto 0) => B"000",
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_ena,
ENBWREN => ram_enb,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => addra(12),
I1 => addra(11),
I2 => addra(13),
I3 => wea(0),
O => ram_ena
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addrb(11),
I1 => addrb(13),
I2 => addrb(12),
O => ram_enb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Vga is
port (
addrb : out STD_LOGIC_VECTOR ( 13 downto 0 );
Hsync_OBUF : out STD_LOGIC;
Vsync_OBUF : out STD_LOGIC;
vgaBlue_OBUF : out STD_LOGIC_VECTOR ( 0 to 0 );
clk108M : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end Vga;
architecture STRUCTURE of Vga is
signal X : STD_LOGIC_VECTOR ( 2 downto 0 );
signal Y : STD_LOGIC_VECTOR ( 3 downto 0 );
signal char : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \char[0]_i_1_n_0\ : STD_LOGIC;
signal \char[1]_i_1_n_0\ : STD_LOGIC;
signal \char[2]_i_1_n_0\ : STD_LOGIC;
signal \char[3]_i_1_n_0\ : STD_LOGIC;
signal \char[4]_i_1_n_0\ : STD_LOGIC;
signal \char[5]_i_1_n_0\ : STD_LOGIC;
signal \char[6]_i_1_n_0\ : STD_LOGIC;
signal \char[7]_i_1_n_0\ : STD_LOGIC;
signal enable : STD_LOGIC;
signal enable_i_1_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_10_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_11_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_12_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_13_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_14_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_15_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_16_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_17_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_18_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_19_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_1_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_20_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_21_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_22_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_23_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_24_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_25_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_26_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_27_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_28_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_2_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_3_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_4_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_5_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_6_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_7_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_8_n_0 : STD_LOGIC;
signal fbOutAddr_reg_i_9_n_0 : STD_LOGIC;
signal g0_b0_n_0 : STD_LOGIC;
signal g0_b1_n_0 : STD_LOGIC;
signal g0_b2_i_1_n_0 : STD_LOGIC;
signal g0_b2_i_2_n_0 : STD_LOGIC;
signal g0_b2_n_0 : STD_LOGIC;
signal g0_b3_n_0 : STD_LOGIC;
signal g0_b4_n_0 : STD_LOGIC;
signal g0_b5_n_0 : STD_LOGIC;
signal g0_b6_n_0 : STD_LOGIC;
signal g0_b7_n_0 : STD_LOGIC;
signal g10_b0_n_0 : STD_LOGIC;
signal g10_b1_n_0 : STD_LOGIC;
signal g10_b2_n_0 : STD_LOGIC;
signal g10_b3_n_0 : STD_LOGIC;
signal g10_b4_n_0 : STD_LOGIC;
signal g10_b5_n_0 : STD_LOGIC;
signal g11_b0_n_0 : STD_LOGIC;
signal g11_b1_n_0 : STD_LOGIC;
signal g11_b2_n_0 : STD_LOGIC;
signal g11_b3_n_0 : STD_LOGIC;
signal g11_b4_n_0 : STD_LOGIC;
signal g11_b5_n_0 : STD_LOGIC;
signal g11_b6_n_0 : STD_LOGIC;
signal g12_b0_n_0 : STD_LOGIC;
signal g12_b1_n_0 : STD_LOGIC;
signal g12_b2_n_0 : STD_LOGIC;
signal g12_b3_n_0 : STD_LOGIC;
signal g12_b4_n_0 : STD_LOGIC;
signal g12_b5_n_0 : STD_LOGIC;
signal g12_b6_n_0 : STD_LOGIC;
signal g13_b0_n_0 : STD_LOGIC;
signal g13_b1_n_0 : STD_LOGIC;
signal g13_b2_n_0 : STD_LOGIC;
signal g13_b3_n_0 : STD_LOGIC;
signal g13_b4_n_0 : STD_LOGIC;
signal g13_b5_n_0 : STD_LOGIC;
signal g13_b6_n_0 : STD_LOGIC;
signal g14_b0_n_0 : STD_LOGIC;
signal g14_b1_n_0 : STD_LOGIC;
signal g14_b2_n_0 : STD_LOGIC;
signal g14_b3_n_0 : STD_LOGIC;
signal g14_b4_n_0 : STD_LOGIC;
signal g14_b5_n_0 : STD_LOGIC;
signal g14_b6_n_0 : STD_LOGIC;
signal g15_b0_n_0 : STD_LOGIC;
signal g15_b1_n_0 : STD_LOGIC;
signal g15_b2_n_0 : STD_LOGIC;
signal g15_b3_n_0 : STD_LOGIC;
signal g15_b4_n_0 : STD_LOGIC;
signal g15_b5_n_0 : STD_LOGIC;
signal g15_b6_n_0 : STD_LOGIC;
signal g16_b0_n_0 : STD_LOGIC;
signal g16_b1_n_0 : STD_LOGIC;
signal g16_b2_n_0 : STD_LOGIC;
signal g16_b3_n_0 : STD_LOGIC;
signal g16_b4_n_0 : STD_LOGIC;
signal g16_b5_n_0 : STD_LOGIC;
signal g16_b6_n_0 : STD_LOGIC;
signal g17_b0_n_0 : STD_LOGIC;
signal g17_b1_n_0 : STD_LOGIC;
signal g17_b2_n_0 : STD_LOGIC;
signal g17_b3_n_0 : STD_LOGIC;
signal g17_b4_n_0 : STD_LOGIC;
signal g17_b5_n_0 : STD_LOGIC;
signal g17_b6_n_0 : STD_LOGIC;
signal g18_b0_n_0 : STD_LOGIC;
signal g18_b1_n_0 : STD_LOGIC;
signal g18_b2_n_0 : STD_LOGIC;
signal g18_b3_n_0 : STD_LOGIC;
signal g18_b4_n_0 : STD_LOGIC;
signal g18_b5_n_0 : STD_LOGIC;
signal g18_b6_n_0 : STD_LOGIC;
signal g19_b0_n_0 : STD_LOGIC;
signal g19_b1_n_0 : STD_LOGIC;
signal g19_b2_n_0 : STD_LOGIC;
signal g19_b3_n_0 : STD_LOGIC;
signal g19_b4_n_0 : STD_LOGIC;
signal g19_b5_n_0 : STD_LOGIC;
signal g19_b6_n_0 : STD_LOGIC;
signal g19_b7_n_0 : STD_LOGIC;
signal g1_b0_n_0 : STD_LOGIC;
signal g1_b1_n_0 : STD_LOGIC;
signal g1_b2_n_0 : STD_LOGIC;
signal g1_b3_n_0 : STD_LOGIC;
signal g1_b4_n_0 : STD_LOGIC;
signal g1_b5_n_0 : STD_LOGIC;
signal g1_b6_n_0 : STD_LOGIC;
signal g1_b7_n_0 : STD_LOGIC;
signal g20_b0_n_0 : STD_LOGIC;
signal g20_b1_n_0 : STD_LOGIC;
signal g20_b2_n_0 : STD_LOGIC;
signal g20_b3_n_0 : STD_LOGIC;
signal g20_b4_n_0 : STD_LOGIC;
signal g20_b5_n_0 : STD_LOGIC;
signal g20_b6_n_0 : STD_LOGIC;
signal g21_b0_n_0 : STD_LOGIC;
signal g21_b1_n_0 : STD_LOGIC;
signal g21_b2_n_0 : STD_LOGIC;
signal g21_b3_n_0 : STD_LOGIC;
signal g21_b5_n_0 : STD_LOGIC;
signal g21_b6_n_0 : STD_LOGIC;
signal g21_b7_n_0 : STD_LOGIC;
signal g22_b0_n_0 : STD_LOGIC;
signal g22_b1_n_0 : STD_LOGIC;
signal g22_b2_n_0 : STD_LOGIC;
signal g22_b3_n_0 : STD_LOGIC;
signal g22_b4_n_0 : STD_LOGIC;
signal g22_b5_n_0 : STD_LOGIC;
signal g22_b6_n_0 : STD_LOGIC;
signal g22_b7_n_0 : STD_LOGIC;
signal g23_b0_n_0 : STD_LOGIC;
signal g23_b1_n_0 : STD_LOGIC;
signal g23_b2_n_0 : STD_LOGIC;
signal g23_b3_n_0 : STD_LOGIC;
signal g23_b4_n_0 : STD_LOGIC;
signal g23_b5_n_0 : STD_LOGIC;
signal g23_b6_n_0 : STD_LOGIC;
signal g23_b7_n_0 : STD_LOGIC;
signal g24_b0_n_0 : STD_LOGIC;
signal g24_b1_n_0 : STD_LOGIC;
signal g24_b2_n_0 : STD_LOGIC;
signal g24_b3_n_0 : STD_LOGIC;
signal g24_b4_n_0 : STD_LOGIC;
signal g24_b5_n_0 : STD_LOGIC;
signal g24_b6_n_0 : STD_LOGIC;
signal g25_b0_n_0 : STD_LOGIC;
signal g25_b1_n_0 : STD_LOGIC;
signal g25_b2_n_0 : STD_LOGIC;
signal g25_b3_n_0 : STD_LOGIC;
signal g25_b4_n_0 : STD_LOGIC;
signal g25_b5_n_0 : STD_LOGIC;
signal g25_b6_n_0 : STD_LOGIC;
signal g26_b0_n_0 : STD_LOGIC;
signal g26_b1_n_0 : STD_LOGIC;
signal g26_b2_n_0 : STD_LOGIC;
signal g26_b3_n_0 : STD_LOGIC;
signal g26_b4_n_0 : STD_LOGIC;
signal g26_b5_n_0 : STD_LOGIC;
signal g26_b6_n_0 : STD_LOGIC;
signal g27_b0_n_0 : STD_LOGIC;
signal g27_b1_n_0 : STD_LOGIC;
signal g27_b2_n_0 : STD_LOGIC;
signal g27_b3_n_0 : STD_LOGIC;
signal g27_b5_n_0 : STD_LOGIC;
signal g27_b6_n_0 : STD_LOGIC;
signal g27_b7_n_0 : STD_LOGIC;
signal g28_b0_n_0 : STD_LOGIC;
signal g28_b1_n_0 : STD_LOGIC;
signal g28_b2_n_0 : STD_LOGIC;
signal g28_b3_n_0 : STD_LOGIC;
signal g28_b4_n_0 : STD_LOGIC;
signal g28_b5_n_0 : STD_LOGIC;
signal g28_b6_n_0 : STD_LOGIC;
signal g29_b0_n_0 : STD_LOGIC;
signal g29_b1_n_0 : STD_LOGIC;
signal g29_b2_n_0 : STD_LOGIC;
signal g29_b3_n_0 : STD_LOGIC;
signal g29_b4_n_0 : STD_LOGIC;
signal g29_b5_n_0 : STD_LOGIC;
signal g29_b6_n_0 : STD_LOGIC;
signal g29_b7_n_0 : STD_LOGIC;
signal g2_b0_n_0 : STD_LOGIC;
signal g2_b1_n_0 : STD_LOGIC;
signal g2_b2_n_0 : STD_LOGIC;
signal g2_b3_n_0 : STD_LOGIC;
signal g2_b4_n_0 : STD_LOGIC;
signal g2_b5_n_0 : STD_LOGIC;
signal g2_b6_n_0 : STD_LOGIC;
signal g2_b7_n_0 : STD_LOGIC;
signal g30_b0_n_0 : STD_LOGIC;
signal g30_b1_n_0 : STD_LOGIC;
signal g30_b2_n_0 : STD_LOGIC;
signal g30_b3_n_0 : STD_LOGIC;
signal g30_b4_n_0 : STD_LOGIC;
signal g30_b5_n_0 : STD_LOGIC;
signal g30_b6_n_0 : STD_LOGIC;
signal g30_b7_n_0 : STD_LOGIC;
signal g31_b0_n_0 : STD_LOGIC;
signal g31_b1_n_0 : STD_LOGIC;
signal g31_b2_n_0 : STD_LOGIC;
signal g31_b3_n_0 : STD_LOGIC;
signal g31_b4_n_0 : STD_LOGIC;
signal g31_b5_n_0 : STD_LOGIC;
signal g31_b6_n_0 : STD_LOGIC;
signal g3_b0_n_0 : STD_LOGIC;
signal g3_b1_n_0 : STD_LOGIC;
signal g3_b2_n_0 : STD_LOGIC;
signal g3_b3_n_0 : STD_LOGIC;
signal g3_b4_n_0 : STD_LOGIC;
signal g3_b5_n_0 : STD_LOGIC;
signal g3_b6_n_0 : STD_LOGIC;
signal g3_b7_n_0 : STD_LOGIC;
signal g4_b0_n_0 : STD_LOGIC;
signal g4_b1_n_0 : STD_LOGIC;
signal g4_b2_n_0 : STD_LOGIC;
signal g4_b3_n_0 : STD_LOGIC;
signal g4_b4_n_0 : STD_LOGIC;
signal g4_b5_n_0 : STD_LOGIC;
signal g4_b6_n_0 : STD_LOGIC;
signal g5_b0_n_0 : STD_LOGIC;
signal g5_b1_n_0 : STD_LOGIC;
signal g5_b2_n_0 : STD_LOGIC;
signal g5_b3_n_0 : STD_LOGIC;
signal g5_b4_n_0 : STD_LOGIC;
signal g5_b5_n_0 : STD_LOGIC;
signal g5_b6_n_0 : STD_LOGIC;
signal g5_b7_n_0 : STD_LOGIC;
signal g6_b0_n_0 : STD_LOGIC;
signal g6_b1_n_0 : STD_LOGIC;
signal g6_b2_n_0 : STD_LOGIC;
signal g6_b3_n_0 : STD_LOGIC;
signal g6_b4_n_0 : STD_LOGIC;
signal g6_b5_n_0 : STD_LOGIC;
signal g6_b6_n_0 : STD_LOGIC;
signal g7_b0_n_0 : STD_LOGIC;
signal g7_b1_n_0 : STD_LOGIC;
signal g7_b2_n_0 : STD_LOGIC;
signal g7_b3_n_0 : STD_LOGIC;
signal g7_b4_n_0 : STD_LOGIC;
signal g7_b5_n_0 : STD_LOGIC;
signal g7_b6_n_0 : STD_LOGIC;
signal g7_b7_n_0 : STD_LOGIC;
signal g8_b0_n_0 : STD_LOGIC;
signal g8_b1_n_0 : STD_LOGIC;
signal g8_b2_n_0 : STD_LOGIC;
signal g8_b3_n_0 : STD_LOGIC;
signal g8_b4_n_0 : STD_LOGIC;
signal g8_b6_n_0 : STD_LOGIC;
signal g9_b0_n_0 : STD_LOGIC;
signal g9_b1_n_0 : STD_LOGIC;
signal g9_b2_n_0 : STD_LOGIC;
signal g9_b3_n_0 : STD_LOGIC;
signal g9_b4_n_0 : STD_LOGIC;
signal g9_b5_n_0 : STD_LOGIC;
signal g9_b6_n_0 : STD_LOGIC;
signal hSync_i_1_n_0 : STD_LOGIC;
signal hSync_i_2_n_0 : STD_LOGIC;
signal hSync_i_3_n_0 : STD_LOGIC;
signal \h_count[2]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 3 );
signal nextChar : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \nextChar[7]_i_1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vSync_i_1_n_0 : STD_LOGIC;
signal vSync_i_2_n_0 : STD_LOGIC;
signal \v_count[0]_rep_i_1_n_0\ : STD_LOGIC;
signal \v_count[1]_rep_i_1_n_0\ : STD_LOGIC;
signal \v_count[2]_rep_i_1_n_0\ : STD_LOGIC;
signal \v_count[3]_rep__0_i_1_n_0\ : STD_LOGIC;
signal \v_count[3]_rep_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[0]_rep_n_0\ : STD_LOGIC;
signal \v_count_reg[1]_rep_n_0\ : STD_LOGIC;
signal \v_count_reg[2]_rep_n_0\ : STD_LOGIC;
signal \v_count_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \v_count_reg[3]_rep_n_0\ : STD_LOGIC;
signal \v_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 4 );
signal \vgaRed[0]_i_10_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_11_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_13_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_14_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_15_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_16_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_17_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_18_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_19_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_1_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_20_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_21_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_22_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_23_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_29_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_33_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_34_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_40_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_41_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_42_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_48_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_4_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_56_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_5_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_64_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_68_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_69_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_6_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_7_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_80_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_8_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_9_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_100_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_101_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_102_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_103_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_104_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_105_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_106_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_107_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_108_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_109_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_110_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_111_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_112_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_113_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_114_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_115_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_116_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_117_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_118_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_119_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_120_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_121_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_122_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_123_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_124_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_125_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_126_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_127_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_128_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_129_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_12_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_130_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_131_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_132_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_133_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_134_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_135_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_136_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_137_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_138_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_139_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_140_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_141_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_142_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_143_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_144_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_145_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_146_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_147_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_148_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_149_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_150_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_151_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_152_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_153_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_154_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_155_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_156_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_157_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_158_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_159_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_160_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_161_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_162_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_163_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_164_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_165_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_166_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_167_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_168_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_169_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_170_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_171_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_172_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_173_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_174_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_175_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_176_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_177_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_178_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_179_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_180_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_24_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_25_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_26_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_27_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_28_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_30_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_31_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_32_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_35_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_36_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_37_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_38_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_39_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_43_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_44_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_45_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_46_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_47_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_49_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_50_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_51_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_52_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_53_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_54_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_55_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_57_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_58_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_59_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_60_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_61_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_62_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_63_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_65_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_66_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_67_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_70_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_71_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_72_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_73_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_74_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_75_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_76_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_77_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_78_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_79_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_81_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_82_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_83_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_84_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_85_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_86_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_87_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_88_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_89_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_90_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_91_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_92_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_93_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_94_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_95_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_96_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_97_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_98_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_99_n_0\ : STD_LOGIC;
signal NLW_fbOutAddr_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_fbOutAddr_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_fbOutAddr_reg_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_fbOutAddr_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_fbOutAddr_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_fbOutAddr_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_fbOutAddr_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_fbOutAddr_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_fbOutAddr_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_fbOutAddr_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 14 );
signal NLW_fbOutAddr_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \v_count[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \v_count[0]_rep_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \v_count[1]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \v_count[1]_rep_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \v_count[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \v_count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \v_count[3]_rep__0_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \v_count[3]_rep_i_1\ : label is "soft_lutpair14";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \v_count_reg[0]\ : label is "v_count_reg[0]";
attribute ORIG_CELL_NAME of \v_count_reg[0]_rep\ : label is "v_count_reg[0]";
attribute ORIG_CELL_NAME of \v_count_reg[1]\ : label is "v_count_reg[1]";
attribute ORIG_CELL_NAME of \v_count_reg[1]_rep\ : label is "v_count_reg[1]";
attribute ORIG_CELL_NAME of \v_count_reg[2]\ : label is "v_count_reg[2]";
attribute ORIG_CELL_NAME of \v_count_reg[2]_rep\ : label is "v_count_reg[2]";
attribute ORIG_CELL_NAME of \v_count_reg[3]\ : label is "v_count_reg[3]";
attribute ORIG_CELL_NAME of \v_count_reg[3]_rep\ : label is "v_count_reg[3]";
attribute ORIG_CELL_NAME of \v_count_reg[3]_rep__0\ : label is "v_count_reg[3]";
begin
\char[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(0),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(0),
O => \char[0]_i_1_n_0\
);
\char[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(1),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(1),
O => \char[1]_i_1_n_0\
);
\char[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(2),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(2),
O => \char[2]_i_1_n_0\
);
\char[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(3),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(3),
O => \char[3]_i_1_n_0\
);
\char[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(4),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(4),
O => \char[4]_i_1_n_0\
);
\char[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(5),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(5),
O => \char[5]_i_1_n_0\
);
\char[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(6),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(6),
O => \char[6]_i_1_n_0\
);
\char[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(7),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(7),
O => \char[7]_i_1_n_0\
);
\char_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[0]_i_1_n_0\,
Q => char(0),
R => '0'
);
\char_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[1]_i_1_n_0\,
Q => char(1),
R => '0'
);
\char_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[2]_i_1_n_0\,
Q => char(2),
R => '0'
);
\char_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[3]_i_1_n_0\,
Q => char(3),
R => '0'
);
\char_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[4]_i_1_n_0\,
Q => char(4),
R => '0'
);
\char_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[5]_i_1_n_0\,
Q => char(5),
R => '0'
);
\char_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[6]_i_1_n_0\,
Q => char(6),
R => '0'
);
\char_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => enable,
D => \char[7]_i_1_n_0\,
Q => char(7),
R => '0'
);
enable_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => \h_count_reg__0\(10),
I1 => \h_count_reg__0\(8),
I2 => \h_count_reg__0\(9),
I3 => \v_count_reg__0\(10),
O => enable_i_1_n_0
);
enable_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => enable_i_1_n_0,
Q => enable,
R => '0'
);
fbOutAddr_reg: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 0,
AREG => 1,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 1,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 7) => B"00000000000000000000000",
A(6) => fbOutAddr_reg_i_5_n_0,
A(5) => fbOutAddr_reg_i_6_n_0,
A(4) => fbOutAddr_reg_i_7_n_0,
A(3) => fbOutAddr_reg_i_8_n_0,
A(2) => fbOutAddr_reg_i_9_n_0,
A(1) => fbOutAddr_reg_i_10_n_0,
A(0) => fbOutAddr_reg_i_11_n_0,
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_fbOutAddr_reg_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 0) => B"000000000010100000",
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_fbOutAddr_reg_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 8) => B"0000000000000000000000000000000000000000",
C(7) => fbOutAddr_reg_i_12_n_0,
C(6) => fbOutAddr_reg_i_13_n_0,
C(5) => fbOutAddr_reg_i_14_n_0,
C(4) => fbOutAddr_reg_i_15_n_0,
C(3) => fbOutAddr_reg_i_16_n_0,
C(2) => fbOutAddr_reg_i_17_n_0,
C(1) => fbOutAddr_reg_i_18_n_0,
C(0) => fbOutAddr_reg_i_19_n_0,
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_fbOutAddr_reg_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_fbOutAddr_reg_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => fbOutAddr_reg_i_1_n_0,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '1',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => fbOutAddr_reg_i_2_n_0,
CLK => clk108M,
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_fbOutAddr_reg_MULTSIGNOUT_UNCONNECTED,
OPMODE(6) => '0',
OPMODE(5) => enable,
OPMODE(4) => enable,
OPMODE(3 downto 0) => B"0101",
OVERFLOW => NLW_fbOutAddr_reg_OVERFLOW_UNCONNECTED,
P(47 downto 14) => NLW_fbOutAddr_reg_P_UNCONNECTED(47 downto 14),
P(13 downto 0) => addrb(13 downto 0),
PATTERNBDETECT => NLW_fbOutAddr_reg_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_fbOutAddr_reg_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_fbOutAddr_reg_PCOUT_UNCONNECTED(47 downto 0),
RSTA => fbOutAddr_reg_i_3_n_0,
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => fbOutAddr_reg_i_1_n_0,
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => fbOutAddr_reg_i_4_n_0,
UNDERFLOW => NLW_fbOutAddr_reg_UNDERFLOW_UNCONNECTED
);
fbOutAddr_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"88808888"
)
port map (
I0 => \h_count_reg__0\(9),
I1 => \h_count_reg__0\(10),
I2 => \h_count_reg__0\(8),
I3 => fbOutAddr_reg_i_20_n_0,
I4 => fbOutAddr_reg_i_21_n_0,
O => fbOutAddr_reg_i_1_n_0
);
fbOutAddr_reg_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => Y(3),
I1 => Y(1),
I2 => Y(0),
I3 => Y(2),
I4 => \v_count_reg__0\(4),
I5 => \v_count_reg__0\(5),
O => fbOutAddr_reg_i_10_n_0
);
fbOutAddr_reg_i_11: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg__0\(4),
I1 => Y(2),
I2 => Y(0),
I3 => Y(1),
I4 => Y(3),
O => fbOutAddr_reg_i_11_n_0
);
fbOutAddr_reg_i_12: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg__0\(10),
I1 => \h_count_reg__0\(8),
I2 => fbOutAddr_reg_i_27_n_0,
I3 => \h_count_reg__0\(7),
I4 => \h_count_reg__0\(9),
O => fbOutAddr_reg_i_12_n_0
);
fbOutAddr_reg_i_13: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg__0\(9),
I1 => \h_count_reg__0\(7),
I2 => fbOutAddr_reg_i_27_n_0,
I3 => \h_count_reg__0\(8),
O => fbOutAddr_reg_i_13_n_0
);
fbOutAddr_reg_i_14: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \h_count_reg__0\(8),
I1 => \h_count_reg__0\(6),
I2 => \h_count_reg__0\(5),
I3 => \h_count_reg__0\(4),
I4 => fbOutAddr_reg_i_28_n_0,
I5 => \h_count_reg__0\(7),
O => fbOutAddr_reg_i_14_n_0
);
fbOutAddr_reg_i_15: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAAAAAA"
)
port map (
I0 => \h_count_reg__0\(7),
I1 => fbOutAddr_reg_i_28_n_0,
I2 => \h_count_reg__0\(4),
I3 => \h_count_reg__0\(5),
I4 => \h_count_reg__0\(6),
O => fbOutAddr_reg_i_15_n_0
);
fbOutAddr_reg_i_16: unisim.vcomponents.LUT4
generic map(
INIT => X"BF40"
)
port map (
I0 => fbOutAddr_reg_i_28_n_0,
I1 => \h_count_reg__0\(4),
I2 => \h_count_reg__0\(5),
I3 => \h_count_reg__0\(6),
O => fbOutAddr_reg_i_16_n_0
);
fbOutAddr_reg_i_17: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg__0\(5),
I1 => X(2),
I2 => X(0),
I3 => X(1),
I4 => \h_count_reg__0\(3),
I5 => \h_count_reg__0\(4),
O => fbOutAddr_reg_i_17_n_0
);
fbOutAddr_reg_i_18: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => X(2),
I1 => X(0),
I2 => X(1),
I3 => \h_count_reg__0\(3),
I4 => \h_count_reg__0\(4),
O => fbOutAddr_reg_i_18_n_0
);
fbOutAddr_reg_i_19: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg__0\(3),
I1 => X(2),
I2 => X(0),
I3 => X(1),
O => fbOutAddr_reg_i_19_n_0
);
fbOutAddr_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => fbOutAddr_reg_i_22_n_0,
I1 => X(2),
I2 => enable,
I3 => X(1),
I4 => X(0),
O => fbOutAddr_reg_i_2_n_0
);
fbOutAddr_reg_i_20: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => \h_count_reg__0\(7),
I1 => \h_count_reg__0\(6),
I2 => \h_count_reg__0\(5),
O => fbOutAddr_reg_i_20_n_0
);
fbOutAddr_reg_i_21: unisim.vcomponents.LUT6
generic map(
INIT => X"1555FFFFFFFFFFFF"
)
port map (
I0 => \h_count_reg__0\(3),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => \h_count_reg__0\(7),
I5 => \h_count_reg__0\(4),
O => fbOutAddr_reg_i_21_n_0
);
fbOutAddr_reg_i_22: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => enable,
I1 => \h_count_reg__0\(10),
I2 => \h_count_reg__0\(8),
I3 => \h_count_reg__0\(9),
O => fbOutAddr_reg_i_22_n_0
);
fbOutAddr_reg_i_23: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \v_count_reg__0\(6),
I1 => \v_count_reg__0\(7),
I2 => \v_count_reg__0\(9),
I3 => \v_count_reg__0\(8),
O => fbOutAddr_reg_i_23_n_0
);
fbOutAddr_reg_i_24: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => Y(1),
I1 => Y(0),
I2 => Y(2),
O => fbOutAddr_reg_i_24_n_0
);
fbOutAddr_reg_i_25: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Y(3),
I1 => \v_count_reg__0\(4),
O => fbOutAddr_reg_i_25_n_0
);
fbOutAddr_reg_i_26: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \v_count_reg__0\(5),
I1 => \v_count_reg__0\(4),
I2 => Y(2),
I3 => Y(0),
I4 => Y(1),
I5 => Y(3),
O => fbOutAddr_reg_i_26_n_0
);
fbOutAddr_reg_i_27: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \h_count_reg__0\(6),
I1 => \h_count_reg__0\(5),
I2 => \h_count_reg__0\(4),
I3 => fbOutAddr_reg_i_28_n_0,
O => fbOutAddr_reg_i_27_n_0
);
fbOutAddr_reg_i_28: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => X(2),
I1 => X(0),
I2 => X(1),
I3 => \h_count_reg__0\(3),
O => fbOutAddr_reg_i_28_n_0
);
fbOutAddr_reg_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A888800000000"
)
port map (
I0 => fbOutAddr_reg_i_1_n_0,
I1 => fbOutAddr_reg_i_23_n_0,
I2 => fbOutAddr_reg_i_24_n_0,
I3 => fbOutAddr_reg_i_25_n_0,
I4 => \v_count_reg__0\(5),
I5 => \v_count_reg__0\(10),
O => fbOutAddr_reg_i_3_n_0
);
fbOutAddr_reg_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"0000A800"
)
port map (
I0 => \v_count_reg__0\(10),
I1 => \h_count_reg__0\(9),
I2 => \h_count_reg__0\(8),
I3 => \h_count_reg__0\(10),
I4 => enable,
O => fbOutAddr_reg_i_4_n_0
);
fbOutAddr_reg_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg__0\(10),
I1 => \v_count_reg__0\(8),
I2 => \v_count_reg__0\(6),
I3 => fbOutAddr_reg_i_26_n_0,
I4 => \v_count_reg__0\(7),
I5 => \v_count_reg__0\(9),
O => fbOutAddr_reg_i_5_n_0
);
fbOutAddr_reg_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg__0\(9),
I1 => \v_count_reg__0\(7),
I2 => fbOutAddr_reg_i_26_n_0,
I3 => \v_count_reg__0\(6),
I4 => \v_count_reg__0\(8),
O => fbOutAddr_reg_i_6_n_0
);
fbOutAddr_reg_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg__0\(8),
I1 => \v_count_reg__0\(6),
I2 => fbOutAddr_reg_i_26_n_0,
I3 => \v_count_reg__0\(7),
O => fbOutAddr_reg_i_7_n_0
);
fbOutAddr_reg_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg__0\(7),
I1 => \v_count_reg__0\(5),
I2 => \v_count_reg__0\(4),
I3 => fbOutAddr_reg_i_24_n_0,
I4 => Y(3),
I5 => \v_count_reg__0\(6),
O => fbOutAddr_reg_i_8_n_0
);
fbOutAddr_reg_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg__0\(6),
I1 => Y(3),
I2 => fbOutAddr_reg_i_24_n_0,
I3 => \v_count_reg__0\(4),
I4 => \v_count_reg__0\(5),
O => fbOutAddr_reg_i_9_n_0
);
g0_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000007F807F80000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b0_n_0
);
g0_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"01E00FFC08040000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b1_n_0
);
g0_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"03F00F6C08940000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g0_b2_n_0
);
g0_b2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(0),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(0),
O => g0_b2_i_1_n_0
);
g0_b2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0002"
)
port map (
I0 => nextChar(1),
I1 => X(1),
I2 => X(0),
I3 => X(2),
I4 => char(1),
O => g0_b2_i_2_n_0
);
g0_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07F00E7C09840000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g0_b3_n_0
);
g0_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00E7C09840000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g0_b4_n_0
);
g0_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"07F00F6C08940000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g0_b5_n_0
);
g0_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"03F00FFC08040000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b6_n_0
);
g0_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"01E007F807F80000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b7_n_0
);
g10_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g10_b0_n_0
);
g10_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"008002A000000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g10_b1_n_0
);
g10_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"008003E0080403F0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g10_b2_n_0
);
g10_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"03E001C00C0C07F8"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g10_b3_n_0
);
g10_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03E001C007F80C0C"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g10_b4_n_0
);
g10_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"008003E003F00804"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g10_b5_n_0
);
g11_b0: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g11_b0_n_0
);
g11_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0600000000800000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g11_b1_n_0
);
g11_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0300000000801000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g11_b2_n_0
);
g11_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"01800C0000801E00"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g11_b3_n_0
);
g11_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"00C00C0000800E00"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g11_b4_n_0
);
g11_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0060000000800000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g11_b5_n_0
);
g11_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0030000000800000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g11_b6_n_0
);
g12_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"04080E08000007F8"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g12_b0_n_0
);
g12_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0F0C08100FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g12_b1_n_0
);
g12_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0844098408180984"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g12_b2_n_0
);
g12_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"084408C40FFC08C4"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g12_b3_n_0
);
g12_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"084408640FFC0864"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g12_b4_n_0
);
g12_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC0C3C08000FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g12_b5_n_0
);
g12_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07B80C18080007F8"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g12_b6_n_0
);
g13_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000C07F0047C00C0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g13_b0_n_0
);
g13_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0FF80C7C00E0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g13_b1_n_0
);
g13_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0F04084C084400B0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g13_b2_n_0
);
g13_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0F84084408440898"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g13_b3_n_0
);
g13_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"00C4084408440FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g13_b4_n_0
);
g13_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"007C0FC00FC40FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g13_b5_n_0
);
g13_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"003C078007840880"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g13_b6_n_0
);
g14_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000003807B8"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g14_b0_n_0
);
g14_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000087C0FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g14_b1_n_0
);
g14_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000008440844"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g14_b2_n_0
);
g14_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0E30063008440844"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g14_b3_n_0
);
g14_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"063006300C440844"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g14_b4_n_0
);
g14_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000007FC0FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g14_b5_n_0
);
g14_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000003F807B8"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g14_b6_n_0
);
g15_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0018000000000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g15_b0_n_0
);
g15_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"001C080801200080"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g15_b1_n_0
);
g15_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"00040C18012001C0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g15_b2_n_0
);
g15_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0DC4063001200360"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g15_b3_n_0
);
g15_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0DE4036001200630"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g15_b4_n_0
);
g15_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"003C01C001200C18"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g15_b5_n_0
);
g15_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0018008001200808"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g15_b6_n_0
);
g16_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"03F008040FE007F8"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g16_b0_n_0
);
g16_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FF00FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g16_b1_n_0
);
g16_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0FFC00980804"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g16_b2_n_0
);
g16_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"08040844008C0BC4"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g16_b3_n_0
);
g16_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0804084400980BC4"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g16_b4_n_0
);
g16_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0FFC0FF00BFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g16_b5_n_0
);
g16_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"061807B80FE001F8"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g16_b6_n_0
);
g17_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"03F0080408040804"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g17_b0_n_0
);
g17_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FFC0FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g17_b1_n_0
);
g17_b2: unisim.vcomponents.LUT5
generic map(
INIT => X"223E3E3E"
)
port map (
I0 => \v_count_reg[1]_rep_n_0\,
I1 => Y(2),
I2 => \v_count_reg[3]_rep__0_n_0\,
I3 => g0_b2_i_1_n_0,
I4 => g0_b2_i_2_n_0,
O => g17_b2_n_0
);
g17_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0884084408440804"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g17_b3_n_0
);
g17_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"088400E408E40C0C"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g17_b4_n_0
);
g17_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"078C000C0C0C07F8"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g17_b5_n_0
);
g17_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0F98001C0E1C03F0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g17_b6_n_0
);
g18_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0804070000000FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g18_b0_n_0
);
g18_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"3E30003E"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g18_b1_n_0
);
g18_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC080008040040"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g18_b2_n_0
);
g18_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"00C008040FFC0040"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g18_b3_n_0
);
g18_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"01E00FFC0FFC0040"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g18_b4_n_0
);
g18_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0F3C07FC08040FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g18_b5_n_0
);
g18_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0E1C000400000FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g18_b6_n_0
);
g19_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FFC0804"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g19_b0_n_0
);
g19_b1: unisim.vcomponents.LUT3
generic map(
INIT => X"3E"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
O => g19_b1_n_0
);
g19_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0804003800380FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g19_b2_n_0
);
g19_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0804007000700804"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g19_b3_n_0
);
g19_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"080400E000700800"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g19_b4_n_0
);
g19_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC0FFC00380C00"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g19_b5_n_0
);
g19_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FFC0E00"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g19_b6_n_0
);
g19_b7: unisim.vcomponents.LUT5
generic map(
INIT => X"00003E00"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g19_b7_n_0
);
g1_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C001C00080"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b0_n_0
);
g1_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"000001E001C001C0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b1_n_0
);
g1_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"018009F009F003E0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g1_b2_n_0
);
g1_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"03C00FF80E3807F0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g1_b3_n_0
);
g1_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03C00FF80E3803E0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g1_b4_n_0
);
g1_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"018009F009F001C0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g1_b5_n_0
);
g1_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"000001E001C00080"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b6_n_0
);
g1_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C001C00000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b7_n_0
);
g20_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0618080407F80804"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g20_b0_n_0
);
g20_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0E3C0FFC0FFC0FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g20_b1_n_0
);
g20_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"08640FFC08040FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g20_b2_n_0
);
g20_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"084400440E040844"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g20_b3_n_0
);
g20_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"08C400C43C040044"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g20_b4_n_0
);
g20_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0F9C0FFC3FFC007C"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g20_b5_n_0
);
g20_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07180F3827F80038"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g20_b6_n_0
);
g21_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"03FC01FC07FC001C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g21_b0_n_0
);
g21_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"3E1E3E02"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g21_b1_n_0
);
g21_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0E00060008000804"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g21_b2_n_0
);
g21_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"03800C0008000FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g21_b3_n_0
);
g21_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0E0006000FFC0804"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g21_b5_n_0
);
g21_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC03FC07FC000C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g21_b6_n_0
);
g21_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"03FC01FC0000001C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g21_b7_n_0
);
g22_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000E1C001C0C0C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g22_b0_n_0
);
g22_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0C003C0E1C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g22_b1_n_0
);
g22_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC098408600330"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g22_b2_n_0
);
g22_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC08C40FC001E0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g22_b3_n_0
);
g22_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"080408640FC001E0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g22_b4_n_0
);
g22_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0804083408600330"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g22_b5_n_0
);
g22_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"00000C1C003C0E1C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g22_b6_n_0
);
g22_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"00000E0C001C0C0C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g22_b7_n_0
);
g23_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000800000038"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g23_b0_n_0
);
g23_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000C00000070"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g23_b1_n_0
);
g23_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"20000006080400E0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g23_b2_n_0
);
g23_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"20000003080401C0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g23_b3_n_0
);
g23_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"200000060FFC0380"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g23_b4_n_0
);
g23_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000C0FFC0700"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g23_b5_n_0
);
g23_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000800000E00"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g23_b6_n_0
);
g23_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g23_b7_n_0
);
g24_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07C0000407000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g24_b0_n_0
);
g24_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00FFC0FA00000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g24_b1_n_0
);
g24_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"08200FFC08A00003"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g24_b2_n_0
);
g24_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0820082008A00007"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g24_b3_n_0
);
g24_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0820086007E00004"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g24_b4_n_0
);
g24_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0C600FC00FC00000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g24_b5_n_0
);
g24_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0440078008000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g24_b6_n_0
);
g25_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"27C0084007C00780"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g25_b0_n_0
);
g25_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"6FE00FF80FE00FC0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g25_b1_n_0
);
g25_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"48200FFC08A00860"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g25_b2_n_0
);
g25_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"4820084408A00824"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g25_b3_n_0
);
g25_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"7FC0000C08A007FC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g25_b4_n_0
);
g25_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"3FE000180CE00FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g25_b5_n_0
);
g25_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000004C00800"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g25_b6_n_0
);
g26_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0804000000000804"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g26_b0_n_0
);
g26_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"3E40003E"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g26_b1_n_0
);
g26_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC700008200FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g26_b2_n_0
);
g26_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"018040000FEC0040"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g26_b3_n_0
);
g26_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03C040200FEC0020"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g26_b4_n_0
);
g26_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0E607FEC08000FE0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g26_b5_n_0
);
g26_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0C203FEC00000FC0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g26_b6_n_0
);
g27_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07C000200FE00000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g27_b0_n_0
);
g27_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00FE00FE00000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g27_b1_n_0
);
g27_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"08200FC000600804"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g27_b2_n_0
);
g27_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"082000200FC00FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g27_b3_n_0
);
g27_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00FE000600800"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g27_b5_n_0
);
g27_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07C00FC00FE00000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g27_b6_n_0
);
g27_b7: unisim.vcomponents.LUT5
generic map(
INIT => X"00003800"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g27_b7_n_0
);
g28_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0440082007C04020"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g28_b0_n_0
);
g28_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0CE00FE00FE07FE0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g28_b1_n_0
);
g28_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"09A00FC008207FC0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g28_b2_n_0
);
g28_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0920086048204820"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g28_b3_n_0
);
g28_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0B2000207FC00820"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g28_b4_n_0
);
g28_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0E6000E07FE00FE0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g28_b5_n_0
);
g28_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"044000C0402007C0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g28_b6_n_0
);
g29_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07E001E007E00020"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g29_b0_n_0
);
g29_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE003E00FE00020"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g29_b1_n_0
);
g29_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0C000600080007F8"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g29_b2_n_0
);
g29_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07000C0008000FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g29_b3_n_0
);
g29_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"07000C0007E00820"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g29_b4_n_0
);
g29_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0006000FE00C20"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g29_b5_n_0
);
g29_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE003E008000400"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g29_b6_n_0
);
g29_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"07E001E000000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g29_b7_n_0
);
g2_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0780FFFF0000FFFF"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g2_b0_n_0
);
g2_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"38E718FF"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g2_b1_n_0
);
g2_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0860F99F0660FE7F"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g2_b2_n_0
);
g2_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0874FBDF0420FC3F"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g2_b3_n_0
);
g2_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FDCFBDF0420FC3F"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g2_b4_n_0
);
g2_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"078CF99F0660FE7F"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g2_b5_n_0
);
g2_b6: unisim.vcomponents.LUT5
generic map(
INIT => X"06E718FF"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g2_b6_n_0
);
g2_b7: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \char[0]_i_1_n_0\,
O => g2_b7_n_0
);
g30_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000C6047E00820"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g30_b0_n_0
);
g30_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00400E604FE00C60"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g30_b1_n_0
);
g30_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"00400B20480006C0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g30_b2_n_0
);
g30_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07F809A048000380"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g30_b3_n_0
);
g30_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FBC08E068000380"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g30_b4_n_0
);
g30_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"08040C603FE006C0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g30_b5_n_0
);
g30_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"08040C201FE00C60"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g30_b6_n_0
);
g30_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000820"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g30_b7_n_0
);
g31_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0780000800000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g31_b0_n_0
);
g31_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"07C0000C08040000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g31_b1_n_0
);
g31_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0460000408040000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g31_b2_n_0
);
g31_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0430000C0FBC0FBC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g31_b3_n_0
);
g31_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0460000807F80FBC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g31_b4_n_0
);
g31_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"07C0000C00400000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g31_b5_n_0
);
g31_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0780000400400000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g31_b6_n_0
);
g3_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"02A01C000C000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b0_n_0
);
g3_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"02A01FFC0E000278"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b1_n_0
);
g3_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"01C00FFC0FFC02FC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g3_b2_n_0
);
g3_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0F78001407FC0F84"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g3_b3_n_0
);
g3_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0F78001400140F84"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g3_b4_n_0
);
g3_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"01C00E14001402FC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g3_b5_n_0
);
g3_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"02A00FFC001C0278"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b6_n_0
);
g3_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"02A007FC001C0000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b7_n_0
);
g4_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000400FFE"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g4_b0_n_0
);
g4_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC0110004007FC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g4_b1_n_0
);
g4_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC031800E003F8"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g4_b2_n_0
);
g4_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"000007FC01F001F0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g4_b3_n_0
);
g4_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"000007FC03F800E0"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g4_b4_n_0
);
g4_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC031807FC0040"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g4_b5_n_0
);
g4_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC01100FFE0040"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g4_b6_n_0
);
g5_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0008C40038"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g5_b0_n_0
);
g5_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"09100F0019EE007C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g5_b1_n_0
);
g5_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"1B180F00133A0044"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g5_b2_n_0
);
g5_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"1FFC0F0012120FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g5_b3_n_0
);
g5_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC0F0017320FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g5_b4_n_0
);
g5_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0B180F001DE60004"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g5_b5_n_0
);
g5_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"09100F0008C40FFC"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g5_b6_n_0
);
g5_b7: unisim.vcomponents.LUT5
generic map(
INIT => X"0000003E"
)
port map (
I0 => Y(1),
I1 => \v_count_reg[2]_rep_n_0\,
I2 => \v_count_reg[3]_rep_n_0\,
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g5_b7_n_0
);
g6_b0: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g6_b0_n_0
);
g6_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"01C0008002000010"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g6_b1_n_0
);
g6_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"03E0008006000018"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g6_b2_n_0
);
g6_b3: unisim.vcomponents.LUT5
generic map(
INIT => X"02A00FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_2_n_0,
O => g6_b3_n_0
);
g6_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"008003E00FFC0FFC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g6_b4_n_0
);
g6_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"008001C006000018"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g6_b5_n_0
);
g6_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0080008002000010"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g6_b6_n_0
);
g7_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00300600008003C0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b0_n_0
);
g7_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00F0078001C003C0"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b1_n_0
);
g7_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"03F007E003E00200"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g7_b2_n_0
);
g7_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07F007F000800200"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g7_b3_n_0
);
g7_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03F007E000800200"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g7_b4_n_0
);
g7_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"00F0078003E00200"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g7_b5_n_0
);
g7_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0030060001C00200"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b6_n_0
);
g7_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b7_n_0
);
g8_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0220000000000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g8_b0_n_0
);
g8_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FF8000E00000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g8_b1_n_0
);
g8_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FF8001E00380000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g8_b2_n_0
);
g8_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"022000000DFC0000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g8_b3_n_0
);
g8_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FF800000DFC0000"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g8_b4_n_0
);
g8_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0220000E00000000"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g8_b6_n_0
);
g9_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000007800C300638"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g9_b0_n_0
);
g9_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00100FD806300C7C"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g9_b1_n_0
);
g9_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"001E087C03000844"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g9_b2_n_0
);
g9_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"000E08E401803847"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g9_b3_n_0
);
g9_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"000007BC00C03847"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g9_b4_n_0
);
g9_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"00000FD80C600FCC"
)
port map (
I0 => Y(0),
I1 => \v_count_reg[1]_rep_n_0\,
I2 => Y(2),
I3 => \v_count_reg[3]_rep__0_n_0\,
I4 => g0_b2_i_1_n_0,
I5 => g0_b2_i_2_n_0,
O => g9_b5_n_0
);
g9_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"000008400C300798"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => \v_count_reg[3]_rep_n_0\,
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g9_b6_n_0
);
hSync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAFFAFC0"
)
port map (
I0 => hSync_i_2_n_0,
I1 => \h_count_reg__0\(4),
I2 => \h_count_reg__0\(5),
I3 => \h_count_reg__0\(7),
I4 => \h_count_reg__0\(6),
I5 => hSync_i_3_n_0,
O => hSync_i_1_n_0
);
hSync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => X(2),
I1 => X(0),
I2 => X(1),
I3 => \h_count_reg__0\(3),
I4 => \h_count_reg__0\(4),
I5 => \h_count_reg__0\(6),
O => hSync_i_2_n_0
);
hSync_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => \h_count_reg__0\(9),
I1 => \h_count_reg__0\(8),
I2 => \h_count_reg__0\(10),
O => hSync_i_3_n_0
);
hSync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => hSync_i_1_n_0,
Q => Hsync_OBUF,
R => '0'
);
\h_count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => X(0),
O => p_0_in(0)
);
\h_count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => X(0),
I1 => X(1),
O => p_0_in(1)
);
\h_count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => X(2),
I1 => X(1),
I2 => X(0),
O => \h_count[2]_i_1_n_0\
);
\h_count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => p_0_in(0),
Q => X(0),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_12_n_0,
Q => \h_count_reg__0\(10),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => p_0_in(1),
Q => X(1),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[2]_i_1_n_0\,
Q => X(2),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_19_n_0,
Q => \h_count_reg__0\(3),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_18_n_0,
Q => \h_count_reg__0\(4),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_17_n_0,
Q => \h_count_reg__0\(5),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_16_n_0,
Q => \h_count_reg__0\(6),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_15_n_0,
Q => \h_count_reg__0\(7),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_14_n_0,
Q => \h_count_reg__0\(8),
R => fbOutAddr_reg_i_1_n_0
);
\h_count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => fbOutAddr_reg_i_13_n_0,
Q => \h_count_reg__0\(9),
R => fbOutAddr_reg_i_1_n_0
);
\nextChar[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => X(1),
I1 => X(0),
I2 => enable,
I3 => X(2),
O => \nextChar[7]_i_1_n_0\
);
\nextChar_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(0),
Q => nextChar(0),
R => '0'
);
\nextChar_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(1),
Q => nextChar(1),
R => '0'
);
\nextChar_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(2),
Q => nextChar(2),
R => '0'
);
\nextChar_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(3),
Q => nextChar(3),
R => '0'
);
\nextChar_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(4),
Q => nextChar(4),
R => '0'
);
\nextChar_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(5),
Q => nextChar(5),
R => '0'
);
\nextChar_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(6),
Q => nextChar(6),
R => '0'
);
\nextChar_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \nextChar[7]_i_1_n_0\,
D => D(7),
Q => nextChar(7),
R => '0'
);
vSync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000001E"
)
port map (
I0 => \v_count_reg[0]_rep_n_0\,
I1 => Y(1),
I2 => \v_count_reg[2]_rep_n_0\,
I3 => vSync_i_2_n_0,
I4 => fbOutAddr_reg_i_23_n_0,
O => vSync_i_1_n_0
);
vSync_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => \v_count_reg__0\(4),
I1 => Y(3),
I2 => \v_count_reg__0\(10),
I3 => \v_count_reg__0\(5),
O => vSync_i_2_n_0
);
vSync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => vSync_i_1_n_0,
Q => Vsync_OBUF,
R => '0'
);
\v_count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Y(0),
O => \p_0_in__0\(0)
);
\v_count[0]_rep_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Y(0),
O => \v_count[0]_rep_i_1_n_0\
);
\v_count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Y(0),
I1 => Y(1),
O => \p_0_in__0\(1)
);
\v_count[1]_rep_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Y(0),
I1 => Y(1),
O => \v_count[1]_rep_i_1_n_0\
);
\v_count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => Y(2),
I1 => Y(0),
I2 => Y(1),
O => \p_0_in__0\(2)
);
\v_count[2]_rep_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => Y(2),
I1 => Y(0),
I2 => Y(1),
O => \v_count[2]_rep_i_1_n_0\
);
\v_count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => Y(3),
I1 => Y(1),
I2 => Y(0),
I3 => Y(2),
O => \p_0_in__0\(3)
);
\v_count[3]_rep__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => Y(3),
I1 => Y(1),
I2 => Y(0),
I3 => Y(2),
O => \v_count[3]_rep__0_i_1_n_0\
);
\v_count[3]_rep_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => Y(3),
I1 => Y(1),
I2 => Y(0),
I3 => Y(2),
O => \v_count[3]_rep_i_1_n_0\
);
\v_count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \p_0_in__0\(0),
Q => Y(0),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \v_count[0]_rep_i_1_n_0\,
Q => \v_count_reg[0]_rep_n_0\,
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => fbOutAddr_reg_i_5_n_0,
Q => \v_count_reg__0\(10),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \p_0_in__0\(1),
Q => Y(1),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \v_count[1]_rep_i_1_n_0\,
Q => \v_count_reg[1]_rep_n_0\,
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \p_0_in__0\(2),
Q => Y(2),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[2]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \v_count[2]_rep_i_1_n_0\,
Q => \v_count_reg[2]_rep_n_0\,
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \p_0_in__0\(3),
Q => Y(3),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[3]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \v_count[3]_rep_i_1_n_0\,
Q => \v_count_reg[3]_rep_n_0\,
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[3]_rep__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => \v_count[3]_rep__0_i_1_n_0\,
Q => \v_count_reg[3]_rep__0_n_0\,
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => fbOutAddr_reg_i_11_n_0,
Q => \v_count_reg__0\(4),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => fbOutAddr_reg_i_10_n_0,
Q => \v_count_reg__0\(5),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => fbOutAddr_reg_i_9_n_0,
Q => \v_count_reg__0\(6),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => fbOutAddr_reg_i_8_n_0,
Q => \v_count_reg__0\(7),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => fbOutAddr_reg_i_7_n_0,
Q => \v_count_reg__0\(8),
R => fbOutAddr_reg_i_3_n_0
);
\v_count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => fbOutAddr_reg_i_1_n_0,
D => fbOutAddr_reg_i_6_n_0,
Q => \v_count_reg__0\(9),
R => fbOutAddr_reg_i_3_n_0
);
\vgaRed[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"28222888"
)
port map (
I0 => enable,
I1 => \char[7]_i_1_n_0\,
I2 => \vgaRed_reg[0]_i_2_n_0\,
I3 => X(2),
I4 => \vgaRed_reg[0]_i_3_n_0\,
O => \vgaRed[0]_i_1_n_0\
);
\vgaRed[0]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_32_n_0\,
I1 => \vgaRed[0]_i_33_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed[0]_i_34_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_35_n_0\,
O => \vgaRed[0]_i_10_n_0\
);
\vgaRed[0]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_36_n_0\,
I1 => \vgaRed_reg[0]_i_37_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_38_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_39_n_0\,
O => \vgaRed[0]_i_11_n_0\
);
\vgaRed[0]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200000"
)
port map (
I0 => g10_b0_n_0,
I1 => \char[2]_i_1_n_0\,
I2 => \char[3]_i_1_n_0\,
I3 => \char[4]_i_1_n_0\,
I4 => \char[5]_i_1_n_0\,
I5 => \vgaRed[0]_i_42_n_0\,
O => \vgaRed[0]_i_13_n_0\
);
\vgaRed[0]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_43_n_0\,
I1 => \vgaRed_reg[0]_i_44_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_45_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_46_n_0\,
O => \vgaRed[0]_i_14_n_0\
);
\vgaRed[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_47_n_0\,
I1 => \vgaRed[0]_i_48_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_49_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_50_n_0\,
O => \vgaRed[0]_i_15_n_0\
);
\vgaRed[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_51_n_0\,
I1 => \vgaRed_reg[0]_i_52_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_53_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_54_n_0\,
O => \vgaRed[0]_i_16_n_0\
);
\vgaRed[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_55_n_0\,
I1 => \vgaRed[0]_i_56_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_57_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_58_n_0\,
O => \vgaRed[0]_i_17_n_0\
);
\vgaRed[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_59_n_0\,
I1 => \vgaRed_reg[0]_i_60_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_61_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_62_n_0\,
O => \vgaRed[0]_i_18_n_0\
);
\vgaRed[0]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_63_n_0\,
I1 => \vgaRed[0]_i_64_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_65_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_66_n_0\,
O => \vgaRed[0]_i_19_n_0\
);
\vgaRed[0]_i_20\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_67_n_0\,
I1 => \vgaRed[0]_i_68_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed[0]_i_69_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_70_n_0\,
O => \vgaRed[0]_i_20_n_0\
);
\vgaRed[0]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_71_n_0\,
I1 => \vgaRed_reg[0]_i_72_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_73_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_74_n_0\,
O => \vgaRed[0]_i_21_n_0\
);
\vgaRed[0]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_75_n_0\,
I1 => \vgaRed_reg[0]_i_76_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_77_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_78_n_0\,
O => \vgaRed[0]_i_22_n_0\
);
\vgaRed[0]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_79_n_0\,
I1 => \vgaRed[0]_i_80_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_81_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_82_n_0\,
O => \vgaRed[0]_i_23_n_0\
);
\vgaRed[0]_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b5_n_0,
I1 => g10_b5_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b5_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b2_n_0,
O => \vgaRed[0]_i_29_n_0\
);
\vgaRed[0]_i_33\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g27_b3_n_0,
I1 => g26_b4_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g25_b4_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g24_b4_n_0,
O => \vgaRed[0]_i_33_n_0\
);
\vgaRed[0]_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g23_b4_n_0,
I1 => g22_b4_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g21_b3_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g20_b4_n_0,
O => \vgaRed[0]_i_34_n_0\
);
\vgaRed[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed[0]_i_8_n_0\,
I1 => \vgaRed[0]_i_9_n_0\,
I2 => X(0),
I3 => \vgaRed[0]_i_10_n_0\,
I4 => \char[6]_i_1_n_0\,
I5 => \vgaRed[0]_i_11_n_0\,
O => \vgaRed[0]_i_4_n_0\
);
\vgaRed[0]_i_40\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFC0A0C0A000A000"
)
port map (
I0 => \vgaRed_reg[0]_i_109_n_0\,
I1 => g21_b7_n_0,
I2 => \char[4]_i_1_n_0\,
I3 => \char[3]_i_1_n_0\,
I4 => g19_b7_n_0,
I5 => \char[2]_i_1_n_0\,
O => \vgaRed[0]_i_40_n_0\
);
\vgaRed[0]_i_41\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FC000C0A000A000"
)
port map (
I0 => g30_b7_n_0,
I1 => g29_b7_n_0,
I2 => \char[4]_i_1_n_0\,
I3 => \char[3]_i_1_n_0\,
I4 => g27_b7_n_0,
I5 => \char[2]_i_1_n_0\,
O => \vgaRed[0]_i_41_n_0\
);
\vgaRed[0]_i_42\: unisim.vcomponents.LUT6
generic map(
INIT => X"B080FFFFB0800000"
)
port map (
I0 => g7_b7_n_0,
I1 => \char[3]_i_1_n_0\,
I2 => \char[2]_i_1_n_0\,
I3 => g5_b7_n_0,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_110_n_0\,
O => \vgaRed[0]_i_42_n_0\
);
\vgaRed[0]_i_48\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b6_n_0,
I1 => g10_b1_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b6_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b6_n_0,
O => \vgaRed[0]_i_48_n_0\
);
\vgaRed[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_12_n_0\,
I1 => \vgaRed[0]_i_13_n_0\,
I2 => X(0),
I3 => \vgaRed[0]_i_14_n_0\,
I4 => \char[6]_i_1_n_0\,
I5 => \vgaRed[0]_i_15_n_0\,
O => \vgaRed[0]_i_5_n_0\
);
\vgaRed[0]_i_56\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b1_n_0,
I1 => g10_b1_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b1_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b1_n_0,
O => \vgaRed[0]_i_56_n_0\
);
\vgaRed[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed[0]_i_16_n_0\,
I1 => \vgaRed[0]_i_17_n_0\,
I2 => X(0),
I3 => \vgaRed[0]_i_18_n_0\,
I4 => \char[6]_i_1_n_0\,
I5 => \vgaRed[0]_i_19_n_0\,
O => \vgaRed[0]_i_6_n_0\
);
\vgaRed[0]_i_64\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b0_n_0,
I1 => g10_b0_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b0_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b0_n_0,
O => \vgaRed[0]_i_64_n_0\
);
\vgaRed[0]_i_68\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g27_b3_n_0,
I1 => g26_b3_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g25_b3_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g24_b3_n_0,
O => \vgaRed[0]_i_68_n_0\
);
\vgaRed[0]_i_69\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g23_b3_n_0,
I1 => g22_b3_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g21_b3_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g20_b3_n_0,
O => \vgaRed[0]_i_69_n_0\
);
\vgaRed[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed[0]_i_20_n_0\,
I1 => \vgaRed[0]_i_21_n_0\,
I2 => X(0),
I3 => \vgaRed[0]_i_22_n_0\,
I4 => \char[6]_i_1_n_0\,
I5 => \vgaRed[0]_i_23_n_0\,
O => \vgaRed[0]_i_7_n_0\
);
\vgaRed[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_24_n_0\,
I1 => \vgaRed_reg[0]_i_25_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_26_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_27_n_0\,
O => \vgaRed[0]_i_8_n_0\
);
\vgaRed[0]_i_80\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b2_n_0,
I1 => g10_b2_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b2_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b2_n_0,
O => \vgaRed[0]_i_80_n_0\
);
\vgaRed[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_28_n_0\,
I1 => \vgaRed[0]_i_29_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_30_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_31_n_0\,
O => \vgaRed[0]_i_9_n_0\
);
\vgaRed_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \vgaRed[0]_i_1_n_0\,
Q => vgaBlue_OBUF(0),
R => '0'
);
\vgaRed_reg[0]_i_100\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b4_n_0,
I1 => g19_b4_n_0,
O => \vgaRed_reg[0]_i_100_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_101\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b4_n_0,
I1 => g13_b4_n_0,
O => \vgaRed_reg[0]_i_101_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_102\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b4_n_0,
I1 => g15_b4_n_0,
O => \vgaRed_reg[0]_i_102_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_103\: unisim.vcomponents.MUXF7
port map (
I0 => g8_b4_n_0,
I1 => g9_b4_n_0,
O => \vgaRed_reg[0]_i_103_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_104\: unisim.vcomponents.MUXF7
port map (
I0 => g10_b4_n_0,
I1 => g11_b4_n_0,
O => \vgaRed_reg[0]_i_104_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_105\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b4_n_0,
I1 => g5_b4_n_0,
O => \vgaRed_reg[0]_i_105_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_106\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b4_n_0,
I1 => g7_b4_n_0,
O => \vgaRed_reg[0]_i_106_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_107\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b4_n_0,
I1 => g1_b4_n_0,
O => \vgaRed_reg[0]_i_107_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_108\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b4_n_0,
I1 => g3_b4_n_0,
O => \vgaRed_reg[0]_i_108_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_109\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b7_n_0,
I1 => g23_b7_n_0,
O => \vgaRed_reg[0]_i_109_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_110\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_179_n_0\,
I1 => \vgaRed_reg[0]_i_180_n_0\,
O => \vgaRed_reg[0]_i_110_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_111\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b6_n_0,
I1 => g29_b6_n_0,
O => \vgaRed_reg[0]_i_111_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_112\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b6_n_0,
I1 => g31_b6_n_0,
O => \vgaRed_reg[0]_i_112_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_113\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b6_n_0,
I1 => g25_b6_n_0,
O => \vgaRed_reg[0]_i_113_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_114\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b6_n_0,
I1 => g27_b6_n_0,
O => \vgaRed_reg[0]_i_114_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_115\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b6_n_0,
I1 => g21_b6_n_0,
O => \vgaRed_reg[0]_i_115_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_116\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b6_n_0,
I1 => g23_b6_n_0,
O => \vgaRed_reg[0]_i_116_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_117\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b6_n_0,
I1 => g17_b6_n_0,
O => \vgaRed_reg[0]_i_117_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_118\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b6_n_0,
I1 => g19_b6_n_0,
O => \vgaRed_reg[0]_i_118_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_119\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b6_n_0,
I1 => g13_b6_n_0,
O => \vgaRed_reg[0]_i_119_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_12\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_40_n_0\,
I1 => \vgaRed[0]_i_41_n_0\,
O => \vgaRed_reg[0]_i_12_n_0\,
S => \char[5]_i_1_n_0\
);
\vgaRed_reg[0]_i_120\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b6_n_0,
I1 => g15_b6_n_0,
O => \vgaRed_reg[0]_i_120_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_121\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b6_n_0,
I1 => g5_b6_n_0,
O => \vgaRed_reg[0]_i_121_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_122\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b6_n_0,
I1 => g7_b6_n_0,
O => \vgaRed_reg[0]_i_122_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_123\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b6_n_0,
I1 => g1_b6_n_0,
O => \vgaRed_reg[0]_i_123_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_124\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b6_n_0,
I1 => g3_b6_n_0,
O => \vgaRed_reg[0]_i_124_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_125\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b1_n_0,
I1 => g29_b1_n_0,
O => \vgaRed_reg[0]_i_125_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_126\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b1_n_0,
I1 => g31_b1_n_0,
O => \vgaRed_reg[0]_i_126_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_127\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b1_n_0,
I1 => g25_b1_n_0,
O => \vgaRed_reg[0]_i_127_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_128\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b1_n_0,
I1 => g27_b1_n_0,
O => \vgaRed_reg[0]_i_128_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_129\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b1_n_0,
I1 => g21_b1_n_0,
O => \vgaRed_reg[0]_i_129_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_130\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b1_n_0,
I1 => g23_b1_n_0,
O => \vgaRed_reg[0]_i_130_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_131\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b1_n_0,
I1 => g17_b1_n_0,
O => \vgaRed_reg[0]_i_131_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_132\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b1_n_0,
I1 => g19_b1_n_0,
O => \vgaRed_reg[0]_i_132_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_133\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b1_n_0,
I1 => g13_b1_n_0,
O => \vgaRed_reg[0]_i_133_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_134\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b1_n_0,
I1 => g15_b1_n_0,
O => \vgaRed_reg[0]_i_134_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_135\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b1_n_0,
I1 => g5_b1_n_0,
O => \vgaRed_reg[0]_i_135_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_136\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b1_n_0,
I1 => g7_b1_n_0,
O => \vgaRed_reg[0]_i_136_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_137\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b1_n_0,
I1 => g1_b1_n_0,
O => \vgaRed_reg[0]_i_137_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_138\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b1_n_0,
I1 => g3_b1_n_0,
O => \vgaRed_reg[0]_i_138_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_139\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b0_n_0,
I1 => g29_b0_n_0,
O => \vgaRed_reg[0]_i_139_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_140\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b0_n_0,
I1 => g31_b0_n_0,
O => \vgaRed_reg[0]_i_140_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_141\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b0_n_0,
I1 => g25_b0_n_0,
O => \vgaRed_reg[0]_i_141_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_142\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b0_n_0,
I1 => g27_b0_n_0,
O => \vgaRed_reg[0]_i_142_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_143\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b0_n_0,
I1 => g21_b0_n_0,
O => \vgaRed_reg[0]_i_143_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_144\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b0_n_0,
I1 => g23_b0_n_0,
O => \vgaRed_reg[0]_i_144_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_145\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b0_n_0,
I1 => g17_b0_n_0,
O => \vgaRed_reg[0]_i_145_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_146\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b0_n_0,
I1 => g19_b0_n_0,
O => \vgaRed_reg[0]_i_146_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_147\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b0_n_0,
I1 => g13_b0_n_0,
O => \vgaRed_reg[0]_i_147_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_148\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b0_n_0,
I1 => g15_b0_n_0,
O => \vgaRed_reg[0]_i_148_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_149\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b0_n_0,
I1 => g5_b0_n_0,
O => \vgaRed_reg[0]_i_149_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_150\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b0_n_0,
I1 => g7_b0_n_0,
O => \vgaRed_reg[0]_i_150_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_151\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b0_n_0,
I1 => g1_b0_n_0,
O => \vgaRed_reg[0]_i_151_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_152\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b0_n_0,
I1 => g3_b0_n_0,
O => \vgaRed_reg[0]_i_152_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_153\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b3_n_0,
I1 => g29_b3_n_0,
O => \vgaRed_reg[0]_i_153_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_154\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b3_n_0,
I1 => g31_b3_n_0,
O => \vgaRed_reg[0]_i_154_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_155\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b3_n_0,
I1 => g17_b3_n_0,
O => \vgaRed_reg[0]_i_155_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_156\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b3_n_0,
I1 => g19_b3_n_0,
O => \vgaRed_reg[0]_i_156_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_157\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b3_n_0,
I1 => g13_b3_n_0,
O => \vgaRed_reg[0]_i_157_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_158\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b3_n_0,
I1 => g15_b3_n_0,
O => \vgaRed_reg[0]_i_158_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_159\: unisim.vcomponents.MUXF7
port map (
I0 => g8_b3_n_0,
I1 => g9_b3_n_0,
O => \vgaRed_reg[0]_i_159_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_160\: unisim.vcomponents.MUXF7
port map (
I0 => g10_b3_n_0,
I1 => g11_b3_n_0,
O => \vgaRed_reg[0]_i_160_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_161\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b3_n_0,
I1 => g5_b3_n_0,
O => \vgaRed_reg[0]_i_161_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_162\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b3_n_0,
I1 => g7_b3_n_0,
O => \vgaRed_reg[0]_i_162_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_163\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b3_n_0,
I1 => g1_b3_n_0,
O => \vgaRed_reg[0]_i_163_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_164\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b3_n_0,
I1 => g3_b3_n_0,
O => \vgaRed_reg[0]_i_164_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_165\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b2_n_0,
I1 => g29_b2_n_0,
O => \vgaRed_reg[0]_i_165_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_166\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b2_n_0,
I1 => g31_b2_n_0,
O => \vgaRed_reg[0]_i_166_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_167\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b2_n_0,
I1 => g25_b2_n_0,
O => \vgaRed_reg[0]_i_167_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_168\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b2_n_0,
I1 => g27_b2_n_0,
O => \vgaRed_reg[0]_i_168_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_169\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b2_n_0,
I1 => g21_b2_n_0,
O => \vgaRed_reg[0]_i_169_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_170\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b2_n_0,
I1 => g23_b2_n_0,
O => \vgaRed_reg[0]_i_170_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_171\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b2_n_0,
I1 => g17_b2_n_0,
O => \vgaRed_reg[0]_i_171_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_172\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b2_n_0,
I1 => g19_b2_n_0,
O => \vgaRed_reg[0]_i_172_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_173\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b2_n_0,
I1 => g13_b2_n_0,
O => \vgaRed_reg[0]_i_173_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_174\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b2_n_0,
I1 => g15_b2_n_0,
O => \vgaRed_reg[0]_i_174_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_175\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b2_n_0,
I1 => g5_b2_n_0,
O => \vgaRed_reg[0]_i_175_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_176\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b2_n_0,
I1 => g7_b2_n_0,
O => \vgaRed_reg[0]_i_176_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_177\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b2_n_0,
I1 => g1_b2_n_0,
O => \vgaRed_reg[0]_i_177_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_178\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b2_n_0,
I1 => g3_b2_n_0,
O => \vgaRed_reg[0]_i_178_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_179\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b7_n_0,
I1 => g1_b7_n_0,
O => \vgaRed_reg[0]_i_179_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_180\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b7_n_0,
I1 => g3_b7_n_0,
O => \vgaRed_reg[0]_i_180_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_4_n_0\,
I1 => \vgaRed[0]_i_5_n_0\,
O => \vgaRed_reg[0]_i_2_n_0\,
S => X(1)
);
\vgaRed_reg[0]_i_24\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_83_n_0\,
I1 => \vgaRed_reg[0]_i_84_n_0\,
O => \vgaRed_reg[0]_i_24_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_25\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_85_n_0\,
I1 => \vgaRed_reg[0]_i_86_n_0\,
O => \vgaRed_reg[0]_i_25_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_26\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_87_n_0\,
I1 => \vgaRed_reg[0]_i_88_n_0\,
O => \vgaRed_reg[0]_i_26_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_27\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_89_n_0\,
I1 => \vgaRed_reg[0]_i_90_n_0\,
O => \vgaRed_reg[0]_i_27_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_28\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_91_n_0\,
I1 => \vgaRed_reg[0]_i_92_n_0\,
O => \vgaRed_reg[0]_i_28_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_6_n_0\,
I1 => \vgaRed[0]_i_7_n_0\,
O => \vgaRed_reg[0]_i_3_n_0\,
S => X(1)
);
\vgaRed_reg[0]_i_30\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_93_n_0\,
I1 => \vgaRed_reg[0]_i_94_n_0\,
O => \vgaRed_reg[0]_i_30_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_31\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_95_n_0\,
I1 => \vgaRed_reg[0]_i_96_n_0\,
O => \vgaRed_reg[0]_i_31_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_32\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_97_n_0\,
I1 => \vgaRed_reg[0]_i_98_n_0\,
O => \vgaRed_reg[0]_i_32_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_35\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_99_n_0\,
I1 => \vgaRed_reg[0]_i_100_n_0\,
O => \vgaRed_reg[0]_i_35_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_36\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_101_n_0\,
I1 => \vgaRed_reg[0]_i_102_n_0\,
O => \vgaRed_reg[0]_i_36_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_37\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_103_n_0\,
I1 => \vgaRed_reg[0]_i_104_n_0\,
O => \vgaRed_reg[0]_i_37_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_38\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_105_n_0\,
I1 => \vgaRed_reg[0]_i_106_n_0\,
O => \vgaRed_reg[0]_i_38_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_39\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_107_n_0\,
I1 => \vgaRed_reg[0]_i_108_n_0\,
O => \vgaRed_reg[0]_i_39_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_43\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_111_n_0\,
I1 => \vgaRed_reg[0]_i_112_n_0\,
O => \vgaRed_reg[0]_i_43_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_44\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_113_n_0\,
I1 => \vgaRed_reg[0]_i_114_n_0\,
O => \vgaRed_reg[0]_i_44_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_45\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_115_n_0\,
I1 => \vgaRed_reg[0]_i_116_n_0\,
O => \vgaRed_reg[0]_i_45_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_46\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_117_n_0\,
I1 => \vgaRed_reg[0]_i_118_n_0\,
O => \vgaRed_reg[0]_i_46_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_47\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_119_n_0\,
I1 => \vgaRed_reg[0]_i_120_n_0\,
O => \vgaRed_reg[0]_i_47_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_49\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_121_n_0\,
I1 => \vgaRed_reg[0]_i_122_n_0\,
O => \vgaRed_reg[0]_i_49_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_50\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_123_n_0\,
I1 => \vgaRed_reg[0]_i_124_n_0\,
O => \vgaRed_reg[0]_i_50_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_51\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_125_n_0\,
I1 => \vgaRed_reg[0]_i_126_n_0\,
O => \vgaRed_reg[0]_i_51_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_52\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_127_n_0\,
I1 => \vgaRed_reg[0]_i_128_n_0\,
O => \vgaRed_reg[0]_i_52_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_53\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_129_n_0\,
I1 => \vgaRed_reg[0]_i_130_n_0\,
O => \vgaRed_reg[0]_i_53_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_54\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_131_n_0\,
I1 => \vgaRed_reg[0]_i_132_n_0\,
O => \vgaRed_reg[0]_i_54_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_55\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_133_n_0\,
I1 => \vgaRed_reg[0]_i_134_n_0\,
O => \vgaRed_reg[0]_i_55_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_57\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_135_n_0\,
I1 => \vgaRed_reg[0]_i_136_n_0\,
O => \vgaRed_reg[0]_i_57_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_58\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_137_n_0\,
I1 => \vgaRed_reg[0]_i_138_n_0\,
O => \vgaRed_reg[0]_i_58_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_59\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_139_n_0\,
I1 => \vgaRed_reg[0]_i_140_n_0\,
O => \vgaRed_reg[0]_i_59_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_60\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_141_n_0\,
I1 => \vgaRed_reg[0]_i_142_n_0\,
O => \vgaRed_reg[0]_i_60_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_61\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_143_n_0\,
I1 => \vgaRed_reg[0]_i_144_n_0\,
O => \vgaRed_reg[0]_i_61_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_62\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_145_n_0\,
I1 => \vgaRed_reg[0]_i_146_n_0\,
O => \vgaRed_reg[0]_i_62_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_63\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_147_n_0\,
I1 => \vgaRed_reg[0]_i_148_n_0\,
O => \vgaRed_reg[0]_i_63_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_65\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_149_n_0\,
I1 => \vgaRed_reg[0]_i_150_n_0\,
O => \vgaRed_reg[0]_i_65_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_66\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_151_n_0\,
I1 => \vgaRed_reg[0]_i_152_n_0\,
O => \vgaRed_reg[0]_i_66_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_67\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_153_n_0\,
I1 => \vgaRed_reg[0]_i_154_n_0\,
O => \vgaRed_reg[0]_i_67_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_70\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_155_n_0\,
I1 => \vgaRed_reg[0]_i_156_n_0\,
O => \vgaRed_reg[0]_i_70_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_71\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_157_n_0\,
I1 => \vgaRed_reg[0]_i_158_n_0\,
O => \vgaRed_reg[0]_i_71_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_72\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_159_n_0\,
I1 => \vgaRed_reg[0]_i_160_n_0\,
O => \vgaRed_reg[0]_i_72_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_73\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_161_n_0\,
I1 => \vgaRed_reg[0]_i_162_n_0\,
O => \vgaRed_reg[0]_i_73_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_74\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_163_n_0\,
I1 => \vgaRed_reg[0]_i_164_n_0\,
O => \vgaRed_reg[0]_i_74_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_75\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_165_n_0\,
I1 => \vgaRed_reg[0]_i_166_n_0\,
O => \vgaRed_reg[0]_i_75_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_76\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_167_n_0\,
I1 => \vgaRed_reg[0]_i_168_n_0\,
O => \vgaRed_reg[0]_i_76_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_77\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_169_n_0\,
I1 => \vgaRed_reg[0]_i_170_n_0\,
O => \vgaRed_reg[0]_i_77_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_78\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_171_n_0\,
I1 => \vgaRed_reg[0]_i_172_n_0\,
O => \vgaRed_reg[0]_i_78_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_79\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_173_n_0\,
I1 => \vgaRed_reg[0]_i_174_n_0\,
O => \vgaRed_reg[0]_i_79_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_81\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_175_n_0\,
I1 => \vgaRed_reg[0]_i_176_n_0\,
O => \vgaRed_reg[0]_i_81_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_82\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_177_n_0\,
I1 => \vgaRed_reg[0]_i_178_n_0\,
O => \vgaRed_reg[0]_i_82_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_83\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b5_n_0,
I1 => g29_b5_n_0,
O => \vgaRed_reg[0]_i_83_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_84\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b5_n_0,
I1 => g31_b5_n_0,
O => \vgaRed_reg[0]_i_84_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_85\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b5_n_0,
I1 => g25_b5_n_0,
O => \vgaRed_reg[0]_i_85_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_86\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b5_n_0,
I1 => g27_b5_n_0,
O => \vgaRed_reg[0]_i_86_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_87\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b5_n_0,
I1 => g21_b5_n_0,
O => \vgaRed_reg[0]_i_87_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_88\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b5_n_0,
I1 => g23_b5_n_0,
O => \vgaRed_reg[0]_i_88_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_89\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b5_n_0,
I1 => g17_b5_n_0,
O => \vgaRed_reg[0]_i_89_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_90\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b5_n_0,
I1 => g19_b5_n_0,
O => \vgaRed_reg[0]_i_90_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_91\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b5_n_0,
I1 => g13_b5_n_0,
O => \vgaRed_reg[0]_i_91_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_92\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b5_n_0,
I1 => g15_b5_n_0,
O => \vgaRed_reg[0]_i_92_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_93\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b5_n_0,
I1 => g5_b5_n_0,
O => \vgaRed_reg[0]_i_93_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_94\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b5_n_0,
I1 => g7_b5_n_0,
O => \vgaRed_reg[0]_i_94_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_95\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b5_n_0,
I1 => g1_b5_n_0,
O => \vgaRed_reg[0]_i_95_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_96\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b5_n_0,
I1 => g3_b5_n_0,
O => \vgaRed_reg[0]_i_96_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_97\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b4_n_0,
I1 => g29_b4_n_0,
O => \vgaRed_reg[0]_i_97_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_98\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b4_n_0,
I1 => g31_b4_n_0,
O => \vgaRed_reg[0]_i_98_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_99\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b4_n_0,
I1 => g17_b4_n_0,
O => \vgaRed_reg[0]_i_99_n_0\,
S => \char[2]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ps2_keyboard is
port (
ps2_code_new : out STD_LOGIC;
break_reg : out STD_LOGIC;
shift_l_reg : out STD_LOGIC;
shift_r_reg : out STD_LOGIC;
e0_code_reg : out STD_LOGIC;
control_r_reg : out STD_LOGIC;
control_l_reg : out STD_LOGIC;
caps_lock_reg : out STD_LOGIC;
\ascii_reg[7]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\ascii_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
PS2Clk_IBUF : in STD_LOGIC;
clk_BUFG : in STD_LOGIC;
PS2Data_IBUF : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
break : in STD_LOGIC;
shift_l : in STD_LOGIC;
shift_r : in STD_LOGIC;
e0_code : in STD_LOGIC;
control_r_reg_0 : in STD_LOGIC;
control_l_reg_0 : in STD_LOGIC;
caps_lock_reg_0 : in STD_LOGIC;
\ascii_reg[7]_0\ : in STD_LOGIC;
prev_ps2_code_new : in STD_LOGIC
);
end ps2_keyboard;
architecture STRUCTURE of ps2_keyboard is
signal \ascii[0]_i_10_n_0\ : STD_LOGIC;
signal \ascii[0]_i_11_n_0\ : STD_LOGIC;
signal \ascii[0]_i_2_n_0\ : STD_LOGIC;
signal \ascii[0]_i_3_n_0\ : STD_LOGIC;
signal \ascii[0]_i_4_n_0\ : STD_LOGIC;
signal \ascii[0]_i_5_n_0\ : STD_LOGIC;
signal \ascii[0]_i_6_n_0\ : STD_LOGIC;
signal \ascii[0]_i_8_n_0\ : STD_LOGIC;
signal \ascii[0]_i_9_n_0\ : STD_LOGIC;
signal \ascii[1]_i_2_n_0\ : STD_LOGIC;
signal \ascii[1]_i_3_n_0\ : STD_LOGIC;
signal \ascii[1]_i_4_n_0\ : STD_LOGIC;
signal \ascii[1]_i_5_n_0\ : STD_LOGIC;
signal \ascii[1]_i_6_n_0\ : STD_LOGIC;
signal \ascii[1]_i_7_n_0\ : STD_LOGIC;
signal \ascii[1]_i_8_n_0\ : STD_LOGIC;
signal \ascii[1]_i_9_n_0\ : STD_LOGIC;
signal \ascii[2]_i_10_n_0\ : STD_LOGIC;
signal \ascii[2]_i_11_n_0\ : STD_LOGIC;
signal \ascii[2]_i_12_n_0\ : STD_LOGIC;
signal \ascii[2]_i_3_n_0\ : STD_LOGIC;
signal \ascii[2]_i_4_n_0\ : STD_LOGIC;
signal \ascii[2]_i_5_n_0\ : STD_LOGIC;
signal \ascii[2]_i_6_n_0\ : STD_LOGIC;
signal \ascii[2]_i_7_n_0\ : STD_LOGIC;
signal \ascii[2]_i_9_n_0\ : STD_LOGIC;
signal \ascii[3]_i_10_n_0\ : STD_LOGIC;
signal \ascii[3]_i_3_n_0\ : STD_LOGIC;
signal \ascii[3]_i_4_n_0\ : STD_LOGIC;
signal \ascii[3]_i_5_n_0\ : STD_LOGIC;
signal \ascii[3]_i_6_n_0\ : STD_LOGIC;
signal \ascii[3]_i_7_n_0\ : STD_LOGIC;
signal \ascii[3]_i_8_n_0\ : STD_LOGIC;
signal \ascii[3]_i_9_n_0\ : STD_LOGIC;
signal \ascii[4]_i_10_n_0\ : STD_LOGIC;
signal \ascii[4]_i_2_n_0\ : STD_LOGIC;
signal \ascii[4]_i_3_n_0\ : STD_LOGIC;
signal \ascii[4]_i_4_n_0\ : STD_LOGIC;
signal \ascii[4]_i_5_n_0\ : STD_LOGIC;
signal \ascii[4]_i_7_n_0\ : STD_LOGIC;
signal \ascii[4]_i_8_n_0\ : STD_LOGIC;
signal \ascii[4]_i_9_n_0\ : STD_LOGIC;
signal \ascii[5]_i_10_n_0\ : STD_LOGIC;
signal \ascii[5]_i_11_n_0\ : STD_LOGIC;
signal \ascii[5]_i_12_n_0\ : STD_LOGIC;
signal \ascii[5]_i_13_n_0\ : STD_LOGIC;
signal \ascii[5]_i_14_n_0\ : STD_LOGIC;
signal \ascii[5]_i_15_n_0\ : STD_LOGIC;
signal \ascii[5]_i_16_n_0\ : STD_LOGIC;
signal \ascii[5]_i_17_n_0\ : STD_LOGIC;
signal \ascii[5]_i_2_n_0\ : STD_LOGIC;
signal \ascii[5]_i_3_n_0\ : STD_LOGIC;
signal \ascii[5]_i_4_n_0\ : STD_LOGIC;
signal \ascii[6]_i_10_n_0\ : STD_LOGIC;
signal \ascii[6]_i_11_n_0\ : STD_LOGIC;
signal \ascii[6]_i_12_n_0\ : STD_LOGIC;
signal \ascii[6]_i_13_n_0\ : STD_LOGIC;
signal \ascii[6]_i_14_n_0\ : STD_LOGIC;
signal \ascii[6]_i_15_n_0\ : STD_LOGIC;
signal \ascii[6]_i_16_n_0\ : STD_LOGIC;
signal \ascii[6]_i_17_n_0\ : STD_LOGIC;
signal \ascii[6]_i_3_n_0\ : STD_LOGIC;
signal \ascii[6]_i_4_n_0\ : STD_LOGIC;
signal \ascii[6]_i_5_n_0\ : STD_LOGIC;
signal \ascii[6]_i_6_n_0\ : STD_LOGIC;
signal \ascii[6]_i_7_n_0\ : STD_LOGIC;
signal \ascii[6]_i_8_n_0\ : STD_LOGIC;
signal \ascii[6]_i_9_n_0\ : STD_LOGIC;
signal \ascii_reg[0]_i_7_n_0\ : STD_LOGIC;
signal \ascii_reg[2]_i_2_n_0\ : STD_LOGIC;
signal \ascii_reg[2]_i_8_n_0\ : STD_LOGIC;
signal \ascii_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \ascii_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_5_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_6_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_7_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_8_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_9_n_0\ : STD_LOGIC;
signal break_i_2_n_0 : STD_LOGIC;
signal caps_lock_i_2_n_0 : STD_LOGIC;
signal clear : STD_LOGIC;
signal control_l_i_2_n_0 : STD_LOGIC;
signal control_r_i_2_n_0 : STD_LOGIC;
signal control_r_i_3_n_0 : STD_LOGIC;
signal \count_idle[0]_i_2_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_4_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_8_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_9_n_0\ : STD_LOGIC;
signal count_idle_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \count_idle_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \count_idle_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_7\ : STD_LOGIC;
signal e0_code_i_2_n_0 : STD_LOGIC;
signal ps2_clk_int : STD_LOGIC;
signal ps2_code : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^ps2_code_new\ : STD_LOGIC;
signal ps2_code_new0 : STD_LOGIC;
signal ps2_code_new_i_2_n_0 : STD_LOGIC;
signal ps2_code_new_i_3_n_0 : STD_LOGIC;
signal ps2_code_new_i_4_n_0 : STD_LOGIC;
signal ps2_code_new_i_5_n_0 : STD_LOGIC;
signal ps2_code_new_i_6_n_0 : STD_LOGIC;
signal ps2_code_new_i_7_n_0 : STD_LOGIC;
signal ps2_data_int : STD_LOGIC;
signal ps2_word : STD_LOGIC_VECTOR ( 10 downto 0 );
signal shift_l_i_2_n_0 : STD_LOGIC;
signal shift_r_i_2_n_0 : STD_LOGIC;
signal shift_r_i_3_n_0 : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \NLW_count_idle_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_count_idle_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_count_idle_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ascii[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ascii[6]_i_2\ : label is "soft_lutpair1";
begin
ps2_code_new <= \^ps2_code_new\;
\ascii[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[0]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[0]_i_3_n_0\,
O => \ascii_reg[6]\(0)
);
\ascii[0]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DCFDFFDF01000888"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(4),
O => \ascii[0]_i_10_n_0\
);
\ascii[0]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDBDFDFFEEBD030C"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[0]_i_11_n_0\
);
\ascii[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CFC0C0CACACFCF"
)
port map (
I0 => ps2_code(2),
I1 => \ascii[0]_i_4_n_0\,
I2 => ps2_code(1),
I3 => ps2_code(6),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[0]_i_2_n_0\
);
\ascii[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[0]_i_5_n_0\,
I2 => shift_r,
I3 => \ascii[0]_i_6_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[0]_i_7_n_0\,
O => \ascii[0]_i_3_n_0\
);
\ascii[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6515"
)
port map (
I0 => ps2_code(5),
I1 => ps2_code(0),
I2 => ps2_code(3),
I3 => ps2_code(4),
O => \ascii[0]_i_4_n_0\
);
\ascii[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0CFCFEFE0C0C0"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(4),
I2 => ps2_code(7),
I3 => \ascii[0]_i_8_n_0\,
I4 => ps2_code(2),
I5 => \ascii[0]_i_9_n_0\,
O => \ascii[0]_i_5_n_0\
);
\ascii[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(2),
I2 => ps2_code(4),
O => \ascii[0]_i_6_n_0\
);
\ascii[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"EDBDFDFFEEB90344"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[0]_i_8_n_0\
);
\ascii[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"DCFDFFD701000888"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(4),
O => \ascii[0]_i_9_n_0\
);
\ascii[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[1]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[1]_i_3_n_0\,
O => \ascii_reg[6]\(1)
);
\ascii[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6632FFFF66320000"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(0),
I2 => ps2_code(4),
I3 => ps2_code(3),
I4 => ps2_code(2),
I5 => \ascii[1]_i_4_n_0\,
O => \ascii[1]_i_2_n_0\
);
\ascii[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => shift_l,
I1 => \ascii[1]_i_5_n_0\,
I2 => shift_r,
I3 => \ascii[1]_i_6_n_0\,
O => \ascii[1]_i_3_n_0\
);
\ascii[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55559DCDFFFFFFFF"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(3),
I2 => ps2_code(5),
I3 => ps2_code(4),
I4 => ps2_code(6),
I5 => ps2_code(1),
O => \ascii[1]_i_4_n_0\
);
\ascii[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
I2 => ps2_code(7),
I3 => \ascii[1]_i_7_n_0\,
I4 => ps2_code(2),
I5 => \ascii[1]_i_8_n_0\,
O => \ascii[1]_i_5_n_0\
);
\ascii[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
I2 => ps2_code(7),
I3 => \ascii[1]_i_9_n_0\,
I4 => ps2_code(2),
I5 => \ascii[1]_i_8_n_0\,
O => \ascii[1]_i_6_n_0\
);
\ascii[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1120100EEEFD0024"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[1]_i_7_n_0\
);
\ascii[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"20222248DFFF1008"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[1]_i_8_n_0\
);
\ascii[1]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"11021004EAFD0024"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[1]_i_9_n_0\
);
\ascii[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii_reg[2]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[2]_i_3_n_0\,
O => \ascii_reg[6]\(2)
);
\ascii[2]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8E8ADEDDF777"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(3),
O => \ascii[2]_i_10_n_0\
);
\ascii[2]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8E8ADEDDF7F7"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(3),
O => \ascii[2]_i_11_n_0\
);
\ascii[2]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"1504001010303814"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(3),
I4 => ps2_code(4),
I5 => ps2_code(0),
O => \ascii[2]_i_12_n_0\
);
\ascii[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[2]_i_6_n_0\,
I2 => shift_r,
I3 => \ascii[2]_i_7_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[2]_i_8_n_0\,
O => \ascii[2]_i_3_n_0\
);
\ascii[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FAFF0C0EF00CFC0"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(3),
I2 => ps2_code(1),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(0),
O => \ascii[2]_i_4_n_0\
);
\ascii[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5FF0AAFA4EF0FFFF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[2]_i_5_n_0\
);
\ascii[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00DFDF0F00D0D0"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(7),
I3 => \ascii[2]_i_9_n_0\,
I4 => ps2_code(2),
I5 => \ascii[2]_i_10_n_0\,
O => \ascii[2]_i_6_n_0\
);
\ascii[2]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"0D"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(2),
O => \ascii[2]_i_7_n_0\
);
\ascii[2]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"1500001010303A14"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(3),
I4 => ps2_code(4),
I5 => ps2_code(0),
O => \ascii[2]_i_9_n_0\
);
\ascii[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii_reg[3]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[3]_i_3_n_0\,
O => \ascii_reg[6]\(3)
);
\ascii[3]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEECFECDEBCDEBCF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[3]_i_10_n_0\
);
\ascii[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => shift_l,
I1 => \ascii[3]_i_6_n_0\,
I2 => shift_r,
I3 => \ascii[3]_i_7_n_0\,
O => \ascii[3]_i_3_n_0\
);
\ascii[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFE2333F"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(5),
I2 => ps2_code(0),
I3 => ps2_code(3),
I4 => ps2_code(4),
O => \ascii[3]_i_4_n_0\
);
\ascii[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF444444F4F444F4"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(6),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(5),
O => \ascii[3]_i_5_n_0\
);
\ascii[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0DFDFFFF0D0D0"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(6),
I2 => ps2_code(7),
I3 => \ascii[3]_i_8_n_0\,
I4 => ps2_code(2),
I5 => \ascii[3]_i_9_n_0\,
O => \ascii[3]_i_6_n_0\
);
\ascii[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0DFDFFFF0D0D0"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(6),
I2 => ps2_code(7),
I3 => \ascii[3]_i_10_n_0\,
I4 => ps2_code(2),
I5 => \ascii[3]_i_9_n_0\,
O => \ascii[3]_i_7_n_0\
);
\ascii[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEECFEEDEBCFEFCF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[3]_i_8_n_0\
);
\ascii[3]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFDFFB313D333"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(0),
I2 => ps2_code(5),
I3 => ps2_code(4),
I4 => ps2_code(3),
I5 => ps2_code(6),
O => \ascii[3]_i_9_n_0\
);
\ascii[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[4]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[4]_i_3_n_0\,
O => \ascii_reg[6]\(4)
);
\ascii[4]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"15321434FFEF1428"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_10_n_0\
);
\ascii[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCCC3FFCCCC8CB8"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(2),
I2 => ps2_code(5),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(3),
O => \ascii[4]_i_2_n_0\
);
\ascii[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[4]_i_4_n_0\,
I2 => shift_r,
I3 => \ascii[4]_i_5_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[4]_i_6_n_0\,
O => \ascii[4]_i_3_n_0\
);
\ascii[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
I2 => ps2_code(7),
I3 => \ascii[4]_i_7_n_0\,
I4 => ps2_code(2),
I5 => \ascii[4]_i_8_n_0\,
O => \ascii[4]_i_4_n_0\
);
\ascii[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
O => \ascii[4]_i_5_n_0\
);
\ascii[4]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0510141EFBED0000"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_7_n_0\
);
\ascii[4]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A20248CDF70240"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_8_n_0\
);
\ascii[4]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A20200CDF70200"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_9_n_0\
);
\ascii[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[6]_i_4_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[5]_i_2_n_0\,
O => \ascii_reg[6]\(5)
);
\ascii[5]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF8F4C8080"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(5),
O => \ascii[5]_i_10_n_0\
);
\ascii[5]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"111131335544166C"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[5]_i_11_n_0\
);
\ascii[5]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5F5F0F590201080"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(4),
I2 => ps2_code(6),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_12_n_0\
);
\ascii[5]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"1202001240064648"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(4),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_13_n_0\
);
\ascii[5]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0F4C8080"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(5),
O => \ascii[5]_i_14_n_0\
);
\ascii[5]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"11113333154432EC"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[5]_i_15_n_0\
);
\ascii[5]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5F5F0F510201080"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(4),
I2 => ps2_code(6),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_16_n_0\
);
\ascii[5]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"12020212020E4248"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(4),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_17_n_0\
);
\ascii[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[5]_i_3_n_0\,
I2 => shift_r,
I3 => \ascii[5]_i_4_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[5]_i_5_n_0\,
O => \ascii[5]_i_2_n_0\
);
\ascii[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(5),
I1 => ps2_code(2),
I2 => ps2_code(7),
I3 => \ascii_reg[5]_i_6_n_0\,
I4 => caps_lock_reg_0,
I5 => \ascii_reg[5]_i_7_n_0\,
O => \ascii[5]_i_3_n_0\
);
\ascii[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ps2_code(5),
I1 => ps2_code(2),
O => \ascii[5]_i_4_n_0\
);
\ascii[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \ascii[6]_i_3_n_0\,
I1 => Q(0),
O => E(0)
);
\ascii[6]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"00B030300000C0C0"
)
port map (
I0 => e0_code,
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(3),
I4 => ps2_code(4),
I5 => ps2_code(5),
O => \ascii[6]_i_10_n_0\
);
\ascii[6]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"3333F4CC"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(5),
O => \ascii[6]_i_11_n_0\
);
\ascii[6]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"11113B3B555436EC"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[6]_i_12_n_0\
);
\ascii[6]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C040404C8C8F0C0"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(1),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(6),
O => \ascii[6]_i_13_n_0\
);
\ascii[6]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0513141811340014"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[6]_i_14_n_0\
);
\ascii[6]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0513141A11340014"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[6]_i_15_n_0\
);
\ascii[6]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFCFCC8400840"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(1),
I2 => ps2_code(6),
I3 => ps2_code(3),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[6]_i_16_n_0\
);
\ascii[6]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0511141211140014"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[6]_i_17_n_0\
);
\ascii[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[6]_i_4_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[6]_i_5_n_0\,
O => \ascii_reg[6]\(6)
);
\ascii[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0E20000"
)
port map (
I0 => \ascii[6]_i_6_n_0\,
I1 => control_l_reg_0,
I2 => \ascii[6]_i_7_n_0\,
I3 => control_r_reg_0,
I4 => Q(1),
O => \ascii[6]_i_3_n_0\
);
\ascii[6]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(3),
I2 => ps2_code(0),
I3 => ps2_code(2),
O => \ascii[6]_i_4_n_0\
);
\ascii[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => shift_l,
I1 => \ascii[6]_i_8_n_0\,
I2 => shift_r,
I3 => \ascii[6]_i_9_n_0\,
O => \ascii[6]_i_5_n_0\
);
\ascii[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFE200E2"
)
port map (
I0 => \ascii[6]_i_10_n_0\,
I1 => ps2_code(1),
I2 => \ascii[6]_i_11_n_0\,
I3 => ps2_code(2),
I4 => \ascii[6]_i_12_n_0\,
I5 => ps2_code(7),
O => \ascii[6]_i_6_n_0\
);
\ascii[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \ascii[6]_i_13_n_0\,
I1 => ps2_code(2),
I2 => \ascii[6]_i_14_n_0\,
I3 => ps2_code(7),
O => \ascii[6]_i_7_n_0\
);
\ascii[6]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F008F8F0F008080"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(5),
I2 => ps2_code(7),
I3 => \ascii[6]_i_15_n_0\,
I4 => ps2_code(2),
I5 => \ascii[6]_i_16_n_0\,
O => \ascii[6]_i_8_n_0\
);
\ascii[6]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F008F8F0F008080"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(5),
I2 => ps2_code(7),
I3 => \ascii[6]_i_17_n_0\,
I4 => ps2_code(2),
I5 => \ascii[6]_i_16_n_0\,
O => \ascii[6]_i_9_n_0\
);
\ascii[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FFFFF0D0F0D00"
)
port map (
I0 => ps2_code(7),
I1 => \state[1]_i_2_n_0\,
I2 => Q(1),
I3 => Q(0),
I4 => \ascii[6]_i_3_n_0\,
I5 => \ascii_reg[7]_0\,
O => \ascii_reg[7]\
);
\ascii_reg[0]_i_7\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[0]_i_10_n_0\,
I1 => \ascii[0]_i_11_n_0\,
O => \ascii_reg[0]_i_7_n_0\,
S => ps2_code(2)
);
\ascii_reg[2]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[2]_i_4_n_0\,
I1 => \ascii[2]_i_5_n_0\,
O => \ascii_reg[2]_i_2_n_0\,
S => ps2_code(2)
);
\ascii_reg[2]_i_8\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[2]_i_11_n_0\,
I1 => \ascii[2]_i_12_n_0\,
O => \ascii_reg[2]_i_8_n_0\,
S => ps2_code(2)
);
\ascii_reg[3]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[3]_i_4_n_0\,
I1 => \ascii[3]_i_5_n_0\,
O => \ascii_reg[3]_i_2_n_0\,
S => ps2_code(2)
);
\ascii_reg[4]_i_6\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[4]_i_9_n_0\,
I1 => \ascii[4]_i_10_n_0\,
O => \ascii_reg[4]_i_6_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_5\: unisim.vcomponents.MUXF8
port map (
I0 => \ascii_reg[5]_i_8_n_0\,
I1 => \ascii_reg[5]_i_9_n_0\,
O => \ascii_reg[5]_i_5_n_0\,
S => caps_lock_reg_0
);
\ascii_reg[5]_i_6\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_10_n_0\,
I1 => \ascii[5]_i_11_n_0\,
O => \ascii_reg[5]_i_6_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_7\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_12_n_0\,
I1 => \ascii[5]_i_13_n_0\,
O => \ascii_reg[5]_i_7_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_8\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_14_n_0\,
I1 => \ascii[5]_i_15_n_0\,
O => \ascii_reg[5]_i_8_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_9\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_16_n_0\,
I1 => \ascii[5]_i_17_n_0\,
O => \ascii_reg[5]_i_9_n_0\,
S => ps2_code(2)
);
break_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF00000800"
)
port map (
I0 => ps2_code(7),
I1 => break_i_2_n_0,
I2 => ps2_code(2),
I3 => Q(0),
I4 => Q(1),
I5 => break,
O => break_reg
);
break_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(0),
I2 => ps2_code(4),
I3 => ps2_code(3),
I4 => ps2_code(5),
I5 => ps2_code(1),
O => break_i_2_n_0
);
caps_lock_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00100000"
)
port map (
I0 => Q(0),
I1 => break,
I2 => caps_lock_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(1),
I5 => caps_lock_reg_0,
O => caps_lock_reg
);
caps_lock_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => shift_r_i_3_n_0,
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => caps_lock_i_2_n_0
);
control_l_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => control_l_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => control_l_reg_0,
O => control_l_reg
);
control_l_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => ps2_code(1),
I1 => e0_code,
I2 => control_r_i_3_n_0,
I3 => ps2_code(5),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => control_l_i_2_n_0
);
control_r_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => control_r_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => control_r_reg_0,
O => control_r_reg
);
control_r_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => ps2_code(1),
I1 => e0_code,
I2 => control_r_i_3_n_0,
I3 => ps2_code(5),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => control_r_i_2_n_0
);
control_r_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(4),
I2 => ps2_code(0),
O => control_r_i_3_n_0
);
\count_idle[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ps2_clk_int,
O => clear
);
\count_idle[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => count_idle_reg(10),
I1 => \count_idle[0]_i_4_n_0\,
I2 => count_idle_reg(12),
O => \count_idle[0]_i_2_n_0\
);
\count_idle[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFFFFFF"
)
port map (
I0 => count_idle_reg(7),
I1 => count_idle_reg(5),
I2 => \count_idle[0]_i_9_n_0\,
I3 => count_idle_reg(4),
I4 => count_idle_reg(9),
I5 => count_idle_reg(8),
O => \count_idle[0]_i_4_n_0\
);
\count_idle[0]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => count_idle_reg(0),
O => \count_idle[0]_i_8_n_0\
);
\count_idle[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFFFFFFFF"
)
port map (
I0 => count_idle_reg(0),
I1 => count_idle_reg(2),
I2 => count_idle_reg(6),
I3 => count_idle_reg(11),
I4 => count_idle_reg(3),
I5 => count_idle_reg(1),
O => \count_idle[0]_i_9_n_0\
);
\count_idle_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_7\,
Q => count_idle_reg(0),
R => clear
);
\count_idle_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_idle_reg[0]_i_3_n_0\,
CO(2 downto 0) => \NLW_count_idle_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \count_idle_reg[0]_i_3_n_4\,
O(2) => \count_idle_reg[0]_i_3_n_5\,
O(1) => \count_idle_reg[0]_i_3_n_6\,
O(0) => \count_idle_reg[0]_i_3_n_7\,
S(3 downto 1) => count_idle_reg(3 downto 1),
S(0) => \count_idle[0]_i_8_n_0\
);
\count_idle_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_5\,
Q => count_idle_reg(10),
R => clear
);
\count_idle_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_4\,
Q => count_idle_reg(11),
R => clear
);
\count_idle_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[12]_i_1_n_7\,
Q => count_idle_reg(12),
R => clear
);
\count_idle_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_idle_reg[8]_i_1_n_0\,
CO(3 downto 0) => \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => \count_idle_reg[12]_i_1_n_7\,
S(3 downto 1) => B"000",
S(0) => count_idle_reg(12)
);
\count_idle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_6\,
Q => count_idle_reg(1),
R => clear
);
\count_idle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_5\,
Q => count_idle_reg(2),
R => clear
);
\count_idle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_4\,
Q => count_idle_reg(3),
R => clear
);
\count_idle_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_7\,
Q => count_idle_reg(4),
R => clear
);
\count_idle_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_idle_reg[0]_i_3_n_0\,
CO(3) => \count_idle_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_count_idle_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_idle_reg[4]_i_1_n_4\,
O(2) => \count_idle_reg[4]_i_1_n_5\,
O(1) => \count_idle_reg[4]_i_1_n_6\,
O(0) => \count_idle_reg[4]_i_1_n_7\,
S(3 downto 0) => count_idle_reg(7 downto 4)
);
\count_idle_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_6\,
Q => count_idle_reg(5),
R => clear
);
\count_idle_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_5\,
Q => count_idle_reg(6),
R => clear
);
\count_idle_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_4\,
Q => count_idle_reg(7),
R => clear
);
\count_idle_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_7\,
Q => count_idle_reg(8),
R => clear
);
\count_idle_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_idle_reg[4]_i_1_n_0\,
CO(3) => \count_idle_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_count_idle_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_idle_reg[8]_i_1_n_4\,
O(2) => \count_idle_reg[8]_i_1_n_5\,
O(1) => \count_idle_reg[8]_i_1_n_6\,
O(0) => \count_idle_reg[8]_i_1_n_7\,
S(3 downto 0) => count_idle_reg(11 downto 8)
);
\count_idle_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_6\,
Q => count_idle_reg(9),
R => clear
);
e0_code_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF00000800"
)
port map (
I0 => ps2_code(7),
I1 => e0_code_i_2_n_0,
I2 => ps2_code(2),
I3 => Q(0),
I4 => Q(1),
I5 => e0_code,
O => e0_code_reg
);
e0_code_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(0),
I2 => ps2_code(4),
I3 => ps2_code(3),
I4 => ps2_code(5),
I5 => ps2_code(1),
O => e0_code_i_2_n_0
);
ps2_clk_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => PS2Clk_IBUF,
Q => ps2_clk_int,
R => '0'
);
ps2_code_new_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => count_idle_reg(10),
I1 => ps2_code_new_i_2_n_0,
I2 => count_idle_reg(8),
I3 => count_idle_reg(12),
O => ps2_code_new0
);
ps2_code_new_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => count_idle_reg(9),
I1 => count_idle_reg(4),
I2 => ps2_code_new_i_3_n_0,
I3 => count_idle_reg(1),
I4 => count_idle_reg(5),
I5 => count_idle_reg(7),
O => ps2_code_new_i_2_n_0
);
ps2_code_new_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => count_idle_reg(3),
I1 => count_idle_reg(11),
I2 => ps2_code_new_i_4_n_0,
I3 => count_idle_reg(6),
I4 => count_idle_reg(2),
I5 => count_idle_reg(0),
O => ps2_code_new_i_3_n_0
);
ps2_code_new_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FF96FF6969009600"
)
port map (
I0 => ps2_word(9),
I1 => ps2_word(7),
I2 => ps2_word(8),
I3 => ps2_code_new_i_5_n_0,
I4 => ps2_word(5),
I5 => ps2_code_new_i_6_n_0,
O => ps2_code_new_i_4_n_0
);
ps2_code_new_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"6996000096690000"
)
port map (
I0 => ps2_word(6),
I1 => ps2_word(3),
I2 => ps2_word(4),
I3 => ps2_word(1),
I4 => ps2_code_new_i_7_n_0,
I5 => ps2_word(2),
O => ps2_code_new_i_5_n_0
);
ps2_code_new_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9669000069960000"
)
port map (
I0 => ps2_word(6),
I1 => ps2_word(3),
I2 => ps2_word(4),
I3 => ps2_word(1),
I4 => ps2_code_new_i_7_n_0,
I5 => ps2_word(2),
O => ps2_code_new_i_6_n_0
);
ps2_code_new_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ps2_word(10),
I1 => ps2_word(0),
O => ps2_code_new_i_7_n_0
);
ps2_code_new_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_code_new0,
Q => \^ps2_code_new\,
R => '0'
);
\ps2_code_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(1),
Q => ps2_code(0),
R => '0'
);
\ps2_code_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(2),
Q => ps2_code(1),
R => '0'
);
\ps2_code_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(3),
Q => ps2_code(2),
R => '0'
);
\ps2_code_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(4),
Q => ps2_code(3),
R => '0'
);
\ps2_code_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(5),
Q => ps2_code(4),
R => '0'
);
\ps2_code_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(6),
Q => ps2_code(5),
R => '0'
);
\ps2_code_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(7),
Q => ps2_code(6),
R => '0'
);
\ps2_code_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(8),
Q => ps2_code(7),
R => '0'
);
ps2_data_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => PS2Data_IBUF,
Q => ps2_data_int,
R => '0'
);
\ps2_word_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(1),
Q => ps2_word(0),
R => '0'
);
\ps2_word_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_data_int,
Q => ps2_word(10),
R => '0'
);
\ps2_word_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(2),
Q => ps2_word(1),
R => '0'
);
\ps2_word_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(3),
Q => ps2_word(2),
R => '0'
);
\ps2_word_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(4),
Q => ps2_word(3),
R => '0'
);
\ps2_word_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(5),
Q => ps2_word(4),
R => '0'
);
\ps2_word_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(6),
Q => ps2_word(5),
R => '0'
);
\ps2_word_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(7),
Q => ps2_word(6),
R => '0'
);
\ps2_word_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(8),
Q => ps2_word(7),
R => '0'
);
\ps2_word_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(9),
Q => ps2_word(8),
R => '0'
);
\ps2_word_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(10),
Q => ps2_word(9),
R => '0'
);
shift_l_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => shift_l_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => shift_l,
O => shift_l_reg
);
shift_l_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => \ascii[4]_i_5_n_0\,
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => shift_l_i_2_n_0
);
shift_r_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => shift_r_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => shift_r,
O => shift_r_reg
);
shift_r_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000000"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => shift_r_i_3_n_0,
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => shift_r_i_2_n_0
);
shift_r_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(4),
O => shift_r_i_3_n_0
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000004F4"
)
port map (
I0 => prev_ps2_code_new,
I1 => \^ps2_code_new\,
I2 => Q(1),
I3 => break,
I4 => Q(0),
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00D00FD0"
)
port map (
I0 => ps2_code(7),
I1 => \state[1]_i_2_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => break,
O => D(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFBFFFF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => ps2_code(3),
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => \state[1]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider is
port (
clkIn : in STD_LOGIC;
clk108M : out STD_LOGIC;
clk10M : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ClockDivider;
architecture STRUCTURE of ClockDivider is
begin
inst: entity work.ClockDivider_ClockDivider_clk_wiz
port map (
clk108M => clk108M,
clk10M => clk10M,
clkIn => clkIn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_width is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end FrameBuffer_blk_mem_gen_prim_width;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOBDO(7 downto 0) => DOBDO(7 downto 0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ps2_keyboard_to_ascii is
port (
\next_s_reg[1]\ : out STD_LOGIC;
\next_s_reg[0]\ : out STD_LOGIC;
\counter_reg[0]\ : out STD_LOGIC;
\fb_in_dat_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\counter_reg[12]\ : out STD_LOGIC;
PS2Clk_IBUF : in STD_LOGIC;
clk_BUFG : in STD_LOGIC;
PS2Data_IBUF : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\current_s_reg[0]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\counter_reg[0]_0\ : in STD_LOGIC;
\counter_reg[0]_1\ : in STD_LOGIC;
\counter_reg[0]_2\ : in STD_LOGIC;
\counter_reg[0]_3\ : in STD_LOGIC;
\counter_reg[0]_4\ : in STD_LOGIC;
\counter_reg[0]_5\ : in STD_LOGIC;
\counter_reg[0]_6\ : in STD_LOGIC;
\counter_reg[4]\ : in STD_LOGIC;
\counter_reg[4]_0\ : in STD_LOGIC
);
end ps2_keyboard_to_ascii;
architecture STRUCTURE of ps2_keyboard_to_ascii is
signal ascii_code : STD_LOGIC_VECTOR ( 6 downto 0 );
signal ascii_new : STD_LOGIC;
signal ascii_new_i_1_n_0 : STD_LOGIC;
signal ascii_new_i_2_n_0 : STD_LOGIC;
signal ascii_new_i_3_n_0 : STD_LOGIC;
signal ascii_new_i_4_n_0 : STD_LOGIC;
signal ascii_new_i_5_n_0 : STD_LOGIC;
signal ascii_new_i_6_n_0 : STD_LOGIC;
signal ascii_new_i_7_n_0 : STD_LOGIC;
signal ascii_new_i_8_n_0 : STD_LOGIC;
signal ascii_new_i_9_n_0 : STD_LOGIC;
signal \ascii_reg_n_0_[0]\ : STD_LOGIC;
signal \ascii_reg_n_0_[1]\ : STD_LOGIC;
signal \ascii_reg_n_0_[2]\ : STD_LOGIC;
signal \ascii_reg_n_0_[3]\ : STD_LOGIC;
signal \ascii_reg_n_0_[4]\ : STD_LOGIC;
signal \ascii_reg_n_0_[5]\ : STD_LOGIC;
signal \ascii_reg_n_0_[6]\ : STD_LOGIC;
signal \ascii_reg_n_0_[7]\ : STD_LOGIC;
signal break : STD_LOGIC;
signal caps_lock_reg_n_0 : STD_LOGIC;
signal control_l_reg_n_0 : STD_LOGIC;
signal control_r_reg_n_0 : STD_LOGIC;
signal e0_code : STD_LOGIC;
signal prev_ps2_code_new : STD_LOGIC;
signal ps2_code_new : STD_LOGIC;
signal ps2_keyboard_0_n_1 : STD_LOGIC;
signal ps2_keyboard_0_n_10 : STD_LOGIC;
signal ps2_keyboard_0_n_11 : STD_LOGIC;
signal ps2_keyboard_0_n_12 : STD_LOGIC;
signal ps2_keyboard_0_n_13 : STD_LOGIC;
signal ps2_keyboard_0_n_14 : STD_LOGIC;
signal ps2_keyboard_0_n_15 : STD_LOGIC;
signal ps2_keyboard_0_n_16 : STD_LOGIC;
signal ps2_keyboard_0_n_17 : STD_LOGIC;
signal ps2_keyboard_0_n_18 : STD_LOGIC;
signal ps2_keyboard_0_n_2 : STD_LOGIC;
signal ps2_keyboard_0_n_3 : STD_LOGIC;
signal ps2_keyboard_0_n_4 : STD_LOGIC;
signal ps2_keyboard_0_n_5 : STD_LOGIC;
signal ps2_keyboard_0_n_6 : STD_LOGIC;
signal ps2_keyboard_0_n_7 : STD_LOGIC;
signal ps2_keyboard_0_n_8 : STD_LOGIC;
signal ps2_keyboard_0_n_9 : STD_LOGIC;
signal \repeat_counter[0]_i_10_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_11_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_12_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_6_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_7_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_8_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_9_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[20]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_5_n_0\ : STD_LOGIC;
signal repeat_counter_reg : STD_LOGIC_VECTOR ( 20 downto 0 );
signal \repeat_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
signal shift_l : STD_LOGIC;
signal shift_r : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_repeat_counter_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_repeat_counter_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_repeat_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_repeat_counter_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_repeat_counter_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\ascii_code_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[0]\,
Q => ascii_code(0),
R => '0'
);
\ascii_code_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[1]\,
Q => ascii_code(1),
R => '0'
);
\ascii_code_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[2]\,
Q => ascii_code(2),
R => '0'
);
\ascii_code_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[3]\,
Q => ascii_code(3),
R => '0'
);
\ascii_code_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[4]\,
Q => ascii_code(4),
R => '0'
);
\ascii_code_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[5]\,
Q => ascii_code(5),
R => '0'
);
\ascii_code_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[6]\,
Q => ascii_code(6),
R => '0'
);
ascii_new_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A80800000000"
)
port map (
I0 => state(1),
I1 => ascii_new_i_2_n_0,
I2 => repeat_counter_reg(16),
I3 => ascii_new_i_3_n_0,
I4 => \ascii_reg_n_0_[7]\,
I5 => state(0),
O => ascii_new_i_1_n_0
);
ascii_new_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF01FF00FE00"
)
port map (
I0 => repeat_counter_reg(19),
I1 => repeat_counter_reg(12),
I2 => repeat_counter_reg(11),
I3 => ascii_new_i_3_n_0,
I4 => repeat_counter_reg(10),
I5 => ascii_new_i_4_n_0,
O => ascii_new_i_2_n_0
);
ascii_new_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \ascii_reg_n_0_[3]\,
I1 => \ascii_reg_n_0_[5]\,
I2 => ascii_new_i_5_n_0,
I3 => \ascii_reg_n_0_[0]\,
I4 => \ascii_reg_n_0_[4]\,
I5 => \ascii_reg_n_0_[6]\,
O => ascii_new_i_3_n_0
);
ascii_new_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFFFFF40000000"
)
port map (
I0 => repeat_counter_reg(7),
I1 => ascii_new_i_6_n_0,
I2 => repeat_counter_reg(2),
I3 => repeat_counter_reg(0),
I4 => repeat_counter_reg(18),
I5 => ascii_new_i_3_n_0,
O => ascii_new_i_4_n_0
);
ascii_new_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \ascii_reg_n_0_[2]\,
I1 => \ascii_reg_n_0_[1]\,
O => ascii_new_i_5_n_0
);
ascii_new_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFFFFF40000000"
)
port map (
I0 => repeat_counter_reg(5),
I1 => ascii_new_i_7_n_0,
I2 => repeat_counter_reg(6),
I3 => repeat_counter_reg(17),
I4 => repeat_counter_reg(1),
I5 => ascii_new_i_3_n_0,
O => ascii_new_i_6_n_0
);
ascii_new_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF80000000"
)
port map (
I0 => ascii_new_i_8_n_0,
I1 => repeat_counter_reg(9),
I2 => repeat_counter_reg(4),
I3 => repeat_counter_reg(14),
I4 => repeat_counter_reg(15),
I5 => ascii_new_i_3_n_0,
O => ascii_new_i_7_n_0
);
ascii_new_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF8000"
)
port map (
I0 => repeat_counter_reg(13),
I1 => repeat_counter_reg(20),
I2 => repeat_counter_reg(3),
I3 => repeat_counter_reg(8),
I4 => ascii_new_i_9_n_0,
I5 => \ascii_reg_n_0_[6]\,
O => ascii_new_i_8_n_0
);
ascii_new_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \ascii_reg_n_0_[4]\,
I1 => \ascii_reg_n_0_[0]\,
I2 => \ascii_reg_n_0_[2]\,
I3 => \ascii_reg_n_0_[1]\,
I4 => \ascii_reg_n_0_[5]\,
I5 => \ascii_reg_n_0_[3]\,
O => ascii_new_i_9_n_0
);
ascii_new_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ascii_new_i_1_n_0,
Q => ascii_new,
R => '0'
);
\ascii_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_17,
Q => \ascii_reg_n_0_[0]\,
R => '0'
);
\ascii_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_16,
Q => \ascii_reg_n_0_[1]\,
R => '0'
);
\ascii_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_15,
Q => \ascii_reg_n_0_[2]\,
R => '0'
);
\ascii_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_14,
Q => \ascii_reg_n_0_[3]\,
R => '0'
);
\ascii_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_13,
Q => \ascii_reg_n_0_[4]\,
R => '0'
);
\ascii_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_12,
Q => \ascii_reg_n_0_[5]\,
R => '0'
);
\ascii_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_11,
Q => \ascii_reg_n_0_[6]\,
R => '0'
);
\ascii_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_8,
Q => \ascii_reg_n_0_[7]\,
R => '0'
);
break_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_1,
Q => break,
R => '0'
);
caps_lock_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_7,
Q => caps_lock_reg_n_0,
R => '0'
);
control_l_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_6,
Q => control_l_reg_n_0,
R => '0'
);
control_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_5,
Q => control_r_reg_n_0,
R => '0'
);
\counter[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0003A0F3"
)
port map (
I0 => ascii_new,
I1 => \counter_reg[4]\,
I2 => Q(1),
I3 => Q(0),
I4 => \counter_reg[4]_0\,
O => \counter_reg[12]\
);
\counter[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => Q(1),
I1 => ascii_new,
I2 => Q(0),
O => \counter_reg[0]\
);
e0_code_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_4,
Q => e0_code,
R => '0'
);
\fb_in_dat[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(0),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_0\,
O => \fb_in_dat_reg[6]\(0)
);
\fb_in_dat[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(1),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_1\,
O => \fb_in_dat_reg[6]\(1)
);
\fb_in_dat[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(2),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_2\,
O => \fb_in_dat_reg[6]\(2)
);
\fb_in_dat[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(3),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_3\,
O => \fb_in_dat_reg[6]\(3)
);
\fb_in_dat[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(4),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_4\,
O => \fb_in_dat_reg[6]\(4)
);
\fb_in_dat[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(5),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_5\,
O => \fb_in_dat_reg[6]\(5)
);
\fb_in_dat[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(6),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_6\,
O => \fb_in_dat_reg[6]\(6)
);
\next_s[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => D(0),
I1 => \current_s_reg[0]\,
I2 => Q(0),
I3 => Q(1),
I4 => ascii_new,
O => \next_s_reg[0]\
);
\next_s[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEEEEFE"
)
port map (
I0 => D(1),
I1 => \current_s_reg[0]\,
I2 => ascii_new,
I3 => Q(1),
I4 => Q(0),
O => \next_s_reg[1]\
);
prev_ps2_code_new_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_code_new,
Q => prev_ps2_code_new,
R => '0'
);
ps2_keyboard_0: entity work.ps2_keyboard
port map (
D(1) => ps2_keyboard_0_n_9,
D(0) => ps2_keyboard_0_n_10,
E(0) => ps2_keyboard_0_n_18,
PS2Clk_IBUF => PS2Clk_IBUF,
PS2Data_IBUF => PS2Data_IBUF,
Q(1 downto 0) => state(1 downto 0),
\ascii_reg[6]\(6) => ps2_keyboard_0_n_11,
\ascii_reg[6]\(5) => ps2_keyboard_0_n_12,
\ascii_reg[6]\(4) => ps2_keyboard_0_n_13,
\ascii_reg[6]\(3) => ps2_keyboard_0_n_14,
\ascii_reg[6]\(2) => ps2_keyboard_0_n_15,
\ascii_reg[6]\(1) => ps2_keyboard_0_n_16,
\ascii_reg[6]\(0) => ps2_keyboard_0_n_17,
\ascii_reg[7]\ => ps2_keyboard_0_n_8,
\ascii_reg[7]_0\ => \ascii_reg_n_0_[7]\,
break => break,
break_reg => ps2_keyboard_0_n_1,
caps_lock_reg => ps2_keyboard_0_n_7,
caps_lock_reg_0 => caps_lock_reg_n_0,
clk_BUFG => clk_BUFG,
control_l_reg => ps2_keyboard_0_n_6,
control_l_reg_0 => control_l_reg_n_0,
control_r_reg => ps2_keyboard_0_n_5,
control_r_reg_0 => control_r_reg_n_0,
e0_code => e0_code,
e0_code_reg => ps2_keyboard_0_n_4,
prev_ps2_code_new => prev_ps2_code_new,
ps2_code_new => ps2_code_new,
shift_l => shift_l,
shift_l_reg => ps2_keyboard_0_n_2,
shift_r => shift_r,
shift_r_reg => ps2_keyboard_0_n_3
);
\repeat_counter[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A80000"
)
port map (
I0 => state(1),
I1 => repeat_counter_reg(16),
I2 => \repeat_counter[0]_i_3_n_0\,
I3 => \ascii_reg_n_0_[7]\,
I4 => state(0),
O => \repeat_counter[0]_i_1_n_0\
);
\repeat_counter[0]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \ascii_reg_n_0_[3]\,
I1 => \ascii_reg_n_0_[5]\,
I2 => ascii_new_i_5_n_0,
I3 => \ascii_reg_n_0_[0]\,
I4 => \ascii_reg_n_0_[4]\,
I5 => \ascii_reg_n_0_[6]\,
O => \repeat_counter[0]_i_10_n_0\
);
\repeat_counter[0]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFFFFFFFFFF"
)
port map (
I0 => repeat_counter_reg(6),
I1 => repeat_counter_reg(14),
I2 => \repeat_counter[0]_i_12_n_0\,
I3 => repeat_counter_reg(4),
I4 => repeat_counter_reg(15),
I5 => repeat_counter_reg(17),
O => \repeat_counter[0]_i_11_n_0\
);
\repeat_counter[0]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFFFFFFFFFF"
)
port map (
I0 => repeat_counter_reg(8),
I1 => repeat_counter_reg(20),
I2 => ascii_new_i_3_n_0,
I3 => repeat_counter_reg(13),
I4 => repeat_counter_reg(3),
I5 => repeat_counter_reg(9),
O => \repeat_counter[0]_i_12_n_0\
);
\repeat_counter[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => repeat_counter_reg(12),
I1 => repeat_counter_reg(10),
I2 => \repeat_counter[0]_i_9_n_0\,
I3 => repeat_counter_reg(7),
I4 => repeat_counter_reg(11),
I5 => repeat_counter_reg(19),
O => \repeat_counter[0]_i_3_n_0\
);
\repeat_counter[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(0),
O => \repeat_counter[0]_i_4_n_0\
);
\repeat_counter[0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(3),
O => \repeat_counter[0]_i_5_n_0\
);
\repeat_counter[0]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(2),
O => \repeat_counter[0]_i_6_n_0\
);
\repeat_counter[0]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(1),
O => \repeat_counter[0]_i_7_n_0\
);
\repeat_counter[0]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => repeat_counter_reg(0),
I1 => \repeat_counter[0]_i_10_n_0\,
O => \repeat_counter[0]_i_8_n_0\
);
\repeat_counter[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF7FFFFFFFFFFFF"
)
port map (
I0 => repeat_counter_reg(0),
I1 => repeat_counter_reg(1),
I2 => \repeat_counter[0]_i_11_n_0\,
I3 => repeat_counter_reg(5),
I4 => repeat_counter_reg(2),
I5 => repeat_counter_reg(18),
O => \repeat_counter[0]_i_9_n_0\
);
\repeat_counter[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(15),
O => \repeat_counter[12]_i_2_n_0\
);
\repeat_counter[12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(14),
O => \repeat_counter[12]_i_3_n_0\
);
\repeat_counter[12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(13),
O => \repeat_counter[12]_i_4_n_0\
);
\repeat_counter[12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(12),
O => \repeat_counter[12]_i_5_n_0\
);
\repeat_counter[16]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(19),
O => \repeat_counter[16]_i_2_n_0\
);
\repeat_counter[16]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(18),
O => \repeat_counter[16]_i_3_n_0\
);
\repeat_counter[16]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(17),
O => \repeat_counter[16]_i_4_n_0\
);
\repeat_counter[16]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(16),
O => \repeat_counter[16]_i_5_n_0\
);
\repeat_counter[20]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(20),
O => \repeat_counter[20]_i_2_n_0\
);
\repeat_counter[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(7),
O => \repeat_counter[4]_i_2_n_0\
);
\repeat_counter[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(6),
O => \repeat_counter[4]_i_3_n_0\
);
\repeat_counter[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(5),
O => \repeat_counter[4]_i_4_n_0\
);
\repeat_counter[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(4),
O => \repeat_counter[4]_i_5_n_0\
);
\repeat_counter[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(11),
O => \repeat_counter[8]_i_2_n_0\
);
\repeat_counter[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(10),
O => \repeat_counter[8]_i_3_n_0\
);
\repeat_counter[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(9),
O => \repeat_counter[8]_i_4_n_0\
);
\repeat_counter[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(8),
O => \repeat_counter[8]_i_5_n_0\
);
\repeat_counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_7\,
Q => repeat_counter_reg(0),
R => '0'
);
\repeat_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \repeat_counter_reg[0]_i_2_n_0\,
CO(2 downto 0) => \NLW_repeat_counter_reg[0]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \repeat_counter[0]_i_4_n_0\,
O(3) => \repeat_counter_reg[0]_i_2_n_4\,
O(2) => \repeat_counter_reg[0]_i_2_n_5\,
O(1) => \repeat_counter_reg[0]_i_2_n_6\,
O(0) => \repeat_counter_reg[0]_i_2_n_7\,
S(3) => \repeat_counter[0]_i_5_n_0\,
S(2) => \repeat_counter[0]_i_6_n_0\,
S(1) => \repeat_counter[0]_i_7_n_0\,
S(0) => \repeat_counter[0]_i_8_n_0\
);
\repeat_counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_5\,
Q => repeat_counter_reg(10),
R => '0'
);
\repeat_counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_4\,
Q => repeat_counter_reg(11),
R => '0'
);
\repeat_counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_7\,
Q => repeat_counter_reg(12),
R => '0'
);
\repeat_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[8]_i_1_n_0\,
CO(3) => \repeat_counter_reg[12]_i_1_n_0\,
CO(2 downto 0) => \NLW_repeat_counter_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[12]_i_1_n_4\,
O(2) => \repeat_counter_reg[12]_i_1_n_5\,
O(1) => \repeat_counter_reg[12]_i_1_n_6\,
O(0) => \repeat_counter_reg[12]_i_1_n_7\,
S(3) => \repeat_counter[12]_i_2_n_0\,
S(2) => \repeat_counter[12]_i_3_n_0\,
S(1) => \repeat_counter[12]_i_4_n_0\,
S(0) => \repeat_counter[12]_i_5_n_0\
);
\repeat_counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_6\,
Q => repeat_counter_reg(13),
R => '0'
);
\repeat_counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_5\,
Q => repeat_counter_reg(14),
R => '0'
);
\repeat_counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_4\,
Q => repeat_counter_reg(15),
R => '0'
);
\repeat_counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_7\,
Q => repeat_counter_reg(16),
R => '0'
);
\repeat_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[12]_i_1_n_0\,
CO(3) => \repeat_counter_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_repeat_counter_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[16]_i_1_n_4\,
O(2) => \repeat_counter_reg[16]_i_1_n_5\,
O(1) => \repeat_counter_reg[16]_i_1_n_6\,
O(0) => \repeat_counter_reg[16]_i_1_n_7\,
S(3) => \repeat_counter[16]_i_2_n_0\,
S(2) => \repeat_counter[16]_i_3_n_0\,
S(1) => \repeat_counter[16]_i_4_n_0\,
S(0) => \repeat_counter[16]_i_5_n_0\
);
\repeat_counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_6\,
Q => repeat_counter_reg(17),
R => '0'
);
\repeat_counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_5\,
Q => repeat_counter_reg(18),
R => '0'
);
\repeat_counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_4\,
Q => repeat_counter_reg(19),
R => '0'
);
\repeat_counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_6\,
Q => repeat_counter_reg(1),
R => '0'
);
\repeat_counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[20]_i_1_n_7\,
Q => repeat_counter_reg(20),
R => '0'
);
\repeat_counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[16]_i_1_n_0\,
CO(3 downto 0) => \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => \repeat_counter_reg[20]_i_1_n_7\,
S(3 downto 1) => B"000",
S(0) => \repeat_counter[20]_i_2_n_0\
);
\repeat_counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_5\,
Q => repeat_counter_reg(2),
R => '0'
);
\repeat_counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_4\,
Q => repeat_counter_reg(3),
R => '0'
);
\repeat_counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_7\,
Q => repeat_counter_reg(4),
R => '0'
);
\repeat_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[0]_i_2_n_0\,
CO(3) => \repeat_counter_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_repeat_counter_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[4]_i_1_n_4\,
O(2) => \repeat_counter_reg[4]_i_1_n_5\,
O(1) => \repeat_counter_reg[4]_i_1_n_6\,
O(0) => \repeat_counter_reg[4]_i_1_n_7\,
S(3) => \repeat_counter[4]_i_2_n_0\,
S(2) => \repeat_counter[4]_i_3_n_0\,
S(1) => \repeat_counter[4]_i_4_n_0\,
S(0) => \repeat_counter[4]_i_5_n_0\
);
\repeat_counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_6\,
Q => repeat_counter_reg(5),
R => '0'
);
\repeat_counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_5\,
Q => repeat_counter_reg(6),
R => '0'
);
\repeat_counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_4\,
Q => repeat_counter_reg(7),
R => '0'
);
\repeat_counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_7\,
Q => repeat_counter_reg(8),
R => '0'
);
\repeat_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[4]_i_1_n_0\,
CO(3) => \repeat_counter_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_repeat_counter_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[8]_i_1_n_4\,
O(2) => \repeat_counter_reg[8]_i_1_n_5\,
O(1) => \repeat_counter_reg[8]_i_1_n_6\,
O(0) => \repeat_counter_reg[8]_i_1_n_7\,
S(3) => \repeat_counter[8]_i_2_n_0\,
S(2) => \repeat_counter[8]_i_3_n_0\,
S(1) => \repeat_counter[8]_i_4_n_0\,
S(0) => \repeat_counter[8]_i_5_n_0\
);
\repeat_counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_6\,
Q => repeat_counter_reg(9),
R => '0'
);
shift_l_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_2,
Q => shift_l,
R => '0'
);
shift_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_3,
Q => shift_r,
R => '0'
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_10,
Q => state(0),
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_9,
Q => state(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end FrameBuffer_blk_mem_gen_generic_cstr;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is
signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
begin
\has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0),
DOBDO(7) => \ramloop[2].ram.r_n_0\,
DOBDO(6) => \ramloop[2].ram.r_n_1\,
DOBDO(5) => \ramloop[2].ram.r_n_2\,
DOBDO(4) => \ramloop[2].ram.r_n_3\,
DOBDO(3) => \ramloop[2].ram.r_n_4\,
DOBDO(2) => \ramloop[2].ram.r_n_5\,
DOBDO(1) => \ramloop[2].ram.r_n_6\,
DOBDO(0) => \ramloop[2].ram.r_n_7\,
addrb(2 downto 0) => addrb(13 downto 11),
clkb => clkb,
doutb(7 downto 0) => doutb(7 downto 0)
);
\ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7 downto 0) => ram_doutb(7 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7) => \ramloop[1].ram.r_n_0\,
\doutb[7]\(6) => \ramloop[1].ram.r_n_1\,
\doutb[7]\(5) => \ramloop[1].ram.r_n_2\,
\doutb[7]\(4) => \ramloop[1].ram.r_n_3\,
\doutb[7]\(3) => \ramloop[1].ram.r_n_4\,
\doutb[7]\(2) => \ramloop[1].ram.r_n_5\,
\doutb[7]\(1) => \ramloop[1].ram.r_n_6\,
\doutb[7]\(0) => \ramloop[1].ram.r_n_7\,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\
port map (
DOBDO(7) => \ramloop[2].ram.r_n_0\,
DOBDO(6) => \ramloop[2].ram.r_n_1\,
DOBDO(5) => \ramloop[2].ram.r_n_2\,
DOBDO(4) => \ramloop[2].ram.r_n_3\,
DOBDO(3) => \ramloop[2].ram.r_n_4\,
DOBDO(2) => \ramloop[2].ram.r_n_5\,
DOBDO(1) => \ramloop[2].ram.r_n_6\,
DOBDO(0) => \ramloop[2].ram.r_n_7\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top";
end FrameBuffer_blk_mem_gen_top;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is
begin
\valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end FrameBuffer_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "20";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.58651 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes";
end FrameBuffer_blk_mem_gen_v8_3_1;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is
begin
dbiterr <= 'Z';
rsta_busy <= 'Z';
rstb_busy <= 'Z';
s_axi_arready <= 'Z';
s_axi_awready <= 'Z';
s_axi_bvalid <= 'Z';
s_axi_dbiterr <= 'Z';
s_axi_rlast <= 'Z';
s_axi_rvalid <= 'Z';
s_axi_sbiterr <= 'Z';
s_axi_wready <= 'Z';
sbiterr <= 'Z';
douta(0) <= 'Z';
douta(1) <= 'Z';
douta(2) <= 'Z';
douta(3) <= 'Z';
douta(4) <= 'Z';
douta(5) <= 'Z';
douta(6) <= 'Z';
douta(7) <= 'Z';
rdaddrecc(0) <= 'Z';
rdaddrecc(1) <= 'Z';
rdaddrecc(2) <= 'Z';
rdaddrecc(3) <= 'Z';
rdaddrecc(4) <= 'Z';
rdaddrecc(5) <= 'Z';
rdaddrecc(6) <= 'Z';
rdaddrecc(7) <= 'Z';
rdaddrecc(8) <= 'Z';
rdaddrecc(9) <= 'Z';
rdaddrecc(10) <= 'Z';
rdaddrecc(11) <= 'Z';
rdaddrecc(12) <= 'Z';
rdaddrecc(13) <= 'Z';
s_axi_bid(0) <= 'Z';
s_axi_bid(1) <= 'Z';
s_axi_bid(2) <= 'Z';
s_axi_bid(3) <= 'Z';
s_axi_bresp(0) <= 'Z';
s_axi_bresp(1) <= 'Z';
s_axi_rdaddrecc(0) <= 'Z';
s_axi_rdaddrecc(1) <= 'Z';
s_axi_rdaddrecc(2) <= 'Z';
s_axi_rdaddrecc(3) <= 'Z';
s_axi_rdaddrecc(4) <= 'Z';
s_axi_rdaddrecc(5) <= 'Z';
s_axi_rdaddrecc(6) <= 'Z';
s_axi_rdaddrecc(7) <= 'Z';
s_axi_rdaddrecc(8) <= 'Z';
s_axi_rdaddrecc(9) <= 'Z';
s_axi_rdaddrecc(10) <= 'Z';
s_axi_rdaddrecc(11) <= 'Z';
s_axi_rdaddrecc(12) <= 'Z';
s_axi_rdaddrecc(13) <= 'Z';
s_axi_rdata(0) <= 'Z';
s_axi_rdata(1) <= 'Z';
s_axi_rdata(2) <= 'Z';
s_axi_rdata(3) <= 'Z';
s_axi_rdata(4) <= 'Z';
s_axi_rdata(5) <= 'Z';
s_axi_rdata(6) <= 'Z';
s_axi_rdata(7) <= 'Z';
s_axi_rid(0) <= 'Z';
s_axi_rid(1) <= 'Z';
s_axi_rid(2) <= 'Z';
s_axi_rid(3) <= 'Z';
s_axi_rresp(0) <= 'Z';
s_axi_rresp(1) <= 'Z';
inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=20,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.58651 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end FrameBuffer;
architecture STRUCTURE of FrameBuffer is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_deepsleep_UNCONNECTED : STD_LOGIC;
signal NLW_U0_eccpipece_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ena_UNCONNECTED : STD_LOGIC;
signal NLW_U0_enb_UNCONNECTED : STD_LOGIC;
signal NLW_U0_injectdbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_injectsbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_regcea_UNCONNECTED : STD_LOGIC;
signal NLW_U0_regceb_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_aclk_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_aresetn_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_injectdbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_injectsbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_shutdown_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sleep_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dinb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_s_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_web_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "20";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.58651 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => NLW_U0_deepsleep_UNCONNECTED,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => NLW_U0_dinb_UNCONNECTED(7 downto 0),
douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => NLW_U0_eccpipece_UNCONNECTED,
ena => NLW_U0_ena_UNCONNECTED,
enb => NLW_U0_enb_UNCONNECTED,
injectdbiterr => NLW_U0_injectdbiterr_UNCONNECTED,
injectsbiterr => NLW_U0_injectsbiterr_UNCONNECTED,
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => NLW_U0_regcea_UNCONNECTED,
regceb => NLW_U0_regceb_UNCONNECTED,
rsta => NLW_U0_rsta_UNCONNECTED,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => NLW_U0_rstb_UNCONNECTED,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => NLW_U0_s_aclk_UNCONNECTED,
s_aresetn => NLW_U0_s_aresetn_UNCONNECTED,
s_axi_araddr(31 downto 0) => NLW_U0_s_axi_araddr_UNCONNECTED(31 downto 0),
s_axi_arburst(1 downto 0) => NLW_U0_s_axi_arburst_UNCONNECTED(1 downto 0),
s_axi_arid(3 downto 0) => NLW_U0_s_axi_arid_UNCONNECTED(3 downto 0),
s_axi_arlen(7 downto 0) => NLW_U0_s_axi_arlen_UNCONNECTED(7 downto 0),
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => NLW_U0_s_axi_arsize_UNCONNECTED(2 downto 0),
s_axi_arvalid => NLW_U0_s_axi_arvalid_UNCONNECTED,
s_axi_awaddr(31 downto 0) => NLW_U0_s_axi_awaddr_UNCONNECTED(31 downto 0),
s_axi_awburst(1 downto 0) => NLW_U0_s_axi_awburst_UNCONNECTED(1 downto 0),
s_axi_awid(3 downto 0) => NLW_U0_s_axi_awid_UNCONNECTED(3 downto 0),
s_axi_awlen(7 downto 0) => NLW_U0_s_axi_awlen_UNCONNECTED(7 downto 0),
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => NLW_U0_s_axi_awsize_UNCONNECTED(2 downto 0),
s_axi_awvalid => NLW_U0_s_axi_awvalid_UNCONNECTED,
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => NLW_U0_s_axi_bready_UNCONNECTED,
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => NLW_U0_s_axi_injectdbiterr_UNCONNECTED,
s_axi_injectsbiterr => NLW_U0_s_axi_injectsbiterr_UNCONNECTED,
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => NLW_U0_s_axi_rready_UNCONNECTED,
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => NLW_U0_s_axi_wdata_UNCONNECTED(7 downto 0),
s_axi_wlast => NLW_U0_s_axi_wlast_UNCONNECTED,
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => NLW_U0_s_axi_wstrb_UNCONNECTED(0),
s_axi_wvalid => NLW_U0_s_axi_wvalid_UNCONNECTED,
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => NLW_U0_shutdown_UNCONNECTED,
sleep => NLW_U0_sleep_UNCONNECTED,
wea(0) => wea(0),
web(0) => NLW_U0_web_UNCONNECTED(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
port (
vgaRed : out STD_LOGIC_VECTOR ( 3 downto 0 );
vgaGreen : out STD_LOGIC_VECTOR ( 3 downto 0 );
vgaBlue : out STD_LOGIC_VECTOR ( 3 downto 0 );
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
led : out STD_LOGIC_VECTOR ( 15 downto 0 );
sw : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
btnC : in STD_LOGIC;
btnU : in STD_LOGIC;
btnL : in STD_LOGIC;
btnR : in STD_LOGIC;
btnD : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
RsRx : inout STD_LOGIC;
RsTx : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of top : entity is true;
attribute ECO_CHECKSUM : string;
attribute ECO_CHECKSUM of top : entity is "d678d57b";
attribute POWER_OPT_BRAM_CDC : integer;
attribute POWER_OPT_BRAM_CDC of top : entity is 0;
attribute POWER_OPT_BRAM_SR_ADDR : integer;
attribute POWER_OPT_BRAM_SR_ADDR of top : entity is 0;
attribute POWER_OPT_LOOPED_NET_PERCENTAGE : integer;
attribute POWER_OPT_LOOPED_NET_PERCENTAGE of top : entity is 0;
end top;
architecture STRUCTURE of top is
signal Hsync_OBUF : STD_LOGIC;
signal PS2Clk_IBUF : STD_LOGIC;
signal PS2Data_IBUF : STD_LOGIC;
signal Vsync_OBUF : STD_LOGIC;
signal addra : STD_LOGIC_VECTOR ( 13 downto 0 );
signal btnC_IBUF : STD_LOGIC;
signal btnD_IBUF : STD_LOGIC;
signal btnL_IBUF : STD_LOGIC;
signal btnR_IBUF : STD_LOGIC;
signal btnU_IBUF : STD_LOGIC;
signal clk108M : STD_LOGIC;
signal clk10M : STD_LOGIC;
signal clk_1_i_1_n_0 : STD_LOGIC;
signal clk_1_i_2_n_0 : STD_LOGIC;
signal clk_1_i_3_n_0 : STD_LOGIC;
signal clk_1_i_4_n_0 : STD_LOGIC;
signal clk_1_i_5_n_0 : STD_LOGIC;
signal clk_1_reg_n_0 : STD_LOGIC;
signal clk_BUFG : STD_LOGIC;
signal clk_IBUF : STD_LOGIC;
signal \counter[0]__0_i_1_n_0\ : STD_LOGIC;
signal \counter[0]_i_1_n_0\ : STD_LOGIC;
signal \counter[10]_i_1_n_0\ : STD_LOGIC;
signal \counter[13]_i_2_n_0\ : STD_LOGIC;
signal \counter[13]_i_3_n_0\ : STD_LOGIC;
signal \counter[13]_i_4_n_0\ : STD_LOGIC;
signal \counter[13]_i_6_n_0\ : STD_LOGIC;
signal \counter[13]_i_7_n_0\ : STD_LOGIC;
signal \counter[1]_i_1_n_0\ : STD_LOGIC;
signal \counter[22]_i_10_n_0\ : STD_LOGIC;
signal \counter[22]_i_11_n_0\ : STD_LOGIC;
signal \counter[22]_i_12_n_0\ : STD_LOGIC;
signal \counter[22]_i_13_n_0\ : STD_LOGIC;
signal \counter[22]_i_14_n_0\ : STD_LOGIC;
signal \counter[22]_i_15_n_0\ : STD_LOGIC;
signal \counter[22]_i_16_n_0\ : STD_LOGIC;
signal \counter[22]_i_17_n_0\ : STD_LOGIC;
signal \counter[22]_i_18_n_0\ : STD_LOGIC;
signal \counter[22]_i_19_n_0\ : STD_LOGIC;
signal \counter[22]_i_1_n_0\ : STD_LOGIC;
signal \counter[22]_i_20_n_0\ : STD_LOGIC;
signal \counter[22]_i_21_n_0\ : STD_LOGIC;
signal \counter[22]_i_22_n_0\ : STD_LOGIC;
signal \counter[22]_i_7_n_0\ : STD_LOGIC;
signal \counter[2]_i_1_n_0\ : STD_LOGIC;
signal \counter[4]_i_1_n_0\ : STD_LOGIC;
signal \counter[5]_i_1_n_0\ : STD_LOGIC;
signal \counter[6]_i_1_n_0\ : STD_LOGIC;
signal \counter[7]_i_1_n_0\ : STD_LOGIC;
signal \counter[8]_i_1_n_0\ : STD_LOGIC;
signal \counter[9]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[0]__0_n_0\ : STD_LOGIC;
signal \counter_reg[10]__0_n_0\ : STD_LOGIC;
signal \counter_reg[11]__0_n_0\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[12]__0_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[13]__0_n_0\ : STD_LOGIC;
signal \counter_reg[13]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[1]__0_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[22]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[22]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[22]_i_3_n_3\ : STD_LOGIC;
signal \counter_reg[22]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[22]_i_9_n_0\ : STD_LOGIC;
signal \counter_reg[2]__0_n_0\ : STD_LOGIC;
signal \counter_reg[3]__0_n_0\ : STD_LOGIC;
signal \counter_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[4]__0_n_0\ : STD_LOGIC;
signal \counter_reg[5]__0_n_0\ : STD_LOGIC;
signal \counter_reg[6]__0_n_0\ : STD_LOGIC;
signal \counter_reg[7]__0_n_0\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[8]__0_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[9]__0_n_0\ : STD_LOGIC;
signal \counter_reg_n_0_[0]\ : STD_LOGIC;
signal \counter_reg_n_0_[10]\ : STD_LOGIC;
signal \counter_reg_n_0_[11]\ : STD_LOGIC;
signal \counter_reg_n_0_[12]\ : STD_LOGIC;
signal \counter_reg_n_0_[13]\ : STD_LOGIC;
signal \counter_reg_n_0_[14]\ : STD_LOGIC;
signal \counter_reg_n_0_[15]\ : STD_LOGIC;
signal \counter_reg_n_0_[16]\ : STD_LOGIC;
signal \counter_reg_n_0_[17]\ : STD_LOGIC;
signal \counter_reg_n_0_[18]\ : STD_LOGIC;
signal \counter_reg_n_0_[19]\ : STD_LOGIC;
signal \counter_reg_n_0_[1]\ : STD_LOGIC;
signal \counter_reg_n_0_[20]\ : STD_LOGIC;
signal \counter_reg_n_0_[21]\ : STD_LOGIC;
signal \counter_reg_n_0_[22]\ : STD_LOGIC;
signal \counter_reg_n_0_[2]\ : STD_LOGIC;
signal \counter_reg_n_0_[3]\ : STD_LOGIC;
signal \counter_reg_n_0_[4]\ : STD_LOGIC;
signal \counter_reg_n_0_[5]\ : STD_LOGIC;
signal \counter_reg_n_0_[6]\ : STD_LOGIC;
signal \counter_reg_n_0_[7]\ : STD_LOGIC;
signal \counter_reg_n_0_[8]\ : STD_LOGIC;
signal \counter_reg_n_0_[9]\ : STD_LOGIC;
signal current_s : STD_LOGIC_VECTOR ( 1 downto 0 );
signal dina : STD_LOGIC_VECTOR ( 7 downto 0 );
signal doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal fbOutAddr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal fb_in_addr0 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \fb_in_addr[0]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[10]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_7_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_8_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_9_n_0\ : STD_LOGIC;
signal \fb_in_addr[12]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[13]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[13]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[13]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[1]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[2]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_6_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_7_n_0\ : STD_LOGIC;
signal \fb_in_addr[4]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[5]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[6]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_6_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_7_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_8_n_0\ : STD_LOGIC;
signal \fb_in_addr[8]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr[9]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_addr_reg[11]_i_2_n_0\ : STD_LOGIC;
signal \fb_in_addr_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \fb_in_addr_reg[7]_i_2_n_0\ : STD_LOGIC;
signal fb_in_dat : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \g0_b0__0_n_0\ : STD_LOGIC;
signal \g0_b1__0_n_0\ : STD_LOGIC;
signal \g0_b2__0_n_0\ : STD_LOGIC;
signal \g0_b3__0_n_0\ : STD_LOGIC;
signal \g0_b4__0_n_0\ : STD_LOGIC;
signal \g0_b5__0_n_0\ : STD_LOGIC;
signal \g0_b6__0_i_1_n_0\ : STD_LOGIC;
signal \g0_b6__0_i_2_n_0\ : STD_LOGIC;
signal \g0_b6__0_i_3_n_0\ : STD_LOGIC;
signal \g0_b6__0_i_4_n_0\ : STD_LOGIC;
signal \g0_b6__0_i_5_n_0\ : STD_LOGIC;
signal \g0_b6__0_i_6_n_0\ : STD_LOGIC;
signal \g0_b6__0_i_7_n_0\ : STD_LOGIC;
signal \g0_b6__0_n_0\ : STD_LOGIC;
signal keyboard0_n_0 : STD_LOGIC;
signal keyboard0_n_1 : STD_LOGIC;
signal keyboard0_n_10 : STD_LOGIC;
signal keyboard0_n_2 : STD_LOGIC;
signal next_s : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \next_s[1]_i_2_n_0\ : STD_LOGIC;
signal \sw[0]\ : STD_LOGIC;
signal \sw[0]_IBUF\ : STD_LOGIC;
signal \sw[10]\ : STD_LOGIC;
signal \sw[10]_IBUF\ : STD_LOGIC;
signal \sw[11]\ : STD_LOGIC;
signal \sw[11]_IBUF\ : STD_LOGIC;
signal \sw[12]\ : STD_LOGIC;
signal \sw[12]_IBUF\ : STD_LOGIC;
signal \sw[13]\ : STD_LOGIC;
signal \sw[13]_IBUF\ : STD_LOGIC;
signal \sw[14]\ : STD_LOGIC;
signal \sw[14]_IBUF\ : STD_LOGIC;
signal \sw[15]\ : STD_LOGIC;
signal \sw[15]_IBUF\ : STD_LOGIC;
signal \sw[1]\ : STD_LOGIC;
signal \sw[1]_IBUF\ : STD_LOGIC;
signal \sw[2]\ : STD_LOGIC;
signal \sw[2]_IBUF\ : STD_LOGIC;
signal \sw[3]\ : STD_LOGIC;
signal \sw[3]_IBUF\ : STD_LOGIC;
signal \sw[4]\ : STD_LOGIC;
signal \sw[4]_IBUF\ : STD_LOGIC;
signal \sw[5]\ : STD_LOGIC;
signal \sw[5]_IBUF\ : STD_LOGIC;
signal \sw[6]\ : STD_LOGIC;
signal \sw[6]_IBUF\ : STD_LOGIC;
signal \sw[7]\ : STD_LOGIC;
signal \sw[7]_IBUF\ : STD_LOGIC;
signal \sw[8]\ : STD_LOGIC;
signal \sw[8]_IBUF\ : STD_LOGIC;
signal \sw[9]\ : STD_LOGIC;
signal \sw[9]_IBUF\ : STD_LOGIC;
signal vgaBlue_OBUF : STD_LOGIC_VECTOR ( 0 to 0 );
signal \PS2Clk^Mid\ : STD_LOGIC;
signal \PS2Data^Mid\ : STD_LOGIC;
signal \NLW_counter_reg[12]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[12]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[13]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[22]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_counter_reg[22]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[22]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[22]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[22]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[22]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[3]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[4]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[8]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_counter_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_fb_in_addr_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_fb_in_addr_reg[3]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_fb_in_addr_reg[7]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute OPT_INSERTED : boolean;
attribute OPT_INSERTED of btnC_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnD_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnL_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnR_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnU_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of clk_IBUF_inst : label is std.standard.true;
attribute syn_black_box : string;
attribute syn_black_box of clock0 : label is "TRUE";
attribute syn_black_box of frameBuffer0 : label is "TRUE";
attribute x_core_info : string;
attribute x_core_info of frameBuffer0 : label is "blk_mem_gen_v8_3_1,Vivado 2015.4";
attribute OPT_INSERTED of \sw[0]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[10]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[11]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[12]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[13]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[14]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[15]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[1]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[2]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[3]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[4]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[5]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[6]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[7]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[8]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[9]_IBUF_inst\ : label is std.standard.true;
begin
\PS2Clk^Mid\ <= PS2Clk;
\PS2Data^Mid\ <= PS2Data;
\sw[0]\ <= sw(0);
\sw[10]\ <= sw(10);
\sw[11]\ <= sw(11);
\sw[12]\ <= sw(12);
\sw[13]\ <= sw(13);
\sw[14]\ <= sw(14);
\sw[15]\ <= sw(15);
\sw[1]\ <= sw(1);
\sw[2]\ <= sw(2);
\sw[3]\ <= sw(3);
\sw[4]\ <= sw(4);
\sw[5]\ <= sw(5);
\sw[6]\ <= sw(6);
\sw[7]\ <= sw(7);
\sw[8]\ <= sw(8);
\sw[9]\ <= sw(9);
\pullup_PS2Clk^Midinst\: unisim.vcomponents.PULLUP
port map (
O => \PS2Clk^Mid\
);
\pullup_PS2Data^Midinst\: unisim.vcomponents.PULLUP
port map (
O => \PS2Data^Mid\
);
led(0) <= 'Z';
led(1) <= 'Z';
led(2) <= 'Z';
led(3) <= 'Z';
led(4) <= 'Z';
led(5) <= 'Z';
led(6) <= 'Z';
led(7) <= 'Z';
led(8) <= 'Z';
led(9) <= 'Z';
led(10) <= 'Z';
led(11) <= 'Z';
led(12) <= 'Z';
led(13) <= 'Z';
led(14) <= 'Z';
led(15) <= 'Z';
Hsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => Hsync_OBUF,
O => Hsync
);
PS2Clk_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => \PS2Clk^Mid\,
O => PS2Clk_IBUF
);
PS2Data_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => \PS2Data^Mid\,
O => PS2Data_IBUF
);
Vsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => Vsync_OBUF,
O => Vsync
);
btnC_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnC,
O => btnC_IBUF
);
btnD_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnD,
O => btnD_IBUF
);
btnL_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnL,
O => btnL_IBUF
);
btnR_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnR,
O => btnR_IBUF
);
btnU_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnU,
O => btnU_IBUF
);
clk_1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAAD5555555"
)
port map (
I0 => \counter_reg[22]_i_3_n_3\,
I1 => clk_1_i_2_n_0,
I2 => clk_1_i_3_n_0,
I3 => clk_1_i_4_n_0,
I4 => clk_1_i_5_n_0,
I5 => clk_1_reg_n_0,
O => clk_1_i_1_n_0
);
clk_1_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \counter_reg[16]_i_1_n_6\,
I1 => \counter_reg[16]_i_1_n_5\,
I2 => \counter_reg[12]__0_i_1_n_4\,
I3 => \counter_reg[16]_i_1_n_7\,
I4 => \counter_reg[20]_i_1_n_7\,
I5 => \counter_reg[16]_i_1_n_4\,
O => clk_1_i_2_n_0
);
clk_1_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \counter_reg[20]_i_1_n_4\,
I1 => \counter_reg[22]_i_2_n_7\,
I2 => \counter_reg[20]_i_1_n_6\,
I3 => \counter_reg[20]_i_1_n_5\,
I4 => \counter_reg[22]_i_2_n_6\,
I5 => \counter_reg[0]__0_n_0\,
O => clk_1_i_3_n_0
);
clk_1_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \counter_reg[8]__0_i_1_n_4\,
I1 => \counter_reg[12]__0_i_1_n_7\,
I2 => \counter_reg[8]__0_i_1_n_6\,
I3 => \counter_reg[8]__0_i_1_n_5\,
I4 => \counter_reg[12]__0_i_1_n_5\,
I5 => \counter_reg[12]__0_i_1_n_6\,
O => clk_1_i_4_n_0
);
clk_1_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter_reg[4]__0_i_1_n_7\,
I1 => \counter_reg[4]__0_i_1_n_6\,
I2 => \counter_reg[4]__0_i_1_n_5\,
I3 => \counter_reg[8]__0_i_1_n_7\,
I4 => \counter_reg[4]__0_i_1_n_4\,
O => clk_1_i_5_n_0
);
clk_1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => clk_1_i_1_n_0,
Q => clk_1_reg_n_0,
R => '0'
);
clk_BUFG_inst: unisim.vcomponents.BUFG
port map (
I => clk_IBUF,
O => clk_BUFG
);
clk_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => clk,
O => clk_IBUF
);
clock0: entity work.ClockDivider
port map (
clk108M => clk108M,
clk10M => clk10M,
clkIn => clk_BUFG
);
\counter[0]__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[0]__0_n_0\,
O => \counter[0]__0_i_1_n_0\
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[0]\,
O => \counter[0]_i_1_n_0\
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[10]_i_1_n_0\
);
\counter[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[13]_i_5_n_7\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[13]_i_2_n_0\
);
\counter[13]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \counter_reg_n_0_[4]\,
I1 => \counter_reg_n_0_[2]\,
I2 => \counter_reg_n_0_[1]\,
I3 => \counter[13]_i_7_n_0\,
I4 => \g0_b6__0_i_6_n_0\,
O => \counter[13]_i_3_n_0\
);
\counter[13]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => current_s(0),
O => \counter[13]_i_4_n_0\
);
\counter[13]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => current_s(0),
I2 => current_s(1),
O => \counter[13]_i_6_n_0\
);
\counter[13]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \counter_reg_n_0_[13]\,
I1 => \counter_reg_n_0_[0]\,
I2 => \counter_reg_n_0_[11]\,
I3 => \counter_reg_n_0_[3]\,
O => \counter[13]_i_7_n_0\
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[3]_i_1_n_7\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[1]_i_1_n_0\
);
\counter[22]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[22]_i_3_n_3\,
O => \counter[22]_i_1_n_0\
);
\counter[22]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \counter_reg_n_0_[18]\,
I1 => \counter_reg_n_0_[19]\,
O => \counter[22]_i_10_n_0\
);
\counter[22]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[14]\,
I1 => \counter_reg_n_0_[15]\,
O => \counter[22]_i_11_n_0\
);
\counter[22]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[20]\,
I1 => \counter_reg_n_0_[21]\,
O => \counter[22]_i_12_n_0\
);
\counter[22]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg_n_0_[18]\,
I1 => \counter_reg_n_0_[19]\,
O => \counter[22]_i_13_n_0\
);
\counter[22]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[16]\,
I1 => \counter_reg_n_0_[17]\,
O => \counter[22]_i_14_n_0\
);
\counter[22]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[14]\,
I1 => \counter_reg_n_0_[15]\,
O => \counter[22]_i_15_n_0\
);
\counter[22]_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[11]__0_n_0\,
O => \counter[22]_i_16_n_0\
);
\counter[22]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \counter_reg[8]__0_n_0\,
I1 => \counter_reg[9]__0_n_0\,
O => \counter[22]_i_17_n_0\
);
\counter[22]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[6]__0_n_0\,
I1 => \counter_reg[7]__0_n_0\,
O => \counter[22]_i_18_n_0\
);
\counter[22]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[12]__0_n_0\,
I1 => \counter_reg[13]__0_n_0\,
O => \counter[22]_i_19_n_0\
);
\counter[22]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[11]__0_n_0\,
I1 => \counter_reg[10]__0_n_0\,
O => \counter[22]_i_20_n_0\
);
\counter[22]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[8]__0_n_0\,
I1 => \counter_reg[9]__0_n_0\,
O => \counter[22]_i_21_n_0\
);
\counter[22]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[6]__0_n_0\,
I1 => \counter_reg[7]__0_n_0\,
O => \counter[22]_i_22_n_0\
);
\counter[22]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[22]\,
O => \counter[22]_i_7_n_0\
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[3]_i_1_n_6\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[2]_i_1_n_0\
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[3]_i_1_n_4\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[4]_i_1_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[5]_i_1_n_0\
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[6]_i_1_n_0\
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[7]_i_1_n_0\
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[8]_i_1_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF01FF0FFF01"
)
port map (
I0 => \counter[13]_i_3_n_0\,
I1 => current_s(1),
I2 => \counter[13]_i_4_n_0\,
I3 => \next_s[1]_i_2_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[13]_i_6_n_0\,
O => \counter[9]_i_1_n_0\
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[0]_i_1_n_0\,
Q => \counter_reg_n_0_[0]\,
R => keyboard0_n_10
);
\counter_reg[0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter[0]__0_i_1_n_0\,
Q => \counter_reg[0]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[10]_i_1_n_0\,
Q => \counter_reg_n_0_[10]\,
R => '0'
);
\counter_reg[10]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_6\,
Q => \counter_reg[10]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter_reg[12]_i_2_n_5\,
Q => \counter_reg_n_0_[11]\,
R => keyboard0_n_10
);
\counter_reg[11]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_5\,
Q => \counter_reg[11]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter_reg[12]_i_2_n_4\,
Q => \counter_reg_n_0_[12]\,
R => keyboard0_n_10
);
\counter_reg[12]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_4\,
Q => \counter_reg[12]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[12]__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]__0_i_1_n_0\,
CO(3) => \counter_reg[12]__0_i_1_n_0\,
CO(2 downto 0) => \NLW_counter_reg[12]__0_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]__0_i_1_n_4\,
O(2) => \counter_reg[12]__0_i_1_n_5\,
O(1) => \counter_reg[12]__0_i_1_n_6\,
O(0) => \counter_reg[12]__0_i_1_n_7\,
S(3) => \counter_reg[12]__0_n_0\,
S(2) => \counter_reg[11]__0_n_0\,
S(1) => \counter_reg[10]__0_n_0\,
S(0) => \counter_reg[9]__0_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2 downto 0) => \NLW_counter_reg[12]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter_reg_n_0_[12]\,
S(2) => \counter_reg_n_0_[11]\,
S(1) => \counter_reg_n_0_[10]\,
S(0) => \counter_reg_n_0_[9]\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[13]_i_2_n_0\,
Q => \counter_reg_n_0_[13]\,
R => '0'
);
\counter_reg[13]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_7\,
Q => \counter_reg[13]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[13]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3 downto 0) => \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_counter_reg[13]_i_5_O_UNCONNECTED\(3 downto 1),
O(0) => \counter_reg[13]_i_5_n_7\,
S(3 downto 1) => B"000",
S(0) => \counter_reg_n_0_[13]\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_6\,
Q => \counter_reg_n_0_[14]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_5\,
Q => \counter_reg_n_0_[15]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_4\,
Q => \counter_reg_n_0_[16]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]__0_i_1_n_0\,
CO(3) => \counter_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_counter_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_1_n_4\,
O(2) => \counter_reg[16]_i_1_n_5\,
O(1) => \counter_reg[16]_i_1_n_6\,
O(0) => \counter_reg[16]_i_1_n_7\,
S(3) => \counter_reg_n_0_[16]\,
S(2) => \counter_reg_n_0_[15]\,
S(1) => \counter_reg_n_0_[14]\,
S(0) => \counter_reg[13]__0_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_7\,
Q => \counter_reg_n_0_[17]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_6\,
Q => \counter_reg_n_0_[18]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_5\,
Q => \counter_reg_n_0_[19]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[1]_i_1_n_0\,
Q => \counter_reg_n_0_[1]\,
R => '0'
);
\counter_reg[1]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_7\,
Q => \counter_reg[1]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_4\,
Q => \counter_reg_n_0_[20]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_1_n_0\,
CO(3) => \counter_reg[20]_i_1_n_0\,
CO(2 downto 0) => \NLW_counter_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_1_n_4\,
O(2) => \counter_reg[20]_i_1_n_5\,
O(1) => \counter_reg[20]_i_1_n_6\,
O(0) => \counter_reg[20]_i_1_n_7\,
S(3) => \counter_reg_n_0_[20]\,
S(2) => \counter_reg_n_0_[19]\,
S(1) => \counter_reg_n_0_[18]\,
S(0) => \counter_reg_n_0_[17]\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[22]_i_2_n_7\,
Q => \counter_reg_n_0_[21]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[22]_i_2_n_6\,
Q => \counter_reg_n_0_[22]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[22]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_1_n_0\,
CO(3 downto 0) => \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_counter_reg[22]_i_2_O_UNCONNECTED\(3 downto 2),
O(1) => \counter_reg[22]_i_2_n_6\,
O(0) => \counter_reg[22]_i_2_n_7\,
S(3 downto 2) => B"00",
S(1) => \counter_reg_n_0_[22]\,
S(0) => \counter_reg_n_0_[21]\
);
\counter_reg[22]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[22]_i_6_n_0\,
CO(3 downto 1) => \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \counter_reg[22]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \counter[22]_i_7_n_0\,
O(3 downto 0) => \NLW_counter_reg[22]_i_3_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \counter_reg_n_0_[22]\
);
\counter_reg[22]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[22]_i_9_n_0\,
CO(3) => \counter_reg[22]_i_6_n_0\,
CO(2 downto 0) => \NLW_counter_reg[22]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \counter[22]_i_10_n_0\,
DI(1) => '0',
DI(0) => \counter[22]_i_11_n_0\,
O(3 downto 0) => \NLW_counter_reg[22]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \counter[22]_i_12_n_0\,
S(2) => \counter[22]_i_13_n_0\,
S(1) => \counter[22]_i_14_n_0\,
S(0) => \counter[22]_i_15_n_0\
);
\counter_reg[22]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[22]_i_9_n_0\,
CO(2 downto 0) => \NLW_counter_reg[22]_i_9_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \counter[22]_i_16_n_0\,
DI(1) => \counter[22]_i_17_n_0\,
DI(0) => \counter[22]_i_18_n_0\,
O(3 downto 0) => \NLW_counter_reg[22]_i_9_O_UNCONNECTED\(3 downto 0),
S(3) => \counter[22]_i_19_n_0\,
S(2) => \counter[22]_i_20_n_0\,
S(1) => \counter[22]_i_21_n_0\,
S(0) => \counter[22]_i_22_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[2]_i_1_n_0\,
Q => \counter_reg_n_0_[2]\,
R => '0'
);
\counter_reg[2]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_6\,
Q => \counter_reg[2]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter_reg[3]_i_1_n_5\,
Q => \counter_reg_n_0_[3]\,
R => keyboard0_n_10
);
\counter_reg[3]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_5\,
Q => \counter_reg[3]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[3]_i_1_n_0\,
CO(2 downto 0) => \NLW_counter_reg[3]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => \counter_reg_n_0_[0]\,
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[3]_i_1_n_4\,
O(2) => \counter_reg[3]_i_1_n_5\,
O(1) => \counter_reg[3]_i_1_n_6\,
O(0) => \counter_reg[3]_i_1_n_7\,
S(3) => \counter_reg_n_0_[4]\,
S(2) => \counter_reg_n_0_[3]\,
S(1) => \counter_reg_n_0_[2]\,
S(0) => \counter_reg_n_0_[1]\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[4]_i_1_n_0\,
Q => \counter_reg_n_0_[4]\,
R => '0'
);
\counter_reg[4]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_4\,
Q => \counter_reg[4]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[4]__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]__0_i_1_n_0\,
CO(2 downto 0) => \NLW_counter_reg[4]__0_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => \counter_reg[0]__0_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]__0_i_1_n_4\,
O(2) => \counter_reg[4]__0_i_1_n_5\,
O(1) => \counter_reg[4]__0_i_1_n_6\,
O(0) => \counter_reg[4]__0_i_1_n_7\,
S(3) => \counter_reg[4]__0_n_0\,
S(2) => \counter_reg[3]__0_n_0\,
S(1) => \counter_reg[2]__0_n_0\,
S(0) => \counter_reg[1]__0_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[5]_i_1_n_0\,
Q => \counter_reg_n_0_[5]\,
R => '0'
);
\counter_reg[5]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_7\,
Q => \counter_reg[5]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[6]_i_1_n_0\,
Q => \counter_reg_n_0_[6]\,
R => '0'
);
\counter_reg[6]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_6\,
Q => \counter_reg[6]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[7]_i_1_n_0\,
Q => \counter_reg_n_0_[7]\,
R => '0'
);
\counter_reg[7]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_5\,
Q => \counter_reg[7]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[8]_i_1_n_0\,
Q => \counter_reg_n_0_[8]\,
R => '0'
);
\counter_reg[8]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_4\,
Q => \counter_reg[8]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[8]__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]__0_i_1_n_0\,
CO(3) => \counter_reg[8]__0_i_1_n_0\,
CO(2 downto 0) => \NLW_counter_reg[8]__0_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]__0_i_1_n_4\,
O(2) => \counter_reg[8]__0_i_1_n_5\,
O(1) => \counter_reg[8]__0_i_1_n_6\,
O(0) => \counter_reg[8]__0_i_1_n_7\,
S(3) => \counter_reg[8]__0_n_0\,
S(2) => \counter_reg[7]__0_n_0\,
S(1) => \counter_reg[6]__0_n_0\,
S(0) => \counter_reg[5]__0_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[3]_i_1_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2 downto 0) => \NLW_counter_reg[8]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter_reg_n_0_[8]\,
S(2) => \counter_reg_n_0_[7]\,
S(1) => \counter_reg_n_0_[6]\,
S(0) => \counter_reg_n_0_[5]\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \counter[9]_i_1_n_0\,
Q => \counter_reg_n_0_[9]\,
R => '0'
);
\counter_reg[9]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_7\,
Q => \counter_reg[9]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\current_s_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => next_s(0),
Q => current_s(0),
R => '0'
);
\current_s_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => next_s(1),
Q => current_s(1),
R => '0'
);
\fb_in_addr[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"11F100E0"
)
port map (
I0 => current_s(1),
I1 => current_s(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter_reg_n_0_[0]\,
I4 => fb_in_addr0(0),
O => \fb_in_addr[0]_i_1_n_0\
);
\fb_in_addr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(10),
I1 => \counter_reg[12]_i_2_n_6\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[10]_i_1_n_0\
);
\fb_in_addr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F111E000"
)
port map (
I0 => current_s(1),
I1 => current_s(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter_reg[12]_i_2_n_5\,
I4 => fb_in_addr0(11),
O => \fb_in_addr[11]_i_1_n_0\
);
\fb_in_addr[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[12]_i_2_n_5\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[11]_i_3_n_0\
);
\fb_in_addr[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[12]_i_2_n_6\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[11]_i_4_n_0\
);
\fb_in_addr[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[8]_i_2_n_4\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[11]_i_5_n_0\
);
\fb_in_addr[11]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[12]_i_2_n_5\,
O => \fb_in_addr[11]_i_6_n_0\
);
\fb_in_addr[11]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[12]_i_2_n_6\,
O => \fb_in_addr[11]_i_7_n_0\
);
\fb_in_addr[11]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[12]_i_2_n_7\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[11]_i_8_n_0\
);
\fb_in_addr[11]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[8]_i_2_n_4\,
O => \fb_in_addr[11]_i_9_n_0\
);
\fb_in_addr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F111E000"
)
port map (
I0 => current_s(1),
I1 => current_s(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter_reg[12]_i_2_n_4\,
I4 => fb_in_addr0(12),
O => \fb_in_addr[12]_i_1_n_0\
);
\fb_in_addr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(13),
I1 => \counter_reg[13]_i_5_n_7\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[13]_i_1_n_0\
);
\fb_in_addr[13]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[13]_i_5_n_7\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[13]_i_3_n_0\
);
\fb_in_addr[13]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[12]_i_2_n_4\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[13]_i_4_n_0\
);
\fb_in_addr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(1),
I1 => \counter_reg[3]_i_1_n_7\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[1]_i_1_n_0\
);
\fb_in_addr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(2),
I1 => \counter_reg[3]_i_1_n_6\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[2]_i_1_n_0\
);
\fb_in_addr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F111E000"
)
port map (
I0 => current_s(1),
I1 => current_s(0),
I2 => \counter[13]_i_3_n_0\,
I3 => \counter_reg[3]_i_1_n_5\,
I4 => fb_in_addr0(3),
O => \fb_in_addr[3]_i_1_n_0\
);
\fb_in_addr[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[3]_i_1_n_7\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[3]_i_3_n_0\
);
\fb_in_addr[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[3]_i_1_n_5\,
O => \fb_in_addr[3]_i_4_n_0\
);
\fb_in_addr[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[3]_i_1_n_6\,
O => \fb_in_addr[3]_i_5_n_0\
);
\fb_in_addr[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[3]_i_1_n_7\,
O => \fb_in_addr[3]_i_6_n_0\
);
\fb_in_addr[3]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg_n_0_[0]\,
O => \fb_in_addr[3]_i_7_n_0\
);
\fb_in_addr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(4),
I1 => \counter_reg[3]_i_1_n_4\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[4]_i_1_n_0\
);
\fb_in_addr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(5),
I1 => \counter_reg[8]_i_2_n_7\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[5]_i_1_n_0\
);
\fb_in_addr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(6),
I1 => \counter_reg[8]_i_2_n_6\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[6]_i_1_n_0\
);
\fb_in_addr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(7),
I1 => \counter_reg[8]_i_2_n_5\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[7]_i_1_n_0\
);
\fb_in_addr[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[8]_i_2_n_6\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[7]_i_3_n_0\
);
\fb_in_addr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[8]_i_2_n_7\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[7]_i_4_n_0\
);
\fb_in_addr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[8]_i_2_n_5\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[7]_i_5_n_0\
);
\fb_in_addr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[8]_i_2_n_6\,
O => \fb_in_addr[7]_i_6_n_0\
);
\fb_in_addr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \g0_b6__0_i_1_n_0\,
I1 => \counter_reg[8]_i_2_n_7\,
O => \fb_in_addr[7]_i_7_n_0\
);
\fb_in_addr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[3]_i_1_n_4\,
I1 => \g0_b6__0_i_1_n_0\,
O => \fb_in_addr[7]_i_8_n_0\
);
\fb_in_addr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(8),
I1 => \counter_reg[8]_i_2_n_4\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[8]_i_1_n_0\
);
\fb_in_addr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCA0FFA"
)
port map (
I0 => fb_in_addr0(9),
I1 => \counter_reg[12]_i_2_n_7\,
I2 => current_s(0),
I3 => current_s(1),
I4 => \counter[13]_i_3_n_0\,
O => \fb_in_addr[9]_i_1_n_0\
);
\fb_in_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[0]_i_1_n_0\,
Q => addra(0),
R => '0'
);
\fb_in_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[10]_i_1_n_0\,
Q => addra(10),
R => '0'
);
\fb_in_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[11]_i_1_n_0\,
Q => addra(11),
R => '0'
);
\fb_in_addr_reg[11]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \fb_in_addr_reg[7]_i_2_n_0\,
CO(3) => \fb_in_addr_reg[11]_i_2_n_0\,
CO(2 downto 0) => \NLW_fb_in_addr_reg[11]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \fb_in_addr[11]_i_3_n_0\,
DI(2) => \fb_in_addr[11]_i_4_n_0\,
DI(1) => '0',
DI(0) => \fb_in_addr[11]_i_5_n_0\,
O(3 downto 0) => fb_in_addr0(11 downto 8),
S(3) => \fb_in_addr[11]_i_6_n_0\,
S(2) => \fb_in_addr[11]_i_7_n_0\,
S(1) => \fb_in_addr[11]_i_8_n_0\,
S(0) => \fb_in_addr[11]_i_9_n_0\
);
\fb_in_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[12]_i_1_n_0\,
Q => addra(12),
R => '0'
);
\fb_in_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[13]_i_1_n_0\,
Q => addra(13),
R => '0'
);
\fb_in_addr_reg[13]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \fb_in_addr_reg[11]_i_2_n_0\,
CO(3 downto 0) => \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => fb_in_addr0(13 downto 12),
S(3 downto 2) => B"00",
S(1) => \fb_in_addr[13]_i_3_n_0\,
S(0) => \fb_in_addr[13]_i_4_n_0\
);
\fb_in_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[1]_i_1_n_0\,
Q => addra(1),
R => '0'
);
\fb_in_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[2]_i_1_n_0\,
Q => addra(2),
R => '0'
);
\fb_in_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[3]_i_1_n_0\,
Q => addra(3),
R => '0'
);
\fb_in_addr_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \fb_in_addr_reg[3]_i_2_n_0\,
CO(2 downto 0) => \NLW_fb_in_addr_reg[3]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \fb_in_addr[3]_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => fb_in_addr0(3 downto 0),
S(3) => \fb_in_addr[3]_i_4_n_0\,
S(2) => \fb_in_addr[3]_i_5_n_0\,
S(1) => \fb_in_addr[3]_i_6_n_0\,
S(0) => \fb_in_addr[3]_i_7_n_0\
);
\fb_in_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[4]_i_1_n_0\,
Q => addra(4),
R => '0'
);
\fb_in_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[5]_i_1_n_0\,
Q => addra(5),
R => '0'
);
\fb_in_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[6]_i_1_n_0\,
Q => addra(6),
R => '0'
);
\fb_in_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[7]_i_1_n_0\,
Q => addra(7),
R => '0'
);
\fb_in_addr_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \fb_in_addr_reg[3]_i_2_n_0\,
CO(3) => \fb_in_addr_reg[7]_i_2_n_0\,
CO(2 downto 0) => \NLW_fb_in_addr_reg[7]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \fb_in_addr[7]_i_3_n_0\,
DI(1) => \fb_in_addr[7]_i_4_n_0\,
DI(0) => '0',
O(3 downto 0) => fb_in_addr0(7 downto 4),
S(3) => \fb_in_addr[7]_i_5_n_0\,
S(2) => \fb_in_addr[7]_i_6_n_0\,
S(1) => \fb_in_addr[7]_i_7_n_0\,
S(0) => \fb_in_addr[7]_i_8_n_0\
);
\fb_in_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[8]_i_1_n_0\,
Q => addra(8),
R => '0'
);
\fb_in_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => \fb_in_addr[9]_i_1_n_0\,
Q => addra(9),
R => '0'
);
\fb_in_dat[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => clk_1_reg_n_0,
I1 => current_s(1),
I2 => current_s(0),
O => fb_in_dat(7)
);
\fb_in_dat_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(0),
Q => dina(0),
R => '0'
);
\fb_in_dat_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(1),
Q => dina(1),
R => '0'
);
\fb_in_dat_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(2),
Q => dina(2),
R => '0'
);
\fb_in_dat_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(3),
Q => dina(3),
R => '0'
);
\fb_in_dat_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(4),
Q => dina(4),
R => '0'
);
\fb_in_dat_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(5),
Q => dina(5),
R => '0'
);
\fb_in_dat_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(6),
Q => dina(6),
R => '0'
);
\fb_in_dat_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_2,
D => fb_in_dat(7),
Q => dina(7),
R => '0'
);
frameBuffer0: entity work.FrameBuffer
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => fbOutAddr(13 downto 0),
clka => clk_BUFG,
clkb => clk108M,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => '1'
);
\g0_b0__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F40F40FBBBFB0"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \g0_b6__0_i_2_n_0\,
I3 => \g0_b6__0_i_3_n_0\,
I4 => \g0_b6__0_i_4_n_0\,
I5 => \g0_b6__0_i_5_n_0\,
O => \g0_b0__0_n_0\
);
\g0_b1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04F0B4F400B40F40"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \g0_b6__0_i_2_n_0\,
I3 => \g0_b6__0_i_3_n_0\,
I4 => \g0_b6__0_i_4_n_0\,
I5 => \g0_b6__0_i_5_n_0\,
O => \g0_b1__0_n_0\
);
\g0_b2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04FFBFB4B40400B0"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \g0_b6__0_i_2_n_0\,
I3 => \g0_b6__0_i_3_n_0\,
I4 => \g0_b6__0_i_4_n_0\,
I5 => \g0_b6__0_i_5_n_0\,
O => \g0_b2__0_n_0\
);
\g0_b3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04F0F4B40BBF0000"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \g0_b6__0_i_2_n_0\,
I3 => \g0_b6__0_i_3_n_0\,
I4 => \g0_b6__0_i_4_n_0\,
I5 => \g0_b6__0_i_5_n_0\,
O => \g0_b3__0_n_0\
);
\g0_b4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00040B00BB0B0F4B"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \g0_b6__0_i_2_n_0\,
I3 => \g0_b6__0_i_3_n_0\,
I4 => \g0_b6__0_i_4_n_0\,
I5 => \g0_b6__0_i_5_n_0\,
O => \g0_b4__0_n_0\
);
\g0_b5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"04FFFFFFFFFFFFF0"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \g0_b6__0_i_2_n_0\,
I3 => \g0_b6__0_i_3_n_0\,
I4 => \g0_b6__0_i_4_n_0\,
I5 => \g0_b6__0_i_5_n_0\,
O => \g0_b5__0_n_0\
);
\g0_b6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000FFFF4BFBFBFFB"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \g0_b6__0_i_2_n_0\,
I3 => \g0_b6__0_i_3_n_0\,
I4 => \g0_b6__0_i_4_n_0\,
I5 => \g0_b6__0_i_5_n_0\,
O => \g0_b6__0_n_0\
);
\g0_b6__0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000007F"
)
port map (
I0 => \counter_reg_n_0_[4]\,
I1 => \counter_reg_n_0_[2]\,
I2 => \counter_reg_n_0_[3]\,
I3 => \counter_reg_n_0_[11]\,
I4 => \counter_reg_n_0_[13]\,
I5 => \g0_b6__0_i_6_n_0\,
O => \g0_b6__0_i_1_n_0\
);
\g0_b6__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"84"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b6__0_i_1_n_0\,
I2 => \counter_reg[3]_i_1_n_7\,
O => \g0_b6__0_i_2_n_0\
);
\g0_b6__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"D020"
)
port map (
I0 => \counter_reg[3]_i_1_n_7\,
I1 => \counter_reg_n_0_[0]\,
I2 => \g0_b6__0_i_1_n_0\,
I3 => \counter_reg[3]_i_1_n_6\,
O => \g0_b6__0_i_3_n_0\
);
\g0_b6__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"A060A0A0"
)
port map (
I0 => \counter_reg[3]_i_1_n_5\,
I1 => \counter_reg[3]_i_1_n_6\,
I2 => \g0_b6__0_i_1_n_0\,
I3 => \counter_reg_n_0_[0]\,
I4 => \counter_reg[3]_i_1_n_7\,
O => \g0_b6__0_i_4_n_0\
);
\g0_b6__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"D0F0F0F020000000"
)
port map (
I0 => \counter_reg[3]_i_1_n_7\,
I1 => \counter_reg_n_0_[0]\,
I2 => \g0_b6__0_i_1_n_0\,
I3 => \counter_reg[3]_i_1_n_6\,
I4 => \counter_reg[3]_i_1_n_5\,
I5 => \counter_reg[3]_i_1_n_4\,
O => \g0_b6__0_i_5_n_0\
);
\g0_b6__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \g0_b6__0_i_7_n_0\,
I1 => \counter_reg_n_0_[7]\,
I2 => \counter_reg_n_0_[9]\,
I3 => \counter_reg_n_0_[8]\,
O => \g0_b6__0_i_6_n_0\
);
\g0_b6__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \counter_reg_n_0_[6]\,
I1 => \counter_reg_n_0_[5]\,
I2 => \counter_reg_n_0_[10]\,
I3 => \counter_reg_n_0_[12]\,
O => \g0_b6__0_i_7_n_0\
);
keyboard0: entity work.ps2_keyboard_to_ascii
port map (
D(1 downto 0) => next_s(1 downto 0),
PS2Clk_IBUF => PS2Clk_IBUF,
PS2Data_IBUF => PS2Data_IBUF,
Q(1 downto 0) => current_s(1 downto 0),
clk_BUFG => clk_BUFG,
\counter_reg[0]\ => keyboard0_n_2,
\counter_reg[0]_0\ => \g0_b0__0_n_0\,
\counter_reg[0]_1\ => \g0_b1__0_n_0\,
\counter_reg[0]_2\ => \g0_b2__0_n_0\,
\counter_reg[0]_3\ => \g0_b3__0_n_0\,
\counter_reg[0]_4\ => \g0_b4__0_n_0\,
\counter_reg[0]_5\ => \g0_b5__0_n_0\,
\counter_reg[0]_6\ => \g0_b6__0_n_0\,
\counter_reg[12]\ => keyboard0_n_10,
\counter_reg[4]\ => \g0_b6__0_i_1_n_0\,
\counter_reg[4]_0\ => \counter[13]_i_3_n_0\,
\current_s_reg[0]\ => \next_s[1]_i_2_n_0\,
\fb_in_dat_reg[6]\(6 downto 0) => fb_in_dat(6 downto 0),
\next_s_reg[0]\ => keyboard0_n_1,
\next_s_reg[1]\ => keyboard0_n_0
);
\next_s[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => current_s(0),
I1 => current_s(1),
I2 => \counter[13]_i_3_n_0\,
O => \next_s[1]_i_2_n_0\
);
\next_s_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => keyboard0_n_1,
Q => next_s(0),
R => '0'
);
\next_s_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => keyboard0_n_0,
Q => next_s(1),
R => '0'
);
\sw[0]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[0]\,
O => \sw[0]_IBUF\
);
\sw[10]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[10]\,
O => \sw[10]_IBUF\
);
\sw[11]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[11]\,
O => \sw[11]_IBUF\
);
\sw[12]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[12]\,
O => \sw[12]_IBUF\
);
\sw[13]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[13]\,
O => \sw[13]_IBUF\
);
\sw[14]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[14]\,
O => \sw[14]_IBUF\
);
\sw[15]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[15]\,
O => \sw[15]_IBUF\
);
\sw[1]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[1]\,
O => \sw[1]_IBUF\
);
\sw[2]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[2]\,
O => \sw[2]_IBUF\
);
\sw[3]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[3]\,
O => \sw[3]_IBUF\
);
\sw[4]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[4]\,
O => \sw[4]_IBUF\
);
\sw[5]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[5]\,
O => \sw[5]_IBUF\
);
\sw[6]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[6]\,
O => \sw[6]_IBUF\
);
\sw[7]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[7]\,
O => \sw[7]_IBUF\
);
\sw[8]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[8]\,
O => \sw[8]_IBUF\
);
\sw[9]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[9]\,
O => \sw[9]_IBUF\
);
vga0: entity work.Vga
port map (
D(7 downto 0) => doutb(7 downto 0),
Hsync_OBUF => Hsync_OBUF,
Vsync_OBUF => Vsync_OBUF,
addrb(13 downto 0) => fbOutAddr(13 downto 0),
clk108M => clk108M,
vgaBlue_OBUF(0) => vgaBlue_OBUF(0)
);
\vgaBlue_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(0)
);
\vgaBlue_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(1)
);
\vgaBlue_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(2)
);
\vgaBlue_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(3)
);
\vgaGreen_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(0)
);
\vgaGreen_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(1)
);
\vgaGreen_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(2)
);
\vgaGreen_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(3)
);
\vgaRed_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(0)
);
\vgaRed_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(1)
);
\vgaRed_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(2)
);
\vgaRed_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(3)
);
end STRUCTURE;
|
mit
|
d185a2a84a3e86863370db7fc4b67060
| 0.538985 | 2.583178 | false | false | false | false |
luebbers/reconos
|
demos/resume_demo/hw/hwthreads/wait_and_yield/wait_and_yield.vhd
| 1 | 6,253 |
--!
--! \file wait_and_yield.vhd
--!
--! Benchmark for cooperative multithreading
--!
--! \author Enno Luebbers <[email protected]>
--! \date 13.03.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major Changes:
--
-- 13.03.2009 Enno Luebbers File created.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wait_and_yield is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_SUB_NADD : integer := 0 -- 0: ADD, 1: SUB
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end wait_and_yield;
architecture Behavioral of wait_and_yield is
-- OS synchronization state machine states
type state_t is (STATE_CHECK,
STATE_INIT,
STATE_WAIT_BEFORE,
STATE_DELAY,
STATE_RESUME,
STATE_WAIT_AFTER,
STATE_EXIT);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06");
constant decode : decode_t := (STATE_CHECK,
STATE_INIT,
STATE_WAIT_BEFORE,
STATE_DELAY,
STATE_RESUME,
STATE_WAIT_AFTER,
STATE_EXIT);
signal state : state_t := STATE_CHECK;
begin
-- tie RAM signals low (we don't use them)
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWe <= '0';
o_RAMClk <= '0';
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable next_state : state_t := STATE_CHECK;
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable delay : std_logic_vector(0 to C_OSIF_DATA_WIDTH/2-1) := (others => '0');
variable wait_before_after : std_logic_vector(0 to C_OSIF_DATA_WIDTH/2-2) := (others => '0'); -- possible values: 0..32767 (x 1.31 ms)
variable do_yield : std_logic := '0';
variable counter : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_CHECK;
next_state := STATE_CHECK;
resume_state_enc := (others => '0');
done := false;
success := false;
delay := (others => '0');
wait_before_after := (others => '0');
do_yield := '0';
counter := (others => '0');
init_data := (others => '0');
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if success then
next_state := decode(to_integer(unsigned(resume_state_enc)));
else
next_state := STATE_INIT;
end if;
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, init_data);
do_yield := init_data(0);
wait_before_after := init_data(1 to 15);
delay := init_data(16 to 31);
counter := wait_before_after & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT_BEFORE;
when STATE_WAIT_BEFORE =>
if counter = X"00000000" then
next_state := STATE_DELAY;
else
counter := counter - 1;
end if;
when STATE_DELAY =>
reconos_thread_delay(o_osif, i_osif, (X"0000" & delay)); -- delay for 'delay' timer ticks
if do_yield = '1' then
reconos_flag_yield(o_osif, i_osif, encode(STATE_RESUME));
end if;
counter := wait_before_after & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT_AFTER;
when STATE_RESUME =>
reconos_get_init_data(done, o_osif, i_osif, init_data);
wait_before_after := init_data(1 to 15);
counter := wait_before_after & "0" & X"0000"; -- x 1.31 ms
next_state := STATE_WAIT_AFTER;
when STATE_WAIT_AFTER =>
if counter = X"00000000" then
next_state := STATE_EXIT;
else
counter := counter - 1;
end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
next_state := STATE_EXIT;
end case;
if done then
state <= next_state;
end if;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
4f4b29a7219a10b0876b6e069ab484f6
| 0.476891 | 3.965124 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/TESTBENCH_ac97_core.vhd
| 4 | 14,282 |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_core.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
--
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read_strobe, reg_write_strobe : std_logic := '0';
signal reg_error : std_logic := '0';
signal reg_busy, reg_data_valid : std_logic;
signal play_left_accept, play_right_accept : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15) := (others =>'0');
signal PCM_Playback_Right: std_logic_vector(0 to 15) := (others => '0');
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
model : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Strobe => reg_read_strobe, --
AC97_Reg_Write_Strobe => reg_write_strobe, --
AC97_Reg_Busy => reg_busy, --
AC97_Reg_Error => reg_error, -- d
AC97_Reg_Read_Data_Valid => reg_data_valid, -- d
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Playback_Left_Accept => play_left_accept, -- d
PCM_Playback_Right_Accept => play_right_accept, -- d
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
CODEC_RDY => CODEC_RDY
);
-- simulate a 20 ns reset pulse
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
register_if_process: process
begin
--PCM_Playback_Right_Valid <= '0';
--PCM_Playback_Left_Valid <= '0';
reg_read_strobe <= '0';
reg_write_strobe <= '0';
reg_addr <= (others => '0');
--PCM_Playback_Left <= (others => '0');
--PCM_Playback_Right <= (others => '0');
-- wait for codec ready
test_no <= 0;
wait until CODEC_RDY='1';
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Perform a register write (to reset register)
test_no <= 1;
reg_addr <= "0000010";
reg_write_data <= X"A5A5";
wait until clk'event and clk='1';
reg_write_strobe <= '1';
wait until clk'event and clk='1';
reg_write_strobe <= '0';
reg_addr <= "0000000";
reg_write_data <= X"0000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
-- Perform a register read
test_no <= 2;
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
reg_addr <= "0000010";
wait until clk'event and clk='1';
reg_read_strobe <= '1';
wait until clk'event and clk='1';
reg_read_strobe <= '0';
reg_addr <= "0000000";
wait until clk'event and clk='1';
wait until reg_busy = '0';
test_no <= 3;
-- -- set default values
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- test_no <= 1;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 2;
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- test_no <= 3;
-- -- send a read command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_read <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_read <= '0';
-- wait;
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- Test process
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
play_data_process: process
type register_type is array(0 to 31) of std_logic_vector(15 downto 0);
variable play_data : register_type := (
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000",
X"0001", X"0002", X"0004", X"0008", X"0010", X"0020", X"0040", X"0080",
X"0100", X"0200", X"0400", X"0800", X"1000", X"2000", X"4000", X"8000"
);
variable count : integer := 0;
begin
wait until codec_rdy = '1';
for count in 0 to 31 loop
PCM_Playback_Left <= play_data(count);
PCM_Playback_Right <= play_data(count);
wait until play_left_accept = '1' and
play_right_accept = '1' and clk'event and clk='1';
wait until clk'event and clk='1';
wait until clk'event and clk='1';
end loop;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
gpl-3.0
|
c6f7ef4e02517a8cf6b38bff539ab7b3
| 0.521776 | 3.290025 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/physical/v6_gtxwizard_gtx_orig.vhd
| 1 | 35,802 |
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.5
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : v6_gtxwizard_gtx.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module V6_GTXWIZARD_GTX (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity V6_GTXWIZARD_GTX is
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE : string := "TXPLL";
-- Save power parameter
GTX_POWER_SAVE : bit_vector := "0000000000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
RXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT : out std_logic;
RXCHARISK_OUT : out std_logic;
RXDISPERR_OUT : out std_logic;
RXNOTINTABLE_OUT : out std_logic;
RXRUNDISP_OUT : out std_logic;
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN_IN : in std_logic;
RXENPCOMMAALIGN_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT : out std_logic_vector(7 downto 0);
RXRECCLK_OUT : out std_logic;
RXRESET_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXELECIDLE_OUT : out std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET_IN : in std_logic;
RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARDISPMODE_IN : in std_logic;
TXCHARDISPVAL_IN : in std_logic;
TXCHARISK_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(7 downto 0);
TXOUTCLK_OUT : out std_logic;
TXRESET_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic
);
end V6_GTXWIZARD_GTX;
architecture RTL of V6_GTXWIZARD_GTX is
--**************************** Signal Declarations ****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
-- RX Datapath signals
signal rxdata_i : std_logic_vector(31 downto 0);
signal rxchariscomma_float_i : std_logic_vector(2 downto 0);
signal rxcharisk_float_i : std_logic_vector(2 downto 0);
signal rxdisperr_float_i : std_logic_vector(2 downto 0);
signal rxnotintable_float_i : std_logic_vector(2 downto 0);
signal rxrundisp_float_i : std_logic_vector(2 downto 0);
-- TX Datapath signals
signal txdata_i : std_logic_vector(31 downto 0);
signal txkerr_float_i : std_logic_vector(2 downto 0);
signal txrundisp_float_i : std_logic_vector(2 downto 0);
--******************************** Main Body of Code***************************
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
------------------- GTX Datapath byte mapping -----------------
RXDATA_OUT <= rxdata_i(7 downto 0);
txdata_i <= (tied_to_ground_vec_i(23 downto 0) & TXDATA_IN);
----------------------------- GTX Instance --------------------------
gtxe1_i :GTXE1
generic map
(
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_GTXRESET_SPEEDUP => (GTX_SIM_GTXRESET_SPEEDUP),
SIM_TX_ELEC_IDLE_LEVEL => ("X"),
SIM_VERSION => ("2.0"),
SIM_TXREFCLK_SOURCE => ("000"),
SIM_RXREFCLK_SOURCE => ("000"),
----------------------------TX PLL----------------------------
TX_CLK_SOURCE => (GTX_TX_CLK_SOURCE),
TX_OVERSAMPLE_MODE => (FALSE),
TXPLL_COM_CFG => (x"21680a"),
TXPLL_CP_CFG => (x"0D"),
TXPLL_DIVSEL_FB => (2),
TXPLL_DIVSEL_OUT => (2),
TXPLL_DIVSEL_REF => (1),
TXPLL_DIVSEL45_FB => (5),
TXPLL_LKDET_CFG => ("111"),
TX_CLK25_DIVIDER => (5),
TXPLL_SATA => ("00"),
TX_TDCC_CFG => ("00"),
PMA_CAS_CLK_EN => (FALSE),
POWER_SAVE => (GTX_POWER_SAVE),
-------------------------TX Interface-------------------------
GEN_TXUSRCLK => (TRUE),
TX_DATA_WIDTH => (10),
TX_USRCLK_CFG => (x"00"),
TXOUTCLK_CTRL => ("TXPLLREFCLK_DIV1"),
TXOUTCLK_DLY => ("0000000000"),
--------------TX Buffering and Phase Alignment----------------
TX_PMADATA_OPT => ('0'),
PMA_TX_CFG => (x"80082"),
TX_BUFFER_USE => (TRUE),
TX_BYTECLK_CFG => (x"00"),
TX_EN_RATE_RESET_BUF => (TRUE),
TX_XCLK_SEL => ("TXOUT"),
TX_DLYALIGN_CTRINC => ("0100"),
TX_DLYALIGN_LPFINC => ("0110"),
TX_DLYALIGN_MONSEL => ("000"),
TX_DLYALIGN_OVRDSETTING => ("10000000"),
-------------------------TX Gearbox---------------------------
GEARBOX_ENDEC => ("000"),
TXGEARBOX_USE => (FALSE),
----------------TX Driver and OOB Signalling------------------
TX_DRIVE_MODE => ("DIRECT"),
TX_IDLE_ASSERT_DELAY => ("101"),
TX_IDLE_DEASSERT_DELAY => ("011"),
TXDRIVE_LOOPBACK_HIZ => (FALSE),
TXDRIVE_LOOPBACK_PD => (FALSE),
--------------TX Pipe Control for PCI Express/SATA------------
COM_BURST_VAL => ("1111"),
------------------TX Attributes for PCI Express---------------
TX_DEEMPH_0 => ("11010"),
TX_DEEMPH_1 => ("10000"),
TX_MARGIN_FULL_0 => ("1001110"),
TX_MARGIN_FULL_1 => ("1001001"),
TX_MARGIN_FULL_2 => ("1000101"),
TX_MARGIN_FULL_3 => ("1000010"),
TX_MARGIN_FULL_4 => ("1000000"),
TX_MARGIN_LOW_0 => ("1000110"),
TX_MARGIN_LOW_1 => ("1000100"),
TX_MARGIN_LOW_2 => ("1000010"),
TX_MARGIN_LOW_3 => ("1000000"),
TX_MARGIN_LOW_4 => ("1000000"),
----------------------------RX PLL----------------------------
RX_OVERSAMPLE_MODE => (FALSE),
RXPLL_COM_CFG => (x"21680a"),
RXPLL_CP_CFG => (x"0D"),
RXPLL_DIVSEL_FB => (2),
RXPLL_DIVSEL_OUT => (2),
RXPLL_DIVSEL_REF => (1),
RXPLL_DIVSEL45_FB => (5),
RXPLL_LKDET_CFG => ("111"),
RX_CLK25_DIVIDER => (5),
-------------------------RX Interface-------------------------
GEN_RXUSRCLK => (TRUE),
RX_DATA_WIDTH => (10),
RXRECCLK_CTRL => ("RXRECCLKPMA_DIV1"),
RXRECCLK_DLY => ("0000000000"),
RXUSRCLK_DLY => (x"0000"),
----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
AC_CAP_DIS => (TRUE),
CDR_PH_ADJ_TIME => ("10100"),
OOBDETECT_THRESHOLD => ("011"),
PMA_CDR_SCAN => (x"640404C"),
PMA_RX_CFG => (x"05ce048"),
RCV_TERM_GND => (FALSE),
RCV_TERM_VTTRX => (FALSE),
RX_EN_IDLE_HOLD_CDR => (FALSE),
RX_EN_IDLE_RESET_FR => (TRUE),
RX_EN_IDLE_RESET_PH => (TRUE),
TX_DETECT_RX_CFG => (x"1832"),
TERMINATION_CTRL => ("00000"),
TERMINATION_OVRD => (FALSE),
CM_TRIM => ("01"),
PMA_RXSYNC_CFG => (x"00"),
PMA_CFG => (x"0040000040000000003"),
BGTEST_CFG => ("00"),
BIAS_CFG => (x"00000"),
--------------RX Decision Feedback Equalizer(DFE)-------------
DFE_CAL_TIME => ("01100"),
DFE_CFG => ("00011011"),
RX_EN_IDLE_HOLD_DFE => (TRUE),
RX_EYE_OFFSET => (x"4C"),
RX_EYE_SCANMODE => ("00"),
-------------------------PRBS Detection-----------------------
RXPRBSERR_LOOPBACK => ('0'),
------------------Comma Detection and Alignment---------------
ALIGN_COMMA_WORD => (1),
COMMA_10B_ENABLE => ("0001111111"),
COMMA_DOUBLE => (FALSE),
DEC_MCOMMA_DETECT => (TRUE),
DEC_PCOMMA_DETECT => (TRUE),
DEC_VALID_COMMA_ONLY => (FALSE),
MCOMMA_10B_VALUE => ("1010000011"),
MCOMMA_DETECT => (TRUE),
PCOMMA_10B_VALUE => ("0101111100"),
PCOMMA_DETECT => (TRUE),
RX_DECODE_SEQ_MATCH => (TRUE),
RX_SLIDE_AUTO_WAIT => (5),
RX_SLIDE_MODE => ("OFF"),
SHOW_REALIGN_COMMA => (FALSE),
-----------------RX Loss-of-sync State Machine----------------
RX_LOS_INVALID_INCR => (1),
RX_LOS_THRESHOLD => (4),
RX_LOSS_OF_SYNC_FSM => (FALSE),
-------------------------RX Gearbox---------------------------
RXGEARBOX_USE => (FALSE),
-------------RX Elastic Buffer and Phase alignment------------
RX_BUFFER_USE => (TRUE),
RX_EN_IDLE_RESET_BUF => (TRUE),
RX_EN_MODE_RESET_BUF => (TRUE),
RX_EN_RATE_RESET_BUF => (TRUE),
RX_EN_REALIGN_RESET_BUF => (FALSE),
RX_EN_REALIGN_RESET_BUF2 => (FALSE),
RX_FIFO_ADDR_MODE => ("FULL"),
RX_IDLE_HI_CNT => ("1000"),
RX_IDLE_LO_CNT => ("0000"),
RX_XCLK_SEL => ("RXREC"),
RX_DLYALIGN_CTRINC => ("0100"),
RX_DLYALIGN_EDGESET => ("00010"),
RX_DLYALIGN_LPFINC => ("0110"),
RX_DLYALIGN_MONSEL => ("000"),
RX_DLYALIGN_OVRDSETTING => ("10000000"),
------------------------Clock Correction----------------------
CLK_COR_ADJ_LEN => (2),
CLK_COR_DET_LEN => (2),
CLK_COR_INSERT_IDLE_FLAG => (FALSE),
CLK_COR_KEEP_IDLE => (FALSE),
CLK_COR_MAX_LAT => (18),
CLK_COR_MIN_LAT => (14),
CLK_COR_PRECEDENCE => (TRUE),
CLK_COR_REPEAT_WAIT => (0),
CLK_COR_SEQ_1_1 => ("0110111100"),
CLK_COR_SEQ_1_2 => ("0001010000"),
CLK_COR_SEQ_1_3 => ("0000000000"),
CLK_COR_SEQ_1_4 => ("0000000000"),
CLK_COR_SEQ_1_ENABLE => ("1111"),
CLK_COR_SEQ_2_1 => ("0110111100"),
CLK_COR_SEQ_2_2 => ("0010110101"),
CLK_COR_SEQ_2_3 => ("0000000000"),
CLK_COR_SEQ_2_4 => ("0000000000"),
CLK_COR_SEQ_2_ENABLE => ("1111"),
CLK_COR_SEQ_2_USE => (TRUE),
CLK_CORRECT_USE => (TRUE),
------------------------Channel Bonding----------------------
CHAN_BOND_1_MAX_SKEW => (1),
CHAN_BOND_2_MAX_SKEW => (1),
CHAN_BOND_KEEP_ALIGN => (FALSE),
CHAN_BOND_SEQ_1_1 => ("0000000000"),
CHAN_BOND_SEQ_1_2 => ("0000000000"),
CHAN_BOND_SEQ_1_3 => ("0000000000"),
CHAN_BOND_SEQ_1_4 => ("0000000000"),
CHAN_BOND_SEQ_1_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2 => ("0000000000"),
CHAN_BOND_SEQ_2_3 => ("0000000000"),
CHAN_BOND_SEQ_2_4 => ("0000000000"),
CHAN_BOND_SEQ_2_CFG => ("00000"),
CHAN_BOND_SEQ_2_ENABLE => ("1111"),
CHAN_BOND_SEQ_2_USE => (FALSE),
CHAN_BOND_SEQ_LEN => (1),
PCI_EXPRESS_MODE => (FALSE),
-------------RX Attributes for PCI Express/SATA/SAS----------
SAS_MAX_COMSAS => (52),
SAS_MIN_COMSAS => (40),
SATA_BURST_VAL => ("100"),
SATA_IDLE_VAL => ("100"),
SATA_MAX_BURST => (9),
SATA_MAX_INIT => (27),
SATA_MAX_WAKE => (9),
SATA_MIN_BURST => (5),
SATA_MIN_INIT => (15),
SATA_MIN_WAKE => (5),
TRANS_TIME_FROM_P2 => (x"03c"),
TRANS_TIME_NON_P2 => (x"19"),
TRANS_TIME_RATE => (x"ff"),
TRANS_TIME_TO_P2 => (x"064")
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK => LOOPBACK_IN,
RXPOWERDOWN => RXPOWERDOWN_IN,
TXPOWERDOWN => TXPOWERDOWN_IN,
-------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
RXDATAVALID => open,
RXGEARBOXSLIP => tied_to_ground_i,
RXHEADER => open,
RXHEADERVALID => open,
RXSTARTOFSEQ => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA(3 downto 1) => rxchariscomma_float_i,
RXCHARISCOMMA(0) => RXCHARISCOMMA_OUT,
RXCHARISK(3 downto 1) => rxcharisk_float_i,
RXCHARISK(0) => RXCHARISK_OUT,
RXDEC8B10BUSE => tied_to_vcc_i,
RXDISPERR(3 downto 1) => rxdisperr_float_i,
RXDISPERR(0) => RXDISPERR_OUT,
RXNOTINTABLE(3 downto 1) => rxnotintable_float_i,
RXNOTINTABLE(0) => RXNOTINTABLE_OUT,
RXRUNDISP(3 downto 1) => rxrundisp_float_i,
RXRUNDISP(0) => RXRUNDISP_OUT,
USRCODEERR => tied_to_ground_i,
------------------- Receive Ports - Channel Bonding Ports ------------------
RXCHANBONDSEQ => open,
RXCHBONDI => tied_to_ground_vec_i(3 downto 0),
RXCHBONDLEVEL => tied_to_ground_vec_i(2 downto 0),
RXCHBONDMASTER => tied_to_ground_i,
RXCHBONDO => open,
RXCHBONDSLAVE => tied_to_ground_i,
RXENCHANSYNC => tied_to_ground_i,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT => RXCLKCORCNT_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED => open,
RXBYTEREALIGN => open,
RXCOMMADET => open,
RXCOMMADETUSE => tied_to_vcc_i,
RXENMCOMMAALIGN => RXENMCOMMAALIGN_IN,
RXENPCOMMAALIGN => RXENPCOMMAALIGN_IN,
RXSLIDE => tied_to_ground_i,
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET => tied_to_ground_i,
RXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
RXPRBSERR => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA => rxdata_i,
RXRECCLK => RXRECCLK_OUT,
RXRECCLKPCS => open,
RXRESET => RXRESET_IN,
RXUSRCLK => tied_to_ground_i,
RXUSRCLK2 => RXUSRCLK2_IN,
------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
DFECLKDLYADJ => tied_to_ground_vec_i(5 downto 0),
DFECLKDLYADJMON => open,
DFEDLYOVRD => tied_to_vcc_i,
DFEEYEDACMON => open,
DFESENSCAL => open,
DFETAP1 => tied_to_ground_vec_i(4 downto 0),
DFETAP1MONITOR => open,
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR => open,
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR => open,
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR => open,
DFETAPOVRD => tied_to_vcc_i,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE => tied_to_ground_i,
IGNORESIGDET => tied_to_ground_i,
RXCDRRESET => tied_to_ground_i,
RXELECIDLE => RXELECIDLE_OUT,
RXEQMIX => "0000000111",
RXN => RXN_IN,
RXP => RXP_IN,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => RXBUFRESET_IN,
RXBUFSTATUS => RXBUFSTATUS_OUT,
RXCHANISALIGNED => open,
RXCHANREALIGN => open,
RXDLYALIGNDISABLE => tied_to_ground_i,
RXDLYALIGNMONENB => tied_to_ground_i,
RXDLYALIGNMONITOR => open,
RXDLYALIGNOVERRIDE => tied_to_ground_i,
RXDLYALIGNRESET => tied_to_ground_i,
RXDLYALIGNSWPPRECURB => tied_to_vcc_i,
RXDLYALIGNUPDSW => tied_to_ground_i,
RXENPMAPHASEALIGN => tied_to_ground_i,
RXPMASETPHASE => tied_to_ground_i,
RXSTATUS => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC => open,
---------------------- Receive Ports - RX Oversampling ---------------------
RXENSAMPLEALIGN => tied_to_ground_i,
RXOVERSAMPLEERR => open,
------------------------ Receive Ports - RX PLL Ports ----------------------
GREFCLKRX => tied_to_ground_i,
GTXRXRESET => GTXRXRESET_IN,
MGTREFCLKRX => MGTREFCLKRX_IN,
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
PERFCLKRX => tied_to_ground_i,
PLLRXRESET => PLLRXRESET_IN,
RXPLLLKDET => RXPLLLKDET_OUT,
RXPLLLKDETEN => tied_to_vcc_i,
RXPLLPOWERDOWN => tied_to_ground_i,
RXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
RXRATE => tied_to_ground_vec_i(1 downto 0),
RXRATEDONE => open,
RXRESETDONE => RXRESETDONE_OUT,
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS => open,
RXVALID => open,
----------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY => tied_to_ground_i,
--------------------- Receive Ports - RX Ports for SATA --------------------
COMINITDET => open,
COMSASDET => open,
COMWAKEDET => open,
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => tied_to_ground_vec_i(7 downto 0),
DCLK => tied_to_ground_i,
DEN => tied_to_ground_i,
DI => tied_to_ground_vec_i(15 downto 0),
DRDY => open,
DRPDO => open,
DWE => tied_to_ground_i,
-------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXBYPASS8B10B => tied_to_ground_vec_i(3 downto 0),
TXCHARDISPMODE(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPMODE(0) => TXCHARDISPMODE_IN,
TXCHARDISPVAL(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARDISPVAL(0) => TXCHARDISPVAL_IN,
TXCHARISK(3 downto 1) => tied_to_ground_vec_i(2 downto 0),
TXCHARISK(0) => TXCHARISK_IN,
TXENC8B10BUSE => tied_to_vcc_i,
TXKERR => open,
TXRUNDISP => open,
------------------------- Transmit Ports - GTX Ports -----------------------
GTXTEST => "1000000000000",
MGTREFCLKFAB => open,
TSTCLK0 => tied_to_ground_i,
TSTCLK1 => tied_to_ground_i,
TSTIN => "11111111111111111111",
TSTOUT => open,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA => txdata_i,
TXOUTCLK => TXOUTCLK_OUT,
TXOUTCLKPCS => open,
TXRESET => TXRESET_IN,
TXUSRCLK => tied_to_ground_i,
TXUSRCLK2 => TXUSRCLK2_IN,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXBUFDIFFCTRL => "100",
TXDIFFCTRL => "0000",
TXINHIBIT => tied_to_ground_i,
TXN => TXN_OUT,
TXP => TXP_OUT,
TXPOSTEMPHASIS => "00000",
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXPREEMPHASIS => "0000",
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => TXBUFSTATUS_OUT,
-------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
TXDLYALIGNDISABLE => tied_to_vcc_i,
TXDLYALIGNMONENB => tied_to_ground_i,
TXDLYALIGNMONITOR => open,
TXDLYALIGNOVERRIDE => tied_to_ground_i,
TXDLYALIGNRESET => tied_to_ground_i,
TXDLYALIGNUPDSW => tied_to_vcc_i,
TXENPMAPHASEALIGN => tied_to_ground_i,
TXPMASETPHASE => tied_to_ground_i,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GREFCLKTX => tied_to_ground_i,
GTXTXRESET => GTXTXRESET_IN,
MGTREFCLKTX => MGTREFCLKTX_IN,
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
PERFCLKTX => tied_to_ground_i,
PLLTXRESET => PLLTXRESET_IN,
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
TXPLLLKDET => TXPLLLKDET_OUT,
TXPLLLKDETEN => tied_to_vcc_i,
TXPLLPOWERDOWN => tied_to_ground_i,
TXPLLREFSELDY => tied_to_ground_vec_i(2 downto 0),
TXRATE => tied_to_ground_vec_i(1 downto 0),
TXRATEDONE => open,
TXRESETDONE => TXRESETDONE_OUT,
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
TXPRBSFORCEERR => tied_to_ground_i,
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY => tied_to_ground_i,
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDEEMPH => tied_to_ground_i,
TXDETECTRX => tied_to_ground_i,
TXELECIDLE => tied_to_ground_i,
TXMARGIN => tied_to_ground_vec_i(2 downto 0),
TXPDOWNASYNCH => tied_to_ground_i,
TXSWING => tied_to_ground_i,
--------------------- Transmit Ports - TX Ports for SATA -------------------
COMFINISH => open,
TXCOMINIT => tied_to_ground_i,
TXCOMSAS => tied_to_ground_i,
TXCOMWAKE => tied_to_ground_i
);
end RTL;
|
gpl-3.0
|
b7a79ec8d7e9c87d72e8c8dca8564cc2
| 0.369951 | 5.063216 | false | false | false | false |
makestuff/vhdl
|
package/gate/gate_tb.vhdl
| 1 | 1,963 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.gate_pkg.all;
entity gate_tb is
end gate_tb;
architecture behavioural of gate_tb is
signal op : Operation;
signal a : std_logic;
signal b : std_logic;
signal x : std_logic;
begin
-- Instantiate the unit under test
uut: entity work.gate
port map(
op_in => op,
a_in => a,
b_in => b,
x_out => x
);
-- Drive the unit under test. Read stimulus from stimulus.txt and write results to results.txt
process
variable inLine, outLine : line;
variable inData : std_logic_vector(2 downto 0);
variable outData : std_logic;
file inFile : text open read_mode is "stimulus.txt";
file outFile : text open write_mode is "results.txt";
begin
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
if ( inData(2) = '1' ) then
op <= OP_AND;
else
op <= OP_OR;
end if;
a <= inData(1);
b <= inData(0);
wait for 10 ns;
outData := x;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait;
--assert false report "NONE. End of simulation." severity failure;
end process;
end architecture;
|
gpl-3.0
|
132c805f647f2181eb2bc38b8c1f223d
| 0.676516 | 3.390328 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/wishbone_pkg.vhd
| 1 | 75,692 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 32;
constant c_wishbone_data_width : integer := 32;
subtype t_wishbone_address is
std_logic_vector(c_wishbone_address_width-1 downto 0);
subtype t_wishbone_data is
std_logic_vector(c_wishbone_data_width-1 downto 0);
subtype t_wishbone_byte_select is
std_logic_vector((c_wishbone_address_width/8)-1 downto 0);
subtype t_wishbone_cycle_type is
std_logic_vector(2 downto 0);
subtype t_wishbone_burst_type is
std_logic_vector(1 downto 0);
type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
type t_wishbone_address_granularity is (BYTE, WORD);
type t_wishbone_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_master_out;
subtype t_wishbone_slave_in is t_wishbone_master_out;
type t_wishbone_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
type t_wishbone_byte_select_array is array(natural range <>) of t_wishbone_byte_select;
type t_wishbone_data_array is array(natural range <>) of t_wishbone_data;
type t_wishbone_address_array is array(natural range <>) of t_wishbone_address;
type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
--type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
subtype t_wishbone_slave_in_array is t_wishbone_master_out_array;
type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
--type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
subtype t_wishbone_master_in_array is t_wishbone_slave_out_array;
constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_data : std_logic_vector(c_wishbone_address_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_slave_in : t_wishbone_slave_in :=
('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
constant cc_dummy_master_out : t_wishbone_master_out := cc_dummy_slave_in;
-- Dangerous! Will stall a bus.
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', 'X', cc_dummy_data);
constant cc_dummy_master_in : t_wishbone_master_in := cc_dummy_slave_out;
constant cc_dummy_address_array : t_wishbone_address_array(0 downto 0) := (0 => cc_dummy_address);
-- A generally useful function.
function f_ceil_log2(x : natural) return natural;
function f_bits2string(s : std_logic_vector) return string;
function f_string2bits(s : string) return std_logic_vector;
function f_string2svl (s : string) return std_logic_vector;
function f_slv2string (slv : std_logic_vector) return string;
function f_string_fix_len( s : string; ret_len : natural := 10; fill_char : character := '0' ) return string;
function f_hot_to_bin(x : std_logic_vector) return natural;
-- *** Wishbone slave interface functions ***
-- f_wb_wr:
-- processes an incoming write reqest to a register while honoring the select lines
-- valid modes are overwrite "owr", set "set" (bits are or'ed) and clear "clr" (bits are nand'ed)
function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector;
------------------------------------------------------------------------------
-- SDB declaration
------------------------------------------------------------------------------
constant c_sdb_device_length : natural := 512; -- bits
subtype t_sdb_record is std_logic_vector(c_sdb_device_length-1 downto 0);
type t_sdb_record_array is array(natural range <>) of t_sdb_record;
type t_sdb_product is record
vendor_id : std_logic_vector(63 downto 0);
device_id : std_logic_vector(31 downto 0);
version : std_logic_vector(31 downto 0);
date : std_logic_vector(31 downto 0);
name : string(1 to 19);
end record t_sdb_product;
type t_sdb_component is record
addr_first : std_logic_vector(63 downto 0);
addr_last : std_logic_vector(63 downto 0);
product : t_sdb_product;
end record t_sdb_component;
constant c_sdb_endian_big : std_logic := '0';
constant c_sdb_endian_little : std_logic := '1';
type t_sdb_device is record
abi_class : std_logic_vector(15 downto 0);
abi_ver_major : std_logic_vector(7 downto 0);
abi_ver_minor : std_logic_vector(7 downto 0);
wbd_endian : std_logic; -- 0 = big, 1 = little
wbd_width : std_logic_vector(3 downto 0); -- 3=64-bit, 2=32-bit, 1=16-bit, 0=8-bit
sdb_component : t_sdb_component;
end record t_sdb_device;
type t_sdb_bridge is record
sdb_child : std_logic_vector(63 downto 0);
sdb_component : t_sdb_component;
end record t_sdb_bridge;
type t_sdb_integration is record
product : t_sdb_product;
end record t_sdb_integration;
type t_sdb_repo_url is record
repo_url : string(1 to 63);
end record t_sdb_repo_url;
type t_sdb_synthesis is record
syn_module_name : string(1 to 16);
syn_commit_id : string(1 to 32);
syn_tool_name : string(1 to 8);
syn_tool_version : std_logic_vector(31 downto 0);
syn_date : std_logic_vector(31 downto 0);
syn_username : string(1 to 15);
end record t_sdb_synthesis;
-- general crossbar building functions
function f_sdb_create_array(g_enum_dev_id : boolean := false;
g_dev_id_offs : natural := 0;
g_enum_dev_name : boolean := false;
g_dev_name_offs : natural := 0;
device : t_sdb_device;
instances : natural := 1) return t_sdb_record_array;
function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array;
function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector;
function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector;
function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0')) return t_sdb_record_array;
function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned) return unsigned;
function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address;
-- Used to configure a device at a certain address
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address) return t_sdb_record;
function f_sdb_embed_integration(integr : t_sdb_integration) return t_sdb_record;
function f_sdb_embed_repo_url(url : t_sdb_repo_url) return t_sdb_record;
function f_sdb_embed_synthesis(syn : t_sdb_synthesis) return t_sdb_record;
function f_sdb_extract_device(sdb_record : t_sdb_record) return t_sdb_device;
function f_sdb_extract_bridge(sdb_record : t_sdb_record) return t_sdb_bridge;
function f_sdb_extract_integration(sdb_record : t_sdb_record) return t_sdb_integration;
function f_sdb_extract_repo_url(sdb_record : t_sdb_record) return t_sdb_repo_url;
function f_sdb_extract_synthesis(sdb_record : t_sdb_record) return t_sdb_synthesis;
-- Automatic crossbar mapping functions
function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true) return t_sdb_record;
function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true) return t_sdb_record;
function f_sdb_auto_layout(records : t_sdb_record_array) return t_sdb_record_array;
function f_sdb_auto_sdb (records : t_sdb_record_array) return t_wishbone_address;
-- For internal use by the crossbar
function f_sdb_embed_product(product : t_sdb_product) return std_logic_vector; -- (319 downto 8)
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address) return std_logic_vector; -- (447 downto 8)
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8)) return t_sdb_product;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8)) return t_sdb_component;
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_slave_adapter
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_master_granularity : t_wishbone_address_granularity;
g_slave_use_struct : boolean;
g_slave_mode : t_wishbone_interface_mode;
g_slave_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := cc_dummy_sel;
sl_cyc_i : in std_logic := '0';
sl_stb_i : in std_logic := '0';
sl_we_i : in std_logic := '0';
sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_err_o : out std_logic;
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
ma_cyc_o : out std_logic;
ma_stb_o : out std_logic;
ma_we_o : out std_logic;
ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
ma_err_i : in std_logic := '0';
ma_rty_i : in std_logic := '0';
ma_ack_i : in std_logic := '0';
ma_stall_i : in std_logic := '0';
ma_int_i : in std_logic := '0';
master_i : in t_wishbone_master_in := cc_dummy_slave_out;
master_o : out t_wishbone_master_out);
end component;
component wb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_sel_o : out std_logic_vector(3 downto 0);
wb_cyc_o : out std_logic;
wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
wb_ack_i : in std_logic;
wb_stall_i : in std_logic := '0');
end component;
component xwb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
component xwb_bus_fanout
generic (
g_num_outputs : natural;
g_bits_per_slave : integer;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_slave_interface_mode : t_wishbone_interface_mode := CLASSIC);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
end component;
component xwb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean;
g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end component;
-- Use the f_xwb_bridge_*_sdb to bridge a crossbar to another
function f_xwb_bridge_manual_sdb( -- take a manual bus size
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
function f_xwb_bridge_layout_sdb( -- determine bus size from layout
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge;
component xwb_sdb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean := false;
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end component;
component xwb_register_link -- puts a register of delay between crossbars
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
component sdb_rom is
generic(
g_layout : t_sdb_record_array;
g_bus_end : unsigned(63 downto 0));
port(
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out);
end component;
constant c_xwb_dma_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"cababa56",
version => x"00000001",
date => x"20120518",
name => "WB4-Streaming-DMA_0")));
component xwb_dma is
generic(
-- Value 0 cannot stream
-- Value 1 only slaves with async ACK can stream
-- Value 2 only slaves with combined latency <= 2 can stream
-- Value 3 only slaves with combined latency <= 6 can stream
-- Value 4 only slaves with combined latency <= 14 can stream
-- ....
logRingLen : integer := 4
);
port(
-- Common wishbone signals
clk_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
r_master_i : in t_wishbone_master_in;
r_master_o : out t_wishbone_master_out;
-- Master writer port
w_master_i : in t_wishbone_master_in;
w_master_o : out t_wishbone_master_out;
-- Pulsed high completion signal
interrupt_o : out std_logic
);
end component;
-- If you reset one clock domain, you must reset BOTH!
-- Release of the reset lines may be arbitrarily out-of-phase
component xwb_clock_crossing is
generic(
g_size : natural := 16);
port(
-- Slave control port
slave_clk_i : in std_logic;
slave_rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- Master reader port
master_clk_i : in std_logic;
master_rst_n_i : in std_logic;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end component;
-- g_size is in words
function f_xwb_dpram(g_size : natural) return t_sdb_device;
component xwb_dpram
generic (
g_size : natural;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave2_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave1_granularity : t_wishbone_address_granularity := WORD;
g_slave2_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component;
-- Just like the DMA controller, but constantly at address 0
component xwb_streamer is
generic(
-- Value 0 cannot stream
-- Value 1 only slaves with async ACK can stream
-- Value 2 only slaves with combined latency = 2 can stream
-- Value 3 only slaves with combined latency = 6 can stream
-- Value 4 only slaves with combined latency = 14 can stream
-- ....
logRingLen : integer := 4
);
port(
-- Common wishbone signals
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Master reader port
r_master_i : in t_wishbone_master_in;
r_master_o : out t_wishbone_master_out;
-- Master writer port
w_master_i : in t_wishbone_master_in;
w_master_o : out t_wishbone_master_out);
end component;
constant c_xwb_gpio_port_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"441c5143",
version => x"00000001",
date => x"20121129",
name => "WB-GPIO-Port ")));
component wb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component xwb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
constant c_xwb_i2c_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"123c5443",
version => x"00000001",
date => x"20121129",
name => "WB-I2C-Master ")));
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_interfaces : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
end component;
component xwb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_interfaces : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
scl_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
scl_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
scl_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_i : in std_logic_vector(g_num_interfaces-1 downto 0);
sda_pad_o : out std_logic_vector(g_num_interfaces-1 downto 0);
sda_padoen_o : out std_logic_vector(g_num_interfaces-1 downto 0));
end component;
component xwb_lm32
generic (
g_profile : string;
g_reset_vector : std_logic_vector(31 downto 0) := x"00000000");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
iwb_o : out t_wishbone_master_out;
iwb_i : in t_wishbone_master_in);
end component;
constant c_xwb_onewire_master_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"779c5443",
version => x"00000001",
date => x"20121129",
name => "WB-OneWire-Master ")));
component wb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "1.0";
g_ow_btp_overdrive : string := "5.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component xwb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
constant c_xwb_spi_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"e503947e", -- echo "WB-SPI.Control " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SPI.Control ")));
component wb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_divider_len : integer := 16;
g_max_char_len : integer := 128;
g_num_slaves : integer := 8);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component xwb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_divider_len : integer := 16;
g_max_char_len : integer := 128;
g_num_slaves : integer := 8);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
pad_cs_o : out std_logic_vector(g_num_slaves-1 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component wb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component xwb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_vuart_fifo_size : integer := 1024);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component wb_simple_pwm
generic (
g_num_channels : integer range 1 to 8;
g_regs_size : integer range 1 to 16 := 16;
g_default_period : integer range 0 to 255 := 0;
g_default_presc : integer range 0 to 255 := 0;
g_default_val : integer range 0 to 255 := 0;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
pwm_o : out std_logic_vector(g_num_channels-1 downto 0));
end component;
component xwb_simple_pwm
generic (
g_num_channels : integer range 1 to 8;
g_regs_size : integer range 1 to 16 := 16;
g_default_period : integer range 0 to 255 := 0;
g_default_presc : integer range 0 to 255 := 0;
g_default_val : integer range 0 to 255 := 0;
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := BYTE);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
pwm_o : out std_logic_vector(g_num_channels-1 downto 0));
end component;
component wb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic);
end component;
component xwb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor);
end component;
component wb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural;
g_init_vectors : t_wishbone_address_array := cc_dummy_address_array
);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
constant c_xwb_vic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000013",
version => x"00000002",
date => x"20120113",
name => "WB-VIC-Int.Control ")));
component xwb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural;
g_init_vectors : t_wishbone_address_array := cc_dummy_address_array);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
constant c_wb_serial_lcd_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"b77a5045",
version => x"00000001",
date => x"20130222",
name => "SERIAL-LCD-DISPLAY ")));
component wb_serial_lcd
generic(
g_cols : natural := 40;
g_rows : natural := 24;
g_hold : natural := 15; -- How many times to repeat a line (for sharpness)
g_wait : natural := 1); -- How many cycles per state change (for 20MHz timing)
port(
slave_clk_i : in std_logic;
slave_rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
di_clk_i : in std_logic;
di_scp_o : out std_logic;
di_lp_o : out std_logic;
di_flm_o : out std_logic;
di_dat_o : out std_logic);
end component;
function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device;
component wb_spi_flash is
generic(
g_port_width : natural := 1; -- 1 for EPCS, 4 for EPCQ
g_addr_width : natural := 24; -- log of memory (24=16MB)
g_idle_time : natural := 3;
g_dummy_time : natural := 8;
-- leave these at defaults if you have:
-- a) slow clock, b) valid constraints, or c) registered in/outputs
g_input_latch_edge : std_logic := '1'; -- rising
g_output_latch_edge : std_logic := '0'; -- falling
g_input_to_output_cycles : natural := 1); -- between 1 and 8
port(
clk_i : in std_logic;
rstn_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- For properly constrained designs, set clk_out_i = clk_in_i.
clk_out_i : in std_logic;
clk_in_i : in std_logic;
ncs_o : out std_logic;
oe_o : out std_logic_vector(g_port_width-1 downto 0);
asdi_o : out std_logic_vector(g_port_width-1 downto 0);
data_i : in std_logic_vector(g_port_width-1 downto 0);
external_request_i : in std_logic := '0'; -- JTAG wants to use SPI?
external_granted_o : out std_logic);
end component;
-----------------------------------------------------------------------------
-- I2C to Wishbone bridge, following protocol defined with ELMA
-----------------------------------------------------------------------------
component wb_i2c_bridge is
generic
(
-- FSM watchdog timeout, see Appendix A in the component documentation for
-- an example of setting this generic
g_fsm_wdt : positive
);
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- I2C address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- Status outputs
-- TIP : Transfer In Progress
-- '1' when the I2C slave detects a matching I2C address, thus a
-- transfer is in progress
-- '0' when idle
-- ERR : Error
-- '1' when the SysMon attempts to access an invalid WB slave
-- '0' when idle
-- WDTO : Watchdog timeout (single clock cycle pulse)
-- '1' -- timeout of watchdog occured
-- '0' -- when idle
tip_o : out std_logic;
err_p_o : out std_logic;
wdto_p_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component wb_i2c_bridge;
------------------------------------------------------------------------------
-- MultiBoot component
------------------------------------------------------------------------------
component xwb_xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xwb_xil_multiboot;
constant c_xwb_xil_multiboot_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000001f",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"11da333d", -- echo "WB-Xilinx-MultiBoot" | md5sum | cut -c1-8
version => x"00000001",
date => x"20140313",
name => "WB-Xilinx-MultiBoot")));
end wishbone_pkg;
package body wishbone_pkg is
-- f_wb_wr: processes a write reqest to a slave register with select lines. valid modes are "owr", "set" and "clr"
function f_wb_wr(pval : std_logic_vector; ival : std_logic_vector; sel : std_logic_vector; mode : string := "owr") return std_logic_vector is
variable n_sel : std_logic_vector(pval'range);
variable n_val : std_logic_vector(pval'range);
variable result : std_logic_vector(pval'range);
begin
for i in pval'range loop
n_sel(i) := sel(i / 8);
n_val(i) := ival(i);
end loop;
if(mode = "set") then
result := pval or (n_val and n_sel);
elsif (mode = "clr") then
result := pval and not (n_val and n_sel);
else
result := (pval and not n_sel) or (n_val and n_sel);
end if;
return result;
end f_wb_wr;
function f_ceil_log2(x : natural) return natural is
begin
if x <= 1
then return 0;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
function f_sdb_embed_product(product : t_sdb_product)
return std_logic_vector -- (319 downto 8)
is
variable result : std_logic_vector(319 downto 8);
begin
result(319 downto 256) := product.vendor_id;
result(255 downto 224) := product.device_id;
result(223 downto 192) := product.version;
result(191 downto 160) := product.date;
for i in 0 to 18 loop -- string to ascii
result(159-i*8 downto 152-i*8) :=
std_logic_vector(to_unsigned(character'pos(product.name(i+1)), 8));
end loop;
return result;
end;
function f_sdb_extract_product(sdb_record : std_logic_vector(319 downto 8))
return t_sdb_product
is
variable result : t_sdb_product;
begin
result.vendor_id := sdb_record(319 downto 256);
result.device_id := sdb_record(255 downto 224);
result.version := sdb_record(223 downto 192);
result.date := sdb_record(191 downto 160);
for i in 0 to 18 loop -- ascii to string
result.name(i+1) := character'val(to_integer(unsigned(sdb_record(159-i*8 downto 152-i*8))));
end loop;
return result;
end;
function f_sdb_embed_component(sdb_component : t_sdb_component; address : t_wishbone_address)
return std_logic_vector -- (447 downto 8)
is
variable result : std_logic_vector(447 downto 8);
constant first : unsigned(63 downto 0) := unsigned(sdb_component.addr_first);
constant last : unsigned(63 downto 0) := unsigned(sdb_component.addr_last);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(447 downto 384) := std_logic_vector(base);
result(383 downto 320) := std_logic_vector(base + last - first);
result(319 downto 8) := f_sdb_embed_product(sdb_component.product);
return result;
end;
function f_sdb_extract_component(sdb_record : std_logic_vector(447 downto 8))
return t_sdb_component
is
variable result : t_sdb_component;
begin
result.addr_first := sdb_record(447 downto 384);
result.addr_last := sdb_record(383 downto 320);
result.product := f_sdb_extract_product(sdb_record(319 downto 8));
return result;
end;
function f_sdb_embed_device(device : t_sdb_device; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 496) := device.abi_class;
result(495 downto 488) := device.abi_ver_major;
result(487 downto 480) := device.abi_ver_minor;
result(479 downto 456) := (others => '0');
result(455) := device.wbd_endian;
result(454 downto 452) := (others => '0');
result(451 downto 448) := device.wbd_width;
result(447 downto 8) := f_sdb_embed_component(device.sdb_component, address);
result(7 downto 0) := x"01"; -- device
return result;
end;
function f_sdb_extract_device(sdb_record : t_sdb_record)
return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := sdb_record(511 downto 496);
result.abi_ver_major := sdb_record(495 downto 488);
result.abi_ver_minor := sdb_record(487 downto 480);
result.wbd_endian := sdb_record(452);
result.wbd_width := sdb_record(451 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"01"
report "Cannot extract t_sdb_device from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity failure;
return result;
end;
function f_sdb_embed_integration(integr : t_sdb_integration)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 320) := (others => '0');
result(319 downto 8) := f_sdb_embed_product(integr.product);
result(7 downto 0) := x"80"; -- integration record
return result;
end f_sdb_embed_integration;
function f_sdb_extract_integration(sdb_record : t_sdb_record)
return t_sdb_integration
is
variable result : t_sdb_integration;
begin
result.product := f_sdb_extract_product(sdb_record(319 downto 8));
assert sdb_record(7 downto 0) = x"80"
report "Cannot extract t_sdb_integration from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end f_sdb_extract_integration;
function f_sdb_embed_repo_url(url : t_sdb_repo_url)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 8) := f_string2svl(url.repo_url);
result( 7 downto 0) := x"81"; -- repo_url record
return result;
end;
function f_sdb_extract_repo_url(sdb_record : t_sdb_record)
return t_sdb_repo_url
is
variable result : t_sdb_repo_url;
begin
result.repo_url := f_slv2string(sdb_record(511 downto 8));
assert sdb_record(7 downto 0) = x"81"
report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_sdb_embed_synthesis(syn : t_sdb_synthesis)
return t_sdb_record
is
variable result : t_sdb_record;
begin
result(511 downto 384) := f_string2svl(syn.syn_module_name);
result(383 downto 256) := f_string2bits(syn.syn_commit_id);
result(255 downto 192) := f_string2svl(syn.syn_tool_name);
result(191 downto 160) := syn.syn_tool_version;
result(159 downto 128) := syn.syn_date;
result(127 downto 8) := f_string2svl(syn.syn_username);
result( 7 downto 0) := x"82"; -- synthesis record
return result;
end;
function f_sdb_extract_synthesis(sdb_record : t_sdb_record)
return t_sdb_synthesis
is
variable result : t_sdb_synthesis;
begin
result.syn_module_name := f_slv2string(sdb_record(511 downto 384));
result.syn_commit_id := f_bits2string(sdb_record(383 downto 256));
result.syn_tool_name := f_slv2string(sdb_record(255 downto 192));
result.syn_tool_version := sdb_record(191 downto 160);
result.syn_date := sdb_record(159 downto 128);
result.syn_username := f_slv2string(sdb_record(127 downto 8));
assert sdb_record(7 downto 0) = x"82"
report "Cannot extract t_sdb_repo_url from record of type " & Integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity Failure;
return result;
end;
function f_sdb_embed_bridge(bridge : t_sdb_bridge; address : t_wishbone_address)
return t_sdb_record
is
variable result : t_sdb_record;
constant first : unsigned(63 downto 0) := unsigned(bridge.sdb_component.addr_first);
constant child : unsigned(63 downto 0) := unsigned(bridge.sdb_child);
variable base : unsigned(63 downto 0) := (others => '0');
begin
base(address'length-1 downto 0) := unsigned(address);
result(511 downto 448) := std_logic_vector(base + child - first);
result(447 downto 8) := f_sdb_embed_component(bridge.sdb_component, address);
result(7 downto 0) := x"02"; -- bridge
return result;
end;
function f_sdb_extract_bridge(sdb_record : t_sdb_record)
return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := sdb_record(511 downto 448);
result.sdb_component := f_sdb_extract_component(sdb_record(447 downto 8));
assert sdb_record(7 downto 0) = x"02"
report "Cannot extract t_sdb_bridge from record of type " & integer'image(to_integer(unsigned(sdb_record(7 downto 0)))) & "."
severity failure;
return result;
end;
function f_sdb_auto_device(device : t_sdb_device; enable : boolean := true)
return t_sdb_record
is
constant c_zero : t_wishbone_address := (others => '0');
variable v_empty : t_sdb_record := (others => '0');
begin
v_empty(7 downto 0) := (others => '1');
if enable then
return f_sdb_embed_device(device, c_zero);
else
return v_empty;
end if;
end f_sdb_auto_device;
function f_sdb_auto_bridge(bridge : t_sdb_bridge; enable : boolean := true)
return t_sdb_record
is
constant c_zero : t_wishbone_address := (others => '0');
variable v_empty : t_sdb_record := (others => '0');
begin
v_empty(7 downto 0) := (others => '1');
if enable then
return f_sdb_embed_bridge(bridge, c_zero);
else
return v_empty;
end if;
end f_sdb_auto_bridge;
subtype t_usdb_address is unsigned(63 downto 0);
type t_usdb_address_array is array(natural range <>) of t_usdb_address;
-- We map devices by placing the smallest ones first.
-- This is guaranteed to pack the maximum number of devices in the smallest space.
-- If a device has an address != 0, we leave it alone and let the crossbar confirm
-- that the address does not cause a conflict.
function f_sdb_auto_layout_helper(records : t_sdb_record_array)
return t_usdb_address_array
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
constant c_zero : t_usdb_address := (others => '0');
constant c_used_entries : natural := c_records'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries);
constant c_rom_bytes : natural := c_rom_entries * c_sdb_device_length / 8;
variable v_component : t_sdb_component;
variable v_sizes : t_usdb_address_array(c_records'length downto 0);
variable v_address : t_usdb_address_array(c_records'length downto 0);
variable v_map : std_logic_vector(c_records'length downto 0) := (others => '0');
variable v_cursor : unsigned(63 downto 0) := (others => '0');
variable v_increment : unsigned(63 downto 0) := (others => '0');
begin
-- First, extract the length of the devices, ignoring those not to be mapped
for i in c_records'range loop
v_component := f_sdb_extract_component(c_records(i)(447 downto 8));
v_sizes(i) := unsigned(v_component.addr_last);
v_address(i) := unsigned(v_component.addr_first);
-- Silently round up to a power of two; the crossbar will give a warning for us
for j in 62 downto 0 loop
v_sizes(i)(j) := v_sizes(i)(j+1) or v_sizes(i)(j);
end loop;
-- Only map devices/bridges at address zero
if v_address(i) = c_zero then
case c_records(i)(7 downto 0) is
when x"01" => v_map(i) := '1';
when x"02" => v_map(i) := '1';
when others => null;
end case;
end if;
end loop;
-- Assign the SDB record a spot as well
v_address(c_records'length) := (others => '0');
v_sizes(c_records'length) := to_unsigned(c_rom_bytes-1, 64);
v_map(c_records'length) := '1';
-- Start assigning addresses
for j in 0 to 63 loop
v_increment := (others => '0');
v_increment(j) := '1';
for i in 0 to c_records'length loop
if v_map(i) = '1' and v_sizes(i)(j) = '0' then
v_map(i) := '0';
v_address(i) := v_cursor;
v_cursor := v_cursor + v_increment;
end if;
end loop;
-- Round up to the next required alignment
if v_cursor(j) = '1' then
v_cursor := v_cursor + v_increment;
end if;
end loop;
return v_address;
end f_sdb_auto_layout_helper;
function f_sdb_auto_layout(records : t_sdb_record_array)
return t_sdb_record_array
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
variable v_result : t_sdb_record_array(c_records'range) := c_records;
constant c_address : t_usdb_address_array := f_sdb_auto_layout_helper(c_records);
variable v_address : t_wishbone_address;
begin
-- Put the addresses into the mapping
for i in v_result'range loop
v_address := std_logic_vector(c_address(i)(t_wishbone_address'range));
if c_records(i)(7 downto 0) = x"01" then
v_result(i) := f_sdb_embed_device(f_sdb_extract_device(v_result(i)), v_address);
end if;
if c_records(i)(7 downto 0) = x"02" then
v_result(i) := f_sdb_embed_bridge(f_sdb_extract_bridge(v_result(i)), v_address);
end if;
end loop;
return v_result;
end f_sdb_auto_layout;
function f_sdb_auto_sdb(records : t_sdb_record_array)
return t_wishbone_address
is
alias c_records : t_sdb_record_array(records'length-1 downto 0) is records;
constant c_address : t_usdb_address_array(c_records'length downto 0) := f_sdb_auto_layout_helper(c_records);
begin
return std_logic_vector(c_address(c_records'length)(t_wishbone_address'range));
end f_sdb_auto_sdb;
--**************************************************************************************************************************--
-- START MAT's NEW FUNCTIONS FROM 18th Oct 2013
------------------------------------------------------------------------------------------------------------------------------
function f_sdb_create_array(g_enum_dev_id : boolean := false;
g_dev_id_offs : natural := 0;
g_enum_dev_name : boolean := false;
g_dev_name_offs : natural := 0;
device : t_sdb_device;
instances : natural := 1)
return t_sdb_record_array is
variable result : t_sdb_record_array(instances-1 downto 0);
variable i,j, pos : natural;
variable dev, newdev : t_sdb_device;
variable serial_no : string(1 to 3);
variable text_possible : boolean := false;
begin
dev := device;
report "### Creating " & integer'image(instances) & " x " & dev.sdb_component.product.name
severity note;
for i in 0 to instances-1 loop
newdev := dev;
if(g_enum_dev_id) then
dev.sdb_component.product.device_id :=
std_logic_vector( unsigned(dev.sdb_component.product.device_id)
+ to_unsigned(i+g_dev_id_offs, dev.sdb_component.product.device_id'length));
end if;
if(g_enum_dev_name) then
-- find end of name
for j in dev.sdb_component.product.name'length downto 1 loop
if(dev.sdb_component.product.name(j) /= ' ') then
pos := j;
exit;
end if;
end loop;
-- convert i+g_dev_name_offs to string
serial_no := f_string_fix_len(integer'image(i+g_dev_name_offs), serial_no'length);
report "### Now: " & serial_no & " of " & dev.sdb_component.product.name severity note;
-- check if space is sufficient
assert (serial_no'length+1 <= dev.sdb_component.product.name'length - pos)
report "Not enough space in namestring of sdb_device " & dev.sdb_component.product.name
& " to add serial number " & serial_no & ". Space available " &
integer'image(dev.sdb_component.product.name'length-pos-1) & ", required "
& integer'image(serial_no'length+1)
severity Failure;
end if;
if(g_enum_dev_name) then
newdev.sdb_component.product.name(pos+1) := '_';
for j in 1 to serial_no'length loop
newdev.sdb_component.product.name(pos+1+j) := serial_no(j);
end loop;
end if;
-- insert
report "### to: " & newdev.sdb_component.product.name severity note;
result(i) := f_sdb_embed_device(newdev, (others=>'0'));
end loop;
return result;
end f_sdb_create_array;
function f_sdb_join_arrays(a : t_sdb_record_array; b : t_sdb_record_array) return t_sdb_record_array is
variable result : t_sdb_record_array(a'length+b'length-1 downto 0);
variable i : natural;
begin
for i in 0 to a'left loop
result(i) := a(i);
end loop;
for i in 0 to b'left loop
result(i+a'length) := b(i);
end loop;
return result;
end f_sdb_join_arrays;
function f_sdb_extract_base_addr(sdb_record : t_sdb_record) return std_logic_vector is
begin
return sdb_record(447 downto 384);
end f_sdb_extract_base_addr;
function f_sdb_extract_end_addr(sdb_record : t_sdb_record) return std_logic_vector is
begin
return sdb_record(383 downto 320);
end f_sdb_extract_end_addr;
function f_align_addr_offset(offs : unsigned; this_rng : unsigned; prev_rng : unsigned)
return unsigned is
variable this_pow, prev_pow : natural;
variable start, env, result : unsigned(63 downto 0) := (others => '0');
begin
start(offs'left downto 0) := offs;
--calculate address envelopes (next power of 2) for previous and this component and choose the larger one
this_pow := f_hot_to_bin(std_logic_vector(this_rng));
prev_pow := f_hot_to_bin(std_logic_vector(prev_rng));
-- no max(). thank you very much, std_numeric :-/
if(this_pow >= prev_pow) then
env(this_pow) := '1';
else
env(prev_pow) := '1';
end if;
--round up to the next multiple of the envelope...
if(prev_rng /= 0) then
result := start + env - (start mod env);
else
result := start; --...except for first element, result is start.
end if;
return result;
end f_align_addr_offset;
-- generates aligned address map for an sdb_record_array, accepts optional start offset
function f_sdb_automap_array(sdb_array : t_sdb_record_array; start_offset : t_wishbone_address := (others => '0'))
return t_sdb_record_array is
variable this_rng : unsigned(63 downto 0) := (others => '0');
variable prev_rng : unsigned(63 downto 0) := (others => '0');
variable prev_offs : unsigned(63 downto 0) := (others => '0');
variable this_offs : unsigned(63 downto 0) := (others => '0');
variable device : t_sdb_device;
variable bridge : t_sdb_bridge;
variable sdb_type : std_logic_vector(7 downto 0);
variable i : natural;
variable result : t_sdb_record_array(sdb_array'length-1 downto 0); -- last
begin
prev_offs(start_offset'left downto 0) := unsigned(start_offset);
--traverse the array
for i in 0 to sdb_array'length-1 loop
-- find the fitting extraction function by evaling the type byte.
-- could also use the component, but it's safer to use Wes' embed and extract functions.
sdb_type := sdb_array(i)(7 downto 0);
case sdb_type is
--device
when x"01" => device := f_sdb_extract_device(sdb_array(i));
this_rng := unsigned(device.sdb_component.addr_last) - unsigned(device.sdb_component.addr_first);
this_offs := f_align_addr_offset(prev_offs, this_rng, prev_rng);
result(i) := f_sdb_embed_device(device, std_logic_vector(this_offs(31 downto 0)));
--bridge
when x"02" => bridge := f_sdb_extract_bridge(sdb_array(i));
this_rng := unsigned(bridge.sdb_component.addr_last) - unsigned(bridge.sdb_component.addr_first);
this_offs := f_align_addr_offset(prev_offs, this_rng, prev_rng);
result(i) := f_sdb_embed_bridge(bridge, std_logic_vector(this_offs(31 downto 0)) );
--other
when others => result(i) := sdb_array(i);
end case;
-- doesnt hurt because this_* doesnt change if its not a device or bridge
prev_rng := this_rng;
prev_offs := this_offs;
end loop;
report "##* " & integer'image(sdb_array'length) & " Elements, last address: " & f_bits2string(std_logic_vector(this_offs+this_rng)) severity Note;
return result;
end f_sdb_automap_array;
-- find place for sdb rom on crossbar and return address. try to put it in an address gap.
function f_sdb_create_rom_addr(sdb_array : t_sdb_record_array) return t_wishbone_address is
constant rom_bytes : natural := (2**f_ceil_log2(sdb_array'length + 1)) * (c_sdb_device_length / 8);
variable result : t_wishbone_address := (others => '0');
variable this_base, this_end : unsigned(63 downto 0) := (others => '0');
variable prev_base, prev_end : unsigned(63 downto 0) := (others => '0');
variable rom_base : unsigned(63 downto 0) := (others => '0');
variable sdb_type : std_logic_vector(7 downto 0);
begin
--traverse the array
for i in 0 to sdb_array'length-1 loop
sdb_type := sdb_array(i)(7 downto 0);
if(sdb_type = x"01" or sdb_type = x"02") then
-- get
this_base := unsigned(f_sdb_extract_base_addr(sdb_array(i)));
this_end := unsigned(f_sdb_extract_end_addr(sdb_array(i)));
if(unsigned(result) = 0) then
rom_base := f_align_addr_offset(prev_base, to_unsigned(rom_bytes-1, 64), (prev_end-prev_base));
if(rom_base + to_unsigned(rom_bytes, 64) <= this_base) then
result := std_logic_vector(rom_base(t_wishbone_address'left downto 0));
end if;
end if;
prev_base := this_base;
prev_end := this_end;
end if;
end loop;
-- if there was no gap to fit the sdb rom, place it at the end
if(unsigned(result) = 0) then
result := std_logic_vector(f_align_addr_offset(this_base, to_unsigned(rom_bytes-1, 64),
this_end-this_base)(t_wishbone_address'left downto 0));
end if;
return result;
end f_sdb_create_rom_addr;
------------------------------------------------------------------------------------------------------------------------------
-- END MAT's NEW FUNCTIONS FROM 18th Oct 2013
------------------------------------------------------------------------------------------------------------------------------
function f_xwb_bridge_manual_sdb(
g_size : t_wishbone_address;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
variable result : t_sdb_bridge;
begin
result.sdb_child := (others => '0');
result.sdb_child(c_wishbone_address_width-1 downto 0) := g_sdb_addr;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := (others => '0');
result.sdb_component.addr_last(c_wishbone_address_width-1 downto 0) := g_size;
result.sdb_component.product.vendor_id := x"0000000000000651"; -- GSI
result.sdb_component.product.device_id := x"eef0b198";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120511";
result.sdb_component.product.name := "WB4-Bridge-GSI ";
return result;
end f_xwb_bridge_manual_sdb;
function f_xwb_bridge_layout_sdb(
g_wraparound : boolean := true;
g_layout : t_sdb_record_array;
g_sdb_addr : t_wishbone_address) return t_sdb_bridge
is
alias c_layout : t_sdb_record_array(g_layout'length-1 downto 0) is g_layout;
-- How much space does the ROM need?
constant c_used_entries : natural := c_layout'length + 1;
constant c_rom_entries : natural := 2**f_ceil_log2(c_used_entries); -- next power of 2
constant c_sdb_bytes : natural := c_sdb_device_length / 8;
constant c_rom_bytes : natural := c_rom_entries * c_sdb_bytes;
variable result : unsigned(63 downto 0);
variable sdb_component : t_sdb_component;
begin
if not g_wraparound then
result := (others => '0');
for i in 0 to c_wishbone_address_width-1 loop
result(i) := '1';
end loop;
else
-- The ROM will be an addressed slave as well
result := (others => '0');
result(c_wishbone_address_width-1 downto 0) := unsigned(g_sdb_addr);
result := result + to_unsigned(c_rom_bytes, 64) - 1;
for i in c_layout'range loop
sdb_component := f_sdb_extract_component(c_layout(i)(447 downto 8));
if unsigned(sdb_component.addr_last) > result then
result := unsigned(sdb_component.addr_last);
end if;
end loop;
-- round result up to a power of two -1
for i in 62 downto 0 loop
result(i) := result(i) or result(i+1);
end loop;
end if;
return f_xwb_bridge_manual_sdb(std_logic_vector(result(c_wishbone_address_width-1 downto 0)), g_sdb_addr);
end f_xwb_bridge_layout_sdb;
function f_xwb_dpram(g_size : natural) return t_sdb_device
is
variable result : t_sdb_device;
begin
result.abi_class := x"0001"; -- RAM device
result.abi_ver_major := x"01";
result.abi_ver_minor := x"00";
result.wbd_width := x"7"; -- 32/16/8-bit supported
result.wbd_endian := c_sdb_endian_big;
result.sdb_component.addr_first := (others => '0');
result.sdb_component.addr_last := std_logic_vector(to_unsigned(g_size*4-1, 64));
result.sdb_component.product.vendor_id := x"000000000000CE42"; -- CERN
result.sdb_component.product.device_id := x"66cfeb52";
result.sdb_component.product.version := x"00000001";
result.sdb_component.product.date := x"20120305";
result.sdb_component.product.name := "WB4-BlockRAM ";
return result;
end f_xwb_dpram;
function f_bits2string(s : std_logic_vector) return string is
--- extend length to full hex nibble
variable result : string((s'length+7)/4 downto 1);
variable s_norm : std_logic_vector(result'length*4-1 downto 0) := (others=>'0');
variable cut : natural;
variable nibble: std_logic_vector(3 downto 0);
begin
s_norm(s'length-1 downto 0) := s;
for i in result'length-1 downto 0 loop
nibble := s_norm(i*4+3 downto i*4);
case nibble is
when "0000" => result(i+1) := '0';
when "0001" => result(i+1) := '1';
when "0010" => result(i+1) := '2';
when "0011" => result(i+1) := '3';
when "0100" => result(i+1) := '4';
when "0101" => result(i+1) := '5';
when "0110" => result(i+1) := '6';
when "0111" => result(i+1) := '7';
when "1000" => result(i+1) := '8';
when "1001" => result(i+1) := '9';
when "1010" => result(i+1) := 'a';
when "1011" => result(i+1) := 'b';
when "1100" => result(i+1) := 'c';
when "1101" => result(i+1) := 'd';
when "1110" => result(i+1) := 'e';
when "1111" => result(i+1) := 'f';
when others => result(i+1) := 'X';
end case;
end loop;
-- trim leading 0s
strip : for i in result'length downto 1 loop
cut := i;
exit strip when result(i) /= '0';
end loop;
return "0x" & result(cut downto 1);
end f_bits2string;
-- Converts string (hex number, without leading 0x) to std_logic_vector
function f_string2bits(s : string) return std_logic_vector is
variable slv : std_logic_vector(s'length*4-1 downto 0);
variable nibble : std_logic_vector(3 downto 0);
begin
for i in 0 to s'length-1 loop
case s(i+1) is
when '0' => nibble := X"0";
when '1' => nibble := X"1";
when '2' => nibble := X"2";
when '3' => nibble := X"3";
when '4' => nibble := X"4";
when '5' => nibble := X"5";
when '6' => nibble := X"6";
when '7' => nibble := X"7";
when '8' => nibble := X"8";
when '9' => nibble := X"9";
when 'a' => nibble := X"A";
when 'A' => nibble := X"A";
when 'b' => nibble := X"B";
when 'B' => nibble := X"B";
when 'c' => nibble := X"C";
when 'C' => nibble := X"C";
when 'd' => nibble := X"D";
when 'D' => nibble := X"D";
when 'e' => nibble := X"E";
when 'E' => nibble := X"E";
when 'f' => nibble := X"F";
when 'F' => nibble := X"F";
when others => nibble := "XXXX";
end case;
slv(((i+1)*4)-1 downto i*4) := nibble;
end loop;
return slv;
end f_string2bits;
-- Converts string to ascii (std_logic_vector)
function f_string2svl (s : string) return std_logic_vector is
variable slv : std_logic_vector((s'length * 8) - 1 downto 0);
begin
for i in 0 to s'length-1 loop
slv(slv'high-i*8 downto (slv'high-7)-i*8) :=
std_logic_vector(to_unsigned(character'pos(s(i+1)), 8));
end loop;
return slv;
end f_string2svl;
-- Converts ascii (std_logic_vector) to string
function f_slv2string (slv : std_logic_vector) return string is
variable s : string(1 to slv'length/8);
begin
for i in 0 to (slv'length/8)-1 loop
s(i+1) := character'val(to_integer(unsigned(slv(slv'high-i*8 downto (slv'high-7)-i*8))));
end loop;
return s;
end f_slv2string;
-- pads a string of unknown length to a given length (useful for integer'image)
function f_string_fix_len ( s : string; ret_len : natural := 10; fill_char : character := '0' ) return string is
variable ret_v : string (1 to ret_len);
constant pad_len : integer := ret_len - s'length ;
variable pad_v : string (1 to abs(pad_len));
begin
if pad_len < 1 then
ret_v := s(ret_v'range);
else
pad_v := (others => fill_char);
ret_v := pad_v & s;
end if;
return ret_v;
end f_string_fix_len;
function f_hot_to_bin(x : std_logic_vector) return natural is
variable rv : natural;
begin
rv := 0;
-- if there are few ones set in _x_ then the most significant will be
-- translated to bin
for i in 0 to x'left loop
if x(i) = '1' then
rv := i+1;
end if;
end loop;
return rv;
end function;
function f_wb_spi_flash_sdb(g_bits : natural) return t_sdb_device is
variable result : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"02",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000ffffff",
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"5cf12a1c",
version => x"00000002",
date => x"20140417",
name => "SPI-FLASH-16M-MMAP ")));
begin
result.sdb_component.addr_last := std_logic_vector(to_unsigned(2**g_bits-1, 64));
return result;
end f_wb_spi_flash_sdb;
end wishbone_pkg;
|
lgpl-3.0
|
7605bdec7200ab503c72fb28a9345d10
| 0.574565 | 3.348907 | false | false | false | false |
denis4net/hw_design
|
2/altera-project/src/main.vhd
| 1 | 2,097 |
-- Variant 13
-- 8 bit counter with input registers
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity COUNTER8 is
port (
DATA: in std_logic_vector(7 downto 0);
NCCLR, NCCKEN, CCK, NCLOAD, RCK: in std_logic;
NRCO: out std_logic;
QDATA: out std_logic_vector(7 downto 0)
);
end entity;
architecture counter_arch of COUNTER8 is
component MEMCELL
port(
A, B, NRCK, CLOAD, NCCLR: in std_logic;
O: out std_logic
);
end component;
component COLLECTOR
port(
A: in std_logic_vector(7 downto 0);
B: out std_logic_vector(6 downto 0);
NRCO: out std_logic;
CLK: in std_logic
);
end component;
component CLKBLK is
port (
NCLKEN, NCCLR: in std_logic;
CCK: in std_logic;
IN_CCK: out std_logic
);
end component;
signal IN_CCK, CLOAD, NRCK: std_logic;
signal COLLECTOR_IN: std_logic_vector(7 downto 0);
signal CARRY: std_logic_vector(6 downto 0);
begin
CLOAD <= not NCLOAD;
NRCK <= RCK;
CLKBLK0: CLKBLK port map(CCK=>CCK, NCLKEN=>NCCKEN, IN_CCK=>IN_CCK, NCCLR=>NCCLR);
COLLECTOR0: COLLECTOR port map(A=>COLLECTOR_IN, B=>CARRY, CLK=>IN_CCK, NRCO=>NRCO);
QDATA <= COLLECTOR_IN;
CELL0: MEMCELL port map(A=>DATA(0), B=>IN_CCK, NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(0));
CELL1: MEMCELL port map(A=>DATA(1), B=>CARRY(0), NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(1));
CELL2: MEMCELL port map(A=>DATA(2), B=>CARRY(1), NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(2));
CELL3: MEMCELL port map(A=>DATA(3), B=>CARRY(2), NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(3));
CELL4: MEMCELL port map(A=>DATA(4), B=>CARRY(3), NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(4));
CELL5: MEMCELL port map(A=>DATA(5), B=>CARRY(4), NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(5));
CELL6: MEMCELL port map(A=>DATA(6), B=>CARRY(5), NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(6));
CELL7: MEMCELL port map(A=>DATA(7), B=>CARRY(6), NRCK=>NRCK, CLOAD=>CLOAD, NCCLR=>NCCLR, O=>COLLECTOR_IN(7));
end architecture;
|
mit
|
8aedeb0bbf76bb884cf791277a7d53a7
| 0.674297 | 2.698842 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a/simulation/behavioral/bfm_processor_wrapper.vhd
| 6 | 4,975 |
-------------------------------------------------------------------------------
-- bfm_processor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_master_bfm_v1_00_a;
use plbv46_master_bfm_v1_00_a.all;
entity bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end bfm_processor_wrapper;
architecture STRUCTURE of bfm_processor_wrapper is
component plbv46_master_bfm is
generic (
PLB_MASTER_SIZE : std_logic_vector(0 to 1);
PLB_MASTER_NUM : std_logic_vector(0 to 3);
PLB_MASTER_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_MASTER_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_MASTER_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_MASTER_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MPLB_DWIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_MPLB_DWIDTH/8)-1));
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to (C_MPLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
begin
bfm_processor : plbv46_master_bfm
generic map (
PLB_MASTER_SIZE => B"10",
PLB_MASTER_NUM => B"0000",
PLB_MASTER_ADDR_LO_0 => X"00000000",
PLB_MASTER_ADDR_HI_0 => X"00000000",
PLB_MASTER_ADDR_LO_1 => X"00000000",
PLB_MASTER_ADDR_HI_1 => X"00000000",
C_MPLB_DWIDTH => 128
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSsize => PLB_MSsize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst
);
end architecture STRUCTURE;
|
gpl-3.0
|
9643de9580fe91666b7ec154b684357c
| 0.580503 | 3.199357 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/lm32_ram.vhd
| 2 | 1,882 |
-- Work-alike to lm32_ram.v, but using generic_simple_dpram
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity lm32_ram is
generic(
data_width : natural := 1;
address_width : natural := 1);
port(
read_clk : in std_logic;
write_clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
read_address : in std_logic_vector(address_width-1 downto 0);
enable_write : in std_logic;
write_address : in std_logic_vector(address_width-1 downto 0);
write_data : in std_logic_vector(data_width -1 downto 0);
write_enable : in std_logic;
read_data : out std_logic_vector(data_width -1 downto 0));
end lm32_ram;
architecture syn of lm32_ram is
signal wea : std_logic;
signal reb : std_logic;
-- Emulate read-enable using another bypass
signal old_data : std_logic_vector(data_width-1 downto 0);
signal new_data : std_logic_vector(data_width-1 downto 0);
signal data : std_logic_vector(data_width-1 downto 0);
begin
wea <= enable_write and write_enable;
ram : generic_simple_dpram
generic map(
g_data_width => data_width,
g_size => 2**address_width,
g_with_byte_enable => false,
g_addr_conflict_resolution => "write_first",
g_dual_clock => false) -- read_clk always = write_clk in LM32
port map(
clka_i => read_clk,
wea_i => wea,
aa_i => write_address,
da_i => write_data,
clkb_i => write_clk,
ab_i => read_address,
qb_o => new_data);
data <= old_data when reb='0' else new_data;
read_data <= data;
main : process(read_clk) is
begin
if rising_edge(read_clk) then
old_data <= data;
reb <= enable_read;
end if;
end process;
end syn;
|
lgpl-3.0
|
97c4ba1728919c68ddab59e8c4ac7f84
| 0.593518 | 3.211604 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/dcr_timebase_v1_00_b/hdl/vhdl/dcr_timebase.vhd
| 2 | 5,183 |
--
--
-- register at offset 0 is timebase. read- and writeable
-- reguster at offset 1 is control register. not yet used.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.ipif_pkg.all;
--library opb_ipif_v3_01_c;
--use opb_ipif_v3_01_c.all;
entity dcr_timebase is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32
);
port (
i_clk : in std_logic;
i_reset : in std_logic;
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
o_timeBase : out std_logic_vector(0 to C_DCR_DWIDTH-1);
o_irq : out std_logic
);
end dcr_timebase;
architecture implementation of dcr_timebase is
constant C_NUM_REGS : natural := 2;
signal dcrDBus : std_logic_vector( 0 to C_DCR_DWIDTH-1 );
signal dcrAck : std_logic;
signal dcrAddrHit : std_logic;
signal regAddr : std_logic_vector(0 to 0); -- FIXME: hardcoded
signal readCE : std_logic_vector(0 to C_NUM_REGS-1);
signal writeCE : std_logic_vector(0 to C_NUM_REGS-1);
signal slv_reg0 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal timebase : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal set_timebase : std_logic := '0'; -- loads slv_reg0 into timebase when '1'
begin
-- generate outputs
o_dcrAck <= dcrAck;
o_dcrDBus <= dcrDBus;
-- 2 registers = 1 LSBs FIXME: hardcoded. Use log2 instead!
dcrAddrHit <= '1' when i_dcrABus(0 to C_DCR_AWIDTH-2) = C_DCR_BASEADDR(0 to C_DCR_AWIDTH-2)
else '0';
regAddr <= i_dcrABus(C_DCR_AWIDTH-1 to C_DCR_AWIDTH-1);
--
-- decode read and write accesses into chip enable signals
-- ASYNCHRONOUS
--
ce_gen : process(dcrAddrHit, i_dcrRead, i_dcrWrite,
regAddr)
begin
-- clear all chip enables by default
for i in 0 to C_NUM_REGS-1 loop
readCE(i) <= '0';
writeCE(i) <= '0';
end loop;
-- decode register address and set
-- corresponding chip enable signal
if dcrAddrHit = '1' then
if i_dcrRead = '1' then
readCE(TO_INTEGER(unsigned(regAddr))) <= '1';
elsif i_dcrWrite = '1' then
writeCE(TO_INTEGER(unsigned(regAddr))) <= '1';
end if;
end if;
end process;
--
-- generate DCR slave acknowledge signal
-- SYNCHRONOUS
--
gen_ack_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
dcrAck <= '0';
elsif rising_edge(i_clk) then
dcrAck <= ( i_dcrRead or i_dcrWrite ) and
dcrAddrHit;
end if;
end process;
--
-- update slave registers on write access
-- SYNCHRONOUS
--
reg_write_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
set_timebase <= '0';
elsif rising_edge(i_clk) then
set_timebase <= '0';
if dcrAck = '0' then -- register values only ONCE per write select
case writeCE is
when "01" =>
slv_reg0 <= i_dcrDBus;
set_timebase <= '1';
when "10" =>
slv_reg1 <= i_dcrDBus;
when others => null;
end case;
end if;
end if;
end process;
--
-- output slave registers on data bus on read access
-- ASYNCHRONOUS
--
reg_read_proc: process(readCE, timebase, slv_reg1,
i_dcrDBus)
begin
dcrDBus <= i_dcrDBus;
case readCE is
when "01" =>
dcrDBus <= timebase;
when "10" =>
dcrDBus <= slv_reg1;
when others =>
dcrDBus <= i_dcrDBus;
end case;
end process;
--
-- timebase register implementation
--
timebase_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
timebase <= (others => '0');
elsif rising_edge(i_clk) then
if set_timebase = '1' then
timebase <= slv_reg0;
else
timebase <= STD_LOGIC_VECTOR(UNSIGNED(timebase) + 1);
end if;
end if;
end process;
o_timeBase <= timebase;
o_irq <= '1' when timebase = X"FFFFFFFF" else '0';
end implementation;
|
gpl-3.0
|
d1a9dab874fbf1bc9ab4d89cb9892a46
| 0.518233 | 3.72342 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/framework/observation.vhd
| 1 | 42,473 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity observation is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- CHANGE 1 OF 7
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
-- END CHANGE
);
end observation;
architecture Behavioral of observation is
component uf_extract_observation is
Port(
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- parameters loaded
parameter_loaded : in std_logic;
parameter_loaded_ack : out std_logic;
-- new particle loaded
new_particle : in std_logic;
new_particle_ack : out std_logic;
-- input data address
input_data_address : in std_logic_vector(0 to 31);
input_data_needed : out std_logic;
-- get word data
word_data_en : in std_logic;
word_address : out std_logic_vector(0 to 31);
word_data : in std_logic_vector(0 to 31);
word_data_ack : out std_logic;
-- if the observation is calculated, this signal has to be set to '1'
finished : out std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
constant C_MB_EXIT : std_logic_vector(0 to 31) := X"00000003";
-- states
type state_t is (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_CALCULATE_REMAINING_OBSERVATIONS_6,
STATE_CALCULATE_REMAINING_OBSERVATIONS_7,
STATE_CALCULATE_REMAINING_OBSERVATIONS_8,
STATE_CALCULATE_REMAINING_OBSERVATIONS_9,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_READ_NEXT_PARTICLE,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_INPUT_DATA,
STATE_CACHE_HIT,
STATE_CACHE_MISS,
STATE_CACHE_MISS_2,
STATE_LOAD_WORD,
STATE_LOAD_WORD_2,
STATE_WRITE_WORD_BACK,
STATE_WRITE_WORD_ACK,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_EXIT
); -- 51 states = 0x00 - 0x32
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07",
X"08",
X"09",
X"0A",
X"0B",
X"0C",
X"0D",
X"0E",
X"0F",
X"10",
X"11",
X"12",
X"13",
X"14",
X"15",
X"16",
X"17",
X"18",
X"19",
X"1A",
X"1B",
X"1C",
X"1D",
X"1E",
X"1F",
X"20",
X"21",
X"22",
X"23",
X"24",
X"25",
X"26",
X"27",
X"28",
X"29",
X"2A",
X"2B",
X"2C",
X"2D",
X"2E",
X"2F",
X"30",
X"31",
X"32",
X"33"
);
constant decode : decode_t := (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLE_ADDRESS,
STATE_READ_NUMBER_OF_PARTICLES,
STATE_READ_PARTICLE_SIZE,
STATE_READ_BLOCK_SIZE,
STATE_READ_OBSERVATION_SIZE,
STATE_NEEDED_BURSTS,
STATE_NEEDED_BURSTS_2,
STATE_LENGTH_LAST_BURST,
STATE_LENGTH_LAST_BURST_2,
STATE_READ_OBSERVATION_ARRAY_ADDRESS,
STATE_READ_INPUT_DATA_LINK_ADDRESS,
STATE_READ_PARAMETER_SIZE,
STATE_READ_PARAMETER_ADDRESS,
STATE_COPY_PARAMETER,
STATE_COPY_PARAMETER_2,
STATE_COPY_PARAMETER_3,
STATE_COPY_PARAMETER_ACK,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_OBSERVATIONS_1,
STATE_CALCULATE_REMAINING_OBSERVATIONS_2,
STATE_CALCULATE_REMAINING_OBSERVATIONS_3,
STATE_CALCULATE_REMAINING_OBSERVATIONS_4,
STATE_CALCULATE_REMAINING_OBSERVATIONS_5,
STATE_CALCULATE_REMAINING_OBSERVATIONS_6,
STATE_CALCULATE_REMAINING_OBSERVATIONS_7,
STATE_CALCULATE_REMAINING_OBSERVATIONS_8,
STATE_CALCULATE_REMAINING_OBSERVATIONS_9,
STATE_READ_INPUT_DATA_ADDRESS,
STATE_READ_NEXT_PARTICLE,
STATE_START_EXTRACT_OBSERVATION,
STATE_START_EXTRACT_OBSERVATION_WAIT,
STATE_EXTRACT_OBSERVATION,
STATE_GET_INPUT_DATA,
STATE_CACHE_HIT,
STATE_CACHE_MISS,
STATE_CACHE_MISS_2,
STATE_LOAD_WORD,
STATE_LOAD_WORD_2,
STATE_WRITE_WORD_BACK,
STATE_WRITE_WORD_ACK,
STATE_WRITE_OBSERVATION,
STATE_WRITE_OBSERVATION_2,
STATE_WRITE_OBSERVATION_3,
STATE_WRITE_OBSERVATION_4,
STATE_MORE_PARTICLES,
STATE_MORE_PARTICLES_2,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_EXIT
);
-- current state
signal state : state_t := STATE_CHECK;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- := "00010000000000000000000000000000";
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
--local RAM cache addresses
signal local_ram_cache_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := "00000000000000000001111110000000";
signal local_ram_cache_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := "011111100000";
signal cache_min : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal cache_max : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- lin/pointer to memory word, where the input address is stored
signal input_data_link_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of observations
signal remaining_observations : integer := 2;
-- number of needed bursts
signal number_of_bursts : integer := 3;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 3;
-- length of last burst
signal length_of_last_burst : integer := 7;
-- size of a particle
signal particle_size : integer := 32;
-- number of particles
signal N : integer := 20;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal cache_offset : integer := 0;
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 2;
-- current particle data
signal particle_data : integer := 0;
-- parameter address
signal parameter_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- parameter size
signal parameter_size : integer := 0;
-- parameter loaded
signal parameter_loaded : std_logic := '0';
-- parameters acknowledged by user process
signal parameter_loaded_ack : std_logic; -- := '0';
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
--signal time_start : integer := 0;
--signal time_stop : integer := 0;
--signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- new particle loaded
signal new_particle : std_logic := '0';
-- new particle loaded - ackowledgement
signal new_particle_ack : std_logic := '1';
-- input data address
signal input_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- input data needed signal
signal input_data_needed : std_logic := '0';
-- word data enable
signal word_data_en : std_logic := '0';
-- word data address
signal word_data : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- word address
signal word_address : std_logic_vector(0 to 31) := (others => '0');
-- word_ack
signal word_data_ack : std_logic := '0';
-- if the observation is extracted, this signal is set to '1'
signal finished : std_logic := '1';
--current address
signal current_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- for switch 1: corrected local ram address. the least bit is inverted,
-- because else the local ram will be used incorrect
signal o_RAMAddrExtractObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this observation thread
signal o_RAMAddrObservation : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEExtractObservation : std_logic := '0';
-- for switch 2: Write enable, observation
signal o_RAMWEObservation : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataExtractObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, observation
signal o_RAMDataObservation : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_extract_observation
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrExtractObservation,
o_RAMData=>o_RAMDataExtractObservation, i_RAMData=>i_RAMData,
o_RAMWE=>o_RAMWEExtractObservation, o_RAMClk=>o_RAMClk,
parameter_loaded=>parameter_loaded, parameter_loaded_ack=>parameter_loaded_ack,
new_particle=>new_particle, new_particle_ack=>new_particle_ack,
input_data_address=>input_data_address, input_data_needed=>input_data_needed,
word_data_en=>word_data_en, word_address=>word_address,
word_data=>word_data, word_data_ack=>word_data_ack,
init=>init, enable=>enable, finished=>finished);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrExtractObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrExtractObservation(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrObservation(0 to C_BURST_AWIDTH-2) & not o_RAMAddrObservation(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEExtractObservation when enable = '1' else o_RAMWEObservation;
-- switch 3: output ram data
o_RAMData <= o_RAMDataExtractObservation when enable = '1' else o_RAMDataObservation;
-----------------------------------------------------------------------------
--
-- ReconOS State Machine for Observation:
--
-----------------------------------------------------------------------------
--
-- 1) read data from information struct
--
-- 2) receive message m
--
-- 3) set current address for input data
--
-- 4) load current particle (into local ram, starting address (others=>'0'))
--
-- 5) start user process for observation extraction
--
-- 6) wait for finished signal of user process
--
-- 7) write observation into main memory (from local ram, starting address (others=>'0'))
--
-- 8) if more particle need to be processed
-- go to step 4
-- else
-- go to step 9
--
-- 9) send message m
--
-- 9*) send measurement
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable parameter_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable preempted : boolean;
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"0B0B0B0B");
resume_state_enc := (others => '0');
done := false;
success := false;
preempted := false;
state <= STATE_CHECK;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case (state) is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
-- preempted
preempted := true;
state <= decode(to_integer(unsigned(resume_state_enc)));
else
-- unpreempted
state <= STATE_INIT;
end if;
end if;
when STATE_INIT =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
if done then
local_ram_cache_address <= "00000000000000000001111110000000";
local_ram_cache_address_if <= "011111100000";
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
new_particle <= '0';
parameter_loaded <= '0';
-- CHANGE CHANGE CHANGE
state <= STATE_READ_PARTICLE_ADDRESS;
--state <= STATE_WAIT_FOR_MESSAGE;
-- END OF CHANGE CHANGE CHANGE
-- CHANGE 2 OF 7
--state <= STATE_NEEDED_BURSTS;
-- END CHANGE
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ INFORMATION_STRUCT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_PARTICLE_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= STATE_READ_NUMBER_OF_PARTICLES;
end if;
when STATE_READ_NUMBER_OF_PARTICLES =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_OBSERVATION_SIZE;
end if;
when STATE_READ_OBSERVATION_SIZE =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= STATE_NEEDED_BURSTS;
end if;
when STATE_NEEDED_BURSTS =>
--! calculate needed bursts
number_of_bursts_remember <= observation_size / 128;
state <= STATE_LENGTH_LAST_BURST;
when STATE_LENGTH_LAST_BURST =>
--! calculate number of reads (1 of 2)
length_of_last_burst <= observation_size mod 128;
state <= STATE_LENGTH_LAST_BURST_2;
when STATE_LENGTH_LAST_BURST_2 =>
--! calculate number of reads (2 of 2)
length_of_last_burst <= length_of_last_burst / 8;
state <= STATE_READ_OBSERVATION_ARRAY_ADDRESS;
-- CHANGE 3 OF 7
--state <= STATE_WAIT_FOR_MESSAGE;
-- END CHANGE
when STATE_READ_OBSERVATION_ARRAY_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+20, observation_array_start_address);
if done then
state <= STATE_READ_INPUT_DATA_LINK_ADDRESS;
end if;
when STATE_READ_INPUT_DATA_LINK_ADDRESS =>
--! read observation array address
reconos_read_s (done, o_osif, i_osif, information_struct+24, input_data_link_address);
if done then
--state <= STATE_WAIT_FOR_MESSAGE;
state <= STATE_READ_PARAMETER_SIZE;
end if;
when STATE_READ_PARAMETER_SIZE =>
--! read parameter size
reconos_read (done, o_osif, i_osif, information_struct+28, parameter_size_var);
if done then
parameter_size <= TO_INTEGER(SIGNED(parameter_size_var));
state <= STATE_READ_PARAMETER_ADDRESS;
end if;
when STATE_READ_PARAMETER_ADDRESS =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, information_struct+32, parameter_address);
if done then
state <= STATE_COPY_PARAMETER;
local_ram_address_if <= local_ram_start_address_if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 1: READ PARAMETERS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_COPY_PARAMETER =>
--! read parameter size
o_RAMWEObservation <= '0';
if (parameter_size > 0) then
parameter_size <= parameter_size - 1;
state <= STATE_COPY_PARAMETER_2;
else
state <= STATE_COPY_PARAMETER_ACK;
parameter_loaded <= '1';
enable <= '1';
init <= '0';
end if;
when STATE_COPY_PARAMETER_2 =>
--! read parameter size
reconos_read_s (done, o_osif, i_osif, parameter_address, ram_data);
if done then
state <= STATE_COPY_PARAMETER_3;
end if;
when STATE_COPY_PARAMETER_3 =>
--! read parameter size
parameter_address <= parameter_address + 4;
local_ram_address_if <= local_ram_address_if + 1;
enable <= '0';
o_RAMWEObservation <= '1';
o_RAMAddrObservation <= local_ram_address_if;
o_RAMDataObservation <= ram_data;
state <= STATE_COPY_PARAMETER;
when STATE_COPY_PARAMETER_ACK =>
--! read parameter size
if (parameter_loaded_ack = '1') then
enable <= '0';
init <= '1';
parameter_loaded <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
if preempted then
preempted := false;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 2: WAIT FOR MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WAIT_FOR_MESSAGE =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
reconos_flag_yield(o_osif, i_osif, encode(STATE_WAIT_FOR_MESSAGE));
if done then
if success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
enable <= '0';
init <= '1';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
parameter_loaded <= '0';
if preempted then
state <= STATE_INIT;
else
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_1;
end if;
else
state <= STATE_EXIT;
end if;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
temp <= 0;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_2;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_2 =>
--! calculates particle array address and number of particles to sample
--temp <= message2 * block_size; -- timing error for virtex 4 ("18 setup errors")
if (message2 > 0) then
temp <= temp + block_size;
message2 <= message2 - 1;
else
-- temp = (message-1) * block_size
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_3;
end if;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_3 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_4;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_4 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_5;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_5 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_6;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_6 =>
--! calculates particle array address and number of particles to sample
temp3 <= temp * observation_size;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_7;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_7 =>
--! calculates particle array address and number of particles to sample
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_8;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_8 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
observation_array_address <= observation_array_start_address + temp3;
remaining_observations <= N - temp;
state <= STATE_CALCULATE_REMAINING_OBSERVATIONS_9;
when STATE_CALCULATE_REMAINING_OBSERVATIONS_9 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
end if;
state <= STATE_READ_INPUT_DATA_ADDRESS;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 3: READ CURRENT INPUT DATA ADDRESS
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_INPUT_DATA_ADDRESS =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, input_data_link_address, input_data_address);
if done then
state <= STATE_READ_NEXT_PARTICLE;
end if;
-- CHANGE 5 of 7
-- input data address: 0x20000000
--input_data_address <= "00100000000000000000000000000000";
-- the particle array address: 0x10000000
--particle_array_address <= "00010000000000000000000000000000";
-- the observation array address: 0x11000000
--observation_array_address <= "00010001000000000000000000000000";
--state <= STATE_READ_NEXT_PARTICLE;
-- END CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 4: WRITE PARTICLE INTO CURRENT RAM
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_READ_NEXT_PARTICLE =>
--! read next particle to local ram (writing the first 128 bytes to the local ram)
-- CHANGE CHANGE CHANGE
reconos_read_burst(done, o_osif, i_osif, local_ram_start_address, particle_array_address);
if done then
particle_array_address <= particle_array_address + particle_size;
-- CHANGE CHANGE CHANGE
state <= STATE_START_EXTRACT_OBSERVATION;
--state <= STATE_WRITE_OBSERVATION;
-- END OF CHANGE CHANGE CHANGE
end if;
-- END OF CHANGE CHANGE CHANGE
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
----
---- STEP 5: START OBSERVATION EXTRACTION
----
--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
when STATE_START_EXTRACT_OBSERVATION =>
--! start the user process
init <= '0';
enable <= '1';
new_particle <= '1';
state <= STATE_START_EXTRACT_OBSERVATION_WAIT;
when STATE_START_EXTRACT_OBSERVATION_WAIT =>
--! user process needs to start the execution
-- CHANGE CHANGE CHANGE
if new_particle_ack = '1' then
new_particle <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
-- END OF CHANGE CHANGE CHANGE
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 6: WAIT FOR OBSERVATION EXTRACTION TO FINISH / ANSWER DATA CALLS INBETWEEN
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_EXTRACT_OBSERVATION =>
--! check if observation is finished, or it input data is needed (from cache)
if finished = '1' then
-- observation finished
enable <= '0';
init <= '1';
new_particle <= '0';
state <= STATE_WRITE_OBSERVATION;
elsif input_data_needed = '1' then
state <= STATE_GET_INPUT_DATA;
end if;
when STATE_GET_INPUT_DATA =>
--! get input data at word_address (and write it into word_data)
enable <= '0';
cache_offset <= 0;
if (cache_min <= word_address) and (word_address < cache_max) then
-- cache hit
state <= STATE_CACHE_HIT;
--current_address <= cache_min;
current_address <= word_address - cache_min;
else
-- cache miss
state <= STATE_CACHE_MISS;
end if;
when STATE_CACHE_HIT =>
--! calculate the correct position in the local ram
cache_offset <= TO_INTEGER(UNSIGNED(current_address)) / 4;
state <= STATE_LOAD_WORD;
when STATE_CACHE_MISS =>
--! check if word address is double aligned
if (word_address(29) = '0') then
-- word address is double-word aligned (needed for read bursts)
cache_min <= word_address;
cache_max <= word_address + 128;
cache_offset <= 0;
else
-- word address is NOT double-word aligned => cache_min has to be adjusted
cache_min <= word_address - 4;
cache_max <= word_address + 124;
cache_offset <= 1;
end if;
state <= STATE_CACHE_MISS_2;
when STATE_CACHE_MISS_2 =>
--! reads 128 byte input burst into local ram cache
reconos_read_burst(done, o_osif, i_osif, local_ram_cache_address, cache_min);
if done then
state <= STATE_LOAD_WORD;
end if;
when STATE_LOAD_WORD =>
--! load word data
o_RAMAddrObservation <= local_ram_cache_address_if + cache_offset;
state <= STATE_LOAD_WORD_2;
when STATE_LOAD_WORD_2 =>
--! load word data (wait one cycle)
-- state <= STATE_LOAD_WORD_3;
--
--
-- when STATE_LOAD_WORD_3 =>
-- --! load word data (get word)
-- word_data <= i_RAMData;
state <= STATE_WRITE_WORD_BACK;
when STATE_WRITE_WORD_BACK =>
--! activate user process and transfer the word
enable <= '1';
word_data_en <= '1';
word_data <= i_RAMData;
state <= STATE_WRITE_WORD_ACK;
when STATE_WRITE_WORD_ACK =>
--! wait for acknowledgement
if word_data_ack = '1' then
word_data_en <= '0';
state <= STATE_EXTRACT_OBSERVATION;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 7: WRITE OBSERVATION TO MAIN MEMORY
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_WRITE_OBSERVATION =>
--! write observation (init)
number_of_bursts <= number_of_bursts_remember;
local_ram_address <= local_ram_start_address;
--write_histo_en <= '1';
state <= STATE_WRITE_OBSERVATION_2;
when STATE_WRITE_OBSERVATION_2 =>
--! write observation (check burst number)
if number_of_bursts > 0 then
-- more full bursts needed
state <= STATE_WRITE_OBSERVATION_3;
number_of_bursts <= number_of_bursts - 1;
elsif length_of_last_burst > 0 then
-- last burst needed (not full)
temp4 <= length_of_last_burst * 8;
state <= STATE_WRITE_OBSERVATION_4;
else
-- no last burst needed (which is not full)
state <= STATE_MORE_PARTICLES;
end if;
when STATE_WRITE_OBSERVATION_3 =>
--! write observation (write bursts)
reconos_write_burst(done, o_osif, i_osif, local_ram_address, observation_array_address);
if done then
observation_array_address <= observation_array_address + 128;
local_ram_address <= local_ram_address + 128;
state <= STATE_WRITE_OBSERVATION_2;
end if;
when STATE_WRITE_OBSERVATION_4 =>
--! write observation (write last burst)
reconos_write_burst_l(done, o_osif, i_osif, local_ram_address, observation_array_address, length_of_last_burst);
if done then
state <= STATE_MORE_PARTICLES;
observation_array_address <= observation_array_address + temp4;
local_ram_address <= local_ram_address + temp4;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 8: MORE PARTICLES?
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_MORE_PARTICLES =>
--! check if more particles need an observation
remaining_observations <= remaining_observations - 1;
state <= STATE_MORE_PARTICLES_2;
when STATE_MORE_PARTICLES_2 =>
--! check if more particles need an observation
if (remaining_observations > 0) then
state <= STATE_READ_NEXT_PARTICLE;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= STATE_SEND_MESSAGE;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9: SEND MESSAGE
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MESSAGE =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
state <= STATE_SEND_MEASUREMENT_1;
end if;
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
--
-- STEP 9*: SEND MEASURMENT
--
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
reconos_mbox_tryget(done, success, o_osif, i_osif, C_MB_EXIT, message_var);
if done then
if success then
state <= STATE_EXIT;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
-- state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when STATE_SEND_MEASUREMENT_2 =>
--! sends time measurement to message box
-- send message
--reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
--if (done and success) then
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
f94a8c5ff8cb1f0f1f9000230e7f9d1e
| 0.491889 | 4.399524 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S72_S72.vhd
| 1 | 6,370 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S72_S72.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (64 and 64) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S72_S72 is
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end entity BRAM_S72_S72;
architecture BRAM_S72_S72_arch of BRAM_S72_S72 is
component RAMB16_S36_S36
port (
ADDRA: in std_logic_vector(8 downto 0);
ADDRB: in std_logic_vector(8 downto 0);
DIA: in std_logic_vector(31 downto 0);
DIPA: in std_logic_vector(3 downto 0);
DIB: in std_logic_vector(31 downto 0);
DIPB: in std_logic_vector(3 downto 0);
WEA: in std_logic;
WEB: in std_logic;
CLKA: in std_logic;
CLKB: in std_logic;
SSRA: in std_logic;
SSRB: in std_logic;
ENA: in std_logic;
ENB: in std_logic;
DOA: out std_logic_vector(31 downto 0);
DOPA: out std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0);
DOPB: out std_logic_vector(3 downto 0));
END component;
signal doa1 : std_logic_vector (31 downto 0);
signal dob1 : std_logic_vector (31 downto 0);
signal doa2 : std_logic_vector (31 downto 0);
signal dob2 : std_logic_vector (31 downto 0);
signal dia1 : std_logic_vector (31 downto 0);
signal dib1 : std_logic_vector (31 downto 0);
signal dia2 : std_logic_vector (31 downto 0);
signal dib2 : std_logic_vector (31 downto 0);
signal dipa1: std_logic_vector(3 downto 0);
signal dipa2: std_logic_vector(3 downto 0);
signal dipb1: std_logic_vector(3 downto 0);
signal dipb2: std_logic_vector(3 downto 0);
signal dopa1: std_logic_vector(3 downto 0);
signal dopa2: std_logic_vector(3 downto 0);
signal dopb1: std_logic_vector(3 downto 0);
signal dopb2: std_logic_vector(3 downto 0);
begin
dia1(15 downto 0) <= DIA(15 downto 0);
dia2(15 downto 0) <= DIA(31 downto 16);
dia1(31 downto 16) <= DIA(47 downto 32);
dia2(31 downto 16) <= DIA(63 downto 48);
dib1 <= DIB(31 downto 0);
dib2 <= DIB(63 downto 32);
DOA(31 downto 0) <= doa1;
DOA(63 downto 32) <= doa2;
DOB(31 downto 0) <= dob1;
DOB(63 downto 32) <= dob2;
dipa1 <= dipa(3 downto 0);
dipa2 <= dipa(7 downto 4);
dopa(3 downto 0) <= dopa1;
dopa(7 downto 4) <= dopa2;
dipb1 <= dipb(3 downto 0);
dipb2 <= dipb(7 downto 4);
dopb(3 downto 0) <= dopb1;
dopb(7 downto 4) <= dopb2;
bram1: RAMB16_S36_S36
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: RAMB16_S36_S36
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S72_S72_arch;
|
gpl-3.0
|
e4b5c13aae87c060171f037a576133dd
| 0.428414 | 4.246667 | false | false | false | false |
luebbers/reconos
|
demos/huffman_demo/hw/src/hwt_build_histo.vhd
| 2 | 11,699 |
--**************************************************************************
-- $Id$
--
-- hwt_build_histo.vhd: ReconOS package
--
-- This hardware thread creates a histogram over a sequence of bytes. The
-- input is received in a sequence of blocks via a posix message queue.
-- After receiving the last block, the histogram is send to the outgoing
-- message queue.
--
-- Author : Andreas Agne <[email protected]>
-- Created: 1.8.2008
--*************************************************************************/
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_build_histo is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( C_BURST_AWIDTH-1 downto 0);
o_RAMData : out std_logic_vector( C_BURST_DWIDTH-1 downto 0);
i_RAMData : in std_logic_vector( C_BURST_DWIDTH-1 downto 0);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_build_histo is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_MQ_IN : std_logic_vector(31 downto 0) := X"00000000";
constant C_MQ_OUT : std_logic_vector(31 downto 0) := X"00000001";
-- ReconOS state machine
type t_state is (
STATE_INIT,
STATE_CLEAR_HISTOGRAM,
STATE_RECV_NUM_BLOCKS,
STATE_SAVE_NUM_BLOCKS,
STATE_LOOP,
STATE_RECV_BLOCK,
STATE_UPDATE_HISTOGRAM,
STATE_COPY_HISTOGRAM,
STATE_SEND_RESULT,
STATE_FINAL);
signal state : t_state;
signal block_size : std_logic_vector(31 downto 0); -- size of the last received block
-- update histogram
signal update_histo_en : std_logic; -- handshake signal
signal update_histo_done : std_logic; -- handshake signal
signal update_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal update_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- copy histogram
signal copy_histo_en : std_logic; -- handshake signal
signal copy_histo_done : std_logic; -- handshake signal
signal copy_histo_addr : std_logic_vector(C_BURST_AWIDTH-1 downto 0); -- burst ram addr
signal copy_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- clear histogram
signal clear_histo_en : std_logic; -- handshake signal
signal clear_histo_done : std_logic; -- handshake signal
signal clear_histo_bucket : std_logic_vector(7 downto 0); -- histogram addr
-- histogram
type t_ram is array (255 downto 0) of std_logic_vector(31 downto 0);
signal histo_ram : t_ram; -- histogram memory
signal histo_bucket : std_logic_vector(7 downto 0); -- current histogram bucket
signal histo_inc : std_logic; -- enables incrementing
signal histo_clear : std_logic; -- enables setting to zero
signal histo_value : std_logic_vector(31 downto 0); -- value of current bucket
signal histo_value_max : std_logic_vector(31 downto 0);
signal histo_value16 : std_logic_vector(15 downto 0);
begin
-- connect burst-ram to clk:
o_RAMClk <= clk;
-- histogram memory is basically a single port ram with
-- asynchronous read. the current bucket is incremented each
-- clock cycle when histo_inc is high, or set to zero when
-- histo_clear is high.
histo_value <= histo_ram(CONV_INTEGER(histo_bucket));
process(clk, reset)
variable tmp : std_logic_vector(31 downto 0);
begin
if reset = '1' then
tmp := (others => '0');
histo_value_max <= (others => '0');
elsif rising_edge(clk) then
if histo_inc = '1' then
if tmp > histo_value_max then
histo_value_max <= tmp;
end if;
tmp := histo_value + 1;
histo_ram(CONV_INTEGER(histo_bucket)) <= tmp;
elsif histo_clear = '1' then
histo_ram(CONV_INTEGER(histo_bucket)) <= (others => '0');
tmp := (others => '0');
histo_value_max <= (others => '0');
end if;
end if;
end process;
process(histo_value, histo_value_max)
variable max_bit : natural range 15 to 31;
begin
max_bit := 15;
for i in 16 to 31 loop
if histo_value_max(i) = '1' then
max_bit := i;
end if;
end loop;
histo_value16 <= histo_value(max_bit downto max_bit - 15);
end process;
-- signals and processes related to updating the histogram from
-- burst-ram data
update_histogramm : process(clk, reset, update_histo_en)
variable step : natural range 0 to 7;
begin
if reset = '1' or update_histo_en = '0' then
step := 0;
histo_inc <= '0';
update_histo_addr <= (others => '0');
update_histo_done <= '0';
update_histo_bucket <= (others => '0');
elsif rising_edge(clk) then
case step is
when 0 => -- set burst ram address to 0
update_histo_addr <= (others => '0');
step := step + 1;
when 1 => -- wait until address is valid
step := step + 1;
when 2 => -- turn on histogram incrementing, first byte
histo_inc <= '1';
update_histo_bucket <= i_ramdata(7 downto 0);
step := step + 1;
when 3 => -- second byte
update_histo_bucket <= i_ramdata(15 downto 8);
step := step + 1;
when 4 => -- load next word from burst ram, third byte
update_histo_bucket <= i_ramdata(23 downto 16);
if update_histo_addr + 1 < block_size(31 downto 2) then
update_histo_addr <= update_histo_addr + 1;
step := step + 1;
else
step := 6;
end if;
when 5 => -- last byte in word, continue
update_histo_bucket <= i_ramdata(31 downto 24);
step := 2;
when 6 => -- last byte in word, end of block
update_histo_bucket <= i_ramdata(31 downto 24);
step := step + 1;
when 7 => -- turn off histogram incrementing, set handshake signal
histo_inc <= '0';
update_histo_done <= '1';
end case;
end if;
end process;
-- signals and processes related to copying the histogram to
-- burst-ram
copy_histogram : process(clk, reset, copy_histo_en)
variable step : natural range 0 to 5;
begin
if reset = '1' or copy_histo_en = '0' then
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
copy_histo_done <= '0';
o_ramwe <= '0';
step := 0;
elsif rising_edge(clk) then
case step is
when 0 => -- set histogram and burst ram addresses to 0
copy_histo_addr <= (others => '0');
copy_histo_bucket <= (others => '0');
step := step + 1;
when 1 =>
o_ramdata(31 downto 16) <= histo_value16;
copy_histo_bucket <= copy_histo_bucket + 1;
step := step + 1;
when 2 => -- copy first word
copy_histo_addr <= (others => '0');
copy_histo_bucket <= copy_histo_bucket + 1;
o_ramwe <= '1';
o_ramdata(15 downto 0) <= histo_value16;
step := step + 1;
when 3 =>
o_ramdata(31 downto 16) <= histo_value16;
copy_histo_addr <= copy_histo_addr + 1;
copy_histo_bucket <= copy_histo_bucket + 1;
step := step + 1;
when 4 => -- copy remaining histogram buckets to burst ram
copy_histo_bucket <= copy_histo_bucket + 1;
o_ramwe <= '1';
o_ramdata(15 downto 0) <= histo_value16;
if copy_histo_addr >= 127 then
step := step + 1;
else
step := 3;
end if;
when 5 => -- all buckets copied -> set handshake signal
copy_histo_done <= '1';
o_ramwe <= '0';
end case;
end if;
end process;
-- signals and processes related to clearing the histogram
clear_histogram : process(clk, reset, clear_histo_en)
variable step : natural range 0 to 2;
begin
if reset = '1' or clear_histo_en = '0' then
step := 0;
histo_clear <= '0';
clear_histo_bucket <= (others => '0');
clear_histo_done <= '0';
elsif rising_edge(clk) then
case step is
when 0 => -- enable bucket zeroing
clear_histo_bucket <= (others => '0');
histo_clear <= '1';
step := step + 1;
when 1 => -- visit every bucket
clear_histo_bucket <= clear_histo_bucket + 1;
if clear_histo_bucket = 255 then
step := step + 1;
end if;
when 2 => -- set handshake signal
histo_clear <= '0';
clear_histo_done <= '1';
end case;
end if;
end process;
-- histogram ram mux
process(update_histo_en, copy_histo_en, clear_histo_en, update_histo_addr, update_histo_bucket,
copy_histo_addr, copy_histo_bucket, clear_histo_bucket)
variable addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0);
variable bucket : std_logic_vector(7 downto 0);
begin
if update_histo_en = '1' then
addr := update_histo_addr;
bucket := update_histo_bucket;
elsif copy_histo_en = '1' then
addr := copy_histo_addr;
bucket := copy_histo_bucket;
elsif clear_histo_en = '1' then
addr := (others => '0');
bucket := clear_histo_bucket;
else
addr := (others => '0');
bucket := (others => '0');
end if;
o_RAMAddr <= addr(C_BURST_AWIDTH - 1 downto 1) & not addr(0);
histo_bucket <= bucket;
end process;
-- the os interaction state machine performs the following sequential program:
--
-- set all histogram buckets to 0
-- receive the numer of blocks to process
-- for each block:
-- receive block
-- update histogram
-- copy histogram to burst ram
-- send histogram
--
state_proc: process( clk, reset )
variable done : boolean;
variable success : boolean;
variable num_blocks : std_logic_vector(31 downto 0);
variable len : std_logic_vector(31 downto 0);
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
done := false;
success := false;
num_blocks := (others => '0');
block_size <= (others => '0');
len := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
clear_histo_en <= '1';
state <= STATE_CLEAR_HISTOGRAM;
--reconos_get_init_data(done, o_osif, i_osif, offset);
--if done then state <= STATE_FILL; end if;
when STATE_CLEAR_HISTOGRAM =>
if clear_histo_done = '1' then
clear_histo_en <= '0';
state <= STATE_RECV_NUM_BLOCKS;
end if;
when STATE_RECV_NUM_BLOCKS =>
reconos_mq_receive(done, success, o_osif, i_osif, C_MQ_IN, X"00000000", len);
if done then
state <= STATE_SAVE_NUM_BLOCKS;
end if;
when STATE_SAVE_NUM_BLOCKS =>
num_blocks := i_ramdata;
state <= STATE_LOOP;
when STATE_LOOP =>
if num_blocks = 0 then
copy_histo_en <= '1';
state <= STATE_COPY_HISTOGRAM;
else
state <= STATE_RECV_BLOCK;
end if;
when STATE_RECV_BLOCK =>
reconos_mq_receive(done, success, o_osif, i_osif, C_MQ_IN, X"00000000", len);
if done then
state <= STATE_UPDATE_HISTOGRAM;
block_size <= len;
update_histo_en <= '1';
end if;
when STATE_UPDATE_HISTOGRAM =>
if update_histo_done = '1' then
update_histo_en <= '0';
num_blocks := num_blocks - 1;
state <= STATE_LOOP;
end if;
when STATE_COPY_HISTOGRAM =>
if copy_histo_done = '1' then
copy_histo_en <= '0';
state <= STATE_SEND_RESULT;
end if;
when STATE_SEND_RESULT =>
len := X"00000200";
reconos_mq_send(done,success,o_osif, i_osif, C_MQ_OUT, X"00000000", len);
if done then
state <= STATE_FINAL;
end if;
when others =>
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
bac985c6f8748ce030f04375fb383c10
| 0.61048 | 3.178212 | false | false | false | false |
luebbers/reconos
|
support/pcores/message_manager_v1_00_a/hdl/vhdl/message_manager.vhd
| 1 | 19,784 |
-- *************************
-- Message Manager
-- (Prototype)
--
-- Written by Jason Agron
-- *************************
-- FIXMEs:
-- * Add in support for full-handshaking (user -> queue -> back to user)
-- * Change underlying queue structure to be faster (eliminate useless states)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity message_manager is
generic(
START_WITH_TOKEN : integer := 0;
QUEUE_ADDRESS_WIDTH : integer := 9;
DATA_WIDTH : integer := 32;
CHANNEL_ID_WIDTH : integer := 8;
SENDER_ID_WIDTH : integer := 8
);
port(
-- System-Level Control Ports
clk : in std_logic;
reset : in std_logic;
-- User Interface Ports
i_request : in std_logic;
i_user_opcode : in std_logic_vector(0 to 7);
i_user_data : in std_logic_vector(0 to DATA_WIDTH-1);
i_user_channel : in std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
i_user_sender : in std_logic_vector(0 to SENDER_ID_WIDTH-1);
o_user_data : out std_logic_vector(0 to DATA_WIDTH-1);
o_user_channel : out std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
o_user_sender : out std_logic_vector(0 to SENDER_ID_WIDTH-1);
o_busy : out std_logic;
o_send_ready : out std_logic;
o_recv_ready : out std_logic;
-- System Ports - Incoming Packet Interface
i_packet_data : in std_logic_vector(0 to DATA_WIDTH-1);
i_packet_channel : in std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
i_packet_sender : in std_logic_vector(0 to SENDER_ID_WIDTH-1);
i_packet_valid : in std_logic;
-- System Ports -- Token Interface
i_token : in std_logic;
o_token : out std_logic;
-- System Ports - Outgoing Packet Interface
o_packet_data : out std_logic_vector(0 to DATA_WIDTH-1);
o_packet_channel : out std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
o_packet_sender : out std_logic_vector(0 to SENDER_ID_WIDTH-1);
o_packet_valid : out std_logic
);
end entity message_manager;
architecture IMP of message_manager is
-- *****************************
-- Function Definitions
-- *****************************
-- Form a packet from it's components
function form_packet(
channel : std_logic_vector(0 to CHANNEL_ID_WIDTH - 1);
sender : std_logic_vector(0 to SENDER_ID_WIDTH - 1);
data : std_logic_vector(0 to DATA_WIDTH - 1)
) return std_logic_vector is
begin
return (channel & sender & data);
end function form_packet;
-- Extract data field from a formed packet
function get_packet_data(formed_packet : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1)) return std_logic_vector is
begin
return formed_packet((CHANNEL_ID_WIDTH + SENDER_ID_WIDTH) to (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1));
end function get_packet_data;
-- Extract sender field from a formed packet
function get_packet_sender(formed_packet : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1)) return std_logic_vector is
begin
return formed_packet((CHANNEL_ID_WIDTH) to (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH - 1));
end function get_packet_sender;
-- Extract channel field from a formed packet
function get_packet_channel(formed_packet : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1)) return std_logic_vector is
begin
return formed_packet(0 to (CHANNEL_ID_WIDTH - 1));
end function get_packet_channel;
-- *****************************
-- Component declaration for queue IP
-- *****************************
COMPONENT fast_queue
generic(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
PORT(
clk : in std_logic;
rst : in std_logic;
add_busy : out std_logic;
remove_busy : out std_logic;
add : in std_logic;
remove : in std_logic;
entryToAdd : in std_logic_vector(0 to DATA_BITS-1);
head : out std_logic_vector(0 to DATA_BITS-1);
headValid : out std_logic;
full : out std_logic;
empty : out std_logic
);
END COMPONENT;
-- **********************************
-- Constant Defintions
-- **********************************
-- Message Manager Opcodes
constant RESET_SEND_QUEUE : std_logic_vector(0 to 7) := x"01";
constant RESET_RECV_QUEUE : std_logic_vector(0 to 7) := x"02";
constant REGISTER_CHANNEL : std_logic_vector(0 to 7) := x"03";
constant SEND_PACKET : std_logic_vector(0 to 7) := x"04";
constant RECV_PACKET : std_logic_vector(0 to 7) := x"05";
constant REGISTER_SENDER : std_logic_vector(0 to 7) := x"06";
constant GET_QUEUE_STATUS : std_logic_vector(0 to 7) := x"07";
-- Pseudonyms for token values
constant NO_TOKEN : std_logic := '0';
constant HAS_TOKEN : std_logic := '1';
-- Pseudonyms for token counter values
constant COUNTER_OUT_OF_TIME : std_logic_vector(0 to QUEUE_ADDRESS_WIDTH -1) := (others => '0');
constant COUNTER_RESET_VALUE : std_logic_vector(0 to QUEUE_ADDRESS_WIDTH -1) := (others => '1');
-- **********************************
-- Internal registers and signals
-- **********************************
-- Registers to hold channel to listen for and sender ID
signal listen_channel, listen_channel_next : std_logic_vector(0 to CHANNEL_ID_WIDTH - 1);
signal sender_id, sender_id_next : std_logic_vector(0 to SENDER_ID_WIDTH - 1);
-- Registers used to detect incoming (valid) packets
signal i_packet_valid_d1, incoming_packet : std_logic;
-- Token register and token down counter
signal token_register : std_logic;
signal token_counter : std_logic_vector(0 to QUEUE_ADDRESS_WIDTH - 1); -- Decrementing token counter (limits the number of packets that can be sent at once)
-- Signals used to connect SEND QUEUE
signal send_queue_reset : std_logic;
signal send_queue_add : std_logic;
signal send_queue_add_busy, send_queue_remove_busy : std_logic;
signal send_queue_remove : std_logic;
signal send_queue_entry_to_add, send_queue_entry_to_add_next : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal send_queue_head : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal send_queue_head_valid : std_logic;
signal send_queue_full : std_logic;
signal send_queue_empty : std_logic;
-- Signals used to connect RECV QUEUE
signal recv_queue_reset : std_logic;
signal recv_queue_add : std_logic;
signal recv_queue_add_busy, recv_queue_remove_busy : std_logic;
signal recv_queue_remove : std_logic;
signal recv_queue_entry_to_add : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal recv_queue_head : std_logic_vector(0 to CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH - 1);
signal recv_queue_head_valid : std_logic;
signal recv_queue_full : std_logic;
signal recv_queue_empty : std_logic;
-- Signals used to return data to user (b/c outputs are registered)
signal out_busy, out_busy_next : std_logic;
signal out_user_data, out_user_data_next : std_logic_vector(0 to DATA_WIDTH-1);
signal out_user_channel, out_user_channel_next : std_logic_vector(0 to CHANNEL_ID_WIDTH-1);
signal out_user_sender, out_user_sender_next : std_logic_vector(0 to SENDER_ID_WIDTH-1);
-- **************************
-- State definition for FSM
-- **************************
type state_type is (
IDLE,
RESET_MM,
CMD_RESET_SEND_QUEUE,
CMD_RESET_RECV_QUEUE,
CMD_REGISTER_CHANNEL,
CMD_REGISTER_SENDER,
CMD_SEND_PACKET,
CMD_RECV_PACKET,
CMD_GET_QUEUE_STATUS
);
signal current_state, next_state : state_type := IDLE;
begin
-- ********************************************************
-- Instantiations of receive (RECV) and send (SEND) queues
-- ********************************************************
SEND_QUEUE : fast_queue
generic map(
ADDRESS_BITS => QUEUE_ADDRESS_WIDTH,
DATA_BITS => (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH)
)
port map(
clk => clk,
rst => send_queue_reset,
add_busy => send_queue_add_busy,
remove_busy => send_queue_remove_busy,
add => send_queue_add,
remove => send_queue_remove,
entryToAdd => send_queue_entry_to_add,
head => send_queue_head,
headValid => send_queue_head_valid,
full => send_queue_full,
empty => send_queue_empty
);
RECV_QUEUE : fast_queue
generic map(
ADDRESS_BITS => QUEUE_ADDRESS_WIDTH,
DATA_BITS => (CHANNEL_ID_WIDTH + SENDER_ID_WIDTH + DATA_WIDTH)
)
port map(
clk => clk,
rst => recv_queue_reset,
add_busy => recv_queue_add_busy,
remove_busy => recv_queue_remove_busy,
add => recv_queue_add,
remove => recv_queue_remove,
entryToAdd => recv_queue_entry_to_add,
head => recv_queue_head,
headValid => recv_queue_head_valid,
full => recv_queue_full,
empty => recv_queue_empty
);
-- ************************************************************
-- Set up status signals for user
-- ************************************************************
o_send_ready <= (not out_busy) and (not send_queue_full) and (not send_queue_add_busy);
o_recv_ready <= (not out_busy) and (recv_queue_head_valid);
o_user_data <= out_user_data;
o_user_channel <= out_user_channel;
o_user_sender <= out_user_sender;
o_busy <= out_busy;
-- ************************************************************
-- Process: USER_COMMAND_CONTROLLER
-- Purpose: FSM Controller for processing user-driven commands
-- ************************************************************
USER_COMMAND_CONTROLLER : process (clk) is
begin
if (clk'event and clk = '1') then
if (reset = '1') then
-- Reset all FSM variables
current_state <= RESET_MM;
listen_channel <= (others => '0');
send_queue_entry_to_add <= (others => '0');
out_user_data <= (others => '0');
out_user_channel <= (others => '0');
out_user_sender <= (others => '0');
out_busy <= '0';
sender_id <= (others => '0');
else
-- Transition all FSM variables
current_state <= next_state;
listen_channel <= listen_channel_next;
send_queue_entry_to_add <= send_queue_entry_to_add_next;
out_user_data <= out_user_data_next;
out_user_channel <= out_user_channel_next;
out_user_sender <= out_user_sender_next;
out_busy <= out_busy_next;
sender_id <= sender_id_next;
end if;
end if;
end process USER_COMMAND_CONTROLLER;
-- *****************************************************
-- Process: USER_COMMAND_CONTROLLER_LOGIC
-- Purpose: FSM Logic to processs user-driven commands
-- *****************************************************
USER_COMMAND_CONTROLLER_LOGIC : process (
current_state, listen_channel, send_queue_entry_to_add, i_request,
i_user_opcode, i_user_channel, i_user_sender, i_user_data, recv_queue_head,
sender_id, send_queue_empty, send_queue_full, send_queue_add_busy,
send_queue_remove_busy, recv_queue_empty, recv_queue_full, recv_queue_add_busy,
recv_queue_remove_busy, send_queue_head_valid, recv_queue_head_valid, out_user_data, out_user_channel, out_user_sender
) is
begin
-- Set default values for FSM signals
send_queue_add <= '0';
send_queue_reset <= '0';
send_queue_entry_to_add_next <= send_queue_entry_to_add;
recv_queue_reset <= '0';
recv_queue_remove <= '0';
--out_user_data_next <= (others => '0');
--out_user_channel_next <= (others => '0');
--out_user_sender_next <= (others => '0');
out_user_data_next <= out_user_data;
out_user_channel_next <= out_user_channel;
out_user_sender_next <= out_user_sender;
out_busy_next <= '0';
listen_channel_next <= listen_channel;
sender_id_next <= sender_id;
-- FSM Logic:
case (current_state) is
-- ************************
-- IDLE State
-- ************************
when IDLE =>
-- Check if a request is coming in and check the opcode...
if (i_request = '1') then
case (i_user_opcode) is
when RESET_SEND_QUEUE =>
send_queue_reset <= '1';
next_state <= CMD_RESET_SEND_QUEUE;
out_busy_next <= '1';
when RESET_RECV_QUEUE =>
recv_queue_reset <= '1';
next_state <= CMD_RESET_RECV_QUEUE;
out_busy_next <= '1';
when REGISTER_CHANNEL =>
listen_channel_next <= i_user_channel;
next_state <= CMD_REGISTER_CHANNEL;
out_busy_next <= '1';
when REGISTER_SENDER =>
sender_id_next <= i_user_sender;
next_state <= CMD_REGISTER_SENDER;
out_busy_next <= '1';
when SEND_PACKET =>
-- send_queue_entry_to_add_next <= form_packet(i_user_channel, sender_id, i_user_data); -- Use existing senderID register
send_queue_entry_to_add_next <= form_packet(i_user_channel, i_user_sender, i_user_data); -- Use fresh senderID coming from user
next_state <= CMD_SEND_PACKET;
out_busy_next <= '1';
when RECV_PACKET =>
out_user_data_next <= get_packet_data(recv_queue_head);
out_user_channel_next <= get_packet_channel(recv_queue_head);
out_user_sender_next <= get_packet_sender(recv_queue_head);
next_state <= CMD_RECV_PACKET;
out_busy_next <= '1';
when GET_QUEUE_STATUS =>
next_state <= CMD_GET_QUEUE_STATUS;
out_busy_next <= '1';
when others =>
next_state <= IDLE;
out_busy_next <= '1';
end case;
-- If no request is coming in then just stay in the IDLE state
else
next_state <= IDLE;
out_busy_next <= '0';
end if;
-- ************************
-- RESET SEND QUEUE
-- ************************
when CMD_RESET_SEND_QUEUE =>
send_queue_reset <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- RESET RECV QUEUE
-- ************************
when CMD_RESET_RECV_QUEUE =>
recv_queue_reset <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- REGISTER CHANNEL ID
-- ************************
when CMD_REGISTER_CHANNEL =>
out_busy_next <= '0';
next_state <= IDLE;
-- ************************
-- REGISTER SENDER ID
-- ************************
when CMD_REGISTER_SENDER =>
out_busy_next <= '0';
next_state <= IDLE;
-- ************************
-- SEND PACKET
-- ************************
when CMD_SEND_PACKET =>
send_queue_add <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- RECEIVE PACKET
-- ************************
when CMD_RECV_PACKET =>
out_user_data_next <= get_packet_data(recv_queue_head);
out_user_channel_next <= get_packet_channel(recv_queue_head);
out_user_sender_next <= get_packet_sender(recv_queue_head);
recv_queue_remove <= '1';
out_busy_next <= '1';
next_state <= IDLE;
-- ************************
-- GET QUEUE STATUS
-- ************************
when CMD_GET_QUEUE_STATUS =>
out_user_data_next <= x"00000" & "00" &
(send_queue_empty & send_queue_full & send_queue_add_busy & send_queue_remove_busy & send_queue_head_valid) &
(recv_queue_empty & recv_queue_full & recv_queue_add_busy & recv_queue_remove_busy & recv_queue_head_valid);
out_busy_next <= '0';
next_state <= IDLE;
-- ************************
-- RESET MESSAGE MANAGER
-- ************************
when RESET_MM =>
send_queue_reset <= '1';
recv_queue_reset <= '1';
out_busy_next <= '1';
next_state <= IDLE;
when others =>
-- Should never come here!!!!
next_state <= RESET_MM;
end case;
end process USER_COMMAND_CONTROLLER_LOGIC;
-- *****************************************************
-- Process: TOKEN_ANALYSIS
-- Purpose: To capture and process tokens as needed
-- *****************************************************
TOKEN_ANALYSIS : process (clk) is
begin
if (clk'event and clk = '1') then
-- Reset all token logic
if (reset = '1') then
-- Implement the initial token holder logic
if (START_WITH_TOKEN = 1) then
token_register <= HAS_TOKEN;
else
token_register <= NO_TOKEN;
end if;
-- Reset token counter and output token value
token_counter <= COUNTER_RESET_VALUE;
o_token <= NO_TOKEN;
else
-- If we have the token and it is time to give it up
if (token_register = HAS_TOKEN and token_counter = COUNTER_OUT_OF_TIME) then
-- Reset the counter
token_counter <= COUNTER_RESET_VALUE;
-- Give up the token
token_register <= NO_TOKEN;
-- Transfer the token down the line
o_token <= HAS_TOKEN;
-- If we have the token, but we don't need the token (nothing in the send queue)
elsif (token_register = HAS_TOKEN and send_queue_empty = '1') then
-- Keep the token counter at it's reset value
token_counter <= COUNTER_RESET_VALUE;
-- Give up the token
token_register <= NO_TOKEN;
-- Transfer the token down the line
o_token <= HAS_TOKEN;
-- If we have the token and it is not yet time to give it up
elsif (token_register = HAS_TOKEN) then
-- Decrement the token counter
token_counter <= token_counter - 1;
-- Keep the token
token_register <= HAS_TOKEN;
-- Don't pass the token down the line
o_token <= NO_TOKEN;
-- Otherwise
else
-- Keep the token counter at it's reset value
token_counter <= COUNTER_RESET_VALUE;
-- Keep monitoring for incoming tokens
token_register <= i_token;
-- Don't pass a token down the line
o_token <= NO_TOKEN;
end if;
end if;
end if;
end process TOKEN_ANALYSIS;
-- *****************************************************
-- Process: INCOMING_PACKET_DETECTOR
-- Purpose: Detects incoming valid incoming packets
-- *****************************************************
INCOMING_PACKET_DETECTOR : process (clk) is
begin
if (clk'event and clk = '1') then
if (reset = '1') then
i_packet_valid_d1 <= '0';
else
i_packet_valid_d1 <= i_packet_valid;
end if;
end if;
end process INCOMING_PACKET_DETECTOR;
incoming_packet <= i_packet_valid and (not i_packet_valid_d1); -- Detects positive edges
-- *****************************************************
-- Process: INCOMING_PACKET_CONTROLLER
-- Purpose: Incoming Packet Filtering
-- *****************************************************
INCOMING_PACKET_CONTROLLER : process (clk) is
begin
if (clk'event and clk = '1') then
-- If a valid packet is coming in and it matches the channel we are listening on, capture it
if (incoming_packet = '1' and i_packet_channel = listen_channel and i_packet_sender /= sender_id) then
recv_queue_add <= '1';
recv_queue_entry_to_add <= form_packet(i_packet_channel, i_packet_sender, i_packet_data);
else
recv_queue_add <= '0';
recv_queue_entry_to_add <= (others => '0');
end if;
end if;
end process INCOMING_PACKET_CONTROLLER;
-- *****************************************************
-- Process: OUTGOING_PACKET_CONTROLLER
-- Purpose: Outgoing Packet Filtering
-- *****************************************************
OUTGOING_PACKET_CONTROLLER : process (clk) is
begin
if (clk'event and clk = '1') then
-- If we don't have a token, then just forward packets from incoming port to outgoing port (unless the packet is one that we sent, packet has cycled)
if (token_register = NO_TOKEN and i_packet_sender /= sender_id) then
o_packet_data <= i_packet_data;
o_packet_channel <= i_packet_channel;
o_packet_sender <= i_packet_sender;
o_packet_valid <= i_packet_valid;
send_queue_remove <= '0';
-- If we do have a token and we have packets to send, then send them
elsif ((token_register = HAS_TOKEN) and (send_queue_head_valid = '1')) then
o_packet_data <= get_packet_data(send_queue_head);
o_packet_channel <= get_packet_channel(send_queue_head);
o_packet_sender <= get_packet_sender(send_queue_head);
o_packet_valid <= '1';
send_queue_remove <= '1';
-- Otherwise, drive valid line to low
else
o_packet_data <= (others => '0');
o_packet_channel <= (others => '0');
o_packet_sender <= (others => '0');
o_packet_valid <= '0';
send_queue_remove <= '0';
end if;
end if;
end process OUTGOING_PACKET_CONTROLLER;
end architecture IMP;
|
gpl-3.0
|
41ca5defe021c57fe654c7efbb86a0a2
| 0.604074 | 3.116572 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/irq_gen_v1_1/f141c1dc/hdl/vhdl/slave_attachment.vhd
| 2 | 21,509 |
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library my_ipif;
use my_ipif.proc_common_pkg.clog2;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_num_ce;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
gpl-2.0
|
463e22eaeb89141f0549fbddab33e7f5
| 0.497001 | 3.969915 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/FontROM/synth/FontROM.vhd
| 1 | 6,769 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY FontROM IS
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END FontROM;
ARCHITECTURE FontROM_arch OF FontROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FontROM_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FontROM_arch: ARCHITECTURE IS "dist_mem_gen_v8_0_9,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FontROM_arch : ARCHITECTURE IS "FontROM,dist_mem_gen_v8_0_9,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FontROM_arch: ARCHITECTURE IS "FontROM,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=14,C_DEFAULT_DATA=0,C_DEPTH=16384,C_HAS_CLK=0,C_HAS_D=0,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=0,C_MEM_INIT_FILE=FontROM.mif,C_ELABORATION_DIR=./,C_MEM_TYPE=0,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=1,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=1,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 14,
C_DEFAULT_DATA => "0",
C_DEPTH => 16384,
C_HAS_CLK => 0,
C_HAS_D => 0,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 0,
C_MEM_INIT_FILE => "FontROM.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 0,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 1,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
clk => '0',
we => '0',
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END FontROM_arch;
|
mit
|
1d8762f2a366591dc22e2fdc144ed4b0
| 0.64367 | 3.189915 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/client/address_swap_module_8.vhd
| 1 | 14,023 |
-------------------------------------------------------------------------------
-- Title : Address Swapping Module
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : address_swap_module_8.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------
-- Description: - Takes in frame from the client-side EMAC reciever.
-- - Swaps the source address with destination address.
-- - Outputs the modified frame.
-- - rx_data_valid, rx_good_frame, rx_bad_frame are delayed
-- by an equal number of clock cycles to rx_data.
-- - The module consists of a six-stage shift register and
-- multiplexer to select data either from the shift
-- register output or directly from the data input. The
-- destination address is loaded into the shift register
-- and held whilst the source address is selected
-- directly from the input. Once the source address has
-- been output, data is taken from the shift register.
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity address_swap_module_8 is
port (
rx_ll_clock : in std_logic; -- Input CLK from TRIMAC Reciever
rx_ll_reset : in std_logic; -- Synchronous reset signal
rx_ll_data_in : in std_logic_vector(7 downto 0); -- Input data
rx_ll_sof_in_n : in std_logic; -- Input start of frame
rx_ll_eof_in_n : in std_logic; -- Input end of frame
rx_ll_src_rdy_in_n : in std_logic; -- Input source ready
rx_ll_data_out : out std_logic_vector(7 downto 0); -- Modified output data
rx_ll_sof_out_n : out std_logic; -- Output start of frame
rx_ll_eof_out_n : out std_logic; -- Output end of frame
rx_ll_src_rdy_out_n : out std_logic; -- Output source ready
rx_ll_dst_rdy_in_n : in std_logic -- Input destination ready
);
end address_swap_module_8;
architecture arch1 of address_swap_module_8 is
--Signal declarations
signal sel_delay_path : std_logic; -- controls mux in Process data_out_mux
signal enable_data_sr : std_logic; -- clock enable for data shift register
signal data_sr5 : std_logic_vector(7 downto 0); -- data after 6 cycle delay
signal mux_out : std_logic_vector(7 downto 0); -- data to output register
signal rx_enable : std_logic;
--FSM type and signals
type state_type is (wait_sf,
bypass_sa1,
bypass_sa2,
bypass_sa3,
bypass_sa4,
bypass_sa5,
bypass_sa6,
pass_rof);
signal control_fsm_state : state_type; -- holds state of control fsm
--6 stage shift register type and signals
type sr6by8 is array (0 to 5) of std_logic_vector(7 downto 0);
signal data_sr_content : sr6by8; -- holds contents of data sr
--7 stage shift register type and signals
type sr7by1 is array (0 to 6) of std_logic;
signal eof_sr_content : sr7by1; -- holds contents of end of frame sr
signal sof_sr_content : sr7by1; -- holds contents of start of frame sr
signal rdy_sr_content : sr7by1;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
begin -- arch1
----------------------------------------------------------------------------
--Process data_sr_p
--A six stage shift register to hold six bytes of incoming data.
--Clock enable signal enable_data_sr allows destination address to be stored
--in shift register while the source address is being transmitted.
----------------------------------------------------------------------------
data_sr_p : process(rx_ll_clock)
begin
if rising_edge(rx_ll_clock) then
if enable_data_sr = '1' and rx_enable = '1' then
data_sr_content <= rx_ll_data_in & data_sr_content (0 to 4);
end if;
end if;
end process; -- data_sr_p
data_sr5 <= data_sr_content(5);
----------------------------------------------------------------------------
--Process data_out_mux_p
--Selects data_out from the data shift register or from data_in, allowing
--destination address to be bypassed
----------------------------------------------------------------------------
data_out_mux_p : process(rx_ll_data_in, data_sr5, sel_delay_path)
begin
if sel_delay_path = '1' then
mux_out <= rx_ll_data_in;
else
mux_out <= data_sr5;
end if;
end process; -- data_out_mux_p
----------------------------------------------------------------------------
--Process data_out_reg_p
--Registers data output from output mux
----------------------------------------------------------------------------
data_out_reg_p : process(rx_ll_clock)
begin
if rising_edge(rx_ll_clock) then
if rx_enable = '1' then
rx_ll_data_out <= mux_out after dly;
end if;
end if;
end process; -- data_out_reg_p
rx_enable <= not(rx_ll_dst_rdy_in_n);
----------------------------------------------------------------------------
--Process data_sof_sr_p
--Delays start of frame by 7 clock cycles
----------------------------------------------------------------------------
data_sof_sr_p : process(rx_ll_clock)
begin
if rising_edge(rx_ll_clock) then
if rx_enable = '1' then
sof_sr_content <= not rx_ll_sof_in_n & sof_sr_content(0 to 5);
end if;
end if;
end process; -- data_sof_sr_p
rx_ll_sof_out_n <= not sof_sr_content(6) after dly;
----------------------------------------------------------------------------
--Process data_eof_sr_p
--Delays end of frame by 7 clock cycles
----------------------------------------------------------------------------
data_eof_sr_p : process(rx_ll_clock)
begin
if rising_edge(rx_ll_clock) then
if rx_enable = '1' then
eof_sr_content <= not rx_ll_eof_in_n & eof_sr_content(0 to 5);
end if;
end if;
end process; -- data_eof_sr_p
rx_ll_eof_out_n <= not eof_sr_content(6) after dly;
----------------------------------------------------------------------------
--Process src_rdy_sr_p
--Delays source ready by 7 clock cycles
----------------------------------------------------------------------------
src_rdy_sr_p : process(rx_ll_clock)
begin
if rising_edge(rx_ll_clock) then
if rx_enable = '1' then
rdy_sr_content <= not rx_ll_src_rdy_in_n & rdy_sr_content(0 to 5);
end if;
end if;
end process; -- src_rdy_sr_p
rx_ll_src_rdy_out_n <= not rdy_sr_content(6) after dly;
----------------------------------------------------------------------------
--Process control_fsm_sync_p
--Synchronous update of next state of control_fsm
----------------------------------------------------------------------------
control_fsm_sync_p : process(rx_ll_clock)
begin
if rising_edge(rx_ll_clock) then
if rx_ll_reset = '1' then
control_fsm_state <= wait_sf;
else
if rx_enable = '1' then
case control_fsm_state is
when wait_sf =>
if sof_sr_content(4) = '1' then
control_fsm_state <= bypass_sa1;
else
control_fsm_state <= wait_sf;
end if;
when bypass_sa1 =>
if not(sof_sr_content(4) = '0' and eof_sr_content(4) = '1') then
control_fsm_state <= bypass_sa2;
else
control_fsm_state <= wait_sf;
end if;
when bypass_sa2 =>
if not(sof_sr_content(4) = '0' and eof_sr_content(4) = '1') then
control_fsm_state <= bypass_sa3;
else
control_fsm_state <= wait_sf;
end if;
when bypass_sa3 =>
if not(sof_sr_content(4) = '0' and eof_sr_content(4) = '1') then
control_fsm_state <= bypass_sa4;
else
control_fsm_state <= wait_sf;
end if;
when bypass_sa4 =>
if not(sof_sr_content(4) = '0' and eof_sr_content(4) = '1') then
control_fsm_state <= bypass_sa5;
else
control_fsm_state <= wait_sf;
end if;
when bypass_sa5 =>
if not(sof_sr_content(4) = '0' and eof_sr_content(4) = '1') then
control_fsm_state <= bypass_sa6;
else
control_fsm_state <= wait_sf;
end if;
when bypass_sa6 =>
if not(sof_sr_content(4) = '0' and eof_sr_content(4) = '1') then
control_fsm_state <= pass_rof;
else
control_fsm_state <= wait_sf;
end if;
when pass_rof =>
if not(sof_sr_content(4) = '0' and eof_sr_content(4) = '1') then
control_fsm_state <= pass_rof;
else
control_fsm_state <= wait_sf;
end if;
when others =>
control_fsm_state <= wait_sf;
end case;
end if;
end if;
end if;
end process; -- control_fsm_sync_p
----------------------------------------------------------------------------
--Process control_fsm_comb_p
--Determines control signals from control_fsm state
----------------------------------------------------------------------------
control_fsm_comb_p : process(control_fsm_state)
begin
case control_fsm_state is
when wait_sf =>
sel_delay_path <= '0'; -- output data from data shift register
enable_data_sr <= '1'; -- enable data to be loaded into shift register
when bypass_sa1 =>
sel_delay_path <= '1'; -- output data directly from input
enable_data_sr <= '0'; -- hold current data in shift register
when bypass_sa2 =>
sel_delay_path <= '1'; -- output data directly from input
enable_data_sr <= '0'; -- hold current data in shift register
when bypass_sa3 =>
sel_delay_path <= '1'; -- output data directly from input
enable_data_sr <= '0'; -- hold current data in shift register
when bypass_sa4 =>
sel_delay_path <= '1'; -- output data directly from input
enable_data_sr <= '0'; -- hold current data in shift register
when bypass_sa5 =>
sel_delay_path <= '1'; -- output data directly from input
enable_data_sr <= '0'; -- hold current data in shift register
when bypass_sa6 =>
sel_delay_path <= '1'; -- output data directly from input
enable_data_sr <= '0'; -- hold current data in shift register
when pass_rof =>
sel_delay_path <= '0'; -- output data from data shift register
enable_data_sr <= '1'; -- enable data to be loaded into shift register
when others =>
sel_delay_path <= '0';
enable_data_sr <= '1';
end case;
end process; -- control_fsm_comb_p
end arch1; --arch1
|
gpl-3.0
|
fccfff0741b0e32016a540a2d550c02a
| 0.51551 | 4.264903 | false | false | false | false |
luebbers/reconos
|
core/pcores/reconos_v2_01_a/hdl/vhdl/reconos_pkg.vhd
| 1 | 81,782 |
--
-- \file reconos_pkg.vhd
--
-- ReconOS package
--
-- Contains type definitions and functions for hardware OS services in VHDL
--
-- \author Enno Luebbers <[email protected]>
-- \date 27.06.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
--
-- Major changes
-- 27.06.2006 Enno Luebbers File created
-- 30.06.2006 Enno Luebbers added shared memory data types
-- 17.07.2006 Enno Luebbers merged osif and shm interfaces
-- 18.07.2006 Enno Luebbers implemented shared memory reads
-- 03.08.2006 Enno Luebbers Added commands for shared memory
-- initialization (PLB busmaster)
-- 04.07.2007 Enno Luebbers Added support for multi-cycle
-- commands, tidied code (command_decoder)
-- 10.07.2007 Enno Luebbers Added support for auxiliary thread "data"
-- 11.07.2007 Enno Luebbers Added support for mutexes
-- xx.07.2007 Enno Luebbers Added support for condition variables
-- xx.09.2007 Enno Luebbers added support for mailboxes
-- 04.10.2007 Enno Luebbers added support for local mailboxes
-- 09.02.2008 Enno Luebbers implemented thread_exit() call
-- 19.04.2008 Enno Luebbers added handshaking between command_decoder
-- and HW thread
-- 04.08.2008 Andreas Agne implemented mq send and receive functions
-- 22.08.2010 Andreas Agne added MMU related command codes
--*************************************************************************/
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package reconos_pkg is
--######################## CONSTANTS #########################
-- width of shared memory ports FIXME: this should be configurable per task
--constant C_SHARED_MEM_DWIDTH : natural := 32;
--constant C_SHARED_MEM_AWIDTH : natural := 26; -- maximum of 64MBytes shared memory
-- width of OSIF commands, data registers
constant C_OSIF_CMD_WIDTH : natural := 8;
constant C_OSIF_DATA_WIDTH : natural := 32;
constant C_OSIF_STATE_ENC_WIDTH : natural := 8; -- max 256 state
constant C_OSIF_DATA_BURSTLEN_WIDTH : natural := 10;
-- number of bits in communication records
constant C_OSIF_OS2TASK_REC_WIDTH : natural := C_OSIF_CMD_WIDTH + C_OSIF_DATA_WIDTH + 5 + 2;
constant C_OSIF_TASK2OS_REC_WIDTH : natural := C_OSIF_CMD_WIDTH + C_OSIF_DATA_WIDTH + C_OSIF_STATE_ENC_WIDTH + 3;
-- OSIF flags
constant C_OSIF_FLAGS_WIDTH : natural := 8; -- flags (such as ready to yield)
constant C_OSIF_FLAGS_YIELD_BITPOS : natural := 0;
-- FIXME: DEPRECATED -- this is not necessarily true and is subject to change
-- upon further extensions
-- a OSIF shared memory command is structured as follows:
-- bit 0: request is blocking (0)
constant C_OSIF_CMD_BLOCKING_BITPOS : natural := 0;
-- bit 1: request is handled by hardware (1)
constant C_OSIF_CMD_REQUEST_HANDLED_BY_HW_BITPOS : natural := 1;
-- bit 2: request is a memory request (1)
constant C_OSIF_CMD_MEMORY_REQUEST_BITPOS : natural := 2;
-- bit 3: request is a read request
constant C_OSIF_CMD_MEMORY_DIRECTION_BITPOS : natural := 3;
-- bit 4: request is a burst request
constant C_OSIF_CMD_BURST_BITPOS : natural := 4;
-- bits 6-31: address of memory request
-- constant C_OSIF_CMD_SHM_ADDRESS_BITPOS : natural := C_OSIF_CMD_WIDTH-C_SHARED_MEM_AWIDTH;
-- FIXME: the lower two bits of the address should always read '0'. (in case of burst start addresses, the three lower bits)
-- maximum steps a multicycle command can take
constant C_MAX_MULTICYCLE_STEPS : natural := 4;
constant C_OSIF_STEP_ENC_WIDTH : natural := 2; -- max 4 steps
constant C_STEP_RESUME : natural := C_MAX_MULTICYCLE_STEPS-1; -- step in which to resume multi-cycle commands
-- common constants
constant C_RECONOS_FAILURE : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"00000000";
constant C_RECONOS_SUCCESS : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"00000001";
---------------------------------------------------
-- task2os commands
---------------------------------------------------
----- non-blocking commands (MSB cleared) -----
-- post semaphore
constant OSIF_CMD_SEM_POST : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"00";
-- write to shared memory
-- constant OSIF_CMD_SHM_WRITE_PREFIX : std_logic_vector(0 to C_OSIF_CMD_SHM_ADDRESS_BITPOS-1) := X"6" & "00";
-- read from shared memory
-- constant OSIF_CMD_SHM_READ_PREFIX : std_logic_vector(0 to C_OSIF_CMD_SHM_ADDRESS_BITPOS-1) := X"7" & "00";
-- initiate write burst to shared memory
-- constant OSIF_CMD_SHM_WRITE_BURST_PREFIX : std_logic_vector(0 to C_OSIF_CMD_SHM_ADDRESS_BITPOS-1) := X"6" & "10";
-- initiate read burst from shared memory
-- constant OSIF_CMD_SHM_READ_BURST_PREFIX : std_logic_vector(0 to C_OSIF_CMD_SHM_ADDRESS_BITPOS-1) := X"7" & "10";
-- read word from memory
constant OSIF_CMD_READ : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"48";
-- write word to memory
constant OSIF_CMD_WRITE : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"49";
-- initiate read burst from shared memory
constant OSIF_CMD_READ_BURST : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"4A";
-- initiate write burst to shared memory
constant OSIF_CMD_WRITE_BURST : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"4B";
-- read thread data (from thread initialization)
constant OSIF_CMD_GET_INIT_DATA : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"40";
-- mutex unlock
constant OSIF_CMD_MUTEX_UNLOCK : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"02";
-- mutex release
constant OSIF_CMD_MUTEX_RELEASE : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"03";
-- signal condition variable
constant OSIF_CMD_COND_SIGNAL : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"04";
-- broadcast condition variable
constant OSIF_CMD_COND_BROADCAST : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"05";
-- thread resume
constant OSIF_CMD_THREAD_RESUME : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"10";
----- blocking commands (MSB set) -----
-- wait on semaphore
constant OSIF_CMD_SEM_WAIT : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"81";
-- mutex lock
constant OSIF_CMD_MUTEX_LOCK : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"82";
-- mutex trylock (blocking because hardware has to wait for the return value)
constant OSIF_CMD_MUTEX_TRYLOCK : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"83";
-- wait on condition variable
constant OSIF_CMD_COND_WAIT : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"84";
-- mbox get
constant OSIF_CMD_MBOX_GET : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"85";
-- mbox tryget (blocking because hardware has to wait for the return value)
constant OSIF_CMD_MBOX_TRYGET : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"86";
-- mbox put
constant OSIF_CMD_MBOX_PUT : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"87";
-- mbox tryput (blocking because hardware has to wait for the return value)
constant OSIF_CMD_MBOX_TRYPUT : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"88";
-- mq send
constant OSIF_CMD_MQ_SEND : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"8A";
-- mq receive
constant OSIF_CMD_MQ_RECEIVE : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"8C";
-- thread_delay
constant OSIF_CMD_THREAD_DELAY : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"8D";
-- thread exit (blocking to prevent further activity, never returns)
constant OSIF_CMD_THREAD_EXIT : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"F0";
-- thread yield (NOTE: only _potentially_ blocking)
constant OSIF_CMD_THREAD_YIELD : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"F1";
-- FIXME: DEPRECATED!
-- local mbox tryget
constant OSIF_CMD_MBOX_TRYGET_LOCAL : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"41";
-- local mbox tryput
constant OSIF_CMD_MBOX_TRYPUT_LOCAL : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"42";
-- mmu exceptions
constant OSIF_CMD_MMU_FAULT : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"4C";
constant OSIF_CMD_MMU_ACCESS_VIOLATION : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"4D";
---------------------------------------------------
-- os2task commands
---------------------------------------------------
-- end blocking request
constant OSIF_CMD_UNBLOCK : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"00";
-- set thread data (on initialization)
constant OSIF_CMD_SET_INIT_DATA : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"01";
-- reset thread (and block it)
constant OSIF_CMD_RESET : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"02";
-- enable/disable busmacros
constant OSIF_CMD_BUSMACRO : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"03";
constant OSIF_DATA_BUSMACRO_DISABLE : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"00000000";
-- set local FIFO handles
constant OSIF_CMD_SET_FIFO_READ_HANDLE : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"04";
constant OSIF_CMD_SET_FIFO_WRITE_HANDLE : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"05";
-- control yield/resume state
constant OSIF_CMD_SET_RESUME_STATE : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"06";
constant OSIF_CMD_CLEAR_RESUME_STATE : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"07";
constant OSIF_CMD_REQUEST_YIELD : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"08";
constant OSIF_CMD_CLEAR_YIELD : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"09";
-- mmu initialization and exception handling
constant OSIF_CMD_MMU_SETPGD : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"0A";
constant OSIF_CMD_MMU_REPEAT : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"0B";
constant OSIF_CMD_MMU_RESET : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := X"0C";
--######################## TYPES #########################
---------------------------------------------------
-- communication records
---------------------------------------------------
-- Note: These signals should be set and read synchronously.
-- Use the reconos_* procedures and functions.
-- Note: If you change the OSIF or SHM interface definitions,
-- remember to adjust the C_*_REC_WIDTH constants above
-- OS to task communication
type osif_os2task_t is record
command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1); -- command identifier
data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- attached data
busy : std_logic; -- OS interface busy
blocking : std_logic; -- executing blocking OS call
ack : std_logic; -- acknowledge (for asynchronous communication)
req_yield: std_logic;
valid : std_logic; -- command valid (new command)
step : natural range 0 to C_MAX_MULTICYCLE_STEPS-1; -- for multi-cycle commands
end record;
-- task to OS communication
type osif_task2os_t is record
command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1); -- command identifier
data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- attached data
request : std_logic; -- request indicator (high for 1 cycle)
yield : std_logic; -- yield indicator (thread can be removed)
saved_state_enc : std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1); -- saved state when yielding
error : std_logic; -- error indicator
end record;
-------------------------
-- standard state encoding
subtype reconos_state_enc_t is std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1);
subtype reconos_step_enc_t is std_logic_vector(0 to C_OSIF_STEP_ENC_WIDTH-1);
--######################## FUNCTIONS & PROCEDURES #########################
function to_std_logic_vector (osif_os2task : osif_os2task_t) return std_logic_vector;
function to_std_logic_vector (osif_task2os : osif_task2os_t) return std_logic_vector;
function to_osif_os2task_t (vector : std_logic_vector) return osif_os2task_t;
function to_osif_task2os_t (vector : std_logic_vector) return osif_task2os_t;
function reconos_ready (osif_os2task : osif_os2task_t) return boolean;
procedure reconos_reset (signal osif_task2os : out osif_task2os_t;
osif_os2task : osif_os2task_t);
procedure reconos_reset_with_signature (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
signature : in std_logic_vector(0 to 31) );
procedure reconos_begin (signal osif_task2os : out osif_task2os_t;
osif_os2task : osif_os2task_t);
function reconos_check_yield (osif_os2task : osif_os2task_t) return boolean;
procedure reconos_sem_post (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_sem_wait (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_write (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_read (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_read_s (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_write_burst (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_read_burst (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_write_burst_l (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
burst_length : in natural range 2 to 512);
procedure reconos_read_burst_l (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
burst_length : in natural range 2 to 512);
procedure reconos_get_init_data (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_get_init_data_s (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mutex_lock(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mutex_trylock(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mutex_unlock(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mutex_release(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_cond_wait(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_cond_signal(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_cond_broadcast(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_get(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_get_s(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_tryget(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_tryget_s(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_put(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mq_send(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
offset : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
length : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mq_receive(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
offset : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
length : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_tryput(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
--------- FIXME: local mbox operations only for testing
--------- they should really be handled by the 'regular' mailbox procedures
procedure reconos_mbox_tryget_local(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_tryget_local_s(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_mbox_tryput_local(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_thread_exit(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
retval : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
procedure reconos_flag_yield(signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
saved_state_enc : in reconos_state_enc_t);
procedure reconos_thread_yield(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
saved_state_enc : in reconos_state_enc_t);
procedure reconos_thread_resume(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
variable resume_state_enc : out reconos_state_enc_t);
procedure reconos_thread_delay(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
delay : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1));
--================ TOOL FUNCTIONS ==================
-- FIXME: this should be in seperate package
function reduce_or (input : std_logic_vector) return std_logic;
end reconos_pkg;
package body reconos_pkg is
---------------------------------------------------
-- to_std_logic_vector: converts a osif_os2task_t or
-- osif_task2os_t record
-- to a std_logic_vector
---------------------------------------------------
function to_std_logic_vector (osif_os2task : osif_os2task_t) return std_logic_vector is
begin
return osif_os2task.command & osif_os2task.data & osif_os2task.busy & osif_os2task.blocking & osif_os2task.ack & osif_os2task.req_yield & osif_os2task.valid & std_logic_vector(TO_UNSIGNED(osif_os2task.step, 2));
end;
function to_std_logic_vector (osif_task2os : osif_task2os_t) return std_logic_vector is
begin
return osif_task2os.command &
osif_task2os.data &
osif_task2os.request &
osif_task2os.yield &
osif_task2os.saved_state_enc &
osif_task2os.error;
end;
---------------------------------------------------
-- to_osif_(os2(task)2os)_t: converts a std_logic_vector
-- to the appropriate record
---------------------------------------------------
function to_osif_os2task_t (vector : std_logic_vector) return osif_os2task_t is
variable rec : osif_os2task_t;
variable i, j : natural;
begin
i := vector'low; j := i + C_OSIF_CMD_WIDTH;
rec.command := vector(i to j-1);
i := j; j := i + C_OSIF_DATA_WIDTH;
rec.data := vector(i to j-1);
i := j; j := i + 1;
rec.busy := vector(i);
i := j; j := i + 1;
rec.blocking := vector(i);
i := j; j := i + 1;
rec.ack := vector(i);
i := j; j := i + 1;
rec.req_yield := vector(i);
i := j; j := i + 1;
rec.valid := vector(i);
i := j; j := i + 2;
rec.step := TO_INTEGER(unsigned(vector(i to j-1))); -- 2 bits for step
return rec;
end;
function to_osif_task2os_t (vector : std_logic_vector) return osif_task2os_t is
variable rec : osif_task2os_t;
variable i, j : natural;
begin
i := vector'low; j := i + C_OSIF_CMD_WIDTH;
rec.command := vector(i to j-1);
i := j; j := i + C_OSIF_DATA_WIDTH;
rec.data := vector(i to j-1);
i := j; j := i + 1;
rec.request := vector(i);
i := j; j := i + 1;
rec.yield := vector(i);
i := j; j := i + C_OSIF_STATE_ENC_WIDTH;
rec.saved_state_enc := vector(i to j-1);
i := j; j := i + 1;
rec.error := vector(i);
return rec;
end;
---------------------------------------------------
-- reconos_ready: check whether OSIF is ready
--
-- osif_os2task: OSIF os2task channel
--
-- returns false if OSIF is busy or there is
-- a blocking OS call running, true otherwise
---------------------------------------------------
function reconos_ready (osif_os2task : osif_os2task_t) return boolean is
begin
if osif_os2task.blocking = '1' or osif_os2task.busy = '1' then
return false;
else
return true;
end if;
end;
---------------------------------------------------
-- reconos_reset_with_signature: reset task2os interface and set hwthread
-- signature.
--
-- should be used in the "if reset"-clause of
-- the osif communication process in a user task.
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
---------------------------------------------------
procedure reconos_reset_with_signature (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
signature : in std_logic_vector(0 to 31) ) is
begin
osif_task2os.command <= (others => '0');
osif_task2os.data <= signature;
osif_task2os.request <= '0';
osif_task2os.yield <= '0';
osif_task2os.saved_state_enc <= (others => '0');
osif_task2os.error <= '0';
end;
---------------------------------------------------
-- reconos_reset: reset task2os interface
--
-- should be used in the "if reset"-clause of
-- the osif communication process in a user task.
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
---------------------------------------------------
procedure reconos_reset (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t) is
begin
reconos_reset_with_signature(osif_task2os, osif_os2task, X"00000000");
end;
---------------------------------------------------
-- reconos_begin: every-cycle signal assignments
--
-- contains assignments that need to be run on
-- every clock cycle
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
---------------------------------------------------
procedure reconos_begin (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t) is
begin
osif_task2os.request <= '0';
osif_task2os.yield <= '0';
end;
---------------------------------------------------
-- reconos_check_yield: check whether OS requests yield
--
-- osif_os2task: OSIF os2task channel
--
-- returns true if OS has set the req_yield flag, false otherwise
---------------------------------------------------
function reconos_check_yield (osif_os2task : osif_os2task_t) return boolean is
begin
if osif_os2task.req_yield = '1' then
return true;
else
return false;
end if;
end;
---------------------------------------------------
-- reconos_flag_yield: signal possible yield
--
-- this signals the OS that this thread has no
-- state and could be removed
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- saved_state_enc : encoded state to resume in
---------------------------------------------------
procedure reconos_flag_yield (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
saved_state_enc : in reconos_state_enc_t ) is
begin
osif_task2os.yield <= '1';
osif_task2os.saved_state_enc <= saved_state_enc;
end;
---------------------------------------------------
-- reconos_sem_post: post a counting semaphore
--
-- equivalent to eCos' cyg_semaphore_post()
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : ReconOS handle identifier
---------------------------------------------------
procedure reconos_sem_post (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to 31)) is
begin
osif_task2os.command <= OSIF_CMD_SEM_POST;
osif_task2os.data <= handle;
osif_task2os.request <= '1';
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end;
---------------------------------------------------
-- reconos_sem_wait: wait for a counting semaphore
--
-- equivalent to eCos' cyg_semaphore_wait()
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : ReconOS handle identifier
---------------------------------------------------
procedure reconos_sem_wait (signal osif_task2os : out osif_task2os_t;
osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to 31)) is
begin
osif_task2os.command <= OSIF_CMD_SEM_WAIT;
osif_task2os.data <= handle;
osif_task2os.request <= '1';
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end;
---------------------------------------------------
-- reconos_thread_delay: wait for a specified number of 'ticks'
--
-- equivalent to eCos' cyg_thread_delay()
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- delay : number of ticks to wait
---------------------------------------------------
procedure reconos_thread_delay (signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
delay : in std_logic_vector(0 to 31)) is
begin
osif_task2os.command <= OSIF_CMD_THREAD_DELAY;
osif_task2os.data <= delay;
osif_task2os.request <= '1';
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end;
--------------- multi-cycle functions --------------
---------------------------------------------------
-- reconos_write: write to system memory
---
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- address : system memory address
-- data : data to write
---------------------------------------------------
procedure reconos_write (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_WRITE;
osif_task2os.request <= '1';
completed := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= address;
when 1 => osif_task2os.data <= data;
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_write
---------------------------------------------------
-- reconos_read: read from system memory
---
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- address : system memory address
-- data : signal to read data into
---------------------------------------------------
procedure reconos_read (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_READ;
osif_task2os.request <= '1';
completed := false;
data := (others => '0');
case osif_os2task.step is
when 0 => osif_task2os.data <= address;
when 1 => data := osif_os2task.data;
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_read
---------------------------------------------------
-- reconos_read: read from system memory
---
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- address : system memory address
-- data : signal to read data into
---------------------------------------------------
procedure reconos_read_s (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
variable tmp : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable done : boolean;
begin
reconos_read(done, osif_task2os, osif_os2task, address, tmp);
data <= tmp;
completed := done;
end; -- reconos_read_s
---------------------------------------------------
-- reconos_write_burst: write a burst to system memory (16x64 Bit)
--
-- retained for compatibility reasons
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os : OSIF task2os channel
-- osif_os2task : OSIF os2task channel
-- my_address : local burst ram address (in bytes!)
-- target_address: system memory address
---------------------------------------------------
procedure reconos_write_burst (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
reconos_write_burst_l(completed,
osif_task2os,
osif_os2task,
my_address,
target_address,
16);
end; -- reconos_write_burst
---------------------------------------------------
-- reconos_read_burst: read a burst from system memory (16x64 Bit)
--
-- retained for compatibility reasons
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os : OSIF task2os channel
-- osif_os2task : OSIF os2task channel
-- my_address : local burst ram address (in bytes!)
-- target_address: system memory address
---------------------------------------------------
procedure reconos_read_burst (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
reconos_read_burst_l(completed,
osif_task2os,
osif_os2task,
my_address,
target_address,
16);
end; -- reconos_read_burst
---------------------------------------------------
-- reconos_write_burst_l: write a burst to system memory with specified burst length
---
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os : OSIF task2os channel
-- osif_os2task : OSIF os2task channel
-- my_address : local burst ram address (in bytes!)
-- target_address: system memory address
-- burst_length : length of the burst in 64bit transfers (=cycles)
---------------------------------------------------
procedure reconos_write_burst_l (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
burst_length : in natural range 2 to 512) is
begin
osif_task2os.command <= OSIF_CMD_WRITE_BURST;
osif_task2os.request <= '1';
completed := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= my_address;
when 1 => osif_task2os.data <= target_address;
when 2 => osif_task2os.data(C_OSIF_DATA_WIDTH-C_OSIF_DATA_BURSTLEN_WIDTH to C_OSIF_DATA_WIDTH-1) <= std_logic_vector(to_unsigned(burst_length, C_OSIF_DATA_BURSTLEN_WIDTH));
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_write_burst_l
---------------------------------------------------
-- reconos_read_burst_l: read a burst from system memory with specified length
---
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os : OSIF task2os channel
-- osif_os2task : OSIF os2task channel
-- my_address : local burst ram address (in bytes!)
-- target_address: system memory address
-- burst_length : length of the burst in 64bit transfers (=cycles)
---------------------------------------------------
procedure reconos_read_burst_l (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
my_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
target_address : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
burst_length : in natural range 2 to 512) is
begin
osif_task2os.command <= OSIF_CMD_READ_BURST;
osif_task2os.request <= '1';
completed := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= my_address;
when 1 => osif_task2os.data <= target_address;
when 2 => osif_task2os.data(C_OSIF_DATA_WIDTH-C_OSIF_DATA_BURSTLEN_WIDTH to C_OSIF_DATA_WIDTH-1) <= std_logic_vector(to_unsigned(burst_length, C_OSIF_DATA_BURSTLEN_WIDTH));
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_read_burst_l
---------------------------------------------------
-- reconos_mutex_lock: attain a lock on a mutex
--
-- If the mutex is already locked, wait (blocking) until its release
-- Returns '1' in "success" if mutex lock was successful, otherwise '0'
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully locked, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : mutex to lock
---------------------------------------------------
procedure reconos_mutex_lock(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MUTEX_LOCK;
osif_task2os.request <= '1';
completed := false;
success := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
when 1 =>
completed := true;
if osif_os2task.data = C_RECONOS_FAILURE then
success := false;
else
success := true;
end if;
when C_STEP_RESUME =>
-- wait step for resuming
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mutex_lock
---------------------------------------------------
-- reconos_mutex_trylock: try attaining a lock on a mutex
--
-- If the mutex is already locked, return immediately (do not wait)
-- Returns '1' in "success" if mutex lock was successful, otherwise '0'
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully locked, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : mutex to lock
---------------------------------------------------
-- this is implemented as a blocking call, to be able to receive a return value
procedure reconos_mutex_trylock(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MUTEX_TRYLOCK;
osif_task2os.request <= '1';
completed := false;
success := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
when 1 =>
completed := true;
if osif_os2task.data = C_RECONOS_FAILURE then
success := false;
else
success := true;
end if;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mutex_trylock
---------------------------------------------------
-- reconos_mutex_unlock: unlock a previously locked mutex
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : mutex to unlock
---------------------------------------------------
procedure reconos_mutex_unlock(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MUTEX_UNLOCK;
osif_task2os.request <= '1';
osif_task2os.data <= handle;
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end; -- reconos_mutex_unlock
---------------------------------------------------
-- reconos_mutex_release: release all threads waiting on this mutex
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : mutex to release
---------------------------------------------------
procedure reconos_mutex_release(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MUTEX_RELEASE;
osif_task2os.request <= '1';
osif_task2os.data <= handle;
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end; -- reconos_mutex_release
---------------------------------------------------
-- reconos_get_init_data: read thread init data
--
-- "thread init data" is a 32 bit value that is passed to
-- the thread creation function (i.e. reconos_hwthread_create()).
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- data : variable to read data into
---------------------------------------------------
procedure reconos_get_init_data (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_GET_INIT_DATA;
osif_task2os.request <= '1';
completed := false;
data := (others => '0');
case osif_os2task.step is
when 0 => null;
when 1 => data := osif_os2task.data;
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_get_init_data
---------------------------------------------------
-- reconos_get_init_data_s: read thread init data into signal
--
-- "thread init data" is a 32 bit value that is passed to
-- the thread creation function (i.e. reconos_hwthread_create()).
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- data : signal to read data into
---------------------------------------------------
procedure reconos_get_init_data_s (variable completed : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
variable tmp : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable done : boolean;
begin
reconos_get_init_data(done, osif_task2os, osif_os2task, tmp);
data <= tmp;
completed := done;
end; -- reconos_get_init_data
---------------------------------------------------
-- reconos_cond_wait: wait for condition change
--
-- This implicitly unlocks the mutex associated with the condition variable "handle".
-- waits blocking until someone "signals" the condition variable
-- Returns '1' in "success" if mutex lock was successful, otherwise '0'
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully locked, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to wait for
---------------------------------------------------
procedure reconos_cond_wait(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_COND_WAIT;
osif_task2os.request <= '1';
completed := false;
success := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
when 1 =>
completed := true;
if osif_os2task.data = C_RECONOS_FAILURE then
success := false;
else
success := true;
end if;
when C_STEP_RESUME =>
-- wait step for resuming
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_cond_wait
---------------------------------------------------
-- reconos_cond_signal: wake next thread waiting on condition variable
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
---------------------------------------------------
procedure reconos_cond_signal(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_COND_SIGNAL;
osif_task2os.request <= '1';
osif_task2os.data <= handle;
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end; -- reconos_cond_signal
---------------------------------------------------
-- reconos_cond_signal: wake all threads waiting on condition variable
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
---------------------------------------------------
procedure reconos_cond_broadcast(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_COND_BROADCAST;
osif_task2os.request <= '1';
osif_task2os.data <= handle;
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end; -- reconos_cond_broadcast
---------------------------------------------------
-- reconos_mbox_get: retrieve message from mailbox
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Blocks if mailbox is empty.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : variable to read message into
---------------------------------------------------
procedure reconos_mbox_get(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MBOX_GET;
osif_task2os.request <= '1';
completed := false;
success := false;
data := (others => '0');
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
when 1 => null;
when 2 =>
completed := true;
-- if osif_os2task.data = C_RECONOS_FAILURE then
if osif_os2task.valid = '0' then
success := false;
else
success := true;
data := osif_os2task.data;
end if;
when C_STEP_RESUME =>
-- wait step for resuming
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mbox_get
---------------------------------------------------
-- reconos_mbox_get_s: retrieve message from mailbox into a signal
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Blocks if mailbox is empty.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : signal to read message into
---------------------------------------------------
procedure reconos_mbox_get_s(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
variable tmp : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable done : boolean;
variable success_tmp : boolean;
begin
reconos_mbox_get(done, success_tmp, osif_task2os, osif_os2task, handle, tmp);
data <= tmp;
completed := done;
success := success_tmp;
end; -- reconos_mbox_get_s
---------------------------------------------------
-- reconos_mbox_tryget: retrieve message from mailbox, if available
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Returns immediately (non-blocking). If mailbox is empty,
-- success is '0'.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : variable to read message into
---------------------------------------------------
procedure reconos_mbox_tryget(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MBOX_TRYGET;
osif_task2os.request <= '1';
completed := false;
success := false;
data := (others => '0');
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
when 1 => null; -- wait state for hardware FIFO access
when 2 =>
completed := true;
if osif_os2task.valid = '0' then
success := false;
else
success := true;
data := osif_os2task.data;
end if;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mbox_tryget
---------------------------------------------------
-- reconos_mbox_tryget_s: retrieve message from mailbox, if available,
-- into a signal
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Returns immediately (non-blocking). If mailbox is empty,
-- success is '0'.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : signal to read message into
---------------------------------------------------
procedure reconos_mbox_tryget_s(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
variable tmp : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable done : boolean;
variable success_tmp : boolean;
begin
reconos_mbox_tryget(done, success_tmp, osif_task2os, osif_os2task, handle, tmp);
data <= tmp;
completed := done;
success := success_tmp;
end; -- reconos_mbox_tryget_s
---------------------------------------------------
-- reconos_mbox_put: send message to a mailbox
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Blocks, if mailbox full.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : variable to read message into
---------------------------------------------------
procedure reconos_mbox_put(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MBOX_PUT;
osif_task2os.request <= '1';
completed := false;
success := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
when 1 => osif_task2os.data <= data;
when 2 =>
completed := true;
-- if osif_os2task.data = C_RECONOS_FAILURE then
if osif_os2task.valid = '0' then
success := false;
else
success := true;
end if;
when C_STEP_RESUME =>
-- wait step for resuming
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mbox_put
---------------------------------------------------
-- reconos_mq_receive: receive message from a message queue
--
-- The message is stored in local bram
-- Blocks, if mailbox is empty.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : handle of the mq
-- offset : byte offset of the message in local ram
-- length : length of the message in bytes
---------------------------------------------------
procedure reconos_mq_receive(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
offset : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
length : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MQ_RECEIVE;
osif_task2os.request <= '1';
completed := false;
success := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
-- hack: save one cycle by packing offset and length in one word; assume C_OSIF_DATA_WIDTH = 32
when 1 => osif_task2os.data <= offset(16 to 31) & X"0000";
when 2 =>
completed := true;
length := osif_os2task.data;
if osif_os2task.valid = '0' then
success := false;
else
success := true;
end if;
when C_STEP_RESUME =>
-- wait step for resuming
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mq_receive
---------------------------------------------------
-- reconos_mq_send: send message to a message queue
--
-- The message is stored in local bram
-- Blocks, if mailbox is full.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- offset : byte offset of the message in local ram
-- length : length of the message in bytes
---------------------------------------------------
procedure reconos_mq_send(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
offset : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
length : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MQ_SEND;
osif_task2os.request <= '1';
completed := false;
success := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
-- hack: save one cycle by packing offset and length in one word; assume C_OSIF_DATA_WIDTH = 32
when 1 => osif_task2os.data <= offset(16 to 31) & length(16 to 31);
when 2 =>
completed := true;
if osif_os2task.valid = '0' then
success := false;
else
success := true;
end if;
when C_STEP_RESUME =>
-- wait step for resuming
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mq_send
---------------------------------------------------
-- reconos_mbox_tryput: send message to a mailbox, if possible
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Returns immediately (non-blocking). If mailbox is full,
-- success is '0'.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : variable to read message into
---------------------------------------------------
procedure reconos_mbox_tryput(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MBOX_TRYPUT;
osif_task2os.request <= '1';
completed := false;
success := false;
case osif_os2task.step is
when 0 => osif_task2os.data <= handle;
when 1 => osif_task2os.data <= data;
when 2 =>
completed := true;
if osif_os2task.valid = '0' then
success := false;
else
success := true;
end if;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mbox_tryput
---------------------------------------------------
-- reconos_mbox_tryget_local: retrieve message from local mailbox, if available
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Returns immediately (non-blocking). If mailbox is empty,
-- success is '0'.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : variable to read message into
---------------------------------------------------
procedure reconos_mbox_tryget_local(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MBOX_TRYGET_LOCAL;
osif_task2os.request <= '1';
success := false;
data := X"AFFEDEAD";
completed := false;
case osif_os2task.step is
when 0 => null;
when 1 => null;
when 2 =>
if osif_os2task.valid = '1' then
success := true;
else
success := false;
end if;
data := osif_os2task.data;
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mbox_tryget_local
---------------------------------------------------
-- reconos_mbox_tryget_local_s: retrieve message from mailbox, if available,
-- into a signal
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Returns immediately (non-blocking). If mailbox is empty,
-- success is '0'.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : signal to read message into
---------------------------------------------------
procedure reconos_mbox_tryget_local_s(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal data : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
variable tmp : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
variable success_tmp : boolean;
variable done : boolean;
begin
reconos_mbox_tryget_local(done, success_tmp, osif_task2os, osif_os2task, handle, tmp);
data <= tmp;
completed := done;
success := success_tmp;
end; -- reconos_mbox_tryget_local_s
---------------------------------------------------
-- reconos_mbox_tryput_local: send message to a mailbox, if possible
--
-- A message consists of 32 bits which may point to
-- a memory location.
-- Returns immediately (non-blocking). If mailbox is full,
-- success is '0'.
--
-- !!! multi-cycle command, see MultiCycleCommands in the ReconOS Wiki !!!
--
-- completed : goes '1' when last cycle completed
-- success : '1' if successfully retrieved, else '0'
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- handle : condition variable to signal on
-- data : variable to read message into
---------------------------------------------------
procedure reconos_mbox_tryput_local(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
handle : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
data : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_MBOX_TRYPUT_LOCAL;
osif_task2os.data <= data;
osif_task2os.request <= '1';
success := false;
completed := false;
case osif_os2task.step is
when 0 =>
when 1 =>
if osif_os2task.valid = '1' then
success := true;
else
success := false;
end if;
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end; -- reconos_mbox_tryput_local
---------------------------------------------------
-- reconos_thread_exit: terminate a hardware thread
--
-- This call blocks the hardware thread and causes
-- the corresponding delegate thread to terminate.
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- retval : return value
---------------------------------------------------
procedure reconos_thread_exit(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
retval : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)) is
begin
osif_task2os.command <= OSIF_CMD_THREAD_EXIT;
osif_task2os.data <= retval;
osif_task2os.request <= '1';
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end;
---------------------------------------------------
-- reconos_thread_yield: tell the operating system
-- that the current thread has
-- no internal state and could be
-- interrupted and removed
--
-- If there are no HW threads waiting to execute,
-- this is essentially a NOOP, and will not cause
-- an interrupt. Therefore, this call is safe to
-- be invoked every time the thread has no internal
-- state, since it incurs very little overhead.
-- This implies a call to reconos_flag_yield().
--
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- saved_state_enc: binary encoded value of OSIF
-- sync FSM state (where to resume)
---------------------------------------------------
procedure reconos_thread_yield(signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
saved_state_enc : in reconos_state_enc_t) is
begin
osif_task2os.command <= OSIF_CMD_THREAD_YIELD;
osif_task2os.data <= (others => '0');
osif_task2os.request <= '1';
reconos_flag_yield( osif_task2os, osif_os2task, saved_state_enc );
if osif_os2task.step /= 0 then
osif_task2os.error <= '1';
end if;
end;
---------------------------------------------------
-- reconos_thread_resume: ask the operating system
-- whether this thread has just been resumed
--
-- completed : goes '1' when last cycle completed
-- success : true, if thread was resumed
-- false, if it was newly created
-- osif_task2os: OSIF task2os channel
-- osif_os2task: OSIF os2task channel
-- resume_state_enc: binary encoded value of OSIF
-- sync FSM state (where to resume)
---------------------------------------------------
procedure reconos_thread_resume(variable completed : out boolean;
variable success : out boolean;
signal osif_task2os : out osif_task2os_t;
signal osif_os2task : in osif_os2task_t;
variable resume_state_enc : out reconos_state_enc_t) is
begin
osif_task2os.command <= OSIF_CMD_THREAD_RESUME;
osif_task2os.data <= (others => '0');
osif_task2os.request <= '1';
success := false;
completed := false;
resume_state_enc := (others => '0');
case osif_os2task.step is
when 0 =>
when 1 =>
if osif_os2task.valid = '1' then
success := true;
resume_state_enc := osif_os2task.data(0 to C_OSIF_STATE_ENC_WIDTH-1);
else
success := false;
resume_state_enc := (others => '0');
end if;
completed := true;
when others => osif_task2os.error <= '1'; -- this shouldn't happen
end case;
end;
---------------------------------------------------
-- reduce_or: or all input signals together
--
-- input: vector of signals to reduce
-- len : length of input vector
--
-- Returns result of OR operation
---------------------------------------------------
function reduce_or (input : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in input'high to input'low loop
result := result or input(i);
end loop;
return result;
end;
end reconos_pkg;
|
gpl-3.0
|
c67af382a0554ca7c68439455372002f
| 0.525189 | 4.06734 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/new/Ram.vhd
| 1 | 4,366 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.math_real.all;
-- todo: optimize
entity Ram is
Port
(
clk : in std_logic;
re : in std_logic_vector (1 downto 0);
we : in std_logic_vector (1 downto 0);
addr : in integer range 0 to 16#1FFFF#;
dat_r : out std_logic_vector (15 downto 0);
dat_w : in std_logic_vector (15 downto 0)
);
end Ram;
architecture Behavioral of Ram is
component Mem is
port
(
clka : in std_logic;
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(16 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0)
);
end component;
signal ram_en : std_logic := '0';
signal ram_we : std_logic := '0';
signal ram_addr : std_logic_vector(16 downto 0) := (others => '0');
signal ram_dat_in : std_logic_vector(7 downto 0) := (others => '0');
signal ram_dat_out : std_logic_vector(7 downto 0) := (others => '0');
begin
mem0: Mem
port map (
clka => clk,
ena => ram_en,
wea(0) => ram_we,
addra => ram_addr,
dina => ram_dat_in,
douta => ram_dat_out
);
--process (clk)
-- type state_type is (S0, S1, S2, S3);
-- variable state : state_type := S0;-- The current/next state
-- variable tmp : std_logic_vector(15 downto 0) := (others => '0');
--begin
-- if rising_edge(clk) then
-- ram_en <= '1';
-- ram_we <= '0';
-- case state is
-- when S0 =>
-- state := S1;
-- when S1 =>
-- ram_addr <= conv_std_logic_vector(addr, 17);
-- state := S2;
-- when S2 =>
-- ram_addr <= conv_std_logic_vector(addr + 1, 17);
-- -- Write first byte if required
-- if we(1) = '1' then
-- ram_we <= '1';
-- ram_dat_in <= dat_w(15 downto 8);
-- end if;
-- -- Read fist byte if required
-- if re(1) = '1' then
-- tmp(15 downto 8) := ram_dat_out;
-- else
-- tmp(15 downto 8) := (others => 'U');
-- end if;
-- state := S3;
-- when S3 =>
-- -- Write second byte if required
-- if we(0) = '1' then
-- ram_we <= '1';
-- ram_dat_in <= dat_w(7 downto 0);
-- end if;
-- -- Read second byte if required
-- if re(0) = '1' then
-- tmp(7 downto 0) := ram_dat_out;
-- else
-- tmp(7 downto 0) := (others => 'U');
-- end if;
-- dat_r <= tmp;
-- state := S0;
-- end case;
-- end if;
--end process;
process (clk)
type state_type is (S0, S1, S2, S3, S4, S5);
variable state : state_type := S0;-- The current/next state
variable tmp : std_logic_vector(15 downto 0) := (others => '0');
begin
if rising_edge(clk) then
ram_en <= '1';
ram_we <= '0';
case state is
when S0 =>
state := S1;
when S1 =>
dat_r <= (others => 'U');
ram_addr <= conv_std_logic_vector(addr, 17);
state := S2;
when S2 =>
-- Write first byte if required
if we(1) = '1' then
ram_we <= '1';
ram_dat_in <= dat_w(15 downto 8);
end if;
state := S3;
when S3 =>
-- Read fist byte if required
if re(1) = '1' then
tmp(15 downto 8) := ram_dat_out;
else
tmp(15 downto 8) := (others => 'U');
end if;
state := S4;
ram_addr <= conv_std_logic_vector(addr + 1, 17);
when S4 =>
-- Write second byte if required
if we(0) = '1' then
ram_we <= '1';
ram_dat_in <= dat_w(7 downto 0);
end if;
state := S5;
when S5 =>
-- Read second byte if required
if re(0) = '1' then
tmp(7 downto 0) := ram_dat_out;
else
tmp(7 downto 0) := (others => 'U');
end if;
dat_r <= tmp;
state := S0;
end case;
end if;
end process;
end Behavioral;
|
mit
|
dc1d10c35cf7270639954260bb4c339b
| 0.45694 | 3.327744 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/IcapCTRL_v1_00_d/ise/icap/icapCTRL.vhd
| 1 | 16,763 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:05 07/20/2006
-- Design Name:
-- Module Name: icapCTRL - icapCTRL_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity icapCTRL is
generic (
C_FAMILY : string := "virtex5";
C_ICAP_DWIDTH : integer:= 32;
C_BURST_SIZE : natural := 16; -- Number of DWords
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := b"10_0000_0000"; --DCR_BaseAddr
C_DCR_HIGHADDR : std_logic_vector(9 downto 0) := b"00_0000_0011"; --DCR_HighAddr, not used
C_COUNT_ADDR : std_logic_vector(31 downto 0) := X"00000010"
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic_vector(1 downto 0);
M_rdAddr_o : out std_logic_vector(31 downto 0);
M_rdReq_o : out std_logic;
M_rdNum_o : out std_logic_vector(4 downto 0);
M_rdAccept_i : in std_logic;
M_rdData_i : in std_logic_vector(63 downto 0);
M_rdAck_i : in std_logic;
M_rdComp_i : in std_logic;
M_wrAddr_o : out std_logic_vector(31 downto 0);
M_wrReq_o : out std_logic;
M_wrNum_o : out std_logic_vector(4 downto 0);
M_wrAccept_i : in std_logic;
M_wrData_o : out std_logic_vector(63 downto 0);
M_wrRdy_i : in std_logic;
M_wrAck_i : in std_logic;
M_wrComp_i : in std_logic;
BUSY : out std_ulogic;
O : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
CE : out std_ulogic;
I : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
WRITE : out std_ulogic;
Fifo_empty_o : out std_logic;
Fifo_full_o : out std_logic;
--- Interrupt
done_int : out std_logic;
--- DCR signals
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
---
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
DCR_ABus_o : out std_logic_vector(9 downto 0);
DCR_Write_o : out std_logic;
DCR_Din_o : out std_logic_vector(31 downto 0)
);
end icapCTRL;
architecture icapCTRL_rtl of icapCTRL is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then
return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
component ICAP_VIRTEX2
port (
BUSY : out std_ulogic;
O : out std_logic_vector(7 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(7 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX4
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX5
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component icapFIFO
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end component;
-- component DCR_control
-- generic(
-- ICAP_DCR_ADDR_L : std_logic_vector(9 downto 0) := b"10_0000_0000";
-- ICAP_DCR_ADDR_H : std_logic_vector(9 downto 0) := b"10_0000_0011"
-- );
-- port(
-- dcr_addr : in std_logic_vector(9 downto 0);
-- dcr_mrd : in std_logic;
-- dcr_mwr : in std_logic;
-- dcr_din : in std_logic_vector(31 downto 0);
-- ---
-- dcr_ack : out std_logic;
-- dcr_dout : out std_logic_vector(31 downto 0);
-- ---
-- start_w : out std_logic;
-- start_r : out std_logic;
-- addr : out std_logic_vector(31 downto 0);
-- ---
-- clk : in std_logic
-- );
-- end component;
component dcr_if is
generic (
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := B"00_0000_0000";
C_ON_INIT : std_logic := '0');
port (
clk : in std_logic;
rst : in std_logic;
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
ctrl_reg : out std_logic_vector(31 downto 0));
end component;
type state_type is (IDLE, INIT, ACTIVE, BURSTING, WRITE_COUNT, DONE);
signal state : state_type;
--signal addr : std_logic_vector(14 downto 0);
--signal addr : std_logic_vector(13 downto 0);
signal addr : std_logic_vector(18-(log2(C_BURST_SIZE)) downto 0);
signal addr_tail : std_logic_vector(2+(log2(C_BURST_SIZE)) downto 0);
signal base_addr : std_logic_vector(31 downto 22);
signal base_lngth : std_logic_vector(15 downto 0);
signal icap_busy : std_logic;
signal icap_dout : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din_r : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_en_l : std_logic;
signal icap_rnw : std_logic;
signal fifo_rEn : std_logic;
signal fifo_wEn : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal count : std_logic_vector(31 downto 0);
signal debounce : std_logic_vector(1 downto 0);
signal dcr_reg : std_logic_vector(31 downto 0);
signal dcr_start_w : std_logic;
signal dcr_start_w_n : std_logic;
signal dcr_start_r : std_logic;
signal dcr_addr : std_logic_vector(31 downto 0);
signal ctrl_reg : std_logic_vector(31 downto 0);
signal Sl_dcrAck_sig : std_logic;
signal done_int_i : std_logic;
begin
ICAP_4 : ICAP_VIRTEX5
generic map (
ICAP_WIDTH => "X32") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
SWAP_BITS: process (icap_din) is
begin -- process Swap_bit_Order
for byte_i in 0 to 3 loop
for bit_i in 0 to 7 loop
icap_din_r(byte_i*8 + (7-bit_i)) <= icap_din(byte_i*8 + bit_i);
end loop; -- Bit
end loop; -- Byte
end process SWAP_BITS;
addr_tail <= (others => '0');
-- Make icap signals available to chipscope at output
BUSY <= icap_busy; -- Busy output
O <= icap_dout; -- 8-bit data output
CE <= icap_en_l; -- Clock enable input
I <= icap_din; -- 8-bit data input
WRITE <= icap_rnw; -- Write input
-- dcr interface instantiation
dcr_control: dcr_if
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR)
port map (
clk => clk,
rst => reset,
DCR_ABus => DCR_ABus,
DCR_Sl_DBus => DCR_Sl_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
Sl_dcrAck => Sl_dcrAck_sig,
Sl_dcrDBus => Sl_dcrDBus,
ctrl_reg => ctrl_reg);
dcr_start_w <= Sl_dcrAck_sig and DCR_Write;
Sl_dcrAck <= Sl_dcrAck_sig;
-- Make DCR signals available to chipscope at output
DCR_ABus_o <= DCR_ABus;
DCR_Write_o <= DCR_Write;
DCR_Din_o <= ctrl_reg;
Fifo_empty_o <= fifo_empty;
Fifo_full_o <= fifo_full;
-- -- WARNING!!!
-- -- The ICAP's data signals are reversed!
-- process(icap_din) begin
-- for i in 0 to 7 loop
-- icap_din_r(7-i) <= icap_din(i);
-- end loop;
-- end process;
---- if virtex2P or Virtex2 use ICAP_Virtex2 and invert input bits
-- V2_GEN : if (C_FAMILY = "virtex2p" or C_FAMILY = "virtex2") generate
--
-- V2_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
-- ICAP_0 : ICAP_VIRTEX2
-- port map (
-- BUSY => icap_busy, -- Busy output
-- O => icap_dout, -- 8-bit data output
-- CE => icap_en_l, -- Clock enable input
-- CLK => clk, -- Clock input
-- I => icap_din_r, -- 8-bit data input
-- WRITE => icap_rnw -- Write input
-- );
--
-- -- WARNING!!!
-- -- The ICAP's data signals are reversed in V2P!
-- process(icap_din) begin
-- for i in 0 to 7 loop
-- icap_din_r(7-i) <= icap_din(i);
-- end loop;
-- end process;
--
-- end generate V2_GEN_8;
-- end generate V2_GEN;
--
-- V4_GEN : if (C_FAMILY = "virtex4") generate
-- V4_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
--
-- ICAP_1 : ICAP_VIRTEX4
-- generic map (
-- ICAP_WIDTH => "X8") -- "X8" or "X32"
-- port map (
-- BUSY => icap_busy, -- Busy output
-- O => icap_dout, -- 8-bit data output
-- CE => icap_en_l, -- Clock enable input
-- CLK => clk, -- Clock input
-- I => icap_din_r, -- 8-bit data input
-- WRITE => icap_rnw -- Write input
-- );
--
-- process(icap_din) begin
-- for i in 0 to 7 loop
-- icap_din_r(7-i) <= icap_din(i);
-- end loop;
-- end process;
--
-- end generate V4_GEN_8;
--
-- V4_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
--
-- ICAP_2 : ICAP_VIRTEX4
-- generic map (
-- ICAP_WIDTH => "X32") -- "X8" or "X32"
-- port map (
-- BUSY => icap_busy, -- Busy output
-- O => icap_dout, -- 8-bit data output
-- CE => icap_en_l, -- Clock enable input
-- CLK => clk, -- Clock input
-- I => icap_din_r, -- 8-bit data input
-- WRITE => icap_rnw -- Write input
-- );
--
-- icap_din_r <= icap_din;
--
-- end generate V4_GEN_32;
--
-- end generate V4_GEN;
--
-- V5_GEN : if (C_FAMILY = "virtex5") generate
-- V5_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
--
-- ICAP_3 : ICAP_VIRTEX5
-- generic map (
-- ICAP_WIDTH => "X8") -- "X8" or "X32"
-- port map (
-- BUSY => icap_busy, -- Busy output
-- O => icap_dout, -- 8-bit data output
-- CE => icap_en_l, -- Clock enable input
-- CLK => clk, -- Clock input
-- I => icap_din_r, -- 8-bit data input
-- WRITE => icap_rnw -- Write input
-- );
--
-- process(icap_din) begin
-- for i in 0 to 7 loop
-- icap_din_r(7-i) <= icap_din(i);
-- end loop;
-- end process;
--
-- end generate V5_GEN_8;
--
-- V5_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
--
-- ICAP_4 : ICAP_VIRTEX5
-- generic map (
-- ICAP_WIDTH => "X32") -- "X8" or "X32"
-- port map (
-- BUSY => icap_busy, -- Busy output
-- O => icap_dout, -- 8-bit data output
-- CE => icap_en_l, -- Clock enable input
-- CLK => clk, -- Clock input
-- I => icap_din_r, -- 8-bit data input
-- WRITE => icap_rnw -- Write input
-- );
--
-- SWAP_BITS: process (icap_din) is
-- begin -- process Swap_bit_Order
-- for byte_i in 0 to 3 loop
-- for bit_i in 0 to 7 loop
-- icap_din_r(byte_i*8 + (7-bit_i)) <= icap_din(byte_i*8 + bit_i);
-- end loop; -- Bit
-- end loop; -- Byte
-- end process SWAP_BITS;
--
-- end generate V5_GEN_32;
-- end generate V5_GEN;
-- fifo_empty is active high. If Fifo is not empty (fifo_empty = '0') rnw and ce gow low!
icap_rnw <= fifo_empty;
icap_en_l <= fifo_empty;
fifo_rEn <= not icap_busy;
fifo_wEn <= M_rdAck_i when(state=BURSTING) else '0';
icapFIFO_0 : icapFIFO
generic map (
C_FIFO_DEPTH => 64,
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => C_ICAP_DWIDTH
)
port map (
clk => clk,
reset => reset,
wEn_i => fifo_wEn,
wData_i => M_rdData_i,
rEn_i => fifo_rEn,
rData_o => icap_din,
full_o => fifo_full,
empty_o => fifo_empty
);
-- process(state, debounce, addr, base_addr) begin
-- M_rdAddr_o <= base_addr & addr & b"0000000";
-- if(state=IDLE) then
-- if(debounce(0)='0') then
-- M_rdAddr_o <= C_CONFIG_ADDR_0;
-- else
-- M_rdAddr_o <= C_CONFIG_ADDR_1;
-- end if;
-- end if;
-- end process;
-- Generate the read address
--M_rdAddr_o <= base_addr & addr & b"0000000";
--M_rdAddr_o <= base_addr & addr & b"00000000";
M_rdAddr_o <= base_addr & addr & addr_tail;
done_int <= done_int_i;
-- delay start signal by one cycle
process(clk) begin
if(clk='1' and clk'event) then
dcr_start_w_n <= dcr_start_w;
end if;
end process;
process(state, fifo_full, fifo_empty, addr) begin
-- don't request data
M_rdReq_o <= '0';
M_rdNum_o <= "10000";
M_wrReq_o <= '0';
-- if(state=IDLE) then
-- -- debounce is active low, when one of the switches is pressed debounce goes low.
-- --M_rdReq_o <= not debounce(0) or not debounce(1); -- is one of the switches pressed?
-- M_rdReq_o <= dcr_start_w;
-- M_rdNum_o <= "00001"; -- request one 64 bit word
-- els
--if(state=ACTIVE) then
if ((state=ACTIVE or state=BURSTING) and (addr /= base_lngth)) then
M_rdReq_o <= not fifo_full;
elsif(state=WRITE_COUNT) then
M_wrReq_o <= fifo_empty;
end if;
end process;
M_wrAddr_o <= C_COUNT_ADDR;
M_wrNum_o <= "00001";
M_wrData_o(63 downto 32) <= (others=>'0');
M_wrData_o(31 downto 0) <= count;
process(clk) begin
if(clk='1' and clk'event) then
if(state=IDLE) then
count <= (others=>'0');
else
if(fifo_empty='0') then -- if Fifo is not empty increase counter
count <= count+1;
end if;
end if;
end if;
end process;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
state <= IDLE;
addr <= (others=>'0');
base_addr <= (others=>'0');
base_lngth <= (others=>'0');
dcr_reg <= (others => '0');
done_int_i <= '0';
else
done_int_i <= '0';
case(state) is
when IDLE =>
addr <= (others=>'0');
-- initialize base addr and base_lngth with the data from DCR bus once!
base_addr <= ctrl_reg(31 downto 22);
base_lngth <= ctrl_reg(15 downto 0);
if(dcr_start_w_n='1') then
state <= ACTIVE;
end if;
when ACTIVE =>
if(M_rdAccept_i='1') then
addr <= addr + 1;
--dcr_reg(21 downto 7) <= dcr_reg(21 downto 7) + 1;
state <= BURSTING;
end if;
when BURSTING =>
if(M_rdComp_i='1') then
if(addr=base_lngth) then
state <= WRITE_COUNT;
else
state <= ACTIVE;
end if;
end if;
when WRITE_COUNT =>
--if(M_wrAccept_i='1') then
state <= DONE;
--end if;
when DONE =>
if(fifo_empty = '1') then
done_int_i <= '1';
state <= IDLE;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
end icapCTRL_rtl;
|
gpl-3.0
|
98a0719d62953d374b968cf43e804e2d
| 0.518702 | 3.089384 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/FiFo/fifo_generator_v13_0_1/hdl/fifo_generator_v13_0.vhd
| 10 | 91,022 |
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`protect end_protected
|
mit
|
d2a0be1c94febb1c2b5bcdee9899e364
| 0.952737 | 1.839869 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/v_ram/synth/v_ram.vhd
| 1 | 14,504 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY v_ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END v_ram;
ARCHITECTURE v_ram_arch OF v_ram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF v_ram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF v_ram_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF v_ram_arch : ARCHITECTURE IS "v_ram,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF v_ram_arch: ARCHITECTURE IS "v_ram,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=v_ram.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=76800,C_READ_DEPTH_A=76800,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=76800,C_READ_DEPTH_B=76800,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=26,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.2184 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "v_ram.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 76800,
C_READ_DEPTH_A => 76800,
C_ADDRA_WIDTH => 17,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 76800,
C_READ_DEPTH_B => 76800,
C_ADDRB_WIDTH => 17,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "26",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.2184 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END v_ram_arch;
|
mit
|
fb1a0a558ab5027c529de0c32cd28fa1
| 0.626586 | 3.017894 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/srl_fifo.vhd
| 4 | 7,611 |
-------------------------------------------------------------------------------
-- $Id: srl_fifo.vhd,v 1.1 2005/02/17 20:29:35 crh Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:29:35 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : integer := 8;
C_DEPTH : integer := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
FIFO_Level : out std_logic_vector(0 to 3);
Half_Full : out std_logic;
Half_Empty : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
-- pragma translate_off
Xon : boolean;
-- pragma translate_on
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
signal Addr : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
signal reset_int : std_logic;
begin -- architecture IMP
FIFO_Level <= Addr;
reset_int <= Clear_FIFO or Reset;
buffer_Full <= '1' when (Addr = "1111") else '0';
FIFO_Full <= buffer_Full;
Half_Full <= Addr(3);
Half_Empty <= not Addr(3);
buffer_Empty <= '1' when (Addr = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (reset_int = '1') then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(4) is not used anywhere
Used_MuxCY : if I < 3 generate
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => reset_int); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
end architecture IMP;
|
gpl-3.0
|
d1693f5c98804309e2f9ad65a80cfc83
| 0.420838 | 3.779047 | false | false | false | false |
db-electronics/SMSFlashCart
|
SMSCart.vhd
| 1 | 2,455 |
--*************************************************************
-- db Mapper
-- Copyright 2015 Rene Richard
-- DEVICE : EPM3064ATC100-10
--*************************************************************
--
-- Description:
-- This is a VHDL implementation of an SMS Sega Mapper
-- it is intended to be used on the db Electronics SMS Homebrew Carts
-- Supported Flash Memory Configurations:
-- 2Mbit (1x 2Mbit)
-- 4Mbit (1x 4Mbit)
-- 8Mbit (1x 4Mbit)
-- Support RAM Configurations
-- 32KB
--
-- for a complete description of SMS Mappers, go to http://www.smspower.org/Development/Mappers
--*************************************************************
--
-- RAM and Misc. Register
-- $FFFC
-- bit 7: ROM Write Enable
-- when '1' writes to ROM (i.e. Flash) are enabled
-- when '0' writes to mapper registers are enabled
-- bit 3: RAM Enable
-- when '1' RAM will be mapped into slot 2, overriding any ROM banking via $ffff
-- when '0' ROM banking is effective
-- bit 2: RAM Bank Select
-- when '1' maps the upper 16KB of RAM into slot 2
-- when '0' maps the lower 16KB of RAM into slot 2
--*************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SMSCart is
port (
--input from sms
ADDR_p : in std_logic_vector(15 downto 0);
DATA_p : in std_logic_vector(7 downto 0);
nRST_p : in std_logic;
nWR_p : in std_logic;
nCE_p : in std_logic;
--output to ROM
nROMWE_p : out std_logic;
nROMCE_p : out std_logic;
ROMADDR1914_p : out std_logic_vector(5 downto 0);
--output to serial EEPROM
EE_CS_p : out std_logic;
EE_SO_p : out std_logic;
EE_SI_p : out std_logic;
EE_SCK_p : out std_logic;
--output to SRAM
nSRAMCE_p : out std_logic;
nSRAMWE_p : out std_logic;
SRAMADDR14_p : out std_logic
);
end entity;
architecture SMSCart_a of SMSCart is
begin
SMSMapper_inst: entity work.SMSMapper
generic map(
SLOT0ENABLE => true,
SLOT1ENABLE => true
)
port map(
ADDR_p => ADDR_p,
DATA_p => DATA_p,
nRST_p => nRST_p,
nWR_p => nWR_p,
nCE_p => nCE_p,
nROMWE_p => nROMWE_p,
nROMCE_p => nROMCE_p,
ROMADDR1914_p => ROMADDR1914_p,
EE_CS_p => EE_CS_p,
EE_SO_p => EE_SO_p,
EE_SI_p => EE_SI_p,
EE_SCK_p => EE_SCK_p,
nSRAMCE_p => nSRAMCE_p,
nSRAMWE_p => nSRAMWE_p,
SRAMADDR14_p => SRAMADDR14_p
);
end SMSCart_a;
|
gpl-2.0
|
df00db753fd46a4d4159f0d60592fae2
| 0.556008 | 2.767756 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v1_00_a/hdl/vhdl/standalone/standalone.vhd
| 4 | 4,083 |
-------------------------------------------------------------------------------
-- Filename: standalone.vhd
--
-- Description: Sample circuit for doing audio standalone
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/17 20:26:29 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity standalone is
port (
ClkIn : in std_logic;
Reset_n : in std_logic;
LED : out std_logic_vector(3 downto 0);
DEBUG : out std_logic_vector(4 downto 0);
-- CODEC signals
AC97Reset_n : out std_logic;
AC97Clk : in std_logic; -- master clock for design
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end standalone;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.ac97_if_pkg.all;
architecture imp of standalone is
signal new_sample : std_logic;
signal left_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_0 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_1 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal left_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal right_channel_2 : std_logic_Vector(15 downto 0) := "0000000000000000";
signal leds_i : std_logic_vector(3 downto 0);
signal clkin_cntr : unsigned(26 downto 0) := (others => '0');
signal ac97clk_cntr : unsigned(26 downto 0) := (others => '0');
signal debug_i : std_logic_vector(3 downto 0);
signal reset_i : std_logic;
signal ac97reset_n_i,sync_i,sdata_out_i : std_logic;
component ac97_if is
port (
ClkIn : in std_logic;
Reset : in std_logic;
-- All signals synchronous to ClkIn
PCM_Playback_Left: in std_logic_vector(15 downto 0);
PCM_Playback_Right: in std_logic_vector(15 downto 0);
PCM_Playback_Accept: out std_logic;
PCM_Record_Left: out std_logic_vector(15 downto 0);
PCM_Record_Right: out std_logic_vector(15 downto 0);
PCM_Record_Valid: out std_logic;
Debug : out std_logic_vector(3 downto 0);
AC97Reset_n : out std_logic; -- AC97Clk
-- CODEC signals (synchronized to AC97Clk)
AC97Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic
);
end component ac97_if;
begin
reset_i <= not Reset_n;
delay_PROCESS : process (ClkIn) is
begin
if ClkIn'event and ClkIn='1' and new_sample = '1' then
left_channel_1 <= left_channel_0;
right_channel_1 <= right_channel_0;
left_channel_2 <= left_channel_1;
right_channel_2 <= right_channel_1;
end if;
end process;
LED <= not debug_i;
ac97_if_I : ac97_if
port map (
ClkIn => ClkIn,
Reset => Reset_i,
PCM_Playback_Left => left_channel_2,
PCM_Playback_Right => right_channel_2,
PCM_Playback_Accept => new_sample,
PCM_Record_Left => left_channel_0,
PCM_Record_Right => right_channel_0,
PCM_Record_Valid => open,
Debug => debug_i,
AC97Reset_n => AC97Reset_n_i,
AC97Clk => AC97Clk,
Sync => sync_i,
SData_Out => SData_Out_i,
SData_In => SData_in
);
AC97Reset_n <= AC97Reset_n_i;
Sync <= sync_i;
SData_Out <= SData_Out_i;
DEBUG(0) <= AC97Clk;
DEBUG(1) <= AC97Reset_n_i;
DEBUG(2) <= Sync_i;
DEBUG(3) <= SData_Out_i;
DEBUG(4) <= SData_In;
end architecture imp;
|
gpl-3.0
|
37cc75bafba6e165678ceb1f43a293b3
| 0.551555 | 3.466044 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_dpram.vhd
| 1 | 6,394 |
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-16
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-- 2012-03-13 1.1 wterpstra Added initial value as array
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram;
architecture syn of generic_dpram is
component generic_dpram_sameclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram_dualclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
gen_single_clk : if(g_dual_clock = false) generate
U_RAM_SC: generic_dpram_sameclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clk_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_single_clk;
gen_dual_clk : if(g_dual_clock = true) generate
U_RAM_DC: generic_dpram_dualclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
clkb_i => clkb_i,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_dual_clk;
end syn;
|
lgpl-3.0
|
5a5c30807ff68b456eb4dd71da121384
| 0.507663 | 3.237468 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/dcr_v29_v9_00_a/hdl/vhdl/dcr_v29_wrp.vhd
| 7 | 8,671 |
-------------------------------------------------------------------------------
-- $Header: /devl/xcs/repo/env/Databases/ip2/processor/hardware/dcr_v29/dcr_v29_v1_00_b/hdl/src/vhdl/Attic/dcr_v29_wrp.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Im_SP1
-- Updated Release For V5 Porting
-- END_CHANGELOG
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library dcr_v29_v9_00_a;
use dcr_v29_v9_00_a.all;
ENTITY dcr_v29_wrp IS
-- Declare wrapper generic parameters here
generic (
C_DCR_NUM_SLAVES : INTEGER := 1;
C_DCR_AWIDTH : INTEGER := 10;
C_DCR_DWIDTH : INTEGER := 32;
C_USE_LUT_OR : INTEGER := 1
);
-- Declare wrapper ports here
port (
-- Master outputs
M_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
M_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
M_dcrRead : in std_logic;
M_dcrWrite : in std_logic;
-- Master inputs
DCR_M_DBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Ack : out std_logic;
-- Slave inputs
DCR_ABus : out std_logic_vector(0 to C_DCR_AWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Sl_DBus : out std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Read : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
DCR_Write : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
-- slave outputs
Sl_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
Sl_dcrAck : in std_logic_vector(0 to C_DCR_NUM_SLAVES-1)
);
END ENTITY dcr_v29_wrp;
architecture implementation of dcr_v29_wrp is
COMPONENT dcr_v29 IS
-- Declare generic parameters here
generic (
C_DCR_NUM_SLAVES : integer;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_USE_LUT_OR : integer
);
-- Declare ports here
port (
-- Master outputs
M_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
M_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
M_dcrRead : in std_logic;
M_dcrWrite : in std_logic;
-- Master inputs
DCR_M_DBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Ack : out std_logic;
-- Slave inputs
DCR_ABus : out std_logic_vector(0 to C_DCR_AWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Sl_DBus : out std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
DCR_Read : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
DCR_Write : out std_logic_vector(0 to C_DCR_NUM_SLAVES-1);
-- slave outputs
Sl_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH*C_DCR_NUM_SLAVES-1);
Sl_dcrAck : in std_logic_vector(0 to C_DCR_NUM_SLAVES-1)
);
END COMPONENT dcr_v29;
BEGIN -- architecture implementation
dcr_v29_imp : dcr_v29
GENERIC MAP ( -- Declare generic map here
C_DCR_NUM_SLAVES => C_DCR_NUM_SLAVES,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_USE_LUT_OR => C_USE_LUT_OR
)
PORT MAP ( -- Declare port map here
M_dcrABus => M_dcrABus,
M_dcrDBus => M_dcrDBus,
M_dcrRead => M_dcrRead,
M_dcrWrite => M_dcrWrite,
DCR_M_DBus => DCR_M_DBus,
DCR_Ack => DCR_Ack,
DCR_ABus => DCR_ABus,
DCR_Sl_DBus => DCR_Sl_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
Sl_dcrDBus => Sl_dcrDBus,
Sl_dcrAck => Sl_dcrAck
);
END ARCHITECTURE implementation;
|
gpl-3.0
|
46c1a9891d4fe2e8d4d83ab3c9d2bb60
| 0.434783 | 4.761669 | false | false | false | false |
luebbers/reconos
|
tests/simulation/plb/mbox_hw/test_mbox.vhd
| 1 | 2,316 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mbox is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mbox;
architecture Behavioral of test_mbox is
constant C_MB_IN : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_OUT : std_logic_vector(0 to 31) := X"00000001";
type t_state is (STATE_GET, STATE_PUT);
signal state : t_state := STATE_GET;
signal data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal data_inv : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
data_inv <= not data;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_IN, data);
if done and success then
state <= STATE_PUT;
end if;
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_OUT, data_inv);
if done and success then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
2b8cc8f7bb66f3cd18c5da1b7b222253
| 0.59456 | 3.230126 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/FiFo/sim/FiFo.vhd
| 1 | 33,440 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY FiFo IS
PORT (
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END FiFo;
ARCHITECTURE FiFo_arch OF FiFo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FiFo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END FiFo_arch;
|
mit
|
ab6f537d44f4736f35f6728e9e9f5ac4
| 0.606669 | 3.06958 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/bfm_system.vhd
| 1 | 31,892 |
-------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_compress : out std_logic;
M_guarded : out std_logic;
M_ordered : out std_logic;
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 15);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_ordered : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 127);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MErr : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 7);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_ordered : in std_logic;
PLB_lockErr : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 1);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_MErr : in std_logic_vector(0 to 3);
Sl_ssize : in std_logic_vector(0 to 3);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 63);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMErr : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_ordered : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MErr : in std_logic_vector(0 to 3);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_compress : out std_logic;
PLB_guarded : out std_logic;
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_ordered : out std_logic;
PLB_pendPri : out std_logic_vector(0 to 1);
PLB_pendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic;
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic;
PLB_SaddrAck : out std_logic;
PLB_SMErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
ArbAddrVldReg : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to 7);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to 7);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_M_ABus : std_logic_vector(0 to 63);
signal plb_bus_M_BE : std_logic_vector(0 to 15);
signal plb_bus_M_MSize : std_logic_vector(0 to 3);
signal plb_bus_M_RNW : std_logic_vector(0 to 1);
signal plb_bus_M_abort : std_logic_vector(0 to 1);
signal plb_bus_M_busLock : std_logic_vector(0 to 1);
signal plb_bus_M_compress : std_logic_vector(0 to 1);
signal plb_bus_M_guarded : std_logic_vector(0 to 1);
signal plb_bus_M_lockErr : std_logic_vector(0 to 1);
signal plb_bus_M_ordered : std_logic_vector(0 to 1);
signal plb_bus_M_priority : std_logic_vector(0 to 3);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 1);
signal plb_bus_M_request : std_logic_vector(0 to 1);
signal plb_bus_M_size : std_logic_vector(0 to 7);
signal plb_bus_M_type : std_logic_vector(0 to 5);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 1);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 7);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_MErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 3);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 63);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_compress : std_logic;
signal plb_bus_PLB_guarded : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_ordered : std_logic;
signal plb_bus_PLB_pendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_pendReq : std_logic;
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 63);
signal plb_bus_PLB_wrPrim : std_logic;
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 3);
signal plb_bus_Sl_MErr : std_logic_vector(0 to 3);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 3);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 1);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 127);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 1);
signal plb_bus_Sl_wait : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 1);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 1);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize(0 to 1),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MErr => plb_bus_PLB_MErr(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(0 to 63),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(0 to 3),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority(0 to 1),
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE(0 to 7),
M_msize => plb_bus_M_MSize(0 to 1),
M_size => plb_bus_M_size(0 to 3),
M_type => plb_bus_M_type(0 to 2),
M_compress => plb_bus_M_compress(0),
M_guarded => plb_bus_M_guarded(0),
M_ordered => plb_bus_M_ordered(0),
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_ABus => plb_bus_M_ABus(0 to 31),
M_wrDBus => plb_bus_M_wrDBus(0 to 63),
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_ordered => plb_bus_PLB_ordered,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize(0 to 1),
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus(0 to 63),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(0 to 3),
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy(0 to 1),
Sl_MErr => plb_bus_Sl_MErr(0 to 1)
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request,
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock,
M_RNW => plb_bus_M_RNW,
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_compress => plb_bus_M_compress,
M_guarded => plb_bus_M_guarded,
M_ordered => plb_bus_M_ordered,
M_lockErr => plb_bus_M_lockErr,
M_abort => plb_bus_M_abort,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst,
M_rdBurst => plb_bus_M_rdBurst,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MErr => plb_bus_PLB_MErr,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_ordered => plb_bus_PLB_ordered,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_wait => plb_bus_Sl_wait,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_wrDAck => plb_bus_Sl_wrDAck,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MErr => plb_bus_Sl_MErr,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SMErr => plb_bus_PLB_SMErr,
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW,
M_abort => plb_bus_M_abort,
M_busLock => plb_bus_M_busLock,
M_compress => plb_bus_M_compress,
M_guarded => plb_bus_M_guarded,
M_lockErr => plb_bus_M_lockErr,
M_MSize => plb_bus_M_MSize,
M_ordered => plb_bus_M_ordered,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst,
M_request => plb_bus_M_request,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst,
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck,
Sl_MErr => plb_bus_Sl_MErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm,
Sl_rdComp => plb_bus_Sl_rdComp,
Sl_rdDAck => plb_bus_Sl_rdDAck,
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate,
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait,
Sl_wrBTerm => plb_bus_Sl_wrBTerm,
Sl_wrComp => plb_bus_Sl_wrComp,
Sl_wrDAck => plb_bus_Sl_wrDAck,
PLB_ABus => plb_bus_PLB_ABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MErr => plb_bus_PLB_MErr,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_ordered => plb_bus_PLB_ordered,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMErr => plb_bus_PLB_SMErr,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd2,
ArbAddrVldReg => open,
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
PLB_Clk => sys_clk,
PLB_Rst => plb_bus_PLB_Rst,
Sl_addrAck => plb_bus_Sl_addrAck(1),
Sl_MBusy => plb_bus_Sl_MBusy(2 to 3),
Sl_MErr => plb_bus_Sl_MErr(2 to 3),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(1),
Sl_rdComp => plb_bus_Sl_rdComp(1),
Sl_rdDAck => plb_bus_Sl_rdDAck(1),
Sl_rdDBus => plb_bus_Sl_rdDBus(64 to 127),
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr(4 to 7),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(1),
Sl_SSize => plb_bus_Sl_SSize(2 to 3),
Sl_wait => plb_bus_Sl_wait(1),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(1),
Sl_wrComp => plb_bus_Sl_wrComp(1),
Sl_wrDAck => plb_bus_Sl_wrDAck(1),
PLB_abort => plb_bus_PLB_abort,
PLB_ABus => plb_bus_PLB_ABus,
PLB_BE => plb_bus_PLB_BE,
PLB_busLock => plb_bus_PLB_busLock,
PLB_compress => plb_bus_PLB_compress,
PLB_guarded => plb_bus_PLB_guarded,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_ordered => plb_bus_PLB_ordered,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_pendPri => plb_bus_PLB_pendPri,
PLB_pendReq => plb_bus_PLB_pendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim,
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim,
M_abort => plb_bus_M_abort(1),
M_ABus => plb_bus_M_ABus(32 to 63),
M_BE => plb_bus_M_BE(8 to 15),
M_busLock => plb_bus_M_busLock(1),
M_compress => plb_bus_M_compress(1),
M_guarded => plb_bus_M_guarded(1),
M_lockErr => plb_bus_M_lockErr(1),
M_MSize => plb_bus_M_MSize(2 to 3),
M_ordered => plb_bus_M_ordered(1),
M_priority => plb_bus_M_priority(2 to 3),
M_rdBurst => plb_bus_M_rdBurst(1),
M_request => plb_bus_M_request(1),
M_RNW => plb_bus_M_RNW(1),
M_size => plb_bus_M_size(4 to 7),
M_type => plb_bus_M_type(3 to 5),
M_wrBurst => plb_bus_M_wrBurst(1),
M_wrDBus => plb_bus_M_wrDBus(64 to 127),
PLB_MBusy => plb_bus_PLB_MBusy(1),
PLB_MErr => plb_bus_PLB_MErr(1),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(1),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(1),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(1),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(1),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(1),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(64 to 127),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(4 to 7),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(1),
PLB_MSSize => plb_bus_PLB_MSSize(2 to 3),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
|
gpl-3.0
|
7d5a9e64672a15759c0fc63627bf1ca7
| 0.603255 | 3.032712 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/IcapCTRL_v1_00_d/ise/icap/icapFIFO.vhd
| 2 | 5,731 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:02:34 07/20/2006
-- Design Name:
-- Module Name: icapFIFO - icapFIFO_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity icapFIFO is
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end icapFIFO;
architecture icapFIFO_rtl of icapFIFO is
-- A synthesizable function that returns the integer part of the base 2 logarithm for a positive number
-- is (uses recursion) from http://tams-www.informatik.uni-hamburg.de/vhdl/doc/faq/FAQ1.html
function log2(x:positive) return natural is
begin
if(x<=1) then
return 0;
else
return log2(x/2)+1;
end if;
end function log2;
constant C_AIN_WIDTH : integer := log2(C_FIFO_DEPTH); -- 6 in this case
constant C_AOUT_WIDTH : integer := log2(C_FIFO_DEPTH*C_DIN_WIDTH/C_DOUT_WIDTH); -- 9 in this case
constant C_AOUT_SPLIT : integer := C_AOUT_WIDTH - C_AIN_WIDTH; -- 3 in this case
type fifo_type is array(C_FIFO_DEPTH-1 downto 0) of std_logic_vector(C_DIN_WIDTH-1 downto 0);
signal fifo : fifo_type;
signal head, head_n : std_logic_vector(C_AIN_WIDTH-1 downto 0);
signal tail, tail_n : std_logic_vector(C_AOUT_WIDTH-1 downto 0);
signal empty, empty_p : std_logic;
-- Add keep attribute to tail_n to prevent synthesis of both counter and adder
attribute keep : string;
attribute keep of tail_n : signal is "true";
signal fData : std_logic_vector(C_DIN_WIDTH-1 downto 0);
type fMux_type is array(C_DIN_WIDTH/C_DOUT_WIDTH-1 downto 0) of std_logic_vector(C_DOUT_WIDTH-1 downto 0);
signal fMux : fMux_type;
begin
head_n <= head+1 when(wEn_i='1') else head;
tail_n <= tail+1 when(rEn_i='1') else tail;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
head <= (others=>'0');
tail <= (others=>'0');
else
head <= head_n;
tail <= tail_n;
end if;
-- if wEn_i ='1' write wData_i to Address specified by head pointer.
if(wEn_i='1') then
fifo(CONV_INTEGER(UNSIGNED(head))) <= wData_i;
end if;
-- if(wEn_i='1' and tail_n(C_AOUT_WIDTH-1 downto C_AOUT_WIDTH-C_AIN_WIDTH)=head) then
-- fData <= wData_i;
-- else
fData <= fifo(CONV_INTEGER(UNSIGNED(tail_n(C_AOUT_WIDTH-1 downto C_AOUT_SPLIT)))); -- tail_n(8 downto 3)
-- ???
-- end if;
end if;
end process;
--empty signal one cycle delayed, because no write through is supported
empty <= '1' when(tail(C_AOUT_WIDTH-1 downto C_AOUT_SPLIT) = head) else '0'; -- tail(8 downto 3)
process(clk) begin
if(clk='1' and clk'event) then
empty_p <= empty;
end if;
end process;
empty_o <= '0' when(empty='0' and empty_p='0') else '1';
-- Generate the full signal
-- asserted whenever the fifo memory is 3/4 full
-- here is an example when the fifo memory is 3/4 full (fMSB = 1100)
-- 00 01 10 11 00 01 10 <- MSBs from head and tail
-- |________|________|________|________|________|________|________|
--
-- ^ ^
-- | |
-- Tail Head
--
-- The fifo is 3/4 full when fMSB equals (0001, 0110, 1011, 1100)
-- These processes generate the full and the empty signal
process(head, tail)
variable fMSB : std_logic_vector(3 downto 0);
begin
-- in this case fMSB is composed of head(5) & head (4) & tail(8) & tail(7)
fMSB := head(C_AIN_WIDTH-1)&head(C_AIN_WIDTH-2)&tail(C_AOUT_WIDTH-1)&tail(C_AOUT_WIDTH-2);
case(fMSB) is
when "0000" => full_o <= '0';
when "0001" => full_o <= '1';
when "0010" => full_o <= '0';
when "0011" => full_o <= '0';
when "0100" => full_o <= '0';
when "0101" => full_o <= '0';
when "0110" => full_o <= '1';
when "0111" => full_o <= '0';
when "1000" => full_o <= '0';
when "1001" => full_o <= '0';
when "1010" => full_o <= '0';
when "1011" => full_o <= '1';
when "1100" => full_o <= '1';
when "1101" => full_o <= '0';
when "1110" => full_o <= '0';
when "1111" => full_o <= '0';
when others => full_o <= '0';
end case;
end process;
process(fData) begin
for i in 0 to C_DIN_WIDTH/C_DOUT_WIDTH-1 loop
-- BUG: fMux(C_DIN_WIDTH/C_DOUT_WIDTH-1-i) <= fData((i+1)*(C_DIN_WIDTH/C_DOUT_WIDTH)-1 downto i*(C_DIN_WIDTH/C_DOUT_WIDTH));
fMux(C_DIN_WIDTH/C_DOUT_WIDTH-1-i) <= fData((i+1)*C_DOUT_WIDTH-1 downto i*C_DOUT_WIDTH);
end loop;
end process;
rData_o <= fMux(CONV_INTEGER(UNSIGNED(tail(C_AOUT_SPLIT-1 downto 0)))); -- tail(2 downto 0)
end icapFIFO_rtl;
|
gpl-3.0
|
7ad998c990fe2cd966642b1ed85ac215
| 0.549468 | 3.203466 | false | false | false | false |
five-elephants/hw-neural-sampling
|
sampling_shell.vhdl
| 1 | 2,797 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
use work.net_config.all;
entity sampling_shell is
generic (
num_samplers : integer := 4;
tau : positive := 20;
num_observers : natural := 16
);
port (
clk, reset : in std_ulogic;
observed_joints : in state_array2_t(1 to num_observers, 1 to num_samplers);
joint_counters : out joint_counter_array_t(1 to num_observers);
systime : out systime_t
);
end sampling_shell;
architecture rtl of sampling_shell is
------------------------------------------------------------
--function init_seeds
--return lfsr_state_array_t is
--variable seed1, seed2 : positive;
--variable rand : real;
--variable int_rand : integer;
--variable rv : lfsr_state_array_t(1 to num_samplers);
--begin
--for i in rv'range loop
--uniform(seed1, seed2, rand);
--int_rand := integer(rand*(2.0**lfsr_width-1.0));
--rv(i) := std_logic_vector(to_unsigned(int_rand, rv(i)'length));
--end loop;
--return rv;
--end function init_seeds;
------------------------------------------------------------
-- TODO initialise constants
--constant seeds : lfsr_state_array_t(1 to num_samplers) := init_seeds;
signal state : state_array_t(1 to num_samplers);
begin
------------------------------------------------------------
net: entity work.sampling_network(rtl)
generic map (
num_samplers => num_samplers,
tau => tau
)
port map (
clk => clk,
reset => reset,
clock_tick => open,
systime => systime,
state => state,
membranes => open,
fires => open,
seeds => seeds,
biases => biases,
weights => weights
);
------------------------------------------------------------
------------------------------------------------------------
gen_observers: for observer_i in 1 to num_observers generate
signal observe_state : state_array_t(1 to num_samplers);
begin
------------------------------------------------------------
process ( observed_joints )
begin
for i in 1 to num_samplers loop
observe_state(i) <= observed_joints(observer_i, i);
end loop;
end process;
------------------------------------------------------------
obs: entity work.observer(rtl)
generic map (
num_samplers => num_samplers,
counter_width => joint_counter_width
)
port map (
clk => clk,
reset => reset,
state => state,
observe_state => observe_state,
count => joint_counters(observer_i),
saturated => open
);
end generate gen_observers;
------------------------------------------------------------
end rtl;
-- vim: set et fenc= ff=unix sts=0 sw=2 ts=2 :
|
apache-2.0
|
d96e065fb1c6d005536623e41b10207b
| 0.508044 | 4.137574 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/bd/system/ip/system_irq_gen_0_0/synth/system_irq_gen_0_0.vhd
| 1 | 8,527 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:irq_gen:1.1
-- IP Revision: -1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY my_ipif;
USE my_ipif.irq_gen;
ENTITY system_irq_gen_0_0 IS
PORT (
IRQ : OUT STD_LOGIC;
VIO_IRQ_TICK : IN STD_LOGIC;
vio_rise_edge : OUT STD_LOGIC;
slv_reg : OUT STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC
);
END system_irq_gen_0_0;
ARCHITECTURE system_irq_gen_0_0_arch OF system_irq_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_irq_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT irq_gen IS
GENERIC (
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_DPHASE_TIMEOUT : INTEGER;
C_FAMILY : STRING
);
PORT (
IRQ : OUT STD_LOGIC;
VIO_IRQ_TICK : IN STD_LOGIC;
vio_rise_edge : OUT STD_LOGIC;
slv_reg : OUT STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC
);
END COMPONENT irq_gen;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_irq_gen_0_0_arch: ARCHITECTURE IS "irq_gen,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_irq_gen_0_0_arch : ARCHITECTURE IS "system_irq_gen_0_0,irq_gen,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_irq_gen_0_0_arch: ARCHITECTURE IS "system_irq_gen_0_0,irq_gen,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=irq_gen,x_ipVersion=1.1,x_ipCoreRevision=-1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=9,C_DPHASE_TIMEOUT=8,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF IRQ: SIGNAL IS "xilinx.com:signal:interrupt:1.0 signal_interrupt INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
BEGIN
U0 : irq_gen
GENERIC MAP (
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 9,
C_DPHASE_TIMEOUT => 8,
C_FAMILY => "zynq"
)
PORT MAP (
IRQ => IRQ,
VIO_IRQ_TICK => VIO_IRQ_TICK,
vio_rise_edge => vio_rise_edge,
slv_reg => slv_reg,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY
);
END system_irq_gen_0_0_arch;
|
gpl-2.0
|
707c5e092ce383efdbd102a808e072c2
| 0.69579 | 3.280877 | false | false | false | false |
luebbers/reconos
|
core/pcores/plb_osif_v2_03_a/hdl/vhdl/bus_master.vhd
| 2 | 8,968 |
--!
--! \file bus_master.vhd
--!
--! PLB bus master logic for ReconOS OSIF (user_logic)
--!
--! \author Enno Luebbers <[email protected]>
--! \date 07.08.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 07.08.2006 Enno Luebbers File created
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity bus_master is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_SLAVE_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_BURST_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_BURSTLEN_WIDTH : integer := 5
);
port (
clk : in std_logic;
reset : in std_logic; -- high active synchronous
-- PLB bus master signals
Bus2IP_MstError : in std_logic;
Bus2IP_MstLastAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
IP2Bus_Addr : out std_logic_vector(0 to C_AWIDTH-1);
IP2Bus_MstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
IP2Bus_MstBurst : out std_logic;
IP2Bus_MstBusLock : out std_logic;
IP2Bus_MstNum : out std_logic_vector(0 to 4);
IP2Bus_MstRdReq : out std_logic;
IP2Bus_MstWrReq : out std_logic;
IP2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
-- user interface
i_my_addr : in std_logic_vector(0 to C_AWIDTH-1);
i_target_addr : in std_logic_vector(0 to C_AWIDTH-1);
i_read_req : in std_logic; -- single word
i_write_req : in std_logic; -- single word
i_burst_read_req : in std_logic; -- 128x64Bit burst
i_burst_write_req : in std_logic; -- 128x64Bit burst
i_burst_length : in std_logic_vector(0 to 4); -- number of burst beats (n x 64 bits)
o_busy : out std_logic;
o_read_done : out std_logic;
o_write_done : out std_logic
);
end bus_master;
architecture behavioral of bus_master is
-- signals for master control state machine
type plb_master_state_t is (IDLE, READ, WRITE);
signal plb_master_state : plb_master_state_t := IDLE;
signal mst_sm_rd_req : std_logic;
signal mst_sm_wr_req : std_logic;
signal mst_ip2ip_addr : std_logic_vector(0 to C_AWIDTH-1);
begin
-- connect common bus signalling
IP2Bus_Addr <= i_target_addr;
IP2IP_Addr <= mst_ip2ip_addr;
IP2Bus_MstBusLock <= '0'; -- FIXME: no atomic (locked) transactions
IP2Bus_MstRdReq <= mst_sm_rd_req;
IP2Bus_MstWrReq <= mst_sm_wr_req;
-- we are busy, when there are no pending and no running requests.
-- NOTE: incoming requests while non-idle are ignored.
o_busy <= '0' when (
(plb_master_state = IDLE) and
((i_read_req or i_write_req or i_burst_read_req or i_burst_write_req) = '0')
)
else '1';
-------------------------------------------------------------------
-- PLB master state machine
--
-- FIXME: are the mst_sm_*_req signals set right, or does this
-- cause too complicated logic?
-------------------------------------------------------------------
plb_master : process(clk, reset)
begin
if reset = '1' then
plb_master_state <= IDLE;
mst_sm_rd_req <= '0';
mst_sm_wr_req <= '0';
o_read_done <= '0';
o_write_done <= '0';
IP2Bus_MstBE <= "00000000"; -- 0 Bit
IP2Bus_MstBurst <= '0'; -- no burst
IP2Bus_MstNum <= "00001"; -- single beat transaction
mst_ip2ip_addr <= (others => '0');
elsif rising_edge(clk) then
o_read_done <= '0';
o_write_done <= '0';
case plb_master_state is
when IDLE =>
if i_read_req = '1' then
plb_master_state <= READ;
mst_sm_rd_req <= '1';
-- single
if i_target_addr(29) = '0' then -- align word access
IP2Bus_MstBE <= "11110000"; -- 32 Bit
else
IP2Bus_MstBE <= "00001111"; -- 32 Bit
end if;
IP2Bus_MstBurst <= '0'; -- no burst
IP2Bus_MstNum <= "00001"; -- single beat transaction
mst_ip2ip_addr <= i_my_addr OR C_SLAVE_BASEADDR;
elsif i_write_req = '1' then
plb_master_state <= WRITE;
mst_sm_wr_req <= '1';
-- single
if i_target_addr(29) = '0' then -- align word access
IP2Bus_MstBE <= "11110000"; -- 32 Bit
else
IP2Bus_MstBE <= "00001111"; -- 32 Bit
end if;
IP2Bus_MstBurst <= '0'; -- no burst
IP2Bus_MstNum <= "00001"; -- single beat transaction
mst_ip2ip_addr <= i_my_addr OR C_SLAVE_BASEADDR;
elsif i_burst_read_req = '1' then
plb_master_state <= READ;
mst_sm_rd_req <= '1';
-- burst
IP2Bus_MstBE <= "11111111"; -- 64 Bit
IP2Bus_MstBurst <= '1'; -- burst
IP2Bus_MstNum <= "11111"; -- 16x64 Bit burst
-- IP2Bus_MstNum <= i_burst_length; -- n x 64 Bit burst, max 16
mst_ip2ip_addr <= i_my_addr OR C_BURST_BASEADDR;
elsif i_burst_write_req = '1' then
plb_master_state <= WRITE;
mst_sm_wr_req <= '1';
-- burst
IP2Bus_MstBE <= "11111111"; -- 64 Bit
IP2Bus_MstBurst <= '1'; -- burst
mst_ip2ip_addr <= i_my_addr OR C_BURST_BASEADDR;
IP2Bus_MstNum <= "11111"; -- 16x64 Bit burst
-- IP2Bus_MstNum <= i_burst_length; -- n x 64 Bit burst, max 16
end if;
when READ =>
if Bus2IP_MstLastAck = '1' or -- on completion or
Bus2IP_MstTimeout = '1' or -- on timeout or
Bus2IP_MstError = '1' then -- on error
o_read_done <= '1'; -- finish transaction
mst_sm_rd_req <= '0';
plb_master_state <= IDLE;
end if;
when WRITE =>
if Bus2IP_MstLastAck = '1' or -- on completion or
Bus2IP_MstTimeout = '1' or -- on timeout or
Bus2IP_MstError = '1' then -- on error
o_write_done <= '1';
mst_sm_wr_req <= '0'; -- finish transaction
plb_master_state <= IDLE;
end if;
when others =>
plb_master_state <= IDLE;
end case;
end if;
end process;
end behavioral;
|
gpl-3.0
|
0ffd051a60ad017d18fe73229f8582e1
| 0.473127 | 3.97694 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/irq_gen_v1_1/f141c1dc/hdl/vhdl/irq_gen.vhd
| 2 | 17,014 |
------------------------------------------------------------------------------
-- irq_gen.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: irq_gen.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed May 30 12:34:16 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library my_ipif;
use my_ipif.ipif_pkg.SLV64_ARRAY_TYPE;
use my_ipif.ipif_pkg.INTEGER_ARRAY_TYPE;
use my_ipif.ipif_pkg.calc_start_ce_index;
use my_ipif.ipif_pkg.calc_num_ce;
-- library proc_common_v3_00_a;
-- use proc_common_v3_00_a.proc_common_pkg.all;
-- use proc_common_v3_00_a.ipif_pkg.all;
--
-- library axi_lite_ipif_v1_01_a;
-- use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library irq_gen_v1_00_a;
use irq_gen_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity irq_gen is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
IRQ : out std_logic;
VIO_IRQ_TICK : in std_logic;
vio_rise_edge : out std_logic;
slv_reg : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity irq_gen;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of irq_gen is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity my_ipif.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity irq_gen_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
IRQ => IRQ,
VIO_IRQ_TICK => VIO_IRQ_TICK,
vio_rise_edge => vio_rise_edge,
slv_reg => slv_reg,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
gpl-2.0
|
dc629c771f492387c4b680d34568049c
| 0.460444 | 4.116622 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/dcr_v29_v9_00_a/hdl/vhdl/or_gate.vhd
| 7 | 9,289 |
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2009/10/06 21:09:10 gburch Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- GAB 10-05-09 Removed reference to proc_common_v1_00_b and pulled
-- or_gate and or_muxcy into dcr library.
-- Updated copyright header
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library dcr_v29_v9_00_a;
use dcr_v29_v9_00_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Replaced with direct instantiation 10/5/09
--component or_muxcy
-- generic (
-- C_NUM_BITS : integer := 8
-- );
-- port (
-- In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
-- Or_out : out std_logic
-- );
--end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: entity dcr_v29_v9_00_a.or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
gpl-3.0
|
1936d68bbad16c700fca08b0011c42d3
| 0.416837 | 4.956777 | false | false | false | false |
luebbers/reconos
|
support/pcores/message_manager_v1_00_a/hdl/vhdl/fast_queue_tb.vhd
| 1 | 3,986 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:16:35 10/31/2006
-- Design Name: fast_queue
-- Module Name: C:/fast_queueProject/src/fast_queue_tb.vhd
-- Project Name: myProj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fast_queue
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY fast_queue_tb IS
END fast_queue_tb;
ARCHITECTURE behavior OF fast_queue_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fast_queue
generic(
ADDRESS_BITS : integer := 2;
DATA_BITS : integer := 32
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
add_busy : out std_logic;
remove_busy : out std_logic;
add : IN std_logic;
remove : IN std_logic;
entryToAdd : IN std_logic_vector(0 to 31);
headValid : INOUT std_logic;
full : INOUT std_logic;
empty : INOUT std_logic;
head : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL add : std_logic := '0';
SIGNAL remove : std_logic := '0';
SIGNAL entryToAdd : std_logic_vector(0 to 31) := (others=>'0');
--BiDirs
SIGNAL headValid : std_logic;
SIGNAL full : std_logic;
SIGNAL empty : std_logic;
signal add_busy : std_logic;
signal remove_busy : std_logic;
--Outputs
SIGNAL head : std_logic_vector(0 to 31);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fast_queue
GENERIC MAP(
ADDRESS_BITS => 2,
DATA_BITS => 32
)
PORT MAP(
clk => clk,
rst => rst,
add_busy => add_busy,
remove_busy => remove_busy,
add => add,
remove => remove,
entryToAdd => entryToAdd,
head => head,
headValid => headValid,
full => full,
empty => empty
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Place stimulus here
rst <= '1'; -- Reset the FIFO
wait for 20 ns;
rst <= '0';
wait for 20 ns;
entryToAdd <= x"1111_1111"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"2222_2222"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"3333_3333"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"4444_4444"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
entryToAdd <= x"5555_5555"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
clockProcess : PROCESS
BEGIN
clk <= '1'; -- clock cycle 10 ns
wait for 5 ns;
clk <= '0';
wait for 5 ns;
END PROCESS;
END;
|
gpl-3.0
|
84b52e714a4d124653810f5d42c15276
| 0.592323 | 3.033486 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/Stack/synth/Stack.vhd
| 1 | 6,818 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0_9;
USE dist_mem_gen_v8_0_9.dist_mem_gen_v8_0_9;
ENTITY Stack IS
PORT (
a : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END Stack;
ARCHITECTURE Stack_arch OF Stack IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Stack_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0_9 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0_9;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Stack_arch: ARCHITECTURE IS "dist_mem_gen_v8_0_9,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Stack_arch : ARCHITECTURE IS "Stack,dist_mem_gen_v8_0_9,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Stack_arch: ARCHITECTURE IS "Stack,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=10,C_DEFAULT_DATA=0,C_DEPTH=1024,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=no_coe_file_loaded,C_ELABORATION_DIR=./,C_MEM_TYPE=1,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=0,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=16,C_PARSER_TYPE=1}";
BEGIN
U0 : dist_mem_gen_v8_0_9
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 10,
C_DEFAULT_DATA => "0",
C_DEPTH => 1024,
C_HAS_CLK => 1,
C_HAS_D => 1,
C_HAS_DPO => 0,
C_HAS_DPRA => 0,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 1,
C_MEM_INIT_FILE => "no_coe_file_loaded",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 1,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 0,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 16,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => d,
dpra => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
clk => clk,
we => we,
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo
);
END Stack_arch;
|
mit
|
80d264963c9e4b57685ff5f72aeff6c0
| 0.641977 | 3.177074 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/AccelerometerCtl.vhd
| 1 | 6,366 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 15:00:45 03/04/2014
-- Design Name:
-- Module Name: AccelerometerCtl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This is the main module for the the Nexys4 onboard ADXL362 accelerometer.
-- The module consists of two components, AXDX362Ctrl and AccelArithmetics. The first one
-- configures the ADXL362 accelerometer and continuously reads X, Y, Z acceleration data and
-- temperature data in 12-bit two's complement format.
-- The data read is sent to the AccelArithmetics module that formats X and Y acceleration
-- data to be displayed on the VGA screen in a 512 X 512 pixel area. Therefore the X and Y
-- acceleration data will be scaled and limited to -1g: 0, 0g: 255, 1g: 511.
-- The AccelArithmetics module also determines the acceleration magnitude using the
-- SQRT (X^2 + Y^2 + Z^2) formula. The magnitude value is also displayed on the VGA screen.
-- To perform SQRT calculation a Logicore component is used.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AccelerometerCtl is
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
SCLK_FREQUENCY_HZ : integer := 1000000;
NUM_READS_AVG : integer := 16;
UPDATE_FREQUENCY_HZ : integer := 100
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Spi interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC;
-- Accelerometer data signals
ACCEL_X_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_Y_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_MAG_OUT : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_TMP_OUT : out STD_LOGIC_VECTOR (11 downto 0)
);
end AccelerometerCtl;
architecture Behavioral of AccelerometerCtl is
component ADXL362Ctrl
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
SCLK_FREQUENCY_HZ : integer := 1000000;
NUM_READS_AVG : integer := 16;
UPDATE_FREQUENCY_HZ : integer := 1000
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Accelerometer data signals
ACCEL_X : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Y : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Z : out STD_LOGIC_VECTOR (11 downto 0);
ACCEL_TMP : out STD_LOGIC_VECTOR (11 downto 0);
Data_Ready : out STD_LOGIC;
--SPI Interface Signals
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
SS : out STD_LOGIC
);
end component;
component AccelArithmetics
generic
(
SYSCLK_FREQUENCY_HZ : integer := 100000000;
ACC_X_Y_MAX : STD_LOGIC_VECTOR (9 downto 0) := "01" & X"FF"; -- 511 pixels, corresponding to +1g
ACC_X_Y_MIN : STD_LOGIC_VECTOR (9 downto 0) := (others => '0') -- corresponding to -1g
);
port
(
SYSCLK : in STD_LOGIC; -- System Clock
RESET : in STD_LOGIC;
-- Accelerometer data input signals
ACCEL_X_IN : in STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Y_IN : in STD_LOGIC_VECTOR (11 downto 0);
ACCEL_Z_IN : in STD_LOGIC_VECTOR (11 downto 0);
Data_Ready : in STD_LOGIC;
-- Accelerometer data output signals to be sent to the VGA controller
ACCEL_X_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_Y_OUT : out STD_LOGIC_VECTOR (8 downto 0);
ACCEL_MAG_OUT : out STD_LOGIC_VECTOR (11 downto 0)
);
end component;
-- Self-blocking reset counter constants
constant ACC_RESET_PERIOD_US : integer := 10;
constant ACC_RESET_IDLE_CLOCKS : integer := ((ACC_RESET_PERIOD_US*1000)/(1000000000/SYSCLK_FREQUENCY_HZ));
signal ACCEL_X : STD_LOGIC_VECTOR (11 downto 0);
signal ACCEL_Y : STD_LOGIC_VECTOR (11 downto 0);
signal ACCEL_Z : STD_LOGIC_VECTOR (11 downto 0);
signal Data_Ready : STD_LOGIC;
-- Self-blocking reset counter
signal cnt_acc_reset : integer range 0 to (ACC_RESET_IDLE_CLOCKS - 1):= 0;
signal RESET_INT: std_logic;
begin
-- Create the self-blocking reset counter
COUNT_RESET: process(SYSCLK, cnt_acc_reset, RESET)
begin
if SYSCLK'EVENT and SYSCLK = '1' then
if (RESET = '1') then
cnt_acc_reset <= 0;
RESET_INT <= '1';
elsif cnt_acc_reset = (ACC_RESET_IDLE_CLOCKS - 1) then
cnt_acc_reset <= (ACC_RESET_IDLE_CLOCKS - 1);
RESET_INT <= '0';
else
cnt_acc_reset <= cnt_acc_reset + 1;
RESET_INT <= '1';
end if;
end if;
end process COUNT_RESET;
ADXL_Control: ADXL362Ctrl
generic map
(
SYSCLK_FREQUENCY_HZ => SYSCLK_FREQUENCY_HZ,
SCLK_FREQUENCY_HZ => SCLK_FREQUENCY_HZ,
NUM_READS_AVG => NUM_READS_AVG,
UPDATE_FREQUENCY_HZ => UPDATE_FREQUENCY_HZ
)
port map
(
SYSCLK => SYSCLK,
RESET => RESET_INT,
-- Accelerometer data signals
ACCEL_X => ACCEL_X,
ACCEL_Y => ACCEL_Y,
ACCEL_Z => ACCEL_Z,
ACCEL_TMP => ACCEL_TMP_OUT,
Data_Ready => Data_Ready,
--SPI Interface Signals
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
SS => SS
);
Accel_Calculation: AccelArithmetics
GENERIC MAP
(
SYSCLK_FREQUENCY_HZ => 100000000,
ACC_X_Y_MAX => "01" & X"FF", -- 511 pixels, corresponding to +1g
ACC_X_Y_MIN => (others => '0') -- corresponding to -1g
)
PORT MAP
(
SYSCLK => SYSCLK,
RESET => RESET_INT,
-- Accelerometer data input signals
ACCEL_X_IN => ACCEL_X,
ACCEL_Y_IN => ACCEL_Y,
ACCEL_Z_IN => ACCEL_Z,
Data_Ready => Data_Ready,
-- Accelerometer data output signals to be sent to the VGA display
ACCEL_X_OUT => ACCEL_X_OUT,
ACCEL_Y_OUT => ACCEL_Y_OUT,
ACCEL_MAG_OUT => ACCEL_MAG_OUT
);
end Behavioral;
|
gpl-3.0
|
0b457c1ab10c388cdc504d03da39885f
| 0.619855 | 3.56439 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/user_processes/uf_resampling.vhd
| 1 | 12,009 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : R E S A M P L I N G
--
-- In many cases, this function does not have to be changed.
-- Only if you want/need to change/adjust the resampling algorithm
-- you can change it here.
--
-- Here the Residual Systematic Resampling Algorithm is used.
-- It is not easy to change to a complete other resampling algorithm,
-- because the framework is adjusted to use a algorithm, which
-- only uses one cycle of iterations and so without any correction cycle.
--
-- Some basic information about the resampling user function:
--
-- The particle weights are loaded into the local RAM by the Framework
-- The first 63 * 128 bytes (of 64 * 128 bytes) are filled with
-- all the particle weights needed. There will not be any space
-- between the particle weights.
--
-- The last 128 bytes are used for the resampling.
-- The user has to store two values for every particle.
-- 1. the index of the particle (as integer)
-- 2. the replication factor of the particle (as integer)
-- The ordering of this two values must not be changed,
-- because it is used later for the sampling step.
--
-- The two integer values (also known as index_type) are written
-- into the last 128 byte. Since two integer values need 8 bytes,
-- information about 16 particles can be written into the last 128 bytes
-- of the local ram before they have to be written by the Framework.
--
-- The outgoing signal write_burst has to be '1', if the the indexes
-- and replication factors should be written into the Main Memory.
-- This should only happen, if the information about 16
-- particles is resampled or the last particle has been resampled.
--
-- The incoming signal write_burst_done is equal to '1', if the
-- Framework has written the information to the Main Memory
--
-- If resampling is finished the outgoing signal finish has to be set to '1'.
-- A new run of the resampling will be started if the next particles are
-- loaded into local RAM. This is the case when the incoming signal
-- particles_loaded is equal to '1'.
--
------------------------------------------------------------------------------------
entity uf_resampling is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- additional incoming signals
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- additional outgoing signals
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_resampling;
architecture Behavioral of uf_resampling is
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- local RAM read/write address
signal local_ram_read_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_write_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- particle counter for allready resampled particles at all
signal counter_resampled_particles : integer := 0;
-- write counter (used bytes)
signal write_counter :integer := 0;
-- current particle weight
signal current_particle_weight : integer := 0;
-- signals needed for residual systematic resampling
signal temp : integer := 0;
signal fact : integer := 0; -- replication factor
signal U : integer := 0;
-- states
type t_state is (initialize,
load_particle_1, load_particle_2, load_weight,
calculate_replication_factor_1, calculate_replication_factor_2,
calculate_replication_factor_3, calculate_replication_factor_4,
calculate_replication_factor_5, calculate_replication_factor_6,
write_particle_index, write_particle_replication,
write_burst_decision, write_burst, write_burst_done_ack,
write_burst_done_ack_2, finish
);
-- current state
signal state : t_state := initialize;
begin
-- burst ram clock
o_RAMClk <= clk;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--
-- (0) initialize
--
-- i = 0; // current particle
-- j = 0; // current replication factor
-- k = 0; // current number of cloned particles
-- finished = 0;
--
--
-- (1) load particle and weight
--
-- load weight of i-th particle from local memory
-- i ++;
--
--
-- (2) calculate replication
--
-- calculate replication factor
--
--
-- (3) write particle index and replication
--
-- write particle index + replicationfactor to local ram
--
--
-- (4) write burst
--
-- write_burst = 1;
-- if (write_burst_done)
-- write_burst = 0;
-- go to step 4
--
--
-- (5) finished
--
-- finished = 1;
-- if (particles_loaded)
-- go to step 0;
--
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= initialize;
elsif rising_edge(clk) then
if init = '1' then
state <= initialize;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
U <= U_init;
elsif enable = '1' then
case state is
when initialize =>
--! init data
local_ram_read_address <= (others => '0');
local_ram_write_address <= write_address;
counter_resampled_particles <= 0;
counter <= start_particle_index;
current_particle_weight <= 0;
temp <= 0;
fact <= 0;
--U <= U_init;
write_counter <= 0;
written_values <= 0;
write_burst <= '0';
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
state <= load_particle_1;
end if;
when load_particle_1 =>
--! load a particle
write_burst <= '0';
if (number_of_particles <= counter_resampled_particles) then
state <= write_burst_decision;
else
o_RAMAddr <= local_ram_read_address;
state <= load_particle_2;
end if;
when load_particle_2 =>
--!needed because reading from local RAM needs two clock steps
state <= load_weight;
when load_weight =>
--! load particle weight
current_particle_weight <= TO_INTEGER(SIGNED(i_RAMData));
state <= calculate_replication_factor_1;
when calculate_replication_factor_1 =>
--! calculate replication factor (step 2/6)
temp <= current_particle_weight * number_of_particles_in_total;
state <= calculate_replication_factor_2;
when calculate_replication_factor_2 =>
--! calculate replication factor (step 2/6)
temp <= temp - U;
state <= calculate_replication_factor_3;
when calculate_replication_factor_3 =>
--! calculate replication factor (step 3/6)
fact <= temp + GRANULARITY;
state <= calculate_replication_factor_4;
when calculate_replication_factor_4 =>
--! calculate replication factor (step 4/6)
fact <= fact / GRANULARITY;
state <= calculate_replication_factor_5;
when calculate_replication_factor_5 =>
--! calculate replication factor (step 5/6)
U <= fact * GRANULARITY;
state <= calculate_replication_factor_6;
when calculate_replication_factor_6 =>
--! calculate replication factor (step 6/6)
U <= U - temp;
state <= write_particle_index;
-- todo: change back
--state <= write_burst_decision;
when write_particle_index =>
--! read particle from local ram
-- copy particle_size / 32 from local RAM to local RAM
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(counter, C_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
state <= write_particle_replication;
when write_particle_replication =>
--! needed because reading takes 2 clock steps
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(fact, C_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
write_counter <= write_counter + 1;
state <= write_burst_decision;
when write_burst_decision =>
--! write burst to main memory
o_RAMWE <= '0';
if (16 <= write_counter) then
-- write burst
state <= write_burst;
-- todo change back
--state <= write_burst_decision;
write_counter <= 0;
local_ram_write_address <= write_address;
written_values <= 16;
elsif (number_of_particles <= counter_resampled_particles and write_counter > 0) then
-- write burst
state <= write_burst;
--todo: changed back
--state <= write_burst_decision;
write_counter <= 0;
--write_burst <= '1';
written_values <= write_counter;
elsif (number_of_particles <= counter_resampled_particles) then
state <= finish;
else
-- get next particle
counter <= counter + 1;
counter_resampled_particles <= counter_resampled_particles + 1;
local_ram_read_address <= local_ram_read_address + 1;
state <= load_particle_1;
end if;
when write_burst =>
--! write burst to main memory
--write_burst <= '1';
--written_values <= write_counter;
write_burst <= '1';
write_burst_done_ack <= '0';
--change back
--write_counter <= 0;
if (write_burst_done = '1') then
write_burst <= '0';
state <= write_burst_done_ack;
end if;
when write_burst_done_ack =>
--! write burst to main memory
write_burst_done_ack <= '1';
write_counter <= 0;
write_burst <= '0';
if (write_burst_done = '0') then
state <= write_burst_done_ack_2;
end if;
when write_burst_done_ack_2 =>
--! write burst to main memory
write_burst_done_ack <= '0';
if (number_of_particles <= counter_resampled_particles) then
state <= finish;
else
--todo: changed for hopefully good
--state <= load_particle_1;
state <= write_burst_decision;
end if;
when finish =>
--! write finished signal
write_burst <= '0';
finished <= '1';
if (particles_loaded = '1') then
state <= initialize;
end if;
when others =>
state <= initialize;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
f7f80ea4885715cf08982d7aa6f434db
| 0.607877 | 3.634685 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/DRAM/DRAM_fifo.vhd
| 1 | 47,090 |
---------------------------------------------------------------------------
--
-- Module : DRAM_fifo.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Asynchronous FIFO implemented in Distributed RAM
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_bit.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fifo_u.all;
use work.DRAM_fifo_pkg.all;
entity DRAM_fifo is
generic (
DRAM_DEPTH : integer := 16; -- FIFO depth, default is 16,
-- allowable values are 16, 32,
-- 64, 128.
WR_DWIDTH : integer := 32; -- FIFO write data width,
-- allowable values are 8, 16,
-- 32, 64, 128.
RD_DWIDTH : integer := 32; -- FIFO read data width,
-- allowable values are 8, 16,
-- 32, 64, 128.
WR_REM_WIDTH : integer := 2; -- log2(WR_DWIDTH/8)
RD_REM_WIDTH : integer := 2; -- log2(RD_DWIDTH/8)
USE_LENGTH : boolean := true;
glbtm : time := 1 ns -- Assignment delay for simulation
);
port (
-- Reset
FIFO_GSR_IN : in std_logic;
-- Clocks
WRITE_CLOCK_IN : in std_logic;
READ_CLOCK_IN : in std_logic;
-- Sink Interface: standard signals for reading data from a FIFO
READ_DATA_OUT : out std_logic_vector(RD_DWIDTH-1 downto 0);
READ_REM_OUT : out std_logic_vector(RD_REM_WIDTH-1 downto 0);
READ_SOF_OUT_N : out std_logic;
READ_EOF_OUT_N : out std_logic;
DATA_VALID_OUT : out std_logic;
READ_ENABLE_IN : in std_logic;
-- Source Interface: standard signals for writing data to a FIFO
WRITE_DATA_IN : in std_logic_vector(WR_DWIDTH-1 downto 0);
WRITE_REM_IN : in std_logic_vector(WR_REM_WIDTH-1 downto 0);
WRITE_SOF_IN_N : in std_logic;
WRITE_EOF_IN_N : in std_logic;
WRITE_ENABLE_IN : in std_logic;
-- FIFO status signals
FIFOSTATUS_OUT : out std_logic_vector(3 downto 0);
FULL_OUT : out std_logic;
EMPTY_OUT : out std_logic;
-- Length Control
LEN_OUT : out std_logic_vector(15 downto 0);
LEN_RDY_OUT : out std_logic;
LEN_ERR_OUT : out std_logic);
end DRAM_fifo;
architecture DRAM_fifo_hdl of DRAM_fifo is
-- Constants Related to FIFO Width parameters for Data
constant MEM_IDX : integer := SQUARE2(DRAM_DEPTH);
constant RD_ADDR_WIDTH : integer := GET_WIDTH(MEM_IDX,RD_DWIDTH,WR_DWIDTH,1,0);
constant WR_ADDR_WIDTH : integer := GET_WIDTH(MEM_IDX,RD_DWIDTH,WR_DWIDTH,1,1);
constant RD_ADDR_MINOR_WIDTH : integer := GET_WIDTH(MEM_IDX, RD_DWIDTH, WR_DWIDTH, 2, 0);
constant WR_ADDR_MINOR_WIDTH : integer := GET_WIDTH(MEM_IDX, RD_DWIDTH, WR_DWIDTH, 2, 1);
constant MAX_WIDTH: integer := GET_MAX_WIDTH(RD_DWIDTH, WR_DWIDTH);
constant WRDW_div_RDDW: integer := GET_WRDW_div_RDDW(RD_DWIDTH, WR_DWIDTH);
--Constants Related to FIFO Width parameters for Control
constant CTRL_WIDTH: integer := GET_CTRL_WIDTH(RD_REM_WIDTH, WR_REM_WIDTH, RD_DWIDTH, WR_DWIDTH);
constant REM_SEL_HIGH_VALUE : integer := GET_HIGH_VALUE(RD_REM_WIDTH,WR_REM_WIDTH);
type rd_data_vec_type is array(0 to 2**RD_ADDR_MINOR_WIDTH-1) of std_logic_vector(RD_DWIDTH-1 downto 0);
type rd_rem_vec_type is array(0 to 2**RD_ADDR_MINOR_WIDTH-1) of std_logic_vector(RD_REM_WIDTH-1 downto 0);
constant RD_MINOR_HIGH : integer := POWER2(RD_ADDR_MINOR_WIDTH);
constant REM_SEL_HIGH1 : integer := POWER2(REM_SEL_HIGH_VALUE);
constant WR_MINOR_HIGH : integer := POWER2(WR_ADDR_MINOR_WIDTH);
constant LEN_IFACE_SIZE: integer := 16; -- Length count is a std_logic_vec
-- of 16 bits by default.
-- User may change size.
constant LEN_COUNT_SIZE: integer := 14;
-- length control constants
constant BYTE_NUM_PER_WORD: integer := WR_DWIDTH/8;
signal rd_clk: std_logic;
signal wr_clk: std_logic;
signal rd_en: std_logic;
signal wr_en: std_logic;
signal fifo_gsr: std_logic;
signal rd_data: std_logic_vector(RD_DWIDTH-1 downto 0);
signal wr_data: std_logic_vector(WR_DWIDTH-1 downto 0);
-- Control RAM signals --
signal rd_rem: std_logic_vector(RD_REM_WIDTH-1 downto 0);
signal wr_rem: std_logic_vector(WR_REM_WIDTH-1 downto 0);
signal wr_sof_n: std_logic;
signal wr_eof_n: std_logic;
signal wr_sof_n_p: std_logic;
signal wr_eof_n_p: std_logic;
signal rd_sof_n: std_logic;
signal rd_eof_n: std_logic;
signal ctrl_wr_buf: std_logic_vector(CTRL_WIDTH-1 downto 0);
-------------------------
signal full: std_logic;
signal empty: std_logic;
signal rd_addr: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal rd_addr_minor: std_logic_vector(RD_ADDR_MINOR_WIDTH-1 downto 0);
signal read_addrgray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal read_nextgray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal read_lastgray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal wr_addr: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal wr_addr_i: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal wr_addr_minor: std_logic_vector(WR_ADDR_MINOR_WIDTH-1 downto 0);
signal wr_addr_minor_p: std_logic_vector(WR_ADDR_MINOR_WIDTH-1 downto 0);
signal wr_addrgray: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal wr_addrgray_i: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal write_nextgray: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal write_nextgray_i: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal fifostatus: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal rd_allow: std_logic;
signal rd_allow_minor: std_logic;
signal wr_allow: std_logic;
signal wr_allow_i: std_logic;
signal wr_allow_p: std_logic;
signal wr_allow_minor: std_logic;
signal wr_allow_minor_p: std_logic;
signal wr_allow_flag: std_logic;
signal full_allow: std_logic;
signal empty_allow: std_logic;
signal emptyg: std_logic;
signal fullg: std_logic;
signal ecomp: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal fcomp: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal emuxcyo: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal fmuxcyo: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal read_truegray: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal rag_writesync: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal ra_writesync: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal wr_addrr: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal gnd: std_logic;
signal pwr: std_logic;
signal data_valid: std_logic;
-- Temp signals --
signal rd_temp: std_logic_vector(MAX_WIDTH-1 downto 0);
signal rd_buf: std_logic_vector(MAX_WIDTH-1 downto 0);
signal rd_data_p: rd_data_vec_type;
signal wr_buf: std_logic_vector(MAX_WIDTH-1 downto 0);
signal min_addr1: integer := 0;
signal rem_sel1 : integer := 0;
signal rem_sel2: integer := 0;
-- Length Control FIFO --
signal wr_len: std_logic_vector(LEN_IFACE_SIZE downto 0);
signal wr_len_r: std_logic_vector(LEN_IFACE_SIZE downto 0);
signal wr_len_p: std_logic_vector(LEN_IFACE_SIZE downto 0);
signal rd_len: std_logic_vector(LEN_IFACE_SIZE downto 0);
signal rd_len_temp: std_logic_vector(LEN_IFACE_SIZE downto 0);
signal len_byte_cnt: std_logic_vector(LEN_COUNT_SIZE+3 downto 0);
signal len_byte_cnt_plus_rem: std_logic_vector(LEN_COUNT_SIZE+3 downto 0);
signal len_word_cnt: std_logic_vector(LEN_COUNT_SIZE-1 downto 0);
signal len_wr_allow: std_logic;
signal len_wr_allow_r: std_logic;
signal len_wr_allow_p: std_logic;
signal len_rd_allow: std_logic;
signal len_wr_addr: std_logic_vector(WR_ADDR_WIDTH-1 downto 0);
signal len_rd_addr: std_logic_vector(RD_ADDR_WIDTH-1 downto 0);
signal rd_len_rdy: std_logic;
signal wr_rem_plus_one: std_logic_vector(WR_REM_WIDTH downto 0);
signal len_byte_cnt_plus_rem_with_carry : std_logic_vector(LEN_COUNT_SIZE+4 downto 0);
signal total_len_byte_cnt_with_carry : std_logic_vector(LEN_COUNT_SIZE+4 downto 0);
signal len_word_cnt_with_carry : std_logic_vector(LEN_COUNT_SIZE downto 0);
signal len_byte_cnt_with_carry: std_logic_vector(LEN_COUNT_SIZE+4 downto 0);
signal carry1, carry2, carry3, carry4 : std_logic;
signal len_counter_overflow : std_logic;
signal inframe: std_logic;
signal inframe_i: std_logic;
component MUXCY_L
port (
DI: in std_logic;
CI: in std_logic;
S: in std_logic;
LO: out std_logic);
end component;
begin
rd_clk <= READ_CLOCK_IN;
wr_clk <= WRITE_CLOCK_IN;
fifo_gsr <= FIFO_GSR_IN;
wr_en <= WRITE_ENABLE_IN;
wr_data <= revByteOrder(WRITE_DATA_IN);
wr_rem <= WRITE_REM_IN;
wr_sof_n <= WRITE_SOF_IN_N;
wr_eof_n <= WRITE_EOF_IN_N;
rd_en <= READ_ENABLE_IN;
READ_DATA_OUT <= revByteOrder(rd_data);
READ_REM_OUT <= rd_rem;
READ_SOF_OUT_N <= rd_sof_n;
READ_EOF_OUT_N <= rd_eof_n;
EMPTY_OUT <= empty;
FULL_OUT <= full;
FIFOSTATUS_OUT <= fifostatus(WR_ADDR_WIDTH-1 downto WR_ADDR_WIDTH-4);
DATA_VALID_OUT <= data_valid;
min_addr1 <= slv2int(rd_addr_minor);
gnd <= '0';
pwr <= '1';
-------------------------------------------------------------------------------
------------------------------INFRAME signal generation------------------------
-- This signal is used as a flag to indicate whether the incoming data are --
-- part of a frame. Since LL_FIFO is a packet FIFO so it will only store --
-- packets, not random data without frame delimiter. If the data is not --
-- part of the frame, it will be dropped. The inframe_i signal will be --
-- assert the cycle after the sof_n asserts. If the frame is only a cycle --
-- long then inframe_i signal won't be asserted for that particular frame to--
-- prevent misleading information. However, the inframe signal will include --
-- wr_sof_n to give the accurate status of the frame, and which will be used--
-- for wr_allow. --
-------------------------------------------------------------------------------
inframe_i_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
inframe_i <= '0';
elsif (wr_clk'EVENT and wr_clk = '1') then
if WR_DWIDTH >= RD_DWIDTH then
if inframe_i = '0' then
inframe_i <= wr_allow and not wr_sof_n and wr_eof_n after glbtm;
elsif (inframe_i = '1' and wr_allow = '1' and wr_eof_n = '0') then
inframe_i <= '0' after glbtm;
end if;
else
if inframe_i = '0' then
inframe_i <= wr_allow_minor and not wr_sof_n and wr_eof_n after glbtm;
elsif (inframe_i = '1' and wr_allow_minor = '1' and wr_eof_n = '0') then
inframe_i <= '0' after glbtm;
end if;
end if;
end if;
end process inframe_i_proc;
inframe <= not wr_sof_n or inframe_i;
----------------------------------------------------------------
------------------ALLOW signal generation-----------------------
-- Allow flags determine whether FifO control logic can --
-- operate. If rd_en is driven high, and the FifO is --
-- not empty, then Reads are allowed. Similarly, if the --
-- wr_en signal is high, and the FifO is not FULL_OUT, --
-- then Writes are allowed. --
-- --
----------------------------------------------------------------
gen1: if RD_DWIDTH < WR_DWIDTH generate
begin
rd_allow_minor <= (rd_en and not empty);
rd_allow <= rd_allow_minor when allOnes(rd_addr_minor) else '0';
wr_allow <= (wr_en and not full) and inframe;
full_allow <= (full or wr_en);
empty_allow <= rd_en or empty when allOnes(rd_addr_minor) else empty ;
end generate gen1;
gen2: if RD_DWIDTH > WR_DWIDTH generate
rd_allow <= (rd_en and not empty);
empty_allow <= (empty or rd_en);
wr_allow_minor <= (wr_en and not full) and inframe;
wr_allow_i <= wr_allow_minor and (boolean_to_std_logic(allOnes(wr_addr_minor)) or not wr_eof_n);
full_allow <= wr_allow or full;
-------------------------------------------------------------------------------
-----------------------------WR_ALLOW GENERATION-------------------------------
-- The wr_allow_flag signal is use to assert wr_allow when fifo is not full --
-- when wr_allow was high during fifo was full. When the fifo is --
-- full, we must stop writing into the FIFO, so wr_allow must deasserts --
-- immediately so that the address won't increment until the fifo is not --
-- full. If we don't have the wr_allow_flag signal, the write address will --
-- not increment when fifo is not full anymore but will when new data is --
-- coming in, which cause data drop. --
-------------------------------------------------------------------------------
proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_allow_p <= '0';
wr_allow_flag <= '0';
wr_sof_n_p <= '0';
wr_eof_n_p <= '0';
wr_allow_minor_p <= '0';
elsif (wr_clk'EVENT and wr_clk = '1') then
wr_allow_p <= wr_allow_i after glbtm;
wr_sof_n_p <= wr_sof_n after glbtm;
wr_eof_n_p <= wr_eof_n after glbtm;
wr_allow_minor_p <= wr_allow_minor after glbtm;
if full = '1' then
if wr_allow_p = '1' then
wr_allow_flag <= wr_allow_p after glbtm;
else
wr_allow_flag <= wr_allow_flag after glbtm;
end if;
else
wr_allow_flag <= '0' after glbtm;
end if;
end if;
end process proc;
wr_allow <= (wr_allow_p or wr_allow_flag) and not full;
end generate gen2;
gen3: if RD_DWIDTH = WR_DWIDTH generate
wr_allow <= (wr_en and not full) and inframe;
rd_allow <= (rd_en and not empty);
empty_allow <= (empty or rd_en);
full_allow <= wr_en or full;
end generate gen3;
-------------------------------------------------------------------------------
--_____________________________The Data Valid Signal___________________________
-- The data valid signal is asserted when the data coming out of the FIFO is
-- data that was put there by the source, and not just garbage from the FIFO's
-- memory. Moreover, when sink and source datawidths are different, the data
-- valid signal must tell what part of data is valid and what is not depending
-- on the frame delimiter. Therefore, the src_rdy_n signal greatly depend on
-- this.
-------------------------------------------------------------------------------
data_valid_gen1: if RD_DWIDTH < WR_DWIDTH generate
data_valid_proc1: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
data_valid <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow_minor = '1') then
if (min_addr1 /= 0 and rd_eof_n = '0') then --RD_MINOR_HIGH-1
data_valid <= '0' after glbtm;
else
if data_valid = '0' and min_addr1 /= 0 then
data_valid <= '0' after glbtm;
else
data_valid <= '1' after glbtm;
end if;
end if;
--should extend data_valid when user halts read, do this when FIFO still contains data
elsif data_valid = '1' and (empty = '0' or rd_eof_n = '0') then
data_valid <= '1' after glbtm;
else
data_valid <= '0' after glbtm;
end if;
end if;
end process data_valid_proc1;
end generate data_valid_gen1;
data_valid_gen2: if RD_DWIDTH > WR_DWIDTH generate
data_valid_proc2: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
data_valid <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
if rd_en = '0' and data_valid = '1' then -- should extend data_valid when user halts read,
-- so data won't get lost.
data_valid <= '1' after glbtm;
else
data_valid <= rd_allow after glbtm;
end if;
end if;
end process data_valid_proc2;
end generate data_valid_gen2;
data_valid_gen3: if RD_DWIDTH = WR_DWIDTH generate
data_valid_proc3: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
data_valid <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
if rd_en = '0' and data_valid = '1' then
data_valid <= '1' after glbtm;
else
data_valid <= rd_allow after glbtm;
end if;
end if;
end process data_valid_proc3;
end generate data_valid_gen3;
DRAM_macro_inst: DRAM_macro
generic map (
DRAM_DEPTH => DRAM_DEPTH,
-- allowable values are 16, 32,
-- 64, 128.
WR_DWIDTH => WR_DWIDTH,
--Allowed: 8, 16, 32, 64
RD_DWIDTH => RD_DWIDTH,
--Allowed: 8, 16, 32, 64
WR_REM_WIDTH => WR_REM_WIDTH,
RD_REM_WIDTH => RD_REM_WIDTH,
RD_ADDR_MINOR_WIDTH => RD_ADDR_MINOR_WIDTH,
RD_ADDR_WIDTH => RD_ADDR_WIDTH,
WR_ADDR_MINOR_WIDTH => WR_ADDR_MINOR_WIDTH,
WR_ADDR_WIDTH => WR_ADDR_WIDTH,
CTRL_WIDTH => CTRL_WIDTH,
glbtm => glbtm )
port map(
-- Reset
fifo_gsr => fifo_gsr,
-- clocks -- clocks
wr_clk => wr_clk,
rd_clk => rd_clk,
rd_allow => rd_allow,
rd_allow_minor => rd_allow_minor,
rd_addr_minor => rd_addr_minor,
rd_addr => rd_addr,
rd_data => rd_data,
rd_rem => rd_rem,
rd_sof_n => rd_sof_n,
rd_eof_n => rd_eof_n,
wr_allow => wr_allow,
wr_allow_minor => wr_allow_minor,
wr_allow_minor_p => wr_allow_minor_p,
wr_addr => wr_addr,
wr_addr_minor => wr_addr_minor,
wr_data => wr_data,
wr_rem => wr_rem,
wr_sof_n => wr_sof_n,
wr_eof_n => wr_eof_n,
wr_sof_n_p => wr_sof_n_p,
wr_eof_n_p => wr_eof_n_p,
ctrl_wr_buf => ctrl_wr_buf );
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- Length Control FIFO --
--------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------Distributed SelectRAM port mapping-----------------------
-- It uses up to 512 deep RAM, in which 64 and lower are horizontally --
-- cascaded primitives and 128 and up are macro of 64 deep RAM. --
-------------------------------------------------------------------------------
DRAMgen1: if DRAM_DEPTH = 16 generate
begin
-- Length Control RAM --
len_gen1: if USE_LENGTH = true generate
len_DRAM_gen1: for i in 0 to LEN_IFACE_SIZE generate
D_RAM1: RAM16X1D port map (
D => wr_len(i),
WE => pwr,
WCLK => wr_clk,
A0 => len_wr_addr(0),
A1 => len_wr_addr(1),
A2 => len_wr_addr(2),
A3 => len_wr_addr(3),
DPRA0 => len_rd_addr(0),
DPRA1 => len_rd_addr(1),
DPRA2 => len_rd_addr(2),
DPRA3 => len_rd_addr(3),
DPO => rd_len(i),
SPO => rd_len_temp(i));
end generate len_DRAM_gen1;
end generate len_gen1;
end generate DRAMgen1;
DRAMgen2: if DRAM_DEPTH = 32 generate
begin
-- Length Control RAM --
len_gen11: if USE_LENGTH = true generate
len_DRAM_gen2: for i in 0 to LEN_IFACE_SIZE generate
D_RAM1: RAM32X1D port map (
D => wr_len(i),
WE => pwr,
WCLK => wr_clk,
A0 => len_wr_addr(0),
A1 => len_wr_addr(1),
A2 => len_wr_addr(2),
A3 => len_wr_addr(3),
A4 => len_wr_addr(4),
DPRA0 => len_rd_addr(0),
DPRA1 => len_rd_addr(1),
DPRA2 => len_rd_addr(2),
DPRA3 => len_rd_addr(3),
DPRA4 => len_rd_addr(4),
DPO => rd_len(i),
SPO => rd_len_temp(i));
end generate len_DRAM_gen2;
end generate len_gen11;
end generate DRAMgen2;
DRAMgen3: if DRAM_DEPTH = 64 generate
begin
-- Length Control RAM --
len_gen2: if USE_LENGTH = true generate
len_DRAM_gen3: for i in 0 to LEN_IFACE_SIZE generate
D_RAM1: RAM64X1D port map (
D => wr_len(i),
WE => pwr,
WCLK => wr_clk,
A0 => len_wr_addr(0),
A1 => len_wr_addr(1),
A2 => len_wr_addr(2),
A3 => len_wr_addr(3),
A4 => len_wr_addr(4),
A5 => len_wr_addr(5),
DPRA0 => len_rd_addr(0),
DPRA1 => len_rd_addr(1),
DPRA2 => len_rd_addr(2),
DPRA3 => len_rd_addr(3),
DPRA4 => len_rd_addr(4),
DPRA5 => len_rd_addr(5),
DPO => rd_len(i),
SPO => rd_len_temp(i));
end generate len_DRAM_gen3;
end generate len_gen2;
end generate DRAMgen3;
DRAMgen4: if DRAM_DEPTH = 128 generate
begin
-- Length Control RAM --
len_gen4: if USE_LENGTH = true generate
len_DRAM_gen4: for i in 0 to LEN_IFACE_SIZE generate
D_RAM1: RAM_64nX1
generic map(2, 7)
port map (
DI => wr_len(i),
WEn => pwr,
WCLK => wr_clk,
Ad => len_wr_addr(6 downto 0),
DRA => len_rd_addr(6 downto 0),
DO => rd_len(i),
SO => open);
end generate len_DRAM_gen4;
end generate len_gen4;
end generate DRAMgen4;
DRAMgen5: if DRAM_DEPTH = 256 generate
begin
-- Length Control RAM --
len_gen5: if USE_LENGTH = true generate
len_DRAM_gen5: for i in 0 to LEN_IFACE_SIZE generate
D_RAM1: RAM_64nX1
generic map(4, 8)
port map (
DI => wr_len(i),
WEn => pwr,
WCLK => wr_clk,
Ad => len_wr_addr(7 downto 0),
DRA => len_rd_addr(7 downto 0),
DO => rd_len(i));
end generate len_DRAM_gen5;
end generate len_gen5;
end generate DRAMgen5;
DRAMgen6: if DRAM_DEPTH = 512 generate
begin
-- Length Control RAM --
len_gen6: if USE_LENGTH = true generate
len_DRAM_gen6: for i in 0 to LEN_IFACE_SIZE generate
D_RAM1: RAM_64nX1
generic map(8, 9)
port map (
DI => wr_len(i),
WEn => pwr,
WCLK => wr_clk,
Ad => len_wr_addr(8 downto 0),
DRA => len_rd_addr(8 downto 0),
DO => rd_len(i));
end generate len_DRAM_gen6;
end generate len_gen6;
end generate DRAMgen6;
use_length_gen1: if USE_LENGTH = false generate
---------------------------------------------------------------------------
-- When the user does not want to use the Length FIFO, the output of --
-- the length count will always be zero and the len_rdy signal will --
-- always be asserted. --
---------------------------------------------------------------------------
LEN_OUT <= (others => '0');
LEN_RDY_OUT <= '0';
LEN_ERR_OUT <= '0';
end generate use_length_gen1;
use_length_gen2 : if USE_LENGTH = true generate
---------------------------------------------------------------------------
-- Calculating the number of bytes being written into the FIFO (wr_len) --
-- the length counter (len_count) is incremented every cycle when a --
-- valid data is received and when it's not the end of the frame, that --
-- is, wr_eof_n is not equal to '0'. However, since the length count --
-- is always a cycle late and we are writing the length into the length --
-- FIFO at the same cycle as when wr_eof_n asserts. So the --
-- combinatorial logic that finalize the counting of byte length will --
-- add one more word to the calculation to make up for it. --
---------------------------------------------------------------------------
LEN_A_GEN: if WR_DWIDTH >= RD_DWIDTH generate
len_wr_allow_r <= wr_allow and (not wr_eof_n);
len_rd_allow <= rd_len_rdy;
-- calculate data bytes in remainder
wr_rem_plus_one <= '0' & wr_rem + '1';
-- add data bytes in remainder into length byte count
len_byte_cnt_plus_rem_with_carry <= '0' & len_byte_cnt + wr_rem_plus_one;
len_byte_cnt_plus_rem <= len_byte_cnt_plus_rem_with_carry(LEN_COUNT_SIZE+3 downto 0);
carry2 <= len_byte_cnt_plus_rem_with_carry(LEN_COUNT_SIZE+4);
-- calculate total length byte count by adding one more data beats at certain condition
-- to compensate for SOF data bytes,
total_len_byte_cnt_with_carry <= '0' & len_byte_cnt_plus_rem when wr_sof_n = '0' and len_wr_allow_r = '1' else
'0' & len_byte_cnt_plus_rem + conv_std_logic_vector(BYTE_NUM_PER_WORD, 5)
when wr_sof_n = '1' and len_wr_allow_r = '1' else
(others => '0');
-- Prepare the data to write into Length FIFO
wr_len_r(LEN_IFACE_SIZE) <= not wr_eof_n when wr_allow = '1' else '0';
wr_len_r(LEN_IFACE_SIZE-1 downto 0) <= total_len_byte_cnt_with_carry(LEN_IFACE_SIZE-1 downto 0);
carry1 <= not boolean_to_std_logic(allZeroes(total_len_byte_cnt_with_carry(LEN_COUNT_SIZE+4 downto LEN_IFACE_SIZE)));
end generate LEN_A_GEN;
LEN_B_GEN: if WR_DWIDTH < RD_DWIDTH generate
len_wr_allow_r <= wr_allow_minor_p and (not wr_eof_n_p);
len_rd_allow <= rd_len_rdy;
-- calculate data bytes in remainder
wr_rem_gen0: if WR_DWIDTH /= 8 generate
wr_rem_plus_one <= '0' & ctrl_wr_buf(WR_REM_WIDTH-1 downto 0) + '1';
end generate;
wr_rem_gen1: if WR_DWIDTH = 8 generate
wr_rem_plus_one <= conv_std_logic_vector(1, WR_REM_WIDTH+1);
end generate;
-- add data bytes in remainder into length byte count
len_byte_cnt_plus_rem_with_carry <= '0' & len_byte_cnt + wr_rem_plus_one;
len_byte_cnt_plus_rem <= len_byte_cnt_plus_rem_with_carry(LEN_COUNT_SIZE+3 downto 0);
carry2 <= len_byte_cnt_plus_rem_with_carry(LEN_COUNT_SIZE+4);
-- calculate total length byte count by adding one more data beats at certain condition
-- to compensate for SOF data bytes,
total_len_byte_cnt_with_carry <= '0' & len_byte_cnt_plus_rem when wr_sof_n_p = '0' and len_wr_allow_r = '1'
else '0' & len_byte_cnt_plus_rem + conv_std_logic_vector(BYTE_NUM_PER_WORD, 5)
when wr_sof_n_p = '1' and len_wr_allow_r = '1' else
(others => '0');
-- Prepare the data to write into Length FIFO
wr_len_r(LEN_IFACE_SIZE)<=not wr_eof_n_p when wr_allow_minor_p='1' else '0';
wr_len_r(LEN_IFACE_SIZE-1 downto 0) <= total_len_byte_cnt_with_carry(LEN_IFACE_SIZE-1 downto 0);
carry1 <= not boolean_to_std_logic(allZeroes(total_len_byte_cnt_with_carry(LEN_COUNT_SIZE+4 downto LEN_IFACE_SIZE)));
end generate LEN_B_GEN;
process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
LEN_OUT <= (others => '0');
LEN_RDY_OUT <= '0';
elsif (rd_clk'EVENT and rd_clk = '1') then
LEN_OUT <= rd_len(LEN_IFACE_SIZE-1 downto 0) after glbtm;
LEN_RDY_OUT <= rd_len_rdy after glbtm;
end if;
end process;
LEN_ERR_OUT <= '0';
rd_len_rdy <= rd_len(LEN_IFACE_SIZE);
---------------------------------------------------------------------------
-- Pipeline the wr_len and wr_len_rdy, and detect counter overflow
---------------------------------------------------------------------------
len_pipeline_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_counter_overflow <= '0' after glbtm;
len_wr_allow <= '0' after glbtm;
wr_len <= (others => '0') after glbtm;
elsif (wr_clk'EVENT and wr_clk = '1') then
len_wr_allow <= len_wr_allow_p after glbtm;
wr_len(LEN_IFACE_SIZE-1 downto 0) <=
bit_duplicate(len_counter_overflow ,LEN_IFACE_SIZE) or
wr_len_p(LEN_IFACE_SIZE-1 downto 0) after glbtm;
wr_len(LEN_IFACE_SIZE) <= wr_len_p(LEN_IFACE_SIZE) after glbtm;
if (WR_DWIDTH >= RD_DWIDTH) then
if (wr_sof_n = '0') then
len_counter_overflow <= '0' after glbtm;
elsif (carry1 = '1' or carry2 = '1' or carry3 = '1' or carry4 = '1') then
len_counter_overflow <= '1' after glbtm;
end if;
else
if (wr_sof_n = '0') then
len_counter_overflow <= '0' after glbtm;
elsif (carry1 = '1' or carry2 = '1' or carry3 = '1' or carry4 = '1') then
len_counter_overflow <= '1' after glbtm;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Need to pipeline the stage so it can align with the counter overflow --
-- signal. --
---------------------------------------------------------------------------
wr_len_pipline_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_len_p <= (others => '0');
len_wr_allow_p <= '0';
elsif (wr_clk'EVENT and wr_clk = '1') then
wr_len_p <= wr_len_r after glbtm;
len_wr_allow_p <= len_wr_allow_r after glbtm;
end if;
end process wr_len_pipline_proc;
---------------------------------------------------------------------------
len_word_cnt <= len_word_cnt_with_carry(LEN_COUNT_SIZE-1 downto 0);
carry4 <= len_word_cnt_with_carry(LEN_COUNT_SIZE);
len_byte_cnt <= len_byte_cnt_with_carry(LEN_COUNT_SIZE+3 downto 0);
carry3 <= len_byte_cnt_with_carry(LEN_COUNT_SIZE+4);
-- only counts data beats between SOF/EOF
len_counter_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_word_cnt_with_carry <= (others => '0'); -- unit is words
len_byte_cnt_with_carry <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (WR_DWIDTH >= RD_DWIDTH) then
if (wr_allow = '1') then
if (wr_sof_n = '0' or wr_eof_n = '0') then
len_word_cnt_with_carry <= (others => '0') after glbtm;
len_byte_cnt_with_carry <= (others => '0') after glbtm;
else
len_word_cnt_with_carry <= '0' & len_word_cnt + '1' after glbtm;
len_byte_cnt_with_carry <= conv_std_logic_vector
(slv2int(len_word_cnt)*BYTE_NUM_PER_WORD, LEN_COUNT_SIZE + 5 ) +
conv_std_logic_vector(BYTE_NUM_PER_WORD, 5)
after glbtm;
end if;
end if;
elsif (WR_DWIDTH < RD_DWIDTH) then
if (wr_allow_minor_p = '1') then
if (wr_sof_n_p = '0' or wr_eof_n_p = '0') then
len_word_cnt_with_carry <= (others => '0') after glbtm;
len_byte_cnt_with_carry <= (others => '0') after glbtm;
else
len_word_cnt_with_carry <= '0' & len_word_cnt + '1' after glbtm;
len_byte_cnt_with_carry <= conv_std_logic_vector
(slv2int(len_word_cnt)* BYTE_NUM_PER_WORD, LEN_COUNT_SIZE + 5 ) +
conv_std_logic_vector(BYTE_NUM_PER_WORD, 5)
after glbtm;
end if;
end if;
end if;
end if;
end process len_counter_proc;
---------------------------------------------------------------------------
inc_len_wr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_wr_addr <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (len_wr_allow = '1') then
len_wr_addr <= len_wr_addr + '1' after glbtm;
end if;
end if;
end process inc_len_wr_proc;
inc_len_rd_addr_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
len_rd_addr <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (len_rd_allow = '1') then
len_rd_addr <= len_rd_addr + '1' after glbtm;
end if;
end if;
end process inc_len_rd_addr_proc;
end generate use_length_gen2;
--------------------------------------------------------------------------
empty_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
empty <= '1';
elsif (rd_clk'EVENT and rd_clk = '1') then
if (empty_allow = '1') then
empty <= emptyg after glbtm;
end if;
end if;
end process empty_proc;
full_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
full <= '0';
elsif (wr_clk'EVENT and wr_clk = '1') then
if (full_allow = '1') then
full <= fullg after glbtm;
end if;
end if;
end process full_proc;
------------------------------------------------------------------------------------
inc_rd_addr_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_addr <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
rd_addr <= rd_addr + '1' after glbtm;
end if;
end if;
end process inc_rd_addr_proc;
gray_conv_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_nextgray(RD_ADDR_WIDTH-1) <= '1';
read_nextgray(RD_ADDR_WIDTH-2 downto 0) <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
read_nextgray(RD_ADDR_WIDTH-1) <= rd_addr(RD_ADDR_WIDTH-1) after glbtm;
for i in RD_ADDR_WIDTH-2 downto 0 loop
read_nextgray(i) <= rd_addr(i+1) xor rd_addr(i) after glbtm;
end loop;
end if;
end if;
end process gray_conv_proc;
pip_proc1: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_addrgray(RD_ADDR_WIDTH-1) <= '1';
read_addrgray(0) <= '1';
read_addrgray(RD_ADDR_WIDTH-2 downto 1) <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
read_addrgray <= read_nextgray after glbtm;
end if;
end if;
end process pip_proc1;
pip_proc2: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_lastgray(RD_ADDR_WIDTH-1) <= '1';
read_lastgray(0) <= '1';
read_lastgray(1) <= '1';
read_lastgray(RD_ADDR_WIDTH-2 downto 2) <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (rd_allow = '1') then
read_lastgray <= read_addrgray after glbtm;
end if;
end if;
end process pip_proc2;
-------------------------------------------------------------------------------
inc_wr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addr <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (wr_allow = '1') then
wr_addr <= wr_addr + '1' after glbtm;
end if;
end if;
end process inc_wr_proc;
wr_nextgray_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
write_nextgray(WR_ADDR_WIDTH-1) <= '1';
write_nextgray(WR_ADDR_WIDTH-2 downto 0) <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (wr_allow = '1') then
write_nextgray(WR_ADDR_WIDTH-1) <= wr_addr(WR_ADDR_WIDTH-1) after glbtm;
for i in WR_ADDR_WIDTH-2 downto 0 loop
write_nextgray(i) <= wr_addr(i+1) xor wr_addr(i) after glbtm;
end loop;
end if;
end if;
end process wr_nextgray_proc;
wr_addrgray_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addrgray(WR_ADDR_WIDTH-1) <= '1';
wr_addrgray(0) <= '1';
wr_addrgray(WR_ADDR_WIDTH-2 downto 1) <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (wr_allow = '1') then
wr_addrgray <= write_nextgray after glbtm;
end if;
end if;
end process wr_addrgray_proc;
------------------------------------------------------------------------------
rd_minor_proc: process(rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rd_addr_minor <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
if (WR_DWIDTH /= RD_DWIDTH) then
if (rd_allow_minor = '1') then
rd_addr_minor <= rd_addr_minor + '1' after glbtm;
end if;
end if;
end if;
end process rd_minor_proc;
wr_minor_proc: process(wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addr_minor <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (WR_DWIDTH < RD_DWIDTH) then
-- if (wr_eof_n = '0') then
-- wr_addr_minor <= (others => '0') after glbtm;
-- elsif (wr_allow_minor = '1') then
-- wr_addr_minor <= wr_addr_minor + '1' after glbtm;
-- end if;
if (wr_allow_minor = '1') then
if (wr_eof_n = '0') then
wr_addr_minor <= (others => '0') after glbtm;
else
wr_addr_minor <= wr_addr_minor + '1' after glbtm;
end if;
end if;
end if;
end if;
end process wr_minor_proc;
------------------------------------------------------------------------------
truegray_proc: process (rd_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
read_truegray <= (others => '0');
elsif (rd_clk'EVENT and rd_clk = '1') then
read_truegray(RD_ADDR_WIDTH-1) <= rd_addr(RD_ADDR_WIDTH-1);
for i in RD_ADDR_WIDTH-2 downto 0 loop
read_truegray(i) <= rd_addr(i+1) xor rd_addr(i) after glbtm;
end loop;
end if;
end process truegray_proc;
rag_wr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
rag_writesync <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
rag_writesync <= read_truegray after glbtm;
end if;
end process rag_wr_proc;
----------------------------------------------------------
-- --
-- Gray to binary Conversion. --
-- --
----------------------------------------------------------
ra_writesync <= gray_to_bin(rag_writesync);
----------------------------------------------------------
wr_addrr_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
wr_addrr <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
wr_addrr <= wr_addr after glbtm;
end if;
end process wr_addrr_proc;
------------------------------------------------------------------------------------------------------
status_proc: process (wr_clk, fifo_gsr)
begin
if (fifo_gsr = '1') then
fifostatus <= (others => '0');
elsif (wr_clk'EVENT and wr_clk = '1') then
if (full = '0') then
fifostatus <= (wr_addrr - ra_writesync) after glbtm;
end if;
end if;
end process status_proc;
--------------------------------------------------------------------------------------------------------
ecompgen: for i in 0 to WR_ADDR_WIDTH-1 generate
begin
ecomp(i) <= (not (wr_addrgray(i) xor read_addrgray(i)) and empty) or
(not (wr_addrgray(i) xor read_nextgray(i)) and not empty);
end generate ecompgen;
----------------------------------------------------------------------------------------------------------
emuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr,S=>ecomp(0),LO=>emuxcyo(0));
emuxcygen1: for i in 1 to WR_ADDR_WIDTH-2 generate
emuxcyx: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(i-1),S=>ecomp(i),LO=>emuxcyo(i));
end generate emuxcygen1;
emuxcylast: MUXCY_L port map (DI=>gnd,CI=>emuxcyo(WR_ADDR_WIDTH-2),S=>ecomp(WR_ADDR_WIDTH-1),LO=>emptyg);
----------------------------------------------------------------------------------------------------------
fcompgen: for j in 0 to WR_ADDR_WIDTH-1 generate
begin
fcomp(j) <= (not (read_lastgray(j) xor wr_addrgray(j)) and full) or
(not (read_lastgray(j) xor write_nextgray(j)) and not full);
end generate fcompgen;
----------------------------------------------------------------------------------------------------
fmuxcy0: MUXCY_L port map (DI=>gnd,CI=>pwr, S=>fcomp(0),LO=>fmuxcyo(0));
fmuxcygen2: for i in 1 to WR_ADDR_WIDTH-2 generate
fmuxcyx: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(i-1),S=>fcomp(i),LO=>fmuxcyo(i));
end generate fmuxcygen2;
fmuxcylast: MUXCY_L port map (DI=>gnd,CI=>fmuxcyo(WR_ADDR_WIDTH-2),S=>fcomp(WR_ADDR_WIDTH-1),LO=>fullg);
end DRAM_fifo_hdl;
|
gpl-3.0
|
4ef9468ae41d3bb2acca1a97c907df14
| 0.478743 | 3.781722 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_xps_osif_v2_01_a/simulation/behavioral/bfm_monitor_wrapper.vhd
| 1 | 16,448 |
-------------------------------------------------------------------------------
-- bfm_monitor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plbv46_monitor_bfm_v1_00_a;
use plbv46_monitor_bfm_v1_00_a.all;
entity bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 31);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_UABus : in std_logic_vector(0 to 63);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 255);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MRdErr : in std_logic_vector(0 to 1);
PLB_MWrErr : in std_logic_vector(0 to 1);
PLB_MIRQ : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 255);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 0);
PLB_wrPrim : in std_logic_vector(0 to 0);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_wait : in std_logic_vector(0 to 0);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 1);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMRdErr : in std_logic_vector(0 to 1);
PLB_SMWrErr : in std_logic_vector(0 to 1);
PLB_SMIRQ : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end bfm_monitor_wrapper;
architecture STRUCTURE of bfm_monitor_wrapper is
component plbv46_monitor_bfm is
generic (
PLB_MONITOR_NUM : std_logic_vector(0 to 3);
PLB_SLAVE0_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE0_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE1_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE2_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE3_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE4_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE5_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE6_ADDR_HI_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_SLAVE7_ADDR_HI_1 : std_logic_vector(0 to 31);
C_MON_PLB_AWIDTH : integer;
C_MON_PLB_DWIDTH : integer;
C_MON_PLB_NUM_MASTERS : integer;
C_MON_PLB_NUM_SLAVES : integer;
C_MON_PLB_MID_WIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_buslock : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_RNW : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_BE : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_DWIDTH/8)-1));
M_msize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
M_size : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
M_type : in std_logic_vector(0 to ((3*C_MON_PLB_NUM_MASTERS)-1));
M_TAttribute : in std_logic_vector(0 to 16*C_MON_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_UABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_ABus : in std_logic_vector(0 to ((C_MON_PLB_AWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
M_wrBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
M_rdBurst : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MAddrAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MTimeout : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_MASTERS)-1));
PLB_MRdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Mssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_MASTERS)-1));
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_wrPrim : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
PLB_MasterID : in std_logic_vector(0 to C_MON_PLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH/8)-1));
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to (C_MON_PLB_DWIDTH-1));
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wait : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rearbitrate : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to ((C_MON_PLB_DWIDTH*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdWdAddr : in std_logic_vector(0 to ((4*C_MON_PLB_NUM_SLAVES)-1));
Sl_rdDAck : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_rdBTerm : in std_logic_vector(0 to C_MON_PLB_NUM_SLAVES-1);
Sl_MBusy : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MRdErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MWrErr : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_MIRQ : in std_logic_vector(0 to ((C_MON_PLB_NUM_MASTERS*C_MON_PLB_NUM_SLAVES)-1));
Sl_ssize : in std_logic_vector(0 to ((2*C_MON_PLB_NUM_SLAVES)-1));
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to C_MON_PLB_DWIDTH-1);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMRdErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMWrErr : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_SMIRQ : in std_logic_vector(0 to C_MON_PLB_NUM_MASTERS-1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
begin
bfm_monitor : plbv46_monitor_bfm
generic map (
PLB_MONITOR_NUM => B"0000",
PLB_SLAVE0_ADDR_LO_0 => X"00000000",
PLB_SLAVE0_ADDR_HI_0 => X"00000000",
PLB_SLAVE1_ADDR_LO_0 => X"00000000",
PLB_SLAVE1_ADDR_HI_0 => X"00000000",
PLB_SLAVE2_ADDR_LO_0 => X"00000000",
PLB_SLAVE2_ADDR_HI_0 => X"00000000",
PLB_SLAVE3_ADDR_LO_0 => X"00000000",
PLB_SLAVE3_ADDR_HI_0 => X"00000000",
PLB_SLAVE4_ADDR_LO_0 => X"00000000",
PLB_SLAVE4_ADDR_HI_0 => X"00000000",
PLB_SLAVE5_ADDR_LO_0 => X"00000000",
PLB_SLAVE5_ADDR_HI_0 => X"00000000",
PLB_SLAVE6_ADDR_LO_0 => X"00000000",
PLB_SLAVE6_ADDR_HI_0 => X"00000000",
PLB_SLAVE7_ADDR_LO_0 => X"00000000",
PLB_SLAVE7_ADDR_HI_0 => X"00000000",
PLB_SLAVE0_ADDR_LO_1 => X"00000000",
PLB_SLAVE0_ADDR_HI_1 => X"00000000",
PLB_SLAVE1_ADDR_LO_1 => X"00000000",
PLB_SLAVE1_ADDR_HI_1 => X"00000000",
PLB_SLAVE2_ADDR_LO_1 => X"00000000",
PLB_SLAVE2_ADDR_HI_1 => X"00000000",
PLB_SLAVE3_ADDR_LO_1 => X"00000000",
PLB_SLAVE3_ADDR_HI_1 => X"00000000",
PLB_SLAVE4_ADDR_LO_1 => X"00000000",
PLB_SLAVE4_ADDR_HI_1 => X"00000000",
PLB_SLAVE5_ADDR_LO_1 => X"00000000",
PLB_SLAVE5_ADDR_HI_1 => X"00000000",
PLB_SLAVE6_ADDR_LO_1 => X"00000000",
PLB_SLAVE6_ADDR_HI_1 => X"00000000",
PLB_SLAVE7_ADDR_LO_1 => X"00000000",
PLB_SLAVE7_ADDR_HI_1 => X"00000000",
C_MON_PLB_AWIDTH => 32,
C_MON_PLB_DWIDTH => 128,
C_MON_PLB_NUM_MASTERS => 2,
C_MON_PLB_NUM_SLAVES => 1,
C_MON_PLB_MID_WIDTH => 1
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_Mssize => PLB_Mssize,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_MasterID => PLB_MasterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_msize => PLB_msize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_UABus => PLB_UABus,
PLB_ABus => PLB_ABus,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_rdpendReq => PLB_rdpendReq,
PLB_wrpendReq => PLB_wrpendReq,
PLB_rdpendPri => PLB_rdpendPri,
PLB_wrpendPri => PLB_wrpendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MIRQ => Sl_MIRQ,
Sl_ssize => Sl_ssize,
PLB_SaddrAck => PLB_SaddrAck,
PLB_Swait => PLB_Swait,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_SwrDAck => PLB_SwrDAck,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SMBusy => PLB_SMBusy,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMIRQ => PLB_SMIRQ,
PLB_Sssize => PLB_Sssize
);
end architecture STRUCTURE;
|
gpl-3.0
|
cdda64243e4b7c33fdcfa9c75410faf5
| 0.607855 | 2.91115 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_fa4_test4.vhd
| 4 | 2,583 |
-- In this test, we declare a component in the "mypackage" package
-- and show that it can be referenced within the package namespace.
-- it also shows the usage of subtypes, constants and signals
-- expressed in terms of defined subtypes
library ieee;
use ieee.numeric_bit.all;
package mypackage is
-- trivial sub type
subtype Myrange_t is integer range 0 to 4;
-- some constants
constant ZERO: Myrange_t := 0;
constant ONE: Myrange_t := 1;
constant TWO: Myrange_t := 2;
constant THREE: Myrange_t := 3;
constant FOUR: Myrange_t := 4;
-- another subtype
subtype AdderWidth_t is bit_vector (THREE downto ZERO);
subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO);
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
end package mypackage;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
use work.mypackage.all;
entity fa4 is
port (va_i, vb_i: in AdderWidth_t;
c_i: in bit;
vs_o: out AdderWidth_t;
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
-- auxiliary signal for carry
signal c_int: CarryWidth_t;
begin
-- carry in
c_int(ZERO) <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int(ZERO),
a_i => va_i(ZERO),
b_i => vb_i(ZERO),
s_o => vs_o(ZERO),
c_o => c_int(ONE)
);
-- slice 1
s1: fa1 port map (c_i => c_int(ONE),
a_i => va_i(ONE),
b_i => vb_i(ONE),
s_o => vs_o(ONE),
c_o => c_int(TWO)
);
-- slice 2
s2: fa1 port map (c_i => c_int(TWO),
a_i => va_i(TWO),
b_i => vb_i(TWO),
s_o => vs_o(TWO),
c_o => c_int(THREE)
);
-- slice 3
s3: fa1 port map (c_i => c_int(THREE),
a_i => va_i(THREE),
b_i => vb_i(THREE),
s_o => vs_o(THREE),
c_o => c_int(FOUR)
);
-- carry out
c_o <= c_int(FOUR);
end architecture fa4_rtl;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
|
gpl-2.0
|
e79638fd9968106139579c86c6b63546
| 0.501742 | 3.216687 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/thermal_monitor_v1_03_a/hdl/vhdl/delay_comp.vhd
| 1 | 1,242 |
----------------------------------------------------------------------------------
-- Company: University of Paderborn
-- Engineer: Markus Happe
--
-- Create Date: 16:03:25 02/09/2011
-- Design Name:
-- Module Name: delay_comp - Behavioral
-- Project Name: Thermal Sensor Net
-- Target Devices: Virtex 6 ML605
-- Tool versions: 12.3
-- Description: delay lut for ring oscillator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VComponents.all;
entity delay_comp is
Port ( rst : in std_logic;
x_in : in std_logic;
x_out : out std_logic);
end delay_comp;
architecture Behavioral of delay_comp is
signal x : std_logic;
attribute KEEP : string;
attribute KEEP of x : signal is "true";
--attribute INIT : string;
--attribute INIT of delay_lut : label is "4";
begin
x_out <= x;
delay_lut: LUT2
--synthesis translate_off
generic map (INIT => X"4")
--synthesis translate_on
port map( I0 => rst,
I1 => x_in,
O => x
);
end Behavioral;
|
gpl-3.0
|
d0482e7edc62c95f8815726fc7bc244c
| 0.542673 | 3.821538 | false | false | false | false |
BenBoZ/realtimestagram
|
src/rgb2hsv_tb.vhd
| 2 | 6,052 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
--! Used for calculation of h_count and v_count port width
use ieee.math_real.all;
--======================================================================================--
entity rgb2hsv_tb is
generic (
input_file: string := "tst/input/smpte_bars.pnm"; --! Input file of test
output_file: string := "tst/output/rgb2hsv_smpte_bars.pnm"; --! Output file of test
image_width: integer := const_imagewidth; --! Width of input image
image_height: integer := const_imageheight --! Height of input image
);
end entity;
--======================================================================================--
architecture structural of rgb2hsv_tb is
--===================component declaration===================--
component test_bench_driver_color is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 6
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
h_count: out std_logic_vector;
v_count: out std_logic_vector;
red_pixel_from_file: out std_logic_vector;
green_pixel_from_file: out std_logic_vector;
blue_pixel_from_file: out std_logic_vector;
red_pixel_to_file: in std_logic_vector;
green_pixel_to_file: in std_logic_vector;
blue_pixel_to_file: in std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
component rgb2hsv is
generic (
wordsize: integer := 8 --! input image wordsize in bits
);
port (
-- inputs
clk: in std_logic; --! completely clocked process
rst: in std_logic; --! asynchronous reset
enable: in std_logic; --! enables block
pixel_red_i: in std_logic_vector; --! the input pixel
pixel_green_i: in std_logic_vector; --! the input pixel
pixel_blue_i: in std_logic_vector; --! the input pixel
-- outputs
pixel_hue_o: out std_logic_vector;
pixel_sat_o: out std_logic_vector;
pixel_val_o: out std_logic_vector
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal h_count: std_logic_vector((integer(ceil(log2(real(image_width))))-1) downto 0) := (others => '0');
signal v_count: std_logic_vector((integer(ceil(log2(real(image_height))))-1) downto 0) := (others => '0');
signal red_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal red_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal green_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal blue_pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver_color
port map(
clk => clk,
rst => rst,
enable => enable,
h_count => h_count,
v_count => v_count,
red_pixel_from_file => red_pixel_from_file,
green_pixel_from_file => green_pixel_from_file,
blue_pixel_from_file => blue_pixel_from_file,
red_pixel_to_file => red_pixel_to_file,
green_pixel_to_file => green_pixel_to_file,
blue_pixel_to_file => blue_pixel_to_file
);
device_under_test: rgb2hsv
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_red_i => red_pixel_from_file,
pixel_green_i => green_pixel_from_file,
pixel_blue_i => blue_pixel_from_file,
pixel_hue_o => red_pixel_to_file,
pixel_sat_o => green_pixel_to_file,
pixel_val_o => blue_pixel_to_file
);
end architecture;
|
gpl-2.0
|
2196ca64922027ddbb967bad49b722e6
| 0.488929 | 4.252987 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/new/Vga.vhd
| 1 | 3,925 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.Font.all;
-- Information from http://tinyvga.com/vga-timing/1280x1024@60Hz
entity Vga is
Generic (
H_PIX : integer := 1280; -- Horizontal frame size
H_FP : integer := 48; -- Horizontal Front Porch
H_SY : integer := 112; -- Horizontal Sync
H_BP : integer := 248; -- Horizontal Back Porch
H_POL : std_logic := '1'; -- Horizontal Sync Polarity
V_PIX : integer := 1024; -- Vertical frame size
V_FP : integer := 1; -- Vertical Front Porch
V_SY : integer := 3; -- Vertical Sync
V_BP : integer := 36; -- Vertical Back Porch
V_POL : std_logic := '1' -- Vertical Sync Polarity
);
Port
(
clk : in std_logic;
hSync : out std_logic;
vSync : out std_logic;
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
fbOutAddr : out std_logic_vector(13 downto 0);
fbOutDat : in std_logic_vector(7 downto 0)
);
end Vga;
architecture Behavioral of Vga is
constant H_MAX : integer := H_PIX + H_FP + H_SY + H_BP; -- 1688 for 1280x1024@60Hz
constant V_MAX : integer := V_PIX + V_FP + V_SY + V_BP; -- 1066 for 1280x1024@60Hz
--------------------------------------------------------
begin -- BEGIN
--------------------------------------------------------
process(clk)
variable h_count : integer range 0 to H_MAX - 1 := 0; --horizontal counter (counts the columns)
variable v_count : integer range 0 to V_MAX - 1 := 0; --vertical counter (counts the rows)
variable char : std_logic_vector(7 downto 0);
--variable nextChar : std_logic_vector(7 downto 0);
variable charX : integer range 0 to 8;
variable charY : integer range 0 to 16;
begin
if (rising_edge(clk)) then
--counters
if (h_count < H_MAX - 1) then
h_count := h_count + 1;
else
h_count := 0;
if (v_count < V_MAX - 1) then
v_count := v_count + 1;
else
v_count := 0;
end if;
end if;
--horizontal sync signal
if (h_count < H_PIX + H_FP or h_count > H_PIX + H_FP + H_SY) then
hSync <= not H_POL;
else
hSync <= H_POL;
end if;
--vertical sync signal
if (v_count < V_PIX + V_FP or v_count > V_PIX + V_FP + V_SY) then
vSync <= not V_POL;
else
vSync <= V_POL;
end if;
--text display
if (h_count < H_PIX AND v_count < V_PIX) then
charX := h_count mod 8;
charY := v_count mod 16;
if (charX = 0) then -- Set up next character
char := fbOutDat;
elsif (charX = 1) then
fbOutAddr <= std_logic_vector(to_unsigned(1 + (h_count / 8) + ((v_count / 16) * 160), fbOutAddr'LENGTH));
end if;
-- char[7] = invert bit
if (char(7) = '1' xor draw_char(charX, charY, to_integer(unsigned(char and "01111111")))) then
vgaRed <= "1111";
vgaGreen <= "1111";
vgaBlue <= "1111";
else
vgaRed <= "0000";
vgaGreen <= "0000";
vgaBlue <= "0000";
end if;
else
fbOutAddr <= std_logic_vector(to_unsigned(((v_count / 16) * 160), fbOutAddr'LENGTH));
vgaRed <= "0000";
vgaGreen <= "0000";
vgaBlue <= "0000";
end if;
end if;
end process;
--------------------------------------------------------
end Behavioral; -- END
--------------------------------------------------------
|
mit
|
a5f71329af1334bc22384d7bfa1a6c73
| 0.487643 | 3.870809 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/framework/resampling.vhd
| 1 | 28,785 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity resampling is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end resampling;
architecture Behavioral of resampling is
component uf_resampling
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
Port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type state_t is (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLES_ADDRESS,
STATE_READ_INDEXES_ADDRESS,
STATE_READ_N,
STATE_READ_PARTICLE_SIZE,
STATE_READ_MAX_NUMBER_OF_PARTICLES,
STATE_READ_BLOCK_SIZE,
STATE_READ_U_FUNCTION,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_PARTICLES_1,
STATE_CALCULATE_REMAINING_PARTICLES_2,
STATE_CALCULATE_REMAINING_PARTICLES_3,
STATE_CALCULATE_REMAINING_PARTICLES_4,
STATE_CALCULATE_REMAINING_PARTICLES_5,
STATE_LOAD_U_INIT,
STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1,
STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_2,
STATE_WRITE_TO_RAM,
STATE_WRITE_BURST_DECISION,
STATE_WRITE_BURST_DECISION_2,
STATE_WRITE_BURST,
STATE_WRITE_DECISION,
STATE_READ,
STATE_WRITE,
STATE_WRITE_BURST_DONE_ACK,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_SEND_INFO_1,
STATE_SEND_INFO_2,
STATE_EXIT
);
type encode_t is array(state_t) of reconos_state_enc_t;
type decode_t is array(natural range <>) of state_t;
constant encode : encode_t := (X"00",
X"01",
X"02",
X"03",
X"04",
X"05",
X"06",
X"07",
X"08",
X"09",
X"0A",
X"0B",
X"0C",
X"0D",
X"0E",
X"0F",
X"10",
X"11",
X"12",
X"13",
X"14",
X"15",
X"16",
X"17",
X"18",
X"19",
X"1A",
X"1B",
X"1C",
X"1D",
X"1E",
X"1F"
);
constant decode : decode_t := (
STATE_CHECK,
STATE_INIT,
STATE_READ_PARTICLES_ADDRESS,
STATE_READ_INDEXES_ADDRESS,
STATE_READ_N,
STATE_READ_PARTICLE_SIZE,
STATE_READ_MAX_NUMBER_OF_PARTICLES,
STATE_READ_BLOCK_SIZE,
STATE_READ_U_FUNCTION,
STATE_WAIT_FOR_MESSAGE,
STATE_CALCULATE_REMAINING_PARTICLES_1,
STATE_CALCULATE_REMAINING_PARTICLES_2,
STATE_CALCULATE_REMAINING_PARTICLES_3,
STATE_CALCULATE_REMAINING_PARTICLES_4,
STATE_CALCULATE_REMAINING_PARTICLES_5,
STATE_LOAD_U_INIT,
STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1,
STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_2,
STATE_WRITE_TO_RAM,
STATE_WRITE_BURST_DECISION,
STATE_WRITE_BURST_DECISION_2,
STATE_WRITE_BURST,
STATE_WRITE_DECISION,
STATE_READ,
STATE_WRITE,
STATE_WRITE_BURST_DONE_ACK,
STATE_SEND_MESSAGE,
STATE_SEND_MEASUREMENT_1,
STATE_SEND_MEASUREMENT_2,
STATE_SEND_INFO_1,
STATE_SEND_INFO_2,
STATE_EXIT
);
-- current state
signal state : state_t := STATE_CHECK;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- index array
signal index_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"10000000";
signal index_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- resampling function U array
signal U_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"10000000";
signal U_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_address_if_write : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_address_if_read : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- local RAM write_address
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like N, particle size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- message (received from message box). The number in the message says,
-- which particle block has to be sampled
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- block size, is the number of particles in a particle block
signal block_size : integer := 10;
-- local RAM data (particle weight)
signal weight_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles (set by message box, default = 100)
signal N : integer := 18;
-- number of particles still to resample
signal remaining_particles : integer := 0;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- size of a particle
signal particle_size : integer := 8;
-- temp variable
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
-- number of particles to resample
signal number_of_particles_to_resample : integer := 9;
-- write counter
signal write_counter : integer := 0;
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- start index
signal start_index : integer := 3;
-- temporary variables
signal offset : integer := 1;
signal offset2 : integer := 1;
-- time values for start, stop and the difference of both
--signal time_start : integer := 0;
--signal time_stop : integer := 0;
--signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for resampling user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the resampling user process
signal particles_loaded : std_logic := '0';
-- number of particles in local RAM
signal number_of_particles : integer := 18;
-- number of particles in total
signal number_of_particles_in_total : integer := 18;
-- index of first particles (the particles are sorted increasingly)
signal start_particle_index : integer := 0;
-- resampling function init
signal U_init : integer := 2000;
-- address of the last 128 byte burst in local RAM
signal write_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- information if a write burst has been handled by the Framework
signal write_burst_done : std_logic := '0';
-- the last burst from local RAM into Maim Memory
signal write_burst : std_logic := '0';
-- number of currently written index values
signal written_values : integer := 0;
-- if every particle is resampled, this signal has to be set to '1'
signal finished : std_logic := '0';
-- for switch 1: corrected local ram address. the least bit is inverted, because else the local ram will be used incorrect
signal o_RAMAddrUserProcess : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrResampling : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWEUserProcess : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEResampling : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataUserProcess : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataResampling : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- write burst done acknowledgement
signal write_burst_done_ack : std_logic := '0';
begin
-- entity of user process
user_process : uf_resampling
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrUserProcess, o_RAMData=>o_RAMDataUserProcess,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWEUserProcess, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, particles_loaded=>particles_loaded,
number_of_particles=>number_of_particles,
number_of_particles_in_total => number_of_particles_in_total,
start_particle_index=>start_particle_index,
U_init=>U_init, write_address=>write_address,
write_burst_done=>write_burst_done, write_burst=>write_burst,
write_burst_done_ack=>write_burst_done_ack, written_values=>written_values,
finished=>finished);
-- burst ram interface
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrUserProcess(0 to C_BURST_AWIDTH-2) & not o_RAMAddrUserProcess(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrResampling(0 to C_BURST_AWIDTH-2) & not o_RAMAddrResampling(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWEUserProcess when enable = '1' else o_RAMWEResampling;
-- switch 3: output ram data
o_RAMData <= o_RAMDataUserProcess when enable = '1' else o_RAMDataResampling;
number_of_particles_in_total <= N;
write_address <= "011111100000";
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Resampling:
--
-- 1) The index array adress, the number of particles (N) and
-- the particle size is received by message boxes
--
--
-- 2) Waiting for Message m (Start of a Resampling run)
-- Resample particles of m-th block
--
--
-- 3) calcualte the number of particles, which have to be resampled
--
--
-- 4) Copy the weight of the particles to the local RAM
--
--
-- 5) The user resampling process is started
--
--
-- 6) Every time the user process demands to make a write burst into
-- the index array, it is done by the Framework
--
--
-- 7) If the user process is finished go to step 8
--
--
-- 8) Send Message m (Stop of a Resampling run)
-- Particles of m-th block are resampled
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
variable success : boolean;
-- signals for N, particle_size and max number of particles which fit in the local RAM
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable U_init_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable resume_state_enc : reconos_state_enc_t := (others => '0');
variable preempted : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
resume_state_enc := (others => '0');
done := false;
success := false;
preempted := false;
state <= STATE_CHECK;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_CHECK =>
reconos_thread_resume(done, success, o_osif, i_osif, resume_state_enc);
if done then
if success then
-- preempted
preempted := true;
state <= decode(to_integer(unsigned(resume_state_enc)));
else
-- unpreempted
state <= STATE_INIT;
end if;
end if;
when STATE_INIT =>
--! init state, receive particle array address
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK !!! (1 of 3)
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_address);
enable <= '0';
init <= '1';
if done then
--state <= STATE_READ_PARTICLES_ADDRESS;
state <= STATE_SEND_INFO_1;
-- CHANGE BACK !!! (2 of 3)
--state <= STATE_WAIT_FOR_MESSAGE;
end if;
when STATE_SEND_INFO_1 =>
-- send particles array address
reconos_mbox_put(done,success,o_osif,i_osif,C_MB_MEASUREMENT,information_struct);
if (done and success) then
state <= STATE_READ_PARTICLES_ADDRESS;
end if;
when STATE_READ_PARTICLES_ADDRESS =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
--state <= STATE_READ_INDEXES_ADDRESS;
state <= STATE_SEND_INFO_2;
end if;
when STATE_SEND_INFO_2 =>
-- send particles array address
reconos_mbox_put(done,success,o_osif,i_osif,C_MB_MEASUREMENT,particle_array_start_address);
if (done and success) then
state <= STATE_READ_INDEXES_ADDRESS;
end if;
when STATE_READ_INDEXES_ADDRESS =>
--! read index array address
reconos_read_s (done, o_osif, i_osif, information_struct+4, index_array_start_address);
if done then
state <= STATE_READ_N;
end if;
when STATE_READ_N =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+8, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= STATE_READ_PARTICLE_SIZE;
end if;
when STATE_READ_PARTICLE_SIZE =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= STATE_READ_BLOCK_SIZE;
end if;
when STATE_READ_BLOCK_SIZE =>
--! read number of particles to resample
reconos_read (done, o_osif, i_osif, information_struct+16, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= STATE_READ_U_FUNCTION;
end if;
when STATE_READ_U_FUNCTION =>
--! read start index of first particle to resample
reconos_read_s (done, o_osif, i_osif, information_struct+20, U_array_start_address);
if done then
if preempted then
preempted := false;
state <= STATE_CALCULATE_REMAINING_PARTICLES_1;
else
state <= STATE_WAIT_FOR_MESSAGE;
end if;
end if;
when STATE_WAIT_FOR_MESSAGE =>
--! wait for Message, that starts resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
reconos_flag_yield(o_osif, i_osif, encode(STATE_WAIT_FOR_MESSAGE));
if done then
if success then
message <= TO_INTEGER(SIGNED(message_var));
--remaining_particles <= number_of_particles_to_resample;
--index_array_address <= index_array_address;
--particle_array_address <= particle_array_address;
local_ram_address <= (others=>'0');
local_ram_address_if_read <= (others=>'0');
local_ram_address_if_write <= (others=>'0');
init <= '1';
enable <= '0';
particles_loaded <= '0';
if preempted then
state <= STATE_INIT;
else
state <= STATE_CALCULATE_REMAINING_PARTICLES_1;
end if;
--time_start <= TO_INTEGER(SIGNED(i_timebase));
-- CHANGE BACK !!! (3 of 3)
--state <= STATE_NEEDED_BURSTS_1;
else
state <= STATE_EXIT;
end if;
end if;
when STATE_CALCULATE_REMAINING_PARTICLES_1 =>
--! calcualte remaining particles
message2 <= message - 1;
state <= STATE_CALCULATE_REMAINING_PARTICLES_2;
when STATE_CALCULATE_REMAINING_PARTICLES_2 =>
--! calcualte remaining particles
offset <= message2 * block_size;
temp2 <= message2 * 4;
state <= STATE_CALCULATE_REMAINING_PARTICLES_3;
when STATE_CALCULATE_REMAINING_PARTICLES_3 =>
--! calcualte remaining particles
temp3 <= offset * 8;
state <= STATE_CALCULATE_REMAINING_PARTICLES_4;
when STATE_CALCULATE_REMAINING_PARTICLES_4 =>
--! calcualte remaining particles
remaining_particles <= N - offset;
index_array_address <= index_array_start_address + temp3;
start_index <= offset;
start_particle_index <= offset;
temp4 <= offset * particle_size;
U_array_address <= U_array_start_address + temp2;
state <= STATE_CALCULATE_REMAINING_PARTICLES_5;
when STATE_CALCULATE_REMAINING_PARTICLES_5 =>
--! calcualte remaining particles
if (remaining_particles > block_size) then
number_of_particles_to_resample <= block_size;
remaining_particles <= block_size;
else
number_of_particles_to_resample <= remaining_particles;
end if;
particle_array_address <= particle_array_start_address + temp4;
state <= STATE_LOAD_U_INIT;
when STATE_LOAD_U_INIT =>
--! load U_init
reconos_read (done, o_osif, i_osif, U_array_address, U_init_var);
if done then
U_init <= TO_INTEGER(SIGNED(U_init_var));
state <= STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1;
number_of_particles <= remaining_particles;
end if;
when STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1 =>
--! load weights to local ram, if this is done start the resampling
o_RAMWEResampling<= '0';
if (remaining_particles > 0) then
remaining_particles <= remaining_particles - 1;
state <= STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_2;
else
enable <= '1';
particles_loaded <= '1';
init <= '0';
state <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_2 =>
--! load weights to local ram
reconos_read_s (done, o_osif, i_osif, particle_array_address, weight_data);
if done then
state <= STATE_WRITE_TO_RAM;
particle_array_address <= particle_array_address + particle_size;
end if;
when STATE_WRITE_TO_RAM =>
--! write value to ram
o_RAMWEResampling<= '1';
o_RAMAddrResampling <= local_ram_address_if_read;
o_RAMDataResampling <= weight_data;
local_ram_address_if_read <= local_ram_address_if_read + 1;
state <= STATE_LOAD_WEIGHTS_TO_LOCAL_RAM_1;
when STATE_WRITE_BURST_DECISION =>
--! if write burst is demanded by user process, it will be done
write_burst_done <= '0';
if (finished = '1') then
-- everything is finished
state <= STATE_SEND_MESSAGE;
enable <= '0';
particles_loaded <= '0';
--time_stop <= TO_INTEGER(SIGNED(i_timebase));
--init <= '1';
elsif (write_burst = '1') then
--state <= STATE_WRITE_BURST;
state <= STATE_WRITE_BURST_DECISION_2;
end if;
when STATE_WRITE_BURST_DECISION_2 =>
--! decides if there will be a burst or there will be several writes
-- NO MORE BURSTS
--if (written_values = 16) then
-- write only burst, if the burst is full
-- state <= STATE_WRITE_BURST;
--else
local_ram_address_if_write <= write_address;
write_counter <= 2 * written_values;
enable <= '0';
state <= STATE_WRITE_DECISION;
--end if;
when STATE_WRITE_BURST =>
--! write bursts from local ram into index array
-- TODO: FIXME!!! WRITES COMMENTED OUT --- CHANGE CHANGE CHANGE
--reconos_write_burst(done, o_osif, i_osif, (local_ram_start_address + 8064), index_array_address);
--if done then
write_burst_done <= '1';
index_array_address <= index_array_address + 128;
state <= STATE_WRITE_BURST_DONE_ACK;
--end if;
when STATE_WRITE_DECISION =>
-- decides if there is still something to write
if (write_counter > 0) then
o_RAMAddrResampling <= local_ram_address_if_write;
state <= STATE_READ;
else
write_burst_done <= '1';
enable <= '1';
state <= STATE_WRITE_BURST_DONE_ACK;
end if;
when STATE_READ =>
--! read index values
state <= STATE_WRITE;
when STATE_WRITE =>
--! write data to index array
-- TODO: FIXME!!! WRITES COMMENTED OUT --- CHANGE CHANGE CHANGE
reconos_write(done, o_osif, i_osif, index_array_address, i_RAMData);
if done then
index_array_address <= index_array_address + 4;
local_ram_address_if_write <= local_ram_address_if_write + 1;
write_counter <= write_counter - 1;
state <= STATE_WRITE_DECISION;
end if;
when STATE_WRITE_BURST_DONE_ACK =>
--! write bursts from local ram into index array
if (write_burst_done_ack = '1') then
write_burst_done <= '0';
state <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_SEND_MESSAGE =>
--! send Message (resampling is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
particles_loaded <= '0';
state <= STATE_SEND_MEASUREMENT_1;
end if;
when STATE_SEND_MEASUREMENT_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
-- time_measurement <= time_stop - time_start;
-- state <= STATE_SEND_MEASUREMENT_2;
--else
state <= STATE_WAIT_FOR_MESSAGE;
--end if;
--when STATE_SEND_MEASUREMENT_2 =>
--! sends time measurement to message box
-- send message
--reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT, STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
-- state <= STATE_WAIT_FOR_MESSAGE;
--end if;
when STATE_EXIT =>
reconos_thread_exit(o_osif, i_osif, X"00000000");
when others =>
state <= STATE_WAIT_FOR_MESSAGE;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
fc93e41f8c96e3890a55b957100dd218
| 0.540177 | 3.970345 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_fifo.vhd
| 7 | 29,087 |
-------------------------------------------------------------------------------
-- Filename: ac97_fifo.vhd
--
-- Description: This module provides a FIFO interface for the AC97
-- module and provides an asyncrhonous interface for a
-- higher level module that is not synchronous with the AC97
-- clock (Bit_Clk).
--
-- This module provides a FIFO interface for both the incoming
-- data (playback data) and outgoing data (record data).
--
-- This module provides a bus independent interface so the
-- module can be used for more than one bus interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- ac97_core
-- ac97_timing
-- srl_fifo
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity ac97_fifo is
generic (
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
-- Interrupt strategy
-- 0 = No interrupts
-- 1 = when fifos are half empty (in half empty, out is half full)
-- 2 = when fifos are empty (in is empty, out is full)
-- 3 = when fifos are equal to interrupt fifo depth
C_INTR_LEVEL : integer := 0;
-- Use block ram FIFOs if 1, otherwise use a shallow
-- SRL fifo.
C_USE_BRAM : integer := 1
);
port (
-- IP Interface
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Interrupt: out std_logic;
-- CODEC signals
Bit_Clk : in std_logic;
Sync : out std_logic;
SData_Out : out std_logic;
SData_In : in std_logic;
AC97Reset_n : out std_logic
);
end entity ac97_fifo;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
library unisim;
use unisim.all;
architecture IMP of ac97_fifo is
component ac97_core is
generic (
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
-- AC97 register interface
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Strobe : in std_logic; -- initiates a "read" command
AC97_Reg_Write_Strobe : in std_logic; -- initiates a "write" command
AC97_Reg_Busy : out std_logic;
AC97_Reg_Error : out std_logic;
AC97_Reg_Read_Data_Valid : out std_logic;
-- Playback signal interface
PCM_Playback_Left: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Right: in std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Playback_Left_Accept: out std_logic;
PCM_Playback_Right_Accept: out std_logic;
-- Record signal interface
PCM_Record_Left: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Right: out std_logic_vector(0 to C_PCM_DATA_WIDTH-1);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
DEBUG : out std_logic_vector(0 to 15);
CODEC_RDY : out std_logic
);
end component ac97_core;
component FDCPE
port(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CLR : in std_ulogic;
D : in std_ulogic;
PRE : in std_ulogic
);
end component;
component SRL_FIFO is
generic (
C_DATA_BITS : integer;
C_DEPTH : integer);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
FIFO_Level : out std_logic_vector(0 to 3);
Half_Full : out std_logic;
Half_Empty : out std_logic
);
end component SRL_FIFO;
component BRAM_FIFO is
generic (
C_DATA_BITS : integer := 32;
C_ADDR_BITS : integer := 9
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Level : out std_logic_vector(0 to C_ADDR_BITS);
Full : out std_logic;
HalfFull : out std_logic;
HalfEmpty : out std_logic;
Overflow : out std_logic;
Underflow : out std_logic;
Empty : out std_logic
);
end component BRAM_FIFO;
-- OUT_FIFO: record data from out fifo (left and right)
-- IN_FIFO: playback data (left and right)
-- STATUS: status of FIFOs/AC97
-- CONTROL: overall controll. clear fifos, interrupts
-- AC97_READ_ADR: result of AC97 register read
-- AC97_WRITE_ADR: Value to send for a AC97 write
-- AC97_CTRL_ADR: write ac97 command
signal controller_addr : std_logic_vector(0 to 2);
-- Register Map
-- Addr Read Write
-- 0x0 OUT_FIFO IN_FIFO
-- 0x4 STATUS Control
-- 0x8 AC97_READ AC97_WRITE
-- 0xc N/A AC97_CNTRL
constant IN_FIFO_ADR : std_logic_vector(0 to 2) := "000"; -- x0000
constant OUT_FIFO_ADR : std_logic_vector(0 to 2) := "000"; -- x0000
constant STATUS_ADR : std_logic_vector(0 to 2) := "001"; -- x0004
constant CTRL_ADR : std_logic_vector(0 to 2) := "001"; -- x0004
constant AC97_READ_ADR : std_logic_vector(0 to 2) := "010"; -- x0008
constant AC97_WRITE_ADR : std_logic_vector(0 to 2) := "010"; -- x0008
constant AC97_CTRL_ADR : std_logic_vector(0 to 2) := "011"; -- x000C
constant DEBUG_ADR : std_logic_vector(0 to 2) := "011"; -- x000C
-- Fifo signals
signal in_FIFO_Write : std_logic;
signal in_FIFO_Read : std_logic;
signal in_Data_FIFO : std_logic_vector(0 to 31);
signal in_FIFO_Full : std_logic;
signal in_Data_Exists : std_logic;
signal in_FIFO_Empty : std_logic;
signal in_FIFO_Half_Full : std_logic;
signal in_FIFO_Half_Empty : std_logic;
signal out_FIFO_Write : std_logic;
signal out_FIFO_Read : std_logic;
signal out_Data_Read : std_logic_vector(0 to 31);
signal out_Data_FIFO : std_logic_vector(0 to 31);
signal out_FIFO_Full : std_logic;
signal out_Data_Exists : std_logic;
signal out_FIFO_Empty : std_logic;
signal out_FIFO_Half_Empty : std_logic;
signal out_FIFO_Half_Full : std_logic;
signal out_FIFO_Overrun : std_logic := '0';
signal in_FIFO_Underrun : std_logic := '0';
signal clear_in_fifo : std_logic;
signal clear_out_fifo : std_logic;
signal in_fifo_interrupt_en : std_logic;
signal out_fifo_interrupt_en : std_logic;
signal status_Reg : std_logic_vector(31 downto 0) := (others => '0');
signal IpClk_ac97_reg_addr : std_logic_vector(0 to 6);
signal IpClk_ac97_Reg_Write_Data : std_logic_vector(0 to 15);
signal IpClk_ac97_reg_read : std_logic;
signal BitClk_codec_rdy, IpClk_codec_rdy : std_logic := '0';
signal BitClk_ac97_Reg_Read_Data : std_logic_vector(0 to 15);
signal IpClk_ac97_reg_access_S : std_logic;
signal BitClk_ac97_reg_access_St : std_logic_vector(2 downto 0);
signal BitClk_ac97_reg_access_S : std_logic;
signal BitClk_ac97_reg_read_data_valid : std_logic;
signal in_fifo_level, out_fifo_level : std_logic_vector(0 to 9);
signal in_srl_fifo_level, out_srl_fifo_level : std_logic_vector(0 to 3);
signal BitClk_ac97_reg_data_valid : std_logic; -- ignore?
signal BitClk_record_left_valid,BitClk_record_right_valid : std_logic;
signal BitClk_playback_left_accept,BitClk_playback_right_accept : std_logic;
signal BitClk_ac97_reg_read_strobe : std_logic := '0';
signal BitClk_ac97_reg_write_strobe : std_logic := '0';
signal BitClk_playback_left_valid,BitClk_playback_right_valid : std_logic;
signal BitClk_ac97_reg_busy, IpClk_ac97_reg_busy : std_logic := '0';
signal BitClk_ac97_reg_error, IpClk_ac97_reg_error : std_logic := '0';
signal IpClk_access_request : std_logic;
signal IpClk_playback_accept_St : std_logic_vector(1 downto 0);
signal IpClk_playback_accept_S : std_logic;
signal IpClk_record_valid_St : std_logic_vector(1 downto 0);
signal IpClk_record_accept_S : std_logic;
signal ac97_reset_i : std_logic := '0';
signal register_access_busy : std_logic;
type register_access_state is (IDLE, ISSUE_ACCESS, PROCESS_ACCESS);
signal ac97_register_access_sm : register_access_state := IDLE;
signal debug_i : std_logic_vector(0 to 15);
signal ac97_core_reset : std_logic;
begin -- architecture IMP
------------------------------------------------------------
-- IP Interface
------------------------------------------------------------
-- Register address decoding bits
controller_addr <= Bus2IP_Addr(27 to 29);
-- Output multiplixer for read registers:
-- status register
-- AC97 register data
-- Audio data
OUT_MUX: process (controller_addr, status_reg, Bitclk_ac97_Reg_Read_Data,
out_Data_read) is
begin
IP2Bus_Data <= (others => '0');
case controller_addr is
when STATUS_ADR =>
IP2Bus_Data((32-status_reg'length) to 31) <= status_reg;
when AC97_READ_ADR =>
IP2Bus_Data(16 to 31) <= BitClk_ac97_Reg_Read_Data; -- todo: fix
when DEBUG_ADR =>
IP2Bus_Data(16 to 31) <= debug_i;
when others =>
IP2Bus_Data <= out_Data_Read;
end case;
end process OUT_MUX;
----------------------------------------------------------------
-- FIFO Control
----------------------------------------------------------------
-- Generating read and write pulses for FIFOs
in_FIFO_write <= '1' when ( Bus2IP_WrCE = '1'
and controller_addr = IN_FIFO_ADR)
else '0';
out_FIFO_read <= '1' when (Bus2IP_RdCE = '1'
and controller_addr = OUT_FIFO_ADR)
else '0';
clear_fifo_PROCESS : process (Bus2IP_WrCE, controller_addr,
Bus2IP_Data(30 to 31))
begin
if Bus2IP_WrCE = '1' and controller_addr = CTRL_ADR then
clear_in_fifo <= Bus2IP_Data(31);
clear_out_fifo <= Bus2IP_Data(30);
else
clear_in_fifo <= '0';
clear_out_fifo <= '0';
end if;
end process;
----------------------------------------------------------------
-- Interrupt enable register
----------------------------------------------------------------
fifo_interrupt_enable_proc : process (Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
in_fifo_interrupt_en <= '0';
out_fifo_interrupt_en <= '0';
elsif Bus2IP_WrCE = '1' and controller_addr = CTRL_ADR then
in_fifo_interrupt_en <= Bus2IP_Data(29);
out_fifo_interrupt_en <= Bus2IP_Data(28);
end if;
end if;
end process fifo_interrupt_enable_proc;
----------------------------------------------------------------
-- AC97Reset control register
----------------------------------------------------------------
ac97_reset_n_PROCESS : process (Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
ac97_reset_i <= '1';
elsif Bus2IP_WrCE = '1' and controller_addr = CTRL_ADR then
ac97_reset_i <= Bus2IP_Data(27);
end if;
end if;
end process;
AC97Reset_n <= not ac97_reset_i;
-- The reset signal to the core & timing module occurs when
-- the bus is reset or when the AC97 codec is reset
ac97_core_reset <= ac97_reset_i or Bus2IP_Reset;
-----------------------------------------------------------------------------
-- Status register
-----------------------------------------------------------------------------
FIFO_Error_PROCESS : process (Bus2IP_Clk) is
begin -- process AC97_Write_Reg_Data
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if Bus2IP_Reset = '1' then
out_FIFO_Overrun <= '0';
in_FIFO_Underrun <= '0';
else
if (clear_in_fifo = '1') then
in_FIFO_Underrun <= '0';
elsif (in_Data_Exists = '0') and (in_FIFO_Read = '1') then
in_FIFO_Underrun <= '1';
end if;
if (clear_out_fifo = '1') then
out_FIFO_Overrun <= '0';
elsif (out_FIFO_Full = '1') and (out_FIFO_Write = '1')
and (out_FIFO_read = '0') then
out_FIFO_Overrun <= '1';
end if;
end if;
end if;
end process;
status_reg(31 downto 22) <= out_fifo_level;
status_reg(21 downto 12) <= in_fifo_level;
--status_reg(11 downto 9) <= (others => '0');
status_reg(10) <= out_fifo_interrupt_en;
status_reg(9) <= in_fifo_interrupt_en;
status_reg(8) <= IpClk_ac97_reg_error;
status_reg(7) <= out_FIFO_Overrun;
status_reg(6) <= in_FIFO_Underrun;
status_reg(5) <= IpClk_codec_rdy;
status_reg(4) <= register_access_busy; --IpClk_ac97_reg_busy;
status_reg(3) <= out_Data_Exists;
status_reg(2) <= out_fifo_empty;
status_reg(1) <= in_fifo_empty;
status_reg(0) <= in_FIFO_Full;
process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
IpClk_codec_rdy <= BitClk_codec_rdy;
IpClk_ac97_reg_busy <= BitClk_ac97_reg_busy;
IpClk_ac97_reg_error <= BitClk_ac97_reg_error;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 Access Register
-----------------------------------------------------------------------------
-- The AC97 access register is used to initiate an AC97 register
-- read or write command. This register holds the AC97 address to
-- read/write as well as the direction (IpClk_ac97_reg_read).
AC97_Access_Reg : process (Bus2IP_Clk) is
begin -- process AC97_Write_Reg_Data
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
IpClk_ac97_reg_addr <= (others => '0');
IpClk_ac97_reg_read <= '0';
else
if Bus2IP_WrCE = '1' and AC97_CTRL_ADR = controller_addr then
IpClk_ac97_reg_addr <= Bus2IP_Data(25 to 31);
IpClk_ac97_reg_read <= Bus2IP_Data(24);
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 Write data register
-----------------------------------------------------------------------------
-- AC97 Register Write Data: This register holds the data that is to
-- be written to the AC97 internal register.
--
-- Writing to this register does not cause the actual
-- write process to the AC97. Once this register has been written,
-- a command must be written to the AC97_Access_Reg to initiate the
-- actual write.
AC97_Write_Reg : process (Bus2IP_Clk) is
begin -- process AC97_Write_Reg_Data
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
IpClk_ac97_reg_write_data <= (others => '0');
else
if Bus2IP_WrCE = '1' and controller_addr = AC97_WRITE_ADR then
IpClk_ac97_reg_write_data <= Bus2IP_Data(16 to 31);
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- AC97 Access initiate one shot
-----------------------------------------------------------------------------
-- This one bit signal is asserted when a write occurs to the AC97_CTRL_ADDR.
-- This is a one-shot signal that is only asserted for one cycle
-- (Bus2IP_Clk).
-- This signal will initiate the AC97 register access state machine.
AC97_Access_S_PROCESS : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_WrCE = '1' and controller_addr = AC97_CTRL_ADR then
IpClk_ac97_reg_access_S <= '1'; -- one shot
else
IpClk_ac97_reg_access_S <= '0';
end if;
end if;
end process;
-- busy signal
process (Bus2IP_Clk) is
begin
if Bus2IP_Reset = '1' then
ac97_register_access_sm <= IDLE;
elsif Bus2IP_Clk'event and Bus2IP_Clk='1' then
case ac97_register_access_sm is
when IDLE =>
if IpClk_ac97_reg_access_S = '1' then
ac97_register_access_sm <= ISSUE_ACCESS;
end if;
when ISSUE_ACCESS =>
-- TODO: add time out in case the codec is not hooked up
if IpClk_ac97_reg_busy = '1' then
ac97_register_access_sm <= PROCESS_ACCESS;
end if;
when PROCESS_ACCESS =>
if IpClk_ac97_reg_busy = '0' then
ac97_register_access_sm <= IDLE;
end if;
end case;
end if;
end process;
register_access_busy <= '1' when (ac97_register_access_sm = ISSUE_ACCESS or
ac97_register_access_sm = PROCESS_ACCESS)
else '0';
-----------------------------------------------------------------------------
-- Clock crossing signals
-----------------------------------------------------------------------------
-- convert the one cycle strobe in the IpClk domain to
-- the BitClk domain.
fdcpe_1 : FDCPE
port map (
Q => IpClk_access_request,
C => '0',
CE => '0',
CLR => BitClk_ac97_reg_access_S,
D => '0',
PRE => IpClk_ac97_reg_access_S
);
process (Bit_Clk) is
begin
if Bit_Clk'event and Bit_Clk='1' then
BitClk_ac97_reg_access_St(0) <= IpClk_access_request;
BitClk_ac97_reg_access_St(1) <= BitClk_ac97_reg_access_St(0);
BitClk_ac97_reg_access_S <= BitClk_ac97_reg_access_St(0) and
(not BitClk_ac97_reg_access_St(1));
end if;
end process;
BitClk_ac97_reg_read_strobe <= BitClk_ac97_reg_access_S and
IpClk_ac97_reg_read;
BitClk_ac97_reg_write_strobe <= BitClk_ac97_reg_access_S and
(not IpClk_ac97_reg_read);
BitClk_playback_left_valid <= '1';
BitClk_playback_right_valid <= '1';
-----------------------------------------------------------------------------
-- Fifo Control Signals (asynchronous clock transfer)
--
-----------------------------------------------------------------------------
-- BitClk is slower than IpClk.
process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_clk='1' then
IpClk_playback_accept_St(0) <= BitClk_playback_left_accept;
IpClk_playback_accept_St(1) <= IpClk_playback_accept_St(0);
end if;
IpClk_playback_accept_S <= IpClk_playback_accept_St(0) and
(not IpClk_playback_accept_St(1));
end process;
process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_clk='1' then
IpClk_record_valid_St(0) <= BitClk_record_left_valid;
IpClk_record_valid_St(1) <= IpClk_record_valid_St(0);
end if;
end process;
IpClk_record_accept_S <= IpClk_record_valid_St(0) and
(not IpClk_record_valid_St(1));
in_FIFO_Read <= IpClk_playback_accept_S;
out_FIFO_Write <= IpClk_record_accept_S;
-----------------------------------------------------------------------------
-- IN_FIFO
--
-- This fifo receives data directly from the OPB bus and performs a "fifo
-- write" for each OPB write to the FIFO. The FIFO sends data directly to the
-- AC97 core and performs a "fifo read" every time a new AC97 frame is sent.
--
-----------------------------------------------------------------------------
Using_Playback_SRL : if (C_PLAYBACK = 1 and C_USE_BRAM = 0) generate
IN_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => 32, -- Left and Right channel
C_DEPTH => 16)
port map (
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
Clear_FIFO => clear_in_fifo,
FIFO_Write => in_FIFO_Write,
Data_In => Bus2IP_Data,
FIFO_Read => in_FIFO_Read,
Data_Out => in_Data_FIFO,
FIFO_Full => in_FIFO_Full,
Data_Exists => in_Data_Exists,
FIFO_Level => in_srl_fifo_level,
Half_Full => in_FIFO_Half_Full,
Half_Empty => in_FIFO_Half_Empty);
in_fifo_level <= "000000" & in_srl_fifo_level;
in_FIFO_Empty <= not in_Data_Exists;
end generate Using_Playback_SRL;
Using_Playback_BRAM : if (C_PLAYBACK = 1 and C_USE_BRAM = 1) generate
IN_FIFO : BRAM_FIFO
port map (
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
Clear_FIFO => clear_in_fifo,
FIFO_Write => in_FIFO_Write,
Data_In => Bus2IP_Data,
FIFO_Read => in_FIFO_Read,
Data_Out => in_Data_FIFO,
FIFO_Level => in_fifo_level,
FULL => in_FIFO_Full,
HalfFull => in_FIFO_HALF_FULL,
HalfEmpty => in_FIFO_Half_Empty,
Overflow => open,
Underflow => open,
Empty => in_FIFO_Empty
);
in_Data_Exists <= not in_FIFO_Empty;
end generate Using_Playback_BRAM;
No_Playback : if (C_PLAYBACK = 0) generate
in_Data_FIFO <= (others => '0');
in_FIFO_Full <= '0';
in_Data_Exists <= '0';
in_FIFO_Empty <= '0';
in_fifo_level <= (others => '0');
out_fifo_level <= (others => '0');
end generate No_Playback;
-----------------------------------------------------------------------------
-- OUT_FIFO
--
-- This fifo receives data directly from the AC97 and performs a "fifo
-- write" for each AC97 frame. The FIFO sends data directly to the
-- OPB Bus core and performs a "fifo read" every time data is read from the
-- FIFO over the OPB bus.
--
-----------------------------------------------------------------------------
Using_Recording_SRL : if (C_RECORD = 1 and C_USE_BRAM = 0) generate
OUT_FIFO : SRL_FIFO
generic map (
C_DATA_BITS => 32, -- [integer]
C_DEPTH => 16) -- [integer]
port map (
Clk => Bus2IP_Clk, -- [in std_logic]
Reset => Bus2IP_Reset, -- [in std_logic]
Clear_FIFO => clear_out_fifo, -- [in std_logic]
FIFO_Write => out_FIFO_Write, -- [in std_logic]
Data_In => out_Data_FIFO,
FIFO_Read => out_FIFO_Read, -- [in std_logic]
Data_Out => out_Data_Read, -- [out std_logic_vector(0 to C_OPB_DWIDTH-1)]
FIFO_Full => out_FIFO_Full, -- [out std_logic]
Data_Exists => out_Data_Exists, -- [out std_logic]
FIFO_Level => out_srl_fifo_level,
Half_Full => out_FIFO_Half_Full, -- [out std_logic]
Half_Empty => open); -- [out std_logic]
out_fifo_level <= "000000" & out_srl_fifo_level;
out_fifo_empty <= not out_Data_exists;
end generate Using_Recording_SRL;
Using_Recording_BRAM : if (C_RECORD = 1 and C_USE_BRAM = 1) generate
OUT_FIFO : BRAM_FIFO
port map (
Clk => Bus2IP_Clk,
Reset => Bus2IP_Reset,
Clear_FIFO => clear_out_fifo,
FIFO_Write => out_FIFO_Write,
Data_In => out_Data_FIFO,
FIFO_Read => out_FIFO_Read,
Data_Out => out_Data_Read,
FIFO_Level => out_fifo_level,
FULL => out_FIFO_Full,
HalfFull => out_FIFO_HALF_FULL,
HalfEmpty => out_FIFO_HALF_Empty,
Overflow => open,
Underflow => open,
Empty => out_FIFO_Empty); -- [out std_logic]
out_Data_Exists <= not out_FIFO_Empty;
end generate Using_Recording_BRAM;
No_Recording : if (C_RECORD = 0) generate
out_Data_Read <= (others => '0');
out_FIFO_Full <= '0';
out_Data_Exists <= '0';
end generate No_Recording;
-----------------------------------------------------------------------------
-- Instanciating the core
-----------------------------------------------------------------------------
ac97_core_I : ac97_core
port map (
Reset => ac97_core_reset,
AC97_Bit_Clk => Bit_Clk,
AC97_Sync => Sync,
AC97_SData_Out => SData_Out,
AC97_SData_In => SData_In,
AC97_Reg_Addr => IpClk_ac97_reg_addr, -- async
AC97_Reg_Write_Data => IpClk_ac97_reg_write_data, -- async
AC97_Reg_Read_Data => BitClk_ac97_Reg_Read_Data,
AC97_Reg_Read_Strobe => BitClk_ac97_reg_read_strobe,
AC97_Reg_Write_Strobe => BitClk_ac97_reg_write_strobe,
AC97_Reg_Busy => BitClk_ac97_reg_busy,
AC97_Reg_Error => BitClk_ac97_reg_error,
AC97_Reg_Read_Data_Valid => BitClk_ac97_reg_data_valid,
PCM_Playback_Left => in_Data_Fifo(16 to 31),
PCM_Playback_Right => in_Data_Fifo(0 to 15),
PCM_Playback_Left_Valid => BitClk_playback_left_valid,
PCM_Playback_Right_Valid => BitClk_playback_right_valid,
PCM_Playback_Left_Accept => BitClk_playback_left_accept,
PCM_Playback_Right_Accept => BitClk_playback_right_accept,
PCM_Record_Left => out_Data_Fifo(16 to 31),
PCM_Record_Right => out_Data_Fifo(0 to 15),
PCM_Record_Left_Valid => BitClk_record_left_valid,
PCM_Record_Right_Valid => BitClk_record_right_valid,
DEBUG => debug_i,
CODEC_RDY => BitClk_codec_rdy
);
-----------------------------------------------------------------------------
-- Handling the interrupts
-----------------------------------------------------------------------------
Interrupt_Handle: process (in_FIFO_Half_Full,
in_FIFO_Full, In_Data_Exists,
in_fifo_interrupt_en,
out_FIFO_Half_Full, out_FIFO_Half_Empty,
out_FIFO_Full, out_Data_Exists,
out_fifo_interrupt_en
) is
begin -- process Playback_Interrupt_Handle
if (C_INTR_LEVEL = 1) then
Interrupt <= (in_fifo_interrupt_en and in_FIFO_Half_Empty) or
(out_fifo_interrupt_en and out_FIFO_Half_Full);
elsif (C_INTR_LEVEL = 2) then
Interrupt <= (in_fifo_interrupt_en and in_FIFO_Full) or
(out_fifo_interrupt_en and out_FIFO_Empty);
elsif (C_INTR_LEVEL = 3) then
Interrupt <= (in_fifo_interrupt_en and in_FIFO_Half_Full) or
(out_fifo_interrupt_en and out_Fifo_Half_Empty);
-- TODO: implement level 3
else
Interrupt <= '0';
end if;
end process Interrupt_Handle;
end architecture IMP;
|
gpl-3.0
|
1a775d671f51e2140b81faeb39a4a3ef
| 0.511809 | 3.671674 | false | false | false | false |
luebbers/reconos
|
tests/automated/mutex/hw/hwthreads/mutex/hwt_mutex.vhd
| 1 | 2,298 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_mutex is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_mutex is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_MUTEX : std_logic_vector(31 downto 0) := X"00000000";
type t_state is ( STATE_MUTEX_LOCK,
STATE_WAIT,
STATE_MUTEX_UNLOCK,
STATE_WAIT2);
signal state : t_state;
begin
state_proc: process( clk, reset )
variable done: boolean;
variable success: boolean;
variable addr : std_logic_vector(31 downto 0);
variable data : std_logic_vector(31 downto 0);
variable counter : integer range 0 to 25000001;
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_MUTEX_LOCK;
done := false;
success := false;
counter := 0;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_MUTEX_LOCK =>
reconos_mutex_lock(done, success, o_osif, i_osif, C_MUTEX);
if done then
counter := 25000000; -- 0.25 seconds @ 100MHz
state <= STATE_WAIT;
end if;
when STATE_WAIT =>
if counter = 0 then
state <= STATE_MUTEX_UNLOCK;
else
counter := counter - 1;
end if;
when STATE_MUTEX_UNLOCK =>
reconos_mutex_unlock(o_osif, i_osif, C_MUTEX);
counter := 25000000; -- 0.25 seconds @ 100MHz
state <= STATE_WAIT2;
when STATE_WAIT2 =>
if counter = 0 then
state <= STATE_MUTEX_LOCK;
else
counter := counter - 1;
end if;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
c96563b1c28866a92d65b72cffe43cfd
| 0.624456 | 3.064 | false | false | false | false |
five-elephants/hw-neural-sampling
|
sampling_pkg.vhdl
| 1 | 2,639 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package sampling is
constant weight_width : integer := 4;
constant weight_fraction : integer := 1;
constant membrane_width : integer := 16;
constant membrane_fraction : integer := 12;
constant lfsr_width : integer := 16;
constant lfsr_use_width : integer := 16;
constant lfsr_fraction : integer := 16;
constant joint_counter_width : positive := 16;
subtype systime_t is unsigned(63 downto 0);
subtype lfsr_state_t is std_logic_vector(lfsr_width-1 downto 0);
subtype membrane_t is signed(membrane_width-1 downto 0);
subtype weight_t is signed(weight_width-1 downto 0);
subtype joint_counter_t is unsigned(joint_counter_width-1 downto 0);
type lfsr_state_array_t is array(positive range <>) of
lfsr_state_t;
type membrane_array_t is array(positive range <>) of
membrane_t;
type weight_array_t is array(positive range <>) of
weight_t;
type weight_array2_t is array(positive range <>, positive range <>) of
weight_t;
type state_array_t is array(positive range <>) of
std_ulogic;
type state_array2_t is array(positive range <>, positive range <>) of
std_ulogic;
type phase_t is (
idle,
propagate,
tick,
evaluate
);
type joint_counter_array_t is array(positive range <>) of
joint_counter_t;
-- 8bit full polynomial
--constant lfsr_polynomial : lfsr_state_t := "10111000";
-- 16bit full polynomial
constant lfsr_polynomial : lfsr_state_t := "1011010000000000";
-- generate a fixed point number in the given representation
function make_fixed(number : real; i_width, f_width : natural)
return signed;
function make_ufixed(number : real; i_width, f_width : natural)
return unsigned;
-- compute size of input to sampler from synapses
function sum_in_size(num_samplers : positive)
return positive;
end sampling;
package body sampling is
function make_fixed(number : real; i_width, f_width : natural)
return signed is
variable rv : signed(i_width+f_width downto 0);
begin
rv := to_signed(integer(number * (2.0**f_width) ), i_width+f_width+1);
return rv;
end make_fixed;
function make_ufixed(number : real; i_width, f_width : natural)
return unsigned is
variable rv : unsigned(i_width+f_width-1 downto 0);
begin
rv := to_unsigned(integer(number * (2.0**f_width) ), rv'length);
return rv;
end make_ufixed;
function sum_in_size(num_samplers : positive)
return positive is
begin
return weight_width + num_samplers;
end sum_in_size;
end sampling;
|
apache-2.0
|
2d81492e90f9703c9a9d3003721ad07b
| 0.685866 | 3.620027 | false | false | false | false |
luebbers/reconos
|
core/pcores/mbox_fifo_v1_01_a/hdl/vhdl/mbox_fifo.vhd
| 1 | 3,741 |
--
-- \file mbox_fifo.vhd
--
-- Mailbox FIFO to establish point-to-point connections between HW threads
--
-- adapted for ReconOS by Enno Luebbers <[email protected]>
--
-- \author Jason Agron <[email protected]>
-- \date 21.11.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.ipif_pkg.all;
--library opb_ipif_v3_01_c;
--use opb_ipif_v3_01_c.all;
library mbox_fifo_v1_01_a;
use mbox_fifo_v1_01_a.all;
entity mbox_fifo is
generic (
ADDRESS_WIDTH : integer := 9;
DATA_WIDTH : integer := 32
);
port (
readClk : in std_logic;
readRst : in std_logic;
writeClk : in std_logic;
writeRst : in std_logic;
write : in std_logic;
read : in std_logic;
dataIn : in std_logic_vector(0 to DATA_WIDTH-1);
dataOut : out std_logic_vector(0 to DATA_WIDTH-1);
clearToWrite : out std_logic;
clearToRead : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of readClk : signal is "Clk";
attribute SIGIS of writeClk : signal is "Clk";
attribute SIGIS of readRst : signal is "Rst";
attribute SIGIS of writeRst : signal is "Rst";
end entity mbox_fifo;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of mbox_fifo is
-- Component Declaration for the "guts" of the fifo core
component fifo_async
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic
);
end component;
signal empty : std_logic;
signal full : std_logic;
signal valid : std_logic;
signal reset : std_logic;
begin
-- instantiate FIFOs
fifo_inst : fifo_async
port map (
rd_clk => readClk,
wr_clk => writeClk,
din => dataIn,
rd_en => read,
rst => reset,
wr_en => write,
dout => dataOut,
empty => empty,
full => full,
valid => valid);
reset <= readRst or writeRst;
clearToRead <= (not empty) or valid;
clearToWrite <= not full;
end IMP;
|
gpl-3.0
|
b6bbdbbd69cae18cf2e99a4975b78e62
| 0.557338 | 3.856701 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_const_array_pkg.vhd
| 3 | 1,309 |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for constant arrays access
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package constant_array_pkg is
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant const_array : t_unsigned_array(7 downto 0) :=
(0 => "00000010",
1 => "00001000",
2 => "00010000",
3 => "00100000",
4 => "01000000",
5 => "01111100",
others => "00000010");
end package constant_array_pkg;
|
gpl-2.0
|
d9dae510d0c192fb62df64584b61286e
| 0.68984 | 3.954683 | false | false | false | false |
bzero/freezing-spice
|
src/ex.vhd
| 2 | 2,151 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.ex_pkg.all;
entity instruction_executor is
port (ex_d : in ex_in;
ex_q : out ex_out);
end entity instruction_executor;
architecture Behavioral of instruction_executor is
signal op1 : word;
signal op2 : word;
signal alu_out : word;
signal compare_result : std_logic;
signal return_addr : unsigned(word'range);
constant c_four : unsigned(2 downto 0) := to_unsigned(4, 3);
begin -- architecture Behavioral
-- assign modules outputs
ex_q.alu_result <= alu_out;
ex_q.compare_result <= compare_result;
ex_q.return_addr <= std_logic_vector(return_addr);
-- ALU operand 1 multiplexer
op1 <= ex_d.npc when (ex_d.insn_type = OP_BRANCH or
ex_d.insn_type = OP_JAL or
ex_d.insn_type = OP_JALR or
ex_d.insn_type = OP_AUIPC)
else ex_d.rs1;
-- ALU operand 2 multiplexer
op2 <= ex_d.imm when ((ex_d.insn_type = OP_ALU and ex_d.use_imm = '1') or
ex_d.insn_type = OP_BRANCH or
ex_d.insn_type = OP_JAL or
ex_d.insn_type = OP_JALR or
ex_d.insn_type = OP_LOAD or
ex_d.insn_type = OP_STORE or
ex_d.insn_type = OP_AUIPC)
else ex_d.rs2;
-- ALU
arithmetic_logic_unit : entity work.alu(Behavioral)
port map (alu_func => ex_d.alu_func,
op1 => op1,
op2 => op2,
result => alu_out);
-- compare unit
conditionals : entity work.compare_unit(Behavioral)
port map (branch_type => ex_d.branch_type,
op1 => op1,
op2 => op2,
compare_result => compare_result);
-- return address for JAL/JALR
return_addr <= unsigned(ex_d.npc) + c_four;
end architecture Behavioral;
|
bsd-3-clause
|
75932fc0cc19fa859a0a10ca11716852
| 0.504881 | 3.74087 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_generic_eval.vhd
| 3 | 2,192 |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for generics evaluation.
library ieee;
use ieee.std_logic_1164.all;
entity eval_generic is
generic(
msb : integer range 1 to 7 := 7;
bit_select : integer range 0 to 7 := 3
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end entity eval_generic;
architecture test of eval_generic is
begin
out_bit <= in_word(bit_select);
end architecture test;
library ieee;
use ieee.std_logic_1164.all;
entity test_eval_generic is
port(
in_word : in std_logic_vector(7 downto 0);
out_bit_def, out_bit_ovr : out std_logic
);
end entity test_eval_generic;
architecture test of test_eval_generic is
constant const_int : integer := 7;
component eval_generic is
generic(
msb : integer range 1 to 7;
bit_select : integer range 0 to 7
);
port(
in_word : in std_logic_vector(msb downto 0);
out_bit : out std_logic
);
end component eval_generic;
begin
override_test_unit: eval_generic
generic map(bit_select => 2,
msb => const_int)
port map(
in_word => (others => '1'),
out_bit => out_bit_ovr
);
default_test_unit: eval_generic
port map(
in_word => in_word,
out_bit => out_bit_def
);
end architecture test;
|
gpl-2.0
|
fdaf32a7cc02dde2a79b091682c33f66
| 0.645985 | 3.812174 | false | true | false | false |
luebbers/reconos
|
demos/huffman_demo/hw/pcores/hw_task_v1_01_b/hdl/vhdl/hw_task.vhd
| 1 | 4,660 |
------------
-- pcore top level wrapper
-- generated at 2008-01-29 13:02:52.513801 by 'mkhwtask.py hwt_memcopy 1 hwt_memcopy.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.ALL;
library burst_ram_v2_01_a;
use burst_ram_v2_01_a.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 14; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 12; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
i_burstBE : in std_logic_vector(7 downto 0)
);
end hw_task;
architecture structural of hw_task is
signal o_osif_flat_i : std_logic_vector(0 to 41);
signal i_osif_flat_i : std_logic_vector(0 to 44);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
constant C_GND_TASK_DATA : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
constant C_GND_TASK_ADDR : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_build_histo_i : entity hwt_build_histo
generic map (
C_BURST_AWIDTH => C_TASK_BURST_AWIDTH,
C_BURST_DWIDTH => C_TASK_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk
);
burst_ram_i : entity burst_ram_v2_01_a.burst_ram
generic map (
G_PORTA_AWIDTH => C_TASK_BURST_AWIDTH,
G_PORTA_DWIDTH => C_TASK_BURST_DWIDTH,
G_PORTA_PORTS => 1,
G_PORTB_AWIDTH => C_BUS_BURST_AWIDTH-3,
G_PORTB_DWIDTH => C_BUS_BURST_DWIDTH,
G_PORTB_USE_BE => 1
)
port map (
addra => task2burst_Addr,
addrax => C_GND_TASK_ADDR,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkax => '0',
clkb => clk,
dina => task2burst_Data,
dinax => C_GND_TASK_DATA,
dinb => i_burstData,
douta => burst2task_Data,
doutax => open,
doutb => o_burstData,
wea => task2burst_WE,
weax => '0',
web => i_burstWE,
ena => '1',
enax => '0',
enb => '1',
beb => i_burstBE
);
end structural;
|
gpl-3.0
|
3331360c820b5033082f0799f47b0fa5
| 0.490343 | 3.85124 | false | false | false | false |
luebbers/reconos
|
support/threads/shared/rank_filter3x3.vhd
| 1 | 3,179 |
--
-- \file rank_filter3x3.vhd
--
-- Configurable 3x3 rank filter
--
-- \author Andreas Agne <[email protected]>
-- \date 21.11.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rank_filter3x3 is
Port (
shift_in : in STD_LOGIC_VECTOR (23 downto 0);
shift_out : out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
ien : in std_logic;
rst : in STD_LOGIC;
i : in STD_LOGIC_VECTOR (3 downto 0)
);
end entity;
architecture Behavioral of rank_filter3x3 is
signal row_a : std_logic_vector(23 downto 0);
signal row_b : std_logic_vector(23 downto 0);
signal row_c : std_logic_vector(23 downto 0);
signal pixels : std_logic_vector(71 downto 0); -- 9 pixels x 8 bit
-- instant sorting
function get_pixel( pixels : std_logic_vector(71 downto 0);
rank : std_logic_vector(3 downto 0)) return std_logic_vector
is
variable s : std_logic_vector(3 downto 0);
variable pixel_j : std_logic_vector(7 downto 0);
variable pixel_k : std_logic_vector(7 downto 0);
begin
for j in 0 to 8 loop -- for each pixel j
s := X"0";
pixel_j := pixels(j*8 + 7 downto j*8);
for k in 0 to 8 loop -- for each pixel k
pixel_k := pixels(k*8 + 7 downto k*8);
if k < j and pixel_k >= pixel_j then
s := s + 1;
elsif k > j and pixel_k > pixel_j then
s := s + 1;
end if;
end loop;
if s = rank then
return pixel_j;
end if;
end loop;
return X"00";
end function;
begin
pixels <= row_a & row_b & row_c;
shift : process(clk, rst)
begin
if rst = '1' then
row_a <= (others => '0');
row_b <= (others => '0');
row_c <= (others => '0');
elsif rising_edge(clk) then
if ien = '1' then
row_a <= shift_in;
row_b <= row_a;
row_c <= row_b;
end if;
shift_out <= get_pixel(pixels, rank);
end if;
end process;
end Behavioral;
|
gpl-3.0
|
a79d7ff6286f77a7bf066e1fdf029a0d
| 0.600503 | 3.314911 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/bd/system/ip/system_rst_processing_system7_0_50M_0/synth/system_rst_processing_system7_0_50M_0.vhd
| 1 | 6,798 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY system_rst_processing_system7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_processing_system7_0_50M_0;
ARCHITECTURE system_rst_processing_system7_0_50M_0_arch OF system_rst_processing_system7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rst_processing_system7_0_50M_0_arch : ARCHITECTURE IS "system_rst_processing_system7_0_50M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "system_rst_processing_system7_0_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_processing_system7_0_50M_0_arch;
|
gpl-2.0
|
eeb6ef4fef9f3b57993b279b9cb6680b
| 0.717711 | 3.459542 | false | false | false | false |
luebbers/reconos
|
tests/simulation/plb/mbox/test_mbox.vhd
| 1 | 2,292 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mbox is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mbox;
architecture Behavioral of test_mbox is
constant C_MB_IN : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_OUT : std_logic_vector(0 to 31) := X"00000001";
type t_state is (STATE_GET, STATE_PUT);
signal state : t_state := STATE_GET;
signal data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal data_inv : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= clk;
data_inv <= not data;
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_IN, data);
if done then
state <= STATE_PUT;
end if;
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_OUT, data_inv);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9ccfd1ad016bfb5710cdcf7434b2135c
| 0.592059 | 3.214586 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/ll_fifo.vhd
| 1 | 7,965 |
-------------------------------------------------------------------------------
--
-- Module : ll_fifo.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Top Level of LocalLink FIFO
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.ll_fifo_pkg.all;
entity ll_fifo is
generic (
MEM_TYPE : integer := 0; -- 0 choose BRAM,
-- 1 choose Distributed RAM
BRAM_MACRO_NUM : integer := 16; -- Memory Depth. For BRAM only (square nr only)
DRAM_DEPTH : integer := 16; -- Memory Depth. For DRAM only
WR_DWIDTH : integer := 32; -- FIFO write data width,
-- Acceptable values are
-- 8, 16, 32, 64, 128.
RD_DWIDTH : integer := 8; -- FIFO read data width,
-- Acceptable values are
-- 8, 16, 32, 64, 128.
RD_REM_WIDTH : integer := 1; -- Remainder width of read data
WR_REM_WIDTH : integer := 2; -- Remainder width of write data
USE_LENGTH : boolean := false; -- Length FIFO option
glbtm : time := 1 ns); -- Global timing delay for simulation
port (
-- Reset
areset_in: in std_logic;
-- clocks
write_clock_in: in std_logic;
read_clock_in: in std_logic;
-- Interface to downstream user application
data_out: out std_logic_vector(0 to RD_DWIDTH-1);
rem_out: out std_logic_vector(0 to RD_REM_WIDTH-1);
sof_out_n: out std_logic;
eof_out_n: out std_logic;
src_rdy_out_n: out std_logic;
dst_rdy_in_n: in std_logic;
-- Interface to upstream user application
data_in: in std_logic_vector(0 to WR_DWIDTH-1);
rem_in: in std_logic_vector(0 to WR_REM_WIDTH-1);
sof_in_n: in std_logic;
eof_in_n: in std_logic;
src_rdy_in_n: in std_logic;
dst_rdy_out_n: out std_logic;
-- FIFO status signals
fifostatus_out: out std_logic_vector(0 to 3);
-- Length Status
len_rdy_out: out std_logic;
len_out: out std_logic_vector(0 to 15);
len_err_out: out std_logic);
end ll_fifo;
architecture LL_FIFO_rtl of ll_fifo is
begin
BRAM_GEN: if MEM_TYPE = 0 generate
BRAMFIFO: ll_fifo_BRAM
generic map (
BRAM_MACRO_NUM => BRAM_MACRO_NUM,
WR_DWIDTH => WR_DWIDTH,
RD_DWIDTH => RD_DWIDTH,
RD_REM_WIDTH => RD_REM_WIDTH,
WR_REM_WIDTH => WR_REM_WIDTH,
USE_LENGTH => USE_LENGTH,
glbtm => glbtm )
port map (
-- Reset
reset => areset_in,
-- clocks
write_clock_in => write_clock_in,
read_clock_in => read_clock_in,
-- interface to upstream user application
data_in => data_in,
rem_in => rem_in,
sof_in_n => sof_in_n,
eof_in_n => eof_in_n,
src_rdy_in_n => src_rdy_in_n,
dst_rdy_out_n => dst_rdy_out_n,
-- interface to downstream user application
data_out => data_out,
rem_out => rem_out,
sof_out_n => sof_out_n,
eof_out_n => eof_out_n,
src_rdy_out_n => src_rdy_out_n,
dst_rdy_in_n => dst_rdy_in_n,
-- FIFO status signals
fifostatus_out => fifostatus_out,
-- Length signals
len_rdy_out => len_rdy_out,
len_out => len_out,
len_err_out => len_err_out);
end generate BRAM_GEN;
DRAM_GEN: if MEM_TYPE = 1 generate
DRAMFIFO: ll_fifo_DRAM
generic map (
DRAM_DEPTH => DRAM_DEPTH,
WR_DWIDTH => WR_DWIDTH,
RD_DWIDTH => RD_DWIDTH,
RD_REM_WIDTH => RD_REM_WIDTH,
WR_REM_WIDTH => WR_REM_WIDTH,
USE_LENGTH => USE_LENGTH,
glbtm => glbtm
)
port map (
-- Reset
reset => areset_in,
-- clocks
write_clock_in => write_clock_in,
read_clock_in => read_clock_in,
-- interface to upstream user application
data_in => data_in,
rem_in => rem_in,
sof_in_n => sof_in_n,
eof_in_n => eof_in_n,
src_rdy_in_n => src_rdy_in_n,
dst_rdy_out_n => dst_rdy_out_n,
-- interface to downstream user application
data_out => data_out,
rem_out => rem_out,
sof_out_n => sof_out_n,
eof_out_n => eof_out_n,
src_rdy_out_n => src_rdy_out_n,
dst_rdy_in_n => dst_rdy_in_n,
-- FIFO status signals
fifostatus_out => fifostatus_out,
len_rdy_out => len_rdy_out,
len_out => len_out,
len_err_out => len_err_out);
end generate DRAM_GEN;
end LL_FIFO_rtl;
|
gpl-3.0
|
b5e50cb1563b6755965ef61db242c5ee
| 0.411802 | 4.417637 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_const_package_pkg.vhd
| 3 | 1,266 |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Tests if constants in packages can be initialized with expressions
-- that normally require elaboration to be properly emitted.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package const_package_pkg is
constant c_bitstring : std_logic_vector(3 downto 0) := "1001";
constant c_aggregate : std_logic_vector(7 downto 0) := (7 => '1', 3 => '1', others => '0');
end const_package_pkg;
package body const_package_pkg is
end const_package_pkg;
|
gpl-2.0
|
23592562e3f1cab3019f44128268a602
| 0.735387 | 3.919505 | false | false | false | false |
wicker/learning-languages
|
vhdl/blink-leds/fpga/blink_led.vhd
| 1 | 801 |
-- Blink LEDs
-- Jenner Hanni
-- First program for the Terasic DE0-Nano
-----------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
-----------------------------------------
entity blink_led is
port (
clock_50 : in std_logic;
key : in std_logic_vector(1 downto 0);
led : out std_logic_vector(7 downto 0)
);
end entity;
-----------------------------------------
architecture behavioral of blink_led is
begin
process (clock_50) begin
if rising_edge(clock_50) then
case key is
when "11" => led <= "00011000";
when "01" => led <= "00001111";
when "10" => led <= "11110000";
when "00" => led <= "11111111";
end case;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
0e151b23a9a5a7c8dd58b331b5db0fe3
| 0.498127 | 3.778302 | false | false | false | false |
makestuff/vhdl
|
dpimfifo/topLevel.vhd
| 1 | 6,729 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic;
led : out std_logic_vector(1 downto 0)
);
end TopLevel;
architecture Behavioural of TopLevel is
component fifo_generator_v5_1 -- From CoreGen's .vho file
port(
clk : in std_logic;
din : in std_logic_vector(7 downto 0);
rd_en : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
dout : out std_logic_vector(7 downto 0);
empty : out std_logic;
full : out std_logic
);
end component;
attribute box_type : string;
attribute box_type of fifo_generator_v5_1 : component is "black_box";
type State is (
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- FIFO read/write enables, and data to be mux'd back to host
signal iWriteEnable : std_logic;
signal iReadEnable : std_logic;
signal iDataOutput : std_logic_vector(7 downto 0);
signal iFifoData : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
begin
fifo : fifo_generator_v5_1
port map(
clk => clk,
din => eppDataBus,
rd_en => iReadEnable,
rst => reset,
wr_en => iWriteEnable,
dout => iFifoData,
empty => led(0),
full => led(1)
);
-- Drive the outputs
eppAck <= iThisAck;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
iFifoData when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iWriteEnable <= '0'; -- No write to FIFO
iReadEnable <= '0'; -- No read from FIFO
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iWriteEnable <= '1'; -- Write to FIFO
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
if ( iThisRegAddr = "11" ) then
iReadEnable <= '1';
end if;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
gpl-3.0
|
015ae932347a28d0edbbafd7154d7c5a
| 0.58508 | 3.523037 | false | false | false | false |
five-elephants/hw-neural-sampling
|
activation.vhdl
| 1 | 10,496 |
library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
entity activation is
generic (
num_points : positive := 8;
lfsr_polynomial : lfsr_state_t;
tau : real := 20.0
);
port (
clk, reset : in std_ulogic;
membrane : in membrane_t;
active : out std_ulogic;
seed : in lfsr_state_t
);
end activation;
architecture behave of activation is
signal rng_out : lfsr_state_t;
begin
------------------------------------------------------------
rng: entity work.lfsr(rtl)
generic map(
width => lfsr_width
)
port map (
clk => clk,
reset => reset,
seed => seed,
poly => lfsr_polynomial,
rand_out => rng_out
);
------------------------------------------------------------
------------------------------------------------------------
process ( membrane, rng_out )
variable u, rand, cmp : real;
begin
u := real(to_integer(membrane)) / 2.0 ** membrane_fraction;
rand := real(to_integer(unsigned(rng_out))) / 2.0 ** lfsr_width;
cmp := 1.0 / (1.0 + exp(-u + log(20.0)));
if rand < cmp then
active <= '1';
else
active <= '0';
end if;
end process;
------------------------------------------------------------
end behave;
architecture rtl of activation is
constant lookup_width : integer := 4;
constant lookup_fraction : integer := 1;
subtype membrane_index_t is unsigned(lookup_width-1 downto 0);
subtype cmp_t is unsigned(lfsr_use_width-1 downto 0);
type lookup_t is array(0 to 15)
of cmp_t;
constant sigma_lookup : lookup_t :=
(
-- lookup for -u + log tau
8 => make_ufixed(0.000915, lfsr_use_width-lfsr_fraction, lfsr_fraction),
9 => make_ufixed(0.001508, lfsr_use_width-lfsr_fraction, lfsr_fraction),
10 => make_ufixed(0.002483, lfsr_use_width-lfsr_fraction, lfsr_fraction),
11 => make_ufixed(0.004087, lfsr_use_width-lfsr_fraction, lfsr_fraction),
12 => make_ufixed(0.006721, lfsr_use_width-lfsr_fraction, lfsr_fraction),
13 => make_ufixed(0.011033, lfsr_use_width-lfsr_fraction, lfsr_fraction),
14 => make_ufixed(0.018062, lfsr_use_width-lfsr_fraction, lfsr_fraction),
15 => make_ufixed(0.029434, lfsr_use_width-lfsr_fraction, lfsr_fraction),
0 => make_ufixed(0.047619, lfsr_use_width-lfsr_fraction, lfsr_fraction),
1 => make_ufixed(0.076158, lfsr_use_width-lfsr_fraction, lfsr_fraction),
2 => make_ufixed(0.119652, lfsr_use_width-lfsr_fraction, lfsr_fraction),
3 => make_ufixed(0.183063, lfsr_use_width-lfsr_fraction, lfsr_fraction),
4 => make_ufixed(0.269781, lfsr_use_width-lfsr_fraction, lfsr_fraction),
5 => make_ufixed(0.378544, lfsr_use_width-lfsr_fraction, lfsr_fraction),
6 => make_ufixed(0.501067, lfsr_use_width-lfsr_fraction, lfsr_fraction),
7 => make_ufixed(0.623462, lfsr_use_width-lfsr_fraction, lfsr_fraction)
-- 4.1
--16 => make_ufixed(0.000017, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--17 => make_ufixed(0.000028, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--18 => make_ufixed(0.000046, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--19 => make_ufixed(0.000075, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--20 => make_ufixed(0.000124, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--21 => make_ufixed(0.000204, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--22 => make_ufixed(0.000337, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--23 => make_ufixed(0.000555, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--24 => make_ufixed(0.000915, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--25 => make_ufixed(0.001508, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--26 => make_ufixed(0.002483, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--27 => make_ufixed(0.004087, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--28 => make_ufixed(0.006721, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--29 => make_ufixed(0.011033, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--30 => make_ufixed(0.018062, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--31 => make_ufixed(0.029434, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--0 => make_ufixed(0.047619, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--1 => make_ufixed(0.076158, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--2 => make_ufixed(0.119652, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--3 => make_ufixed(0.183063, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--4 => make_ufixed(0.269781, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--5 => make_ufixed(0.378544, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--6 => make_ufixed(0.501067, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--7 => make_ufixed(0.623462, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--8 => make_ufixed(0.731897, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--9 => make_ufixed(0.818210, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--10 => make_ufixed(0.881244, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--11 => make_ufixed(0.924440, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--12 => make_ufixed(0.952767, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--13 => make_ufixed(0.970809, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--14 => make_ufixed(0.982089, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--15 => make_ufixed(0.989059, lfsr_use_width-lfsr_fraction, lfsr_fraction)
-- 3.2
--16 => make_ufixed(0.000915, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--17 => make_ufixed(0.001175, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--18 => make_ufixed(0.001508, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--19 => make_ufixed(0.001935, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--20 => make_ufixed(0.002483, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--21 => make_ufixed(0.003186, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--22 => make_ufixed(0.004087, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--23 => make_ufixed(0.005242, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--24 => make_ufixed(0.006721, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--25 => make_ufixed(0.008614, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--26 => make_ufixed(0.011033, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--27 => make_ufixed(0.014123, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--28 => make_ufixed(0.018062, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--29 => make_ufixed(0.023073, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--30 => make_ufixed(0.029434, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--31 => make_ufixed(0.037481, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--0 => make_ufixed(0.047619, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--1 => make_ufixed(0.060328, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--2 => make_ufixed(0.076158, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--3 => make_ufixed(0.095718, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--4 => make_ufixed(0.119652, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--5 => make_ufixed(0.148586, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--6 => make_ufixed(0.183063, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--7 => make_ufixed(0.223440, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--8 => make_ufixed(0.269781, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--9 => make_ufixed(0.321752, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--10 => make_ufixed(0.378544, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--11 => make_ufixed(0.438874, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--12 => make_ufixed(0.501067, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--13 => make_ufixed(0.563227, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--14 => make_ufixed(0.623462, lfsr_use_width-lfsr_fraction, lfsr_fraction),
--15 => make_ufixed(0.680108, lfsr_use_width-lfsr_fraction, lfsr_fraction)
);
constant membrane_min : membrane_t := make_fixed(-4.0,
membrane_width-membrane_fraction-1,
membrane_fraction
);
constant membrane_max : membrane_t := make_fixed(3.5,
membrane_width-membrane_fraction-1,
membrane_fraction
);
constant log_tau : membrane_t := make_fixed(log(tau),
membrane_width-membrane_fraction-1,
membrane_fraction
);
signal x: membrane_t;
signal rng_out : lfsr_state_t;
begin
--x <= log_tau - membrane;
x <= membrane;
------------------------------------------------------------
rng: entity work.lfsr(rtl)
generic map(
width => lfsr_width
)
port map (
clk => clk,
reset => reset,
seed => seed,
poly => lfsr_polynomial,
rand_out => rng_out
);
------------------------------------------------------------
--process
--variable ln : line;
--variable u : membrane_index_t;
--begin
--write(ln, string'("log_tau = "));
--hwrite(ln, std_logic_vector(log_tau));
--writeline(output, ln);
--write(ln, string'("lookup values"));
--writeline(output, ln);
--for v in sigma_lookup'range loop
--write(ln, v);
--write(ln, string'(" : "));
--hwrite(ln, std_logic_vector(sigma_lookup(v)));
--writeline(output, ln);
--end loop;
--loop
--wait until x'event;
--u := unsigned(resize(
--shift_right(x,
--membrane_fraction-lookup_fraction
--),
--u'length
--));
--write(ln, string'("x: "));
--hwrite(ln, std_logic_vector(x));
--write(ln, string'(" u = "));
--hwrite(ln, std_logic_vector(u));
--write(ln, string'(" sigma_lookup(x) = "));
--hwrite(ln, std_logic_vector(sigma_lookup(to_integer(u))));
--writeline(output, ln);
--end loop;
--wait;
--end process;
------------------------------------------------------------
process ( x, rng_out )
variable u : membrane_index_t;
variable rand, cmp : cmp_t;
begin
if x < membrane_min then
active <= '1';
elsif x > membrane_max then
active <= '0';
else
u := unsigned(resize(
shift_right(x,
membrane_fraction-lookup_fraction
),
u'length
));
rand := resize(unsigned(rng_out), rand'length);
cmp := sigma_lookup(to_integer(u));
if rand(lfsr_fraction-1 downto 0) < cmp(lfsr_fraction-1 downto 0) then
active <= '1';
else
active <= '0';
end if;
end if;
end process;
------------------------------------------------------------
end rtl;
|
apache-2.0
|
1e076dcf702dd5ed89db4657f011c25e
| 0.625572 | 3.152899 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S36_S144.vhd
| 1 | 7,433 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S36_S144.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (36 and --
-- 128) made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S36_S144 is
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end entity BRAM_S36_S144;
architecture BRAM_S36_S144_arch of BRAM_S36_S144 is
component BRAM_S18_S72
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end component;
signal doa1 : std_logic_vector (15 downto 0);
signal dob1 : std_logic_vector (63 downto 0);
signal doa2 : std_logic_vector (15 downto 0);
signal dob2 : std_logic_vector (63 downto 0);
signal dia1 : std_logic_vector (15 downto 0);
signal dib1 : std_logic_vector (63 downto 0);
signal dia2 : std_logic_vector (15 downto 0);
signal dib2 : std_logic_vector (63 downto 0);
signal dipa1: std_logic_vector (1 downto 0);
signal dipa2: std_logic_vector (1 downto 0);
signal dopa1: std_logic_vector (1 downto 0);
signal dopa2: std_logic_vector (1 downto 0);
signal dipb1: std_logic_vector (7 downto 0);
signal dipb2: std_logic_vector (7 downto 0);
signal dopb1: std_logic_vector (7 downto 0);
signal dopb2: std_logic_vector (7 downto 0);
begin
dia1(15 downto 0) <= DIA(15 downto 0);
dia2(15 downto 0) <= DIA(31 downto 16);
dipa1(1 downto 0) <= DIPA(1 downto 0);
dipa2(1 downto 0) <= DIPA(3 downto 2);
DOA(15 downto 0) <= doa1;
DOA(31 downto 16) <= doa2;
DOPA(1 downto 0) <= dopa1;
DOPA(3 downto 2) <= dopa2;
dib1(15 downto 0) <= DIB(15 downto 0);
dib2(15 downto 0) <= DIB(31 downto 16);
dib1(31 downto 16) <= DIB(47 downto 32);
dib2(31 downto 16) <= DIB(63 downto 48);
dib1(47 downto 32) <= DIB(79 downto 64);
dib2(47 downto 32) <= DIB(95 downto 80);
dib1(63 downto 48) <= DIB(111 downto 96);
dib2(63 downto 48) <= DIB(127 downto 112);
DOB(15 downto 0) <= dob1(15 downto 0);
DOB(31 downto 16) <= dob2(15 downto 0);
DOB(47 downto 32) <= dob1(31 downto 16);
DOB(63 downto 48) <= dob2(31 downto 16);
DOB(79 downto 64) <= dob1(47 downto 32);
DOB(95 downto 80) <= dob2(47 downto 32);
DOB(111 downto 96) <= dob1(63 downto 48);
DOB(127 downto 112) <= dob2(63 downto 48);
dipb1(1 downto 0) <= DIPB(1 downto 0);
dipb2(1 downto 0) <= DIPB(3 downto 2);
dipb1(3 downto 2) <= DIPB(5 downto 4);
dipb2(3 downto 2) <= DIPB(7 downto 6);
dipb1(5 downto 4) <= DIPB(9 downto 8);
dipb2(5 downto 4) <= DIPB(11 downto 10);
dipb1(7 downto 6) <= DIPB(13 downto 12);
dipb2(7 downto 6) <= DIPB(15 downto 14);
DOPB(1 downto 0) <= dopb1(1 downto 0);
DOPB(3 downto 2) <= dopb2(1 downto 0);
DOPB(5 downto 4) <= dopb1(3 downto 2);
DOPB(7 downto 6) <= dopb2(3 downto 2);
DOPB(9 downto 8) <= dopb1(5 downto 4);
DOPB(11 downto 10) <= dopb2(5 downto 4);
DOPB(13 downto 12) <= dopb1(7 downto 6);
DOPB(15 downto 14) <= dopb2(7 downto 6);
bram1: BRAM_S18_S72
port map (
ADDRA => addra(10 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: BRAM_S18_S72
port map (
ADDRA => addra(10 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S36_S144_arch;
|
gpl-3.0
|
91ce1e1dff416226500d3e26b9fb5a32
| 0.458765 | 3.964267 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/fifo_utils.vhd
| 1 | 44,568 |
-------------------------------------------------------------------------------
--
-- Module : fifo_utils.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Utility package created for LocalLink FIFO Design
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package fifo_u is
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- data type conversion functions
function to_character (bv : bit_vector(3 downto 0)) return character;
function conv_ascii_logic_vector(nib:std_logic_vector(3 downto 0))
return std_logic_vector;
function to_string (bv : bit_vector) return string;
function to_string (b : bit) return string;
function conv_std_logic_vector (ch : character) return std_logic_vector;
function to_std_logic_vector (b : bit_vector) return std_logic_vector;
function to_std_logic (b : bit) return std_logic;
function boolean_to_std_logic (b : boolean) return std_logic;
function to_bit_vector (a : std_logic_vector) return bit_vector;
function slv2int (S: std_logic_vector) return integer;
function bitv2int (S: bit_vector) return integer;
function int2bv (int_value, width : integer) return bit_vector;
function revByteOrder( arg : std_logic_vector) return std_logic_vector;
-- arithmetic
function log2 (i: natural) return natural;
function POWER2 (p: integer) return integer;
function SQUARE2 (p: integer) return integer;
function maxNat (arg1, arg2 : natural) return natural;
function allZeroes (inp : std_logic_vector) return boolean;
function allOnes (inp : std_logic_vector) return boolean;
function bin_to_gray ( a : std_logic_vector) return std_logic_vector;
function gray_to_bin ( a : std_logic_vector) return std_logic_vector;
function bit_duplicate (b : std_logic; size : natural) return std_logic_vector;
-- FIFO related functions
function GET_ADDR_WIDTH (dw : integer) return integer;
function GET_ADDR_MAJOR_WIDTH (a ,b : integer) return integer;
function GET_ADDR_MINOR_WIDTH (a ,b : integer) return integer;
function GET_WIDTH (i, a, b, m, RorW : integer) return integer;
function GET_MAX_WIDTH(a, b: integer) return integer;
function GET_CTRL_WIDTH(ra,wa,rb,wb:integer) return integer;
function GET_HIGH_VALUE(ra,wa: integer) return integer;
function GET_ADDR_FULL_B(ra, wa, RorW: integer) return integer;
function GET_ADDR_MAJOR_WIDTH(ra, wa, RorW: integer) return integer;
function GET_REM_WIDTH(a: integer) return integer;
function GET_PAR_WIDTH(a: integer) return integer;
function GET_EOF_REM_WIDTH(ra, wa: integer) return integer;
function GET_RATIO(ra, wa, par: integer) return integer;
function GET_WR_SOF_EOF_WIDTH(ra, wa : integer) return integer;
function GET_RD_SOF_EOF_WIDTH(ra, wa : integer) return integer;
function GET_WR_CTRL_REM_WIDTH(ra, wa : integer) return integer;
function GET_RD_CTRL_REM_WIDTH(ra, wa : integer) return integer;
function GET_C_WR_ADDR_WIDTH(ra, wa, mem_num: integer) return integer;
function GET_C_RD_ADDR_WIDTH(ra, wa, mem_num: integer) return integer;
function GET_C_RD_TEMP_WIDTH(ra, wa: integer) return integer;
function GET_C_WR_TEMP_WIDTH(ra, wa: integer) return integer;
function GET_WR_PAD_WIDTH(rd, wd, c_wa, waf, wa: integer) return integer;
function GET_RD_PAD_WIDTH(da, db: integer) return integer;
function GET_NUM_DIV(ra, wa : integer) return integer;
function GET_WR_EN_FACTOR(NUM_DIV, MEM_NUM: integer) return integer;
function GET_RDDWdivWRDW(RD_DWIDTH, WR_DWIDTH : integer) return integer;
function GET_WRDW_div_RDDW(RD_DWIDTH, WR_DWIDTH : integer) return integer;
end fifo_u;
package body fifo_u is
-------------------------------------------------------------------------------
-- data type conversion functions
-------------------------------------------------------------------------------
-- duplicate the bit value to specific width, e.g. '1' -> "1111"
function bit_duplicate (b : std_logic; size : natural)
return std_logic_vector is
variable o : std_logic_vector(size -1 downto 0);
begin
for i in size -1 downto 0 loop
o(i) := b;
end loop;
return o;
end function;
-- convert a character to a nibble wide std_logic_vector
function conv_std_logic_vector (ch : character) return std_logic_vector is
begin
case ch is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' => return "1010";
when 'b' => return "1011";
when 'c' => return "1100";
when 'd' => return "1101";
when 'e' => return "1110";
when 'f' => return "1111";
when others => assert false report "unrecognised character"
severity failure;
end case;
return "0000";
end conv_std_logic_vector;
-- convert bit to std_logic
function to_std_logic (b : bit) return std_logic is
begin
case b is
when '0' => return '0';
when '1' => return '1';
when others => assert false report "unrecognised bit value"
severity failure;
end case;
return '0';
end to_std_logic;
-- convert boolean to std_logic
function boolean_to_std_logic (b : boolean) return std_logic is
begin
case b is
when FALSE => return '0';
when TRUE => return '1';
when others => return '0';
end case;
return '0';
end boolean_to_std_logic;
-- Convert 4-bit vector to a character
function to_character (bv : bit_vector(3 downto 0)) return character is
begin -- to_character
case bv is
when b"0000" => return '0';
when b"0001" => return '1';
when b"0010" => return '2';
when b"0011" => return '3';
when b"0100" => return '4';
when b"0101" => return '5';
when b"0110" => return '6';
when b"0111" => return '7';
when b"1000" => return '8';
when b"1001" => return '9';
when b"1010" => return 'a';
when b"1011" => return 'b';
when b"1100" => return 'c';
when b"1101" => return 'd';
when b"1110" => return 'e';
when b"1111" => return 'f';
end case;
end to_character;
function conv_ascii_logic_vector (nib : std_logic_vector(3 downto 0))
return std_logic_vector is
begin
case nib is
when "0000" => return "00110000";
when "0001" => return "00110001";
when "0010" => return "00110010";
when "0011" => return "00110011";
when "0100" => return "00110100";
when "0101" => return "00110101";
when "0110" => return "00110110";
when "0111" => return "00110111";
when "1000" => return "00111000";
when "1001" => return "00111001";
when "1010" => return "01000001";
when "1011" => return "01000010";
when "1100" => return "01000011";
when "1101" => return "01000100";
when "1110" => return "01000101";
when "1111" => return "01000110";
when others => return "00100000";
end case;
return "00100000";
end conv_ascii_logic_vector;
-- Convert n-bits vector to n/4-character string
function to_string (bv : bit_vector) return string is
constant strlen : integer := bv'length / 4;
variable str : string(1 to strlen);
begin -- to_string
for i in 0 to strlen - 1 loop
str(strlen-i) := to_character(bv((i * 4) + 3 downto (i * 4)));
end loop; -- i
return str;
end to_string;
-- Convert 1-bit to 1-character string
function to_string (b : bit) return string is
begin
case b is
when '0' => return "0";
when '1' => return "1";
when others => assert false report "unrecognised bit value"
severity failure;
end case;
return "0";
end to_string;
-- Convert std_logic_vector to bit_vector
function to_bit_vector (a : std_logic_vector) return bit_vector is
variable b : bit_vector(a'length -1 downto 0);
begin
for i in 0 to a'length - 1 loop
b(i) := to_bit (a(i));
end loop;
return b;
end to_bit_vector;
-- Convert bit_vector to std_logic_vector
function to_std_logic_vector (b : bit_vector) return std_logic_vector is
variable a : std_logic_vector(b'length -1 downto 0);
begin
for i in 0 to b'length - 1 loop
a(i) := to_std_logic (b(i));
end loop;
return a;
end to_std_logic_vector;
-- std_logic_vector to integer
function slv2int (S: std_logic_vector) return integer is
variable S_i: std_logic_vector(S'Length-1 downto 0) := S;
variable N : integer := 0;
begin
for i in S_i'Right to S_i'Left loop
if (S_i(i)) = '1' then
N := N + (2**i);
elsif (S_i(i)) = 'X' then
N := 0;
end if;
end loop;
return N;
end;
-- bit_vector to integer
function bitv2int (S: bit_vector) return integer is
variable S_i: bit_vector(S'Length-1 downto 0) := S;
variable N : integer := 0;
begin
for i in S_i'Right to S_i'Left loop
if (S_i(i)) = '1' then
N := N + (2**i);
end if;
end loop;
return N;
end;
function int2bv (int_value, width : integer) return bit_vector is
variable result : bit_vector(width-1 downto 0) := (others => '0');
begin
for i in 0 to width-1 loop
if ( ((int_value/(2**i)) mod 2) = 1) then
result(i) := '1';
end if;
end loop;
return result;
end int2bv;
function revByteOrder( arg : std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector(arg'high downto 0); -- length is numNibs
variable numbytes : integer;
begin
numbytes := arg'length/8;
lp0: for i in 0 to numbytes -1 loop
tmp( (8*(numbytes-i)-1) downto 8*(numbytes-i-1) ) := arg( (8*i+7) downto 8*i);
end loop lp0;
return tmp ;
end revbyteOrder;
-------------------------------------------------------------------------------
-- arithmetic
-------------------------------------------------------------------------------
function allZeroes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '1' then
t := false;
end if;
end loop;
return t;
end allZeroes;
function allOnes (inp : std_logic_vector) return boolean is
variable t : boolean := true;
begin
t := true; -- for synopsys
for i in inp'range loop
if inp(i) = '0' then
t := false;
end if;
end loop;
return t;
end allOnes;
-- returns the maximum of two naturals
function maxNat (arg1, arg2 : natural)
return natural is
begin -- maxNat
if arg1 >= arg2 then
return arg1;
else
return arg2;
end if;
end maxNat;
-- a function to calculate log2(i)
function log2 (i: natural) return natural is
variable answer : natural ;
begin
for n in 1 to 32 loop -- works for upto 32 bits
if (2**(n-1) < i) and (2**n >= i) then
return (n);
end if;
end loop;
return (1);
end log2;
-- a function to caculate 2 ** p
function POWER2 ( p: in integer) return integer is
variable answer : integer ;
begin
answer := 2**p;
return answer;
end function POWER2;
-- a function to caculate square2(p)
function SQUARE2 ( p: in integer) return integer is
variable answer : integer ;
begin
case p is
when 1 => answer := 0;
when 2 => answer := 1;
when 4 => answer := 2;
when 8 => answer := 3;
when 16 => answer := 4;
when 32 => answer := 5;
when 64 => answer := 6;
when 128 => answer := 7;
when 256 => answer := 8;
when 512 => answer := 9;
when 1024 => answer := 10;
when others => assert false report "overflow or input exceeds acceptable range." severity failure;
end case;
return answer;
end function SQUARE2;
-- convert binary code to gray code
function bin_to_gray ( a : std_logic_vector) return std_logic_vector is
variable b : std_logic_vector(a'range);
begin
b(b'high) := a(a'high);
for i in b'high -1 downto 0 loop
b(i) := a(i+1) XOR a(i);
end loop;
return b;
end function;
-- conver gray code to binary code
function gray_to_bin ( a : std_logic_vector) return std_logic_vector is
variable b : std_logic_vector(a'range);
begin
for i in a'range loop
if i = a'left then
b(i) := a(i);
else
b(i) := a(i) xor b(i+1);
end if;
end loop;
return b;
end function;
-- generate the address width according to the data width, for FIFO
function GET_ADDR_WIDTH (dw : in integer) return integer is
variable aw : integer;
begin
case dw is
when 1 => aw := 14;
when 2 => aw := 13;
when 4 => aw := 12;
when 8 => aw := 11;
when 16=> aw := 10;
when 32=> aw := 9;
when 64=> aw := 9;
when 128=> aw := 9;
when others => assert false report "input is not acceptable." severity failure;
end case;
return aw;
end function GET_ADDR_WIDTH;
-- generate the major address width, for FIFO
function GET_ADDR_MAJOR_WIDTH (a , b: in integer) return integer is
variable result : integer;
begin
if a < b then -- A's data width is shorter than B's data width
-- Then A's addr width is longer than B's addr width
-- The Major & Minor Addrs are positive. The major addr is equal to
-- B's address width
result := GET_ADDR_WIDTH(b);
else -- otherwise, No minor addr exsits
result := GET_ADDR_WIDTH(a);
end if;
return result;
end function GET_ADDR_MAJOR_WIDTH;
-- generate the minor address width, for BRAM_FIFO
function GET_ADDR_MINOR_WIDTH (a , b : in integer) return integer is
variable result : integer;
begin
if a < b then -- A's data width is shorter than B's data width
-- Then A's addr width is longer than B's addr width
-- The Major & Minor Addrs are positive. The minor addr is equal to
-- the differential value between A & B's address width
if b > 32 then
if b = 64 then
result := GET_ADDR_WIDTH(a)+1 - GET_ADDR_WIDTH(b);
elsif b = 128 then
if a = 64 then
result := GET_ADDR_WIDTH(a)+1 - GET_ADDR_WIDTH(b);
else
result := GET_ADDR_WIDTH(a)+2 - GET_ADDR_WIDTH(b);
end if;
end if;
else
result := GET_ADDR_WIDTH(a) - GET_ADDR_WIDTH(b);
end if;
elsif a > b then -- otherwise, invert the result
-- It may be zero which means no minor address exsits.
if a > 32 then
if a = 64 then
result := GET_ADDR_WIDTH(b)+1 - GET_ADDR_WIDTH(a);
elsif a = 128 then
if b = 64 then
result := GET_ADDR_WIDTH(b)+1 - GET_ADDR_WIDTH(a);
else
result := GET_ADDR_WIDTH(b)+2 - GET_ADDR_WIDTH(a);
end if;
end if;
else
result := GET_ADDR_WIDTH(b) - GET_ADDR_WIDTH(a);
end if;
else
result := 1;
end if;
return result;
end function GET_ADDR_MINOR_WIDTH;
function GET_WIDTH (i, a, b, m, RorW : in integer) return integer is
-- m: 1 get major address width; 2 get minor address width
-- RorW: 0 : Rd 1: Wr
-- a: Rd data width ; b: Wr data width
variable result : integer;
begin
if a < b then
if m = 1 then
result := i;
elsif m = 2 then
if RorW = 0 then
result := SQUARE2(b) - SQUARE2(a);
else
result := 1;
end if;
end if;
else -- Rd > Wr
if m = 1 then
result := i;
elsif m = 2 then
if RorW = 0 then --
result := 1;
else
result := SQUARE2(a) - SQUARE2(b);
end if;
end if;
end if;
if result = 0 then
result := result + 1;
return result;
else
return result;
end if;
end function GET_WIDTH;
function GET_MAX_WIDTH(a, b: in integer) return integer is
variable result: integer;
begin
if a < b then
result := b;
else
result := a;
end if;
return result;
end function GET_MAX_WIDTH;
function GET_CTRL_WIDTH(ra,wa,rb,wb: integer) return integer is
variable result: integer;
begin
if rb < wb then
result := wa + 2;
else
result := ra + 2;
end if;
return result;
end function GET_CTRL_WIDTH;
function GET_HIGH_VALUE(ra,wa: integer) return integer is
variable result: integer;
begin
if (wa > ra) then
result := wa - ra;
else
result := 1;
end if;
return result;
end function GET_HIGH_VALUE;
function GET_ADDR_FULL_B(ra, wa, RorW: integer) return integer is
variable result : integer;
begin
if (ra > wa) then
if RorW = 0 then
result := GET_ADDR_WIDTH(ra);
elsif RorW = 1 then
if ra > 36 then
if ra = 64 then
result := GET_ADDR_WIDTH(wa)+1;
elsif ra = 128 then
if wa = 64 then
result := GET_ADDR_WIDTH(wa) + 1;
else
result := GET_ADDR_WIDTH(wa) + 2;
end if;
end if;
else
result := GET_ADDR_WIDTH(wa);
end if;
end if;
else
if RorW = 0 then
if wa > 36 then
if wa = 64 then
result := GET_ADDR_WIDTH(ra)+1;
elsif wa = 128 then
if ra = 64 then
result := GET_ADDR_WIDTH(ra) + 1;
else
result := GET_ADDR_WIDTH(ra) + 2;
end if;
end if;
else
result := GET_ADDR_WIDTH(ra);
end if;
elsif RorW = 1 then
result := GET_ADDR_WIDTH(wa);
end if;
end if;
return result;
end function GET_ADDR_FULL_B;
function GET_ADDR_MAJOR_WIDTH(ra, wa, RorW: integer) return integer is
variable result : integer;
begin
if ra > wa then
if RorW = 0 then
result := GET_ADDR_WIDTH(ra);
elsif RorW = 1 then
if ra > 36 then
if ra = 64 then
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa) + 1;
elsif ra = 128 then
if wa = 64 then
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa) + 1;
else
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa) + 2;
end if;
end if;
else
result := GET_ADDR_WIDTH(wa) - GET_ADDR_MINOR_WIDTH (ra, wa);
end if;
end if;
elsif ra < wa then
if RorW = 0 then
if wa > 36 then
if wa = 64 then
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa)+1;
elsif wa = 128 then
if ra = 64 then
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa)+1;
else
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa)+2;
end if;
end if;
else
result := GET_ADDR_WIDTH(ra) - GET_ADDR_MINOR_WIDTH (ra, wa);
end if;
elsif RorW = 1 then
result := GET_ADDR_WIDTH(wa);
end if;
else
if RorW = 0 then
result := GET_ADDR_WIDTH(ra);
else
result := GET_ADDR_WIDTH(wa);
end if;
end if;
return result;
end function GET_ADDR_MAJOR_WIDTH;
function GET_REM_WIDTH(a: integer) return integer is
variable result : integer;
begin
if a = 0 then
result := 1;
else
result := a;
end if;
return result;
end function GET_REM_WIDTH;
function GET_PAR_WIDTH(a: integer) return integer is
variable result : integer;
begin
case a is
when 8 => result := 1;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 16;
when others => NULL;
end case;
return result;
end function GET_PAR_WIDTH;
function GET_EOF_REM_WIDTH(ra, wa: integer) return integer is
variable result : integer;
begin
if ra > wa then
result := ra;
else
result := wa;
end if;
return result;
end function GET_EOF_REM_WIDTH;
function GET_RATIO(ra, wa, par: integer) return integer is
variable result : integer;
begin
result := (par * ra) / wa;
return result;
end function GET_RATIO;
function GET_WR_SOF_EOF_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 4;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 8;
when 16 => result := 4;
when 32 => result := 4;
when 64 => result := 4;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 16;
when 16 => result := 8;
when 32 => result := 8;
when 64 => result := 8;
when 128 => result := 8;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 32;
when 16 => result := 32;
when 32 => result := 8;
when 64 => result := 16;
when 128 => result := 16;
when others => NULL;
end case;
end if;
return result;
end function GET_WR_SOF_EOF_WIDTH;
function GET_RD_SOF_EOF_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 8;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 8;
when 128 => result := 16;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 2;
when 128 => result := 16;
when others => NULL;
end case;
end if;
return result;
end function GET_RD_SOF_EOF_WIDTH;
function GET_WR_CTRL_REM_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 1;
when 16 => result := 2;
when 32 => result := 1;
when 64 => result := 3;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 2;
when 16 => result := 1;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 2;
when 16 => result := 2;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 16;
when 16 => result := 4;
when 32 => result := 4;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 16;
when 16 => result := 8;
when 32 => result := 16;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_WR_CTRL_REM_WIDTH;
function GET_RD_CTRL_REM_WIDTH(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 => result := 1;
when 16 => result := 2;
when 32 => result := 4;
when 64 => result := 3;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 4;
when 16 => result := 1;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 4;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 2;
when 16 => result := 1;
when 32 => result := 2;
when 64 => result := 4;
when 128 => result := 16;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 16;
when 16 => result := 1;
when 32 => result := 4;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 16;
when 16 => result := 1;
when 32 => result := 4;
when 64 => result := 3;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_RD_CTRL_REM_WIDTH;
function GET_C_WR_ADDR_WIDTH(ra, wa, mem_num: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 =>
if mem_num < 8 then
result := 13;
elsif mem_num = 8 then
result := 14;
elsif mem_num = 16 then
result := 15;
else
result := 16;
end if;
when 16 => result := 13;
when 32 => result := 13;
when 64 =>
if mem_num <= 4 then
result := 11;
elsif mem_num = 8 then
result := 12;
elsif mem_num = 16 then
result := 13;
else
result := 14;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 12;
when 16 => result := 14;
when 32 => result := 13;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 13;
when 16 => result := 13;
when 32 => result := 12;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 13;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 =>
if mem_num <= 2 then
result := 10;
elsif mem_num = 4 then
result := 11;
elsif mem_num = 8 then
result := 12;
elsif mem_num = 16 then
result := 13;
else
result := 14;
end if;
when 16 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 32 => result := 12;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 10;
when 16 => result := 8;
when 32 => result := 11;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_C_WR_ADDR_WIDTH;
function GET_C_RD_ADDR_WIDTH(ra, wa, mem_num: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 8 =>
if mem_num < 8 then
result := 13;
elsif mem_num = 8 then
result := 14;
elsif mem_num = 16 then
result := 15;
else
result := 16;
end if;
when 16 => result := 13;
when 32 => result := 13;
when 64 =>
if mem_num <= 4 then
result := 11;
elsif mem_num = 8 then
result := 12;
elsif mem_num = 16 then
result := 13;
else
result := 14;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 13;
when 16 => result := 14;
when 32 => result := 13;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 11;
when others => NULL;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 13;
when 16 => result := 14;
when 32 => result := 12;
when 64 =>
if mem_num <= 8 then
result := 12;
else
result := 13;
end if;
when 128 => result := 13;
when others => NULL;
end case;
elsif wa = 64 then
case ra is
when 8 =>
if mem_num <= 2 then
result := 13;
elsif mem_num = 4 then
result := 14;
elsif mem_num = 8 then
result := 15;
elsif mem_num = 16 then
result := 16;
else
result := 17;
end if;
when 16 =>
if mem_num <= 8 then
result := 14;
else
result := 15;
end if;
when 32 => result := 12;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
elsif wa = 128 then
case ra is
when 8 => result := 13;
when 16 => result := 8;
when 32 => result := 13;
when 64 => result := 2;
when 128 => result := 2;
when others => NULL;
end case;
end if;
return result;
end function GET_C_RD_ADDR_WIDTH;
function GET_C_RD_TEMP_WIDTH(ra, wa: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 16 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 8;
when 16 => result := 8;
when 32 => result := 8;
when others => result := 8;
end case;
elsif wa = 64 then
case ra is
when 16 => result := 8;
when 8 => result := 8;
when 128 => result := 16;
when others => result := 8;
end case;
elsif wa = 128 then
case ra is
when 16 => result := 4;
when 64 => result := 8;
when others => result := 8;
end case;
else
result := 8;
end if;
return result;
end function GET_C_RD_TEMP_WIDTH;
function GET_C_WR_TEMP_WIDTH(ra, wa: integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 16 then
case ra is
when 64 => result := 8;
when 128 => result := 8;
when others => result := 8;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 8;
when 16 => result := 8;
when 32 => result := 8;
when others => result := 8;
end case;
elsif wa = 64 then
case ra is
when 16 => result := 8;
when 8 => result := 8;
when others => result := 8;
end case;
elsif wa = 128 then
case ra is
when 16 => result := 32;
when 64 => result := 16;
when others => result := 8;
end case;
else
result := 8;
end if;
return result;
end function GET_C_WR_TEMP_WIDTH;
function GET_WR_PAD_WIDTH(rd, wd, c_wa, waf, wa: integer) return integer is
variable result: integer;
begin
if rd> wd then
if c_wa - wa >= 0 then
result := c_wa - wa;
else
result := 0;
end if;
else
if c_wa - waf >= 0 then
result := c_wa - waf;
else
result := 0;
end if;
end if;
return result;
end function GET_WR_PAD_WIDTH;
function GET_RD_PAD_WIDTH(da, db: integer) return integer is
variable result : integer;
begin
if da-db >= 0 then
result := da - db;
else
result := 0;
end if;
return result;
end function GET_RD_PAD_WIDTH;
function GET_NUM_DIV(ra, wa : integer) return integer is
variable result : integer;
begin
if wa = 8 then
case ra is
when 16 => result := 8;
when 64 => result := 2;
when others => result := 1;
end case;
elsif wa = 16 then
case ra is
when 8 => result := 4;
when others => result := 1;
end case;
elsif wa = 32 then
case ra is
when 8 => result := 4;
when others => result := 1;
end case;
elsif wa = 64 then
case ra is
when 8 => result := 2;
when others => result := 1;
end case;
else
result := 1;
end if;
return result;
end function GET_NUM_DIV;
function GET_WR_EN_FACTOR(NUM_DIV, MEM_NUM: integer) return integer is
variable result : integer;
begin
if MEM_NUM < NUM_DIV then
result :=1;
else
result := MEM_NUM/NUM_DIV;
end if;
return result;
end function GET_WR_EN_FACTOR;
function GET_RDDWdivWRDW(RD_DWIDTH, WR_DWIDTH : integer) return integer is
variable result : integer;
begin
if RD_DWIDTH > WR_DWIDTH then
result := RD_DWIDTH / WR_DWIDTH;
else
result := 1;
end if;
return result;
end function GET_RDDWdivWRDW;
function GET_WRDW_div_RDDW(RD_DWIDTH, WR_DWIDTH : integer) return integer is
variable result : integer;
begin
if WR_DWIDTH > RD_DWIDTH then
result := WR_DWIDTH / RD_DWIDTH;
else
result := 1;
end if;
return result;
end function GET_WRDW_div_RDDW;
end fifo_u;
|
gpl-3.0
|
1a069423514f52ba4a1d32e51c1e5450
| 0.438498 | 4.61701 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S18_S72.vhd
| 1 | 7,404 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S18_S72.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (16 and 64) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S18_S72 is
port (ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end entity BRAM_S18_S72;
architecture BRAM_S18_S72_arch of BRAM_S18_S72 is
component RAMB16_S9_S36
port (
ADDRA: in std_logic_vector(10 downto 0);
ADDRB: in std_logic_vector(8 downto 0);
DIA: in std_logic_vector(7 downto 0);
DIPA: in std_logic_vector(0 downto 0);
DIB: in std_logic_vector(31 downto 0);
DIPB: in std_logic_vector(3 downto 0);
WEA: in std_logic;
WEB: in std_logic;
CLKA: in std_logic;
CLKB: in std_logic;
SSRA: in std_logic;
SSRB: in std_logic;
ENA: in std_logic;
ENB: in std_logic;
DOA: out std_logic_vector(7 downto 0);
DOPA: out std_logic_vector(0 downto 0);
DOB: out std_logic_vector(31 downto 0);
DOPB: out std_logic_vector(3 downto 0));
END component;
signal doa1 : std_logic_vector (7 downto 0);
signal dob1 : std_logic_vector (31 downto 0);
signal doa2 : std_logic_vector (7 downto 0);
signal dob2 : std_logic_vector (31 downto 0);
signal dia1 : std_logic_vector (7 downto 0);
signal dib1 : std_logic_vector (31 downto 0);
signal dia2 : std_logic_vector (7 downto 0);
signal dib2 : std_logic_vector (31 downto 0);
signal dipa1: std_logic_vector(0 downto 0);
signal dipa2: std_logic_vector(0 downto 0);
signal dopa1: std_logic_vector(0 downto 0);
signal dopa2: std_logic_vector(0 downto 0);
signal dipb1: std_logic_vector(3 downto 0);
signal dipb2: std_logic_vector(3 downto 0);
signal dopb1: std_logic_vector(3 downto 0);
signal dopb2: std_logic_vector(3 downto 0);
begin
dia1 <= DIA(7 downto 0);
dia2 <= DIA(15 downto 8);
dipa1 <= DIPA(0 downto 0);
dipa2 <= DIPA(1 downto 1);
dib1(7 downto 0) <= DIB(7 downto 0);
dib2(7 downto 0) <= DIB(15 downto 8);
dib1(15 downto 8) <= DIB(23 downto 16);
dib2(15 downto 8) <= DIB(31 downto 24);
dib1(23 downto 16) <= DIB(39 downto 32);
dib2(23 downto 16) <= DIB(47 downto 40);
dib1(31 downto 24) <= DIB(55 downto 48);
dib2(31 downto 24) <= DIB(63 downto 56);
dipb1(0 downto 0) <= DIPB(0 downto 0);
dipb2(0 downto 0) <= DIPB(1 downto 1);
dipb1(1 downto 1) <= DIPB(2 downto 2);
dipb2(1 downto 1) <= DIPB(3 downto 3);
dipb1(2 downto 2) <= DIPB(4 downto 4);
dipb2(2 downto 2) <= DIPB(5 downto 5);
dipb1(3 downto 3) <= DIPB(6 downto 6);
dipb2(3 downto 3) <= DIPB(7 downto 7);
DOA(7 downto 0) <= doa1;
DOA(15 downto 8) <= doa2;
DOPA(0 downto 0) <= dopa1;
DOPA(1 downto 1) <= dopa2;
DOPB(0 downto 0) <= dopb1(0 downto 0);
DOPB(1 downto 1) <= dopb2(0 downto 0);
DOPB(2 downto 2) <= dopb1(1 downto 1);
DOPB(3 downto 3) <= dopb2(1 downto 1);
DOPB(4 downto 4) <= dopb1(2 downto 2);
DOPB(5 downto 5) <= dopb2(2 downto 2);
DOPB(6 downto 6) <= dopb1(3 downto 3);
DOPB(7 downto 7) <= dopb2(3 downto 3);
DOB(7 downto 0) <= dob1(7 downto 0);
DOB(15 downto 8) <= dob2(7 downto 0);
DOB(23 downto 16) <= dob1(15 downto 8);
DOB(31 downto 24) <= dob2(15 downto 8);
DOB(39 downto 32) <= dob1(23 downto 16);
DOB(47 downto 40) <= dob2(23 downto 16);
DOB(55 downto 48) <= dob1(31 downto 24);
DOB(63 downto 56) <= dob2(31 downto 24);
bram1: RAMB16_S9_S36
port map (
ADDRA => addra(10 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: RAMB16_S9_S36
port map (
ADDRA => addra(10 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S18_S72_arch;
|
gpl-3.0
|
509346776b4890705e5a15578866d052
| 0.449487 | 3.991375 | false | false | false | false |
denis4net/hw_design
|
1/altera-project/src/main.vhd
| 1 | 2,940 |
-- Varian number is 4
-- Issue: 4-bit simple ALU ("+", "-", "+1")
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity main is
generic (
bus_width: integer := 4;
op_width: integer := 2
);
port (
a: in std_logic_vector(bus_width-1 downto 0);
b: in std_logic_vector(bus_width-1 downto 0);
op: in std_logic_vector(op_width-1 downto 0);
c: out std_logic_vector(bus_width-1 downto 0)
);
begin
end main;
architecture ALU1 of main is
component add_4_bits
port (
x: in std_logic_vector(3 downto 0);
y: in std_logic_vector(3 downto 0);
cin: in std_logic;
sum: out std_logic_vector(3 downto 0)
);
end component;
component busmux4x4
port (
in_bus: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(3 downto 0);
out_bus: out std_logic_vector(3 downto 0)
);
end component;
signal results: std_logic_vector(15 downto 0);
signal sel: std_logic_vector(3 downto 0);
signal b_inverted, b_additional: std_logic_vector(3 downto 0);
begin
results(3 downto 0) <= b"0000";
adder_4: add_4_bits port map(a, b, '0', results(7 downto 4));
additional_code_unit: add_4_bits port map(b_inverted, b"0001", '0', b_additional);
subber_4: add_4_bits port map(a, b_additional, '0', results(11 downto 8));
inc_4: add_4_bits port map(a, b"0001", '0', results(15 downto 12));
--results(15 downto 8) <= b"00000000";
sel(0) <= not op(1) and not op(0);
sel(1) <= not op(1) and op(0);
sel(2) <= op(1) and not op(0);
sel(3) <= op(1) and op(0);
b_inverted <= not b;
result_busmux: busmux4x4 port map (in_bus=>results, sel=>sel, out_bus=>c);
end ALU1;
-- A signal assignment statement represents a process that assigns values to signals. It has three basic formats.
-- A <= B when condition1 elseC when condition2 else D when condition3 else E;
architecture ALU2 of main is
begin
c <= a + b when conv_integer(op) = 1
else
a - b when conv_integer(op) = 2
else
a + 1 when conv_integer(op) = 3
else
b"0000";
end ALU2;
-- with expression select A <= B when choice1, C when choice2, D when choice3, E when others;
architecture ALU3 of main is
begin
with conv_integer(op) select
c <= a + b when 1,
a -b when 2,
a + 1 when 3,
b"0000" when others;
end ALU3;
-- Using parallel assignment and if condition statement
architecture ALU4 of main is
begin
process (a, b, op) begin
if conv_integer(op) = 1 then
c <= a + b;
elsif conv_integer(op) = 2 then
c <= a - b;
elsif conv_integer(op) = 3 then
c <= a + 1;
else
c <= b"0000";
end if;
end process;
end ALU4;
-- Using case condition statement
architecture ALU5 of main is
begin
process (a, b, op) begin
case conv_integer(op) is
when 1 =>
c <= a + b;
when 2 =>
c <= a - b;
when 3 =>
c <= a + 1;
when others =>
c <= b"0000";
end case;
end process;
end ALU5;
|
mit
|
b95d7c1148639e85fed985656e474967
| 0.632993 | 2.752809 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_real.vhd
| 3 | 1,269 |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for 'real' floating-type support in VHDL.
library ieee;
entity vhdl_real is
end;
architecture test of vhdl_real is
constant c : real := 1111.222;
constant d : real := 23.8;
constant e : real := c + d;
signal a : real := 1.2;
signal b : real := 32.123_23;
signal pi : real := 3.14159265;
signal exp : real := 2.334E+2;
signal no_init : real;
begin
no_init <= a + b;
end test;
|
gpl-2.0
|
8c6b33e72ad77479d6ce9d6ed7802275
| 0.682427 | 3.743363 | false | true | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/irq_gen_v1_1/f141c1dc/hdl/vhdl/user_logic.vhd
| 2 | 10,293 |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed May 30 12:34:16 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
IRQ : out std_logic;
VIO_IRQ_TICK : in std_logic;
vio_rise_edge : out std_logic;
slv_reg : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal vio_rise_p : std_logic_vector(3 downto 0);
signal vio_rise_edge_i : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 downto 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
else
if vio_rise_edge_i = '1' then
slv_reg0(0) <= '1';
end if;
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
begin
case slv_reg_read_sel is
when "1" => slv_ip2bus_data <= slv_reg0;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
TICK_EDGE_DETECT_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
vio_rise_edge_i <= '0';
vio_rise_p <= (others=>'0');
else
vio_rise_p <= vio_rise_p(2 downto 0) & VIO_IRQ_TICK;
vio_rise_edge_i <= not vio_rise_p(3) and vio_rise_p(2);
end if;
end if;
end process TICK_EDGE_DETECT_PROC;
IRQ <= slv_reg0(0);
vio_rise_edge <= vio_rise_edge_i;
slv_reg <= slv_reg0(0);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
gpl-2.0
|
17d24b297f7474267598346bdc2a9e9f
| 0.475663 | 4.339376 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.sim/sim_2/synth/func/test2_func_synth.vhd
| 1 | 429,460 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sat Apr 16 22:18:39 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -mode funcsim -nolib -force -file
-- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.sim/sim_2/synth/func/test2_func_synth.vhd
-- Design : top
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider_ClockDivider_clk_wiz is
port (
clkIn : in STD_LOGIC;
clk108M : out STD_LOGIC;
clk10M : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz";
end ClockDivider_ClockDivider_clk_wiz;
architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is
signal clk108M_ClockDivider : STD_LOGIC;
signal clk10M_ClockDivider : STD_LOGIC;
signal clkfbout_ClockDivider : STD_LOGIC;
signal clkfbout_buf_ClockDivider : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ClockDivider,
O => clkfbout_buf_ClockDivider
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk108M_ClockDivider,
O => clk108M
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk10M_ClockDivider,
O => clk10M
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 54.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 108,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "BUF_IN",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ClockDivider,
CLKFBOUT => clkfbout_ClockDivider,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clkIn,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk108M_ClockDivider,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk10M_ClockDivider,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 2 downto 0 );
clkb : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \FrameBuffer_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\doutb[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(0),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
O => doutb(0)
);
\doutb[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(1),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1),
O => doutb(1)
);
\doutb[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(2),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2),
O => doutb(2)
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(3),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3),
O => doutb(3)
);
\doutb[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(4),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4),
O => doutb(4)
);
\doutb[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(5),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5),
O => doutb(5)
);
\doutb[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(6),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6),
O => doutb(6)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(7),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7),
O => doutb(7)
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(2),
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_wrapper_init is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end FrameBuffer_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"4646464646464646464646464646464646462020202020202020202020202020",
INIT_06 => X"2020202020202020202020505050505050505050505050505050505046464646",
INIT_07 => X"2041414120202020202020202020202020202047474747474747474747474747",
INIT_08 => X"5A20202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A",
INIT_0A => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_0B => X"47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A3A",
INIT_0C => X"413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0D => X"5A20202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0F => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_10 => X"3A3A3A474720202020503A3A3A3A3A5050505050503A3A3A3A3A3A50463A3A3A",
INIT_11 => X"3A3A3A3A3A4120202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_12 => X"5A20202020202020202020202020202020202020202020202020202020202041",
INIT_13 => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_14 => X"3A4646464646464646463A3A3A3A3A3A46462020202020202020202020202020",
INIT_15 => X"3A3A3A3A3A472020503A3A3A3A3A502020202020503A3A3A3A3A5050463A3A3A",
INIT_16 => X"3A3A3A3A3A3A41202020202020202020202020473A3A3A3A4747474747474747",
INIT_17 => X"5A2020202020202020202020202020202020202020202020202020202020413A",
INIT_18 => X"2020202020202020202020202020205A3A3A3A3A3A5A5A5A5A5A5A5A5A3A3A3A",
INIT_19 => X"464620202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_1A => X"473A3A3A3A3A4720503A3A3A3A3A502020202020503A3A3A3A50202046464646",
INIT_1B => X"3A3A3A3A3A3A3A41202020202020202020202047474747474720202020202020",
INIT_1C => X"5A20202020202020202020202020202020202020202020202020202020413A3A",
INIT_1D => X"202020202020202020202020202020205A3A3A3A3A3A5A20202020205A5A5A5A",
INIT_1E => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_1F => X"20473A3A3A3A3A47503A3A3A3A3A502020202020503A3A3A3A50202020202020",
INIT_20 => X"3A3A413A3A3A3A3A412020202020202020202020202020202020202020202020",
INIT_21 => X"20202020202020202020202020202020202020202020202020202020413A3A3A",
INIT_22 => X"2020202020202020202020202020202020205A3A3A3A3A3A5A20202020202020",
INIT_23 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020",
INIT_24 => X"20473A3A3A3A3A4720503A3A3A3A3A5050505050503A3A3A3A50202020202046",
INIT_25 => X"3A4120413A3A3A3A3A4120202020202020202020202020202020202020202020",
INIT_26 => X"202020202020202020202020202020202020202020202020202020413A3A3A3A",
INIT_27 => X"202020202020202020202020202020202020205A3A3A3A3A3A5A202020202020",
INIT_28 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020",
INIT_29 => X"20473A3A3A3A3A47202050503A3A3A3A3A3A3A3A3A3A3A3A3A50202020202046",
INIT_2A => X"41202020413A3A3A3A3A41202020202020202047474747474747474747202020",
INIT_2B => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D202020202020202020413A3A3A3A3A",
INIT_2C => X"20202020202020202020202020202020202020205A3A3A3A3A3A5A2020202020",
INIT_2D => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020",
INIT_2E => X"20473A3A3A3A3A47202020205050505050505050503A3A3A3A50202020202046",
INIT_2F => X"2020202020413A3A3A3A3A4120202020202020473A3A3A3A3A3A3A3A47202020",
INIT_30 => X"20202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D2020202020202020413A3A3A3A3A41",
INIT_31 => X"2020202020202020202020202020202020202020205A3A3A3A3A3A5A20202020",
INIT_32 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020",
INIT_33 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202046",
INIT_34 => X"414141414141413A3A3A3A3A41202020202020473A3A3A3A4747474747202020",
INIT_35 => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020202020413A3A3A3A3A4141",
INIT_36 => X"202020202020202020202020202020202020202020205A3A3A3A3A3A5A202020",
INIT_37 => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_38 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202020",
INIT_39 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A412020202020473A3A3A3A4720202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020413A3A3A3A3A3A3A3A",
INIT_3B => X"20202020202020202020202020202020202020202020205A3A3A3A3A3A5A2020",
INIT_3C => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020",
INIT_3D => X"473A3A3A3A3A4720202020202020202020202020503A3A3A3A50202020202020",
INIT_3E => X"4141414141414141413A3A3A3A3A4120202020473A3A3A3A4720202020202020",
INIT_3F => X"5A202020202020202020202020202020202020202020413A3A3A3A3A41414141",
INIT_40 => X"20202020202020202020202020205A5A5A5A5A20202020205A3A3A3A3A3A5A5A",
INIT_41 => X"2020202020202046463A3A3A3A3A3A3A46462020202020202020202020202020",
INIT_42 => X"3A3A3A3A3A4720202020202020202020202050503A3A3A3A3A3A505020202020",
INIT_43 => X"202020202020202020413A3A3A3A3A41202020473A3A3A3A4747474747474747",
INIT_44 => X"5A2020202020202020202020202020202020202020413A3A3A3A3A4120202020",
INIT_45 => X"20202020202020202020202020205A3A3A3A5A5A5A5A5A5A5A5A3A3A3A3A3A3A",
INIT_46 => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_47 => X"3A3A3A474720202020202020202020202020503A3A3A3A3A3A3A3A5020202020",
INIT_48 => X"20202020202020202020413A3A3A3A3A412020473A3A3A3A3A3A3A3A3A3A3A3A",
INIT_49 => X"5A20202020202020202020202020202020202020413A3A3A3A3A412020202020",
INIT_4A => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_4B => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020",
INIT_4C => X"474747202020202020202020202020202020503A3A3A3A3A3A3A3A5020202020",
INIT_4D => X"2020202020202020202020413A3A3A3A3A4120473A3A3A4747473A3A3A3A3A3A",
INIT_4E => X"5A202020202020202020202020202020202020413A3A3A3A3A41202020202020",
INIT_4F => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_50 => X"2020202020202046464646464646464646462020202020202020202020202020",
INIT_51 => X"2020202020202020202020202020202020205050505050505050505020202020",
INIT_52 => X"2020202020202020202020204141414141414147474747202020474747474747",
INIT_53 => X"5A20202020202020202020202020202020204141414141414120202020202020",
INIT_54 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A",
INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5B => X"2041475046206E41202020202020202020202020202020202020202020202020",
INIT_5C => X"6D656C706D692033206E6F697372655620656E696863614D2D5A206465736162",
INIT_5D => X"20202020202020202020202020202020202020202020202E6E6F697461746E65",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_61 => X"202E7475706E69207478657420726F662064616F6279656B2061206573552020",
INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6B => X"20202E2E2E65756E69746E6F63206F742079656B20796E612073736572502020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => wea(0),
I1 => addra(12),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addrb(12),
I1 => addrb(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
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INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_40 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_41 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_42 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_43 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_44 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_45 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_46 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_47 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_48 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_49 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_50 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_51 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_52 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_53 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_54 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_61 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020",
INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074",
INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073",
INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 3) => addrb(10 downto 0),
ADDRBWRADDR(2 downto 0) => B"000",
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => ram_ena,
ENBWREN => ram_enb,
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => addra(12),
I1 => addra(11),
I2 => addra(13),
I3 => wea(0),
O => ram_ena
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addrb(11),
I1 => addrb(13),
I2 => addrb(12),
O => ram_enb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Vga is
port (
Hsync_OBUF : out STD_LOGIC;
Vsync_OBUF : out STD_LOGIC;
vgaBlue_OBUF : out STD_LOGIC_VECTOR ( 0 to 0 );
clk108M : in STD_LOGIC;
doutb : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end Vga;
architecture STRUCTURE of Vga is
signal char : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \char[0]_i_1_n_0\ : STD_LOGIC;
signal \char[1]_i_1_n_0\ : STD_LOGIC;
signal \char[2]_i_1_n_0\ : STD_LOGIC;
signal \char[3]_i_1_n_0\ : STD_LOGIC;
signal \char[4]_i_1_n_0\ : STD_LOGIC;
signal \char[5]_i_1_n_0\ : STD_LOGIC;
signal \char[6]_i_1_n_0\ : STD_LOGIC;
signal \char[7]_i_1_n_0\ : STD_LOGIC;
signal \char[7]_i_2_n_0\ : STD_LOGIC;
signal \char[7]_i_3_n_0\ : STD_LOGIC;
signal \char[7]_i_4_n_0\ : STD_LOGIC;
signal \char[7]_i_5_n_0\ : STD_LOGIC;
signal \char[7]_i_6_n_0\ : STD_LOGIC;
signal \char[7]_i_7_n_0\ : STD_LOGIC;
signal g0_b0_i_1_n_0 : STD_LOGIC;
signal g0_b0_i_4_n_0 : STD_LOGIC;
signal g0_b0_i_5_n_0 : STD_LOGIC;
signal g0_b0_n_0 : STD_LOGIC;
signal g0_b1_n_0 : STD_LOGIC;
signal g0_b2_n_0 : STD_LOGIC;
signal g0_b3_n_0 : STD_LOGIC;
signal g0_b4_n_0 : STD_LOGIC;
signal g0_b5_n_0 : STD_LOGIC;
signal g0_b6_n_0 : STD_LOGIC;
signal g0_b7_n_0 : STD_LOGIC;
signal g10_b0_n_0 : STD_LOGIC;
signal g10_b1_n_0 : STD_LOGIC;
signal g10_b2_n_0 : STD_LOGIC;
signal g10_b3_n_0 : STD_LOGIC;
signal g10_b4_n_0 : STD_LOGIC;
signal g10_b5_n_0 : STD_LOGIC;
signal g11_b0_n_0 : STD_LOGIC;
signal g11_b1_n_0 : STD_LOGIC;
signal g11_b2_n_0 : STD_LOGIC;
signal g11_b3_n_0 : STD_LOGIC;
signal g11_b4_n_0 : STD_LOGIC;
signal g11_b5_n_0 : STD_LOGIC;
signal g11_b6_n_0 : STD_LOGIC;
signal g12_b0_n_0 : STD_LOGIC;
signal g12_b1_n_0 : STD_LOGIC;
signal g12_b2_n_0 : STD_LOGIC;
signal g12_b3_n_0 : STD_LOGIC;
signal g12_b4_n_0 : STD_LOGIC;
signal g12_b5_n_0 : STD_LOGIC;
signal g12_b6_n_0 : STD_LOGIC;
signal g13_b0_n_0 : STD_LOGIC;
signal g13_b1_n_0 : STD_LOGIC;
signal g13_b2_n_0 : STD_LOGIC;
signal g13_b3_n_0 : STD_LOGIC;
signal g13_b4_n_0 : STD_LOGIC;
signal g13_b5_n_0 : STD_LOGIC;
signal g13_b6_n_0 : STD_LOGIC;
signal g14_b0_n_0 : STD_LOGIC;
signal g14_b1_n_0 : STD_LOGIC;
signal g14_b2_n_0 : STD_LOGIC;
signal g14_b3_n_0 : STD_LOGIC;
signal g14_b4_n_0 : STD_LOGIC;
signal g14_b5_n_0 : STD_LOGIC;
signal g14_b6_n_0 : STD_LOGIC;
signal g15_b0_n_0 : STD_LOGIC;
signal g15_b1_n_0 : STD_LOGIC;
signal g15_b2_n_0 : STD_LOGIC;
signal g15_b3_n_0 : STD_LOGIC;
signal g15_b4_n_0 : STD_LOGIC;
signal g15_b5_n_0 : STD_LOGIC;
signal g15_b6_n_0 : STD_LOGIC;
signal g16_b0_n_0 : STD_LOGIC;
signal g16_b1_n_0 : STD_LOGIC;
signal g16_b2_n_0 : STD_LOGIC;
signal g16_b3_n_0 : STD_LOGIC;
signal g16_b4_n_0 : STD_LOGIC;
signal g16_b5_n_0 : STD_LOGIC;
signal g16_b6_n_0 : STD_LOGIC;
signal g17_b0_n_0 : STD_LOGIC;
signal g17_b1_n_0 : STD_LOGIC;
signal g17_b2_n_0 : STD_LOGIC;
signal g17_b3_n_0 : STD_LOGIC;
signal g17_b4_n_0 : STD_LOGIC;
signal g17_b5_n_0 : STD_LOGIC;
signal g17_b6_n_0 : STD_LOGIC;
signal g18_b0_n_0 : STD_LOGIC;
signal g18_b1_n_0 : STD_LOGIC;
signal g18_b2_n_0 : STD_LOGIC;
signal g18_b3_n_0 : STD_LOGIC;
signal g18_b4_n_0 : STD_LOGIC;
signal g18_b5_n_0 : STD_LOGIC;
signal g18_b6_n_0 : STD_LOGIC;
signal g19_b0_n_0 : STD_LOGIC;
signal g19_b1_n_0 : STD_LOGIC;
signal g19_b2_n_0 : STD_LOGIC;
signal g19_b3_n_0 : STD_LOGIC;
signal g19_b4_n_0 : STD_LOGIC;
signal g19_b5_n_0 : STD_LOGIC;
signal g19_b6_n_0 : STD_LOGIC;
signal g19_b7_n_0 : STD_LOGIC;
signal g1_b0_n_0 : STD_LOGIC;
signal g1_b1_n_0 : STD_LOGIC;
signal g1_b2_n_0 : STD_LOGIC;
signal g1_b3_n_0 : STD_LOGIC;
signal g1_b4_n_0 : STD_LOGIC;
signal g1_b5_n_0 : STD_LOGIC;
signal g1_b6_n_0 : STD_LOGIC;
signal g1_b7_n_0 : STD_LOGIC;
signal g20_b0_n_0 : STD_LOGIC;
signal g20_b1_n_0 : STD_LOGIC;
signal g20_b2_n_0 : STD_LOGIC;
signal g20_b3_n_0 : STD_LOGIC;
signal g20_b4_n_0 : STD_LOGIC;
signal g20_b5_n_0 : STD_LOGIC;
signal g20_b6_n_0 : STD_LOGIC;
signal g21_b0_n_0 : STD_LOGIC;
signal g21_b1_n_0 : STD_LOGIC;
signal g21_b2_n_0 : STD_LOGIC;
signal g21_b3_n_0 : STD_LOGIC;
signal g21_b5_n_0 : STD_LOGIC;
signal g21_b6_n_0 : STD_LOGIC;
signal g21_b7_n_0 : STD_LOGIC;
signal g22_b0_n_0 : STD_LOGIC;
signal g22_b1_n_0 : STD_LOGIC;
signal g22_b2_n_0 : STD_LOGIC;
signal g22_b3_n_0 : STD_LOGIC;
signal g22_b4_n_0 : STD_LOGIC;
signal g22_b5_n_0 : STD_LOGIC;
signal g22_b6_n_0 : STD_LOGIC;
signal g22_b7_n_0 : STD_LOGIC;
signal g23_b0_n_0 : STD_LOGIC;
signal g23_b1_n_0 : STD_LOGIC;
signal g23_b2_n_0 : STD_LOGIC;
signal g23_b3_n_0 : STD_LOGIC;
signal g23_b4_n_0 : STD_LOGIC;
signal g23_b5_n_0 : STD_LOGIC;
signal g23_b6_n_0 : STD_LOGIC;
signal g23_b7_n_0 : STD_LOGIC;
signal g24_b0_n_0 : STD_LOGIC;
signal g24_b1_n_0 : STD_LOGIC;
signal g24_b2_n_0 : STD_LOGIC;
signal g24_b3_n_0 : STD_LOGIC;
signal g24_b4_n_0 : STD_LOGIC;
signal g24_b5_n_0 : STD_LOGIC;
signal g24_b6_n_0 : STD_LOGIC;
signal g25_b0_n_0 : STD_LOGIC;
signal g25_b1_n_0 : STD_LOGIC;
signal g25_b2_n_0 : STD_LOGIC;
signal g25_b3_n_0 : STD_LOGIC;
signal g25_b4_n_0 : STD_LOGIC;
signal g25_b5_n_0 : STD_LOGIC;
signal g25_b6_n_0 : STD_LOGIC;
signal g26_b0_n_0 : STD_LOGIC;
signal g26_b1_n_0 : STD_LOGIC;
signal g26_b2_n_0 : STD_LOGIC;
signal g26_b3_n_0 : STD_LOGIC;
signal g26_b4_n_0 : STD_LOGIC;
signal g26_b5_n_0 : STD_LOGIC;
signal g26_b6_n_0 : STD_LOGIC;
signal g27_b0_n_0 : STD_LOGIC;
signal g27_b1_n_0 : STD_LOGIC;
signal g27_b2_n_0 : STD_LOGIC;
signal g27_b3_n_0 : STD_LOGIC;
signal g27_b5_n_0 : STD_LOGIC;
signal g27_b6_n_0 : STD_LOGIC;
signal g27_b7_n_0 : STD_LOGIC;
signal g28_b0_n_0 : STD_LOGIC;
signal g28_b1_n_0 : STD_LOGIC;
signal g28_b2_n_0 : STD_LOGIC;
signal g28_b3_n_0 : STD_LOGIC;
signal g28_b4_n_0 : STD_LOGIC;
signal g28_b5_n_0 : STD_LOGIC;
signal g28_b6_n_0 : STD_LOGIC;
signal g29_b0_n_0 : STD_LOGIC;
signal g29_b1_n_0 : STD_LOGIC;
signal g29_b2_n_0 : STD_LOGIC;
signal g29_b3_n_0 : STD_LOGIC;
signal g29_b4_n_0 : STD_LOGIC;
signal g29_b5_n_0 : STD_LOGIC;
signal g29_b6_n_0 : STD_LOGIC;
signal g29_b7_n_0 : STD_LOGIC;
signal g2_b0_n_0 : STD_LOGIC;
signal g2_b1_n_0 : STD_LOGIC;
signal g2_b2_n_0 : STD_LOGIC;
signal g2_b3_n_0 : STD_LOGIC;
signal g2_b4_n_0 : STD_LOGIC;
signal g2_b5_n_0 : STD_LOGIC;
signal g2_b6_n_0 : STD_LOGIC;
signal g2_b7_n_0 : STD_LOGIC;
signal g30_b0_n_0 : STD_LOGIC;
signal g30_b1_n_0 : STD_LOGIC;
signal g30_b2_n_0 : STD_LOGIC;
signal g30_b3_n_0 : STD_LOGIC;
signal g30_b4_n_0 : STD_LOGIC;
signal g30_b5_n_0 : STD_LOGIC;
signal g30_b6_n_0 : STD_LOGIC;
signal g30_b7_n_0 : STD_LOGIC;
signal g31_b0_n_0 : STD_LOGIC;
signal g31_b1_n_0 : STD_LOGIC;
signal g31_b2_n_0 : STD_LOGIC;
signal g31_b3_n_0 : STD_LOGIC;
signal g31_b4_n_0 : STD_LOGIC;
signal g31_b5_n_0 : STD_LOGIC;
signal g31_b6_n_0 : STD_LOGIC;
signal g3_b0_n_0 : STD_LOGIC;
signal g3_b1_n_0 : STD_LOGIC;
signal g3_b2_n_0 : STD_LOGIC;
signal g3_b3_n_0 : STD_LOGIC;
signal g3_b4_n_0 : STD_LOGIC;
signal g3_b5_n_0 : STD_LOGIC;
signal g3_b6_n_0 : STD_LOGIC;
signal g3_b7_n_0 : STD_LOGIC;
signal g4_b0_n_0 : STD_LOGIC;
signal g4_b1_n_0 : STD_LOGIC;
signal g4_b2_n_0 : STD_LOGIC;
signal g4_b3_n_0 : STD_LOGIC;
signal g4_b4_n_0 : STD_LOGIC;
signal g4_b5_n_0 : STD_LOGIC;
signal g4_b6_n_0 : STD_LOGIC;
signal g5_b0_n_0 : STD_LOGIC;
signal g5_b1_n_0 : STD_LOGIC;
signal g5_b2_n_0 : STD_LOGIC;
signal g5_b3_n_0 : STD_LOGIC;
signal g5_b4_n_0 : STD_LOGIC;
signal g5_b5_n_0 : STD_LOGIC;
signal g5_b6_n_0 : STD_LOGIC;
signal g5_b7_n_0 : STD_LOGIC;
signal g6_b0_n_0 : STD_LOGIC;
signal g6_b1_n_0 : STD_LOGIC;
signal g6_b2_n_0 : STD_LOGIC;
signal g6_b3_n_0 : STD_LOGIC;
signal g6_b4_n_0 : STD_LOGIC;
signal g6_b5_n_0 : STD_LOGIC;
signal g6_b6_n_0 : STD_LOGIC;
signal g7_b0_n_0 : STD_LOGIC;
signal g7_b1_n_0 : STD_LOGIC;
signal g7_b2_n_0 : STD_LOGIC;
signal g7_b3_n_0 : STD_LOGIC;
signal g7_b4_n_0 : STD_LOGIC;
signal g7_b5_n_0 : STD_LOGIC;
signal g7_b6_n_0 : STD_LOGIC;
signal g7_b7_n_0 : STD_LOGIC;
signal g8_b0_n_0 : STD_LOGIC;
signal g8_b1_n_0 : STD_LOGIC;
signal g8_b2_n_0 : STD_LOGIC;
signal g8_b3_n_0 : STD_LOGIC;
signal g8_b4_n_0 : STD_LOGIC;
signal g8_b6_n_0 : STD_LOGIC;
signal g9_b0_n_0 : STD_LOGIC;
signal g9_b1_n_0 : STD_LOGIC;
signal g9_b2_n_0 : STD_LOGIC;
signal g9_b3_n_0 : STD_LOGIC;
signal g9_b4_n_0 : STD_LOGIC;
signal g9_b5_n_0 : STD_LOGIC;
signal g9_b6_n_0 : STD_LOGIC;
signal hSync_i_1_n_0 : STD_LOGIC;
signal hSync_i_2_n_0 : STD_LOGIC;
signal hSync_i_3_n_0 : STD_LOGIC;
signal hSync_i_4_n_0 : STD_LOGIC;
signal hSync_i_5_n_0 : STD_LOGIC;
signal \h_count[0]_i_1_n_0\ : STD_LOGIC;
signal \h_count[10]_i_1_n_0\ : STD_LOGIC;
signal \h_count[10]_i_2_n_0\ : STD_LOGIC;
signal \h_count[10]_i_3_n_0\ : STD_LOGIC;
signal \h_count[10]_i_4_n_0\ : STD_LOGIC;
signal \h_count[10]_i_5_n_0\ : STD_LOGIC;
signal \h_count[1]_i_1_n_0\ : STD_LOGIC;
signal \h_count[2]_i_1_n_0\ : STD_LOGIC;
signal \h_count[3]_i_1_n_0\ : STD_LOGIC;
signal \h_count[4]_i_1_n_0\ : STD_LOGIC;
signal \h_count[5]_i_1_n_0\ : STD_LOGIC;
signal \h_count[6]_i_1_n_0\ : STD_LOGIC;
signal \h_count[7]_i_1_n_0\ : STD_LOGIC;
signal \h_count[7]_i_2_n_0\ : STD_LOGIC;
signal \h_count[8]_i_1_n_0\ : STD_LOGIC;
signal \h_count[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg_n_0_[0]\ : STD_LOGIC;
signal \h_count_reg_n_0_[10]\ : STD_LOGIC;
signal \h_count_reg_n_0_[1]\ : STD_LOGIC;
signal \h_count_reg_n_0_[2]\ : STD_LOGIC;
signal \h_count_reg_n_0_[3]\ : STD_LOGIC;
signal \h_count_reg_n_0_[4]\ : STD_LOGIC;
signal \h_count_reg_n_0_[5]\ : STD_LOGIC;
signal \h_count_reg_n_0_[6]\ : STD_LOGIC;
signal \h_count_reg_n_0_[7]\ : STD_LOGIC;
signal \h_count_reg_n_0_[8]\ : STD_LOGIC;
signal \h_count_reg_n_0_[9]\ : STD_LOGIC;
signal sel : STD_LOGIC_VECTOR ( 3 downto 0 );
signal vSync_i_1_n_0 : STD_LOGIC;
signal vSync_i_2_n_0 : STD_LOGIC;
signal vSync_i_3_n_0 : STD_LOGIC;
signal vSync_i_4_n_0 : STD_LOGIC;
signal vSync_i_5_n_0 : STD_LOGIC;
signal vSync_i_6_n_0 : STD_LOGIC;
signal v_count3_out : STD_LOGIC_VECTOR ( 10 downto 6 );
signal \v_count[10]_i_2_n_0\ : STD_LOGIC;
signal \v_count[10]_i_3_n_0\ : STD_LOGIC;
signal \v_count[10]_i_4_n_0\ : STD_LOGIC;
signal \v_count[1]_i_2_n_0\ : STD_LOGIC;
signal \v_count[1]_i_3_n_0\ : STD_LOGIC;
signal \v_count[2]_i_1_n_0\ : STD_LOGIC;
signal \v_count[3]_i_1_n_0\ : STD_LOGIC;
signal \v_count[4]_i_1_n_0\ : STD_LOGIC;
signal \v_count[5]_i_1_n_0\ : STD_LOGIC;
signal \v_count[5]_i_2_n_0\ : STD_LOGIC;
signal \v_count[6]_i_2_n_0\ : STD_LOGIC;
signal \v_count[7]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg_n_0_[0]\ : STD_LOGIC;
signal \v_count_reg_n_0_[10]\ : STD_LOGIC;
signal \v_count_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg_n_0_[2]\ : STD_LOGIC;
signal \v_count_reg_n_0_[3]\ : STD_LOGIC;
signal \v_count_reg_n_0_[4]\ : STD_LOGIC;
signal \v_count_reg_n_0_[5]\ : STD_LOGIC;
signal \v_count_reg_n_0_[6]\ : STD_LOGIC;
signal \v_count_reg_n_0_[7]\ : STD_LOGIC;
signal \v_count_reg_n_0_[8]\ : STD_LOGIC;
signal \v_count_reg_n_0_[9]\ : STD_LOGIC;
signal \vgaRed[0]_i_15_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_16_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_17_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_18_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_19_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_1_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_20_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_21_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_22_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_23_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_24_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_25_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_26_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_27_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_28_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_29_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_2_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_30_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_31_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_32_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_34_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_3_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_42_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_4_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_50_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_51_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_54_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_62_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_6_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_74_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_75_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_78_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_7_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_86_n_0\ : STD_LOGIC;
signal \vgaRed[0]_i_9_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_100_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_101_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_102_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_103_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_104_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_105_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_106_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_107_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_108_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_109_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_10_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_110_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_111_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_112_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_113_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_114_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_115_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_116_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_117_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_118_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_119_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_120_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_121_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_122_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_123_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_124_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_125_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_126_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_127_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_128_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_129_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_12_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_130_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_131_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_132_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_133_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_134_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_135_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_136_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_137_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_138_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_139_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_13_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_140_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_141_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_142_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_143_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_144_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_145_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_146_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_147_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_148_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_149_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_14_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_150_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_151_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_152_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_153_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_154_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_155_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_156_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_157_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_158_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_159_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_160_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_161_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_162_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_163_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_164_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_165_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_166_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_167_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_168_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_169_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_170_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_171_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_172_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_173_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_174_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_175_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_176_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_177_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_178_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_179_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_180_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_181_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_182_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_183_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_184_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_185_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_186_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_33_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_35_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_36_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_37_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_38_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_39_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_40_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_41_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_43_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_44_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_45_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_46_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_47_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_48_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_49_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_52_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_53_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_55_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_56_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_57_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_58_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_59_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_5_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_60_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_61_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_63_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_64_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_65_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_66_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_67_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_68_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_69_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_70_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_71_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_72_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_73_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_76_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_77_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_79_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_80_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_81_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_82_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_83_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_84_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_85_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_87_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_88_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_89_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_8_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_90_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_91_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_92_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_93_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_94_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_95_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_96_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_97_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_98_n_0\ : STD_LOGIC;
signal \vgaRed_reg[0]_i_99_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of g11_b0 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of g19_b7 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of g27_b7 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of g5_b7 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of hSync_i_5 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \h_count[0]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \h_count[10]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \h_count[2]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \h_count[3]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \h_count[4]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \h_count[6]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count[7]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \h_count[9]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of vSync_i_3 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of vSync_i_5 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of vSync_i_6 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count[10]_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \v_count[10]_i_4\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \v_count[1]_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \v_count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \v_count[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \v_count[6]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \v_count[7]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \v_count[7]_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count[8]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \v_count[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \vgaRed[0]_i_4\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \vgaRed[0]_i_7\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \vgaRed[0]_i_9\ : label is "soft_lutpair20";
begin
\char[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(0),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(0),
O => \char[0]_i_1_n_0\
);
\char[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(1),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(1),
O => \char[1]_i_1_n_0\
);
\char[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAFBAAAAAA08AAAA"
)
port map (
I0 => doutb(2),
I1 => \h_count_reg_n_0_[3]\,
I2 => \h_count[10]_i_4_n_0\,
I3 => \h_count[10]_i_3_n_0\,
I4 => \h_count[7]_i_2_n_0\,
I5 => char(2),
O => \char[2]_i_1_n_0\
);
\char[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAFBAAAAAA08AAAA"
)
port map (
I0 => doutb(3),
I1 => \h_count_reg_n_0_[3]\,
I2 => \h_count[10]_i_4_n_0\,
I3 => \h_count[10]_i_3_n_0\,
I4 => \h_count[7]_i_2_n_0\,
I5 => char(3),
O => \char[3]_i_1_n_0\
);
\char[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(4),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(4),
O => \char[4]_i_1_n_0\
);
\char[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(5),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(5),
O => \char[5]_i_1_n_0\
);
\char[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(6),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(6),
O => \char[6]_i_1_n_0\
);
\char[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \char[7]_i_3_n_0\,
O => \char[7]_i_1_n_0\
);
\char[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(7),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(7),
O => \char[7]_i_2_n_0\
);
\char[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF00A2FFFFFFFF"
)
port map (
I0 => \char[7]_i_4_n_0\,
I1 => \h_count[9]_i_2_n_0\,
I2 => \h_count[10]_i_1_n_0\,
I3 => \char[7]_i_5_n_0\,
I4 => v_count3_out(10),
I5 => \char[7]_i_6_n_0\,
O => \char[7]_i_3_n_0\
);
\char[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000020000200000"
)
port map (
I0 => \char[7]_i_7_n_0\,
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[5]\,
I3 => \h_count[9]_i_2_n_0\,
I4 => \h_count_reg_n_0_[6]\,
I5 => \h_count_reg_n_0_[7]\,
O => \char[7]_i_4_n_0\
);
\char[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5155555504000000"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => \h_count_reg_n_0_[7]\,
I2 => \h_count[9]_i_2_n_0\,
I3 => \h_count_reg_n_0_[5]\,
I4 => \h_count_reg_n_0_[6]\,
I5 => \h_count_reg_n_0_[8]\,
O => \char[7]_i_5_n_0\
);
\char[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000555500005556"
)
port map (
I0 => \h_count_reg_n_0_[10]\,
I1 => \h_count_reg_n_0_[8]\,
I2 => \h_count_reg_n_0_[7]\,
I3 => \h_count[10]_i_5_n_0\,
I4 => \h_count[10]_i_1_n_0\,
I5 => \h_count_reg_n_0_[9]\,
O => \char[7]_i_6_n_0\
);
\char[7]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"5595555555555555"
)
port map (
I0 => \h_count_reg_n_0_[9]\,
I1 => \h_count_reg_n_0_[8]\,
I2 => \h_count_reg_n_0_[7]\,
I3 => \h_count[9]_i_2_n_0\,
I4 => \h_count_reg_n_0_[5]\,
I5 => \h_count_reg_n_0_[6]\,
O => \char[7]_i_7_n_0\
);
\char_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[0]_i_1_n_0\,
Q => char(0),
R => '0'
);
\char_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[1]_i_1_n_0\,
Q => char(1),
R => '0'
);
\char_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[2]_i_1_n_0\,
Q => char(2),
R => '0'
);
\char_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[3]_i_1_n_0\,
Q => char(3),
R => '0'
);
\char_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[4]_i_1_n_0\,
Q => char(4),
R => '0'
);
\char_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[5]_i_1_n_0\,
Q => char(5),
R => '0'
);
\char_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[6]_i_1_n_0\,
Q => char(6),
R => '0'
);
\char_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \char[7]_i_1_n_0\,
D => \char[7]_i_2_n_0\,
Q => char(7),
R => '0'
);
g0_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000007F807F80000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g0_b0_n_0
);
g0_b0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => \v_count_reg_n_0_[0]\,
I2 => \v_count[10]_i_2_n_0\,
O => g0_b0_i_1_n_0
);
g0_b0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"07FF0800"
)
port map (
I0 => \v_count_reg_n_0_[1]\,
I1 => \v_count_reg_n_0_[0]\,
I2 => \v_count[1]_i_2_n_0\,
I3 => \h_count[10]_i_1_n_0\,
I4 => \v_count_reg_n_0_[2]\,
O => sel(2)
);
g0_b0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"007FFFFF00800000"
)
port map (
I0 => \v_count_reg_n_0_[0]\,
I1 => \v_count_reg_n_0_[1]\,
I2 => \v_count_reg_n_0_[2]\,
I3 => \v_count[1]_i_2_n_0\,
I4 => \h_count[10]_i_1_n_0\,
I5 => \v_count_reg_n_0_[3]\,
O => sel(3)
);
g0_b0_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(0),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(0),
O => g0_b0_i_4_n_0
);
g0_b0_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"ABBBBBBBA8888888"
)
port map (
I0 => doutb(1),
I1 => \h_count[10]_i_1_n_0\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count_reg_n_0_[0]\,
I4 => \h_count_reg_n_0_[1]\,
I5 => char(1),
O => g0_b0_i_5_n_0
);
g0_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"01E00FFC08040000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b1_n_0
);
g0_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"03F00F6C08940000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b2_n_0
);
g0_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07F00E7C09840000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g0_b3_n_0
);
g0_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00E7C09840000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g0_b4_n_0
);
g0_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"07F00F6C08940000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b5_n_0
);
g0_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"03F00FFC08040000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g0_b6_n_0
);
g0_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"01E007F807F80000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g0_b7_n_0
);
g10_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008000000000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g10_b0_n_0
);
g10_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"008002A000000000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g10_b1_n_0
);
g10_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"008003E0080403F0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g10_b2_n_0
);
g10_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"03E001C00C0C07F8"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g10_b3_n_0
);
g10_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03E001C007F80C0C"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g10_b4_n_0
);
g10_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"008003E003F00804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g10_b5_n_0
);
g11_b0: unisim.vcomponents.LUT5
generic map(
INIT => X"20000000"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => g0_b0_i_4_n_0,
I4 => g0_b0_i_5_n_0,
O => g11_b0_n_0
);
g11_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0600000000800000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g11_b1_n_0
);
g11_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0300000000801000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g11_b2_n_0
);
g11_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"01800C0000801E00"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g11_b3_n_0
);
g11_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"00C00C0000800E00"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g11_b4_n_0
);
g11_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0060000000800000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g11_b5_n_0
);
g11_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0030000000800000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g11_b6_n_0
);
g12_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"04080E08000007F8"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g12_b0_n_0
);
g12_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0F0C08100FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g12_b1_n_0
);
g12_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0844098408180984"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g12_b2_n_0
);
g12_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"084408C40FFC08C4"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g12_b3_n_0
);
g12_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"084408640FFC0864"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g12_b4_n_0
);
g12_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC0C3C08000FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g12_b5_n_0
);
g12_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07B80C18080007F8"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g12_b6_n_0
);
g13_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000C07F0047C00C0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g13_b0_n_0
);
g13_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0FF80C7C00E0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g13_b1_n_0
);
g13_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0F04084C084400B0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g13_b2_n_0
);
g13_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0F84084408440898"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g13_b3_n_0
);
g13_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"00C4084408440FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g13_b4_n_0
);
g13_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"007C0FC00FC40FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g13_b5_n_0
);
g13_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"003C078007840880"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g13_b6_n_0
);
g14_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000003807B8"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g14_b0_n_0
);
g14_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000087C0FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g14_b1_n_0
);
g14_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000008440844"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g14_b2_n_0
);
g14_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0E30063008440844"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g14_b3_n_0
);
g14_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"063006300C440844"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g14_b4_n_0
);
g14_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000007FC0FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g14_b5_n_0
);
g14_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000003F807B8"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g14_b6_n_0
);
g15_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0018000000000000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g15_b0_n_0
);
g15_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"001C080801200080"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g15_b1_n_0
);
g15_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"00040C18012001C0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g15_b2_n_0
);
g15_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0DC4063001200360"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g15_b3_n_0
);
g15_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0DE4036001200630"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g15_b4_n_0
);
g15_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"003C01C001200C18"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g15_b5_n_0
);
g15_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0018008001200808"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g15_b6_n_0
);
g16_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"03F008040FE007F8"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g16_b0_n_0
);
g16_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FF00FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g16_b1_n_0
);
g16_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0FFC00980804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g16_b2_n_0
);
g16_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"08040844008C0BC4"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g16_b3_n_0
);
g16_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0804084400980BC4"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g16_b4_n_0
);
g16_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0FFC0FF00BFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g16_b5_n_0
);
g16_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"061807B80FE001F8"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g16_b6_n_0
);
g17_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"03F0080408040804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g17_b0_n_0
);
g17_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FFC0FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g17_b1_n_0
);
g17_b2: unisim.vcomponents.LUT5
generic map(
INIT => X"223E3E3E"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g17_b2_n_0
);
g17_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0884084408440804"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g17_b3_n_0
);
g17_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"088400E408E40C0C"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g17_b4_n_0
);
g17_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"078C000C0C0C07F8"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g17_b5_n_0
);
g17_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0F98001C0E1C03F0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g17_b6_n_0
);
g18_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0804070000000FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g18_b0_n_0
);
g18_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"3E30003E"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g18_b1_n_0
);
g18_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC080008040040"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g18_b2_n_0
);
g18_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"00C008040FFC0040"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g18_b3_n_0
);
g18_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"01E00FFC0FFC0040"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g18_b4_n_0
);
g18_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0F3C07FC08040FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g18_b5_n_0
);
g18_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0E1C000400000FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g18_b6_n_0
);
g19_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FFC0804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g19_b0_n_0
);
g19_b1: unisim.vcomponents.LUT3
generic map(
INIT => X"3E"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
O => g19_b1_n_0
);
g19_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0804003800380FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g19_b2_n_0
);
g19_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0804007000700804"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g19_b3_n_0
);
g19_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"080400E000700800"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g19_b4_n_0
);
g19_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC0FFC00380C00"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g19_b5_n_0
);
g19_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07F80FFC0FFC0E00"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g19_b6_n_0
);
g19_b7: unisim.vcomponents.LUT5
generic map(
INIT => X"00003E00"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => g0_b0_i_4_n_0,
I4 => g0_b0_i_5_n_0,
O => g19_b7_n_0
);
g1_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C001C00080"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g1_b0_n_0
);
g1_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"000001E001C001C0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b1_n_0
);
g1_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"018009F009F003E0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b2_n_0
);
g1_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"03C00FF80E3807F0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g1_b3_n_0
);
g1_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03C00FF80E3803E0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g1_b4_n_0
);
g1_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"018009F009F001C0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b5_n_0
);
g1_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"000001E001C00080"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g1_b6_n_0
);
g1_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C001C00000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g1_b7_n_0
);
g20_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0618080407F80804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g20_b0_n_0
);
g20_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0E3C0FFC0FFC0FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g20_b1_n_0
);
g20_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"08640FFC08040FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g20_b2_n_0
);
g20_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"084400440E040844"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g20_b3_n_0
);
g20_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"08C400C43C040044"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g20_b4_n_0
);
g20_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0F9C0FFC3FFC007C"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g20_b5_n_0
);
g20_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07180F3827F80038"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g20_b6_n_0
);
g21_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"03FC01FC07FC001C"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g21_b0_n_0
);
g21_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"3E1E3E02"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g21_b1_n_0
);
g21_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0E00060008000804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g21_b2_n_0
);
g21_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"03800C0008000FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g21_b3_n_0
);
g21_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0E0006000FFC0804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g21_b5_n_0
);
g21_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC03FC07FC000C"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g21_b6_n_0
);
g21_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"03FC01FC0000001C"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g21_b7_n_0
);
g22_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000E1C001C0C0C"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g22_b0_n_0
);
g22_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0C003C0E1C"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g22_b1_n_0
);
g22_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC098408600330"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g22_b2_n_0
);
g22_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC08C40FC001E0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g22_b3_n_0
);
g22_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"080408640FC001E0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g22_b4_n_0
);
g22_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0804083408600330"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g22_b5_n_0
);
g22_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"00000C1C003C0E1C"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g22_b6_n_0
);
g22_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"00000E0C001C0C0C"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g22_b7_n_0
);
g23_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000800000038"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g23_b0_n_0
);
g23_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000C00000070"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g23_b1_n_0
);
g23_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"20000006080400E0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g23_b2_n_0
);
g23_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"20000003080401C0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g23_b3_n_0
);
g23_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"200000060FFC0380"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g23_b4_n_0
);
g23_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000C0FFC0700"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g23_b5_n_0
);
g23_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000800000E00"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g23_b6_n_0
);
g23_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g23_b7_n_0
);
g24_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07C0000407000000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g24_b0_n_0
);
g24_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00FFC0FA00000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g24_b1_n_0
);
g24_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"08200FFC08A00003"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g24_b2_n_0
);
g24_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0820082008A00007"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g24_b3_n_0
);
g24_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0820086007E00004"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g24_b4_n_0
);
g24_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0C600FC00FC00000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g24_b5_n_0
);
g24_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0440078008000000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g24_b6_n_0
);
g25_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"27C0084007C00780"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g25_b0_n_0
);
g25_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"6FE00FF80FE00FC0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g25_b1_n_0
);
g25_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"48200FFC08A00860"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g25_b2_n_0
);
g25_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"4820084408A00824"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g25_b3_n_0
);
g25_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"7FC0000C08A007FC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g25_b4_n_0
);
g25_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"3FE000180CE00FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g25_b5_n_0
);
g25_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000004C00800"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g25_b6_n_0
);
g26_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0804000000000804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g26_b0_n_0
);
g26_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"3E40003E"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g26_b1_n_0
);
g26_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC700008200FFC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g26_b2_n_0
);
g26_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"018040000FEC0040"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g26_b3_n_0
);
g26_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03C040200FEC0020"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g26_b4_n_0
);
g26_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0E607FEC08000FE0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g26_b5_n_0
);
g26_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0C203FEC00000FC0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g26_b6_n_0
);
g27_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07C000200FE00000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g27_b0_n_0
);
g27_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00FE00FE00000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g27_b1_n_0
);
g27_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"08200FC000600804"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g27_b2_n_0
);
g27_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"082000200FC00FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g27_b3_n_0
);
g27_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE00FE000600800"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g27_b5_n_0
);
g27_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"07C00FC00FE00000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g27_b6_n_0
);
g27_b7: unisim.vcomponents.LUT5
generic map(
INIT => X"00003800"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => g0_b0_i_4_n_0,
I4 => g0_b0_i_5_n_0,
O => g27_b7_n_0
);
g28_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0440082007C04020"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g28_b0_n_0
);
g28_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0CE00FE00FE07FE0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g28_b1_n_0
);
g28_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"09A00FC008207FC0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g28_b2_n_0
);
g28_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0920086048204820"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g28_b3_n_0
);
g28_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0B2000207FC00820"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g28_b4_n_0
);
g28_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0E6000E07FE00FE0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g28_b5_n_0
);
g28_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"044000C0402007C0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g28_b6_n_0
);
g29_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"07E001E007E00020"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g29_b0_n_0
);
g29_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE003E00FE00020"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g29_b1_n_0
);
g29_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0C000600080007F8"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g29_b2_n_0
);
g29_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07000C0008000FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g29_b3_n_0
);
g29_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"07000C0007E00820"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g29_b4_n_0
);
g29_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0006000FE00C20"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g29_b5_n_0
);
g29_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE003E008000400"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g29_b6_n_0
);
g29_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"07E001E000000000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g29_b7_n_0
);
g2_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0780FFFF0000FFFF"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g2_b0_n_0
);
g2_b1: unisim.vcomponents.LUT5
generic map(
INIT => X"38E718FF"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g2_b1_n_0
);
g2_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0860F99F0660FE7F"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g2_b2_n_0
);
g2_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0874FBDF0420FC3F"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g2_b3_n_0
);
g2_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FDCFBDF0420FC3F"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g2_b4_n_0
);
g2_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"078CF99F0660FE7F"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g2_b5_n_0
);
g2_b6: unisim.vcomponents.LUT5
generic map(
INIT => X"06E718FF"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => \char[0]_i_1_n_0\,
I4 => \char[1]_i_1_n_0\,
O => g2_b6_n_0
);
g2_b7: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => g0_b0_i_4_n_0,
O => g2_b7_n_0
);
g30_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000C6047E00820"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g30_b0_n_0
);
g30_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00400E604FE00C60"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g30_b1_n_0
);
g30_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"00400B20480006C0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g30_b2_n_0
);
g30_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07F809A048000380"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g30_b3_n_0
);
g30_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FBC08E068000380"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g30_b4_n_0
);
g30_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"08040C603FE006C0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g30_b5_n_0
);
g30_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"08040C201FE00C60"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g30_b6_n_0
);
g30_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000820"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g30_b7_n_0
);
g31_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0780000800000000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => \char[1]_i_1_n_0\,
O => g31_b0_n_0
);
g31_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"07C0000C08040000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g31_b1_n_0
);
g31_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0460000408040000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g31_b2_n_0
);
g31_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0430000C0FBC0FBC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g31_b3_n_0
);
g31_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0460000807F80FBC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g31_b4_n_0
);
g31_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"07C0000C00400000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g31_b5_n_0
);
g31_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0780000400400000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g31_b6_n_0
);
g3_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"02A01C000C000000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g3_b0_n_0
);
g3_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"02A01FFC0E000278"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b1_n_0
);
g3_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"01C00FFC0FFC02FC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b2_n_0
);
g3_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"0F78001407FC0F84"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g3_b3_n_0
);
g3_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0F78001400140F84"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g3_b4_n_0
);
g3_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"01C00E14001402FC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b5_n_0
);
g3_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"02A00FFC001C0278"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g3_b6_n_0
);
g3_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"02A007FC001C0000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g3_b7_n_0
);
g4_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000400FFE"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g4_b0_n_0
);
g4_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC0110004007FC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g4_b1_n_0
);
g4_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC031800E003F8"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g4_b2_n_0
);
g4_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"000007FC01F001F0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g4_b3_n_0
);
g4_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"000007FC03F800E0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g4_b4_n_0
);
g4_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC031807FC0040"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g4_b5_n_0
);
g4_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0DFC01100FFE0040"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g4_b6_n_0
);
g5_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00000F0008C40038"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g5_b0_n_0
);
g5_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"09100F0019EE007C"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g5_b1_n_0
);
g5_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"1B180F00133A0044"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g5_b2_n_0
);
g5_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"1FFC0F0012120FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g5_b3_n_0
);
g5_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFC0F0017320FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g5_b4_n_0
);
g5_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"0B180F001DE60004"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g5_b5_n_0
);
g5_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"09100F0008C40FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g5_b6_n_0
);
g5_b7: unisim.vcomponents.LUT5
generic map(
INIT => X"0000003E"
)
port map (
I0 => sel(1),
I1 => sel(2),
I2 => sel(3),
I3 => g0_b0_i_4_n_0,
I4 => g0_b0_i_5_n_0,
O => g5_b7_n_0
);
g6_b0: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_5_n_0,
O => g6_b0_n_0
);
g6_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"01C0008002000010"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g6_b1_n_0
);
g6_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"03E0008006000018"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g6_b2_n_0
);
g6_b3: unisim.vcomponents.LUT5
generic map(
INIT => X"02A00FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_5_n_0,
O => g6_b3_n_0
);
g6_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"008003E00FFC0FFC"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g6_b4_n_0
);
g6_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"008001C006000018"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g6_b5_n_0
);
g6_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0080008002000010"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g6_b6_n_0
);
g7_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"00300600008003C0"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g7_b0_n_0
);
g7_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00F0078001C003C0"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b1_n_0
);
g7_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"03F007E003E00200"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b2_n_0
);
g7_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"07F007F000800200"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g7_b3_n_0
);
g7_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"03F007E000800200"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g7_b4_n_0
);
g7_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"00F0078003E00200"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b5_n_0
);
g7_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0030060001C00200"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g7_b6_n_0
);
g7_b7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g7_b7_n_0
);
g8_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"0220000000000000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g8_b0_n_0
);
g8_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"0FF8000E00000000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g8_b1_n_0
);
g8_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FF8001E00380000"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g8_b2_n_0
);
g8_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"022000000DFC0000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g8_b3_n_0
);
g8_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"0FF800000DFC0000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g8_b4_n_0
);
g8_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"0220000E00000000"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g8_b6_n_0
);
g9_b0: unisim.vcomponents.LUT6
generic map(
INIT => X"000007800C300638"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g9_b0_n_0
);
g9_b1: unisim.vcomponents.LUT6
generic map(
INIT => X"00100FD806300C7C"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g9_b1_n_0
);
g9_b2: unisim.vcomponents.LUT6
generic map(
INIT => X"001E087C03000844"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g9_b2_n_0
);
g9_b3: unisim.vcomponents.LUT6
generic map(
INIT => X"000E08E401803847"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g9_b3_n_0
);
g9_b4: unisim.vcomponents.LUT6
generic map(
INIT => X"000007BC00C03847"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => g0_b0_i_4_n_0,
I5 => g0_b0_i_5_n_0,
O => g9_b4_n_0
);
g9_b5: unisim.vcomponents.LUT6
generic map(
INIT => X"00000FD80C600FCC"
)
port map (
I0 => g0_b0_i_1_n_0,
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g9_b5_n_0
);
g9_b6: unisim.vcomponents.LUT6
generic map(
INIT => X"000008400C300798"
)
port map (
I0 => sel(0),
I1 => sel(1),
I2 => sel(2),
I3 => sel(3),
I4 => \char[0]_i_1_n_0\,
I5 => \char[1]_i_1_n_0\,
O => g9_b6_n_0
);
hSync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AEBBFFFF"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => \h_count_reg_n_0_[6]\,
I2 => \h_count[9]_i_2_n_0\,
I3 => \h_count_reg_n_0_[5]\,
I4 => \h_count_reg_n_0_[7]\,
I5 => hSync_i_2_n_0,
O => hSync_i_1_n_0
);
hSync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"EBFFFFFF"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => \h_count_reg_n_0_[8]\,
I2 => hSync_i_3_n_0,
I3 => \h_count_reg_n_0_[10]\,
I4 => hSync_i_4_n_0,
O => hSync_i_2_n_0
);
hSync_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => \h_count_reg_n_0_[7]\,
I1 => \h_count_reg_n_0_[4]\,
I2 => \h_count[7]_i_2_n_0\,
I3 => \h_count_reg_n_0_[3]\,
I4 => \h_count_reg_n_0_[5]\,
I5 => \h_count_reg_n_0_[6]\,
O => hSync_i_3_n_0
);
hSync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F7FFEFAA"
)
port map (
I0 => \h_count_reg_n_0_[7]\,
I1 => \h_count_reg_n_0_[4]\,
I2 => hSync_i_5_n_0,
I3 => \h_count_reg_n_0_[5]\,
I4 => \h_count_reg_n_0_[6]\,
I5 => \h_count[10]_i_1_n_0\,
O => hSync_i_4_n_0
);
hSync_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \h_count_reg_n_0_[2]\,
I1 => \h_count_reg_n_0_[0]\,
I2 => \h_count_reg_n_0_[1]\,
I3 => \h_count_reg_n_0_[3]\,
O => hSync_i_5_n_0
);
hSync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => hSync_i_1_n_0,
Q => Hsync_OBUF,
R => '0'
);
\h_count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_n_0_[0]\,
O => \h_count[0]_i_1_n_0\
);
\h_count[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFFAAAAEAAA"
)
port map (
I0 => \h_count[10]_i_3_n_0\,
I1 => \h_count_reg_n_0_[2]\,
I2 => \h_count_reg_n_0_[0]\,
I3 => \h_count_reg_n_0_[1]\,
I4 => \h_count[10]_i_4_n_0\,
I5 => \h_count_reg_n_0_[3]\,
O => \h_count[10]_i_1_n_0\
);
\h_count[10]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_n_0_[8]\,
I1 => \h_count_reg_n_0_[7]\,
I2 => \h_count[10]_i_5_n_0\,
I3 => \h_count_reg_n_0_[9]\,
I4 => \h_count_reg_n_0_[10]\,
O => \h_count[10]_i_2_n_0\
);
\h_count[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888880808000"
)
port map (
I0 => \h_count_reg_n_0_[10]\,
I1 => \h_count_reg_n_0_[9]\,
I2 => \h_count_reg_n_0_[7]\,
I3 => \h_count_reg_n_0_[6]\,
I4 => \h_count_reg_n_0_[5]\,
I5 => \h_count_reg_n_0_[8]\,
O => \h_count[10]_i_3_n_0\
);
\h_count[10]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \h_count_reg_n_0_[10]\,
I1 => \h_count_reg_n_0_[9]\,
I2 => \h_count_reg_n_0_[4]\,
I3 => \h_count_reg_n_0_[7]\,
O => \h_count[10]_i_4_n_0\
);
\h_count[10]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \h_count_reg_n_0_[6]\,
I1 => \h_count_reg_n_0_[5]\,
I2 => \h_count_reg_n_0_[3]\,
I3 => \h_count[7]_i_2_n_0\,
I4 => \h_count_reg_n_0_[4]\,
O => \h_count[10]_i_5_n_0\
);
\h_count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_n_0_[0]\,
I1 => \h_count_reg_n_0_[1]\,
O => \h_count[1]_i_1_n_0\
);
\h_count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_n_0_[2]\,
I1 => \h_count_reg_n_0_[0]\,
I2 => \h_count_reg_n_0_[1]\,
O => \h_count[2]_i_1_n_0\
);
\h_count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_n_0_[3]\,
I1 => \h_count_reg_n_0_[2]\,
I2 => \h_count_reg_n_0_[0]\,
I3 => \h_count_reg_n_0_[1]\,
O => \h_count[3]_i_1_n_0\
);
\h_count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_n_0_[2]\,
I1 => \h_count_reg_n_0_[0]\,
I2 => \h_count_reg_n_0_[1]\,
I3 => \h_count_reg_n_0_[3]\,
I4 => \h_count_reg_n_0_[4]\,
O => \h_count[4]_i_1_n_0\
);
\h_count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \h_count_reg_n_0_[3]\,
I1 => \h_count_reg_n_0_[1]\,
I2 => \h_count_reg_n_0_[0]\,
I3 => \h_count_reg_n_0_[2]\,
I4 => \h_count_reg_n_0_[4]\,
I5 => \h_count_reg_n_0_[5]\,
O => \h_count[5]_i_1_n_0\
);
\h_count[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \h_count_reg_n_0_[6]\,
I1 => \h_count_reg_n_0_[4]\,
I2 => \h_count[7]_i_2_n_0\,
I3 => \h_count_reg_n_0_[3]\,
I4 => \h_count_reg_n_0_[5]\,
O => \h_count[6]_i_1_n_0\
);
\h_count[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFFFF00800000"
)
port map (
I0 => \h_count_reg_n_0_[6]\,
I1 => \h_count_reg_n_0_[5]\,
I2 => \h_count_reg_n_0_[3]\,
I3 => \h_count[7]_i_2_n_0\,
I4 => \h_count_reg_n_0_[4]\,
I5 => \h_count_reg_n_0_[7]\,
O => \h_count[7]_i_1_n_0\
);
\h_count[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \h_count_reg_n_0_[1]\,
I1 => \h_count_reg_n_0_[0]\,
I2 => \h_count_reg_n_0_[2]\,
O => \h_count[7]_i_2_n_0\
);
\h_count[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFFF2000"
)
port map (
I0 => \h_count_reg_n_0_[7]\,
I1 => \h_count[9]_i_2_n_0\,
I2 => \h_count_reg_n_0_[5]\,
I3 => \h_count_reg_n_0_[6]\,
I4 => \h_count_reg_n_0_[8]\,
O => \h_count[8]_i_1_n_0\
);
\h_count[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFF08000000"
)
port map (
I0 => \h_count_reg_n_0_[6]\,
I1 => \h_count_reg_n_0_[5]\,
I2 => \h_count[9]_i_2_n_0\,
I3 => \h_count_reg_n_0_[7]\,
I4 => \h_count_reg_n_0_[8]\,
I5 => \h_count_reg_n_0_[9]\,
O => \h_count[9]_i_1_n_0\
);
\h_count[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \h_count_reg_n_0_[3]\,
I1 => \h_count_reg_n_0_[1]\,
I2 => \h_count_reg_n_0_[0]\,
I3 => \h_count_reg_n_0_[2]\,
I4 => \h_count_reg_n_0_[4]\,
O => \h_count[9]_i_2_n_0\
);
\h_count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[0]_i_1_n_0\,
Q => \h_count_reg_n_0_[0]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[10]_i_2_n_0\,
Q => \h_count_reg_n_0_[10]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[1]_i_1_n_0\,
Q => \h_count_reg_n_0_[1]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[2]_i_1_n_0\,
Q => \h_count_reg_n_0_[2]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[3]_i_1_n_0\,
Q => \h_count_reg_n_0_[3]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[4]_i_1_n_0\,
Q => \h_count_reg_n_0_[4]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[5]_i_1_n_0\,
Q => \h_count_reg_n_0_[5]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[6]_i_1_n_0\,
Q => \h_count_reg_n_0_[6]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[7]_i_1_n_0\,
Q => \h_count_reg_n_0_[7]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[8]_i_1_n_0\,
Q => \h_count_reg_n_0_[8]\,
R => \h_count[10]_i_1_n_0\
);
\h_count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \h_count[9]_i_1_n_0\,
Q => \h_count_reg_n_0_[9]\,
R => \h_count[10]_i_1_n_0\
);
vSync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAEBAAEAAAAAAAAA"
)
port map (
I0 => vSync_i_2_n_0,
I1 => vSync_i_3_n_0,
I2 => \v_count_reg_n_0_[9]\,
I3 => vSync_i_4_n_0,
I4 => \v_count_reg_n_0_[10]\,
I5 => \v_count[10]_i_2_n_0\,
O => vSync_i_1_n_0
);
vSync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => vSync_i_5_n_0,
I2 => \v_count_reg_n_0_[3]\,
I3 => \v_count_reg_n_0_[4]\,
I4 => \v_count_reg_n_0_[5]\,
I5 => \v_count_reg_n_0_[10]\,
O => vSync_i_2_n_0
);
vSync_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \v_count_reg_n_0_[8]\,
I1 => \v_count[10]_i_3_n_0\,
O => vSync_i_3_n_0
);
vSync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFDFFFFFFFFB"
)
port map (
I0 => \v_count_reg_n_0_[8]\,
I1 => \v_count[6]_i_2_n_0\,
I2 => \v_count_reg_n_0_[6]\,
I3 => vSync_i_6_n_0,
I4 => \v_count_reg_n_0_[2]\,
I5 => \v_count_reg_n_0_[7]\,
O => vSync_i_4_n_0
);
vSync_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"FD57"
)
port map (
I0 => \v_count[1]_i_3_n_0\,
I1 => \v_count_reg_n_0_[1]\,
I2 => \v_count_reg_n_0_[0]\,
I3 => \v_count_reg_n_0_[2]\,
O => vSync_i_5_n_0
);
vSync_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \v_count_reg_n_0_[5]\,
I1 => \v_count_reg_n_0_[4]\,
I2 => \v_count_reg_n_0_[3]\,
O => vSync_i_6_n_0
);
vSync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => vSync_i_1_n_0,
Q => Vsync_OBUF,
R => '0'
);
\v_count[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => \v_count_reg_n_0_[0]\,
I2 => \v_count[10]_i_2_n_0\,
O => sel(0)
);
\v_count[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D0DCD0D0D0D0D0"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => \v_count[10]_i_2_n_0\,
I2 => \v_count_reg_n_0_[10]\,
I3 => \v_count_reg_n_0_[8]\,
I4 => \v_count[10]_i_3_n_0\,
I5 => \v_count_reg_n_0_[9]\,
O => v_count3_out(10)
);
\v_count[10]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \h_count[10]_i_1_n_0\,
I1 => \v_count[1]_i_2_n_0\,
O => \v_count[10]_i_2_n_0\
);
\v_count[10]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFFFFFFFFFF"
)
port map (
I0 => \v_count_reg_n_0_[6]\,
I1 => \v_count_reg_n_0_[4]\,
I2 => \v_count[10]_i_4_n_0\,
I3 => \v_count_reg_n_0_[3]\,
I4 => \v_count_reg_n_0_[5]\,
I5 => \v_count_reg_n_0_[7]\,
O => \v_count[10]_i_3_n_0\
);
\v_count[10]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \v_count_reg_n_0_[0]\,
I1 => \v_count_reg_n_0_[1]\,
I2 => \v_count_reg_n_0_[2]\,
O => \v_count[10]_i_4_n_0\
);
\v_count[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1F40"
)
port map (
I0 => \v_count[1]_i_2_n_0\,
I1 => \v_count_reg_n_0_[0]\,
I2 => \h_count[10]_i_1_n_0\,
I3 => \v_count_reg_n_0_[1]\,
O => sel(1)
);
\v_count[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88808888AAAAAAAA"
)
port map (
I0 => \v_count_reg_n_0_[10]\,
I1 => \v_count_reg_n_0_[5]\,
I2 => \v_count_reg_n_0_[3]\,
I3 => \v_count_reg_n_0_[4]\,
I4 => \v_count[10]_i_4_n_0\,
I5 => \v_count[1]_i_3_n_0\,
O => \v_count[1]_i_2_n_0\
);
\v_count[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \v_count_reg_n_0_[9]\,
I1 => \v_count_reg_n_0_[6]\,
I2 => \v_count_reg_n_0_[8]\,
I3 => \v_count_reg_n_0_[7]\,
O => \v_count[1]_i_3_n_0\
);
\v_count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_n_0_[2]\,
I1 => \v_count_reg_n_0_[0]\,
I2 => \v_count_reg_n_0_[1]\,
O => \v_count[2]_i_1_n_0\
);
\v_count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_n_0_[3]\,
I1 => \v_count_reg_n_0_[2]\,
I2 => \v_count_reg_n_0_[1]\,
I3 => \v_count_reg_n_0_[0]\,
O => \v_count[3]_i_1_n_0\
);
\v_count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_n_0_[4]\,
I1 => \v_count_reg_n_0_[3]\,
I2 => \v_count_reg_n_0_[0]\,
I3 => \v_count_reg_n_0_[1]\,
I4 => \v_count_reg_n_0_[2]\,
O => \v_count[4]_i_1_n_0\
);
\v_count[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \v_count[1]_i_2_n_0\,
I1 => \h_count[10]_i_1_n_0\,
O => \v_count[5]_i_1_n_0\
);
\v_count[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_n_0_[5]\,
I1 => \v_count_reg_n_0_[4]\,
I2 => \v_count_reg_n_0_[2]\,
I3 => \v_count_reg_n_0_[1]\,
I4 => \v_count_reg_n_0_[0]\,
I5 => \v_count_reg_n_0_[3]\,
O => \v_count[5]_i_2_n_0\
);
\v_count[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F44"
)
port map (
I0 => \v_count[6]_i_2_n_0\,
I1 => \v_count[10]_i_2_n_0\,
I2 => \h_count[10]_i_1_n_0\,
I3 => \v_count_reg_n_0_[6]\,
O => v_count3_out(6)
);
\v_count[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \v_count_reg_n_0_[4]\,
I1 => \v_count_reg_n_0_[2]\,
I2 => \v_count_reg_n_0_[1]\,
I3 => \v_count_reg_n_0_[0]\,
I4 => \v_count_reg_n_0_[3]\,
I5 => \v_count_reg_n_0_[5]\,
O => \v_count[6]_i_2_n_0\
);
\v_count[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F44"
)
port map (
I0 => \v_count[7]_i_2_n_0\,
I1 => \v_count[10]_i_2_n_0\,
I2 => \h_count[10]_i_1_n_0\,
I3 => \v_count_reg_n_0_[7]\,
O => v_count3_out(7)
);
\v_count[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \v_count_reg_n_0_[5]\,
I1 => \v_count_reg_n_0_[3]\,
I2 => \v_count[10]_i_4_n_0\,
I3 => \v_count_reg_n_0_[4]\,
I4 => \v_count_reg_n_0_[6]\,
O => \v_count[7]_i_2_n_0\
);
\v_count[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F44"
)
port map (
I0 => \v_count[10]_i_3_n_0\,
I1 => \v_count[10]_i_2_n_0\,
I2 => \h_count[10]_i_1_n_0\,
I3 => \v_count_reg_n_0_[8]\,
O => v_count3_out(8)
);
\v_count[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0FF4040"
)
port map (
I0 => \v_count[10]_i_3_n_0\,
I1 => \v_count_reg_n_0_[8]\,
I2 => \v_count[10]_i_2_n_0\,
I3 => \h_count[10]_i_1_n_0\,
I4 => \v_count_reg_n_0_[9]\,
O => v_count3_out(9)
);
\v_count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => sel(0),
Q => \v_count_reg_n_0_[0]\,
R => '0'
);
\v_count_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => v_count3_out(10),
Q => \v_count_reg_n_0_[10]\,
R => '0'
);
\v_count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => sel(1),
Q => \v_count_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \h_count[10]_i_1_n_0\,
D => \v_count[2]_i_1_n_0\,
Q => \v_count_reg_n_0_[2]\,
R => \v_count[5]_i_1_n_0\
);
\v_count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \h_count[10]_i_1_n_0\,
D => \v_count[3]_i_1_n_0\,
Q => \v_count_reg_n_0_[3]\,
R => \v_count[5]_i_1_n_0\
);
\v_count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \h_count[10]_i_1_n_0\,
D => \v_count[4]_i_1_n_0\,
Q => \v_count_reg_n_0_[4]\,
R => \v_count[5]_i_1_n_0\
);
\v_count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => \h_count[10]_i_1_n_0\,
D => \v_count[5]_i_2_n_0\,
Q => \v_count_reg_n_0_[5]\,
R => \v_count[5]_i_1_n_0\
);
\v_count_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => v_count3_out(6),
Q => \v_count_reg_n_0_[6]\,
R => '0'
);
\v_count_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => v_count3_out(7),
Q => \v_count_reg_n_0_[7]\,
R => '0'
);
\v_count_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => v_count3_out(8),
Q => \v_count_reg_n_0_[8]\,
R => '0'
);
\v_count_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => v_count3_out(9),
Q => \v_count_reg_n_0_[9]\,
R => '0'
);
\vgaRed[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000099A5"
)
port map (
I0 => \char[7]_i_2_n_0\,
I1 => \vgaRed[0]_i_2_n_0\,
I2 => \vgaRed[0]_i_3_n_0\,
I3 => \vgaRed[0]_i_4_n_0\,
I4 => \char[7]_i_3_n_0\,
O => \vgaRed[0]_i_1_n_0\
);
\vgaRed[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_33_n_0\,
I1 => \vgaRed[0]_i_34_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_35_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_36_n_0\,
O => \vgaRed[0]_i_15_n_0\
);
\vgaRed[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_37_n_0\,
I1 => \vgaRed_reg[0]_i_38_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_39_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_40_n_0\,
O => \vgaRed[0]_i_16_n_0\
);
\vgaRed[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FC000C0A000A000"
)
port map (
I0 => g30_b7_n_0,
I1 => g29_b7_n_0,
I2 => \char[4]_i_1_n_0\,
I3 => \char[3]_i_1_n_0\,
I4 => g27_b7_n_0,
I5 => \char[2]_i_1_n_0\,
O => \vgaRed[0]_i_17_n_0\
);
\vgaRed[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFC0A0C0A000A000"
)
port map (
I0 => \vgaRed_reg[0]_i_41_n_0\,
I1 => g21_b7_n_0,
I2 => \char[4]_i_1_n_0\,
I3 => \char[3]_i_1_n_0\,
I4 => g19_b7_n_0,
I5 => \char[2]_i_1_n_0\,
O => \vgaRed[0]_i_18_n_0\
);
\vgaRed[0]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => g10_b0_n_0,
I1 => \char[2]_i_1_n_0\,
I2 => \char[3]_i_1_n_0\,
I3 => \char[4]_i_1_n_0\,
O => \vgaRed[0]_i_19_n_0\
);
\vgaRed[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => \vgaRed_reg[0]_i_5_n_0\,
I1 => \vgaRed[0]_i_6_n_0\,
I2 => \vgaRed[0]_i_7_n_0\,
I3 => \vgaRed_reg[0]_i_8_n_0\,
I4 => \vgaRed[0]_i_9_n_0\,
I5 => \vgaRed_reg[0]_i_10_n_0\,
O => \vgaRed[0]_i_2_n_0\
);
\vgaRed[0]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \vgaRed[0]_i_42_n_0\,
I1 => \char[4]_i_1_n_0\,
I2 => \vgaRed_reg[0]_i_43_n_0\,
I3 => \char[3]_i_1_n_0\,
I4 => \vgaRed_reg[0]_i_44_n_0\,
O => \vgaRed[0]_i_20_n_0\
);
\vgaRed[0]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_45_n_0\,
I1 => \vgaRed_reg[0]_i_46_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_47_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_48_n_0\,
O => \vgaRed[0]_i_21_n_0\
);
\vgaRed[0]_i_22\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_49_n_0\,
I1 => \vgaRed[0]_i_50_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed[0]_i_51_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_52_n_0\,
O => \vgaRed[0]_i_22_n_0\
);
\vgaRed[0]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_53_n_0\,
I1 => \vgaRed[0]_i_54_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_55_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_56_n_0\,
O => \vgaRed[0]_i_23_n_0\
);
\vgaRed[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_57_n_0\,
I1 => \vgaRed_reg[0]_i_58_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_59_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_60_n_0\,
O => \vgaRed[0]_i_24_n_0\
);
\vgaRed[0]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_61_n_0\,
I1 => \vgaRed[0]_i_62_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_63_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_64_n_0\,
O => \vgaRed[0]_i_25_n_0\
);
\vgaRed[0]_i_26\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_65_n_0\,
I1 => \vgaRed_reg[0]_i_66_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_67_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_68_n_0\,
O => \vgaRed[0]_i_26_n_0\
);
\vgaRed[0]_i_27\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_69_n_0\,
I1 => \vgaRed_reg[0]_i_70_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_71_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_72_n_0\,
O => \vgaRed[0]_i_27_n_0\
);
\vgaRed[0]_i_28\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_73_n_0\,
I1 => \vgaRed[0]_i_74_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed[0]_i_75_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_76_n_0\,
O => \vgaRed[0]_i_28_n_0\
);
\vgaRed[0]_i_29\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_77_n_0\,
I1 => \vgaRed[0]_i_78_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_79_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_80_n_0\,
O => \vgaRed[0]_i_29_n_0\
);
\vgaRed[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"505F3030505F3F3F"
)
port map (
I0 => \vgaRed_reg[0]_i_11_n_0\,
I1 => \vgaRed_reg[0]_i_12_n_0\,
I2 => \vgaRed[0]_i_7_n_0\,
I3 => \vgaRed_reg[0]_i_13_n_0\,
I4 => \vgaRed[0]_i_9_n_0\,
I5 => \vgaRed_reg[0]_i_14_n_0\,
O => \vgaRed[0]_i_3_n_0\
);
\vgaRed[0]_i_30\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_81_n_0\,
I1 => \vgaRed_reg[0]_i_82_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_83_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_84_n_0\,
O => \vgaRed[0]_i_30_n_0\
);
\vgaRed[0]_i_31\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_85_n_0\,
I1 => \vgaRed[0]_i_86_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_87_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_88_n_0\,
O => \vgaRed[0]_i_31_n_0\
);
\vgaRed[0]_i_32\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed_reg[0]_i_89_n_0\,
I1 => \vgaRed_reg[0]_i_90_n_0\,
I2 => \char[5]_i_1_n_0\,
I3 => \vgaRed_reg[0]_i_91_n_0\,
I4 => \char[4]_i_1_n_0\,
I5 => \vgaRed_reg[0]_i_92_n_0\,
O => \vgaRed[0]_i_32_n_0\
);
\vgaRed[0]_i_34\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b6_n_0,
I1 => g10_b1_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b6_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b6_n_0,
O => \vgaRed[0]_i_34_n_0\
);
\vgaRed[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => \h_count_reg_n_0_[1]\,
I1 => \h_count_reg_n_0_[0]\,
I2 => \h_count_reg_n_0_[2]\,
I3 => \h_count[10]_i_1_n_0\,
O => \vgaRed[0]_i_4_n_0\
);
\vgaRed[0]_i_42\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => g7_b7_n_0,
I1 => \char[3]_i_1_n_0\,
I2 => \char[2]_i_1_n_0\,
I3 => g5_b7_n_0,
O => \vgaRed[0]_i_42_n_0\
);
\vgaRed[0]_i_50\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g27_b3_n_0,
I1 => g26_b4_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g25_b4_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g24_b4_n_0,
O => \vgaRed[0]_i_50_n_0\
);
\vgaRed[0]_i_51\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g23_b4_n_0,
I1 => g22_b4_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g21_b3_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g20_b4_n_0,
O => \vgaRed[0]_i_51_n_0\
);
\vgaRed[0]_i_54\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b5_n_0,
I1 => g10_b5_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b5_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b2_n_0,
O => \vgaRed[0]_i_54_n_0\
);
\vgaRed[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \vgaRed[0]_i_17_n_0\,
I1 => \vgaRed[0]_i_18_n_0\,
I2 => \char[6]_i_1_n_0\,
I3 => \vgaRed[0]_i_19_n_0\,
I4 => \char[5]_i_1_n_0\,
I5 => \vgaRed[0]_i_20_n_0\,
O => \vgaRed[0]_i_6_n_0\
);
\vgaRed[0]_i_62\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b2_n_0,
I1 => g10_b2_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b2_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b2_n_0,
O => \vgaRed[0]_i_62_n_0\
);
\vgaRed[0]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \h_count_reg_n_0_[1]\,
I1 => \h_count_reg_n_0_[0]\,
I2 => \h_count[10]_i_1_n_0\,
O => \vgaRed[0]_i_7_n_0\
);
\vgaRed[0]_i_74\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g27_b3_n_0,
I1 => g26_b3_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g25_b3_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g24_b3_n_0,
O => \vgaRed[0]_i_74_n_0\
);
\vgaRed[0]_i_75\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g23_b3_n_0,
I1 => g22_b3_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g21_b3_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g20_b3_n_0,
O => \vgaRed[0]_i_75_n_0\
);
\vgaRed[0]_i_78\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b0_n_0,
I1 => g10_b0_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b0_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b0_n_0,
O => \vgaRed[0]_i_78_n_0\
);
\vgaRed[0]_i_86\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => g11_b1_n_0,
I1 => g10_b1_n_0,
I2 => \char[3]_i_1_n_0\,
I3 => g9_b1_n_0,
I4 => \char[2]_i_1_n_0\,
I5 => g8_b1_n_0,
O => \vgaRed[0]_i_86_n_0\
);
\vgaRed[0]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \h_count_reg_n_0_[0]\,
I1 => \h_count[10]_i_1_n_0\,
O => \vgaRed[0]_i_9_n_0\
);
\vgaRed_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk108M,
CE => '1',
D => \vgaRed[0]_i_1_n_0\,
Q => vgaBlue_OBUF(0),
R => '0'
);
\vgaRed_reg[0]_i_10\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_23_n_0\,
I1 => \vgaRed[0]_i_24_n_0\,
O => \vgaRed_reg[0]_i_10_n_0\,
S => \char[6]_i_1_n_0\
);
\vgaRed_reg[0]_i_100\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b6_n_0,
I1 => g31_b6_n_0,
O => \vgaRed_reg[0]_i_100_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_101\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b6_n_0,
I1 => g25_b6_n_0,
O => \vgaRed_reg[0]_i_101_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_102\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b6_n_0,
I1 => g27_b6_n_0,
O => \vgaRed_reg[0]_i_102_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_103\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b6_n_0,
I1 => g21_b6_n_0,
O => \vgaRed_reg[0]_i_103_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_104\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b6_n_0,
I1 => g23_b6_n_0,
O => \vgaRed_reg[0]_i_104_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_105\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b6_n_0,
I1 => g17_b6_n_0,
O => \vgaRed_reg[0]_i_105_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_106\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b6_n_0,
I1 => g19_b6_n_0,
O => \vgaRed_reg[0]_i_106_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_107\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b4_n_0,
I1 => g13_b4_n_0,
O => \vgaRed_reg[0]_i_107_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_108\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b4_n_0,
I1 => g15_b4_n_0,
O => \vgaRed_reg[0]_i_108_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_109\: unisim.vcomponents.MUXF7
port map (
I0 => g8_b4_n_0,
I1 => g9_b4_n_0,
O => \vgaRed_reg[0]_i_109_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_11\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_25_n_0\,
I1 => \vgaRed[0]_i_26_n_0\,
O => \vgaRed_reg[0]_i_11_n_0\,
S => \char[6]_i_1_n_0\
);
\vgaRed_reg[0]_i_110\: unisim.vcomponents.MUXF7
port map (
I0 => g10_b4_n_0,
I1 => g11_b4_n_0,
O => \vgaRed_reg[0]_i_110_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_111\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b4_n_0,
I1 => g5_b4_n_0,
O => \vgaRed_reg[0]_i_111_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_112\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b4_n_0,
I1 => g7_b4_n_0,
O => \vgaRed_reg[0]_i_112_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_113\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b4_n_0,
I1 => g1_b4_n_0,
O => \vgaRed_reg[0]_i_113_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_114\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b4_n_0,
I1 => g3_b4_n_0,
O => \vgaRed_reg[0]_i_114_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_115\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b4_n_0,
I1 => g29_b4_n_0,
O => \vgaRed_reg[0]_i_115_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_116\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b4_n_0,
I1 => g31_b4_n_0,
O => \vgaRed_reg[0]_i_116_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_117\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b4_n_0,
I1 => g17_b4_n_0,
O => \vgaRed_reg[0]_i_117_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_118\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b4_n_0,
I1 => g19_b4_n_0,
O => \vgaRed_reg[0]_i_118_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_119\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b5_n_0,
I1 => g13_b5_n_0,
O => \vgaRed_reg[0]_i_119_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_12\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_27_n_0\,
I1 => \vgaRed[0]_i_28_n_0\,
O => \vgaRed_reg[0]_i_12_n_0\,
S => \char[6]_i_1_n_0\
);
\vgaRed_reg[0]_i_120\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b5_n_0,
I1 => g15_b5_n_0,
O => \vgaRed_reg[0]_i_120_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_121\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b5_n_0,
I1 => g5_b5_n_0,
O => \vgaRed_reg[0]_i_121_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_122\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b5_n_0,
I1 => g7_b5_n_0,
O => \vgaRed_reg[0]_i_122_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_123\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b5_n_0,
I1 => g1_b5_n_0,
O => \vgaRed_reg[0]_i_123_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_124\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b5_n_0,
I1 => g3_b5_n_0,
O => \vgaRed_reg[0]_i_124_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_125\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b5_n_0,
I1 => g29_b5_n_0,
O => \vgaRed_reg[0]_i_125_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_126\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b5_n_0,
I1 => g31_b5_n_0,
O => \vgaRed_reg[0]_i_126_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_127\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b5_n_0,
I1 => g25_b5_n_0,
O => \vgaRed_reg[0]_i_127_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_128\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b5_n_0,
I1 => g27_b5_n_0,
O => \vgaRed_reg[0]_i_128_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_129\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b5_n_0,
I1 => g21_b5_n_0,
O => \vgaRed_reg[0]_i_129_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_13\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_29_n_0\,
I1 => \vgaRed[0]_i_30_n_0\,
O => \vgaRed_reg[0]_i_13_n_0\,
S => \char[6]_i_1_n_0\
);
\vgaRed_reg[0]_i_130\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b5_n_0,
I1 => g23_b5_n_0,
O => \vgaRed_reg[0]_i_130_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_131\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b5_n_0,
I1 => g17_b5_n_0,
O => \vgaRed_reg[0]_i_131_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_132\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b5_n_0,
I1 => g19_b5_n_0,
O => \vgaRed_reg[0]_i_132_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_133\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b2_n_0,
I1 => g13_b2_n_0,
O => \vgaRed_reg[0]_i_133_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_134\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b2_n_0,
I1 => g15_b2_n_0,
O => \vgaRed_reg[0]_i_134_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_135\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b2_n_0,
I1 => g5_b2_n_0,
O => \vgaRed_reg[0]_i_135_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_136\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b2_n_0,
I1 => g7_b2_n_0,
O => \vgaRed_reg[0]_i_136_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_137\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b2_n_0,
I1 => g1_b2_n_0,
O => \vgaRed_reg[0]_i_137_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_138\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b2_n_0,
I1 => g3_b2_n_0,
O => \vgaRed_reg[0]_i_138_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_139\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b2_n_0,
I1 => g29_b2_n_0,
O => \vgaRed_reg[0]_i_139_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_14\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_31_n_0\,
I1 => \vgaRed[0]_i_32_n_0\,
O => \vgaRed_reg[0]_i_14_n_0\,
S => \char[6]_i_1_n_0\
);
\vgaRed_reg[0]_i_140\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b2_n_0,
I1 => g31_b2_n_0,
O => \vgaRed_reg[0]_i_140_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_141\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b2_n_0,
I1 => g25_b2_n_0,
O => \vgaRed_reg[0]_i_141_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_142\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b2_n_0,
I1 => g27_b2_n_0,
O => \vgaRed_reg[0]_i_142_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_143\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b2_n_0,
I1 => g21_b2_n_0,
O => \vgaRed_reg[0]_i_143_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_144\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b2_n_0,
I1 => g23_b2_n_0,
O => \vgaRed_reg[0]_i_144_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_145\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b2_n_0,
I1 => g17_b2_n_0,
O => \vgaRed_reg[0]_i_145_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_146\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b2_n_0,
I1 => g19_b2_n_0,
O => \vgaRed_reg[0]_i_146_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_147\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b3_n_0,
I1 => g13_b3_n_0,
O => \vgaRed_reg[0]_i_147_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_148\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b3_n_0,
I1 => g15_b3_n_0,
O => \vgaRed_reg[0]_i_148_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_149\: unisim.vcomponents.MUXF7
port map (
I0 => g8_b3_n_0,
I1 => g9_b3_n_0,
O => \vgaRed_reg[0]_i_149_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_150\: unisim.vcomponents.MUXF7
port map (
I0 => g10_b3_n_0,
I1 => g11_b3_n_0,
O => \vgaRed_reg[0]_i_150_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_151\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b3_n_0,
I1 => g5_b3_n_0,
O => \vgaRed_reg[0]_i_151_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_152\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b3_n_0,
I1 => g7_b3_n_0,
O => \vgaRed_reg[0]_i_152_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_153\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b3_n_0,
I1 => g1_b3_n_0,
O => \vgaRed_reg[0]_i_153_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_154\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b3_n_0,
I1 => g3_b3_n_0,
O => \vgaRed_reg[0]_i_154_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_155\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b3_n_0,
I1 => g29_b3_n_0,
O => \vgaRed_reg[0]_i_155_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_156\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b3_n_0,
I1 => g31_b3_n_0,
O => \vgaRed_reg[0]_i_156_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_157\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b3_n_0,
I1 => g17_b3_n_0,
O => \vgaRed_reg[0]_i_157_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_158\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b3_n_0,
I1 => g19_b3_n_0,
O => \vgaRed_reg[0]_i_158_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_159\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b0_n_0,
I1 => g13_b0_n_0,
O => \vgaRed_reg[0]_i_159_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_160\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b0_n_0,
I1 => g15_b0_n_0,
O => \vgaRed_reg[0]_i_160_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_161\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b0_n_0,
I1 => g5_b0_n_0,
O => \vgaRed_reg[0]_i_161_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_162\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b0_n_0,
I1 => g7_b0_n_0,
O => \vgaRed_reg[0]_i_162_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_163\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b0_n_0,
I1 => g1_b0_n_0,
O => \vgaRed_reg[0]_i_163_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_164\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b0_n_0,
I1 => g3_b0_n_0,
O => \vgaRed_reg[0]_i_164_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_165\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b0_n_0,
I1 => g29_b0_n_0,
O => \vgaRed_reg[0]_i_165_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_166\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b0_n_0,
I1 => g31_b0_n_0,
O => \vgaRed_reg[0]_i_166_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_167\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b0_n_0,
I1 => g25_b0_n_0,
O => \vgaRed_reg[0]_i_167_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_168\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b0_n_0,
I1 => g27_b0_n_0,
O => \vgaRed_reg[0]_i_168_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_169\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b0_n_0,
I1 => g21_b0_n_0,
O => \vgaRed_reg[0]_i_169_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_170\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b0_n_0,
I1 => g23_b0_n_0,
O => \vgaRed_reg[0]_i_170_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_171\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b0_n_0,
I1 => g17_b0_n_0,
O => \vgaRed_reg[0]_i_171_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_172\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b0_n_0,
I1 => g19_b0_n_0,
O => \vgaRed_reg[0]_i_172_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_173\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b1_n_0,
I1 => g13_b1_n_0,
O => \vgaRed_reg[0]_i_173_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_174\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b1_n_0,
I1 => g15_b1_n_0,
O => \vgaRed_reg[0]_i_174_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_175\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b1_n_0,
I1 => g5_b1_n_0,
O => \vgaRed_reg[0]_i_175_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_176\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b1_n_0,
I1 => g7_b1_n_0,
O => \vgaRed_reg[0]_i_176_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_177\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b1_n_0,
I1 => g1_b1_n_0,
O => \vgaRed_reg[0]_i_177_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_178\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b1_n_0,
I1 => g3_b1_n_0,
O => \vgaRed_reg[0]_i_178_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_179\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b1_n_0,
I1 => g29_b1_n_0,
O => \vgaRed_reg[0]_i_179_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_180\: unisim.vcomponents.MUXF7
port map (
I0 => g30_b1_n_0,
I1 => g31_b1_n_0,
O => \vgaRed_reg[0]_i_180_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_181\: unisim.vcomponents.MUXF7
port map (
I0 => g24_b1_n_0,
I1 => g25_b1_n_0,
O => \vgaRed_reg[0]_i_181_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_182\: unisim.vcomponents.MUXF7
port map (
I0 => g26_b1_n_0,
I1 => g27_b1_n_0,
O => \vgaRed_reg[0]_i_182_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_183\: unisim.vcomponents.MUXF7
port map (
I0 => g20_b1_n_0,
I1 => g21_b1_n_0,
O => \vgaRed_reg[0]_i_183_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_184\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b1_n_0,
I1 => g23_b1_n_0,
O => \vgaRed_reg[0]_i_184_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_185\: unisim.vcomponents.MUXF7
port map (
I0 => g16_b1_n_0,
I1 => g17_b1_n_0,
O => \vgaRed_reg[0]_i_185_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_186\: unisim.vcomponents.MUXF7
port map (
I0 => g18_b1_n_0,
I1 => g19_b1_n_0,
O => \vgaRed_reg[0]_i_186_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_33\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_93_n_0\,
I1 => \vgaRed_reg[0]_i_94_n_0\,
O => \vgaRed_reg[0]_i_33_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_35\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_95_n_0\,
I1 => \vgaRed_reg[0]_i_96_n_0\,
O => \vgaRed_reg[0]_i_35_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_36\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_97_n_0\,
I1 => \vgaRed_reg[0]_i_98_n_0\,
O => \vgaRed_reg[0]_i_36_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_37\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_99_n_0\,
I1 => \vgaRed_reg[0]_i_100_n_0\,
O => \vgaRed_reg[0]_i_37_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_38\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_101_n_0\,
I1 => \vgaRed_reg[0]_i_102_n_0\,
O => \vgaRed_reg[0]_i_38_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_39\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_103_n_0\,
I1 => \vgaRed_reg[0]_i_104_n_0\,
O => \vgaRed_reg[0]_i_39_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_40\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_105_n_0\,
I1 => \vgaRed_reg[0]_i_106_n_0\,
O => \vgaRed_reg[0]_i_40_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_41\: unisim.vcomponents.MUXF7
port map (
I0 => g22_b7_n_0,
I1 => g23_b7_n_0,
O => \vgaRed_reg[0]_i_41_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_43\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b7_n_0,
I1 => g3_b7_n_0,
O => \vgaRed_reg[0]_i_43_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_44\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b7_n_0,
I1 => g1_b7_n_0,
O => \vgaRed_reg[0]_i_44_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_45\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_107_n_0\,
I1 => \vgaRed_reg[0]_i_108_n_0\,
O => \vgaRed_reg[0]_i_45_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_46\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_109_n_0\,
I1 => \vgaRed_reg[0]_i_110_n_0\,
O => \vgaRed_reg[0]_i_46_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_47\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_111_n_0\,
I1 => \vgaRed_reg[0]_i_112_n_0\,
O => \vgaRed_reg[0]_i_47_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_48\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_113_n_0\,
I1 => \vgaRed_reg[0]_i_114_n_0\,
O => \vgaRed_reg[0]_i_48_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_49\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_115_n_0\,
I1 => \vgaRed_reg[0]_i_116_n_0\,
O => \vgaRed_reg[0]_i_49_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_5\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_15_n_0\,
I1 => \vgaRed[0]_i_16_n_0\,
O => \vgaRed_reg[0]_i_5_n_0\,
S => \char[6]_i_1_n_0\
);
\vgaRed_reg[0]_i_52\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_117_n_0\,
I1 => \vgaRed_reg[0]_i_118_n_0\,
O => \vgaRed_reg[0]_i_52_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_53\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_119_n_0\,
I1 => \vgaRed_reg[0]_i_120_n_0\,
O => \vgaRed_reg[0]_i_53_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_55\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_121_n_0\,
I1 => \vgaRed_reg[0]_i_122_n_0\,
O => \vgaRed_reg[0]_i_55_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_56\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_123_n_0\,
I1 => \vgaRed_reg[0]_i_124_n_0\,
O => \vgaRed_reg[0]_i_56_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_57\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_125_n_0\,
I1 => \vgaRed_reg[0]_i_126_n_0\,
O => \vgaRed_reg[0]_i_57_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_58\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_127_n_0\,
I1 => \vgaRed_reg[0]_i_128_n_0\,
O => \vgaRed_reg[0]_i_58_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_59\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_129_n_0\,
I1 => \vgaRed_reg[0]_i_130_n_0\,
O => \vgaRed_reg[0]_i_59_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_60\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_131_n_0\,
I1 => \vgaRed_reg[0]_i_132_n_0\,
O => \vgaRed_reg[0]_i_60_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_61\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_133_n_0\,
I1 => \vgaRed_reg[0]_i_134_n_0\,
O => \vgaRed_reg[0]_i_61_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_63\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_135_n_0\,
I1 => \vgaRed_reg[0]_i_136_n_0\,
O => \vgaRed_reg[0]_i_63_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_64\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_137_n_0\,
I1 => \vgaRed_reg[0]_i_138_n_0\,
O => \vgaRed_reg[0]_i_64_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_65\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_139_n_0\,
I1 => \vgaRed_reg[0]_i_140_n_0\,
O => \vgaRed_reg[0]_i_65_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_66\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_141_n_0\,
I1 => \vgaRed_reg[0]_i_142_n_0\,
O => \vgaRed_reg[0]_i_66_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_67\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_143_n_0\,
I1 => \vgaRed_reg[0]_i_144_n_0\,
O => \vgaRed_reg[0]_i_67_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_68\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_145_n_0\,
I1 => \vgaRed_reg[0]_i_146_n_0\,
O => \vgaRed_reg[0]_i_68_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_69\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_147_n_0\,
I1 => \vgaRed_reg[0]_i_148_n_0\,
O => \vgaRed_reg[0]_i_69_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_70\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_149_n_0\,
I1 => \vgaRed_reg[0]_i_150_n_0\,
O => \vgaRed_reg[0]_i_70_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_71\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_151_n_0\,
I1 => \vgaRed_reg[0]_i_152_n_0\,
O => \vgaRed_reg[0]_i_71_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_72\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_153_n_0\,
I1 => \vgaRed_reg[0]_i_154_n_0\,
O => \vgaRed_reg[0]_i_72_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_73\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_155_n_0\,
I1 => \vgaRed_reg[0]_i_156_n_0\,
O => \vgaRed_reg[0]_i_73_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_76\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_157_n_0\,
I1 => \vgaRed_reg[0]_i_158_n_0\,
O => \vgaRed_reg[0]_i_76_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_77\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_159_n_0\,
I1 => \vgaRed_reg[0]_i_160_n_0\,
O => \vgaRed_reg[0]_i_77_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_79\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_161_n_0\,
I1 => \vgaRed_reg[0]_i_162_n_0\,
O => \vgaRed_reg[0]_i_79_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_8\: unisim.vcomponents.MUXF7
port map (
I0 => \vgaRed[0]_i_21_n_0\,
I1 => \vgaRed[0]_i_22_n_0\,
O => \vgaRed_reg[0]_i_8_n_0\,
S => \char[6]_i_1_n_0\
);
\vgaRed_reg[0]_i_80\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_163_n_0\,
I1 => \vgaRed_reg[0]_i_164_n_0\,
O => \vgaRed_reg[0]_i_80_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_81\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_165_n_0\,
I1 => \vgaRed_reg[0]_i_166_n_0\,
O => \vgaRed_reg[0]_i_81_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_82\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_167_n_0\,
I1 => \vgaRed_reg[0]_i_168_n_0\,
O => \vgaRed_reg[0]_i_82_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_83\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_169_n_0\,
I1 => \vgaRed_reg[0]_i_170_n_0\,
O => \vgaRed_reg[0]_i_83_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_84\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_171_n_0\,
I1 => \vgaRed_reg[0]_i_172_n_0\,
O => \vgaRed_reg[0]_i_84_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_85\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_173_n_0\,
I1 => \vgaRed_reg[0]_i_174_n_0\,
O => \vgaRed_reg[0]_i_85_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_87\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_175_n_0\,
I1 => \vgaRed_reg[0]_i_176_n_0\,
O => \vgaRed_reg[0]_i_87_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_88\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_177_n_0\,
I1 => \vgaRed_reg[0]_i_178_n_0\,
O => \vgaRed_reg[0]_i_88_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_89\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_179_n_0\,
I1 => \vgaRed_reg[0]_i_180_n_0\,
O => \vgaRed_reg[0]_i_89_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_90\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_181_n_0\,
I1 => \vgaRed_reg[0]_i_182_n_0\,
O => \vgaRed_reg[0]_i_90_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_91\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_183_n_0\,
I1 => \vgaRed_reg[0]_i_184_n_0\,
O => \vgaRed_reg[0]_i_91_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_92\: unisim.vcomponents.MUXF8
port map (
I0 => \vgaRed_reg[0]_i_185_n_0\,
I1 => \vgaRed_reg[0]_i_186_n_0\,
O => \vgaRed_reg[0]_i_92_n_0\,
S => \char[3]_i_1_n_0\
);
\vgaRed_reg[0]_i_93\: unisim.vcomponents.MUXF7
port map (
I0 => g12_b6_n_0,
I1 => g13_b6_n_0,
O => \vgaRed_reg[0]_i_93_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_94\: unisim.vcomponents.MUXF7
port map (
I0 => g14_b6_n_0,
I1 => g15_b6_n_0,
O => \vgaRed_reg[0]_i_94_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_95\: unisim.vcomponents.MUXF7
port map (
I0 => g4_b6_n_0,
I1 => g5_b6_n_0,
O => \vgaRed_reg[0]_i_95_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_96\: unisim.vcomponents.MUXF7
port map (
I0 => g6_b6_n_0,
I1 => g7_b6_n_0,
O => \vgaRed_reg[0]_i_96_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_97\: unisim.vcomponents.MUXF7
port map (
I0 => g0_b6_n_0,
I1 => g1_b6_n_0,
O => \vgaRed_reg[0]_i_97_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_98\: unisim.vcomponents.MUXF7
port map (
I0 => g2_b6_n_0,
I1 => g3_b6_n_0,
O => \vgaRed_reg[0]_i_98_n_0\,
S => \char[2]_i_1_n_0\
);
\vgaRed_reg[0]_i_99\: unisim.vcomponents.MUXF7
port map (
I0 => g28_b6_n_0,
I1 => g29_b6_n_0,
O => \vgaRed_reg[0]_i_99_n_0\,
S => \char[2]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ps2_keyboard is
port (
ps2_code_new : out STD_LOGIC;
break_reg : out STD_LOGIC;
shift_l_reg : out STD_LOGIC;
shift_r_reg : out STD_LOGIC;
e0_code_reg : out STD_LOGIC;
control_r_reg : out STD_LOGIC;
control_l_reg : out STD_LOGIC;
caps_lock_reg : out STD_LOGIC;
\ascii_reg[7]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\ascii_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
PS2Clk_IBUF : in STD_LOGIC;
clk_BUFG : in STD_LOGIC;
PS2Data_IBUF : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
break : in STD_LOGIC;
shift_l : in STD_LOGIC;
shift_r : in STD_LOGIC;
e0_code : in STD_LOGIC;
control_r_reg_0 : in STD_LOGIC;
control_l_reg_0 : in STD_LOGIC;
caps_lock_reg_0 : in STD_LOGIC;
\ascii_reg[7]_0\ : in STD_LOGIC;
prev_ps2_code_new : in STD_LOGIC
);
end ps2_keyboard;
architecture STRUCTURE of ps2_keyboard is
signal \ascii[0]_i_10_n_0\ : STD_LOGIC;
signal \ascii[0]_i_11_n_0\ : STD_LOGIC;
signal \ascii[0]_i_2_n_0\ : STD_LOGIC;
signal \ascii[0]_i_3_n_0\ : STD_LOGIC;
signal \ascii[0]_i_4_n_0\ : STD_LOGIC;
signal \ascii[0]_i_5_n_0\ : STD_LOGIC;
signal \ascii[0]_i_6_n_0\ : STD_LOGIC;
signal \ascii[0]_i_8_n_0\ : STD_LOGIC;
signal \ascii[0]_i_9_n_0\ : STD_LOGIC;
signal \ascii[1]_i_2_n_0\ : STD_LOGIC;
signal \ascii[1]_i_3_n_0\ : STD_LOGIC;
signal \ascii[1]_i_4_n_0\ : STD_LOGIC;
signal \ascii[1]_i_5_n_0\ : STD_LOGIC;
signal \ascii[1]_i_6_n_0\ : STD_LOGIC;
signal \ascii[1]_i_7_n_0\ : STD_LOGIC;
signal \ascii[1]_i_8_n_0\ : STD_LOGIC;
signal \ascii[1]_i_9_n_0\ : STD_LOGIC;
signal \ascii[2]_i_10_n_0\ : STD_LOGIC;
signal \ascii[2]_i_11_n_0\ : STD_LOGIC;
signal \ascii[2]_i_12_n_0\ : STD_LOGIC;
signal \ascii[2]_i_3_n_0\ : STD_LOGIC;
signal \ascii[2]_i_4_n_0\ : STD_LOGIC;
signal \ascii[2]_i_5_n_0\ : STD_LOGIC;
signal \ascii[2]_i_6_n_0\ : STD_LOGIC;
signal \ascii[2]_i_7_n_0\ : STD_LOGIC;
signal \ascii[2]_i_9_n_0\ : STD_LOGIC;
signal \ascii[3]_i_10_n_0\ : STD_LOGIC;
signal \ascii[3]_i_3_n_0\ : STD_LOGIC;
signal \ascii[3]_i_4_n_0\ : STD_LOGIC;
signal \ascii[3]_i_5_n_0\ : STD_LOGIC;
signal \ascii[3]_i_6_n_0\ : STD_LOGIC;
signal \ascii[3]_i_7_n_0\ : STD_LOGIC;
signal \ascii[3]_i_8_n_0\ : STD_LOGIC;
signal \ascii[3]_i_9_n_0\ : STD_LOGIC;
signal \ascii[4]_i_10_n_0\ : STD_LOGIC;
signal \ascii[4]_i_2_n_0\ : STD_LOGIC;
signal \ascii[4]_i_3_n_0\ : STD_LOGIC;
signal \ascii[4]_i_4_n_0\ : STD_LOGIC;
signal \ascii[4]_i_5_n_0\ : STD_LOGIC;
signal \ascii[4]_i_7_n_0\ : STD_LOGIC;
signal \ascii[4]_i_8_n_0\ : STD_LOGIC;
signal \ascii[4]_i_9_n_0\ : STD_LOGIC;
signal \ascii[5]_i_10_n_0\ : STD_LOGIC;
signal \ascii[5]_i_11_n_0\ : STD_LOGIC;
signal \ascii[5]_i_12_n_0\ : STD_LOGIC;
signal \ascii[5]_i_13_n_0\ : STD_LOGIC;
signal \ascii[5]_i_14_n_0\ : STD_LOGIC;
signal \ascii[5]_i_15_n_0\ : STD_LOGIC;
signal \ascii[5]_i_16_n_0\ : STD_LOGIC;
signal \ascii[5]_i_17_n_0\ : STD_LOGIC;
signal \ascii[5]_i_2_n_0\ : STD_LOGIC;
signal \ascii[5]_i_3_n_0\ : STD_LOGIC;
signal \ascii[5]_i_4_n_0\ : STD_LOGIC;
signal \ascii[6]_i_10_n_0\ : STD_LOGIC;
signal \ascii[6]_i_11_n_0\ : STD_LOGIC;
signal \ascii[6]_i_12_n_0\ : STD_LOGIC;
signal \ascii[6]_i_13_n_0\ : STD_LOGIC;
signal \ascii[6]_i_14_n_0\ : STD_LOGIC;
signal \ascii[6]_i_15_n_0\ : STD_LOGIC;
signal \ascii[6]_i_16_n_0\ : STD_LOGIC;
signal \ascii[6]_i_17_n_0\ : STD_LOGIC;
signal \ascii[6]_i_3_n_0\ : STD_LOGIC;
signal \ascii[6]_i_4_n_0\ : STD_LOGIC;
signal \ascii[6]_i_5_n_0\ : STD_LOGIC;
signal \ascii[6]_i_6_n_0\ : STD_LOGIC;
signal \ascii[6]_i_7_n_0\ : STD_LOGIC;
signal \ascii[6]_i_8_n_0\ : STD_LOGIC;
signal \ascii[6]_i_9_n_0\ : STD_LOGIC;
signal \ascii_reg[0]_i_7_n_0\ : STD_LOGIC;
signal \ascii_reg[2]_i_2_n_0\ : STD_LOGIC;
signal \ascii_reg[2]_i_8_n_0\ : STD_LOGIC;
signal \ascii_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \ascii_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_5_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_6_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_7_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_8_n_0\ : STD_LOGIC;
signal \ascii_reg[5]_i_9_n_0\ : STD_LOGIC;
signal break_i_2_n_0 : STD_LOGIC;
signal caps_lock_i_2_n_0 : STD_LOGIC;
signal clear : STD_LOGIC;
signal control_l_i_2_n_0 : STD_LOGIC;
signal control_r_i_2_n_0 : STD_LOGIC;
signal control_r_i_3_n_0 : STD_LOGIC;
signal \count_idle[0]_i_2_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_4_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_5_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_6_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_7_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_8_n_0\ : STD_LOGIC;
signal \count_idle[0]_i_9_n_0\ : STD_LOGIC;
signal \count_idle[12]_i_2_n_0\ : STD_LOGIC;
signal \count_idle[4]_i_2_n_0\ : STD_LOGIC;
signal \count_idle[4]_i_3_n_0\ : STD_LOGIC;
signal \count_idle[4]_i_4_n_0\ : STD_LOGIC;
signal \count_idle[4]_i_5_n_0\ : STD_LOGIC;
signal \count_idle[8]_i_2_n_0\ : STD_LOGIC;
signal \count_idle[8]_i_3_n_0\ : STD_LOGIC;
signal \count_idle[8]_i_4_n_0\ : STD_LOGIC;
signal \count_idle[8]_i_5_n_0\ : STD_LOGIC;
signal count_idle_reg : STD_LOGIC_VECTOR ( 12 downto 0 );
signal \count_idle_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_1\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_2\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_3\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \count_idle_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \count_idle_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \count_idle_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \count_idle_reg[8]_i_1_n_7\ : STD_LOGIC;
signal e0_code_i_2_n_0 : STD_LOGIC;
signal ps2_clk_int : STD_LOGIC;
signal ps2_code : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^ps2_code_new\ : STD_LOGIC;
signal ps2_code_new0 : STD_LOGIC;
signal ps2_code_new_i_2_n_0 : STD_LOGIC;
signal ps2_code_new_i_3_n_0 : STD_LOGIC;
signal ps2_code_new_i_4_n_0 : STD_LOGIC;
signal ps2_code_new_i_5_n_0 : STD_LOGIC;
signal ps2_code_new_i_6_n_0 : STD_LOGIC;
signal ps2_code_new_i_7_n_0 : STD_LOGIC;
signal ps2_data_int : STD_LOGIC;
signal ps2_word : STD_LOGIC_VECTOR ( 10 downto 0 );
signal shift_l_i_2_n_0 : STD_LOGIC;
signal shift_r_i_2_n_0 : STD_LOGIC;
signal shift_r_i_3_n_0 : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ascii[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \ascii[0]_i_6\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \ascii[2]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \ascii[4]_i_5\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ascii[5]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ascii[5]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ascii[6]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \ascii[6]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ascii[6]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \ascii[6]_i_7\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of control_r_i_3 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of shift_r_i_3 : label is "soft_lutpair5";
begin
ps2_code_new <= \^ps2_code_new\;
\ascii[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[0]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[0]_i_3_n_0\,
O => \ascii_reg[6]\(0)
);
\ascii[0]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"DCFDFFDF01000888"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(4),
O => \ascii[0]_i_10_n_0\
);
\ascii[0]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDBDFDFFEEBD030C"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[0]_i_11_n_0\
);
\ascii[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CFC0C0CACACFCF"
)
port map (
I0 => ps2_code(2),
I1 => \ascii[0]_i_4_n_0\,
I2 => ps2_code(1),
I3 => ps2_code(6),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[0]_i_2_n_0\
);
\ascii[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[0]_i_5_n_0\,
I2 => shift_r,
I3 => \ascii[0]_i_6_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[0]_i_7_n_0\,
O => \ascii[0]_i_3_n_0\
);
\ascii[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6515"
)
port map (
I0 => ps2_code(5),
I1 => ps2_code(0),
I2 => ps2_code(3),
I3 => ps2_code(4),
O => \ascii[0]_i_4_n_0\
);
\ascii[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0CFCFEFE0C0C0"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(4),
I2 => ps2_code(7),
I3 => \ascii[0]_i_8_n_0\,
I4 => ps2_code(2),
I5 => \ascii[0]_i_9_n_0\,
O => \ascii[0]_i_5_n_0\
);
\ascii[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(2),
I2 => ps2_code(4),
O => \ascii[0]_i_6_n_0\
);
\ascii[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"EDBDFDFFEEB90344"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[0]_i_8_n_0\
);
\ascii[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"DCFDFFD701000888"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(4),
O => \ascii[0]_i_9_n_0\
);
\ascii[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[1]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[1]_i_3_n_0\,
O => \ascii_reg[6]\(1)
);
\ascii[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"6632FFFF66320000"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(0),
I2 => ps2_code(4),
I3 => ps2_code(3),
I4 => ps2_code(2),
I5 => \ascii[1]_i_4_n_0\,
O => \ascii[1]_i_2_n_0\
);
\ascii[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => shift_l,
I1 => \ascii[1]_i_5_n_0\,
I2 => shift_r,
I3 => \ascii[1]_i_6_n_0\,
O => \ascii[1]_i_3_n_0\
);
\ascii[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55559DCDFFFFFFFF"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(3),
I2 => ps2_code(5),
I3 => ps2_code(4),
I4 => ps2_code(6),
I5 => ps2_code(1),
O => \ascii[1]_i_4_n_0\
);
\ascii[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
I2 => ps2_code(7),
I3 => \ascii[1]_i_7_n_0\,
I4 => ps2_code(2),
I5 => \ascii[1]_i_8_n_0\,
O => \ascii[1]_i_5_n_0\
);
\ascii[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
I2 => ps2_code(7),
I3 => \ascii[1]_i_9_n_0\,
I4 => ps2_code(2),
I5 => \ascii[1]_i_8_n_0\,
O => \ascii[1]_i_6_n_0\
);
\ascii[1]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"1120100EEEFD0024"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[1]_i_7_n_0\
);
\ascii[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"20222248DFFF1008"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[1]_i_8_n_0\
);
\ascii[1]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"11021004EAFD0024"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[1]_i_9_n_0\
);
\ascii[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii_reg[2]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[2]_i_3_n_0\,
O => \ascii_reg[6]\(2)
);
\ascii[2]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8E8ADEDDF777"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(3),
O => \ascii[2]_i_10_n_0\
);
\ascii[2]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAA8E8ADEDDF7F7"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(5),
I5 => ps2_code(3),
O => \ascii[2]_i_11_n_0\
);
\ascii[2]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"1504001010303814"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(3),
I4 => ps2_code(4),
I5 => ps2_code(0),
O => \ascii[2]_i_12_n_0\
);
\ascii[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[2]_i_6_n_0\,
I2 => shift_r,
I3 => \ascii[2]_i_7_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[2]_i_8_n_0\,
O => \ascii[2]_i_3_n_0\
);
\ascii[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FAFF0C0EF00CFC0"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(3),
I2 => ps2_code(1),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(0),
O => \ascii[2]_i_4_n_0\
);
\ascii[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"5FF0AAFA4EF0FFFF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[2]_i_5_n_0\
);
\ascii[2]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F00DFDF0F00D0D0"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(7),
I3 => \ascii[2]_i_9_n_0\,
I4 => ps2_code(2),
I5 => \ascii[2]_i_10_n_0\,
O => \ascii[2]_i_6_n_0\
);
\ascii[2]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"0D"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(2),
O => \ascii[2]_i_7_n_0\
);
\ascii[2]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"1500001010303A14"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(3),
I4 => ps2_code(4),
I5 => ps2_code(0),
O => \ascii[2]_i_9_n_0\
);
\ascii[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii_reg[3]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[3]_i_3_n_0\,
O => \ascii_reg[6]\(3)
);
\ascii[3]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEECFECDEBCDEBCF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[3]_i_10_n_0\
);
\ascii[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => shift_l,
I1 => \ascii[3]_i_6_n_0\,
I2 => shift_r,
I3 => \ascii[3]_i_7_n_0\,
O => \ascii[3]_i_3_n_0\
);
\ascii[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFE2333F"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(5),
I2 => ps2_code(0),
I3 => ps2_code(3),
I4 => ps2_code(4),
O => \ascii[3]_i_4_n_0\
);
\ascii[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF444444F4F444F4"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(6),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(5),
O => \ascii[3]_i_5_n_0\
);
\ascii[3]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0DFDFFFF0D0D0"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(6),
I2 => ps2_code(7),
I3 => \ascii[3]_i_8_n_0\,
I4 => ps2_code(2),
I5 => \ascii[3]_i_9_n_0\,
O => \ascii[3]_i_6_n_0\
);
\ascii[3]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0DFDFFFF0D0D0"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(6),
I2 => ps2_code(7),
I3 => \ascii[3]_i_10_n_0\,
I4 => ps2_code(2),
I5 => \ascii[3]_i_9_n_0\,
O => \ascii[3]_i_7_n_0\
);
\ascii[3]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEECFEEDEBCFEFCF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(4),
O => \ascii[3]_i_8_n_0\
);
\ascii[3]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFDFFB313D333"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(0),
I2 => ps2_code(5),
I3 => ps2_code(4),
I4 => ps2_code(3),
I5 => ps2_code(6),
O => \ascii[3]_i_9_n_0\
);
\ascii[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[4]_i_2_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[4]_i_3_n_0\,
O => \ascii_reg[6]\(4)
);
\ascii[4]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"15321434FFEF1428"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_10_n_0\
);
\ascii[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCCC3FFCCCC8CB8"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(2),
I2 => ps2_code(5),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(3),
O => \ascii[4]_i_2_n_0\
);
\ascii[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[4]_i_4_n_0\,
I2 => shift_r,
I3 => \ascii[4]_i_5_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[4]_i_6_n_0\,
O => \ascii[4]_i_3_n_0\
);
\ascii[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
I2 => ps2_code(7),
I3 => \ascii[4]_i_7_n_0\,
I4 => ps2_code(2),
I5 => \ascii[4]_i_8_n_0\,
O => \ascii[4]_i_4_n_0\
);
\ascii[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(3),
O => \ascii[4]_i_5_n_0\
);
\ascii[4]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0510141EFBED0000"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_7_n_0\
);
\ascii[4]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A20248CDF70240"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_8_n_0\
);
\ascii[4]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A20200CDF70200"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(5),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[4]_i_9_n_0\
);
\ascii[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[6]_i_4_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[5]_i_2_n_0\,
O => \ascii_reg[6]\(5)
);
\ascii[5]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF8F4C8080"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(5),
O => \ascii[5]_i_10_n_0\
);
\ascii[5]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"111131335544166C"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[5]_i_11_n_0\
);
\ascii[5]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5F5F0F590201080"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(4),
I2 => ps2_code(6),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_12_n_0\
);
\ascii[5]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"1202001240064648"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(4),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_13_n_0\
);
\ascii[5]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF0F4C8080"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(1),
I2 => ps2_code(4),
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(5),
O => \ascii[5]_i_14_n_0\
);
\ascii[5]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"11113333154432EC"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[5]_i_15_n_0\
);
\ascii[5]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"F5F5F0F510201080"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(4),
I2 => ps2_code(6),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_16_n_0\
);
\ascii[5]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"12020212020E4248"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(4),
I4 => ps2_code(3),
I5 => ps2_code(5),
O => \ascii[5]_i_17_n_0\
);
\ascii[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDC8CDCDCDC8C8C8"
)
port map (
I0 => shift_l,
I1 => \ascii[5]_i_3_n_0\,
I2 => shift_r,
I3 => \ascii[5]_i_4_n_0\,
I4 => ps2_code(7),
I5 => \ascii_reg[5]_i_5_n_0\,
O => \ascii[5]_i_2_n_0\
);
\ascii[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => ps2_code(5),
I1 => ps2_code(2),
I2 => ps2_code(7),
I3 => \ascii_reg[5]_i_6_n_0\,
I4 => caps_lock_reg_0,
I5 => \ascii_reg[5]_i_7_n_0\,
O => \ascii[5]_i_3_n_0\
);
\ascii[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ps2_code(5),
I1 => ps2_code(2),
O => \ascii[5]_i_4_n_0\
);
\ascii[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \ascii[6]_i_3_n_0\,
I1 => Q(0),
O => E(0)
);
\ascii[6]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"00B030300000C0C0"
)
port map (
I0 => e0_code,
I1 => ps2_code(6),
I2 => ps2_code(0),
I3 => ps2_code(3),
I4 => ps2_code(4),
I5 => ps2_code(5),
O => \ascii[6]_i_10_n_0\
);
\ascii[6]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"3333F4CC"
)
port map (
I0 => ps2_code(0),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(5),
O => \ascii[6]_i_11_n_0\
);
\ascii[6]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"11113B3B555436EC"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(3),
I3 => ps2_code(4),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[6]_i_12_n_0\
);
\ascii[6]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C040404C8C8F0C0"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(1),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(3),
I5 => ps2_code(6),
O => \ascii[6]_i_13_n_0\
);
\ascii[6]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0513141811340014"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[6]_i_14_n_0\
);
\ascii[6]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0513141A11340014"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[6]_i_15_n_0\
);
\ascii[6]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFCFCC8400840"
)
port map (
I0 => ps2_code(4),
I1 => ps2_code(1),
I2 => ps2_code(6),
I3 => ps2_code(3),
I4 => ps2_code(0),
I5 => ps2_code(5),
O => \ascii[6]_i_16_n_0\
);
\ascii[6]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0511141211140014"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(6),
I2 => ps2_code(5),
I3 => ps2_code(0),
I4 => ps2_code(4),
I5 => ps2_code(3),
O => \ascii[6]_i_17_n_0\
);
\ascii[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => control_r_reg_0,
I1 => \ascii[6]_i_4_n_0\,
I2 => control_l_reg_0,
I3 => \ascii[6]_i_5_n_0\,
O => \ascii_reg[6]\(6)
);
\ascii[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0E20000"
)
port map (
I0 => \ascii[6]_i_6_n_0\,
I1 => control_l_reg_0,
I2 => \ascii[6]_i_7_n_0\,
I3 => control_r_reg_0,
I4 => Q(1),
O => \ascii[6]_i_3_n_0\
);
\ascii[6]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(3),
I2 => ps2_code(0),
I3 => ps2_code(2),
O => \ascii[6]_i_4_n_0\
);
\ascii[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"CDC8"
)
port map (
I0 => shift_l,
I1 => \ascii[6]_i_8_n_0\,
I2 => shift_r,
I3 => \ascii[6]_i_9_n_0\,
O => \ascii[6]_i_5_n_0\
);
\ascii[6]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFE200E2"
)
port map (
I0 => \ascii[6]_i_10_n_0\,
I1 => ps2_code(1),
I2 => \ascii[6]_i_11_n_0\,
I3 => ps2_code(2),
I4 => \ascii[6]_i_12_n_0\,
I5 => ps2_code(7),
O => \ascii[6]_i_6_n_0\
);
\ascii[6]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => \ascii[6]_i_13_n_0\,
I1 => ps2_code(2),
I2 => \ascii[6]_i_14_n_0\,
I3 => ps2_code(7),
O => \ascii[6]_i_7_n_0\
);
\ascii[6]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F008F8F0F008080"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(5),
I2 => ps2_code(7),
I3 => \ascii[6]_i_15_n_0\,
I4 => ps2_code(2),
I5 => \ascii[6]_i_16_n_0\,
O => \ascii[6]_i_8_n_0\
);
\ascii[6]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F008F8F0F008080"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(5),
I2 => ps2_code(7),
I3 => \ascii[6]_i_17_n_0\,
I4 => ps2_code(2),
I5 => \ascii[6]_i_16_n_0\,
O => \ascii[6]_i_9_n_0\
);
\ascii[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0FFFFF0D0F0D00"
)
port map (
I0 => ps2_code(7),
I1 => \state[1]_i_2_n_0\,
I2 => Q(1),
I3 => Q(0),
I4 => \ascii[6]_i_3_n_0\,
I5 => \ascii_reg[7]_0\,
O => \ascii_reg[7]\
);
\ascii_reg[0]_i_7\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[0]_i_10_n_0\,
I1 => \ascii[0]_i_11_n_0\,
O => \ascii_reg[0]_i_7_n_0\,
S => ps2_code(2)
);
\ascii_reg[2]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[2]_i_4_n_0\,
I1 => \ascii[2]_i_5_n_0\,
O => \ascii_reg[2]_i_2_n_0\,
S => ps2_code(2)
);
\ascii_reg[2]_i_8\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[2]_i_11_n_0\,
I1 => \ascii[2]_i_12_n_0\,
O => \ascii_reg[2]_i_8_n_0\,
S => ps2_code(2)
);
\ascii_reg[3]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[3]_i_4_n_0\,
I1 => \ascii[3]_i_5_n_0\,
O => \ascii_reg[3]_i_2_n_0\,
S => ps2_code(2)
);
\ascii_reg[4]_i_6\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[4]_i_9_n_0\,
I1 => \ascii[4]_i_10_n_0\,
O => \ascii_reg[4]_i_6_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_5\: unisim.vcomponents.MUXF8
port map (
I0 => \ascii_reg[5]_i_8_n_0\,
I1 => \ascii_reg[5]_i_9_n_0\,
O => \ascii_reg[5]_i_5_n_0\,
S => caps_lock_reg_0
);
\ascii_reg[5]_i_6\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_10_n_0\,
I1 => \ascii[5]_i_11_n_0\,
O => \ascii_reg[5]_i_6_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_7\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_12_n_0\,
I1 => \ascii[5]_i_13_n_0\,
O => \ascii_reg[5]_i_7_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_8\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_14_n_0\,
I1 => \ascii[5]_i_15_n_0\,
O => \ascii_reg[5]_i_8_n_0\,
S => ps2_code(2)
);
\ascii_reg[5]_i_9\: unisim.vcomponents.MUXF7
port map (
I0 => \ascii[5]_i_16_n_0\,
I1 => \ascii[5]_i_17_n_0\,
O => \ascii_reg[5]_i_9_n_0\,
S => ps2_code(2)
);
break_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF00000800"
)
port map (
I0 => ps2_code(7),
I1 => break_i_2_n_0,
I2 => ps2_code(2),
I3 => Q(0),
I4 => Q(1),
I5 => break,
O => break_reg
);
break_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000200000"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(0),
I2 => ps2_code(4),
I3 => ps2_code(3),
I4 => ps2_code(5),
I5 => ps2_code(1),
O => break_i_2_n_0
);
caps_lock_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00100000"
)
port map (
I0 => Q(0),
I1 => break,
I2 => caps_lock_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(1),
I5 => caps_lock_reg_0,
O => caps_lock_reg
);
caps_lock_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000010000"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => shift_r_i_3_n_0,
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => caps_lock_i_2_n_0
);
control_l_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => control_l_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => control_l_reg_0,
O => control_l_reg
);
control_l_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => ps2_code(1),
I1 => e0_code,
I2 => control_r_i_3_n_0,
I3 => ps2_code(5),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => control_l_i_2_n_0
);
control_r_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => control_r_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => control_r_reg_0,
O => control_r_reg
);
control_r_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004000000000"
)
port map (
I0 => ps2_code(1),
I1 => e0_code,
I2 => control_r_i_3_n_0,
I3 => ps2_code(5),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => control_r_i_2_n_0
);
control_r_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(4),
I2 => ps2_code(0),
O => control_r_i_3_n_0
);
\count_idle[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ps2_clk_int,
O => clear
);
\count_idle[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => count_idle_reg(10),
I1 => \count_idle[0]_i_4_n_0\,
I2 => count_idle_reg(12),
O => \count_idle[0]_i_2_n_0\
);
\count_idle[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFFFFFF"
)
port map (
I0 => count_idle_reg(7),
I1 => count_idle_reg(5),
I2 => \count_idle[0]_i_9_n_0\,
I3 => count_idle_reg(4),
I4 => count_idle_reg(9),
I5 => count_idle_reg(8),
O => \count_idle[0]_i_4_n_0\
);
\count_idle[0]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(3),
O => \count_idle[0]_i_5_n_0\
);
\count_idle[0]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(2),
O => \count_idle[0]_i_6_n_0\
);
\count_idle[0]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(1),
O => \count_idle[0]_i_7_n_0\
);
\count_idle[0]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => count_idle_reg(0),
O => \count_idle[0]_i_8_n_0\
);
\count_idle[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFDFFFFFFFF"
)
port map (
I0 => count_idle_reg(0),
I1 => count_idle_reg(2),
I2 => count_idle_reg(6),
I3 => count_idle_reg(11),
I4 => count_idle_reg(3),
I5 => count_idle_reg(1),
O => \count_idle[0]_i_9_n_0\
);
\count_idle[12]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(12),
O => \count_idle[12]_i_2_n_0\
);
\count_idle[4]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(7),
O => \count_idle[4]_i_2_n_0\
);
\count_idle[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(6),
O => \count_idle[4]_i_3_n_0\
);
\count_idle[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(5),
O => \count_idle[4]_i_4_n_0\
);
\count_idle[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(4),
O => \count_idle[4]_i_5_n_0\
);
\count_idle[8]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(11),
O => \count_idle[8]_i_2_n_0\
);
\count_idle[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(10),
O => \count_idle[8]_i_3_n_0\
);
\count_idle[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(9),
O => \count_idle[8]_i_4_n_0\
);
\count_idle[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => count_idle_reg(8),
O => \count_idle[8]_i_5_n_0\
);
\count_idle_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_7\,
Q => count_idle_reg(0),
R => clear
);
\count_idle_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \count_idle_reg[0]_i_3_n_0\,
CO(2) => \count_idle_reg[0]_i_3_n_1\,
CO(1) => \count_idle_reg[0]_i_3_n_2\,
CO(0) => \count_idle_reg[0]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \count_idle_reg[0]_i_3_n_4\,
O(2) => \count_idle_reg[0]_i_3_n_5\,
O(1) => \count_idle_reg[0]_i_3_n_6\,
O(0) => \count_idle_reg[0]_i_3_n_7\,
S(3) => \count_idle[0]_i_5_n_0\,
S(2) => \count_idle[0]_i_6_n_0\,
S(1) => \count_idle[0]_i_7_n_0\,
S(0) => \count_idle[0]_i_8_n_0\
);
\count_idle_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_5\,
Q => count_idle_reg(10),
R => clear
);
\count_idle_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_4\,
Q => count_idle_reg(11),
R => clear
);
\count_idle_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[12]_i_1_n_7\,
Q => count_idle_reg(12),
R => clear
);
\count_idle_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_idle_reg[8]_i_1_n_0\,
CO(3 downto 0) => \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => \count_idle_reg[12]_i_1_n_7\,
S(3 downto 1) => B"000",
S(0) => \count_idle[12]_i_2_n_0\
);
\count_idle_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_6\,
Q => count_idle_reg(1),
R => clear
);
\count_idle_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_5\,
Q => count_idle_reg(2),
R => clear
);
\count_idle_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[0]_i_3_n_4\,
Q => count_idle_reg(3),
R => clear
);
\count_idle_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_7\,
Q => count_idle_reg(4),
R => clear
);
\count_idle_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_idle_reg[0]_i_3_n_0\,
CO(3) => \count_idle_reg[4]_i_1_n_0\,
CO(2) => \count_idle_reg[4]_i_1_n_1\,
CO(1) => \count_idle_reg[4]_i_1_n_2\,
CO(0) => \count_idle_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_idle_reg[4]_i_1_n_4\,
O(2) => \count_idle_reg[4]_i_1_n_5\,
O(1) => \count_idle_reg[4]_i_1_n_6\,
O(0) => \count_idle_reg[4]_i_1_n_7\,
S(3) => \count_idle[4]_i_2_n_0\,
S(2) => \count_idle[4]_i_3_n_0\,
S(1) => \count_idle[4]_i_4_n_0\,
S(0) => \count_idle[4]_i_5_n_0\
);
\count_idle_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_6\,
Q => count_idle_reg(5),
R => clear
);
\count_idle_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_5\,
Q => count_idle_reg(6),
R => clear
);
\count_idle_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[4]_i_1_n_4\,
Q => count_idle_reg(7),
R => clear
);
\count_idle_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_7\,
Q => count_idle_reg(8),
R => clear
);
\count_idle_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \count_idle_reg[4]_i_1_n_0\,
CO(3) => \count_idle_reg[8]_i_1_n_0\,
CO(2) => \count_idle_reg[8]_i_1_n_1\,
CO(1) => \count_idle_reg[8]_i_1_n_2\,
CO(0) => \count_idle_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \count_idle_reg[8]_i_1_n_4\,
O(2) => \count_idle_reg[8]_i_1_n_5\,
O(1) => \count_idle_reg[8]_i_1_n_6\,
O(0) => \count_idle_reg[8]_i_1_n_7\,
S(3) => \count_idle[8]_i_2_n_0\,
S(2) => \count_idle[8]_i_3_n_0\,
S(1) => \count_idle[8]_i_4_n_0\,
S(0) => \count_idle[8]_i_5_n_0\
);
\count_idle_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \count_idle[0]_i_2_n_0\,
D => \count_idle_reg[8]_i_1_n_6\,
Q => count_idle_reg(9),
R => clear
);
e0_code_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFF00000800"
)
port map (
I0 => ps2_code(7),
I1 => e0_code_i_2_n_0,
I2 => ps2_code(2),
I3 => Q(0),
I4 => Q(1),
I5 => e0_code,
O => e0_code_reg
);
e0_code_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => ps2_code(6),
I1 => ps2_code(0),
I2 => ps2_code(4),
I3 => ps2_code(3),
I4 => ps2_code(5),
I5 => ps2_code(1),
O => e0_code_i_2_n_0
);
ps2_clk_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => PS2Clk_IBUF,
Q => ps2_clk_int,
R => '0'
);
ps2_code_new_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => count_idle_reg(10),
I1 => ps2_code_new_i_2_n_0,
I2 => count_idle_reg(8),
I3 => count_idle_reg(12),
O => ps2_code_new0
);
ps2_code_new_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"4000000000000000"
)
port map (
I0 => count_idle_reg(9),
I1 => count_idle_reg(4),
I2 => ps2_code_new_i_3_n_0,
I3 => count_idle_reg(1),
I4 => count_idle_reg(5),
I5 => count_idle_reg(7),
O => ps2_code_new_i_2_n_0
);
ps2_code_new_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => count_idle_reg(3),
I1 => count_idle_reg(11),
I2 => ps2_code_new_i_4_n_0,
I3 => count_idle_reg(6),
I4 => count_idle_reg(2),
I5 => count_idle_reg(0),
O => ps2_code_new_i_3_n_0
);
ps2_code_new_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FF96FF6969009600"
)
port map (
I0 => ps2_word(9),
I1 => ps2_word(7),
I2 => ps2_word(8),
I3 => ps2_code_new_i_5_n_0,
I4 => ps2_word(5),
I5 => ps2_code_new_i_6_n_0,
O => ps2_code_new_i_4_n_0
);
ps2_code_new_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"6996000096690000"
)
port map (
I0 => ps2_word(6),
I1 => ps2_word(3),
I2 => ps2_word(4),
I3 => ps2_word(1),
I4 => ps2_code_new_i_7_n_0,
I5 => ps2_word(2),
O => ps2_code_new_i_5_n_0
);
ps2_code_new_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9669000069960000"
)
port map (
I0 => ps2_word(6),
I1 => ps2_word(3),
I2 => ps2_word(4),
I3 => ps2_word(1),
I4 => ps2_code_new_i_7_n_0,
I5 => ps2_word(2),
O => ps2_code_new_i_6_n_0
);
ps2_code_new_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => ps2_word(10),
I1 => ps2_word(0),
O => ps2_code_new_i_7_n_0
);
ps2_code_new_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_code_new0,
Q => \^ps2_code_new\,
R => '0'
);
\ps2_code_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(1),
Q => ps2_code(0),
R => '0'
);
\ps2_code_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(2),
Q => ps2_code(1),
R => '0'
);
\ps2_code_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(3),
Q => ps2_code(2),
R => '0'
);
\ps2_code_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(4),
Q => ps2_code(3),
R => '0'
);
\ps2_code_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(5),
Q => ps2_code(4),
R => '0'
);
\ps2_code_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(6),
Q => ps2_code(5),
R => '0'
);
\ps2_code_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(7),
Q => ps2_code(6),
R => '0'
);
\ps2_code_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ps2_code_new0,
D => ps2_word(8),
Q => ps2_code(7),
R => '0'
);
ps2_data_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => PS2Data_IBUF,
Q => ps2_data_int,
R => '0'
);
\ps2_word_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(1),
Q => ps2_word(0),
R => '0'
);
\ps2_word_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_data_int,
Q => ps2_word(10),
R => '0'
);
\ps2_word_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(2),
Q => ps2_word(1),
R => '0'
);
\ps2_word_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(3),
Q => ps2_word(2),
R => '0'
);
\ps2_word_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(4),
Q => ps2_word(3),
R => '0'
);
\ps2_word_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(5),
Q => ps2_word(4),
R => '0'
);
\ps2_word_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(6),
Q => ps2_word(5),
R => '0'
);
\ps2_word_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(7),
Q => ps2_word(6),
R => '0'
);
\ps2_word_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(8),
Q => ps2_word(7),
R => '0'
);
\ps2_word_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(9),
Q => ps2_word(8),
R => '0'
);
\ps2_word_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '1'
)
port map (
C => ps2_clk_int,
CE => '1',
D => ps2_word(10),
Q => ps2_word(9),
R => '0'
);
shift_l_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => shift_l_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => shift_l,
O => shift_l_reg
);
shift_l_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000020"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => \ascii[4]_i_5_n_0\,
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => shift_l_i_2_n_0
);
shift_r_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF7F00000040"
)
port map (
I0 => break,
I1 => Q(1),
I2 => shift_r_i_2_n_0,
I3 => ps2_code(7),
I4 => Q(0),
I5 => shift_r,
O => shift_r_reg
);
shift_r_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000000"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => shift_r_i_3_n_0,
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => shift_r_i_2_n_0
);
shift_r_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => ps2_code(3),
I1 => ps2_code(4),
O => shift_r_i_3_n_0
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000004F4"
)
port map (
I0 => prev_ps2_code_new,
I1 => \^ps2_code_new\,
I2 => Q(1),
I3 => break,
I4 => Q(0),
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00D00FD0"
)
port map (
I0 => ps2_code(7),
I1 => \state[1]_i_2_n_0\,
I2 => Q(0),
I3 => Q(1),
I4 => break,
O => D(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFBFFFF"
)
port map (
I0 => ps2_code(1),
I1 => ps2_code(5),
I2 => ps2_code(3),
I3 => ps2_code(0),
I4 => ps2_code(6),
I5 => ps2_code(2),
O => \state[1]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider is
port (
clkIn : in STD_LOGIC;
clk108M : out STD_LOGIC;
clk10M : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ClockDivider;
architecture STRUCTURE of ClockDivider is
begin
inst: entity work.ClockDivider_ClockDivider_clk_wiz
port map (
clk108M => clk108M,
clk10M => clk10M,
clkIn => clkIn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_width is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end FrameBuffer_blk_mem_gen_prim_width;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
port (
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOBDO(7 downto 0) => DOBDO(7 downto 0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ps2_keyboard_to_ascii is
port (
\next_s_reg[0]\ : out STD_LOGIC;
\fb_in_dat_reg[6]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
SR : out STD_LOGIC_VECTOR ( 1 downto 0 );
\fb_in_dat_reg[0]\ : out STD_LOGIC;
\fb_in_dat_reg[1]\ : out STD_LOGIC;
\fb_in_dat_reg[2]\ : out STD_LOGIC;
\fb_in_dat_reg[3]\ : out STD_LOGIC;
\fb_in_dat_reg[4]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\next_s_reg[1]\ : out STD_LOGIC;
PS2Clk_IBUF : in STD_LOGIC;
clk_BUFG : in STD_LOGIC;
PS2Data_IBUF : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\current_s_reg[0]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\counter_reg[0]\ : in STD_LOGIC;
\counter_reg[0]_0\ : in STD_LOGIC;
\counter_reg[0]_1\ : in STD_LOGIC;
\counter_reg[0]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\counter_reg[0]_3\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
\counter_reg[0]_4\ : in STD_LOGIC;
\counter_reg[0]_5\ : in STD_LOGIC;
\counter_reg[0]_6\ : in STD_LOGIC;
\counter_reg[0]_7\ : in STD_LOGIC
);
end ps2_keyboard_to_ascii;
architecture STRUCTURE of ps2_keyboard_to_ascii is
signal ascii_code : STD_LOGIC_VECTOR ( 6 downto 0 );
signal ascii_new : STD_LOGIC;
signal ascii_new_i_1_n_0 : STD_LOGIC;
signal ascii_new_i_2_n_0 : STD_LOGIC;
signal ascii_new_i_3_n_0 : STD_LOGIC;
signal ascii_new_i_4_n_0 : STD_LOGIC;
signal ascii_new_i_5_n_0 : STD_LOGIC;
signal ascii_new_i_6_n_0 : STD_LOGIC;
signal ascii_new_i_7_n_0 : STD_LOGIC;
signal ascii_new_i_8_n_0 : STD_LOGIC;
signal ascii_new_i_9_n_0 : STD_LOGIC;
signal \ascii_reg_n_0_[0]\ : STD_LOGIC;
signal \ascii_reg_n_0_[1]\ : STD_LOGIC;
signal \ascii_reg_n_0_[2]\ : STD_LOGIC;
signal \ascii_reg_n_0_[3]\ : STD_LOGIC;
signal \ascii_reg_n_0_[4]\ : STD_LOGIC;
signal \ascii_reg_n_0_[5]\ : STD_LOGIC;
signal \ascii_reg_n_0_[6]\ : STD_LOGIC;
signal \ascii_reg_n_0_[7]\ : STD_LOGIC;
signal break : STD_LOGIC;
signal caps_lock_reg_n_0 : STD_LOGIC;
signal control_l_reg_n_0 : STD_LOGIC;
signal control_r_reg_n_0 : STD_LOGIC;
signal e0_code : STD_LOGIC;
signal prev_ps2_code_new : STD_LOGIC;
signal ps2_code_new : STD_LOGIC;
signal ps2_keyboard_0_n_1 : STD_LOGIC;
signal ps2_keyboard_0_n_10 : STD_LOGIC;
signal ps2_keyboard_0_n_11 : STD_LOGIC;
signal ps2_keyboard_0_n_12 : STD_LOGIC;
signal ps2_keyboard_0_n_13 : STD_LOGIC;
signal ps2_keyboard_0_n_14 : STD_LOGIC;
signal ps2_keyboard_0_n_15 : STD_LOGIC;
signal ps2_keyboard_0_n_16 : STD_LOGIC;
signal ps2_keyboard_0_n_17 : STD_LOGIC;
signal ps2_keyboard_0_n_18 : STD_LOGIC;
signal ps2_keyboard_0_n_2 : STD_LOGIC;
signal ps2_keyboard_0_n_3 : STD_LOGIC;
signal ps2_keyboard_0_n_4 : STD_LOGIC;
signal ps2_keyboard_0_n_5 : STD_LOGIC;
signal ps2_keyboard_0_n_6 : STD_LOGIC;
signal ps2_keyboard_0_n_7 : STD_LOGIC;
signal ps2_keyboard_0_n_8 : STD_LOGIC;
signal ps2_keyboard_0_n_9 : STD_LOGIC;
signal \repeat_counter[0]_i_10_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_11_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_12_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_6_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_7_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_8_n_0\ : STD_LOGIC;
signal \repeat_counter[0]_i_9_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[12]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[16]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[20]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[4]_i_5_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_3_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_4_n_0\ : STD_LOGIC;
signal \repeat_counter[8]_i_5_n_0\ : STD_LOGIC;
signal repeat_counter_reg : STD_LOGIC_VECTOR ( 20 downto 0 );
signal \repeat_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \repeat_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
signal shift_l : STD_LOGIC;
signal shift_r : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[12]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \counter[13]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \counter[13]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \fb_in_dat[4]_i_2\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \next_s[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \next_s[1]_i_1\ : label is "soft_lutpair6";
begin
\ascii_code_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[0]\,
Q => ascii_code(0),
R => '0'
);
\ascii_code_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[1]\,
Q => ascii_code(1),
R => '0'
);
\ascii_code_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[2]\,
Q => ascii_code(2),
R => '0'
);
\ascii_code_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[3]\,
Q => ascii_code(3),
R => '0'
);
\ascii_code_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[4]\,
Q => ascii_code(4),
R => '0'
);
\ascii_code_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[5]\,
Q => ascii_code(5),
R => '0'
);
\ascii_code_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => ascii_new_i_1_n_0,
D => \ascii_reg_n_0_[6]\,
Q => ascii_code(6),
R => '0'
);
ascii_new_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A80800000000"
)
port map (
I0 => state(1),
I1 => ascii_new_i_2_n_0,
I2 => repeat_counter_reg(16),
I3 => ascii_new_i_3_n_0,
I4 => \ascii_reg_n_0_[7]\,
I5 => state(0),
O => ascii_new_i_1_n_0
);
ascii_new_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FF01FF00FE00"
)
port map (
I0 => repeat_counter_reg(19),
I1 => repeat_counter_reg(12),
I2 => repeat_counter_reg(11),
I3 => ascii_new_i_3_n_0,
I4 => repeat_counter_reg(10),
I5 => ascii_new_i_4_n_0,
O => ascii_new_i_2_n_0
);
ascii_new_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \ascii_reg_n_0_[3]\,
I1 => \ascii_reg_n_0_[5]\,
I2 => ascii_new_i_5_n_0,
I3 => \ascii_reg_n_0_[0]\,
I4 => \ascii_reg_n_0_[4]\,
I5 => \ascii_reg_n_0_[6]\,
O => ascii_new_i_3_n_0
);
ascii_new_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFFFFF40000000"
)
port map (
I0 => repeat_counter_reg(7),
I1 => ascii_new_i_6_n_0,
I2 => repeat_counter_reg(2),
I3 => repeat_counter_reg(0),
I4 => repeat_counter_reg(18),
I5 => ascii_new_i_3_n_0,
O => ascii_new_i_4_n_0
);
ascii_new_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \ascii_reg_n_0_[2]\,
I1 => \ascii_reg_n_0_[1]\,
O => ascii_new_i_5_n_0
);
ascii_new_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"EFFFFFFF40000000"
)
port map (
I0 => repeat_counter_reg(5),
I1 => ascii_new_i_7_n_0,
I2 => repeat_counter_reg(6),
I3 => repeat_counter_reg(17),
I4 => repeat_counter_reg(1),
I5 => ascii_new_i_3_n_0,
O => ascii_new_i_6_n_0
);
ascii_new_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFFFFF80000000"
)
port map (
I0 => ascii_new_i_8_n_0,
I1 => repeat_counter_reg(9),
I2 => repeat_counter_reg(4),
I3 => repeat_counter_reg(14),
I4 => repeat_counter_reg(15),
I5 => ascii_new_i_3_n_0,
O => ascii_new_i_7_n_0
);
ascii_new_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF8000"
)
port map (
I0 => repeat_counter_reg(13),
I1 => repeat_counter_reg(20),
I2 => repeat_counter_reg(3),
I3 => repeat_counter_reg(8),
I4 => ascii_new_i_9_n_0,
I5 => \ascii_reg_n_0_[6]\,
O => ascii_new_i_8_n_0
);
ascii_new_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \ascii_reg_n_0_[4]\,
I1 => \ascii_reg_n_0_[0]\,
I2 => \ascii_reg_n_0_[2]\,
I3 => \ascii_reg_n_0_[1]\,
I4 => \ascii_reg_n_0_[5]\,
I5 => \ascii_reg_n_0_[3]\,
O => ascii_new_i_9_n_0
);
ascii_new_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ascii_new_i_1_n_0,
Q => ascii_new,
R => '0'
);
\ascii_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_17,
Q => \ascii_reg_n_0_[0]\,
R => '0'
);
\ascii_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_16,
Q => \ascii_reg_n_0_[1]\,
R => '0'
);
\ascii_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_15,
Q => \ascii_reg_n_0_[2]\,
R => '0'
);
\ascii_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_14,
Q => \ascii_reg_n_0_[3]\,
R => '0'
);
\ascii_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_13,
Q => \ascii_reg_n_0_[4]\,
R => '0'
);
\ascii_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_12,
Q => \ascii_reg_n_0_[5]\,
R => '0'
);
\ascii_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => ps2_keyboard_0_n_18,
D => ps2_keyboard_0_n_11,
Q => \ascii_reg_n_0_[6]\,
R => '0'
);
\ascii_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_8,
Q => \ascii_reg_n_0_[7]\,
R => '0'
);
break_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_1,
Q => break,
R => '0'
);
caps_lock_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_7,
Q => caps_lock_reg_n_0,
R => '0'
);
control_l_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_6,
Q => control_l_reg_n_0,
R => '0'
);
control_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_5,
Q => control_r_reg_n_0,
R => '0'
);
\counter[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF10"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => ascii_new,
I3 => \current_s_reg[0]\,
O => SR(0)
);
\counter[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ascii_new,
I1 => Q(1),
I2 => Q(0),
O => SR(1)
);
\counter[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => Q(1),
I1 => ascii_new,
I2 => Q(0),
O => E(0)
);
e0_code_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_4,
Q => e0_code,
R => '0'
);
\fb_in_dat[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F55C055C"
)
port map (
I0 => \counter_reg[0]_2\(0),
I1 => \counter_reg[0]_3\,
I2 => Q(1),
I3 => Q(0),
I4 => ascii_code(0),
O => \fb_in_dat_reg[0]\
);
\fb_in_dat[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAAC0AAC"
)
port map (
I0 => O(0),
I1 => \counter_reg[0]_4\,
I2 => Q(1),
I3 => Q(0),
I4 => ascii_code(1),
O => \fb_in_dat_reg[1]\
);
\fb_in_dat[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAAC0AAC"
)
port map (
I0 => O(1),
I1 => \counter_reg[0]_5\,
I2 => Q(1),
I3 => Q(0),
I4 => ascii_code(2),
O => \fb_in_dat_reg[2]\
);
\fb_in_dat[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAAC0AAC"
)
port map (
I0 => O(2),
I1 => \counter_reg[0]_6\,
I2 => Q(1),
I3 => Q(0),
I4 => ascii_code(3),
O => \fb_in_dat_reg[3]\
);
\fb_in_dat[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE3E"
)
port map (
I0 => \counter_reg[0]_7\,
I1 => Q(0),
I2 => Q(1),
I3 => ascii_code(4),
O => \fb_in_dat_reg[4]\
);
\fb_in_dat[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AFFCA00C"
)
port map (
I0 => ascii_code(5),
I1 => \counter_reg[0]\,
I2 => Q(0),
I3 => Q(1),
I4 => \counter_reg[0]_0\,
O => \fb_in_dat_reg[6]\(0)
);
\fb_in_dat[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8380"
)
port map (
I0 => ascii_code(6),
I1 => Q(0),
I2 => Q(1),
I3 => \counter_reg[0]_1\,
O => \fb_in_dat_reg[6]\(1)
);
\next_s[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEE0EEEE"
)
port map (
I0 => D(0),
I1 => \current_s_reg[0]\,
I2 => Q(0),
I3 => Q(1),
I4 => ascii_new,
O => \next_s_reg[0]\
);
\next_s[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF10"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => ascii_new,
I3 => \current_s_reg[0]\,
I4 => D(1),
O => \next_s_reg[1]\
);
prev_ps2_code_new_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_code_new,
Q => prev_ps2_code_new,
R => '0'
);
ps2_keyboard_0: entity work.ps2_keyboard
port map (
D(1) => ps2_keyboard_0_n_9,
D(0) => ps2_keyboard_0_n_10,
E(0) => ps2_keyboard_0_n_18,
PS2Clk_IBUF => PS2Clk_IBUF,
PS2Data_IBUF => PS2Data_IBUF,
Q(1 downto 0) => state(1 downto 0),
\ascii_reg[6]\(6) => ps2_keyboard_0_n_11,
\ascii_reg[6]\(5) => ps2_keyboard_0_n_12,
\ascii_reg[6]\(4) => ps2_keyboard_0_n_13,
\ascii_reg[6]\(3) => ps2_keyboard_0_n_14,
\ascii_reg[6]\(2) => ps2_keyboard_0_n_15,
\ascii_reg[6]\(1) => ps2_keyboard_0_n_16,
\ascii_reg[6]\(0) => ps2_keyboard_0_n_17,
\ascii_reg[7]\ => ps2_keyboard_0_n_8,
\ascii_reg[7]_0\ => \ascii_reg_n_0_[7]\,
break => break,
break_reg => ps2_keyboard_0_n_1,
caps_lock_reg => ps2_keyboard_0_n_7,
caps_lock_reg_0 => caps_lock_reg_n_0,
clk_BUFG => clk_BUFG,
control_l_reg => ps2_keyboard_0_n_6,
control_l_reg_0 => control_l_reg_n_0,
control_r_reg => ps2_keyboard_0_n_5,
control_r_reg_0 => control_r_reg_n_0,
e0_code => e0_code,
e0_code_reg => ps2_keyboard_0_n_4,
prev_ps2_code_new => prev_ps2_code_new,
ps2_code_new => ps2_code_new,
shift_l => shift_l,
shift_l_reg => ps2_keyboard_0_n_2,
shift_r => shift_r,
shift_r_reg => ps2_keyboard_0_n_3
);
\repeat_counter[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00A80000"
)
port map (
I0 => state(1),
I1 => repeat_counter_reg(16),
I2 => \repeat_counter[0]_i_3_n_0\,
I3 => \ascii_reg_n_0_[7]\,
I4 => state(0),
O => \repeat_counter[0]_i_1_n_0\
);
\repeat_counter[0]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \ascii_reg_n_0_[3]\,
I1 => \ascii_reg_n_0_[5]\,
I2 => ascii_new_i_5_n_0,
I3 => \ascii_reg_n_0_[0]\,
I4 => \ascii_reg_n_0_[4]\,
I5 => \ascii_reg_n_0_[6]\,
O => \repeat_counter[0]_i_10_n_0\
);
\repeat_counter[0]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFFFFFFFFFF"
)
port map (
I0 => repeat_counter_reg(6),
I1 => repeat_counter_reg(14),
I2 => \repeat_counter[0]_i_12_n_0\,
I3 => repeat_counter_reg(4),
I4 => repeat_counter_reg(15),
I5 => repeat_counter_reg(17),
O => \repeat_counter[0]_i_11_n_0\
);
\repeat_counter[0]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFFFFFFFFFF"
)
port map (
I0 => repeat_counter_reg(8),
I1 => repeat_counter_reg(20),
I2 => ascii_new_i_3_n_0,
I3 => repeat_counter_reg(13),
I4 => repeat_counter_reg(3),
I5 => repeat_counter_reg(9),
O => \repeat_counter[0]_i_12_n_0\
);
\repeat_counter[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => repeat_counter_reg(12),
I1 => repeat_counter_reg(10),
I2 => \repeat_counter[0]_i_9_n_0\,
I3 => repeat_counter_reg(7),
I4 => repeat_counter_reg(11),
I5 => repeat_counter_reg(19),
O => \repeat_counter[0]_i_3_n_0\
);
\repeat_counter[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(0),
O => \repeat_counter[0]_i_4_n_0\
);
\repeat_counter[0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(3),
O => \repeat_counter[0]_i_5_n_0\
);
\repeat_counter[0]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(2),
O => \repeat_counter[0]_i_6_n_0\
);
\repeat_counter[0]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(1),
O => \repeat_counter[0]_i_7_n_0\
);
\repeat_counter[0]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => repeat_counter_reg(0),
I1 => \repeat_counter[0]_i_10_n_0\,
O => \repeat_counter[0]_i_8_n_0\
);
\repeat_counter[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF7FFFFFFFFFFFF"
)
port map (
I0 => repeat_counter_reg(0),
I1 => repeat_counter_reg(1),
I2 => \repeat_counter[0]_i_11_n_0\,
I3 => repeat_counter_reg(5),
I4 => repeat_counter_reg(2),
I5 => repeat_counter_reg(18),
O => \repeat_counter[0]_i_9_n_0\
);
\repeat_counter[12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(15),
O => \repeat_counter[12]_i_2_n_0\
);
\repeat_counter[12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(14),
O => \repeat_counter[12]_i_3_n_0\
);
\repeat_counter[12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(13),
O => \repeat_counter[12]_i_4_n_0\
);
\repeat_counter[12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(12),
O => \repeat_counter[12]_i_5_n_0\
);
\repeat_counter[16]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(19),
O => \repeat_counter[16]_i_2_n_0\
);
\repeat_counter[16]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(18),
O => \repeat_counter[16]_i_3_n_0\
);
\repeat_counter[16]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(17),
O => \repeat_counter[16]_i_4_n_0\
);
\repeat_counter[16]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(16),
O => \repeat_counter[16]_i_5_n_0\
);
\repeat_counter[20]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(20),
O => \repeat_counter[20]_i_2_n_0\
);
\repeat_counter[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(7),
O => \repeat_counter[4]_i_2_n_0\
);
\repeat_counter[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(6),
O => \repeat_counter[4]_i_3_n_0\
);
\repeat_counter[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(5),
O => \repeat_counter[4]_i_4_n_0\
);
\repeat_counter[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(4),
O => \repeat_counter[4]_i_5_n_0\
);
\repeat_counter[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(11),
O => \repeat_counter[8]_i_2_n_0\
);
\repeat_counter[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(10),
O => \repeat_counter[8]_i_3_n_0\
);
\repeat_counter[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(9),
O => \repeat_counter[8]_i_4_n_0\
);
\repeat_counter[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \repeat_counter[0]_i_10_n_0\,
I1 => repeat_counter_reg(8),
O => \repeat_counter[8]_i_5_n_0\
);
\repeat_counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_7\,
Q => repeat_counter_reg(0),
R => '0'
);
\repeat_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \repeat_counter_reg[0]_i_2_n_0\,
CO(2) => \repeat_counter_reg[0]_i_2_n_1\,
CO(1) => \repeat_counter_reg[0]_i_2_n_2\,
CO(0) => \repeat_counter_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \repeat_counter[0]_i_4_n_0\,
O(3) => \repeat_counter_reg[0]_i_2_n_4\,
O(2) => \repeat_counter_reg[0]_i_2_n_5\,
O(1) => \repeat_counter_reg[0]_i_2_n_6\,
O(0) => \repeat_counter_reg[0]_i_2_n_7\,
S(3) => \repeat_counter[0]_i_5_n_0\,
S(2) => \repeat_counter[0]_i_6_n_0\,
S(1) => \repeat_counter[0]_i_7_n_0\,
S(0) => \repeat_counter[0]_i_8_n_0\
);
\repeat_counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_5\,
Q => repeat_counter_reg(10),
R => '0'
);
\repeat_counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_4\,
Q => repeat_counter_reg(11),
R => '0'
);
\repeat_counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_7\,
Q => repeat_counter_reg(12),
R => '0'
);
\repeat_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[8]_i_1_n_0\,
CO(3) => \repeat_counter_reg[12]_i_1_n_0\,
CO(2) => \repeat_counter_reg[12]_i_1_n_1\,
CO(1) => \repeat_counter_reg[12]_i_1_n_2\,
CO(0) => \repeat_counter_reg[12]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[12]_i_1_n_4\,
O(2) => \repeat_counter_reg[12]_i_1_n_5\,
O(1) => \repeat_counter_reg[12]_i_1_n_6\,
O(0) => \repeat_counter_reg[12]_i_1_n_7\,
S(3) => \repeat_counter[12]_i_2_n_0\,
S(2) => \repeat_counter[12]_i_3_n_0\,
S(1) => \repeat_counter[12]_i_4_n_0\,
S(0) => \repeat_counter[12]_i_5_n_0\
);
\repeat_counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_6\,
Q => repeat_counter_reg(13),
R => '0'
);
\repeat_counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_5\,
Q => repeat_counter_reg(14),
R => '0'
);
\repeat_counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[12]_i_1_n_4\,
Q => repeat_counter_reg(15),
R => '0'
);
\repeat_counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_7\,
Q => repeat_counter_reg(16),
R => '0'
);
\repeat_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[12]_i_1_n_0\,
CO(3) => \repeat_counter_reg[16]_i_1_n_0\,
CO(2) => \repeat_counter_reg[16]_i_1_n_1\,
CO(1) => \repeat_counter_reg[16]_i_1_n_2\,
CO(0) => \repeat_counter_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[16]_i_1_n_4\,
O(2) => \repeat_counter_reg[16]_i_1_n_5\,
O(1) => \repeat_counter_reg[16]_i_1_n_6\,
O(0) => \repeat_counter_reg[16]_i_1_n_7\,
S(3) => \repeat_counter[16]_i_2_n_0\,
S(2) => \repeat_counter[16]_i_3_n_0\,
S(1) => \repeat_counter[16]_i_4_n_0\,
S(0) => \repeat_counter[16]_i_5_n_0\
);
\repeat_counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_6\,
Q => repeat_counter_reg(17),
R => '0'
);
\repeat_counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_5\,
Q => repeat_counter_reg(18),
R => '0'
);
\repeat_counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[16]_i_1_n_4\,
Q => repeat_counter_reg(19),
R => '0'
);
\repeat_counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_6\,
Q => repeat_counter_reg(1),
R => '0'
);
\repeat_counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[20]_i_1_n_7\,
Q => repeat_counter_reg(20),
R => '0'
);
\repeat_counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[16]_i_1_n_0\,
CO(3 downto 0) => \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => \repeat_counter_reg[20]_i_1_n_7\,
S(3 downto 1) => B"000",
S(0) => \repeat_counter[20]_i_2_n_0\
);
\repeat_counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_5\,
Q => repeat_counter_reg(2),
R => '0'
);
\repeat_counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[0]_i_2_n_4\,
Q => repeat_counter_reg(3),
R => '0'
);
\repeat_counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_7\,
Q => repeat_counter_reg(4),
R => '0'
);
\repeat_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[0]_i_2_n_0\,
CO(3) => \repeat_counter_reg[4]_i_1_n_0\,
CO(2) => \repeat_counter_reg[4]_i_1_n_1\,
CO(1) => \repeat_counter_reg[4]_i_1_n_2\,
CO(0) => \repeat_counter_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[4]_i_1_n_4\,
O(2) => \repeat_counter_reg[4]_i_1_n_5\,
O(1) => \repeat_counter_reg[4]_i_1_n_6\,
O(0) => \repeat_counter_reg[4]_i_1_n_7\,
S(3) => \repeat_counter[4]_i_2_n_0\,
S(2) => \repeat_counter[4]_i_3_n_0\,
S(1) => \repeat_counter[4]_i_4_n_0\,
S(0) => \repeat_counter[4]_i_5_n_0\
);
\repeat_counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_6\,
Q => repeat_counter_reg(5),
R => '0'
);
\repeat_counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_5\,
Q => repeat_counter_reg(6),
R => '0'
);
\repeat_counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[4]_i_1_n_4\,
Q => repeat_counter_reg(7),
R => '0'
);
\repeat_counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_7\,
Q => repeat_counter_reg(8),
R => '0'
);
\repeat_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \repeat_counter_reg[4]_i_1_n_0\,
CO(3) => \repeat_counter_reg[8]_i_1_n_0\,
CO(2) => \repeat_counter_reg[8]_i_1_n_1\,
CO(1) => \repeat_counter_reg[8]_i_1_n_2\,
CO(0) => \repeat_counter_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \repeat_counter_reg[8]_i_1_n_4\,
O(2) => \repeat_counter_reg[8]_i_1_n_5\,
O(1) => \repeat_counter_reg[8]_i_1_n_6\,
O(0) => \repeat_counter_reg[8]_i_1_n_7\,
S(3) => \repeat_counter[8]_i_2_n_0\,
S(2) => \repeat_counter[8]_i_3_n_0\,
S(1) => \repeat_counter[8]_i_4_n_0\,
S(0) => \repeat_counter[8]_i_5_n_0\
);
\repeat_counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => \repeat_counter[0]_i_1_n_0\,
D => \repeat_counter_reg[8]_i_1_n_6\,
Q => repeat_counter_reg(9),
R => '0'
);
shift_l_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_2,
Q => shift_l,
R => '0'
);
shift_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_3,
Q => shift_r,
R => '0'
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_10,
Q => state(0),
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => ps2_keyboard_0_n_9,
Q => state(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end FrameBuffer_blk_mem_gen_generic_cstr;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is
signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
begin
\has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0),
DOBDO(7) => \ramloop[2].ram.r_n_0\,
DOBDO(6) => \ramloop[2].ram.r_n_1\,
DOBDO(5) => \ramloop[2].ram.r_n_2\,
DOBDO(4) => \ramloop[2].ram.r_n_3\,
DOBDO(3) => \ramloop[2].ram.r_n_4\,
DOBDO(2) => \ramloop[2].ram.r_n_5\,
DOBDO(1) => \ramloop[2].ram.r_n_6\,
DOBDO(0) => \ramloop[2].ram.r_n_7\,
addrb(2 downto 0) => addrb(13 downto 11),
clkb => clkb,
doutb(7 downto 0) => doutb(7 downto 0)
);
\ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7 downto 0) => ram_doutb(7 downto 0),
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
\doutb[7]\(7) => \ramloop[1].ram.r_n_0\,
\doutb[7]\(6) => \ramloop[1].ram.r_n_1\,
\doutb[7]\(5) => \ramloop[1].ram.r_n_2\,
\doutb[7]\(4) => \ramloop[1].ram.r_n_3\,
\doutb[7]\(3) => \ramloop[1].ram.r_n_4\,
\doutb[7]\(2) => \ramloop[1].ram.r_n_5\,
\doutb[7]\(1) => \ramloop[1].ram.r_n_6\,
\doutb[7]\(0) => \ramloop[1].ram.r_n_7\,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\
port map (
DOBDO(7) => \ramloop[2].ram.r_n_0\,
DOBDO(6) => \ramloop[2].ram.r_n_1\,
DOBDO(5) => \ramloop[2].ram.r_n_2\,
DOBDO(4) => \ramloop[2].ram.r_n_3\,
DOBDO(3) => \ramloop[2].ram.r_n_4\,
DOBDO(2) => \ramloop[2].ram.r_n_5\,
DOBDO(1) => \ramloop[2].ram.r_n_6\,
DOBDO(0) => \ramloop[2].ram.r_n_7\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top";
end FrameBuffer_blk_mem_gen_top;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is
begin
\valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end FrameBuffer_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "20";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.58651 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes";
end FrameBuffer_blk_mem_gen_v8_3_1;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=20,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.58651 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end FrameBuffer;
architecture STRUCTURE of FrameBuffer is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "20";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.58651 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
port (
vgaRed : out STD_LOGIC_VECTOR ( 3 downto 0 );
vgaGreen : out STD_LOGIC_VECTOR ( 3 downto 0 );
vgaBlue : out STD_LOGIC_VECTOR ( 3 downto 0 );
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
led : out STD_LOGIC_VECTOR ( 15 downto 0 );
sw : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
btnC : in STD_LOGIC;
btnU : in STD_LOGIC;
btnL : in STD_LOGIC;
btnR : in STD_LOGIC;
btnD : in STD_LOGIC;
PS2Clk : in STD_LOGIC;
PS2Data : in STD_LOGIC;
RsRx : inout STD_LOGIC;
RsTx : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of top : entity is true;
end top;
architecture STRUCTURE of top is
signal Hsync_OBUF : STD_LOGIC;
signal PS2Clk_IBUF : STD_LOGIC;
signal PS2Data_IBUF : STD_LOGIC;
signal Vsync_OBUF : STD_LOGIC;
signal addra : STD_LOGIC_VECTOR ( 13 downto 0 );
signal btnC_IBUF : STD_LOGIC;
signal btnD_IBUF : STD_LOGIC;
signal btnL_IBUF : STD_LOGIC;
signal btnR_IBUF : STD_LOGIC;
signal btnU_IBUF : STD_LOGIC;
signal clk108M : STD_LOGIC;
signal clk10M : STD_LOGIC;
signal clk_1_i_1_n_0 : STD_LOGIC;
signal clk_1_i_2_n_0 : STD_LOGIC;
signal clk_1_i_3_n_0 : STD_LOGIC;
signal clk_1_i_4_n_0 : STD_LOGIC;
signal clk_1_i_5_n_0 : STD_LOGIC;
signal clk_1_reg_n_0 : STD_LOGIC;
signal clk_BUFG : STD_LOGIC;
signal clk_IBUF : STD_LOGIC;
signal \counter[0]__0_i_1_n_0\ : STD_LOGIC;
signal \counter[0]_i_1_n_0\ : STD_LOGIC;
signal \counter[10]_i_1_n_0\ : STD_LOGIC;
signal \counter[11]_i_1_n_0\ : STD_LOGIC;
signal \counter[12]__0_i_2_n_0\ : STD_LOGIC;
signal \counter[12]__0_i_3_n_0\ : STD_LOGIC;
signal \counter[12]__0_i_4_n_0\ : STD_LOGIC;
signal \counter[12]__0_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_2_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[12]_i_7_n_0\ : STD_LOGIC;
signal \counter[13]_i_3_n_0\ : STD_LOGIC;
signal \counter[13]_i_4_n_0\ : STD_LOGIC;
signal \counter[13]_i_6_n_0\ : STD_LOGIC;
signal \counter[13]_i_7_n_0\ : STD_LOGIC;
signal \counter[13]_i_8_n_0\ : STD_LOGIC;
signal \counter[16]_i_2_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[1]_i_1_n_0\ : STD_LOGIC;
signal \counter[20]_i_2_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[22]_i_10_n_0\ : STD_LOGIC;
signal \counter[22]_i_11_n_0\ : STD_LOGIC;
signal \counter[22]_i_12_n_0\ : STD_LOGIC;
signal \counter[22]_i_13_n_0\ : STD_LOGIC;
signal \counter[22]_i_14_n_0\ : STD_LOGIC;
signal \counter[22]_i_15_n_0\ : STD_LOGIC;
signal \counter[22]_i_16_n_0\ : STD_LOGIC;
signal \counter[22]_i_17_n_0\ : STD_LOGIC;
signal \counter[22]_i_18_n_0\ : STD_LOGIC;
signal \counter[22]_i_19_n_0\ : STD_LOGIC;
signal \counter[22]_i_1_n_0\ : STD_LOGIC;
signal \counter[22]_i_20_n_0\ : STD_LOGIC;
signal \counter[22]_i_21_n_0\ : STD_LOGIC;
signal \counter[22]_i_22_n_0\ : STD_LOGIC;
signal \counter[22]_i_4_n_0\ : STD_LOGIC;
signal \counter[22]_i_5_n_0\ : STD_LOGIC;
signal \counter[22]_i_7_n_0\ : STD_LOGIC;
signal \counter[22]_i_8_n_0\ : STD_LOGIC;
signal \counter[2]_i_1_n_0\ : STD_LOGIC;
signal \counter[3]_i_1_n_0\ : STD_LOGIC;
signal \counter[4]__0_i_2_n_0\ : STD_LOGIC;
signal \counter[4]__0_i_3_n_0\ : STD_LOGIC;
signal \counter[4]__0_i_4_n_0\ : STD_LOGIC;
signal \counter[4]__0_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_1_n_0\ : STD_LOGIC;
signal \counter[5]_i_1_n_0\ : STD_LOGIC;
signal \counter[6]_i_1_n_0\ : STD_LOGIC;
signal \counter[7]_i_1_n_0\ : STD_LOGIC;
signal \counter[8]__0_i_2_n_0\ : STD_LOGIC;
signal \counter[8]__0_i_3_n_0\ : STD_LOGIC;
signal \counter[8]__0_i_4_n_0\ : STD_LOGIC;
signal \counter[8]__0_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_1_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter[9]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[0]__0_n_0\ : STD_LOGIC;
signal \counter_reg[10]__0_n_0\ : STD_LOGIC;
signal \counter_reg[11]__0_n_0\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[12]__0_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[12]__0_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_3_n_7\ : STD_LOGIC;
signal \counter_reg[13]__0_n_0\ : STD_LOGIC;
signal \counter_reg[13]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[1]__0_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[22]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[22]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[22]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[22]_i_3_n_3\ : STD_LOGIC;
signal \counter_reg[22]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[22]_i_6_n_1\ : STD_LOGIC;
signal \counter_reg[22]_i_6_n_2\ : STD_LOGIC;
signal \counter_reg[22]_i_6_n_3\ : STD_LOGIC;
signal \counter_reg[22]_i_9_n_0\ : STD_LOGIC;
signal \counter_reg[22]_i_9_n_1\ : STD_LOGIC;
signal \counter_reg[22]_i_9_n_2\ : STD_LOGIC;
signal \counter_reg[22]_i_9_n_3\ : STD_LOGIC;
signal \counter_reg[2]__0_n_0\ : STD_LOGIC;
signal \counter_reg[3]__0_n_0\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[4]__0_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[4]__0_n_0\ : STD_LOGIC;
signal \counter_reg[5]__0_n_0\ : STD_LOGIC;
signal \counter_reg[6]__0_n_0\ : STD_LOGIC;
signal \counter_reg[7]__0_n_0\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_0\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_1\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_2\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_3\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_4\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_5\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_6\ : STD_LOGIC;
signal \counter_reg[8]__0_i_1_n_7\ : STD_LOGIC;
signal \counter_reg[8]__0_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[9]__0_n_0\ : STD_LOGIC;
signal \counter_reg_n_0_[0]\ : STD_LOGIC;
signal \counter_reg_n_0_[10]\ : STD_LOGIC;
signal \counter_reg_n_0_[11]\ : STD_LOGIC;
signal \counter_reg_n_0_[12]\ : STD_LOGIC;
signal \counter_reg_n_0_[13]\ : STD_LOGIC;
signal \counter_reg_n_0_[14]\ : STD_LOGIC;
signal \counter_reg_n_0_[15]\ : STD_LOGIC;
signal \counter_reg_n_0_[16]\ : STD_LOGIC;
signal \counter_reg_n_0_[17]\ : STD_LOGIC;
signal \counter_reg_n_0_[18]\ : STD_LOGIC;
signal \counter_reg_n_0_[19]\ : STD_LOGIC;
signal \counter_reg_n_0_[1]\ : STD_LOGIC;
signal \counter_reg_n_0_[20]\ : STD_LOGIC;
signal \counter_reg_n_0_[21]\ : STD_LOGIC;
signal \counter_reg_n_0_[22]\ : STD_LOGIC;
signal \counter_reg_n_0_[2]\ : STD_LOGIC;
signal \counter_reg_n_0_[3]\ : STD_LOGIC;
signal \counter_reg_n_0_[4]\ : STD_LOGIC;
signal \counter_reg_n_0_[5]\ : STD_LOGIC;
signal \counter_reg_n_0_[6]\ : STD_LOGIC;
signal \counter_reg_n_0_[7]\ : STD_LOGIC;
signal \counter_reg_n_0_[8]\ : STD_LOGIC;
signal \counter_reg_n_0_[9]\ : STD_LOGIC;
signal current_s : STD_LOGIC_VECTOR ( 1 downto 0 );
signal dina : STD_LOGIC_VECTOR ( 7 downto 0 );
signal doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal fb_in_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
signal fb_in_addr0 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \fb_in_addr[11]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_7_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_8_n_0\ : STD_LOGIC;
signal \fb_in_addr[11]_i_9_n_0\ : STD_LOGIC;
signal \fb_in_addr[13]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[13]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_6_n_0\ : STD_LOGIC;
signal \fb_in_addr[3]_i_7_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_6_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_7_n_0\ : STD_LOGIC;
signal \fb_in_addr[7]_i_8_n_0\ : STD_LOGIC;
signal \fb_in_addr_reg[11]_i_2_n_0\ : STD_LOGIC;
signal \fb_in_addr_reg[11]_i_2_n_1\ : STD_LOGIC;
signal \fb_in_addr_reg[11]_i_2_n_2\ : STD_LOGIC;
signal \fb_in_addr_reg[11]_i_2_n_3\ : STD_LOGIC;
signal \fb_in_addr_reg[13]_i_2_n_3\ : STD_LOGIC;
signal \fb_in_addr_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \fb_in_addr_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \fb_in_addr_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \fb_in_addr_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \fb_in_addr_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \fb_in_addr_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \fb_in_addr_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \fb_in_addr_reg[7]_i_2_n_3\ : STD_LOGIC;
signal fb_in_dat : STD_LOGIC_VECTOR ( 7 downto 5 );
signal \fb_in_dat[4]_i_1_n_0\ : STD_LOGIC;
signal \fb_in_dat[5]_i_2_n_0\ : STD_LOGIC;
signal \fb_in_dat[5]_i_3_n_0\ : STD_LOGIC;
signal \fb_in_dat[5]_i_4_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_10_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_11_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_1\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_2\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_3\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_4\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_5\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_6\ : STD_LOGIC;
signal \g0_b0__0_i_1_n_7\ : STD_LOGIC;
signal \g0_b0__0_i_2_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_3_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_4_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_5_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_6_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_7_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_8_n_0\ : STD_LOGIC;
signal \g0_b0__0_i_9_n_0\ : STD_LOGIC;
signal \g0_b0__0_n_0\ : STD_LOGIC;
signal \g0_b1__0_n_0\ : STD_LOGIC;
signal \g0_b2__0_n_0\ : STD_LOGIC;
signal \g0_b3__0_n_0\ : STD_LOGIC;
signal \g0_b4__0_n_0\ : STD_LOGIC;
signal \g0_b5__0_n_0\ : STD_LOGIC;
signal \g0_b6__0_n_0\ : STD_LOGIC;
signal keyboard0_n_0 : STD_LOGIC;
signal keyboard0_n_10 : STD_LOGIC;
signal keyboard0_n_11 : STD_LOGIC;
signal keyboard0_n_3 : STD_LOGIC;
signal keyboard0_n_4 : STD_LOGIC;
signal keyboard0_n_5 : STD_LOGIC;
signal keyboard0_n_6 : STD_LOGIC;
signal keyboard0_n_7 : STD_LOGIC;
signal keyboard0_n_8 : STD_LOGIC;
signal keyboard0_n_9 : STD_LOGIC;
signal next_s : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \next_s[1]_i_2_n_0\ : STD_LOGIC;
signal \next_s[1]_i_3_n_0\ : STD_LOGIC;
signal \next_s[1]_i_4_n_0\ : STD_LOGIC;
signal \next_s[1]_i_5_n_0\ : STD_LOGIC;
signal \sw[0]\ : STD_LOGIC;
signal \sw[0]_IBUF\ : STD_LOGIC;
signal \sw[10]\ : STD_LOGIC;
signal \sw[10]_IBUF\ : STD_LOGIC;
signal \sw[11]\ : STD_LOGIC;
signal \sw[11]_IBUF\ : STD_LOGIC;
signal \sw[12]\ : STD_LOGIC;
signal \sw[12]_IBUF\ : STD_LOGIC;
signal \sw[13]\ : STD_LOGIC;
signal \sw[13]_IBUF\ : STD_LOGIC;
signal \sw[14]\ : STD_LOGIC;
signal \sw[14]_IBUF\ : STD_LOGIC;
signal \sw[15]\ : STD_LOGIC;
signal \sw[15]_IBUF\ : STD_LOGIC;
signal \sw[1]\ : STD_LOGIC;
signal \sw[1]_IBUF\ : STD_LOGIC;
signal \sw[2]\ : STD_LOGIC;
signal \sw[2]_IBUF\ : STD_LOGIC;
signal \sw[3]\ : STD_LOGIC;
signal \sw[3]_IBUF\ : STD_LOGIC;
signal \sw[4]\ : STD_LOGIC;
signal \sw[4]_IBUF\ : STD_LOGIC;
signal \sw[5]\ : STD_LOGIC;
signal \sw[5]_IBUF\ : STD_LOGIC;
signal \sw[6]\ : STD_LOGIC;
signal \sw[6]_IBUF\ : STD_LOGIC;
signal \sw[7]\ : STD_LOGIC;
signal \sw[7]_IBUF\ : STD_LOGIC;
signal \sw[8]\ : STD_LOGIC;
signal \sw[8]_IBUF\ : STD_LOGIC;
signal \sw[9]\ : STD_LOGIC;
signal \sw[9]_IBUF\ : STD_LOGIC;
signal vgaBlue_OBUF : STD_LOGIC_VECTOR ( 0 to 0 );
signal \PS2Clk^Mid\ : STD_LOGIC;
signal \PS2Data^Mid\ : STD_LOGIC;
signal \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[13]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_counter_reg[22]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_counter_reg[22]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[22]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_counter_reg[22]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute OPT_INSERTED : boolean;
attribute OPT_INSERTED of btnC_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnD_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnL_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnR_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of btnU_IBUF_inst : label is std.standard.true;
attribute OPT_INSERTED of clk_IBUF_inst : label is std.standard.true;
attribute syn_black_box : string;
attribute syn_black_box of clock0 : label is "TRUE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \fb_in_addr[0]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \fb_in_dat[7]_i_1\ : label is "soft_lutpair25";
attribute syn_black_box of frameBuffer0 : label is "TRUE";
attribute x_core_info : string;
attribute x_core_info of frameBuffer0 : label is "blk_mem_gen_v8_3_1,Vivado 2015.4";
attribute SOFT_HLUTNM of \g0_b0__0_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \g0_b0__0_i_4\ : label is "soft_lutpair24";
attribute OPT_INSERTED of \sw[0]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[10]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[11]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[12]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[13]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[14]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[15]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[1]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[2]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[3]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[4]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[5]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[6]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[7]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[8]_IBUF_inst\ : label is std.standard.true;
attribute OPT_INSERTED of \sw[9]_IBUF_inst\ : label is std.standard.true;
begin
\PS2Clk^Mid\ <= PS2Clk;
\PS2Data^Mid\ <= PS2Data;
\sw[0]\ <= sw(0);
\sw[10]\ <= sw(10);
\sw[11]\ <= sw(11);
\sw[12]\ <= sw(12);
\sw[13]\ <= sw(13);
\sw[14]\ <= sw(14);
\sw[15]\ <= sw(15);
\sw[1]\ <= sw(1);
\sw[2]\ <= sw(2);
\sw[3]\ <= sw(3);
\sw[4]\ <= sw(4);
\sw[5]\ <= sw(5);
\sw[6]\ <= sw(6);
\sw[7]\ <= sw(7);
\sw[8]\ <= sw(8);
\sw[9]\ <= sw(9);
\pullup_PS2Clk^Midinst\: unisim.vcomponents.PULLUP
port map (
O => \PS2Clk^Mid\
);
\pullup_PS2Data^Midinst\: unisim.vcomponents.PULLUP
port map (
O => \PS2Data^Mid\
);
Hsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => Hsync_OBUF,
O => Hsync
);
PS2Clk_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => \PS2Clk^Mid\,
O => PS2Clk_IBUF
);
PS2Data_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => \PS2Data^Mid\,
O => PS2Data_IBUF
);
Vsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => Vsync_OBUF,
O => Vsync
);
btnC_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnC,
O => btnC_IBUF
);
btnD_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnD,
O => btnD_IBUF
);
btnL_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnL,
O => btnL_IBUF
);
btnR_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnR,
O => btnR_IBUF
);
btnU_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => btnU,
O => btnU_IBUF
);
clk_1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"2AAAAAAAD5555555"
)
port map (
I0 => \counter_reg[22]_i_3_n_3\,
I1 => clk_1_i_2_n_0,
I2 => clk_1_i_3_n_0,
I3 => clk_1_i_4_n_0,
I4 => clk_1_i_5_n_0,
I5 => clk_1_reg_n_0,
O => clk_1_i_1_n_0
);
clk_1_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \counter_reg[16]_i_1_n_6\,
I1 => \counter_reg[16]_i_1_n_5\,
I2 => \counter_reg[12]__0_i_1_n_4\,
I3 => \counter_reg[16]_i_1_n_7\,
I4 => \counter_reg[20]_i_1_n_7\,
I5 => \counter_reg[16]_i_1_n_4\,
O => clk_1_i_2_n_0
);
clk_1_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \counter_reg[20]_i_1_n_4\,
I1 => \counter_reg[22]_i_2_n_7\,
I2 => \counter_reg[20]_i_1_n_6\,
I3 => \counter_reg[20]_i_1_n_5\,
I4 => \counter_reg[22]_i_2_n_6\,
I5 => \counter_reg[0]__0_n_0\,
O => clk_1_i_3_n_0
);
clk_1_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \counter_reg[8]__0_i_1_n_4\,
I1 => \counter_reg[12]__0_i_1_n_7\,
I2 => \counter_reg[8]__0_i_1_n_6\,
I3 => \counter_reg[8]__0_i_1_n_5\,
I4 => \counter_reg[12]__0_i_1_n_5\,
I5 => \counter_reg[12]__0_i_1_n_6\,
O => clk_1_i_4_n_0
);
clk_1_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter_reg[4]__0_i_1_n_7\,
I1 => \counter_reg[4]__0_i_1_n_6\,
I2 => \counter_reg[4]__0_i_1_n_5\,
I3 => \counter_reg[8]__0_i_1_n_7\,
I4 => \counter_reg[4]__0_i_1_n_4\,
O => clk_1_i_5_n_0
);
clk_1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => clk_1_i_1_n_0,
Q => clk_1_reg_n_0,
R => '0'
);
clk_BUFG_inst: unisim.vcomponents.BUFG
port map (
I => clk_IBUF,
O => clk_BUFG
);
clk_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => clk,
O => clk_IBUF
);
clock0: entity work.ClockDivider
port map (
clk108M => clk108M,
clk10M => clk10M,
clkIn => clk_BUFG
);
\counter[0]__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[0]__0_n_0\,
O => \counter[0]__0_i_1_n_0\
);
\counter[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000DDAF"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg_n_0_[0]\,
O => \counter[0]_i_1_n_0\
);
\counter[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BBCF0000"
)
port map (
I0 => \counter[13]_i_4_n_0\,
I1 => current_s(0),
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[12]_i_3_n_6\,
O => \counter[10]_i_1_n_0\
);
\counter[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[12]_i_3_n_5\,
O => \counter[11]_i_1_n_0\
);
\counter[12]__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[12]__0_n_0\,
O => \counter[12]__0_i_2_n_0\
);
\counter[12]__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[11]__0_n_0\,
O => \counter[12]__0_i_3_n_0\
);
\counter[12]__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[10]__0_n_0\,
O => \counter[12]__0_i_4_n_0\
);
\counter[12]__0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[9]__0_n_0\,
O => \counter[12]__0_i_5_n_0\
);
\counter[12]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[12]_i_3_n_4\,
O => \counter[12]_i_2_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[12]\,
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[11]\,
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[10]\,
O => \counter[12]_i_6_n_0\
);
\counter[12]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[9]\,
O => \counter[12]_i_7_n_0\
);
\counter[13]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[13]_i_5_n_7\,
O => \counter[13]_i_3_n_0\
);
\counter[13]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => \counter_reg_n_0_[7]\,
I1 => \counter_reg_n_0_[8]\,
I2 => \counter[13]_i_6_n_0\,
I3 => \counter[13]_i_7_n_0\,
O => \counter[13]_i_4_n_0\
);
\counter[13]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \counter_reg_n_0_[6]\,
I1 => \counter_reg_n_0_[4]\,
I2 => \counter_reg_n_0_[5]\,
I3 => \counter_reg_n_0_[13]\,
I4 => \counter_reg_n_0_[9]\,
I5 => \counter_reg_n_0_[0]\,
O => \counter[13]_i_6_n_0\
);
\counter[13]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \counter_reg_n_0_[10]\,
I1 => \counter_reg_n_0_[12]\,
I2 => \counter_reg_n_0_[11]\,
I3 => \counter_reg_n_0_[2]\,
I4 => \counter_reg_n_0_[3]\,
I5 => \counter_reg_n_0_[1]\,
O => \counter[13]_i_7_n_0\
);
\counter[13]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[13]\,
O => \counter[13]_i_8_n_0\
);
\counter[16]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[16]\,
O => \counter[16]_i_2_n_0\
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[15]\,
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[14]\,
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[13]__0_n_0\,
O => \counter[16]_i_5_n_0\
);
\counter[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \g0_b0__0_i_1_n_7\,
O => \counter[1]_i_1_n_0\
);
\counter[20]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[20]\,
O => \counter[20]_i_2_n_0\
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[19]\,
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[18]\,
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[17]\,
O => \counter[20]_i_5_n_0\
);
\counter[22]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[22]_i_3_n_3\,
O => \counter[22]_i_1_n_0\
);
\counter[22]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \counter_reg_n_0_[18]\,
I1 => \counter_reg_n_0_[19]\,
O => \counter[22]_i_10_n_0\
);
\counter[22]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[14]\,
I1 => \counter_reg_n_0_[15]\,
O => \counter[22]_i_11_n_0\
);
\counter[22]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[20]\,
I1 => \counter_reg_n_0_[21]\,
O => \counter[22]_i_12_n_0\
);
\counter[22]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg_n_0_[18]\,
I1 => \counter_reg_n_0_[19]\,
O => \counter[22]_i_13_n_0\
);
\counter[22]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[16]\,
I1 => \counter_reg_n_0_[17]\,
O => \counter[22]_i_14_n_0\
);
\counter[22]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[14]\,
I1 => \counter_reg_n_0_[15]\,
O => \counter[22]_i_15_n_0\
);
\counter[22]_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[11]__0_n_0\,
O => \counter[22]_i_16_n_0\
);
\counter[22]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \counter_reg[8]__0_n_0\,
I1 => \counter_reg[9]__0_n_0\,
O => \counter[22]_i_17_n_0\
);
\counter[22]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[6]__0_n_0\,
I1 => \counter_reg[7]__0_n_0\,
O => \counter[22]_i_18_n_0\
);
\counter[22]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg[12]__0_n_0\,
I1 => \counter_reg[13]__0_n_0\,
O => \counter[22]_i_19_n_0\
);
\counter[22]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[11]__0_n_0\,
I1 => \counter_reg[10]__0_n_0\,
O => \counter[22]_i_20_n_0\
);
\counter[22]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \counter_reg[8]__0_n_0\,
I1 => \counter_reg[9]__0_n_0\,
O => \counter[22]_i_21_n_0\
);
\counter[22]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[6]__0_n_0\,
I1 => \counter_reg[7]__0_n_0\,
O => \counter[22]_i_22_n_0\
);
\counter[22]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[22]\,
O => \counter[22]_i_4_n_0\
);
\counter[22]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[21]\,
O => \counter[22]_i_5_n_0\
);
\counter[22]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[22]\,
O => \counter[22]_i_7_n_0\
);
\counter[22]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[22]\,
O => \counter[22]_i_8_n_0\
);
\counter[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \g0_b0__0_i_1_n_6\,
O => \counter[2]_i_1_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \g0_b0__0_i_1_n_5\,
O => \counter[3]_i_1_n_0\
);
\counter[4]__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[4]__0_n_0\,
O => \counter[4]__0_i_2_n_0\
);
\counter[4]__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[3]__0_n_0\,
O => \counter[4]__0_i_3_n_0\
);
\counter[4]__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[2]__0_n_0\,
O => \counter[4]__0_i_4_n_0\
);
\counter[4]__0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[1]__0_n_0\,
O => \counter[4]__0_i_5_n_0\
);
\counter[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \g0_b0__0_i_1_n_4\,
O => \counter[4]_i_1_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[8]_i_2_n_7\,
O => \counter[5]_i_1_n_0\
);
\counter[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[8]_i_2_n_6\,
O => \counter[6]_i_1_n_0\
);
\counter[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[8]_i_2_n_5\,
O => \counter[7]_i_1_n_0\
);
\counter[8]__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[8]__0_n_0\,
O => \counter[8]__0_i_2_n_0\
);
\counter[8]__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[7]__0_n_0\,
O => \counter[8]__0_i_3_n_0\
);
\counter[8]__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[6]__0_n_0\,
O => \counter[8]__0_i_4_n_0\
);
\counter[8]__0_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[5]__0_n_0\,
O => \counter[8]__0_i_5_n_0\
);
\counter[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCC40CC4"
)
port map (
I0 => \g0_b0__0_i_2_n_0\,
I1 => \counter_reg[8]_i_2_n_4\,
I2 => current_s(1),
I3 => current_s(0),
I4 => \counter[13]_i_4_n_0\,
O => \counter[8]_i_1_n_0\
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[8]\,
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[7]\,
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[6]\,
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[5]\,
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDAF0000"
)
port map (
I0 => current_s(0),
I1 => \counter[13]_i_4_n_0\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => current_s(1),
I4 => \counter_reg[12]_i_3_n_7\,
O => \counter[9]_i_1_n_0\
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[0]_i_1_n_0\,
Q => \counter_reg_n_0_[0]\,
R => keyboard0_n_4
);
\counter_reg[0]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter[0]__0_i_1_n_0\,
Q => \counter_reg[0]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[10]_i_1_n_0\,
Q => \counter_reg_n_0_[10]\,
R => keyboard0_n_3
);
\counter_reg[10]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_6\,
Q => \counter_reg[10]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[11]_i_1_n_0\,
Q => \counter_reg_n_0_[11]\,
R => keyboard0_n_4
);
\counter_reg[11]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_5\,
Q => \counter_reg[11]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[12]_i_2_n_0\,
Q => \counter_reg_n_0_[12]\,
R => keyboard0_n_4
);
\counter_reg[12]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_4\,
Q => \counter_reg[12]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[12]__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]__0_i_1_n_0\,
CO(3) => \counter_reg[12]__0_i_1_n_0\,
CO(2) => \counter_reg[12]__0_i_1_n_1\,
CO(1) => \counter_reg[12]__0_i_1_n_2\,
CO(0) => \counter_reg[12]__0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]__0_i_1_n_4\,
O(2) => \counter_reg[12]__0_i_1_n_5\,
O(1) => \counter_reg[12]__0_i_1_n_6\,
O(0) => \counter_reg[12]__0_i_1_n_7\,
S(3) => \counter[12]__0_i_2_n_0\,
S(2) => \counter[12]__0_i_3_n_0\,
S(1) => \counter[12]__0_i_4_n_0\,
S(0) => \counter[12]__0_i_5_n_0\
);
\counter_reg[12]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_3_n_0\,
CO(2) => \counter_reg[12]_i_3_n_1\,
CO(1) => \counter_reg[12]_i_3_n_2\,
CO(0) => \counter_reg[12]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_3_n_4\,
O(2) => \counter_reg[12]_i_3_n_5\,
O(1) => \counter_reg[12]_i_3_n_6\,
O(0) => \counter_reg[12]_i_3_n_7\,
S(3) => \counter[12]_i_4_n_0\,
S(2) => \counter[12]_i_5_n_0\,
S(1) => \counter[12]_i_6_n_0\,
S(0) => \counter[12]_i_7_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[13]_i_3_n_0\,
Q => \counter_reg_n_0_[13]\,
R => keyboard0_n_3
);
\counter_reg[13]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_7\,
Q => \counter_reg[13]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[13]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_3_n_0\,
CO(3 downto 0) => \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_counter_reg[13]_i_5_O_UNCONNECTED\(3 downto 1),
O(0) => \counter_reg[13]_i_5_n_7\,
S(3 downto 1) => B"000",
S(0) => \counter[13]_i_8_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_6\,
Q => \counter_reg_n_0_[14]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_5\,
Q => \counter_reg_n_0_[15]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[16]_i_1_n_4\,
Q => \counter_reg_n_0_[16]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]__0_i_1_n_0\,
CO(3) => \counter_reg[16]_i_1_n_0\,
CO(2) => \counter_reg[16]_i_1_n_1\,
CO(1) => \counter_reg[16]_i_1_n_2\,
CO(0) => \counter_reg[16]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_1_n_4\,
O(2) => \counter_reg[16]_i_1_n_5\,
O(1) => \counter_reg[16]_i_1_n_6\,
O(0) => \counter_reg[16]_i_1_n_7\,
S(3) => \counter[16]_i_2_n_0\,
S(2) => \counter[16]_i_3_n_0\,
S(1) => \counter[16]_i_4_n_0\,
S(0) => \counter[16]_i_5_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_7\,
Q => \counter_reg_n_0_[17]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_6\,
Q => \counter_reg_n_0_[18]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_5\,
Q => \counter_reg_n_0_[19]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[1]_i_1_n_0\,
Q => \counter_reg_n_0_[1]\,
R => keyboard0_n_3
);
\counter_reg[1]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_7\,
Q => \counter_reg[1]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[20]_i_1_n_4\,
Q => \counter_reg_n_0_[20]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_1_n_0\,
CO(3) => \counter_reg[20]_i_1_n_0\,
CO(2) => \counter_reg[20]_i_1_n_1\,
CO(1) => \counter_reg[20]_i_1_n_2\,
CO(0) => \counter_reg[20]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_1_n_4\,
O(2) => \counter_reg[20]_i_1_n_5\,
O(1) => \counter_reg[20]_i_1_n_6\,
O(0) => \counter_reg[20]_i_1_n_7\,
S(3) => \counter[20]_i_2_n_0\,
S(2) => \counter[20]_i_3_n_0\,
S(1) => \counter[20]_i_4_n_0\,
S(0) => \counter[20]_i_5_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[22]_i_2_n_7\,
Q => \counter_reg_n_0_[21]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[22]_i_2_n_6\,
Q => \counter_reg_n_0_[22]\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[22]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_1_n_0\,
CO(3 downto 1) => \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\(3 downto 1),
CO(0) => \counter_reg[22]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_counter_reg[22]_i_2_O_UNCONNECTED\(3 downto 2),
O(1) => \counter_reg[22]_i_2_n_6\,
O(0) => \counter_reg[22]_i_2_n_7\,
S(3 downto 2) => B"00",
S(1) => \counter[22]_i_4_n_0\,
S(0) => \counter[22]_i_5_n_0\
);
\counter_reg[22]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[22]_i_6_n_0\,
CO(3 downto 1) => \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \counter_reg[22]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \counter[22]_i_7_n_0\,
O(3 downto 0) => \NLW_counter_reg[22]_i_3_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \counter[22]_i_8_n_0\
);
\counter_reg[22]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[22]_i_9_n_0\,
CO(3) => \counter_reg[22]_i_6_n_0\,
CO(2) => \counter_reg[22]_i_6_n_1\,
CO(1) => \counter_reg[22]_i_6_n_2\,
CO(0) => \counter_reg[22]_i_6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \counter[22]_i_10_n_0\,
DI(1) => '0',
DI(0) => \counter[22]_i_11_n_0\,
O(3 downto 0) => \NLW_counter_reg[22]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \counter[22]_i_12_n_0\,
S(2) => \counter[22]_i_13_n_0\,
S(1) => \counter[22]_i_14_n_0\,
S(0) => \counter[22]_i_15_n_0\
);
\counter_reg[22]_i_9\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[22]_i_9_n_0\,
CO(2) => \counter_reg[22]_i_9_n_1\,
CO(1) => \counter_reg[22]_i_9_n_2\,
CO(0) => \counter_reg[22]_i_9_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \counter[22]_i_16_n_0\,
DI(1) => \counter[22]_i_17_n_0\,
DI(0) => \counter[22]_i_18_n_0\,
O(3 downto 0) => \NLW_counter_reg[22]_i_9_O_UNCONNECTED\(3 downto 0),
S(3) => \counter[22]_i_19_n_0\,
S(2) => \counter[22]_i_20_n_0\,
S(1) => \counter[22]_i_21_n_0\,
S(0) => \counter[22]_i_22_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[2]_i_1_n_0\,
Q => \counter_reg_n_0_[2]\,
R => keyboard0_n_3
);
\counter_reg[2]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_6\,
Q => \counter_reg[2]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[3]_i_1_n_0\,
Q => \counter_reg_n_0_[3]\,
R => keyboard0_n_4
);
\counter_reg[3]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_5\,
Q => \counter_reg[3]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[4]_i_1_n_0\,
Q => \counter_reg_n_0_[4]\,
R => keyboard0_n_3
);
\counter_reg[4]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[4]__0_i_1_n_4\,
Q => \counter_reg[4]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[4]__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]__0_i_1_n_0\,
CO(2) => \counter_reg[4]__0_i_1_n_1\,
CO(1) => \counter_reg[4]__0_i_1_n_2\,
CO(0) => \counter_reg[4]__0_i_1_n_3\,
CYINIT => \counter_reg[0]__0_n_0\,
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]__0_i_1_n_4\,
O(2) => \counter_reg[4]__0_i_1_n_5\,
O(1) => \counter_reg[4]__0_i_1_n_6\,
O(0) => \counter_reg[4]__0_i_1_n_7\,
S(3) => \counter[4]__0_i_2_n_0\,
S(2) => \counter[4]__0_i_3_n_0\,
S(1) => \counter[4]__0_i_4_n_0\,
S(0) => \counter[4]__0_i_5_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[5]_i_1_n_0\,
Q => \counter_reg_n_0_[5]\,
R => keyboard0_n_3
);
\counter_reg[5]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_7\,
Q => \counter_reg[5]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[6]_i_1_n_0\,
Q => \counter_reg_n_0_[6]\,
R => keyboard0_n_3
);
\counter_reg[6]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_6\,
Q => \counter_reg[6]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[7]_i_1_n_0\,
Q => \counter_reg_n_0_[7]\,
R => keyboard0_n_3
);
\counter_reg[7]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_5\,
Q => \counter_reg[7]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[8]_i_1_n_0\,
Q => \counter_reg_n_0_[8]\,
R => keyboard0_n_3
);
\counter_reg[8]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[8]__0_i_1_n_4\,
Q => \counter_reg[8]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\counter_reg[8]__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]__0_i_1_n_0\,
CO(3) => \counter_reg[8]__0_i_1_n_0\,
CO(2) => \counter_reg[8]__0_i_1_n_1\,
CO(1) => \counter_reg[8]__0_i_1_n_2\,
CO(0) => \counter_reg[8]__0_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]__0_i_1_n_4\,
O(2) => \counter_reg[8]__0_i_1_n_5\,
O(1) => \counter_reg[8]__0_i_1_n_6\,
O(0) => \counter_reg[8]__0_i_1_n_7\,
S(3) => \counter[8]__0_i_2_n_0\,
S(2) => \counter[8]__0_i_3_n_0\,
S(1) => \counter[8]__0_i_4_n_0\,
S(0) => \counter[8]__0_i_5_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \g0_b0__0_i_1_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => \counter[9]_i_1_n_0\,
Q => \counter_reg_n_0_[9]\,
R => keyboard0_n_3
);
\counter_reg[9]__0\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk10M,
CE => '1',
D => \counter_reg[12]__0_i_1_n_7\,
Q => \counter_reg[9]__0_n_0\,
R => \counter[22]_i_1_n_0\
);
\current_s_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => next_s(0),
Q => current_s(0),
R => '0'
);
\current_s_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => next_s(1),
Q => current_s(1),
R => '0'
);
\fb_in_addr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9792"
)
port map (
I0 => current_s(0),
I1 => \counter_reg_n_0_[0]\,
I2 => current_s(1),
I3 => fb_in_addr0(0),
O => fb_in_addr(0)
);
\fb_in_addr[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[10]\,
I1 => current_s(0),
I2 => \counter_reg[12]_i_3_n_6\,
I3 => current_s(1),
I4 => fb_in_addr0(10),
O => fb_in_addr(10)
);
\fb_in_addr[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[11]\,
I1 => current_s(0),
I2 => \counter_reg[12]_i_3_n_5\,
I3 => current_s(1),
I4 => fb_in_addr0(11),
O => fb_in_addr(11)
);
\fb_in_addr[11]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[12]_i_3_n_5\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[11]_i_3_n_0\
);
\fb_in_addr[11]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[12]_i_3_n_6\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[11]_i_4_n_0\
);
\fb_in_addr[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[8]_i_2_n_4\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[11]_i_5_n_0\
);
\fb_in_addr[11]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g0_b0__0_i_2_n_0\,
I1 => \counter_reg[12]_i_3_n_5\,
O => \fb_in_addr[11]_i_6_n_0\
);
\fb_in_addr[11]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g0_b0__0_i_2_n_0\,
I1 => \counter_reg[12]_i_3_n_6\,
O => \fb_in_addr[11]_i_7_n_0\
);
\fb_in_addr[11]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[12]_i_3_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[11]_i_8_n_0\
);
\fb_in_addr[11]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g0_b0__0_i_2_n_0\,
I1 => \counter_reg[8]_i_2_n_4\,
O => \fb_in_addr[11]_i_9_n_0\
);
\fb_in_addr[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[12]\,
I1 => current_s(0),
I2 => \counter_reg[12]_i_3_n_4\,
I3 => current_s(1),
I4 => fb_in_addr0(12),
O => fb_in_addr(12)
);
\fb_in_addr[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[13]\,
I1 => current_s(0),
I2 => \counter_reg[13]_i_5_n_7\,
I3 => current_s(1),
I4 => fb_in_addr0(13),
O => fb_in_addr(13)
);
\fb_in_addr[13]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[13]_i_5_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[13]_i_3_n_0\
);
\fb_in_addr[13]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[12]_i_3_n_4\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[13]_i_4_n_0\
);
\fb_in_addr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[1]\,
I1 => current_s(0),
I2 => \g0_b0__0_i_1_n_7\,
I3 => current_s(1),
I4 => fb_in_addr0(1),
O => fb_in_addr(1)
);
\fb_in_addr[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[2]\,
I1 => current_s(0),
I2 => \g0_b0__0_i_1_n_6\,
I3 => current_s(1),
I4 => fb_in_addr0(2),
O => fb_in_addr(2)
);
\fb_in_addr[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[3]\,
I1 => current_s(0),
I2 => \g0_b0__0_i_1_n_5\,
I3 => current_s(1),
I4 => fb_in_addr0(3),
O => fb_in_addr(3)
);
\fb_in_addr[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[3]_i_3_n_0\
);
\fb_in_addr[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \g0_b0__0_i_1_n_5\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[3]_i_4_n_0\
);
\fb_in_addr[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \g0_b0__0_i_1_n_6\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[3]_i_5_n_0\
);
\fb_in_addr[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g0_b0__0_i_2_n_0\,
I1 => \g0_b0__0_i_1_n_7\,
O => \fb_in_addr[3]_i_6_n_0\
);
\fb_in_addr[3]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[3]_i_7_n_0\
);
\fb_in_addr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[4]\,
I1 => current_s(0),
I2 => \g0_b0__0_i_1_n_4\,
I3 => current_s(1),
I4 => fb_in_addr0(4),
O => fb_in_addr(4)
);
\fb_in_addr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[5]\,
I1 => current_s(0),
I2 => \counter_reg[8]_i_2_n_7\,
I3 => current_s(1),
I4 => fb_in_addr0(5),
O => fb_in_addr(5)
);
\fb_in_addr[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[6]\,
I1 => current_s(0),
I2 => \counter_reg[8]_i_2_n_6\,
I3 => current_s(1),
I4 => fb_in_addr0(6),
O => fb_in_addr(6)
);
\fb_in_addr[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[7]\,
I1 => current_s(0),
I2 => \counter_reg[8]_i_2_n_5\,
I3 => current_s(1),
I4 => fb_in_addr0(7),
O => fb_in_addr(7)
);
\fb_in_addr[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[8]_i_2_n_6\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[7]_i_3_n_0\
);
\fb_in_addr[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[8]_i_2_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[7]_i_4_n_0\
);
\fb_in_addr[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg[8]_i_2_n_5\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[7]_i_5_n_0\
);
\fb_in_addr[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g0_b0__0_i_2_n_0\,
I1 => \counter_reg[8]_i_2_n_6\,
O => \fb_in_addr[7]_i_6_n_0\
);
\fb_in_addr[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \g0_b0__0_i_2_n_0\,
I1 => \counter_reg[8]_i_2_n_7\,
O => \fb_in_addr[7]_i_7_n_0\
);
\fb_in_addr[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \g0_b0__0_i_1_n_4\,
I1 => \g0_b0__0_i_2_n_0\,
O => \fb_in_addr[7]_i_8_n_0\
);
\fb_in_addr[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[8]\,
I1 => current_s(0),
I2 => \counter_reg[8]_i_2_n_4\,
I3 => current_s(1),
I4 => fb_in_addr0(8),
O => fb_in_addr(8)
);
\fb_in_addr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8F3B8C0"
)
port map (
I0 => \counter_reg_n_0_[9]\,
I1 => current_s(0),
I2 => \counter_reg[12]_i_3_n_7\,
I3 => current_s(1),
I4 => fb_in_addr0(9),
O => fb_in_addr(9)
);
\fb_in_addr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(0),
Q => addra(0),
R => '0'
);
\fb_in_addr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(10),
Q => addra(10),
R => '0'
);
\fb_in_addr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(11),
Q => addra(11),
R => '0'
);
\fb_in_addr_reg[11]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \fb_in_addr_reg[7]_i_2_n_0\,
CO(3) => \fb_in_addr_reg[11]_i_2_n_0\,
CO(2) => \fb_in_addr_reg[11]_i_2_n_1\,
CO(1) => \fb_in_addr_reg[11]_i_2_n_2\,
CO(0) => \fb_in_addr_reg[11]_i_2_n_3\,
CYINIT => '0',
DI(3) => \fb_in_addr[11]_i_3_n_0\,
DI(2) => \fb_in_addr[11]_i_4_n_0\,
DI(1) => '0',
DI(0) => \fb_in_addr[11]_i_5_n_0\,
O(3 downto 0) => fb_in_addr0(11 downto 8),
S(3) => \fb_in_addr[11]_i_6_n_0\,
S(2) => \fb_in_addr[11]_i_7_n_0\,
S(1) => \fb_in_addr[11]_i_8_n_0\,
S(0) => \fb_in_addr[11]_i_9_n_0\
);
\fb_in_addr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(12),
Q => addra(12),
R => '0'
);
\fb_in_addr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(13),
Q => addra(13),
R => '0'
);
\fb_in_addr_reg[13]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \fb_in_addr_reg[11]_i_2_n_0\,
CO(3 downto 1) => \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\(3 downto 1),
CO(0) => \fb_in_addr_reg[13]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 2) => \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => fb_in_addr0(13 downto 12),
S(3 downto 2) => B"00",
S(1) => \fb_in_addr[13]_i_3_n_0\,
S(0) => \fb_in_addr[13]_i_4_n_0\
);
\fb_in_addr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(1),
Q => addra(1),
R => '0'
);
\fb_in_addr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(2),
Q => addra(2),
R => '0'
);
\fb_in_addr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(3),
Q => addra(3),
R => '0'
);
\fb_in_addr_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \fb_in_addr_reg[3]_i_2_n_0\,
CO(2) => \fb_in_addr_reg[3]_i_2_n_1\,
CO(1) => \fb_in_addr_reg[3]_i_2_n_2\,
CO(0) => \fb_in_addr_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \fb_in_addr[3]_i_3_n_0\,
DI(0) => '0',
O(3 downto 0) => fb_in_addr0(3 downto 0),
S(3) => \fb_in_addr[3]_i_4_n_0\,
S(2) => \fb_in_addr[3]_i_5_n_0\,
S(1) => \fb_in_addr[3]_i_6_n_0\,
S(0) => \fb_in_addr[3]_i_7_n_0\
);
\fb_in_addr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(4),
Q => addra(4),
R => '0'
);
\fb_in_addr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(5),
Q => addra(5),
R => '0'
);
\fb_in_addr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(6),
Q => addra(6),
R => '0'
);
\fb_in_addr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(7),
Q => addra(7),
R => '0'
);
\fb_in_addr_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \fb_in_addr_reg[3]_i_2_n_0\,
CO(3) => \fb_in_addr_reg[7]_i_2_n_0\,
CO(2) => \fb_in_addr_reg[7]_i_2_n_1\,
CO(1) => \fb_in_addr_reg[7]_i_2_n_2\,
CO(0) => \fb_in_addr_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \fb_in_addr[7]_i_3_n_0\,
DI(1) => \fb_in_addr[7]_i_4_n_0\,
DI(0) => '0',
O(3 downto 0) => fb_in_addr0(7 downto 4),
S(3) => \fb_in_addr[7]_i_5_n_0\,
S(2) => \fb_in_addr[7]_i_6_n_0\,
S(1) => \fb_in_addr[7]_i_7_n_0\,
S(0) => \fb_in_addr[7]_i_8_n_0\
);
\fb_in_addr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(8),
Q => addra(8),
R => '0'
);
\fb_in_addr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_addr(9),
Q => addra(9),
R => '0'
);
\fb_in_dat[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => \fb_in_dat[5]_i_2_n_0\,
I1 => current_s(0),
I2 => current_s(1),
O => \fb_in_dat[4]_i_1_n_0\
);
\fb_in_dat[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02020222"
)
port map (
I0 => \fb_in_dat[5]_i_3_n_0\,
I1 => \fb_in_dat[5]_i_4_n_0\,
I2 => \g0_b0__0_i_1_n_5\,
I3 => \g0_b0__0_i_1_n_6\,
I4 => \g0_b0__0_i_1_n_7\,
O => \fb_in_dat[5]_i_2_n_0\
);
\fb_in_dat[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \counter_reg[8]_i_2_n_7\,
I1 => \g0_b0__0_i_1_n_4\,
I2 => \counter_reg[8]_i_2_n_4\,
I3 => \counter_reg[12]_i_3_n_4\,
I4 => \counter_reg[12]_i_3_n_6\,
I5 => \counter_reg[12]_i_3_n_5\,
O => \fb_in_dat[5]_i_3_n_0\
);
\fb_in_dat[5]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \counter_reg[8]_i_2_n_5\,
I1 => \counter_reg[8]_i_2_n_6\,
I2 => \counter_reg[13]_i_5_n_7\,
I3 => \counter_reg[12]_i_3_n_7\,
O => \fb_in_dat[5]_i_4_n_0\
);
\fb_in_dat[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => clk_1_reg_n_0,
I1 => current_s(1),
I2 => current_s(0),
O => fb_in_dat(7)
);
\fb_in_dat_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => keyboard0_n_5,
Q => dina(0),
R => \fb_in_dat[4]_i_1_n_0\
);
\fb_in_dat_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => keyboard0_n_6,
Q => dina(1),
R => \fb_in_dat[4]_i_1_n_0\
);
\fb_in_dat_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => keyboard0_n_7,
Q => dina(2),
R => \fb_in_dat[4]_i_1_n_0\
);
\fb_in_dat_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => keyboard0_n_8,
Q => dina(3),
R => \fb_in_dat[4]_i_1_n_0\
);
\fb_in_dat_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => keyboard0_n_9,
Q => dina(4),
R => \fb_in_dat[4]_i_1_n_0\
);
\fb_in_dat_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_dat(5),
Q => dina(5),
R => '0'
);
\fb_in_dat_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_dat(6),
Q => dina(6),
R => '0'
);
\fb_in_dat_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => keyboard0_n_10,
D => fb_in_dat(7),
Q => dina(7),
R => '0'
);
frameBuffer0: entity work.FrameBuffer
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => B"00000000000000",
clka => clk_BUFG,
clkb => clk108M,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => '1'
);
\g0_b0__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DE0123DEFCFE20"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
I2 => \counter_reg_n_0_[0]\,
I3 => \g0_b0__0_i_3_n_0\,
I4 => \g0_b0__0_i_4_n_0\,
I5 => \g0_b0__0_i_5_n_0\,
O => \g0_b0__0_n_0\
);
\g0_b0__0_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \g0_b0__0_i_1_n_0\,
CO(2) => \g0_b0__0_i_1_n_1\,
CO(1) => \g0_b0__0_i_1_n_2\,
CO(0) => \g0_b0__0_i_1_n_3\,
CYINIT => \counter_reg_n_0_[0]\,
DI(3 downto 0) => B"0000",
O(3) => \g0_b0__0_i_1_n_4\,
O(2) => \g0_b0__0_i_1_n_5\,
O(1) => \g0_b0__0_i_1_n_6\,
O(0) => \g0_b0__0_i_1_n_7\,
S(3) => \g0_b0__0_i_6_n_0\,
S(2) => \g0_b0__0_i_7_n_0\,
S(1) => \g0_b0__0_i_8_n_0\,
S(0) => \g0_b0__0_i_9_n_0\
);
\g0_b0__0_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \counter_reg_n_0_[12]\,
I1 => \counter_reg_n_0_[11]\,
O => \g0_b0__0_i_10_n_0\
);
\g0_b0__0_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF80"
)
port map (
I0 => \counter_reg_n_0_[2]\,
I1 => \counter_reg_n_0_[4]\,
I2 => \counter_reg_n_0_[3]\,
I3 => \counter_reg_n_0_[13]\,
I4 => \counter_reg_n_0_[10]\,
I5 => \counter_reg_n_0_[5]\,
O => \g0_b0__0_i_11_n_0\
);
\g0_b0__0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \counter_reg_n_0_[7]\,
I1 => \counter_reg_n_0_[6]\,
I2 => \counter_reg_n_0_[8]\,
I3 => \counter_reg_n_0_[9]\,
I4 => \g0_b0__0_i_10_n_0\,
I5 => \g0_b0__0_i_11_n_0\,
O => \g0_b0__0_i_2_n_0\
);
\g0_b0__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0B04"
)
port map (
I0 => \counter_reg_n_0_[0]\,
I1 => \g0_b0__0_i_1_n_7\,
I2 => \g0_b0__0_i_2_n_0\,
I3 => \g0_b0__0_i_1_n_6\,
O => \g0_b0__0_i_3_n_0\
);
\g0_b0__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"009A00AA"
)
port map (
I0 => \g0_b0__0_i_1_n_5\,
I1 => \counter_reg_n_0_[0]\,
I2 => \g0_b0__0_i_1_n_7\,
I3 => \g0_b0__0_i_2_n_0\,
I4 => \g0_b0__0_i_1_n_6\,
O => \g0_b0__0_i_4_n_0\
);
\g0_b0__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF00FF00200000"
)
port map (
I0 => \g0_b0__0_i_1_n_5\,
I1 => \counter_reg_n_0_[0]\,
I2 => \g0_b0__0_i_1_n_7\,
I3 => \g0_b0__0_i_2_n_0\,
I4 => \g0_b0__0_i_1_n_6\,
I5 => \g0_b0__0_i_1_n_4\,
O => \g0_b0__0_i_5_n_0\
);
\g0_b0__0_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[4]\,
O => \g0_b0__0_i_6_n_0\
);
\g0_b0__0_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[3]\,
O => \g0_b0__0_i_7_n_0\
);
\g0_b0__0_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[2]\,
O => \g0_b0__0_i_8_n_0\
);
\g0_b0__0_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \counter_reg_n_0_[1]\,
O => \g0_b0__0_i_9_n_0\
);
\g0_b1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"022122230022DE01"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
I2 => \counter_reg_n_0_[0]\,
I3 => \g0_b0__0_i_3_n_0\,
I4 => \g0_b0__0_i_4_n_0\,
I5 => \g0_b0__0_i_5_n_0\,
O => \g0_b1__0_n_0\
);
\g0_b2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FFFE2222020020"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
I2 => \counter_reg_n_0_[0]\,
I3 => \g0_b0__0_i_3_n_0\,
I4 => \g0_b0__0_i_4_n_0\,
I5 => \g0_b0__0_i_5_n_0\,
O => \g0_b2__0_n_0\
);
\g0_b3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02212322DCFE0000"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
I2 => \counter_reg_n_0_[0]\,
I3 => \g0_b0__0_i_3_n_0\,
I4 => \g0_b0__0_i_4_n_0\,
I5 => \g0_b0__0_i_5_n_0\,
O => \g0_b3__0_n_0\
);
\g0_b4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002DC00FCDCDEDD"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
I2 => \counter_reg_n_0_[0]\,
I3 => \g0_b0__0_i_3_n_0\,
I4 => \g0_b0__0_i_4_n_0\,
I5 => \g0_b0__0_i_5_n_0\,
O => \g0_b4__0_n_0\
);
\g0_b5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FFFFFFFFFFFF21"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
I2 => \counter_reg_n_0_[0]\,
I3 => \g0_b0__0_i_3_n_0\,
I4 => \g0_b0__0_i_4_n_0\,
I5 => \g0_b0__0_i_5_n_0\,
O => \g0_b5__0_n_0\
);
\g0_b6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DEFF23FEFEFEFD"
)
port map (
I0 => \g0_b0__0_i_1_n_7\,
I1 => \g0_b0__0_i_2_n_0\,
I2 => \counter_reg_n_0_[0]\,
I3 => \g0_b0__0_i_3_n_0\,
I4 => \g0_b0__0_i_4_n_0\,
I5 => \g0_b0__0_i_5_n_0\,
O => \g0_b6__0_n_0\
);
keyboard0: entity work.ps2_keyboard_to_ascii
port map (
D(1 downto 0) => next_s(1 downto 0),
E(0) => keyboard0_n_10,
O(2) => \g0_b0__0_i_1_n_5\,
O(1) => \g0_b0__0_i_1_n_6\,
O(0) => \g0_b0__0_i_1_n_7\,
PS2Clk_IBUF => PS2Clk_IBUF,
PS2Data_IBUF => PS2Data_IBUF,
Q(1 downto 0) => current_s(1 downto 0),
SR(1) => keyboard0_n_3,
SR(0) => keyboard0_n_4,
clk_BUFG => clk_BUFG,
\counter_reg[0]\ => \g0_b5__0_n_0\,
\counter_reg[0]_0\ => \fb_in_dat[5]_i_2_n_0\,
\counter_reg[0]_1\ => \g0_b6__0_n_0\,
\counter_reg[0]_2\(0) => \counter_reg_n_0_[0]\,
\counter_reg[0]_3\ => \g0_b0__0_n_0\,
\counter_reg[0]_4\ => \g0_b1__0_n_0\,
\counter_reg[0]_5\ => \g0_b2__0_n_0\,
\counter_reg[0]_6\ => \g0_b3__0_n_0\,
\counter_reg[0]_7\ => \g0_b4__0_n_0\,
\current_s_reg[0]\ => \next_s[1]_i_2_n_0\,
\fb_in_dat_reg[0]\ => keyboard0_n_5,
\fb_in_dat_reg[1]\ => keyboard0_n_6,
\fb_in_dat_reg[2]\ => keyboard0_n_7,
\fb_in_dat_reg[3]\ => keyboard0_n_8,
\fb_in_dat_reg[4]\ => keyboard0_n_9,
\fb_in_dat_reg[6]\(1 downto 0) => fb_in_dat(6 downto 5),
\next_s_reg[0]\ => keyboard0_n_0,
\next_s_reg[1]\ => keyboard0_n_11
);
\led_OBUF[0]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(0),
T => '1'
);
\led_OBUF[10]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(10),
T => '1'
);
\led_OBUF[11]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(11),
T => '1'
);
\led_OBUF[12]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(12),
T => '1'
);
\led_OBUF[13]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(13),
T => '1'
);
\led_OBUF[14]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(14),
T => '1'
);
\led_OBUF[15]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(15),
T => '1'
);
\led_OBUF[1]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(1),
T => '1'
);
\led_OBUF[2]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(2),
T => '1'
);
\led_OBUF[3]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(3),
T => '1'
);
\led_OBUF[4]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(4),
T => '1'
);
\led_OBUF[5]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(5),
T => '1'
);
\led_OBUF[6]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(6),
T => '1'
);
\led_OBUF[7]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(7),
T => '1'
);
\led_OBUF[8]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(8),
T => '1'
);
\led_OBUF[9]_inst\: unisim.vcomponents.OBUFT
port map (
I => '0',
O => led(9),
T => '1'
);
\next_s[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => current_s(0),
I1 => current_s(1),
I2 => \next_s[1]_i_3_n_0\,
I3 => \next_s[1]_i_4_n_0\,
I4 => \next_s[1]_i_5_n_0\,
O => \next_s[1]_i_2_n_0\
);
\next_s[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \g0_b0__0_i_1_n_5\,
I1 => \counter_reg_n_0_[0]\,
I2 => \counter_reg[13]_i_5_n_7\,
I3 => \g0_b0__0_i_1_n_7\,
O => \next_s[1]_i_3_n_0\
);
\next_s[1]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \counter_reg[8]_i_2_n_5\,
I1 => \counter_reg[12]_i_3_n_4\,
I2 => \counter_reg[8]_i_2_n_4\,
I3 => \counter_reg[8]_i_2_n_6\,
O => \next_s[1]_i_4_n_0\
);
\next_s[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFFFFFFFFFF"
)
port map (
I0 => \counter_reg[8]_i_2_n_7\,
I1 => \g0_b0__0_i_1_n_4\,
I2 => \counter_reg[12]_i_3_n_5\,
I3 => \counter_reg[12]_i_3_n_7\,
I4 => \g0_b0__0_i_1_n_6\,
I5 => \counter_reg[12]_i_3_n_6\,
O => \next_s[1]_i_5_n_0\
);
\next_s_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => keyboard0_n_0,
Q => next_s(0),
R => '0'
);
\next_s_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_BUFG,
CE => '1',
D => keyboard0_n_11,
Q => next_s(1),
R => '0'
);
\sw[0]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[0]\,
O => \sw[0]_IBUF\
);
\sw[10]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[10]\,
O => \sw[10]_IBUF\
);
\sw[11]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[11]\,
O => \sw[11]_IBUF\
);
\sw[12]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[12]\,
O => \sw[12]_IBUF\
);
\sw[13]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[13]\,
O => \sw[13]_IBUF\
);
\sw[14]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[14]\,
O => \sw[14]_IBUF\
);
\sw[15]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[15]\,
O => \sw[15]_IBUF\
);
\sw[1]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[1]\,
O => \sw[1]_IBUF\
);
\sw[2]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[2]\,
O => \sw[2]_IBUF\
);
\sw[3]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[3]\,
O => \sw[3]_IBUF\
);
\sw[4]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[4]\,
O => \sw[4]_IBUF\
);
\sw[5]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[5]\,
O => \sw[5]_IBUF\
);
\sw[6]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[6]\,
O => \sw[6]_IBUF\
);
\sw[7]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[7]\,
O => \sw[7]_IBUF\
);
\sw[8]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[8]\,
O => \sw[8]_IBUF\
);
\sw[9]_IBUF_inst\: unisim.vcomponents.IBUF
port map (
I => \sw[9]\,
O => \sw[9]_IBUF\
);
vga0: entity work.Vga
port map (
Hsync_OBUF => Hsync_OBUF,
Vsync_OBUF => Vsync_OBUF,
clk108M => clk108M,
doutb(7 downto 0) => doutb(7 downto 0),
vgaBlue_OBUF(0) => vgaBlue_OBUF(0)
);
\vgaBlue_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(0)
);
\vgaBlue_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(1)
);
\vgaBlue_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(2)
);
\vgaBlue_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaBlue(3)
);
\vgaGreen_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(0)
);
\vgaGreen_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(1)
);
\vgaGreen_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(2)
);
\vgaGreen_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaGreen(3)
);
\vgaRed_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(0)
);
\vgaRed_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(1)
);
\vgaRed_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(2)
);
\vgaRed_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => vgaBlue_OBUF(0),
O => vgaRed(3)
);
end STRUCTURE;
|
mit
|
1628a37521130170e7ab8c0fdb7bfc2a
| 0.532098 | 2.567727 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/rom/sim/rom.vhd
| 1 | 12,029 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_arch OF rom IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF rom_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "rom.mif",
C_INIT_FILE => "rom.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 30720,
C_READ_DEPTH_A => 30720,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 30720,
C_READ_DEPTH_B => 30720,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.252613 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END rom_arch;
|
mit
|
9143e085b0cd61bb709aa28955356036
| 0.603043 | 3.208589 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lisipif_master.vhd
| 1 | 11,149 |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lisipif_master
-- Architectures: lisipif_master_rtl
-- Description:
-- The master attachment of the LIS-IPIF may be used by an IP to provide
-- a simplifed interface to the Processor Local Bus (PLB).
-- See the LIS-IPIF specification for details.
--
-- Dependencies:
--
-- Revision:
-- 7.3.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
--------------------------------------------------------------------------------
-- LIS-IPIF Master Entity Declaration
--------------------------------------------------------------------------------
entity lisipif_master is
generic (
C_NUM_WIDTH : integer := 5;
C_ARBITRATION : integer := 0;
C_EN_SRL16 : boolean := true;
C_EN_RECALC_ADDR : boolean := false; -- Not Implemented
C_EN_PIPELINING : boolean := true; -- Not Implemented
C_EN_FAST_ABORT : boolean := false -- Not Implemented
);
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
-- Read Transfer Signals
M_rdReq : in std_logic;
M_rdAccept : out std_logic;
M_rdAddr : in std_logic_vector(31 downto 0);
M_rdNum : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_rdBE : in std_logic_vector(7 downto 0);
M_rdData : out std_logic_vector(63 downto 0);
M_rdAck : out std_logic;
M_rdComp : out std_logic;
M_rdPriority : in std_logic_vector(1 downto 0);
M_rdType : in std_logic_vector(2 downto 0);
M_rdCompress : in std_logic;
M_rdGuarded : in std_logic;
M_rdLockErr : in std_logic;
M_rdRearb : out std_logic;
M_rdAbort : in std_logic;
M_rdError : out std_logic;
-- Write Transfer Signals
M_wrReq : in std_logic;
M_wrAccept : out std_logic;
M_wrAddr : in std_logic_vector(31 downto 0);
M_wrNum : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_wrBE : in std_logic_vector(7 downto 0);
M_wrData : in std_logic_vector(63 downto 0);
M_wrRdy : out std_logic;
M_wrAck : out std_logic;
M_wrComp : out std_logic;
M_wrPriority : in std_logic_vector(1 downto 0);
M_wrType : in std_logic_vector(2 downto 0);
M_wrCompress : in std_logic;
M_wrGuarded : in std_logic;
M_wrOrdered : in std_logic;
M_wrLockErr : in std_logic;
M_wrRearb : out std_logic;
M_wrAbort : in std_logic;
M_wrError : out std_logic;
-- Shared Transfer Signals
M_Error : out std_logic;
M_Lock : in std_logic;
-- PLB Signals
PLB_MAddrAck : in std_logic;
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_pendReq : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
M_request : out std_logic; -- A
M_priority : out std_logic_vector(0 to 1); -- I
M_busLock : out std_logic; -- I
M_RNW : out std_logic; -- A
M_BE : out std_logic_vector(0 to 7); -- A
M_size : out std_logic_vector(0 to 3); -- A
M_type : out std_logic_vector(0 to 2); -- I
M_MSize : out std_logic_vector(0 to 1); -- C
M_compress : out std_logic; -- I
M_guarded : out std_logic; -- I
M_ordered : out std_logic; -- I
M_lockErr : out std_logic; -- I
M_abort : out std_logic; -- A
M_ABus : out std_logic_vector(0 to 31); -- A
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_wrBurst : out std_logic; -- W
M_wrDBus : out std_logic_vector(0 to 63); -- W
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
M_rdBurst : out std_logic; -- R
PLB_MRdDBus : in std_logic_vector(0 to 63)
);
end lisipif_master;
--------------------------------------------------------------------------------
-- LIS-IPIF Master RT Level Architecture
--------------------------------------------------------------------------------
architecture lisipif_master_rtl of lisipif_master is
-- Control Signals between Arbiter and Read/Write Controller
signal rd_rdy : std_logic; -- To arb: Ready for new transfer
signal rd_init : std_logic; -- From arb: Latch new transfer
signal rd_ack : std_logic; -- From arb: Transfer ack'd by slave
signal rd_rearb : std_logic; -- From arb: Rearbitrate transfer
signal rd_retry : std_logic; -- To arb: Repeat the transfer
signal rd_abort : std_logic; -- To arb: Abort the transfer
signal wr_rdy : std_logic; -- To arb: Ready for new transfer
signal wr_init : std_logic; -- From arb: Latch new transfer
signal wr_ack : std_logic; -- From arb: Transfer ack'd by slave
signal wr_rearb : std_logic; -- From arb: Rearbitrate transfer
signal wr_retry : std_logic; -- To arb: Repeat the transfer
signal wr_abort : std_logic; -- To arb: Abort the transfer
begin
M_MSize <= "01";
-- Arbiter
arbiter_0: entity lisipif_master_v1_00_c.lipif_mst_arbiter
generic map (
C_NUM_WIDTH => C_NUM_WIDTH,
C_ARBITRATION => C_ARBITRATION,
C_EN_SRL16 => C_EN_SRL16
)
port map (
clk => PLB_Clk,
reset => PLB_Rst,
-- Control Signals to Read and Write Controller
rd_rdy_i => rd_rdy,
rd_init_o => rd_init,
rd_ack_o => rd_ack,
rd_rearb_o => rd_rearb,
rd_retry_i => rd_retry,
rd_abort_i => rd_abort,
wr_rdy_i => wr_rdy,
wr_init_o => wr_init,
wr_ack_o => wr_ack,
wr_rearb_o => wr_rearb,
wr_retry_i => wr_retry,
wr_abort_i => wr_abort,
-- LIS-IPIC Read Qualifiers
M_rdReq_i => M_rdReq,
M_rdAccept_o => M_rdAccept,
M_rdAddr_i => M_rdAddr,
M_rdNum_i => M_rdNum,
M_rdBE_i => M_rdBE,
M_rdPriority_i => M_rdPriority,
M_rdType_i => M_rdType,
M_rdCompress_i => M_rdCompress,
M_rdGuarded_i => M_rdGuarded,
M_rdLockErr_i => M_rdLockErr,
-- LIS-IPIC Write Qualifiers
M_wrReq_i => M_wrReq,
M_wrAccept_o => M_wrAccept,
M_wrAddr_i => M_wrAddr,
M_wrNum_i => M_wrNum,
M_wrBE_i => M_wrBE,
M_wrPriority_i => M_wrPriority,
M_wrType_i => M_wrType,
M_wrCompress_i => M_wrCompress,
M_wrGuarded_i => M_wrGuarded,
M_wrOrdered_i => M_wrOrdered,
M_wrLockErr_i => M_wrLockErr,
-- LIS-IPIC Shared Qualifiers
M_Error_o => M_Error,
M_Lock_i => M_Lock,
-- PLB Signals
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MErr => PLB_MErr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus
);
-- Read Controller
read_ctrl_0: entity lisipif_master_v1_00_c.lipif_mst_read
generic map (
C_NUM_WIDTH => C_NUM_WIDTH,
C_EN_SRL16 => C_EN_SRL16,
C_EN_FAST_ABORT => C_EN_FAST_ABORT
)
port map (
clk => PLB_Clk,
reset => PLB_Rst,
-- Control Signals to/from Arbiter
xfer_rdy_o => rd_rdy,
xfer_init_i => rd_init,
xfer_ack_i => rd_ack,
xfer_rearb_i => rd_rearb,
xfer_retry_o => rd_retry,
xfer_abort_o => rd_abort,
-- LIS-IPIC Transfer Signals
M_rdNum_i => M_rdNum,
M_rdRearb_o => M_rdRearb,
M_rdAbort_i => M_rdAbort,
M_rdError_o => M_rdError,
M_rdData_o => M_rdData,
M_rdAck_o => M_rdAck,
M_rdComp_o => M_rdComp,
-- PLB Signals
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdWdAddr => PLB_MRdWdAddr,
M_rdBurst => M_rdBurst,
PLB_MRdDBus => PLB_MRdDBus
);
-- Write Controller
write_ctrl_0: entity lisipif_master_v1_00_c.lipif_mst_write
generic map (
C_NUM_WIDTH => C_NUM_WIDTH,
C_EN_SRL16 => C_EN_SRL16,
C_EN_FAST_ABORT => C_EN_FAST_ABORT
)
port map (
clk => PLB_Clk,
reset => PLB_Rst,
-- Control Signals to/from Arbiter
xfer_rdy_o => wr_rdy,
xfer_init_i => wr_init,
xfer_ack_i => wr_ack,
xfer_rearb_i => wr_rearb,
xfer_retry_o => wr_retry,
xfer_abort_o => wr_abort,
-- LIS-IPIC Transfer Signals
M_wrNum_i => M_wrNum,
M_wrRearb_o => M_wrRearb,
M_wrAbort_i => M_wrAbort,
M_wrError_o => M_wrError,
M_wrData_i => M_wrData,
M_wrRdy_o => M_wrRdy,
M_wrAck_o => M_wrAck,
M_wrComp_o => M_wrComp,
-- PLB Signals
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
M_wrBurst => M_WrBurst,
M_wrDBus => M_wrDBus
);
end lisipif_master_rtl;
|
gpl-3.0
|
1089e9951a04efb239b98ad0599a7f41
| 0.469728 | 3.656609 | false | false | false | false |
five-elephants/hw-neural-sampling
|
test_sampling.vhdl
| 1 | 4,177 |
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
use ieee.math_real.all;
use work.sampling.all;
entity test_sampling is
end test_sampling;
architecture behave of test_sampling is
constant clk_period : time := 10 ns;
constant num_samplers : integer := 4;
constant num_rngs_per_sampler : integer := 16;
constant tau : integer := 20;
constant threshold : membrane_t := make_fixed(3.0,
membrane_width-1-membrane_fraction,
membrane_fraction);
constant biases : weight_array_t(1 to num_samplers) := (
make_fixed(-1.0, 2, 1),
make_fixed(-0.5, 2, 1),
make_fixed(-2.0, 2, 1),
make_fixed(-1.5, 2, 1)
);
constant weights : weight_array2_t(1 to num_samplers, 1 to num_samplers) := (
(make_fixed(0.0, 2, 1), make_fixed(1.5, 2, 1), make_fixed(1.0, 2, 1), make_fixed(-1.0, 2, 1)),
(make_fixed(1.5, 2, 1), make_fixed(0.0, 2, 1), make_fixed(1.0, 2, 1), make_fixed(-1.0, 2, 1)),
(make_fixed(1.0, 2, 1), make_fixed(1.0, 2, 1), make_fixed(0.0, 2, 1), make_fixed(0.5, 2, 1)),
(make_fixed(-1.0, 2, 1), make_fixed(-1.0, 2, 1), make_fixed(0.5, 2, 1), make_fixed(0.0, 2, 1))
);
signal clk, reset : std_ulogic;
signal clock_tick : std_ulogic;
signal systime : systime_t;
signal state_clamp_mask,
state_clamp,
state : state_array_t(1 to num_samplers);
signal membranes : membrane_array_t(1 to num_samplers);
signal fires : std_ulogic_vector(1 to num_samplers);
signal seeds : lfsr_state_array_t(1 to num_samplers*num_rngs_per_sampler);
begin
clock_generation: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
------------------------------------------------------------
-- unit under test
------------------------------------------------------------
uut: entity work.sampling_network
generic map (
num_samplers => num_samplers,
tau => tau
)
port map (
clk => clk,
reset => reset,
clock_tick => clock_tick,
systime => systime,
state => state,
membranes => membranes,
fires => fires,
seeds => seeds,
biases => biases,
weights => weights
);
------------------------------------------------------------
-- stimulus generation
------------------------------------------------------------
stimulus: process
variable l : line;
variable seed1, seed2 : positive;
variable rand : real;
variable int_rand : integer;
begin
for i in seeds'range loop
uniform(seed1, seed2, rand);
int_rand := integer(rand*(2.0**lfsr_width-1.0));
seeds(i) <= std_logic_vector(to_unsigned(int_rand, seeds(i)'length));
--seeds(i) <= std_logic_vector(to_unsigned(2**lfsr_width - i, seeds(i)'length));
end loop;
write(l, string'("biases:"));
writeline(output, l);
for i in biases'range loop
hwrite(l, std_logic_vector(biases(i)));
writeline(output, l);
end loop;
write(l, string'("weights:"));
writeline(output, l);
for i in 1 to num_samplers loop
for j in 1 to num_samplers loop
hwrite(l, std_logic_vector(weights(i,j)));
write(l, string'(" "));
end loop;
writeline(output, l);
end loop;
reset <= '1';
wait for 100 ns;
reset <= '0';
wait until rising_edge(clk);
--loop
--write(l, string'("state: "));
--write(l, std_logic_vector(state));
--writeline(output, l);
--wait until rising_edge(clock_tick);
--end loop;
wait;
end process;
------------------------------------------------------------
recorder: process
file f : text open write_mode is "trace";
variable ln : line;
begin
loop
wait until rising_edge(clock_tick);
for i in state'range loop
write(ln, state(i));
write(ln, string'(" "));
write(ln, fires(i));
write(ln, string'(" "));
hwrite(ln, std_logic_vector(membranes(i)));
write(ln, string'(" "));
end loop;
writeline(f, ln);
end loop;
end process;
------------------------------------------------------------
end behave;
|
apache-2.0
|
48c37b4ee5708e1b5113ddc0e508d7d0
| 0.54417 | 3.449216 | false | false | false | false |
twlostow/dsi-shield
|
hdl/top/rev1/reset_gen.vhd
| 1 | 1,205 |
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity reset_gen is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end reset_gen;
architecture behavioral of reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
|
lgpl-3.0
|
813af6a2f43caf0ce039d0ba93b8c9f9
| 0.575934 | 2.808858 | false | false | false | false |
luebbers/reconos
|
core/pcores/plb_osif_v2_01_a/hdl/vhdl/plb_osif.vhd
| 1 | 52,719 |
--!
--! \file osif.vhd
--!
--! OSIF logic and interface to IPIF
--!
--! \author Enno Luebbers <[email protected]>
--! \date 01.08.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 01.08.2006 Enno Luebbers File created (from opb_reconos_slot_v1_00_c)
-- 03.08.2006 Enno Luebbers Added PLB bus master (moved to v1.01.a),
-- removed BRAM interface
-- 23.11.2007 Enno Luebbers Moved OS communications to DCR
-- 07.12.2008 Enno Luebbers Moved memory bus interface to separate module
--
------------------------------------------------------------------------------
--
-- Original Xilinx header follows
--
------------------------------------------------------------------------------
-- osif.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: osif.vhd
-- Version: 1.01.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Tue Aug 1 12:51:51 2006 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_e;
use ipif_common_v1_00_e.ipif_pkg.all;
library plb_ipif_v2_01_a;
use plb_ipif_v2_01_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library plb_osif_v2_01_a;
use plb_osif_v2_01_a.all;
library osif_core_v2_01_a;
use osif_core_v2_01_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_PLB_AWIDTH -- PLB address bus width
-- C_PLB_DWIDTH -- PLB address data width
-- C_PLB_NUM_MASTERS -- Number of PLB masters
-- C_PLB_MID_WIDTH -- log2(C_PLB_NUM_MASTERS)
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- PLB_Clk -- PLB Clock
-- PLB_Rst -- PLB Reset
-- Sl_addrAck -- Slave address acknowledge
-- Sl_MBusy -- Slave busy indicator
-- Sl_MErr -- Slave error indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- PLB_abort -- PLB abort request indicator
-- PLB_ABus -- PLB address bus
-- PLB_BE -- PLB byte enables
-- PLB_busLock -- PLB bus lock
-- PLB_compress -- PLB compressed data transfer indicator
-- PLB_guarded -- PLB guarded transfer indicator
-- PLB_lockErr -- PLB lock error indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_MSize -- PLB master data bus size
-- PLB_ordered -- PLB synchronize transfer indicator
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_pendPri -- PLB pending request priority
-- PLB_pendReq -- PLB pending bus request indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_reqPri -- PLB current request priority
-- PLB_RNW -- PLB read/not write
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- M_abort -- Master abort bus request indicator
-- M_ABus -- Master address bus
-- M_BE -- Master byte enables
-- M_busLock -- Master buslock
-- M_compress -- Master compressed data transfer indicator
-- M_guarded -- Master guarded transfer indicator
-- M_lockErr -- Master lock error indicator
-- M_MSize -- Master data bus size
-- M_ordered -- Master synchronize transfer indicator
-- M_priority -- Master request priority
-- M_rdBurst -- Master burst read transfer indicator
-- M_request -- Master request
-- M_RNW -- Master read/nor write
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_wrBurst -- Master burst write transfer indicator
-- M_wrDBus -- Master write data bus
-- PLB_MBusy -- PLB master slave busy indicator
-- PLB_MErr -- PLB master slave error indicator
-- PLB_MWrBTerm -- PLB master terminate write burst indicator
-- PLB_MWrDAck -- PLB master write data acknowledge
-- PLB_MAddrAck -- PLB master address acknowledge
-- PLB_MRdBTerm -- PLB master terminate read burst indicator
-- PLB_MRdDAck -- PLB master read data acknowledge
-- PLB_MRdDBus -- PLB master read data bus
-- PLB_MRdWdAddr -- PLB master read word address
-- PLB_MRearbitrate -- PLB master bus re-arbitrate indicator
-- PLB_MSSize -- PLB slave data bus size
------------------------------------------------------------------------------
entity plb_osif is
generic
(
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_FIFO_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_BURSTLEN_WIDTH : integer := 5;
C_FAMILY : string := "virtex2p";
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_DCR_ILA : integer := 0 -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- burst mem interface
burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
burstWrData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
burstRdData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
burstWE : out std_logic;
burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- FIFO access signals
o_fifo_clk : out std_logic;
o_fifo_reset : out std_logic;
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic;
-- bus macro control
bmEnable : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DCR Bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0); -- chipscope
-- PLB Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
attribute SIGIS of interrupt : signal is "INTR_LEVEL_HIGH";
end entity plb_osif;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_osif is
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant USER_SLAVE : integer := USER_00;
constant RECONOS_BURST : integer := USER_01; -- shared memory burst transfers
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_SLAVE, -- user logic slave space (s/w addressable constrol/status registers)
1 => RECONOS_BURST -- memory burst access range
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant SLAVE_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant SLAVE_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant BURST_BASEADDR : std_logic_vector := C_BASEADDR or X"00004000";
constant BURST_HIGHADDR : std_logic_vector := C_BASEADDR or X"00007FFF";
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & SLAVE_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & SLAVE_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & BURST_BASEADDR, -- burst range base addresss
ZERO_ADDR_PAD & BURST_HIGHADDR -- burst range high addresss
);
-- specify data width for each target address range.
constant USER_DWIDTH : integer := 32;
constant RECONOS_BURST_DWIDTH : integer := 64;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH, -- user logic slave space data width
1 => RECONOS_BURST_DWIDTH
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant USER_NUM_SLAVE_CE : integer := 1;
constant RECONOS_BURST_NUM_CE : integer := 1;
constant USER_NUM_CE : integer := USER_NUM_SLAVE_CE+RECONOS_BURST_NUM_CE;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
-- 0 => pad_power2(USER_NUM_SLAVE_CE), -- number of chip enableds for user logic slave space (one per register)
-- 1 => pad_power2(RECONOS_BURST_NUM_CE)
0 => USER_NUM_SLAVE_CE, -- number of chip enableds for user logic slave space (one per register)
1 => RECONOS_BURST_NUM_CE
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0), -- user logic slave space dependent properties (none defined)
1 => (others => 0) -- reconos burst range properties (none defined)
);
-- specify determinate timing parameters to be used during read
-- accesses for each address range, these values are used to optimize
-- data beat timing response for burst reads from addresses sources such
-- as ddr and sdram memory, each address space requires three integer
-- entries for mode [0-2], latency [0-31] and wait states [0-31].
constant ARD_DTIME_READ_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate read parameters
0, 0, 0
);
-- specify determinate timing parameters to be used during write
-- accesses for each address range, they not used currently, so
-- all entries should be set to zeros.
constant ARD_DTIME_WRITE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate write parameters
0, 0, 0
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the plb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- plb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 1;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 128.
constant DEV_MAX_BURST_SIZE : integer := 128;
-- specify size of the largest target burstable memory space (in
-- bytes and a power of 2), this is to optimize the size of the
-- internal burst address counters.
constant DEV_BURST_PAGE_SIZE : integer := 1024;
-- specify number of plb clock cycles are allowed before a
-- data phase transfer timeout, this feature is useful during
-- system integration and debug.
constant DEV_DPHASE_TIMEOUT : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a plb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of plb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify allowing dma busrt mode transactions or not.
constant DMA_ALLOW_BURST : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma, apply to software
-- design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000;
-- specify period of the plb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant PLB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the plb data bus width.
constant IPIF_DWIDTH : integer := C_PLB_DWIDTH;
-- specify ipif address bus size, used for future ipif optimization,
-- should be set equal to the plb address bus width.
constant IPIF_AWIDTH : integer := C_PLB_AWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_PLB_AWIDTH;
-- specify index for user logic slave/master spaces chip enable.
constant USER_SLAVE_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_SLAVE));
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_Data : std_logic_vector(0 to C_PLB_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iBus2IP_Addr : std_logic_vector(0 to C_PLB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to C_PLB_DWIDTH - 1);
signal iBus2IP_BE : std_logic_vector(0 to (C_PLB_DWIDTH/8) - 1);
signal iBus2IP_Burst : std_logic;
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstBE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1) := (others => '0');
signal iIP2IP_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iIP2Bus_MstNum : std_logic_vector(0 to log2(DEV_MAX_BURST_SIZE/(C_PLB_DWIDTH/8))) := (others => '0');
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to find_id_dwidth(ARD_ID_ARRAY, ARD_DWIDTH_ARRAY, IPIF_RDFIFO_DATA, 32)-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_DataX : std_logic_vector(USER_DWIDTH to C_PLB_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to (RECONOS_BURST_DWIDTH/8)-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_DataX : std_logic_vector(USER_DWIDTH to C_PLB_DWIDTH-1); -- extended data
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal task_clk_internal : std_logic;
signal task_reset_internal : std_logic;
-- single word data input/output
signal mem2osif_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal osif2mem_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- addresses for master transfers
signal mem_localAddr : std_logic_vector(0 to USER_AWIDTH-1);
signal mem_targetAddr : std_logic_vector(0 to USER_AWIDTH-1);
-- single word transfer requests
signal mem_singleRdReq : std_logic;
signal mem_singleWrReq : std_logic;
-- burst transfer requests
signal mem_burstRdReq : std_logic;
signal mem_burstWrReq : std_logic;
signal mem_burstLen : std_logic_vector(0 to C_BURSTLEN_WIDTH-1);
-- status outputs
signal mem_busy : std_logic;
signal mem_rdDone : std_logic;
signal mem_wrDone : std_logic;
---------
-- local FIFO control and data lines
---------
signal fifomgr_read_remove : std_logic;
signal fifomgr_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_read_wait : std_logic;
signal fifomgr_write_add : std_logic;
signal fifomgr_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_write_wait : std_logic;
begin
------------------------------------------
-- instantiate the PLB IPIF, if necessary
------------------------------------------
PLB_IPIF_I : entity plb_ipif_v2_01_a.plb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_ARD_DTIME_READ_ARRAY => ARD_DTIME_READ_ARRAY,
C_ARD_DTIME_WRITE_ARRAY => ARD_DTIME_WRITE_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_DEV_BURST_PAGE_SIZE => DEV_BURST_PAGE_SIZE,
C_DEV_DPHASE_TIMEOUT => DEV_DPHASE_TIMEOUT,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_ALLOW_BURST => DMA_ALLOW_BURST,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_CLK_PERIOD_PS => PLB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_IPIF_AWIDTH => IPIF_AWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
PLB_clk => PLB_Clk,
Reset => PLB_Rst,
Freeze => '0',
IP2INTC_Irpt => open,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_ordered => PLB_ordered,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_pendReq => PLB_pendReq,
PLB_pendPri => PLB_pendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
IP2Bus_Clk => '0',
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Freeze => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '0',
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_IPMstTrans => open,
IP2RFIFO_WrReq => '0',
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_WrAck => open,
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_Data => open,
WFIFO2IP_RdAck => open,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
IP2Bus_DMA_Req => '0',
Bus2IP_DMA_Ack => open
);
------------------------------------------
-- instantiate the OSIF core
------------------------------------------
USER_LOGIC_I : entity osif_core_v2_01_a.osif_core
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_NUM_CE => USER_NUM_CE,
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_DCR_ILA => C_DCR_ILA
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => interrupt,
busy => busy,
blocking => blocking,
-- task interface
task_clk => task_clk_internal,
task_reset => task_reset_internal,
osif_os2task_vec => osif_os2task_vec,
osif_task2os_vec => osif_task2os_vec,
-- FIFO manager access signals
o_fifomgr_read_remove => fifomgr_read_remove,
i_fifomgr_read_data => fifomgr_read_data,
i_fifomgr_read_wait => fifomgr_read_wait,
o_fifomgr_write_add => fifomgr_write_add,
o_fifomgr_write_data => fifomgr_write_data,
i_fifomgr_write_wait => fifomgr_write_wait,
-- memory access signals
o_mem_singleData => osif2mem_singleData,
i_mem_singleData => mem2osif_singleData,
o_mem_localAddr => mem_localAddr,
o_mem_targetAddr => mem_targetAddr,
o_mem_singleRdReq => mem_singleRdReq,
o_mem_singleWrReq => mem_singleWrReq,
o_mem_burstRdReq => mem_burstRdReq,
o_mem_burstWrReq => mem_burstWrReq,
o_mem_burstLen => mem_burstLen,
i_mem_busy => mem_busy,
i_mem_rdDone => mem_rdDone,
i_mem_wrDone => mem_wrDone,
-- bus macro control
o_bm_enable => bmEnable,
-- MAP USER PORTS ABOVE THIS LINE ------------------
sys_clk => sys_clk,
sys_reset => sys_reset,
-- DCR Bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON
);
---------------------------------------
-- memory bus controller core
--
-- PLBv34
---------------------------------------
mem_plb34_i : entity plb_osif_v2_01_a.mem_plb34
generic map
(
C_SLAVE_BASEADDR => SLAVE_BASEADDR,
-- Bus protocol parameters
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_NUM_CE => USER_NUM_CE,
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_BURST_BASEADDR => BURST_BASEADDR
)
port map
(
clk => task_clk_internal,
reset => task_reset_internal,
-- data interface ---------------------------
-- burst mem interface
o_burstAddr => burstAddr,
o_burstData => burstWrData,
i_burstData => burstRdData,
o_burstWE => burstWE,
o_burstBE => burstBE,
-- single word data input/output
i_singleData => osif2mem_singleData,
o_singleData => mem2osif_singleData,
-- control interface ------------------------
-- addresses for master transfers
i_localAddr => mem_localAddr,
i_targetAddr => mem_targetAddr,
-- single word transfer requests
i_singleRdReq => mem_singleRdReq,
i_singleWrReq => mem_singleWrReq,
-- burst transfer requests
i_burstRdReq => mem_burstRdReq,
i_burstWrReq => mem_burstWrReq,
i_burstLen => mem_burstLen,
-- status outputs
o_busy => mem_busy,
o_rdDone => mem_rdDone,
o_wrDone => mem_wrDone,
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_DataX => uBus2IP_DataX,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_DataX => uIP2Bus_DataX,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr
);
-----------------------------------------------------------------------
-- fifo_mgr_inst: FIFO manager instantiation
--
-- The FIFO manager handles incoming push/pop requests to the two
-- hardware FIFOs attached to the OSIF. It arbitrates between
-- local hardware-thread-initiated requests and indirect bus accesses
-- by other hardware threads.
-----------------------------------------------------------------------
fifo_mgr_inst : entity plb_osif_v2_01_a.fifo_mgr
generic map (
C_FIFO_DWIDTH => C_FIFO_DWIDTH
)
port map (
clk => sys_clk,
reset => sys_reset, -- we don't want a thread reset command to flush
-- the FIFOs, therefore no thread_reset_i!
-- local FIFO access signals
i_local_read_remove => fifomgr_read_remove,
o_local_read_data => fifomgr_read_data,
o_local_read_wait => fifomgr_read_wait,
i_local_write_add => fifomgr_write_add,
i_local_write_data => fifomgr_write_data,
o_local_write_wait => fifomgr_write_wait,
-- "real" FIFO access signals
o_fifo_read_en => o_fifo_read_en,
i_fifo_read_data => i_fifo_read_data,
i_fifo_read_ready => i_fifo_read_ready,
o_fifo_write_en => o_fifo_write_en,
o_fifo_write_data => o_fifo_write_data,
i_fifo_write_ready => i_fifo_write_ready
-- TODO: signal to communicate with the bus_slave_regs module
);
--------
-- set FIFO clock/reset
--------
o_fifo_clk <= sys_clk;
o_fifo_reset <= sys_reset;
---------
-- set task clock/reset
---------
task_clk <= task_clk_internal;
task_reset <= task_reset_internal;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_DataX <= iBus2IP_Data(USER_DWIDTH to C_PLB_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE; --(0 to USER_DWIDTH/8-1);
-- uBus2IP_RdCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_RdCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
-- uBus2IP_WrCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_WrCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
iIP2Bus_Data(USER_DWIDTH to C_PLB_DWIDTH-1) <= uIP2Bus_DataX;
end IMP;
|
gpl-3.0
|
c10a53d4867c8a10841d97b380ae4bd6
| 0.477703 | 4.421251 | false | false | false | false |
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