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stringlengths 137
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stringclasses 15
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stringlengths 32
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float64 0.25
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P3Stor/P3Stor
|
pcie/IP core/pcie_command_send_fifo/example_design/pcie_command_send_fifo_top.vhd
| 1 | 5,856 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_command_send_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_command_send_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_command_send_fifo_top;
architecture xilinx of pcie_command_send_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_command_send_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_command_send_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
8ae92685ea24be1493ea88b4ea21a1df
| 0.512466 | 4.66242 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Finished_Cmd_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,255 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT Finished_Cmd_FIFO_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
7c560f3021c9cd3f3891a8de51d4d292
| 0.504665 | 3.932565 | false | false | false | false |
BBN-Q/APS2-TDM
|
src/TriggerInLogic.vhd
| 1 | 22,373 |
-- TriggerInLogic.vhd
--
-- Deserializes triggers and passes them to the User Logic through a FIFO based interface.
-- The FIFO allows the trigger receive logic and the User Logic clock to have independent clocks.
--
-- REVISIONS
--
-- 3/6/2014 CRJ
-- Created
--
-- 7/31/2014 CRJ
-- Modified to allow use of I/O buffer for loopback
--
-- 8/5/2014 CRJ
-- Unmodified
--
-- 8/28/2014 CRJ
-- Changed back to 0xF0 clock, since now bit slipping in logic versus the input cell
--
-- END REVISIONS
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity TriggerInLogic is
port
(
USER_CLK : in std_logic; -- Clock for the output side of the FIFO
CLK_200MHZ : in std_logic; -- Delay calibration clock
RESET : in std_logic; -- Asynchronous reset for the trigger logic and FIFO
TRIG_CLKP : in std_logic; -- 100MHz Serial Clock, clocks input side of FIFO
TRIG_CLKN : in std_logic;
TRIG_DATP : in std_logic; -- 800 Mbps Serial Data
TRIG_DATN : in std_logic;
TRIG_NEXT : in std_logic; -- Advance the FIFO output to the next trigger, must be synchronous to USER_CLK
TRIG_LOCKED : out std_logic; -- Set when locked and aligned to the received trigger clock, synchronous to USER_CLK
TRIG_ERR : out std_logic; -- Set if unaligned clock received after clock locked and aligned, synchronous to USER_CLK
TRIG_RX : out std_logic_vector(7 downto 0); -- Current trigger value, synchronous to USER_CLK
TRIG_OVFL : out std_logic; -- Set if trigger FIFO overflows, cleared by RESET, synchronous to USER_CLK
TRIG_READY : out std_logic -- FIFO output valid flag, set when TRIG_RX is valid, synchronous to USER_CLK
);
end TriggerInLogic;
architecture behavior of TriggerInLogic is
type TRIG_STATE is (TRIG_START, TRIG_CHK_STABLE, TRIG_NEXT_DLY, TRIG_CHK_DLY, TRIG_RESTART, TRIG_SET_DLY, TRIG_ALIGN, TRIG_DONE);
signal TrigState : TRIG_STATE;
signal TRIG_100MHZ : std_logic;
signal TRIG_200MHZ : std_logic;
signal TRIG_400MHZ : std_logic;
signal TRGCLK_IN : std_logic;
signal TRGCLK_IN_DLY : std_logic;
signal TRGCLK_IN_O : std_logic;
signal TRGDAT_IN : std_logic;
signal TRGDAT_IN_DLY : std_logic;
signal SerClk : std_logic_vector(7 downto 0);
signal PrevClk : std_logic_vector(7 downto 0);
signal FirstClk : std_logic_vector(7 downto 0);
signal SerDat : std_logic_vector(7 downto 0);
signal TrigDat : std_logic_vector(7 downto 0);
signal TrigLocked : std_logic;
signal DelayReady : std_logic;
signal FirstFound : std_logic;
signal DlyVal : std_logic_vector(5 downto 0);
signal DlyDiff : std_logic_vector(5 downto 0);
signal DlySum : std_logic_vector(5 downto 0);
signal FirstDly : std_logic_vector(5 downto 0);
signal CurDly : std_logic_vector(4 downto 0);
signal StableCnt : std_logic_vector(4 downto 0);
signal DbgTrigState : std_logic_vector(2 downto 0);
signal TrigRst : std_logic;
signal BitSlip : std_logic;
signal TrigErr : std_logic;
signal TrigFull : std_logic;
signal TrigValid : std_logic;
signal TrigDone : std_logic;
signal TrigEmpty : std_logic;
signal sTrigDone : std_logic;
signal TrigOvfl : std_logic;
signal SlipCnt : std_logic_vector(3 downto 0);
signal DataA : std_logic_vector(7 downto 0);
signal ClkA : std_logic_vector(7 downto 0);
signal ClkB : std_logic_vector(7 downto 0);
signal SlipData : std_logic_vector(7 downto 0);
signal SlipClk : std_logic_vector(7 downto 0);
begin
DbgTrigState <= std_logic_vector(to_unsigned(TRIG_STATE'pos(TrigState), 3));
-- Buffer Received Clock
BTC1 : IBUFDS
generic map
(
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
)
port map
(
O => TRGCLK_IN, -- Buffer output
I => TRIG_CLKP, -- Diff_p buffer input (connect directly to top-level port)
IB => TRIG_CLKN -- Diff_n buffer input (connect directly to top-level port)
);
-- Buffer Received Data
BTD1 : IBUFDS
generic map
(
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
)
port map
(
O => TRGDAT_IN, -- Buffer output
I => TRIG_DATP, -- Diff_p buffer input (connect directly to top-level port)
IB => TRIG_DATN -- Diff_n buffer input (connect directly to top-level port)
);
-- Generate data receive clocks from the external 100 MHz trigger clock.
CK1 : entity work.TRIG_MMCM
port map
(
CLK_100MHZ_IN => TRGCLK_IN_O, -- From undelayed output of Trigger Clock ISERDES
-- Clock out ports
TRIG_100MHZ => TRIG_100MHZ, -- Parallel trigger clock
TRIG_400MHZ => TRIG_400MHZ, -- DDR Data output clock
-- Status and control signals
RESET => not DelayReady, -- Ignore external clock until input delay is calibrated. IDELAYCTRL reset by RESET
LOCKED => TrigLocked
);
-- Define input delay related logic
IDC1 : IDELAYCTRL
port map
(
RDY => DelayReady,
REFCLK => CLK_200MHZ, -- 1-bit input: Reference clock input
RST => RESET -- 1-bit input: Active high reset input
);
-- Delay for serial clock input
ID1 : IDELAYE2
generic map
(
CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE)
DELAY_SRC => "IDATAIN", -- Delay input (IDATAIN, DATAIN)
HIGH_PERFORMANCE_MODE => "TRUE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
IDELAY_TYPE => "VAR_LOAD",-- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
IDELAY_VALUE => 0, -- Input delay tap setting (0-31)
PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE
REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0).
SIGNAL_PATTERN => "DATA" -- DATA, CLOCK input signal
)
port map
(
CNTVALUEOUT => CurDly, -- 5-bit output: Counter value output
DATAOUT => TRGCLK_IN_DLY, -- 1-bit output: Delayed data output
C => TRIG_100MHZ, -- Must be same as CLKDIV
CE => '0', -- 1-bit input: Active high enable increment/decrement input
CINVCTRL => '0', -- 1-bit input: Dynamic clock inversion input
CNTVALUEIN => DlyVal(4 downto 0), -- 5-bit input: Counter value input
DATAIN => '0', -- 1-bit input: Internal delay data input
IDATAIN => TRGCLK_IN, -- 1-bit input: Data input from the I/O
INC => '0', -- 1-bit input: Increment / Decrement tap delay input
LD => '1', -- 1-bit input: Load IDELAY_VALUE input
LDPIPEEN => '0', -- 1-bit input: Enable PIPELINE register to load data input
REGRST => not TrigLocked
);
-- Delay for serial data input
ID2 : IDELAYE2
generic map
(
CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE)
DELAY_SRC => "IDATAIN", -- Delay input (IDATAIN, DATAIN)
HIGH_PERFORMANCE_MODE => "TRUE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE")
IDELAY_TYPE => "VAR_LOAD",-- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
IDELAY_VALUE => 0, -- Input delay tap setting (0-31)
PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE
REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0).
SIGNAL_PATTERN => "DATA" -- DATA, CLOCK input signal
)
port map
(
CNTVALUEOUT => open , -- 5-bit output: Counter value output
DATAOUT => TRGDAT_IN_DLY, -- 1-bit output: Delayed data output
C => TRIG_100MHZ, -- Must be same as CLKDIV
CE => '0', -- 1-bit input: Active high enable increment/decrement input
CINVCTRL => '0', -- 1-bit input: Dynamic clock inversion input
CNTVALUEIN => DlyVal(4 downto 0), -- 5-bit input: Counter value input
DATAIN => '0', -- 1-bit input: Internal delay data input
IDATAIN => TRGDAT_IN, -- 1-bit input: Data input from the I/O
INC => '0', -- 1-bit input: Increment / Decrement tap delay input
LD => '1', -- 1-bit input: Load IDELAY_VALUE input
LDPIPEEN => '0', -- 1-bit input: Enable PIPELINE register to load data input
REGRST => not TrigLocked
);
-- Deserialize received clock
SIN1 : ISERDESE2
generic map
(
DATA_RATE => "DDR", -- DDR, SDR
DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
INIT_Q1 => '0', -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
IOBDELAY => "IFD", -- NONE, BOTH, IBUF, IFD
NUM_CE => 1, -- Number of clock enables (1,2)
OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE)
SERDES_MODE => "MASTER", -- MASTER, SLAVE
SRVAL_Q1 => '0', -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map
(
O => TRGCLK_IN_O, -- Udelayed clock to MMCM
Q1 => SerClk(7), -- Note that the first received value is wired to Q8
Q2 => SerClk(6), -- We sent data LSB first, so this assignment ordering
Q3 => SerClk(5), -- preserves the bit order
Q4 => SerClk(4),
Q5 => SerClk(3),
Q6 => SerClk(2),
Q7 => SerClk(1),
Q8 => SerClk(0),
SHIFTOUT1 => open ,
SHIFTOUT2 => open ,
BITSLIP => '0', -- Not used since it does not function as expected
CE1 => '1',
CE2 => '1',
CLKDIVP => '0' ,
CLK => TRIG_400MHZ, -- DDR clock
CLKB => not TRIG_400MHZ,
CLKDIV => TRIG_100MHZ, -- Parallel Data Clock
OCLK => '0' ,
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
D => TRGCLK_IN, -- Direct Data input
DDLY => TRGCLK_IN_DLY , -- Data from input delay
OFB => '0' ,
OCLKB => '0' ,
RST => not TrigLocked,
SHIFTIN1 => '0' ,
SHIFTIN2 => '0'
);
-- Deserialize received data
SIN2 : ISERDESE2
generic map
(
DATA_RATE => "DDR", -- DDR, SDR
DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
INIT_Q1 => '0', -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
IOBDELAY => "IFD", -- NONE, BOTH, IBUF, IFD
NUM_CE => 1, -- Number of clock enables (1,2)
OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE)
SERDES_MODE => "MASTER", -- MASTER, SLAVE
SRVAL_Q1 => '0', -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map
(
O => open, -- 1-bit output: Combinatorial output
Q1 => SerDat(7),
Q2 => SerDat(6),
Q3 => SerDat(5),
Q4 => SerDat(4),
Q5 => SerDat(3),
Q6 => SerDat(2),
Q7 => SerDat(1),
Q8 => SerDat(0),
SHIFTOUT1 => open ,
SHIFTOUT2 => open ,
BITSLIP => '0', -- Not used since it does not function as expected
CE1 => '1',
CE2 => '1',
CLKDIVP => '0' ,
CLK => TRIG_400MHZ, -- DDR clock
CLKB => not TRIG_400MHZ,
CLKDIV => TRIG_100MHZ, -- Parallel Data Clock
OCLK => '0' ,
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
D => TRGDAT_IN, -- Direct Data input
DDLY => TRGDAT_IN_DLY , -- Data from input delay
OFB => '0' ,
OCLKB => '0' ,
RST => not TrigLocked,
SHIFTIN1 => '0' ,
SHIFTIN2 => '0'
);
-- Sync the reset before using it to reset the trigger state machine
reset_synchronizer_inst : entity work.synchronizer
generic map(RESET_VALUE => '1')
port map(rst => RESET or (not TrigLocked), clk => TRIG_100MHZ, data_in => '0', data_out => TrigRst);
-- combinational assignment of SlipData
with SlipCnt(2 downto 0) select SlipData <=
DataA(7 downto 0) when "000",
DataA(6 downto 0) & SerDat(7) when "001",
DataA(5 downto 0) & SerDat(7 downto 6) when "010",
DataA(4 downto 0) & SerDat(7 downto 5) when "011",
DataA(3 downto 0) & SerDat(7 downto 4) when "100",
DataA(2 downto 0) & SerDat(7 downto 3) when "101",
DataA(1 downto 0) & SerDat(7 downto 2) when "110",
DataA(0) & SerDat(7 downto 1) when "111",
x"ff" when others;
-- Clock alignment state machine
process(TRIG_100MHZ, TrigRst)
begin
if TrigRst = '1' then
DlyVal <= "000000";
DlyDiff <= "000000";
DlySum <= "000000";
TrigState <= TRIG_START;
StableCnt <= "00000";
PrevClk <= (others => '0');
FirstFound <= '0';
FirstDly <= "000000";
FirstClk <= "00000000";
BitSlip <= '0';
TrigErr <= '0';
TrigOvfl <= '0';
TrigValid <= '0';
TrigDat <= "00000000";
TrigDone <= '0';
SlipCnt <= "0000";
DataA <= x"00";
ClkA <= x"00";
ClkB <= x"00";
SlipClk <= x"00";
elsif rising_edge(TRIG_100MHZ) then
-- Increment stable counter by default
StableCnt <= StableCnt + 1;
if BitSlip = '1' then
SlipCnt <= SlipCnt + 1;
end if;
-- ISERDES2 Bitslip doesn't seem to work for DDR 8:1, so do the slip in logic
DataA <= SerDat;
ClkA <= SerClk;
ClkB <= ClkA;
case SlipCnt(2 downto 0) is
when "000" => SlipClk <= ClkB(7 downto 0);
when "001" => SlipClk <= ClkB(6 downto 0) & ClkA(7);
when "010" => SlipClk <= ClkB(5 downto 0) & ClkA(7 downto 6);
when "011" => SlipClk <= ClkB(4 downto 0) & ClkA(7 downto 5);
when "100" => SlipClk <= ClkB(3 downto 0) & ClkA(7 downto 4);
when "101" => SlipClk <= ClkB(2 downto 0) & ClkA(7 downto 3);
when "110" => SlipClk <= ClkB(1 downto 0) & ClkA(7 downto 2);
when "111" => SlipClk <= ClkB(0) & ClkA(7 downto 1);
when others => null;
end case;
-- Calculate difference between current tap setting and start of stable region
DlyDiff <= DlyVal - FirstDly;
-- Calculate sum of current tap setting and start of stable region to allow finding mid point
DlySum <= DlyVal + FirstDly;
case TrigState is
when TRIG_START =>
-- Cleared in case of restart for debugging
TrigErr <= '0';
TrigDone <= '0';
TrigOvfl <= '0';
TrigValid <= '0';
-- Wait for 16 counts before proceeding
if StableCnt(4) = '1' then
StableCnt(4) <= '0';
PrevClk <= SerClk; -- Remember starting value for stability test
TrigState <= TRIG_CHK_STABLE;
end if;
when TRIG_CHK_STABLE =>
-- You may get a difference before the StableCnt reaches 16, but since the required setup and hold
-- times are so short, it is likely that you will always get stable values for all delay settings.
if PrevClk /= SerClk then
if FirstFound = '1' then
-- At the end of a stable section, check to see if you have found a wide stable set of taps
TrigState <= TRIG_CHK_DLY;
else
-- Haven't found a stable delay so advance the delay and try again
TrigState <= TRIG_NEXT_DLY;
end if;
else
-- 16 clocks with the same SerClk value, so remember the start of the stable region
-- Note that this ignores the PrevClk comparison on the last pass of the loop.
-- Leave StableCnt(4) set to indicate stable delay found for TRIG_CHK_DLY
if StableCnt(4) = '1' then
if FirstFound = '0' then
-- Save the first stable delay tap value and received clock value
FirstDly <= DlyVal;
FirstClk <= SerClk;
FirstFound <= '1';
TrigState <= TRIG_NEXT_DLY; -- Check for more consecutive stable delays
else
if SerClk = FirstClk then
-- Still in the same initial stable portion, so keep advancing
TrigState <= TRIG_NEXT_DLY;
else
-- If you have a new stable value, check to see if you have found a wide stable set of taps
TrigState <= TRIG_CHK_DLY;
end if;
end if;
end if;
end if;
when TRIG_NEXT_DLY =>
-- Increment the tap and wait 16 clocks before testing stability again
DlyVal(4 downto 0) <= DlyVal(4 downto 0) + 1;
StableCnt <= "00000"; -- 16 clocks for the delay and DDR regiters to update
TrigState <= TRIG_START;
when TRIG_CHK_DLY =>
-- This state is entered either when a non-stable tap is found after finding a stable tap,
-- or when a stable value that is different than the first stable value is found.
-- Check if the difference between the first stable tap and the current tap is at least 14
-- and then use the middle of the tap as the delay setting if it is.
-- If StableCnt(4) is set, then you had a new astable value, otherwise, you found an unstable value
-- This state is only entered if FirstFound is true.
if DlyDiff(4 downto 0) > 13 then
-- If you find a stable stretch 14 or longer, then set the delay in the middle of it
TrigState <= TRIG_SET_DLY;
else
if StableCnt(4) = '1' then
-- A short stable section was found, so restart at the current position, which is the start of a new stable section
TrigState <= TRIG_RESTART;
else
-- Start looking for a new starting stable point, since now unstable and previous stable was not 14 or more wide
FirstFound <= '0';
TrigState <= TRIG_NEXT_DLY;
end if;
end if;
when TRIG_RESTART =>
-- Change the starting point to the current clock and delay vlaue
-- Note that FirstFound remains set, only the starting point changes
-- Go through TRIG_START to reset the PrevClk to the current clock value
FirstDly <= DlyVal;
FirstClk <= SerClk;
TrigState <= TRIG_START;
when TRIG_SET_DLY =>
-- Set the delay to the average of the fisrt stable and current unstable delays
DlyVal(4 downto 0) <= DlySum(5 downto 1);
StableCnt <= (others => '0');
TrigState <= TRIG_ALIGN;
when TRIG_ALIGN =>
-- Keep shifting the bits by one clock until the clock is 0xF0 in order to align the data
BitSlip <= '0';
if StableCnt(4) = '1' then
StableCnt(4) <= '0';
if SlipClk /= x"F0" then
BitSlip <= '1';
else
TrigDone <= '1'; -- Single bit to sync for the TRIG_LOCKED output
TrigState <= TRIG_DONE;
end if;
-- Retry if no alignment after 8 slips
if SlipCnt(3) = '1' then
SlipCnt(3) <= '0';
FirstFound <= '0';
BitSlip <= '0';
TrigState <= TRIG_START;
end if;
end if;
when TRIG_DONE =>
-- Set an error flag if you ever receive anything other than an aligned clock on the clock input
-- This is an indication of noise and/or poor alignment on the serial clock input.
if SlipClk /= x"F0" then
TrigErr <= '1';
end if;
TrigDat <= SlipData; -- Save data for possible FIFO write
-- We send 0xFF to indicate "no data", write non-0xFF values to the
-- trigger receive FIFO
if SlipData /= x"ff" then
if TrigFull = '0' then
TrigValid <= '1'; -- Enable write in next cycle
else
TrigValid <= '0'; -- No write since FIFO Full
TrigOvfl <= '1';
end if;
else
TrigValid <= '0'; -- No write since zero value received
end if;
end case;
end if;
end process;
TFFI : entity work.TIO_FIFO
port map
(
rst => not TrigDone, -- Only enable FIFO once you have locked onto the incoming clock
wr_clk => TRIG_100MHZ,
rd_clk => USER_CLK,
din => TrigDat,
wr_en => TrigValid,
rd_en => TRIG_NEXT,
dout => TRIG_RX,
full => TrigFull ,
empty => TrigEmpty,
prog_full => open
);
TRIG_READY <= not TrigEmpty;
-- sync control signals onto USER_CLK
sync_ovfl : entity work.synchronizer
port map ( rst => RESET, clk => USER_CLK, data_in => TrigOvfl, data_out => TRIG_OVFL);
sync_locked : entity work.synchronizer
port map ( rst => RESET, clk => USER_CLK, data_in => TrigDone, data_out => TRIG_LOCKED);
sync_err : entity work.synchronizer
port map ( rst => RESET, clk => USER_CLK, data_in => TrigErr, data_out => TRIG_ERR);
end behavior;
|
mpl-2.0
|
0be6fe5764e0bbc3fa5bcd59f26a799d
| 0.565995 | 3.890957 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
tb_pkg.vhd
| 2 | 5,741 |
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- Yang Zheng
-- Eric Schwartz
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
--use ieee.fixed_float_types.all;
--use ieee.float_pkg.all;
--library ieee_proposed;
--use ieee_proposed.fixed_float_types.all; -- ieee in the release
--use ieee_proposed.float_pkg.all; -- ieee.float_pkg.all; in the release
package tb_pkg is
-----------------------------------------------------------------------
-- Procedure randomIn
-- Description: create random integer within a specified range
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- min : lower bound on randomly generated number
-- max : upper bound on randomly generated number
-- result : randomly generated integer
--
-- Preconditions: min <= max
-----------------------------------------------------------------------
procedure randomInt
(variable seed1, seed2 : inout positive; min, max : in integer;
variable result : out integer);
----------------------------------------------------------
-- Procedure randDecision
-- Description: randomly decide true/false based on a specified probability
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- prob : probability that decision will be yes/true
-- decision : the resulting decision
----------------------------------------------------------
procedure randDecision(seed1, seed2 : inout positive;
prob : real;
decision : out boolean);
----------------------------------------------------------
-- Procedure randDelay
-- Description: Create a delay with random cycle length, with specified
-- probability.
--
-- Parameters:
-- seed1/2 : seed values for random number generation
-- clk : The clock signal used for the delay
-- prob : probability that the delay will occur
-- min : the minimum cycle delay
-- max : the maximum cycle delay
----------------------------------------------------------
procedure randDelay(seed1, seed2 : inout positive;
signal clk : std_logic;
prob : real;
min, max : natural);
end tb_pkg;
package body tb_pkg is
-- procedure randomFloat(variable seed1, seed2 : inout positive; min, max : in real; variable result : out std_logic_vector(31 downto 0)) is
-- variable rand : real; -- Random real value in range 0 to 1.0
-- variable result_real : float32;
-- begin
-- assert (min <= max) report "ERROR: In randomFloat(), min must be <= max" severity error;
-- UNIFORM(seed1, seed2, rand); -- generate random number
-- --report"Random value is" & real'image(rand);
-- result_real := to_float((max-min)*rand+min, result_real'high, -result_real'low);
-- result := to_slv(result_real);
-- end randomFloat;
procedure randomInt(variable seed1, seed2 : inout positive; min, max : in integer; variable result : out integer) is
variable rand : real; -- Random real value in range 0 to 1.0
begin
assert (min <= max) report "ERROR: In randomInt(), min must be <= max" severity error;
UNIFORM(seed1, seed2, rand); -- generate random number
result := integer(TRUNC(real(max-min)*rand+real(min)));
--report"Random(int) value is " & integer'image(result);
end randomInt;
procedure randDecision(seed1, seed2 : inout positive;
prob : real;
decision : out boolean) is
variable rand : real;
begin
UNIFORM(seed1, seed2, rand);
if rand < prob then
decision := true;
else
decision := false;
end if;
end procedure;
procedure randDelay(seed1, seed2 : inout positive;
signal clk : std_logic;
prob : real;
min, max : natural) is
variable should_delay : boolean;
variable cycle_delay : natural;
begin
-- decide whether or not to delay
randDecision(seed1, seed2, prob, should_delay);
if should_delay then
-- delay by a random amount between min and max
randomInt(seed1, seed2, min, max, cycle_delay);
if cycle_delay > 0 then
for i in 0 to cycle_delay-1 loop
wait until rising_edge(clk);
end loop;
end if;
end if;
end procedure;
end package body;
|
gpl-3.0
|
b0469c8ea11b52e70080527543f3eca7
| 0.535098 | 4.559968 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/clock_generation.vhd
| 1 | 3,054 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- clock_generation.vhd
--
-- Generate multiple frequency deskewed clocks using dlls. There's some problem if
-- I hold the reset asserted while waiting for the dlls to to lock I can only upload
-- exactly 4 words. Seems to work OK using the async rst instead of rst_int.
-- I need to manually reset it after loading the code because the dlls haven't locked on yet.
-- I need a way to hold everything reset until the dlls lock
--**********************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.comp_pckgs.all;
ENTITY clock_generation IS
PORT
(
bufclkin : in std_logic;
rst_n : in std_logic;
bufsclkfb : in std_logic; --feedback clock from sdram
rst_int : out std_logic;
clk_12_5Mhz : out std_logic;
clk_50Mhz : out std_logic;
clk_100Mhz : out std_logic;
sclk : out std_logic
);
END clock_generation;
ARCHITECTURE clock_generation_arch OF clock_generation IS
signal lock : std_logic;
signal dllint_clk0 : std_logic;
signal bufdllint_clk0 : std_logic;
signal dllint_clk2x : std_logic;
signal bufdllint_clk2x : std_logic;
signal dllext_clk0 : std_logic;
signal locked, lockint, lockext : std_logic;
signal bufdllint_clkdv : std_logic;
signal dllint_clkdv : std_logic;
BEGIN
-- generate an internal clock sync'ed to the master clock
dllint: CLKDLL
generic map
( CLKDV_DIVIDE => 10)
port map
(
CLKIN=>bufclkin,
CLKFB=>bufdllint_clk0,
CLK0=>dllint_clk0,
RST=>'0',
CLK90=>open,
CLK180=>open,
CLK270=>open,
CLK2X=>dllint_clk2x,
CLKDV=>dllint_clkdv,
LOCKED=>lockint
);
-- generate an external SDRAM clock sync'ed to the master clock
dllext: CLKDLL
port map
(
CLKIN=>bufclkin,
CLKFB=>bufsclkfb,
CLK0=>dllext_clk0,
RST=>'0',
CLK90=>open,
CLK180=>open,
CLK270=>open,
CLK2X=>open,
CLKDV=>open,
LOCKED=>lockext
);
clkg: BUFG port map (I=>dllint_clk0, O=>bufdllint_clk0);
clkg2x: BUFG port map(I=>dllint_clk2x, O=>bufdllint_clk2x);
clkhalfx: BUFG port map(I=>dllint_clkdv, O=>bufdllint_clkdv);
-- output the sync'ed SDRAM clock to the SDRAM
sclk <= dllext_clk0;
clk_12_5Mhz <= bufdllint_clkdv;
clk_50Mhz <= bufdllint_clk0; -- SDRAM controller logic clock
clk_100Mhz <= bufdllint_clk2x; -- doubled clock to other FPGA logic;
locked <= lockint and lockext; -- indicate lock status of the DLLs
-- synchronous reset. internal reset flag is set active by config. bitstream
-- and then gets reset after DLL clocks start.
process(bufclkin)
begin
if(bufclkin'event and bufclkin='1') then
if locked='0' then
rst_int <= '0'; -- keep in reset until DLLs start up
else
rst_int <= rst_n; -- else manually activate reset with pushbutton
end if;
end if;
end process;
END clock_generation_arch;
|
gpl-3.0
|
d3c73fc403f8fa2e640495171ed86d98
| 0.651604 | 3.148454 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/ps2/web_ps2_tx.vhd
| 1 | 3,172 |
-- Иммитация приема байта от хоста в виде сигналов протокола PS/2 и формирует байт
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity web_ps2_tx is
port (
clk, reset: in std_logic;
ps2d_i, ps2c_i: in std_logic;
ps2d_o, ps2c_o: out std_logic;
tx_ack: out std_logic;
tx_done: out std_logic;
dout: out std_logic_vector(7 downto 0)
);
end web_ps2_tx;
architecture Behavioral of web_ps2_tx is
constant MAX_DETECT_VALUE: natural := 5000;
signal detect_counter: natural range 0 to MAX_DETECT_VALUE:= MAX_DETECT_VALUE; -- на частоте 50 MHz 5000 тиков = это 100 мкс
type state_type is (s_wait, s_data, s_ack, s_end);
signal state: state_type := s_wait;
signal bit_count: unsigned(3 downto 0);
signal buff: std_logic_vector(10 downto 0);
signal ack, tx_en, ris_edge, fall_edge, err: std_logic;
begin
tx_ack <= ack;
inst_ps2_clk: entity work.web_ps2_clk
port map(
clk => clk,
reset => reset,
en => ack,
ps2_clk => ps2c_o,
rising => ris_edge,
falling => fall_edge
);
-- определение начала передачи
proc_detect: process(reset, clk)
begin
if reset = '1' then
detect_counter <= MAX_DETECT_VALUE;
tx_en <= '0';
elsif falling_edge(clk) then
tx_en <= '0';
if ps2c_i = '0' then
if detect_counter = 0 then
tx_en <= '1';
detect_counter <= MAX_DETECT_VALUE;
else
detect_counter <= detect_counter - 1;
end if;
else
detect_counter <= MAX_DETECT_VALUE;
end if;
end if;
end process;
-- определяем ошибку приема данных
err <= not (not buff(0) and buff(10) and ( buff(9) xor
buff(8) xor buff(7) xor buff(6) xor buff(5) xor
buff(4) xor buff(3) xor buff(2) xor buff(1)
));
proc_tx: process(clk, reset)
variable skip_tick: boolean;
begin
if reset = '1' then
ack <= '0';
tx_done <= '0';
bit_count <= "0000";
buff <= (others => '0');
elsif rising_edge(clk) then
tx_done <= '0';
case state is
when s_wait =>
ps2d_o <= '1';
ack <= '0';
if tx_en = '1' then
state <= s_data;
ack <= '1';
bit_count <= "1010";
end if;
when s_data =>
if fall_edge = '1' then
buff <= ps2d_i & buff(10 downto 1);
if bit_count = "0000" then
state <= s_ack;
else
bit_count <= bit_count - 1;
end if;
end if;
when s_ack =>
if ris_edge = '1' then
ps2d_o <= '0';
state <= s_end;
end if;
when s_end =>
if ris_edge = '1' then
if err = '0' then
dout <= buff(8 downto 1);
tx_done <= '1';
end if;
ack <= '0';
ps2d_o <= '1';
state <= s_wait;
end if;
end case;
end if;
end process;
end Behavioral;
|
mit
|
e015c3518c7d82e0acd520bd229f1b1b
| 0.523715 | 3.051256 | false | false | false | false |
csrhau/sandpit
|
VHDL/vga_imdisplay/init_funcs.vhdl
| 1 | 1,832 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
use std.textio.all;
package init_funcs is
function read_file(data_file_name: string) return vga_memory_ptr;
function chr(sl: std_logic) return character;
function str(slv: std_logic_vector) return string;
end package init_funcs;
package body init_funcs is
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function read_file(data_file_name: string) return vga_memory_ptr is
variable state_ptr : vga_memory_ptr;
variable data_line : line;
variable text_line : line;
variable pixel_value: natural range 255 downto 0;
variable pixel_slv: std_logic_vector(7 downto 0);
file data_file : text open read_mode is data_file_name;
begin
state_ptr := new vga_memory;
for i in vga_memory'reverse_range loop -- range would operate downto, and reverse the image! (this took 3 hours)
readline(data_file, data_line);
read(data_line, pixel_value);
pixel_slv := std_logic_vector(to_unsigned(pixel_value, pixel_slv'length));
state_ptr(i) := pixel_slv;
end loop;
return state_ptr;
end function read_file;
end package body init_funcs;
|
mit
|
9829561e609a90b7063038853f697a72
| 0.610262 | 3.349177 | false | false | false | false |
chronos38/DSD-Projekt
|
Testbench/tb_debounce.vhd
| 1 | 1,210 |
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_debounce is
end entity tb_debounce;
architecture sim of tb_debounce is
component debounce
generic (
WIDTH : natural;
DELAY : natural);
port (
clk50 : in std_logic;
keyin_i : in std_logic_vector(WIDTH-1 downto 0);
keyout_o : out std_logic_vector(WIDTH-1 downto 0));
end component;
signal s_clk50 : std_logic := '0';
signal s_keyin_i : std_logic_vector(7 downto 0) := x"00";
signal s_keyout_o : std_logic_vector(7 downto 0) := x"00";
begin
i_debounce : debounce
generic map (
WIDTH => s_keyin_i'length,
DELAY => 11)
port map (
clk50 => s_clk50,
keyin_i => s_keyin_i,
keyout_o => s_keyout_o);
s_clk50 <= not s_clk50 after 1 ns;
p_test : process
begin
s_keyin_i <= (others => '0');
wait for 10 ns;
s_keyin_i <= x"FF";
wait for 10 ns;
s_keyin_i <= (others => '0');
wait for 10 ns;
s_keyin_i <= x"FF";
wait for 100 ns;
s_keyin_i <= (others => '0');
wait for 100 ns;
end process;
end sim;
|
gpl-3.0
|
e5c707a1b3b1a585668b7d2a31a9fef0
| 0.517355 | 3.209549 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/write_data_fifo/simulation/fg_tb_rng.vhd
| 54 | 3,878 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fg_tb_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fg_tb_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
gpl-2.0
|
d1aebcc32dec81df658420b7a4f7ad0f
| 0.636411 | 4.342665 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/top.vhd
| 1 | 23,922 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity top is
port(
clk_50mhz: in std_logic;
rs232_dce_txd: out std_logic;
rs232_dce_rxd: in std_logic;
led: out std_logic_vector(7 downto 0);
buttons: in std_logic_vector(7 downto 0);
-- ROTARY
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
-- PS/2
PS2_CLK1: inout std_logic;
PS2_DATA1: inout std_logic;
PS2_CLK2: inout std_logic;
PS2_DATA2: inout std_logic
);
end top;
architecture Behavioral of top is
-- [ TYPES ] --
-- [ TYPES ] - [Îáùèé òèï ñîñòîÿíèé] --
type STATE_TYPE is (
S_DOIT,
S_WAIT
);
-- [ TYPES ] - [Òèï ñîñòîÿíèé äëÿ ïàðñåðà] - [Ôîðìàò 0xAA 0x55 <äëèíà 2 áàéòà> <êîä óñòðîéñòâà> <äàííûå>] --
type PARSER_STATE_TYPE is (
S_AA,
S_55,
S_LENGTH_HIGH,
S_LENGTH_LOW,
S_CODE,
S_DATA
);
-- [TYPES] - [Òèï ñîñòîÿíèé äëÿ ñ÷èòûâàíèÿ ñ áóôåðà] --
type BUFFER_READ_STATE_TYPE is (
S_WAIT_BYTE,
S_BYTE_READY,
S_READ_BYTE
);
-- [ RESET ] -- [ Èíèöèàëèçèðóåò óñòðîéñòâà ]
signal reset: std_logic := '1';
-- [ RS232 ] --
constant system_speed: natural := 11538500;
constant baudrate: natural := 9600;
-- [ RS232 ] - [ receiver ] --
signal rs232_receiver_ack: std_logic := '0';
signal rs232_receiver_dat: unsigned(7 downto 0) := (others => '0');
signal rs232_receiver_stb: std_logic := '0';
-- [ RS232 ] - [ sender ] --
signal rs232_sender_ack: std_logic := '0';
signal rs232_sender_dat: unsigned(7 downto 0);
signal rs232_sender_stb: std_logic := '0';
-- [ CLK ] --
signal clk_main: std_logic;
-- [ FIFO ] - [ IN ] --
signal fifo_WriteEn : STD_LOGIC;
signal fifo_DataIn : STD_LOGIC_VECTOR (7 downto 0);
signal fifo_ReadEn : STD_LOGIC;
signal fifo_DataOut : STD_LOGIC_VECTOR (7 downto 0);
signal fifo_Empty : STD_LOGIC;
signal fifo_Full : STD_LOGIC;
-- [ FIFO ] - [ OUT ] --
signal fifo_out_WriteEn : STD_LOGIC;
signal fifo_out_DataIn : STD_LOGIC_VECTOR (7 downto 0);
signal fifo_out_ReadEn : STD_LOGIC;
signal fifo_out_DataOut : STD_LOGIC_VECTOR (7 downto 0);
signal fifo_out_Empty : STD_LOGIC;
signal fifo_out_Full : STD_LOGIC;
-- [ USER DEVICES ] --
-- [ ECHO ] --
-- signal echo_data_i : std_logic_vector(7 downto 0) := (others => '0');
-- signal echo_stb_i : std_logic := '0';
-- signal echo_ack_send_i : std_logic := '0';
-- signal echo_done_i : std_logic := '0';
-- signal echo_ready_receive_o : std_logic;
-- signal echo_ack_rec_o : std_logic;
-- signal echo_data_o : std_logic_vector(7 downto 0);
-- signal echo_stb_o : std_logic;
-- signal echo_package_length_o : std_logic_vector(15 downto 0);
-- signal echo_ready_send_o : std_logic;
signal echo_data_i : std_logic_vector(7 downto 0) := (others => '0');
signal echo_data_o : std_logic_vector(7 downto 0);
signal echo_package_length_o : std_logic_vector(3 downto 0);
signal echo_read_i : std_logic := '0';
signal echo_write_i : std_logic := '0';
signal echo_full_o : std_logic := '0';
signal echo_empty_o : std_logic := '0';
signal echo_read_state: BUFFER_READ_STATE_TYPE := S_WAIT_BYTE;
-- [ WEB_LED ] --
signal led_o: std_logic_vector(7 downto 0) := (others => '0');
signal led_i: std_logic_vector(7 downto 0) := (others => '0');
signal led_ack: std_logic := '0';
signal led_strobe: std_logic := '0';
-- [ WEB_BUTTON ] -- [ ðåàëèçîâàí òîëüêî îäíèì ñèãíàëîì, êîòîðûé ñâÿçûâàåò ïåðåäàííûé áàéò îò ñåðâåðà ñ ïîëüçîâàòåëüñêèì êîäîì ]
signal button_data_o: std_logic_vector(7 downto 0) := (others => '0');
signal button_rs232_data_i: std_logic_vector(7 downto 0) := (others => '0');
-- [ WEB_ROTARY ] -- [] --
signal web_rotary_rot_a_i: std_logic := '0';
signal web_rotary_rot_b_i: std_logic := '0';
signal web_rotary_rot_center_i: std_logic := '0';
signal web_rotary_rot_a_o: std_logic := '0';
signal web_rotary_rot_b_o: std_logic := '0';
signal web_rotary_rot_center_o: std_logic := '0';
-- [ WEB_OUTPUT ] -- [ ] --
signal web_output_write_i: std_logic := '0';
signal web_output_data_i: std_logic_vector(7 downto 0) := (others => '0');
signal web_output_read_i: std_logic := '0';
signal web_output_data_o: std_logic_vector(7 downto 0) := (others => '0');
signal web_output_empty_o: std_logic := '0';
signal web_output_full_o: std_logic := '0';
signal web_output_ready_i: std_logic := '0';
signal web_output_read_state: BUFFER_READ_STATE_TYPE := S_WAIT_BYTE;
-- [ WEB_KEYBOARD ] -- [] --
signal web_kbd_busy: std_logic := '0';
signal web_kbd_data_i: std_logic_vector(7 downto 0) := (others => '0');
signal web_kbd_rx_en: std_logic := '0';
signal web_kbd_rx_done: std_logic := '0';
signal web_kbd_data_o: std_logic_vector(7 downto 0) := (others => '0');
signal web_kbd_tx_done: std_logic := '0';
signal web_kbd_ps2d: std_logic := 'Z';
signal web_kbd_ps2c: std_logic := 'Z';
-- [ /USER DEVICES ] --
-- [STATES] --
signal rs232_sender_state: STATE_TYPE := S_WAIT;
signal rs232_receiver_state: STATE_TYPE := S_WAIT;
signal device_parser_send: PARSER_STATE_TYPE := S_AA;
signal device_parser_receive: PARSER_STATE_TYPE := S_AA;
signal device_send: STATE_TYPE := S_DOIT;
signal device_receive: STATE_TYPE := S_WAIT;
signal buffer_in_read_state: BUFFER_READ_STATE_TYPE := S_WAIT_BYTE;
signal buffer_out_read_state: BUFFER_READ_STATE_TYPE := S_WAIT_BYTE;
-- [COMPONENTS] --
-- [COMPONENTS] - [ Clock generator ] --
component coregen
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
end component;
signal PLL_LOCKED_OUT: std_logic;
begin
-- [COMPNENT INSTANCE] --
-- [ CLK ] --
inst_coregen: coregen port map(
CLKIN_IN => clk_50mhz,
RST_IN => '0',
CLKFX_OUT => clk_main,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => PLL_LOCKED_OUT
);
--clk_main <= clk_50mhz;
-- [ RS232 ] - [sender] - [ Îòïðàâëÿåò áàéò íà com ïîðò ] --
inst_rs232_sender: entity work.rs232_sender
generic map(system_speed, baudrate)
port map(
ack_o => rs232_sender_ack,
clk_i => clk_main,
dat_i => rs232_sender_dat,
rst_i => reset,
stb_i => rs232_sender_stb,
tx => rs232_dce_txd
);
-- [ RS232 ] - [receiver] - [ Ïðèíèìàåò áàéò ñ com ïîðòà ] --
inst_rs232_receiver: entity work.rs232_receiver
generic map(system_speed, baudrate)
port map(
ack_i => rs232_receiver_ack,
clk_i => clk_main,
dat_o => rs232_receiver_dat,
rst_i => reset,
stb_o => rs232_receiver_stb,
rx => rs232_dce_rxd
);
-- [ FIFO ] --
-- [ Áóôåðèçèðóåò ïðèíÿòûå äàííûå ñ com ïîðòà ] --
inst_fifo_in: entity work.fifo
generic map (64, 8)
port map (
CLK => clk_main,
RST => reset,
WriteEn => fifo_WriteEn,
DataIn => fifo_DataIn,
ReadEn => fifo_ReadEn,
DataOut => fifo_DataOut,
Empty => fifo_Empty,
Full => fifo_Full
);
-- [ Áóôåðèçèðóåò äàííûå äëÿ îòïðàâêè íà com ïîðò ] --
inst_fifo_out: entity work.fifo
generic map (64, 8)
port map (
CLK => clk_main,
RST => reset,
WriteEn => fifo_out_WriteEn,
DataIn => fifo_out_DataIn,
ReadEn => fifo_out_ReadEn,
DataOut => fifo_out_DataOut,
Empty => fifo_out_Empty,
Full => fifo_out_Full
);
-- [USER DEVICES] --
-- [ECHO] - [0x01] --
inst_echo: entity work.echo
port map (
clk => clk_main,
reset => reset,
data_i => echo_data_i,
data_o => echo_data_o,
length_o => echo_package_length_o,
read_i => echo_read_i,
write_i => echo_write_i,
full_o => echo_full_o,
empty_o => echo_empty_o
);
-- [ WEB_LED ] - [0x02] --
inst_web_led: entity work.web_led
port map (
data_o => led_o,
data_i => led_i,
ack_i => led_ack,
strobe_o => led_strobe,
rst_i => reset,
clk => clk_main
);
led <= led_o; -- ôèçè÷åñêèå ñâåòîäèîäû
-- [ WEB_BUTTON ] - [0x03] --
inst_web_button: entity work.web_button
port map (
data_o => button_data_o,
rs232_data_i => button_rs232_data_i,
physical_data_i => buttons,
rst_i => reset,
clk => clk_main
);
-- [ WEB_ROTARY ] -- [0x04] --
inst_web_rotary: entity work.web_rotary
port map (
rot_a_o => web_rotary_rot_a_o,
rot_b_o => web_rotary_rot_b_o,
rot_center_o => web_rotary_rot_center_o,
rot_a_i => rot_a,
rot_b_i => rot_b,
rot_center_i => rot_center,
rot_a_rs232_i => web_rotary_rot_a_i,
rot_b_rs232_i => web_rotary_rot_b_i,
rot_center_rs232_i => web_rotary_rot_center_i,
rst_i => reset,
clk => clk_main
);
-- [ WEB_OUTPUT ] - [0x05] -- [ Âûâîä äàííûõ â êîíñîëü áðàóçåðà ] --
inst_web_output: entity work.fifo
generic map (8, 8)
port map (
CLK => clk_main,
RST => reset,
WriteEn => web_output_write_i,
DataIn => web_output_data_i,
ReadEn => web_output_read_i,
DataOut => web_output_data_o,
Empty => web_output_empty_o,
Full => web_output_full_o
);
-- [ WEB_KEYBOARD ] - [ 0x06 ] - [ Èììèòàòîð êëàâèàòóðû ]
inst_web_keyboard: entity work.web_keyboard
port map(
clk => clk_main,
rst => reset,
busy => web_kbd_busy,
data_i => web_kbd_data_i,
rx_en => web_kbd_rx_en,
rx_done => web_kbd_rx_done,
data_o => web_kbd_data_o,
tx_done => web_kbd_tx_done,
ps2d => web_kbd_ps2d,
ps2c => web_kbd_ps2c,
led => open
);
-- [PROCESS STATEMENTS] --
-- [ Îáðàáîò÷èê ïðèíÿòèÿ áàéòà ñ COM ïîðòà] --
rs232_receive_proc: process(clk_main)
begin
if rising_edge(clk_main) then
case rs232_receiver_state is
-- îæèäàåì âçâîäà strobe
when S_WAIT =>
fifo_WriteEn <= '0';
if rs232_receiver_stb = '1' then
-- ïåðåõîä ê îæèäàíèþ îêîí÷àíèÿ ñ÷èòûâàíèÿ áàéòà
rs232_receiver_state <= S_DOIT;
rs232_receiver_ack <= '1';
end if;
-- îæèäàåì îêîí÷àíèå ïðèíÿòèÿ áàéòà
when S_DOIT =>
if rs232_receiver_stb <= '0' then
rs232_receiver_ack <= '0';
-- Åñëè áóôôåð íå ïîëîí, òî çàïèñûâàåì òóäà ïðèíÿòûé áàéò
if fifo_Full /= '1' then
fifo_DataIn <= std_logic_vector(rs232_receiver_dat);
fifo_WriteEn <= '1';
end if;
-- îæèäàåì ñëåäóþùèé áàéò
rs232_receiver_state <= S_WAIT;
end if;
end case;
end if;
end process;
-- [ Îáðàáîò÷èê ïåðåäà÷è áàéòà íà COM ïîðò] --
rs232_send_proc: process(clk_main)
variable byte: std_logic_vector(7 downto 0) := (others => '0');
variable has_byte: boolean := false;
begin
if rising_edge(clk_main) then
case buffer_out_read_state is
when S_WAIT_BYTE =>
if fifo_out_Empty /= '1' and has_byte = false then
fifo_out_ReadEn <= '1';
buffer_out_read_state <= S_BYTE_READY;
end if;
when S_BYTE_READY =>
buffer_out_read_state <= S_READ_BYTE;
fifo_out_ReadEn <= '0';
when S_READ_BYTE =>
has_byte := true;
byte := fifo_out_DataOut;
buffer_out_read_state <= S_WAIT_BYTE;
end case;
case rs232_sender_state is
when S_WAIT =>
if rs232_sender_ack = '0' and has_byte then
has_byte := false;
rs232_sender_dat <= unsigned(byte);
rs232_sender_stb <= '1';
rs232_sender_state <= S_DOIT;
end if;
when S_DOIT =>
if rs232_sender_ack = '1' then
rs232_sender_stb <= '0';
rs232_sender_state <= S_WAIT;
end if;
end case;
end if;
end process;
-- [ Ïàðñåð îòïðàâêè äàííûõ â óñòðîéñòâî ] --
parser_send_proc: process(clk_main)
-- variable i: integer := 0;
variable code: std_logic_vector(7 downto 0) := (others => '0');
variable len: std_logic_vector(15 downto 0) := (others => '0');
variable byte: std_logic_vector(7 downto 0) := (others => '0');
variable flag: boolean;
variable has_byte: boolean := false;
begin
if rising_edge(clk_main) then
-- Ñ÷èòûâàåì äàííûå ñ áóôåðà
case buffer_in_read_state is
-- åñëè åñòü áàéò äëÿ ñ÷èòûâàíèÿ, òî óêàçûâàåì íà ñ÷èòûâàíèå
when S_WAIT_BYTE =>
if fifo_Empty /= '1' and has_byte = false then
fifo_ReadEn <= '1';
buffer_in_read_state <= S_BYTE_READY;
end if;
-- òàêò ñ÷èòûâàíèÿ
when S_BYTE_READY =>
fifo_ReadEn <= '0';
buffer_in_read_state <= S_READ_BYTE;
-- çàáèðàåì áàéò
when S_READ_BYTE =>
byte := fifo_DataOut;
has_byte := true;
buffer_in_read_state <= S_WAIT_BYTE;
end case;
-- Ïàðñèì ïàêåò äàííûõ
case device_parser_send is
-- Ïåðâûé áàéò 0xAA
when S_AA =>
if has_byte then
has_byte := false;
if byte = X"AA" then
device_parser_send <= S_55;
end if;
end if;
-- Âòîðîé áàéò 0x55
when S_55 =>
if has_byte then
has_byte := false;
if byte = X"55" then
device_parser_send <= S_LENGTH_HIGH;
else
device_parser_send <= S_AA;
end if;
end if;
-- Ñòàðøèé áàéò äëèíû ïàêåòà
when S_LENGTH_HIGH =>
if has_byte then
has_byte := false;
len(15 downto 8) := byte;
device_parser_send <= S_LENGTH_LOW;
end if;
-- Ìëàäøèé áàéò äëèíû ïàêåòà
when S_LENGTH_LOW =>
if has_byte then
has_byte := false;
len(7 downto 0) := byte;
device_parser_send <= S_CODE;
end if;
-- Êîä óñòðîéñòâà
when S_CODE =>
if has_byte then
has_byte := false;
code := byte;
device_parser_send <= S_DATA;
end if;
-- Äàííûå
when S_DATA =>
-- Åñëè äëèíà îáíóëèëàñü, çíà÷èò ïàêåò äàííûõ ïðèíÿò ïîëíîñòüþ
if len = X"0000" then
-- îáíóëÿåì ñîñòîÿíèÿ, è çàïðåùàåì ñ÷èòûâàíèå äàííûõ ñ áóôåðà
device_parser_send <= S_AA;
device_send <= S_DOIT;
else
-- Ïåðåäà÷à äàííûõ óñòðîéñòâàì
case device_send is
-- Ïåðåäàåì äàííûå ê óñòðîéñòâó
when S_DOIT =>
-- [ Âûáèðàåì óñòðîéñòâî, êîòîðîìó ïåðåäàåì äàííûå ] --
case code is
-- Ýõî óñòðîéñòâî
when X"01" =>
if
echo_full_o = '0'
and
has_byte
then
has_byte := false;
echo_data_i <= byte;
echo_write_i <= '1';
device_send <= S_WAIT;
end if;
-- Buttons
when X"03" =>
if has_byte then
has_byte := false;
button_rs232_data_i <= byte;
device_send <= S_WAIT;
end if;
when X"04" =>
if has_byte then
has_byte := false;
web_rotary_rot_a_i <= byte(0);
web_rotary_rot_b_i <= byte(1);
web_rotary_rot_center_i <= byte(2);
device_send <= S_WAIT;
end if;
-- Keyboard
when X"06" =>
if has_byte and web_kbd_busy = '0' then
has_byte := false;
web_kbd_data_i <= byte;
web_kbd_rx_en <= '1';
device_send <= S_WAIT;
end if;
-- Åñëè óñòðîéñòâî íå íàéäåíî, òî ðåèíèöèàëèçàöèÿ
when others =>
device_parser_send <= S_AA;
device_send <= S_DOIT;
end case;
-- Æäåì óñïåøíîãî ïðèíÿòèÿ äàííûõ
when S_WAIT =>
-- [ Âûáèðàåì óñòðîéñòâî ] --
case code is
when X"01" =>
echo_write_i <= '0';
len := len - '1';
device_send <= S_DOIT;
-- Buttons
when X"03" =>
len := len - '1';
device_send <= S_DOIT;
-- Rotary
when X"04" =>
len := len - '1';
device_send <= S_DOIT;
-- Keyboard
when X"06" =>
if web_kbd_rx_done = '1' then
len := len - '1';
web_kbd_rx_en <= '0';
device_send <= S_DOIT;
end if;
-- Åñëè óñòðîéñòâî íå íàéäåíî, òî ðåèíèöèàëèçàöèÿ
when others =>
device_parser_send <= S_AA;
device_send <= S_DOIT;
end case;
end case;
end if;
end case;
end if;
end process;
-- [ Ïàðñåð ïðèåìà äàííûõ îò óñòðîéñòâà ] --
parser_receive_proc: process(clk_main, reset)
variable code: std_logic_vector(7 downto 0) := (others => '0');
variable len: std_logic_vector(15 downto 0) := (others => '0');
variable resolve_receive: boolean := false;
variable was_full: boolean := false;
variable has_byte: boolean := false;
begin
if reset = '1' then
code := X"00";
len := X"0000";
resolve_receive := false;
fifo_out_WriteEn <= '0';
device_receive <= S_WAIT;
device_parser_receive <= S_AA;
echo_read_state <= S_WAIT_BYTE;
web_output_read_state <= S_WAIT_BYTE;
has_byte := false;
elsif rising_edge(clk_main) then
fifo_out_WriteEn <= '0';
if has_byte then
if fifo_out_Full /= '1' then
fifo_out_WriteEn <= '1';
has_byte := false;
end if;
else
case device_receive is
when S_WAIT =>
code := X"00";
-- Âûáèðàåì óñòðîéñòâî, êîòîðîå ãîòîâî ïåðåäàâàòü äàííûå
-- [ ECHO ]
if echo_empty_o = '0' then
code := X"01";
len := X"000" & echo_package_length_o;
echo_read_state <= S_WAIT_BYTE;
device_receive <= S_DOIT;
-- [ LED ] --
elsif led_strobe = '1' then
code := X"02";
len := X"0001";
device_receive <= S_DOIT;
-- [ WEB_OUTPUT ] --
elsif web_output_empty_o /= '1' then
code := X"05";
len := X"0001";
device_receive <= S_DOIT;
-- [ WEB_KEYBOARD ] --
elsif web_kbd_tx_done = '1' then
code := X"06";
len := X"0001";
device_receive <= S_DOIT;
end if;
when S_DOIT =>
case device_parser_receive is
when S_AA =>
fifo_out_DataIn <= X"AA";
device_parser_receive <= S_55;
has_byte := true;
when S_55 =>
fifo_out_DataIn <= X"55";
device_parser_receive <= S_LENGTH_HIGH;
has_byte := true;
when S_LENGTH_HIGH =>
fifo_out_DataIn <= len(15 downto 8);
device_parser_receive <= S_LENGTH_LOW;
has_byte := true;
when S_LENGTH_LOW =>
fifo_out_DataIn <= len(7 downto 0);
device_parser_receive <= S_CODE;
has_byte := true;
when S_CODE =>
fifo_out_DataIn <= code;
device_parser_receive <= S_DATA;
has_byte := true;
when S_DATA =>
case code is
-- [Ýõî óñòðîéñòâî]
when X"01" =>
case echo_read_state is
when S_WAIT_BYTE =>
echo_read_i <= '1';
echo_read_state <= S_BYTE_READY;
when S_BYTE_READY =>
echo_read_i <= '0';
echo_read_state <= S_READ_BYTE;
when S_READ_BYTE =>
fifo_out_DataIn <= echo_data_o;
echo_read_state <= S_WAIT_BYTE;
has_byte := true;
len := len - 1;
if unsigned(len) = X"0000" then
device_parser_receive <= S_AA;
device_receive <= S_WAIT;
end if;
end case;
-- [ LED ] --
when X"02" =>
if led_strobe = '1' then
led_ack <= '1';
fifo_out_DataIn <= led_o;
has_byte := true;
else
led_ack <= '0';
device_receive <= S_WAIT;
device_parser_receive <= S_AA;
end if;
when X"05" =>
case web_output_read_state is
when S_WAIT_BYTE =>
web_output_read_i <= '1';
web_output_read_state <= S_BYTE_READY;
when S_BYTE_READY =>
web_output_read_i <= '0';
web_output_read_state <= S_READ_BYTE;
when S_READ_BYTE =>
fifo_out_DataIn <= web_output_data_o;
web_output_read_state <= S_WAIT_BYTE;
has_byte := true;
len := len - 1;
if unsigned(len) = X"0000" then
device_parser_receive <= S_AA;
device_receive <= S_WAIT;
end if;
end case;
-- [WEB_KEYBOARD] --
when X"06" =>
fifo_out_DataIn <= web_kbd_data_o;
has_byte := true;
device_receive <= S_WAIT;
device_parser_receive <= S_AA;
when others =>
device_receive <= S_WAIT;
device_parser_receive <= S_AA;
fifo_out_WriteEn <= '0';
end case; -- code
end case; -- device_parser_receive
end case; -- device_receive
end if;
end if;
end process;
web_output_ready_i <= not web_output_full_o;
-- USER CODE
inst_user_code: entity work.user_code
port map(
-- [ LED ] --
led => led_i,
-- [ BUTTONS ] --
buttons => button_data_o,
-- [ WEB_OTPUT ] --
web_output_write_o => web_output_write_i,
web_output_data_o => web_output_data_i,
web_output_ready_i => web_output_ready_i,
rot_a => web_rotary_rot_a_o,
rot_b => web_rotary_rot_b_o,
rot_center => web_rotary_rot_center_o,
web_ps2_kbd_data => web_kbd_ps2d,
web_ps2_kbd_clk => web_kbd_ps2c,
ps2_data1 => PS2_DATA1,
ps2_clk1 => PS2_CLK1,
ps2_data2 => PS2_DATA2,
ps2_clk2 => PS2_CLK2,
reset_o => reset,
clk => clk_main
);
end Behavioral;
|
mit
|
ab36cd755aa6f7f3189f4d5180dcdbc1
| 0.494691 | 3.360303 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/write_data_fifo/simulation/fg_tb_pctrl.vhd
| 6 | 18,528 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-2.0
|
68c9f134b4dcd0e681a4b271e4d64cb7
| 0.50815 | 3.238029 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/control7seg.vhd
| 1 | 5,850 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: control7seg.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity control7seg is
port ( clk_1KHz : in STD_LOGIC;
rst: in std_logic;
data_in : in STD_LOGIC_VECTOR (15 downto 0);
data_out : out STD_LOGIC_VECTOR (6 downto 0);
sel : out STD_LOGIC_VECTOR (3 downto 0));
end control7seg;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of control7seg is
-- Tipos propios:
type t_st is (s0, s1, s2, s3);
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal current_state, next_state : t_st; -- Estados actual y siguiente.
signal disp0: std_logic_vector(3 downto 0);
signal disp1: std_logic_vector(3 downto 0);
signal disp2: std_logic_vector(3 downto 0);
signal disp3: std_logic_vector(3 downto 0);
signal dispBin_aux: std_logic_vector(3 downto 0);
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
disp0 <= data_in(3 downto 0); -- disp0 es el de mas a la derecha
disp1 <= data_in(7 downto 4);
disp2 <= data_in(11 downto 8);
disp3 <= data_in(15 downto 12);
-----------------------------------------------------------------------------
-- Instancia de componentes
-----------------------------------------------------------------------------
---------------------------------------------------
-- Proceso de calculo del estado siguiente
---------------------------------------------------
p_next_state : process (current_state) is
begin
case current_state is
when s0 =>
next_state <= s1;
when s1 =>
next_state <= s2;
when s2 =>
next_state <= s3;
when others =>
next_state <= s0;
end case;
end process p_next_state;
---------------------------------------------------
-- Proceso de asignación de valores a las salidas
---------------------------------------------------
p_outputs : process (current_state, disp0, disp1, disp2, disp3)
begin
case current_state is
when s0 =>
dispBin_aux <= disp0;
sel <= "1110";
when s1 =>
dispBin_aux <= disp1;
sel <= "1101";
when s2 =>
dispBin_aux <= disp2;
sel <= "1011";
when s3 =>
dispBin_aux <= disp3;
sel <= "0111";
when others =>
dispBin_aux <= (others => '0');
sel <= "1111";
end case;
end process p_outputs;
---------------------------------------------------
-- Proceso de actualizacion del estado
---------------------------------------------------
p_status_reg : process (clk_1KHz, rst) is
begin
if rst = '1' then
current_state <= s0;
elsif rising_edge(clk_1KHz) then
current_state <= next_state;
end if;
end process p_status_reg;
---------------------------------------------------
-- Conversion binario - 7seg
---------------------------------------------------
p_conv: process(dispBin_aux) is
begin
case dispBin_aux is
when "0000" => --0
data_out <= "1000000";
when "0001" => --1
data_out <= "1111001";
when "0010" => --2
data_out <= "0100100";
when "0011" => --3
data_out <= "0110000";
when "0100" => --4
data_out <= "0011001";
when "0101" => --5
data_out <= "0010010";
when "0110" => --6
data_out <= "0000010";
when "0111" => --7
data_out <= "1111000";
when "1000" => --8
data_out <= "0000000";
when "1001" => --9
data_out <= "0010000";
when "1010" => --A
data_out <= "0001000";
when "1011" => --B
data_out <= "0000011";
when "1100" => --C
data_out <= "1000110";
when "1101" => --D
data_out <= "0100001";
when "1110" => --E
data_out <= "0000110";
when "1111" => --F
data_out <= "0001110";
when others => --apagado
data_out <= "1111111";
end case;
end process p_conv;
end rtl;
|
gpl-3.0
|
9e2dc2dab4d36c263b68d8ddcf296c1c
| 0.434017 | 4.270073 | false | false | false | false |
tuura/fantasi
|
dependencies/Altera_DE4/niosII/system1_inst.vhd
| 1 | 2,065 |
component system1 is
port (
clk_clk : in std_logic := 'X'; -- clk
input0_extern_con_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
input1_extern_con_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
input2_extern_con_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
input3_extern_con_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
output0_extern_con_export : out std_logic_vector(31 downto 0); -- export
output1_extern_con_export : out std_logic_vector(31 downto 0); -- export
output2_extern_con_export : out std_logic_vector(31 downto 0); -- export
output3_extern_con_export : out std_logic_vector(31 downto 0); -- export
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component system1;
u0 : component system1
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
input0_extern_con_export => CONNECTED_TO_input0_extern_con_export, -- input0_extern_con.export
input1_extern_con_export => CONNECTED_TO_input1_extern_con_export, -- input1_extern_con.export
input2_extern_con_export => CONNECTED_TO_input2_extern_con_export, -- input2_extern_con.export
input3_extern_con_export => CONNECTED_TO_input3_extern_con_export, -- input3_extern_con.export
output0_extern_con_export => CONNECTED_TO_output0_extern_con_export, -- output0_extern_con.export
output1_extern_con_export => CONNECTED_TO_output1_extern_con_export, -- output1_extern_con.export
output2_extern_con_export => CONNECTED_TO_output2_extern_con_export, -- output2_extern_con.export
output3_extern_con_export => CONNECTED_TO_output3_extern_con_export, -- output3_extern_con.export
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
|
mit
|
ba9d61352414ba2306f04cf1ebda75c1
| 0.601937 | 3.251969 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
fifo_vr.vhd
| 1 | 14,716 |
-- Copyright (c) University of Florida
--
-- This file is part of window_gen.
--
-- window_gen is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- window_gen is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with window_gen. If not, see <http://www.gnu.org/licenses/>.
-- Greg Stitt
-- University of Florida
-- Description:
-- fifo_vr (variable read)
-- This entity implements a fifo that writes a fixed (but configurable)
-- number of inputs in parallel, while allowing a variable number of outputs
-- to be read each cycle.
--
-- The entity is useful for streams of data where upstream components always
-- produce a fixed amount of data, but downstream components may need to
-- read a variable amount of data. e.g., when streaming an image sequentially
-- from memory into an FPGA, the memory might provide four pixels per cycle.
-- If the circuit buffers each row into separate on-chip memories, then at the
-- end of a row, the circuit may need to read less than four pixels if the # of
-- columns is not a multiple of four. In this case, the buffer enables the
-- memory to continually write four pixels per cycle, while the downstream
-- circuit reads as much as needed.
--
-- The size of the fifo is fixed because its main purpose is to dynamically
-- read varying amounts of data from a stream. If a typical FIFO is needed for
-- buffering, the user should connect that FIFO to the input of this
-- entity.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generic Descriptions
-- data_width : The width of a single element to read from the FIFO
-- parallel_io : The number of parallel inputs written every cycle, which
-- is also the max number of outputs that can be read each
-- cycle.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions (all control signals are active high)
-- clk: clock
-- rst: asynchronous reset
-- rd : read data from the buffer (does nothing when empty is asserted)
-- rd_amount : The amount of elements to read from the buffer when rd is
-- asserted. Note that if rd_amount is larger than the actual
-- amount of elements in the fifo, the fifo returns only what
-- it has stored. e.g., If the fifo has 2 elements and rd_amount
-- is 3 when rd is asserted, the fifo will output two valid
-- elements and a third junk element.
-- wr : write num_inputs inputs into the buffer (does nothing when
-- full is asserted)
-- empty : asserted when the buffer is empty (has 0 elements in fifo)
-- full : asserted when there isn't room to write num_inputs inputs.
-- input : num_inputs input values, concatenated into a big std_logic_vector
-- output : max_outputs outputs. When rd_amount < max_outputs, the higher bits
-- contains valid datas.
-- count : the number of valid data_width elements in the fifo
-- valid_out : individual valid bits for each output
-------------------------------------------------------------------------------
entity fifo_vr is
generic (
data_width : positive;
parallel_io : positive;
input0_at_MSB : boolean := false;
output0_at_MSB : boolean := false);
port (
clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
rd_amount : in std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
wr : in std_logic;
stall : in std_logic;
empty : out std_logic;
full : out std_logic;
input : in std_logic_vector(parallel_io*data_width-1 downto 0);
output : out std_logic_vector(parallel_io*data_width-1 downto 0);
count : out std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
valid_out : out std_logic_vector(parallel_io-1 downto 0));
end fifo_vr;
architecture BARREL_SHIFTER of fifo_vr is
type data_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0);
signal count_s : unsigned(bitsNeeded(parallel_io*2)-1 downto 0);
signal count_r : unsigned(bitsNeeded(parallel_io*2)-1 downto 0);
signal front : unsigned(bitsNeeded(parallel_io-1)-1 downto 0);
signal regs : data_array(0 to parallel_io*2-1);
signal valid_wr : std_logic;
signal valid_rd : std_logic;
signal full_s : std_logic;
signal empty_s : std_logic;
signal valid : std_logic_vector(0 to parallel_io*2-1);
signal valid_shifted : std_logic_vector(0 to parallel_io*2-1);
signal valid_aligned : std_logic_vector(0 to parallel_io-1);
signal valid_out_s : std_logic_vector(0 to parallel_io-1);
signal inputs : data_array(0 to parallel_io-1);
signal window_reset : std_logic;
--signal rd_amount_s : integer range 0 to parallel_io;
signal rd_amount_s : unsigned(bitsNeeded(parallel_io)-1 downto 0);
signal output_unaligned : std_logic_vector(PARALLEL_IO*2*data_width-1 downto 0);
signal output_aligned : std_logic_vector(PARALLEL_IO*2*data_width-1 downto 0);
signal output_valid : std_logic;
signal en : std_logic;
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_rd_en : std_logic;
signal fifo_rd_data : std_logic_vector(input'range);
begin
-- buffers input to decouple reads and writes
-- previously, full depended on rd_en, which caused timing problems
U_INPUT_FIFO : entity work.fifo
generic map (
width => input'length,
depth => 4, -- can probably be shrunk to 2 buts needs testing
same_cycle_output => true)
port map (
clk => clk,
rst => rst,
rd => fifo_rd_en,
wr => valid_wr,
empty => fifo_empty,
full => fifo_full,
almost_full => open,
input => input,
output => fifo_rd_data);
fifo_rd_en <= not fifo_empty and not full_s;
en <= not stall;
empty_s <= not valid(0) or stall;
--empty_s <= not valid(0);
empty <= empty_s;
-- the buffer is full when any of the valid bits in the upper half are
-- asserted, but not when there is a valid read that resets the window
full_s <= (valid(parallel_io) and not (valid_rd and window_reset) and
not empty_s) or stall;
--full <= full_s;
full <= fifo_full;
-- check for valid rd/wr to avoid data loss
--valid_wr <= wr and not full_s;
valid_wr <= wr and not fifo_full;
valid_rd <= '1' when rd = '1' and empty_s = '0' and unsigned(rd_amount) > 0 else '0';
count <= (others => '0') when empty_s = '1' else std_logic_vector(count_r(count'range)) when count_r <= parallel_io else std_logic_vector(to_unsigned(parallel_io, count'length));
valid_out <= valid_out_s;
-- the window position is reset any time front extends past the first half
window_reset <= '0' when front + rd_amount_s < parallel_io else '1';
-- devectorize the input vector into an array based on the whether or not
-- the first input is at the MSB or LDB
U_INPUT0_AT_MSB : if (INPUT0_AT_MSB) generate
process(fifo_rd_data)
begin
for i in 0 to parallel_io-1 loop
inputs(i) <= fifo_rd_data(input'length-i*data_width-1 downto input'length-(i+1)*data_width);
end loop;
end process;
end generate;
U_INPUT0_AT_LSB : if (INPUT0_AT_MSB = false) generate
process(fifo_rd_data)
begin
for i in 0 to parallel_io-1 loop
inputs(i) <= fifo_rd_data((i+1)*data_width-1 downto i*data_width);
end loop;
end process;
end generate;
-- update the count
process(count_r, rd_amount_s, valid_rd, fifo_rd_en)
begin
count_s <= count_r;
-- if (valid_wr = '1') then
if (fifo_rd_en = '1') then
if (valid_rd = '1') then
count_s <= count_r + parallel_io - rd_amount_s;
else
count_s <= count_r + parallel_io;
end if;
end if;
-- if (valid_rd = '1' and valid_wr = '0') then
if (valid_rd = '1' and fifo_rd_en = '0') then
count_s <= count_r - rd_amount_s;
end if;
end process;
-- make sure rd_amount can't exceed number of valid outputs
process(rd_amount, count_r)
begin
if (unsigned(rd_amount) > count_r) then
if (count_r > parallel_io) then
rd_amount_s <= to_unsigned(parallel_io, rd_amount_s'length);
else
rd_amount_s <= count_r(rd_amount'range);
end if;
else
rd_amount_s <= unsigned(rd_amount);
end if;
end process;
-- vectorize the registers for input to the shifter
process(regs)
begin
for i in 0 to PARALLEL_IO*2-1 loop
output_unaligned(output_unaligned'length-(i*data_width)-1 downto output_unaligned'length-(i+1)*data_width) <= regs(i);
end loop;
end process;
-- realign the window so the first element is on the left
U_LEFT_SHIFT_DATA : entity work.left_shift
generic map (
shift_bits => bitsNeeded(PARALLEL_IO-1),
word_width => data_width,
num_words => 2*PARALLEL_IO)
port map (
clk => clk,
rst => rst,
en => en,
input => output_unaligned,
output => output_aligned,
shift_amount => std_logic_vector(front),
valid_in => valid_rd,
valid_out => output_valid);
U_LEFT_SHIFT_VALID : entity work.left_shift
generic map (
shift_bits => bitsNeeded(PARALLEL_IO-1),
word_width => 1,
num_words => 2*PARALLEL_IO)
port map (
clk => clk,
rst => rst,
en => en,
input => valid,
output => valid_shifted,
shift_amount => std_logic_vector(front),
valid_in => valid_rd,
valid_out => open);
-- actual valid bits are in the top half of the shifter output
valid_aligned <= valid_shifted(0 to PARALLEL_IO-1);
-- reorder the outputs based on the OUTPUT0_AT_MSB setting
process(output_aligned, output_valid, valid_aligned)
begin
if (OUTPUT0_AT_MSB) then
output <= output_aligned(output_aligned'length-1 downto output_aligned'length/2);
for i in 0 to PARALLEL_IO-1 loop
--valid_out_s(i) <= valid_aligned(PARALLEL_IO-i-1) and output_valid;
valid_out_s(i) <= valid_aligned(i) and output_valid;
end loop;
else
for i in 0 to PARALLEL_IO-1 loop
-- reverse the order of the words in the outputs
output((i+1)*data_width-1 downto i*data_width) <= output_aligned(output_aligned'length-i*data_width-1 downto output_aligned'length-(i+1)*data_width);
valid_out_s(parallel_io-i-1) <= valid_aligned(i) and output_valid;
end loop;
end if;
end process;
-- track the front of the window
process(clk, rst)
variable new_front : unsigned(rd_amount_s'range);
begin
if (rst = '1') then
for i in 0 to parallel_io*2-1 loop
regs(i) <= (others => '0');
valid(i) <= '0';
end loop;
front <= (others => '0');
count_r <= (others => '0');
elsif (rising_edge(clk)) then
count_r <= count_s;
-- during a read, slide the front of the window so the next output
-- is aligned properly.
if (valid_rd = '1') then
if (window_reset = '0') then
new_front := front + rd_amount_s;
front <= new_front(front'range);
--front <= front + rd_amount_s;
--assert(new_front(new_front'length-1) = '0') report integer'image(to_integer(new_front)) severity failure;
else
new_front := front + rd_amount_s - parallel_io;
front <= new_front(front'range);
--assert(new_front(new_front'length-1) = '0') severity failure;
end if;
end if;
-- check if the bottom half is empty. All parallel_io valid bits
-- of each half should be the same, so only the first bit has to be
-- checked
if (valid(0) = '0' or
(valid_rd = '1' and window_reset = '1')) then
-- move the top half to the bottom.
for i in 0 to parallel_io-1 loop
regs(i) <= regs(i+parallel_io);
valid(i) <= valid(i+parallel_io);
end loop;
-- reset the valid bits for the top half
for i in parallel_io to parallel_io*2-1 loop
valid(i) <= '0';
end loop;
end if;
-- write new data to the top half of buffer
--if (valid_wr = '1') then
if (fifo_rd_en = '1') then
for i in 0 to parallel_io-1 loop
regs(i+parallel_io) <= inputs(i);
valid(i+parallel_io) <= '1';
end loop;
end if;
end if;
end process;
end BARREL_SHIFTER;
|
gpl-3.0
|
eab901cc136b50cd13d54a775a0886ae
| 0.54981 | 3.941082 | false | false | false | false |
tuura/fantasi
|
dependencies/shift-register-enable.vhdl
| 1 | 1,111 |
-- Generic size shift register for enabling the nodes inside the network
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_shift_register_enable IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
SHF_EN : IN std_logic;
DIN : IN std_logic;
DOUT : OUT std_logic_vector(N-1 downto 0));
END Generic_shift_register_enable;
ARCHITECTURE structural OF Generic_shift_register_enable IS
COMPONENT ffd_en is
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic
);
end COMPONENT;
SIGNAL data : std_logic_vector(N downto 0);
BEGIN
REG_GENERATOR : for i in 0 to N-1 generate
FFD_I : ffd_en PORT MAP (
CLK => CLK,
RST => RST,
EN => SHF_EN,
D => data(i),
Q => data(i+1));
DOUT(i) <= data(i+1);
END GENERATE;
data(0) <= DIN;
END structural;
|
mit
|
d28af36ca71a257b8f6e579f78d223cf
| 0.540054 | 3.326347 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,386 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RD_DATA_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
997c2d7033356f9cb7691aea20e3702e
| 0.503074 | 3.92215 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/DMA_READ_QUEUE/simulation/fg_tb_top.vhd
| 1 | 5,679 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 85
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
871e730f9a07e549a67d34b2331827a8
| 0.616306 | 4.175735 | false | false | false | false |
csrhau/sandpit
|
VHDL/stencil_buffer/stencil_buffer.vhdl
| 1 | 2,667 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- NB in practice the stencil buffer shouldn't expose all these values;
-- More commonly, the stencil buffer will be a stencil engine, and produce
-- A single output based on some f(tl, tc, tr... br)
-- This file exists to help understand and iron out offsets
entity stencil_buffer is
generic (
addr_bits : natural
);
port (
clock : in std_logic;
advance: in std_logic;
input : in std_logic_vector;
tl : out std_logic_vector;
tc : out std_logic_vector;
tr : out std_logic_vector;
ml : out std_logic_vector;
mc : out std_logic_vector;
mr : out std_logic_vector;
bl : out std_logic_vector;
bc : out std_logic_vector;
br : out std_logic_vector
);
end entity stencil_buffer;
architecture behavioural of stencil_buffer is
type direction_t is (NORTH_WEST, NORTH, NORTH_EAST,
WEST, CENTER, EAST,
SOUTH_WEST, SOUTH, SOUTH_EAST);
function offset_addr(address: std_logic_vector; direction: direction_t) return natural is
variable offset : natural range 1 to 9;
begin
case direction is
when NORTH_WEST => offset := 9;
when NORTH => offset := 8;
when NORTH_EAST => offset := 7;
when WEST => offset := 6;
when CENTER => offset := 5;
when EAST => offset := 4;
when SOUTH_WEST => offset := 3;
when SOUTH => offset := 2;
when SOUTH_EAST => offset := 1;
end case;
return to_integer(unsigned(address) - offset);
end function offset_addr;
type neighbourhood_t is array(integer range 0 to (2**addr_bits-1)) of std_logic_vector(input'range);
signal neighbourhood : neighbourhood_t := (others => (others => '0'));
signal head : std_logic_vector(addr_bits-1 downto 0) := (others => '0');
begin
SEQUENTIAL: process(clock) begin
if rising_edge(clock) then
if advance = '1' then
neighbourhood(to_integer(unsigned(head))) <= input;
head <= std_logic_vector(unsigned(head) + 1);
end if;
end if;
end process;
COMBI: process (head) begin
tl <= neighbourhood(offset_addr(head, NORTH_WEST));
tc <= neighbourhood(offset_addr(head, NORTH));
tr <= neighbourhood(offset_addr(head, NORTH_EAST));
ml <= neighbourhood(offset_addr(head, WEST));
mc <= neighbourhood(offset_addr(head, CENTER));
mr <= neighbourhood(offset_addr(head, EAST));
bl <= neighbourhood(offset_addr(head, SOUTH_WEST));
bc <= neighbourhood(offset_addr(head, SOUTH));
br <= neighbourhood(offset_addr(head, SOUTH_EAST));
end process;
end behavioural;
|
mit
|
a516f7155a301777d545b5925fea7061
| 0.635171 | 3.719665 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/TargetCmdFIFO/example_design/TargetCmdFIFO_top.vhd
| 1 | 4,956 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: TargetCmdFIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity TargetCmdFIFO_top is
PORT (
CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end TargetCmdFIFO_top;
architecture xilinx of TargetCmdFIFO_top is
SIGNAL clk_i : std_logic;
component TargetCmdFIFO is
PORT (
CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : TargetCmdFIFO PORT MAP (
CLK => clk_i,
ALMOST_FULL => almost_full,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
4d3a8ea5c0f9a3f681c75a20d9792f0f
| 0.524213 | 5.046843 | false | false | false | false |
tuura/fantasi
|
dependencies/delayer.vhdl
| 1 | 935 |
-- FFD to delay a signals of N clock cycles
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Delayer IS
GENERIC (N : integer := 1);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic;
DOUT : OUT std_logic);
END Delayer;
ARCHITECTURE structural OF Delayer IS
COMPONENT ffd is
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic
);
end COMPONENT;
SIGNAL data : std_logic_vector(N downto 0);
BEGIN
REG_GENERATOR : for i in 0 to N-1 generate
FFD_I : ffd PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
D => data(i),
Q => data(i+1));
END GENERATE;
data(0) <= DIN;
DOUT <= data(N);
END structural;
|
mit
|
e2e321324b108820b5a4d2cca627a93e
| 0.495187 | 3.292254 | false | false | false | false |
PiJoules/Zybo-Vision-Processing
|
hdmi_passthrough_720p.srcs/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/synth/design_1_dvi2rgb_0_0.vhd
| 1 | 7,037 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.4
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_dvi2rgb_0_0 IS
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC
);
END design_1_dvi2rgb_0_0;
ARCHITECTURE design_1_dvi2rgb_0_0_arch OF design_1_dvi2rgb_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dvi2rgb_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT dvi2rgb IS
GENERIC (
kEmulateDDC : BOOLEAN;
kRstActiveHigh : BOOLEAN;
kClkRange : INTEGER;
kIDLY_TapValuePs : INTEGER;
kIDLY_TapWidth : INTEGER
);
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
SerialClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END COMPONENT dvi2rgb;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dvi2rgb_0_0_arch: ARCHITECTURE IS "dvi2rgb,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dvi2rgb_0_0_arch : ARCHITECTURE IS "design_1_dvi2rgb_0_0,dvi2rgb,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N";
ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T";
BEGIN
U0 : dvi2rgb
GENERIC MAP (
kEmulateDDC => true,
kRstActiveHigh => true,
kClkRange => 2,
kIDLY_TapValuePs => 78,
kIDLY_TapWidth => 5
)
PORT MAP (
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
TMDS_Data_p => TMDS_Data_p,
TMDS_Data_n => TMDS_Data_n,
RefClk => RefClk,
aRst => aRst,
aRst_n => '1',
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => PixelClk,
aPixelClkLckd => aPixelClkLckd,
DDC_SDA_I => DDC_SDA_I,
DDC_SDA_O => DDC_SDA_O,
DDC_SDA_T => DDC_SDA_T,
DDC_SCL_I => DDC_SCL_I,
DDC_SCL_O => DDC_SCL_O,
DDC_SCL_T => DDC_SCL_T,
pRst => pRst,
pRst_n => '1'
);
END design_1_dvi2rgb_0_0_arch;
|
unlicense
|
b99e06201128191a6f638e4279d7c007
| 0.688504 | 3.45459 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/i_fetch_q_efficient_r2.vhd
| 1 | 11,508 |
-------------------------------------------------------------------------------
-- Design : Instruction Fetch Queue i_fetch_q
-- Project : Tomasulo Processor
-- Author : Gandhi Puvvada
-- Company : University of Southern California
-- Date : 07/25/2008 , 7/15/2009, 6/29/2010
-- This file is same as the file dated 4/27/2010 except for a few spelling errors!
-- File : i_fetch_q_efficient_r2.vhd
-------------------------------------------------------------------------------
-- Description : This is the revised design where we eliminated all
-- barrel shifters. We read an entire cache line of 4 words
-- into the Instruction Fetch Queue.
-----------------------------------------------------------------------------
-- Solution version of the design:
-- ==============================
-- Here we fixed the following two inefficiencies and one restriction
-- which existed in the exercise version of the design (i.e. in i_fetch_q_inefficient_r2.vhd).
-- Inefficiency #1: Delay in conveying branch/jump target address to cache
-- Inefficiency #2: Delay in conveying the target instruction to the dispatch unit:
-- Restriction #1: All branch and jump target addresses shall be aligned to 4-word boundary.
-- Along with removing the inefficiency #2, we will use our forwarding (FWFT)
-- circuitry to forward the first instruction after the IFQ runs dry (becomes empty).
-- FWFT = First Word Fall Through
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all; -- use of this package is discouraged. So, without this, we need to write "unsigned(wp) - unsigned(rp)" inplace of simple "wp - rp".
-- use work.tmslopkg.all ;
entity i_fetch_q is
port (
Clk : in std_logic;
Resetb : in std_logic;
-- interface with the dispatch unit
Ifetch_Instruction : out std_logic_vector(31 downto 0);
Ifetch_PcPlusFour : out std_logic_vector(31 downto 0);
Ifetch_EmptyFlag : out std_logic;
Dis_Ren : in std_logic; -- may be active even if ifq is empty.
Dis_JmpBrAddr : in std_logic_vector(31 downto 0);
Dis_JmpBr : in std_logic;
Dis_JmpBrAddrValid : in std_logic;
-- interface with the cache unit
Ifetch_WpPcIn : out std_logic_vector(31 downto 0);
Ifetch_ReadCache : out std_logic;
-- synopsys translate_off
wp_report, rp_report, depth_report : out std_logic_vector(4 downto 0);
-- synopsys translate_on
Ifetch_AbortPrevRead : out std_logic;
Cache_Cd0 : in std_logic_vector (31 downto 0);
Cache_Cd1 : in std_logic_vector (31 downto 0);
Cache_Cd2 : in std_logic_vector (31 downto 0);
Cache_Cd3 : in std_logic_vector (31 downto 0);
Cache_ReadHit : in std_logic
);
end entity i_fetch_q;
-----------------------------------------------------------------------------
architecture i_fetch_q_arc of i_fetch_q is
-- Component declaration
component i_fetch_fifo_ram_reg_array
generic (N: integer := 2; M: integer := 32);
port (
Clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(N-1 downto 0);
dia : in std_logic_vector(M-1 downto 0);
addrb : in std_logic_vector(N-1 downto 0);
dob : out std_logic_vector(M-1 downto 0)
);
end component i_fetch_fifo_ram_reg_array;
-- local signal declarations
-- Note: The suffix "_int" means an internal local signal. Most outputs
-- may be first generated as an internal signals and then assigned to
-- their output ports.
signal wp, rp : std_logic_vector(4 downto 0);
-- Note: We are using 5-bit pointers for a 16-location fifo. It is not absolutely
-- necessary to use 5-bit pointers as it is a single clock fifo. It is possible to use
-- 4-bit pointer. However, it makes it easy to produce the full and empty flags.
-- We actually use only upper 3-bits of the 5-bit wp and 5-bit rp to compute EMPTY and FULL.
-- This solves a lot of problems we solved earlier using a 2-state state machine!
signal wp_2bit, rp_2bit : std_logic_vector(1 downto 0);
-- the 2-bit pointers (3 downto 2) that go to the four 4x32 register arrays
signal full, nearly_full, empty_int : std_logic; -- internal full and empty flags
signal wp_upper_equals_rp_upper : std_logic; -- to derive empty flag
signal wenq, renq : std_logic; -- write-eable and read-enable, q = qualified
-- synopsys translate_off
signal depth : std_logic_vector(4 downto 0); -- ----------------------------???? Try to avaoid
-- synopsys translate_on
-- instructions read from the i_fetch_q
signal instr0 : std_logic_vector(31 downto 0);
signal instr1 : std_logic_vector(31 downto 0);
signal instr2 : std_logic_vector(31 downto 0);
signal instr3 : std_logic_vector(31 downto 0);
signal bypass_fifo : std_logic; -- forwarding logic signal
signal wp_pc_int, wp_pc_int_next : std_logic_vector(31 downto 0);
-- pc associated with wp
signal rp_pc_plus_four_int : std_logic_vector(31 downto 0);
-- pc associated with rp
signal ValidJump : std_logic; -- Jump only when J, Jal or JR$31. Do not Jump when JR $RS.
begin
-- Component instantiations
ram_dp0: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd0, addrb => rp_2bit, dob => instr0);
ram_dp1: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd1, addrb => rp_2bit, dob => instr1);
ram_dp2: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd2, addrb => rp_2bit, dob => instr2);
ram_dp3: i_fetch_fifo_ram_reg_array
generic map (N => 2, M => 32)
port map(
Clka => Clk, wea => wenq, addra => wp_2bit,
dia => Cache_Cd3, addrb => rp_2bit, dob => instr3);
-- =========================
-- synopsys translate_off
wp_report <= wp; rp_report <= rp; depth_report <= depth;
-- synopsys translate_on
-- =========================
-- Two bits (3 downto 2) of the 5-bit wp counter are sent to all the dual port RAMs.
wp_2bit <= wp(3 downto 2);
rp_2bit <= rp(3 downto 2);
-- The 4 RAMs (register arrays) are organized in a lower-order interleaved fashion.
-- The lower 2 bits of the rp are used to select one instruction from the 4 instructions
-- coming out of the 4 RAMs or the four instructions given out by the instruction cache
-- in the forwarding situation.
-- =========================
-- instruction forwarding
-- =========================
bypass_fifo <= wp_upper_equals_rp_upper AND Cache_ReadHit;-- if fifo was empty, let us forward
Ifetch_Instruction_forwarding_process: process
(bypass_fifo, rp, instr0, instr1, instr2, instr3, Cache_Cd0, Cache_Cd1, Cache_Cd2, Cache_Cd3)
begin
if bypass_fifo = '1' then -- forward the instruction from the cache
case (rp(1 downto 0)) is
when "00" =>
Ifetch_Instruction <= Cache_Cd0;
when "01" =>
Ifetch_Instruction <= Cache_Cd1;
when "10" =>
Ifetch_Instruction <= Cache_Cd2;
when others =>
Ifetch_Instruction <= Cache_Cd3;
end case;
else -- use the instruction previously deposited in the fifo
case (rp(1 downto 0)) is
when "00" =>
Ifetch_Instruction <= instr0;
when "01" =>
Ifetch_Instruction <= instr1;
when "10" =>
Ifetch_Instruction <= instr2;
when others =>
Ifetch_Instruction <= instr3;
end case;
end if;
end process Ifetch_Instruction_forwarding_process;
-- =========================
-- depth, empty, full, ...etc.
-- =========================
-- synopsys translate_off
-- depth calculation and flags generation
depth <= unsigned(wp) - unsigned(rp); ---- avoid producing depth for synthesis ***********************
-- synopsys translate_on
wp_upper_equals_rp_upper <= ( -- only upper three bits!
( wp(4) XNOR rp(4) ) AND
( wp(3) XNOR rp(3) ) AND
( wp(2) XNOR rp(2) )
);
empty_int <= wp_upper_equals_rp_upper AND (NOT(Cache_ReadHit));
Ifetch_EmptyFlag <= empty_int;
-- the dispatch unit shall not consume an instruction during the
-- clock when it asserts "ValidJump" due to a successful branch
-- though the empty_flag will be inactive in that clock.
-- The empty_flag will be inactive in that clock so that the jump instruction
-- is decoded and executed by the dispatch unit.
-- Generating Signal for Valid Jump. When Instruction is Jump type and Jump Addr is valid, Jump.
ValidJump <= Dis_JmpBr AND Dis_JmpBrAddrValid;
---
full <= (
( wp(4) XOR rp(4) ) AND
( wp(3) XNOR rp(3) ) AND
( wp(2) XNOR rp(2) )
);
nearly_full <= '1' when (unsigned(wp(4 downto 2)) - unsigned(rp(4 downto 2)) = unsigned'("011") ) else '0'; -- 3 of the four rows full
Ifetch_ReadCache <= (NOT (full OR (nearly_full AND Cache_ReadHit))) OR (ValidJump);
-- =========================
-- concurrent statements to produce wenq and renq (q = qualified)
wenq <= Cache_ReadHit AND (NOT(full));
-- In the above expression for wenq, "not(full)" is
-- unnecessary as we will not activate read-cache unless we have
-- atleast a row of space_left
renq <= Dis_Ren AND (NOT(empty_int));
-- =========================
wp_pc_int_next_combinational_process: process
(wp_pc_int, wenq, ValidJump, Dis_JmpBrAddr)
begin
if ValidJump = '1' then
wp_pc_int_next <= Dis_JmpBrAddr (31 downto 4) & "0000"; -- aligned address
elsif wenq = '1' then
wp_pc_int_next <= unsigned(wp_pc_int) + 16; -- increment by 16
else
wp_pc_int_next <= wp_pc_int; -- recirculate the current value
end if;
end process wp_pc_int_next_combinational_process;
-- =========================
Clk_registers : process (Clk, Resetb)
begin
if (Resetb = '0') then
wp <= "00000";
rp <= "00000";
wp_pc_int <= X"0000_0000";
rp_pc_plus_four_int <= X"0000_0004";
elsif (Clk'event AND Clk = '1') then
wp_pc_int <= wp_pc_int_next; -- wp_pc_int_next was combinationally derived separately
if (ValidJump = '1') then -- flush the fifo
wp <= "000" & Dis_JmpBrAddr (3 downto 2); rp <= "000" & Dis_JmpBrAddr (3 downto 2);
-- Dis_JmpBrAddr (3 downto 2) is 00 or 01 or 10 or 11
-- depending on the 4-word alignment of the Dis_JmpBrAddr
-- Note: we are not using wp (1 downto 0) anywhere except for producing depth information during simulation.
-- So, wp (1 downto 0) will not be implemented anyway and it does not matter if we initiate it to "00"
-- or to Dis_JmpBrAddr (3 downto 2).
rp_pc_plus_four_int <= unsigned(Dis_JmpBrAddr) + 4;
else
if (wenq = '1') then
wp(4 downto 2) <= unsigned(wp(4 downto 2)) + 1;
end if;
if renq = '1' then
rp <= unsigned(rp) + 1;
rp_pc_plus_four_int <= unsigned(rp_pc_plus_four_int) + 4;
end if;
end if;
end if;
end process Clk_registers;
Ifetch_WpPcIn <= wp_pc_int_next;
-- send it out to the instruction cache
Ifetch_PcPlusFour <= rp_pc_plus_four_int;
-- send it out to the dispatch unit.
Ifetch_AbortPrevRead <= ValidJump;
end architecture i_fetch_q_arc;
-----------------------------------------------------------------------------
|
gpl-2.0
|
b21c19a3dffbd32c659267b70e29a01a
| 0.605579 | 3.416865 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_memory_disambiguation_add_buff_test.vhd
| 3 | 7,754 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"0180C01B_0182681B_0202601B_00000020", -- Loc 0C, 08, 04, 00
X"AC130004_AC120004_8DA90000_AC180004", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_AC09000C", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Gandhi Puvvada and Prasanjeet Das
-- Date : 07/26/09
--************************************************
-- tag opcode mnemonics result
--************************************************
-- 0 0202601B div $12, $16, $2 $12 = (16/2 = 8)
-- 1 0182681B div $13, $12, $2 $13 = (8/2 = 4)
-- 2 0180C01B div $24, $12, $0 $24 = (8/0 = FFFFFFFF)
-- 3 AC180004 sw $24, 4($0) dmem(1) = FFFFFFFF
-- 4 8DA90000 lw $9, 0($13) $9 = dmem(1) = FFFFFFFF
-- 5 AC120004 sw $18, 4($0) dmem(1)= 18
-- 6 AC130004 sw $19, 4($0) dmem(1)= 19
-- 7 AC09000C sw $9,12($0) dmem(3)= FFFFFFFF
--*************************************************
-- "lw" will be waiting for $13 for about 16 clocks
-- for address calculation.
-- 1st "sw" will be waiting for $24 for about 24 clocks
-- the last two "sw"'s will wait until the "lw" has its address
-- then the last two "sw"'s will bypass "lw", count = 2, addbuffmatch = 2
-- then the first "sw" will leave and addbuffmatch = 3
-- then the first "sw" commits and addbuffmatch = 2
-- Now that the "lw" has no "sw" older in the queue and addbuffmatch = count
-- It gets issued.
-- We can see the CDB tag and CDB valid to recognize the order of appearance on CDB
-- ==================================================================================
-- *******************************************************
-- The expected order of appearance on CDB leaving NOP's
-- ******************************************************
-- first 0 0050601B div $12, $16, $2
-- second 1 004C681B div $13, $12, $2
-- third 5 AC120004 sw $18, 4($0)
-- fourth 6 AC130004 sw $19, 4($0)
-- fifth 2 000CC01B div $24, $0, $12
-- sixth 3 AC180004 sw $24, 4($0)
-- seventh 4 8DA90000 lw $9, 0($13)
-- *****************************************************
|
gpl-2.0
|
1b23c9096410e3aea9fe65d8bf46d27e
| 0.625742 | 3.089243 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/user_code.vhd
| 1 | 7,865 |
---------------------------------------------------------
-- Здес код, который может использовать все утсройства --
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity user_code is
port(
buttons: in std_logic_vector(7 downto 0);
led: out std_logic_vector(7 downto 0);
web_output_write_o: out std_logic;
web_output_data_o: out std_logic_vector(7 downto 0);
web_output_ready_i: in std_logic;
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
-- PS/2
web_ps2_kbd_data: inout std_logic;
web_ps2_kbd_clk: inout std_logic;
ps2_data1: inout std_logic;
ps2_clk1: inout std_logic;
ps2_data2: inout std_logic;
ps2_clk2: inout std_logic;
reset_o: out std_logic;
-- 50 Mhz
clk: in std_logic
);
end user_code;
architecture Behavioral of user_code is
signal reset : std_logic := '1';
type state is (s_wait, s_data, s_done);
signal ps2d_out, ps2c_out,
ps2d_i, ps2c_i,
idle, rx_done,
tx_wr_ps2, tx_done: std_logic;
signal rx_data, tx_data: std_logic_vector(7 downto 0);
type state_type is (send_ED, rec_ack, send_lock, wait_send);
signal s : state_type := send_ED;
signal led_kbd, led_shift: std_logic_vector(7 downto 0) := (others => '0');
begin
reset_o <= reset;
reset_proc: process(clk)
variable counter: unsigned(1 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if counter = "11" then
reset <= '0';
else
reset <= '1';
counter := counter + 1;
end if;
end if;
end process;
web_ps2_kbd_data <= '0' when ps2d_out = '0' else 'Z';
web_ps2_kbd_clk <= '0' when ps2c_out = '0' else 'Z';
ps2d_i <= '0' when web_ps2_kbd_data = '0' else '1';
ps2c_i <= '0' when web_ps2_kbd_clk = '0' else '1';
---- ![не проходит один такт, проверить на физ клавиатуре]! --
inst_ps2_rx: entity work.ps2_rx
port map (
clk => clk,
reset => reset,
ps2d => ps2d_i,
ps2c => ps2c_i,
rx_en => idle,
rx_done => rx_done,
dout => rx_data
);
inst_ps2_tx: entity work.ps2_tx
port map (
clk => clk,
reset => reset,
ps2d_out => ps2d_out,
ps2c_out => ps2c_out,
ps2d_in => ps2d_i,
ps2c_in => ps2c_i,
tx_idle => idle,
din => tx_data,
wr_ps2 => tx_wr_ps2,
tx_done => tx_done
);
proc_out: process(reset, clk)
begin
if reset = '1' then
web_output_write_o <= '0';
elsif rising_edge(clk) then
web_output_write_o <= '0';
if rx_done = '1' then
web_output_data_o <= rx_data;
web_output_write_o <= '1';
end if;
end if;
end process;
led <= led_shift;
proc_rx: process(reset, clk)
variable realesed, ext_code: boolean;
begin
if reset = '1' then
led_kbd <= (others => '0');
realesed := false;
ext_code := false;
led_shift <= (others => '0');
elsif rising_edge(clk) then
tx_wr_ps2 <= '0';
case s is
when send_ED =>
if rot_center = '1' then
tx_data <= X"F4";
tx_wr_ps2 <= '1';
s <= rec_ack;
elsif buttons(4) = '1' then
tx_data <= X"AA";
tx_wr_ps2 <= '1';
s <= rec_ack;
elsif rx_done='1' then
if realesed then
realesed := false;
elsif ext_code then
case rx_data is
-- left
when X"6B" =>
led_shift <= led_shift(6 downto 0) & '1';
-- right
when X"74" =>
led_shift <= '0' & led_shift(7 downto 1);
when others => null;
end case;
ext_code := false;
else
case rx_data is
when X"77" =>
led_kbd(1) <= not led_kbd(1);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"7E" =>
led_kbd(0) <= not led_kbd(0);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"58" =>
led_kbd(2) <= not led_kbd(2);
tx_data <= X"ED";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"5A" =>
tx_data <= X"EE";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"76" =>
tx_data <= X"FF";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"05" =>
tx_data <= X"FE";
tx_wr_ps2 <= '1';
s <= rec_ack;
when X"E0" =>
ext_code := true;
when X"F0" =>
realesed := true;
when others => null;
end case;
end if;
end if;
when rec_ack =>
if rx_done = '1' then
if tx_data = X"ED" and rx_data = X"FA" then
s <= send_lock;
else
s <= send_ED;
end if;
end if;
when send_lock =>
tx_data <= led_kbd;
tx_wr_ps2 <= '1';
s <= wait_send;
when wait_send =>
if tx_done = '1' then
s <= send_ED;
end if;
end case;
end if;
end process;
-- proc_rx: process(reset, ps2c_i)
-- variable counter: unsigned(2 downto 0);
-- begin
-- if reset = '1' then
-- rx_done <= '0';
-- rx_data <= (others => '0');
-- elsif rising_edge(ps2c_i) then
-- rx_done <= '0';
-- if idle = '1' then
-- case s is
-- when s_wait =>
-- if ps2d_i = '0' then
-- s <= s_data;
-- counter := "111";
-- end if;
-- when s_data =>
-- rx_data <= ps2d_i & rx_data(7 downto 1);
-- if counter = "000" then
-- s <= s_done;
-- else
-- counter := counter - "001";
-- end if;
-- when s_done =>
-- rx_done <= '1';
-- --led <= rx_data;
-- s <= s_wait;
-- end case;
-- end if;
-- end if;
-- end process;
-- proc_tx: process(reset, ps2c_i)
-- variable counter: unsigned(3 downto 0);
-- begin
-- if reset = '1' then
-- idle <= '1';
-- s_tx <= s_wait;
-- state_send <= s_wait;
-- ps2d_out <= 'Z';
-- ps2c_out <= 'Z';
-- led <= (others => '0');
-- elsif rising_edge(ps2c_i) then
-- web_output_write_o <= '0';
-- case s_tx is
-- when s_wait =>
-- idle <= '1';
-- if rx_done = '1' then
-- s_tx <= s_data;
-- tx_data <= rx_data;
-- counter := "0000";
-- idle <= '0';
-- ps2c_out <= '0';
-- state_send <= s_wait;
-- end if;
-- when s_data =>
-- if counter = "0001" then
-- ps2c_out <= 'Z';
-- ps2d_out <= '0';
-- elsif counter > "0001" and counter < "1010" then
-- ps2d_out <= tx_data(0);
-- tx_data <= '0' & tx_data(7 downto 1);
-- elsif counter = "1010" then
-- if ps2d_i = '0' then
-- web_output_data_o <= "00000001";
-- web_output_write_o <= '1';
-- end if;
-- s_tx <= s_done;
-- end if;
-- counter := counter + 1;
-- when s_done =>
-- ps2d_out <= 'Z';
-- ps2c_out <= 'Z';
-- s_tx <= s_wait;
-- end case;
-- end if;
-- end process;
end Behavioral;
|
mit
|
630006a0506218acccba0d709df56c75
| 0.429618 | 3.106629 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/simulation/random.vhd
| 4 | 4,108 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Random Number Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: random.vhd
--
-- Description:
-- Random Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RANDOM IS
GENERIC ( WIDTH : INTEGER := 32;
SEED : INTEGER :=2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END RANDOM;
ARCHITECTURE BEHAVIORAL OF RANDOM IS
BEGIN
PROCESS(CLK)
VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
VARIABLE TEMP : STD_LOGIC := '0';
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH);
ELSE
IF(EN = '1') THEN
TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2);
RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0);
RAND_TEMP(0) := TEMP;
END IF;
END IF;
END IF;
RANDOM_NUM <= RAND_TEMP;
END PROCESS;
END ARCHITECTURE;
|
gpl-2.0
|
9d70ddb291f9cde7c56794e07fd9de12
| 0.59445 | 4.711009 | false | false | false | false |
tuura/fantasi
|
dependencies/zero_comparator.vhdl
| 1 | 512 |
-- Generic comparator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Generic_zero_comparator IS
GENERIC (N : integer := 8);
PORT (
OP : IN std_logic_vector(N-1 downto 0);
EN : IN std_logic;
EQ : OUT std_logic);
END Generic_zero_comparator;
ARCHITECTURE structural OF Generic_zero_comparator IS
SIGNAL equals : std_logic;
BEGIN
equals <= '1' when (OP = (OP'range => '0')) else '0';
EQ <= EN AND equals;
END structural;
|
mit
|
02c05c4a2f97daebba4f78177f1782e2
| 0.605469 | 3.482993 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/write_data_fifo/simulation/fg_tb_synth.vhd
| 2 | 11,499 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 13,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : write_data_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
8869541c23917c181829443c8583698c
| 0.456388 | 3.958348 | false | false | false | false |
BBN-Q/APS2-TDM
|
testbenches/EthernetFrame.vhd
| 1 | 4,428 |
--- Package for handling APS ethernet frames
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package EthernetFrame is
type MACAddr_t is array(0 to 5) of std_logic_vector(7 downto 0);
type APSCommand_t is record
ack : std_logic;
seq : std_logic;
sel : std_logic;
rw : std_logic;
cmd : std_logic_vector(3 downto 0);
mode : std_logic_vector(7 downto 0);
cnt : std_logic_vector(15 downto 0);
end record;
type APSEthernetFrameHeader_t is record
destMAC : MACAddr_t;
srcMAC : MACAddr_t;
seqNum : unsigned(15 downto 0);
command : APSCommand_t;
addr : std_logic_vector(31 downto 0);
end record;
type APSPayload_t is array(integer range <>) of std_logic_vector(7 downto 0);
procedure write_MAC_addr(macAddr : in MACAddr_t; signal mac_rx : out std_logic_vector(7 downto 0); signal clk : in std_logic);
procedure write_ethernet_frame_header(destMAC : in MACAddr_t; srcMAC : in MACAddr_t; frameType : in std_logic_vector(15 downto 0); signal mac_rx : out std_logic_vector(7 downto 0); signal clk : in std_logic);
procedure write_APS_command(cmd : in APSCommand_t; signal mac_rx : out std_logic_vector(7 downto 0); signal clk : in std_logic);
procedure write_APSEthernet_frame(frame : in APSEthernetFrameHeader_t; payload : in APSPayload_t; signal mac_rx : out std_logic_vector(7 downto 0);
signal clk : in std_logic; signal rx_valid : out std_logic; signal rx_eop : out std_logic; seqNum : in natural := 0; badFCS : in boolean := false; signal mac_fcs : out std_logic );
end EthernetFrame;
package body EthernetFrame is
procedure write_MAC_addr(macAddr : in MACAddr_t; signal mac_rx : out std_logic_vector(7 downto 0); signal clk : in std_logic) is
begin
for ct in 0 to 5 loop
mac_rx <= macAddr(ct); wait until rising_edge(clk);
end loop;
end procedure write_MAC_addr;
procedure write_ethernet_frame_header(destMAC : in MACAddr_t; srcMAC : in MACAddr_t; frameType : in std_logic_vector(15 downto 0); signal mac_rx : out std_logic_vector(7 downto 0); signal clk : in std_logic) is
begin
write_MAC_addr(destMAC, mac_rx, clk);
write_MAC_addr(srcMAC, mac_rx, clk);
mac_rx <= frameType(15 downto 8); wait until rising_edge(clk);
mac_rx <= frameType(7 downto 0); wait until rising_edge(clk);
end procedure write_ethernet_frame_header;
procedure write_APS_command(cmd : in APSCommand_t; signal mac_rx : out std_logic_vector(7 downto 0); signal clk : in std_logic) is
begin
mac_rx <= cmd.ack & cmd.seq & cmd.sel & cmd.rw & cmd.cmd; wait until rising_edge(clk);
mac_rx <= cmd.mode; wait until rising_edge(clk);
mac_rx <= cmd.cnt(15 downto 8); wait until rising_edge(clk);
mac_rx <= cmd.cnt(7 downto 0); wait until rising_edge(clk);
end procedure write_APS_command;
procedure write_APSEthernet_frame(frame : in APSEthernetFrameHeader_t; payload : in APSPayload_t; signal mac_rx : out std_logic_vector(7 downto 0);
signal clk : in std_logic; signal rx_valid : out std_logic; signal rx_eop : out std_logic; seqNum : in natural := 0; badFCS : in boolean := false; signal mac_fcs : out std_logic ) is
variable seqNum_u : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(seqNum, 16));
begin
rx_valid <= '1';
write_ethernet_frame_header(frame.destMAC, frame.srcMAC, x"BB4E", mac_rx, clk);
--seq. num.
mac_rx <= seqNum_u(15 downto 8); wait until rising_edge(clk);
mac_rx <= seqNum_u(7 downto 0); wait until rising_edge(clk);
--command
write_APS_command(frame.command, mac_rx, clk);
--address
for ct in 4 downto 1 loop
if (payload'length = 0) and (ct = 1) then
rx_valid <= '0';
end if;
mac_rx <= frame.addr(ct*8-1 downto (ct-1)*8); wait until rising_edge(clk);
--if there is no payload then the packet ends here
end loop;
-- clock in the payload
for ct in payload'range loop
--deassert valid for last byte until frame check is finished
if ct = payload'right then
rx_valid <= '0';
end if;
mac_rx <= payload(ct); wait until rising_edge(clk);
end loop;
--Frame check sequence
rx_valid <= '0';
for ct in 1 to 4 loop
wait until rising_edge(clk);
end loop;
--Signal end of packet
rx_valid <= '1';
rx_eop <= '1';
if badFCS then
mac_fcs <= '1';
end if;
wait until rising_edge(clk);
rx_valid <= '0';
rx_eop <= '0';
mac_fcs <= '0';
wait until rising_edge(clk);
--Interframe gap of four beats
for ct in 1 to 4 loop
wait until rising_edge(clk);
end loop;
end procedure write_APSEthernet_frame;
end package body;
|
mpl-2.0
|
a5acbb6896b88f2282573405d988cd2f
| 0.701445 | 2.991892 | false | false | false | false |
csrhau/sandpit
|
VHDL/data_types/test_typecasts.vhdl
| 1 | 1,684 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity test_typecasts is
end test_typecasts;
architecture behavioural of test_typecasts is
constant natural_value : natural range 255 downto 0 := 164;
constant slv_value : std_logic_vector(7 downto 0) := "10100100";
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
begin
process
variable natural_holder : natural range 255 downto 0;
variable slv_holder : std_logic_vector(7 downto 0);
variable oline: line;
begin
natural_holder := to_integer(unsigned(slv_value));
assert natural_holder = natural_value
report "1 natural and slv should match" severity error;
slv_holder := std_logic_vector(to_unsigned(natural_value, slv_holder'length));
assert slv_holder = slv_value
report "2 slv and natural should match" severity error;
write(oline, str(slv_holder));
write(oline, '=');
write(oline, str(slv_value));
writeline(output, oline);
wait;
end process;
end behavioural;
|
mit
|
6991007247e11f8e280e8a8d60950a50
| 0.593824 | 3.530398 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/ps2/ps2_rx.vhd
| 1 | 2,702 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ps2_rx is
port (
clk, reset: in std_logic; -- System clock and reset
ps2d, ps2c: in std_logic; -- PS/2 data and clock signals
rx_en: in std_logic; -- Receiver enabled/disabled signal
rx_done: out std_logic; -- End of transmission signal
dout: out std_logic_vector(7 downto 0) -- Output buffer
);
end ps2_rx;
architecture behavioral of ps2_rx is
-- State machine
type state is (idle, busy, done);
signal state_reg, state_next: state;
-- Counter from 9 to 0 - 4 bits should be enough
signal counter_reg, counter_next: unsigned(3 downto 0);
-- Data buffer
signal buf_reg, buf_next: std_logic_vector(10 downto 0);
-- Falling edge detector signals
signal fall_edge: std_logic;
signal ps2_edge: std_logic_vector(1 downto 0);
begin
-- falling edge detector using shift buffer
edge_detector: process(clk, reset)
begin
if reset = '1' then
ps2_edge <= (others => '0');
elsif rising_edge(clk) then
ps2_edge <= ps2_edge(0) & ps2c;
end if;
end process;
fall_edge <= '1' when ps2_edge(1) = '1' and ps2_edge(0) = '0' else '0';
-- clock based state changer
clk_process: process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
buf_reg <= (others => '0');
counter_reg <= (others => '0');
elsif rising_edge(clk) then
state_reg <= state_next;
buf_reg <= buf_next;
counter_reg <= counter_next;
end if;
end process;
state_machine: process(state_reg, fall_edge, rx_en, ps2d, buf_reg, counter_reg)
begin
-- setting default values
state_next <= state_reg;
buf_next <= buf_reg;
counter_next <= counter_reg;
rx_done <= '0';
case (state_reg) is
-- waiting for falling edge and start bit
when idle =>
if rx_en = '1' and fall_edge = '1' and ps2d = '0' then
state_next <= busy;
counter_next <= "1001"; -- 9 bits to go
-- loading bits into buffer
buf_next <= ps2d & buf_reg(10 downto 1);
end if;
-- receiving bits
when busy =>
if fall_edge = '1' then
-- loading bits into buffer
buf_next <= ps2d & buf_reg(10 downto 1);
-- simple counter
if counter_reg = 0 then
state_next <= done;
else
counter_next <= counter_reg - 1;
end if;
end if;
-- end of transmission
when done =>
state_next <= idle;
rx_done <= '1';
end case;
end process;
dout <= buf_reg(8 downto 1); -- output from shift register
end behavioral;
|
mit
|
a24947298767583f972b46eb912e4f38
| 0.579571 | 3.495472 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/top_cpu_slow_r1.vhd
| 1 | 36,608 |
------------------------------------------------------------------------------
-- File name: top_cpu.vhd
-- Function : Top file for the Tomasulo CPU project with file i/o
-- Modified by : Prasanjeet Das
-- Date : 7/20/09, 7/24/09, 7/25/09
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all; -- Xilinx primitive BUFGP
entity top_cpu is
port (
CLK_PORT : in std_logic;
sw0, sw1, sw2, sw3, sw4, sw5, sw6, sw7 : in std_logic; --changed by PRASANJEET
btn3 : in std_logic;
btn2 : in std_logic;
btn1, btn0 : in std_logic;
St_ce_bar, St_rp_bar, Mt_ce_bar, Mt_St_we_bar, Mt_St_oe_bar : out std_logic;
LD7, LD6, LD5, LD4, LD3, LD2, LD1, LD0 : out std_logic;
ca, cb, cc, cd, ce, cf, cg, dp : out std_logic;
AN0, AN1, AN2, AN3 : out std_logic;
------------------------------------------------------------------------
-- Epp-like bus signals (ports to connect to the Cypress USB intrerface)
EppAstb: in std_logic; -- Address strobe --changed by PRASANJEET
EppDstb: in std_logic; -- Data strobe --changed by PRASANJEET
EppWr : in std_logic; -- Port write signal --changed by PRASANJEET
EppDB : inout std_logic_vector(7 downto 0); -- port data bus --changed by PRASANJEET
EppWait: out std_logic; -- Port wait signal --changed by PRASANJEET
------------------------------------------------------------------------
-- user extended signals
Led : in std_logic_vector(7 downto 0); -- 0x01 8 virtual LEDs on the PC I/O Ex GUI --changed by PRASANJEET
LBar : in std_logic_vector(23 downto 0); -- 0x02..4 24 lights on the PC I/O Ex GUI light bar --changed by PRASANJEET
Sw : out std_logic_vector(15 downto 0); -- 0x05..6 16 switches, bottom row on the PC I/O Ex GUI --changed by PRASANJEET
dwOut: out std_logic_vector(31 downto 0); -- 0x09..b 32 Bits user output --changed by PRASANJEET
dwIn : in std_logic_vector(31 downto 0) -- 0x0d..10 32 Bits user input --changed by PRASANJEET
);
end top_cpu ;
------------------------------------------------------------------------------
architecture top_cpu_arc of top_cpu is
SIGNAL clock_half : std_logic ;
signal Resetb : std_logic;
signal BCLK : std_logic;
signal BCLK_TEMP : std_logic;
-- signals to go into the logic under test
signal clk_top, resetb_top : std_logic;
-- component declarations
component tomasulo_top
port (
Reset : in std_logic;
--digi_address : in std_logic_vector(5 downto 0); -- input ID for the register we want to see
--digi_data : out std_logic_vector(31 downto 0); -- output data given by the register
Clk : in std_logic;
--modified by Prasanjeet
-- signals corresponding to Instruction memory
fio_icache_addr_IM : in std_logic_vector(5 downto 0); --changed by PRASANJEET
fio_icache_data_in_IM : in std_logic_vector(127 downto 0); --changed by PRASANJEET
fio_icache_wea_IM : in std_logic; --changed by PRASANJEET
fio_icache_data_out_IM : out std_logic_vector(127 downto 0); --changed by PRASANJEET
fio_icache_ena_IM : in std_logic; -- changed by PRASANJEET
fio_dmem_addr_DM : in std_logic_vector(5 downto 0); --changed by PRASANJEET
fio_dmem_data_out_DM : out std_logic_vector(31 downto 0); --changed by PRASANJEET
fio_dmem_data_in_DM : in std_logic_vector(31 downto 0); --changed by PRASANJEET
fio_dmem_wea_DM : in std_logic; --changed by PRASANJEET
Test_mode : in std_logic; -- for using the test mode
walking_led_start : out std_logic
-- end modified by Prasanjeet
);
end component ;
-- debouncer
component ee560_debounce is
generic (N_dc: positive := 23);
port (CLK, RESETB_DEBOUNCE :in std_logic; -- CLK = 50 MHz
PB :in std_logic; -- push button
DPB, SCEN, MCEN, CCEN :out std_logic );
end component ee560_debounce ;
--bufgp for clock
component BUFGP
port (I: in std_logic; O: out std_logic);
end component;
component BUFG
port (I: in std_logic; O: out std_logic);
end component;
--signals for file i/o
signal Addr_Mem_IM, Addr_Mem_DM, Addr_Mem : std_logic_vector(5 downto 0); -- address going to user memory -- here it is 4 bits
signal WE_Mem_IM, WE_Mem_DM: std_logic; -- Write Enable, Read Enable control signals to user memory
signal Data_to_Mem_IM, Data_to_Mem: std_logic_vector(127 downto 0); -- data to be written to memory
signal Data_to_Mem_DM : std_logic_vector(31 downto 0);
signal Data_from_Mem_IM, Data_from_Mem: std_logic_vector(127 downto 0); -- data to be read from memory
signal Data_from_Mem_DM : std_logic_vector(31 downto 0);
signal test_in: std_logic;
------------
signal regEppAdr: std_logic_vector (7 downto 0); -- Epp address register
signal regVer: std_logic_vector(7 downto 0); -- 0x00 I/O returns the complement of written value -- for I/O Ex Tab
signal busEppInternal: std_logic_vector(7 downto 0); -- internal bus (before tristate)
-- added by Sabya --
signal Mem_Select_Reg: std_logic_vector (7 downto 0); -- 0x2A; we get Sel_IM_Bar_Slash_DM from this
signal Control_Reg: std_logic_vector (7 downto 0); -- 0x2B; We get test mode from this. Not needed in the current design.
-- Type declaration
type state_type is (IDLE, -- idle state(1)
A_RD_FINISH, -- finish reading from address register (2)
A_WR_START, -- start writing to address register(3)
A_WR_FINISH, -- finish writing from address register (4)
OTHER_RD_FINISH, -- finish reading from other than pointer and data memory (5)
OTHER_WR_FINISH, -- finish writing to other than pointer and data memory (6)
OTHER_WR_START, -- start writing to other than pointer and data memory (7)
PNTR_RD_START, -- start reading the memory pointer (8)
PNTR_RD_FINISH, -- finish reading the memory pointer(9)
PNTR_WR_START, -- start writing the memory pointer(10)
PNTR_WR_FINISH, -- finish writing the memory pointer(11)
M_RD_START_1_8, -- start reading data memory (12)
M_RD_FINISH_1_8, -- finish reading data memory(13)
M_RD_START_9_10, -- deals with carriage return and line feed (14)
M_RD_FINISH_9_10, -- deals with carriage return and line feed (15)
M_WR_START_1_8, -- start writing data memory (16)
M_WR_FINISH_1_8, -- finish writing data memory(17)
M_WR_START_9_10, -- deals with carriage return and line feed (18)
M_WR_FINISH_9_10, -- deals with carriage return and line feed (19)
INC_NIB_COUNT, -- increment the nibble counter (20)
INC_MEM_PNTR -- increment the mem_pointer (21)
);
-- Intermediate signal declarations
signal current_state : state_type;
--intermediate signals of the state machine
signal EN_A_RD, EN_M_RD, EN_A_WR, EN_M_WR, EN_PNTR_RD, EN_PNTR_WR, EN_OTHER_RD: std_logic; -- all the read and write enable signals
signal EN_REG_WR, EN_REG_RD: std_logic; -- read and write signals for register file
signal ASTB_S, DSTB_S, ASTB_SS, DSTB_SS : std_logic; -- signals used for double synchronizing address and data strobe
signal D_int1, D_int2, D_int3: std_logic_vector(7 downto 0); -- signals used for registering the Eppdata
signal A_int1, A_int2, A_int3: std_logic_vector(7 downto 0); -- signals used for registering the EppAddress
signal wait_Epp: std_logic; -- internal signal used for EppWait;
signal pointer: std_logic_vector(7 downto 0); -- pointer to memory
signal i: std_logic_vector(1 downto 0); --internal counter
--signal clk, resetb: std_logic; -- clk and Resetb signals
signal nib_count: std_logic_vector(5 downto 0); -- to count the nibbles
signal nib_on_file: std_logic_vector(7 downto 0); -- show the nibbles on the file
signal Sel_IM_Bar_Slash_DM: std_logic; -- A Flip-Flop Resetb or set by SW0 to select between IM/DM; -- FF output = '0' => IM, '1' => DM
-- *****************************************************************************************
-- constant declarations
-- 40, 41 for instruction memory
-- *****************************************************************************************
constant addr_mem_pointer: std_logic_vector(7 downto 0) := X"28"; --40 dec - 28 hex
constant addr_memory: std_logic_vector(7 downto 0) := X"29"; --41 dec - 29 hex
-- added by sabya
constant addr_Mem_Select_Reg: std_logic_vector(7 downto 0) := X"2A";
constant addr_Control_Reg: std_logic_vector(7 downto 0) := X"2B";
--******************************************************************************************
-- intermediate signals for data conversion
signal BINARY, binary_in : std_logic_vector(3 downto 0); -- - BINARY for FPGA ==> File and binary_in for File ==> FPGA
signal ASCII, ascii_out: std_logic_vector(7 downto 0); -- ASCII for ,File ==> FPGA and ascii_out for FPGA ==> File
signal extended_zero : std_logic_vector(95 downto 0);
-- signals used for the array of registers to store the nibbles
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
subtype reg_mem is std_logic_vector(3 downto 0); --register array declaration
type reg_type is array (0 to 31) of reg_mem;
signal reg_array : reg_type;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
signal divclk: std_logic_vector(1 downto 0); -- the divided clock
--***************************************************************
signal reset_fileio, reset_tomasulo: std_logic;
--signal r_sw2, r_sw3: std_logic; -- Resetb signals
--++++++++++++++++++++++++++++++++++++++++++++
signal walking_led: std_logic_vector(7 downto 0); -- walking led counter.
signal walking_led_en: std_logic;
signal walking_led_clk: std_logic_vector(22 downto 0);
signal w_led: std_logic_vector(2 downto 0); -- encoded walking led pattern
--++++++++++++++++++++++++++++++++++++++++++++++++
-- signals from debouncers
signal db_btn0,db_btn1: std_logic;
--++++++++++++++++++++++++++++++++++++++++++++++++++
begin
cpu_2_inst : tomasulo_top
port map (
Reset => reset_tomasulo,
Clk => clk_top,
fio_icache_addr_IM => Addr_Mem_IM, --changed by PRASANJEET
fio_icache_data_in_IM => Data_to_Mem_IM, --changed by PRASANJEET
fio_icache_wea_IM => WE_Mem_IM, --changed by PRASANJEET
fio_icache_data_out_IM => Data_from_Mem_IM,--changed by PRASANJEET
fio_icache_ena_IM => '1', -- changed by PRASANJEET
fio_dmem_addr_DM => Addr_Mem_DM,--changed by PRASANJEET
fio_dmem_data_out_DM => Data_from_Mem_DM, --changed by PRASANJEET
fio_dmem_data_in_DM => Data_to_Mem_DM, --changed by PRASANJEET
fio_dmem_wea_DM => WE_Mem_DM, --changed by PRASANJEET
Test_mode => test_in, -- changed by PRASANJEET
walking_led_start => walking_led_en --changed by PRASANJEET
);
BUF_GP_1: BUFGP port map (I => CLK_PORT, O => BCLK_TEMP);
------------
--concurrent assignments
-- send address and data to both the memories, it's the control signal WE which will determine which memory to write
Data_to_mem_IM <= Data_to_mem;
Data_to_mem_DM <= Data_to_mem(127 downto 96);
Addr_mem_IM <= Addr_mem;
Addr_mem_DM <= Addr_mem;
Data_from_mem <= Data_from_mem_IM when Sel_IM_Bar_Slash_DM = '0' else Data_from_mem_DM&extended_zero; --Data to be read from memory is sent to the file on the control of swith sw0
WE_Mem_IM <= EN_M_WR when Sel_IM_Bar_Slash_DM = '0' else '0'; -- the Sel_IM_Bar_Slash_DM is controlled by sw0
WE_Mem_DM <= EN_M_WR when Sel_IM_Bar_Slash_DM = '1' else '0';
extended_zero <= (others =>'0');
------------------------------------------------------------------------------
--Clock Divider derives slower clocks from the 50 MHz clock on s2 board
CLOCK_DIVIDER1: process (BCLK_TEMP, resetb_top)
begin
if (resetb_top = '0') then
divclk <= (others => '0');
elsif (BCLK_TEMP'event and BCLK_TEMP = '1') then
divclk <= divclk + '1';
end if;
end process CLOCK_DIVIDER1;
--da cheng july17 2011
clock_half <= divclk(1); -- this is 25MHz clock
BUF_G_3: BUFG port map (I => clock_half, O => BCLK);
---------------------------------------------------------------------
walking_led_pro: process(clk_top, resetb_top)
begin
if(resetb_top = '0')then
walking_led_clk <= (others =>'0');
elsif(clk_top'event and clk_top = '1')then
if(walking_led_en = '1')then
walking_led_clk <= walking_led_clk + '1';
end if;
end if;
end process walking_led_pro;
-- ---------------------------------------------------------
--w_led <= walking_led_clk(20 downto 18);
--Da Cheng modified at July 17 2011
w_led <= walking_led_clk(22 downto 20);
-- -- decoder to produce one hot signals
walking_led <= "00000001" when w_led = "000" else
"00000010" when w_led = "001" else
"00000100" when w_led = "010" else
"00001000" when w_led = "011" else
"00010000" when w_led = "100" else
"00100000" when w_led = "101" else
"01000000" when w_led = "110" else
"10000000" when w_led = "111" else
"11111111";
-- ----------------------------------------------------------
--
---------------------------
--concurrent assignments
Resetb <= btn3;--this is active high system Resetb
--added by PRASANJEET
-------------------------------------------------------
resetb_top <= not(btn3); --the Resetb to the debouncer (this is system reset)
-------------------------------------------------------
clk_top <= BCLK;
--process to store the nibbles into the register file
write_reg: process(clk_top)
begin
if(clk_top'event and clk_top = '1')then
if(EN_REG_WR = '1')then
reg_array(CONV_INTEGER(UNSIGNED(nib_count(4 downto 0)))) <= binary_in;
end if;
end if;
end process write_reg;
-------------------------------------------------------------------------------
-- disabling the seven segment display
ca <= '1' ;
cb <= '1' ;
cc <= '1' ;
cd <= '1' ;
ce <= '1' ;
cf <= '1' ;
cg <= '1' ;
dp <= sw3 and sw4 and sw5 and sw6 and sw7 and btn0 and btn2 ; -- just to remove the synthesis warnings let all the unused switches and buttons drive something
AN0 <= '1' ;
AN1 <= '1' ;
AN2 <= '1' ;
AN3 <= '1' ;
-- disabling the flash / memory
St_ce_bar <= '1';
Mt_ce_bar <= '1';
St_rp_bar <= '1';
Mt_St_we_bar <= '1';
Mt_St_oe_bar <= '1';
--%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
LD6 <= walking_led(6);
LD7 <= walking_led(7);-- just to check for wait signal
LD5 <= walking_led(5); LD4 <= walking_led(4);
LD3 <= walking_led(3); LD2 <= walking_led(2) ; LD1 <= walking_led(1); LD0 <= walking_led(0);
-- --****************************************************************************************************
--++++++++++++++++++++++++++++++++
Addr_mem <= pointer(5 downto 0); -- 6 bit address
--++++++++++++++++++++++++++++++++
-- Epp signals
-- Port signals
EppWait <= wait_Epp;
EppDB <= busEppInternal when (EppWr = '1') else "ZZZZZZZZ";
busEppInternal <=
regEppAdr when (EN_A_RD = '1') else
nib_on_file when (EN_M_RD = '1')else --this is the nibble being sent to the file
pointer when (EN_PNTR_RD = '1')else
--@Sabya:- add Mem_Select_Reg and Control_Reg here
Mem_Select_Reg when (EN_OTHER_RD = '1') and (regEppAdr = addr_Mem_Select_Reg) else
Control_Reg when (EN_OTHER_RD = '1') and (regEppAdr = addr_Control_Reg) else
regVer when (EN_OTHER_RD = '1') else --later on to be expanded and qualified with address (regEppAdr = x00)
Led when (regEppAdr = x"01") else
LBar(7 downto 0) when (regEppAdr = x"02") else
LBar(15 downto 8) when (regEppAdr = x"03") else
LBar(23 downto 16) when (regEppAdr = x"04") else
dwIn(7 downto 0) when (regEppAdr = x"0d") else
dwIn(15 downto 8) when (regEppAdr = x"0e") else
dwIn(23 downto 16) when (regEppAdr = x"0f") else
dwIn(31 downto 24) ;
--output function logic
EN_A_RD <= '1' when (current_state = A_RD_FINISH) else '0';
EN_OTHER_RD <= '1' when (current_state = OTHER_RD_FINISH) else '0';
EN_REG_RD <= '1'; --always read the register file
EN_REG_WR <= '1' when (current_state = M_WR_START_1_8 or current_state = M_WR_FINISH_1_8) else '0';
EN_M_RD <= '1' when (current_state = M_RD_START_1_8 or current_state = M_RD_FINISH_1_8 or current_state = M_RD_START_9_10 or current_state = M_RD_FINISH_9_10) else '0';
EN_PNTR_RD <= '1' when (current_state = PNTR_RD_START or current_state = PNTR_RD_FINISH) else '0';
EN_A_WR <= '1' when (current_state = A_WR_START or current_state = A_WR_FINISH) else '0';
EN_M_WR <= '1' when (current_state = M_WR_START_9_10 or current_state = M_WR_FINISH_9_10) else '0';
EN_PNTR_WR <= '1' when (current_state = PNTR_WR_START or current_state = PNTR_WR_FINISH) else '0';
wait_Epp <= '1' when (current_state = A_WR_FINISH or current_state = A_RD_FINISH or current_state = M_WR_FINISH_9_10 or current_state = M_RD_FINISH_9_10
or current_state = PNTR_WR_FINISH or current_state = PNTR_RD_FINISH or current_state = OTHER_WR_FINISH or current_state = OTHER_RD_FINISH
or current_state = M_WR_FINISH_1_8 or current_state = M_RD_FINISH_1_8 or current_state = INC_NIB_COUNT or current_state = INC_MEM_PNTR)
else '0';
nib_on_file <= X"0D" when ((nib_count = "001000" and Sel_IM_Bar_Slash_DM = '1') or (nib_count = "100000" and Sel_IM_Bar_Slash_DM = '0') )else -- carriage return --0D
X"0A" when ((nib_count = "001001" and Sel_IM_Bar_Slash_DM = '1') or (nib_count = "100001" and Sel_IM_Bar_Slash_DM = '0') )else --line feed --0A
ascii_out; -- the nibble being read from memory
--***********************************************************
ascii_out <= X"30" when (BINARY = "0000") else --hex 0
X"31" when (BINARY = "0001") else --hex 1
X"32" when (BINARY = "0010") else --hex 2
X"33" when (BINARY = "0011") else --hex 3
X"34" when (BINARY = "0100") else --hex 4
X"35" when (BINARY = "0101") else --hex 5
X"36" when (BINARY = "0110") else --hex 6
X"37" when (BINARY = "0111") else --hex 7
X"38" when (BINARY = "1000") else --hex 8
X"39" when (BINARY = "1001") else --hex 9
X"41" when (BINARY = "1010") else --hex A
X"42" when (BINARY = "1011") else --hex B
X"43" when (BINARY = "1100") else --hex C
X"44" when (BINARY = "1101") else --hex D
X"45" when (BINARY = "1110") else --hex E
X"46" when (BINARY = "1111") else --hex F
X"37";
binary_in <= "0000" when (ASCII = X"30") else
"0001" when (ASCII = X"31") else
"0010" when (ASCII = X"32") else
"0011" when (ASCII = X"33") else
"0100" when (ASCII = X"34") else
"0101" when (ASCII = X"35") else
"0110" when (ASCII = X"36") else
"0111" when (ASCII = X"37") else
"1000" when (ASCII = X"38") else
"1001" when (ASCII = X"39") else
"1010" when (ASCII = X"41") else
"1011" when (ASCII = X"42") else
"1100" when (ASCII = X"43") else
"1101" when (ASCII = X"44") else
"1110" when (ASCII = X"45") else
"1111" when (ASCII = X"46") else
"0110";
--************************************************************
BINARY <= Data_from_mem(3 downto 0) when (nib_count = "011111")else
Data_from_mem(7 downto 4) when (nib_count = "011110")else
Data_from_mem(11 downto 8) when (nib_count = "011101")else
Data_from_mem(15 downto 12) when (nib_count = "011100")else
Data_from_mem(19 downto 16) when (nib_count = "011011")else
Data_from_mem(23 downto 20) when (nib_count = "011010")else
Data_from_mem(27 downto 24) when (nib_count = "011001")else
Data_from_mem(31 downto 28) when (nib_count = "011000")else
Data_from_mem(35 downto 32) when (nib_count = "010111")else
Data_from_mem(39 downto 36) when (nib_count = "010110")else
Data_from_mem(43 downto 40) when (nib_count = "010101")else
Data_from_mem(47 downto 44) when (nib_count = "010100")else
Data_from_mem(51 downto 48) when (nib_count = "010011")else
Data_from_mem(55 downto 52) when (nib_count = "010010")else
Data_from_mem(59 downto 56) when (nib_count = "010001")else
Data_from_mem(63 downto 60) when (nib_count = "010000")else
Data_from_mem(67 downto 64) when (nib_count = "001111")else
Data_from_mem(71 downto 68) when (nib_count = "001110")else
Data_from_mem(75 downto 72) when (nib_count = "001101")else
Data_from_mem(79 downto 76) when (nib_count = "001100")else
Data_from_mem(83 downto 80) when (nib_count = "001011")else
Data_from_mem(87 downto 84) when (nib_count = "001010")else
Data_from_mem(91 downto 88) when (nib_count = "001001")else
Data_from_mem(95 downto 92) when (nib_count = "001000")else
Data_from_mem(99 downto 96) when (nib_count = "000111")else
Data_from_mem(103 downto 100) when (nib_count = "000110")else
Data_from_mem(107 downto 104) when (nib_count = "000101")else
Data_from_mem(111 downto 108) when (nib_count = "000100")else
Data_from_mem(115 downto 112) when (nib_count = "000011")else
Data_from_mem(119 downto 116) when (nib_count = "000010")else
Data_from_mem(123 downto 120) when (nib_count = "000001")else
Data_from_mem(127 downto 124) when (nib_count = "000000")else
"1010";
-- notice that we start with most significant nibble and end with the least significant nibble
--clocked process with asynchronous active low Resetb for double synchronization
double_sync: process (clk_top, reset_fileio) --double synchronizing to safeguard against metastability
begin
if (reset_fileio = '0') then
ASTB_S <= '1';
DSTB_S <= '1';
ASTB_SS <= '1';
DSTB_SS <= '1';
elsif (clk_top'event and clk_top = '1') then
ASTB_S <= EppAstb;
ASTB_SS <= ASTB_S;
DSTB_S <= EppDstb;
DSTB_SS <= DSTB_S;
end if;
end process double_sync;
-- clocked process with asynchronous active low Resetb for combined CU and DPU
CU_DPU: process (clk_top, reset_fileio)
begin
if (reset_fileio = '0') then
current_state <= IDLE;
i <= (others => 'X');
pointer <= (others => '0');
nib_count <= (others=> '0');
D_int1 <= (others => 'X');
D_int2 <= (others => 'X');
D_int3 <= (others => 'X');
A_int1 <= (others => 'X');
A_int2 <= (others => 'X');
A_int3 <= (others => 'X');
ASCII <= (others =>'X');
regver <=(others =>'X');
--added by sabya
Mem_Select_Reg <= (others =>'X');
Control_Reg <= (others =>'X');
regEppAdr <= (others =>'X');
elsif (clk_top'event and clk_top = '1') then
case (current_state) is
when IDLE => --(1)
-- CU state transitions
if(ASTB_SS = '0')then -- if adress strobe asserted and intent to write
if(EppWr = '0')then
current_state <= A_WR_START;
else
current_state <= A_RD_FINISH;
end if;
elsif(DSTB_SS = '0')then -- if data strobe asserted and intent to write
if(EppWr = '0')then
if(regEppAdr = addr_memory)then
if(((nib_count = "001001" and Sel_IM_Bar_Slash_DM = '1')or (nib_count = "100001" and Sel_IM_Bar_Slash_DM = '0')) or ((nib_count = "001000" and Sel_IM_Bar_Slash_DM = '1' )or(nib_count = "100000" and Sel_IM_Bar_Slash_DM = '0')))then -- for nibble count >= 8(DM) or >= 32(IM)
current_state <= M_WR_START_9_10;
else
current_state <= M_WR_START_1_8;
end if;
elsif(regeppadr = addr_mem_pointer)then
current_state <= PNTR_WR_START;
else
current_state <= OTHER_WR_START;
end if;
else -- if data strobe asserted and intent to read
if(regeppadr = addr_memory)then
if(((nib_count = "001001" and Sel_IM_Bar_Slash_DM = '1')or (nib_count = "100001" and Sel_IM_Bar_Slash_DM = '0')) or ((nib_count = "001000" and Sel_IM_Bar_Slash_DM = '1' )or(nib_count = "100000" and Sel_IM_Bar_Slash_DM = '0')))then -- for nibble count >= 8(DM) or >= 32(IM)
current_state <= M_RD_START_9_10;
else
current_state <= M_RD_START_1_8;
end if;
elsif(regeppadr = addr_mem_pointer)then
current_state <= PNTR_RD_START;
else
current_state <= OTHER_RD_FINISH;
end if;
end if;
elsif (ASTB_SS = '1' and DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
i <= (others => '0');
when A_RD_FINISH => --(2)
-- CU state transitions
if (ASTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
i <= (others => '0');
when A_WR_START => --(3)
-- CU state transitions
if ( i = "11") then
current_state <= A_WR_FINISH;
end if;
-- DPU RTL
i <= i + "01";
A_int1 <= EppDB;
A_int2 <= A_int1;
A_int3 <= A_int2;
regeppadr <= A_int3;
when A_WR_FINISH => --(4)
-- CU state transitions
if (ASTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
A_int1 <= EppDB;
A_int2 <= A_int1;
A_int3 <= A_int2;
regeppadr <= A_int3;
when OTHER_RD_FINISH => --(5)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
-- NO DPU RTL
when OTHER_WR_START => --(6)
-- CU state transitions
if ( i = "11") then
current_state <= OTHER_WR_FINISH;
end if;
-- DPU RTL
i <= i + "01";
D_int1 <= EppDB; --applicable only for regeppaddr = x00
D_int2 <= D_int1;
D_int3 <= D_int2;
--@Sabya:- qualify this with regEppadr
-- default - regver
-- 0x2A - Mem_select_reg
-- 0x2B - Control_register
case regEppAdr is
when addr_Mem_Select_Reg => Mem_Select_Reg <= D_int3;
when addr_Control_Reg => Control_Reg <= D_int3;
when others => regver <= not(D_int3);
end case;
when OTHER_WR_FINISH => --(7)
-- CU state transitions
if (DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
D_int1 <= EppDB; --applicable only for regeppaddr = x00
D_int2 <= D_int1;
D_int3 <= D_int2;
--@Sabya:- qualify this with regEppadr
-- default - regver
-- 0x2A - Mem_select_reg
-- 0x2B - Control_register
case regEppAdr is
when addr_Mem_Select_Reg => Mem_Select_Reg <= D_int3;
when addr_Control_Reg => Control_Reg <= D_int3;
when others => regver <= not(D_int3);
end case;
when PNTR_RD_START => --(8)
-- CU state transitions
if ( i = "11") then
current_state <= PNTR_RD_FINISH;
end if;
-- DPU RTL
i <= i + "01";
when PNTR_RD_FINISH => --(9)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
--NO DPU RTL
when PNTR_WR_START => --(10)
-- CU state transitions
if ( i = "11") then
current_state <= PNTR_WR_FINISH;
end if;
-- DPU RTL
i <= i + "01";
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
Pointer <= D_int3;
when PNTR_WR_FINISH => --(11)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= IDLE;
end if;
-- DPU RTL
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
Pointer <= D_int3;
when M_RD_START_1_8 => --(12)
-- CU state transitions
if ( i = "11") then
current_state <= M_RD_FINISH_1_8;
end if;
-- DPU RTL
i <= i + "01";
when M_RD_FINISH_1_8 => --(13)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
--NO DPU RTL
when M_RD_START_9_10 => --(14)
-- CU state transitions
if ( i = "11") then
current_state <= M_RD_FINISH_9_10;
end if;
-- DPU RTL
i <= i + "01";
when M_RD_FINISH_9_10 => --(15)
-- CU state transitions
if ( DSTB_SS = '1') then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
--NO DPU RTL
when M_WR_START_1_8 => --(16)
-- CU state transitions
if ( i = "11") then
current_state <= M_WR_FINISH_1_8;
end if;
-- DPU RTL
i <= i + "01";
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
ASCII <= D_int3; -- the data read from the file
when M_WR_FINISH_1_8 => --(17)
-- CU state transitions
if(DSTB_SS = '1')then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
D_int1 <= EppDB;
D_int2 <= D_int1;
D_int3 <= D_int2;
ASCII <= D_int3; -- the data read from the file
when M_WR_START_9_10 => --(18)
-- CU state transitions
if ( i = "11") then
current_state <= M_WR_FINISH_9_10;
end if;
-- DPU RTL
i <= i + "01";
Data_to_mem <= reg_array(0)®_array(1)®_array(2)®_array(3)®_array(4)®_array(5)®_array(6)®_array(7)
& reg_array(8)®_array(9)®_array(10)®_array(11)®_array(12)®_array(13)®_array(14)®_array(15)
& reg_array(16)®_array(17)®_array(18)®_array(19)®_array(20)®_array(21)®_array(22)®_array(23)
& reg_array(24)®_array(25)®_array(26)®_array(27)®_array(28)®_array(29)®_array(30)®_array(31);
when M_WR_FINISH_9_10 => --(19)
-- CU state transitions
if(DSTB_SS = '1')then
current_state <= INC_NIB_COUNT;
end if;
-- DPU RTL
Data_to_mem <= reg_array(0)®_array(1)®_array(2)®_array(3)®_array(4)®_array(5)®_array(6)®_array(7)
& reg_array(8)®_array(9)®_array(10)®_array(11)®_array(12)®_array(13)®_array(14)®_array(15)
& reg_array(16)®_array(17)®_array(18)®_array(19)®_array(20)®_array(21)®_array(22)®_array(23)
& reg_array(24)®_array(25)®_array(26)®_array(27)®_array(28)®_array(29)®_array(30)®_array(31);
when INC_NIB_COUNT => --(20)
-- CU state transitions
if((nib_count < "001001" and Sel_IM_Bar_Slash_DM = '1') or (nib_count < "100001" and Sel_IM_Bar_Slash_DM = '0'))then
current_state <= IDLE;
else
current_state <= INC_MEM_PNTR;
end if;
-- DPU RTL
nib_count <= nib_count + "000001";
when INC_MEM_PNTR => --(21)
-- CU state transitions
current_state <= IDLE;
-- DPU RTL
pointer <= pointer + "00000001";
nib_count <= "000000";
when others =>
current_state <= IDLE;
end case;
end if;
end process CU_DPU;
--@Sabya: Changed this so that it comes from the PC
Sel_IM_Bar_Slash_DM <= Mem_Select_Reg(0);
test_in<= Control_Reg(0);
reset_tomasulo<=Control_Reg(1);
--process to store the data sent by sw0 into a register sel_IM_Slash_DM
-- Sel_IM_Bar_Slash_DM_process: process (clk_top)
-- begin
-- if (clk_top'event and clk_top = '1') then
-- Sel_IM_Bar_Slash_DM <= sw0;
-- test_in <= sw1; -- NOTE test mode is set by switch 1.
-- reset_tomasulo <= sw2; --reset_tomasulo
--r_sw2 <= sw2;
--r_sw3 <= sw3;
-- end if;
-- end process Sel_IM_Bar_Slash_DM_process;
btn1_debouncer: ee560_debounce --btn1 used as Resetb for fileio
generic map (N_dc => 25)
port map (clk => clk_top, RESETB_DEBOUNCE => reset_fileio, -- CLK = 50 MHz
PB => btn1,
DPB => db_btn1, SCEN => open, MCEN => open, CCEN => open );
reset_fileio <= not(db_btn1);
end top_cpu_arc ;
------------------------------------------------------------------------------
|
gpl-2.0
|
6dfe7fcc256d37d4de031b1212ac0984
| 0.495274 | 3.666667 | false | false | false | false |
csrhau/sandpit
|
VHDL/GOL_simple/test_multicell.vhdl
| 1 | 3,784 |
package gol_types is
type grid_state is array(3 downto 0, 3 downto 0) of integer range 0 to 1;
end package gol_types;
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.gol_types.all;
entity test_multicell is
end test_multicell;
architecture behavioural of test_multicell is
signal clock : std_logic;
component cell is
generic (
begin_alive : integer range 0 to 1
);
port (
clock : in std_logic;
nw, nn, ne : in integer range 0 to 1;
ww, ee : in integer range 0 to 1;
sw, ss, se : in integer range 0 to 1;
alive: out integer range 0 to 1
);
end component;
function print_state(mat: grid_state)
return integer is
variable l : line;
begin
writeline (output, l);
for i in 3 downto 0 loop
for j in 3 downto 0 loop
write (l, ' ');
write (l, mat(i,j));
end loop;
writeline (output, l);
end loop;
return 0;
end print_state;
signal interconnect: grid_state;
begin
ROW:
for ROW in 0 to 1 generate
COL:
for COL in 0 to 1 generate
cell_xx: cell generic map (begin_alive => 0)
port map (clock,
interconnect(ROW + 0, COL + 0), interconnect(ROW + 0, COL + 1), interconnect(ROW + 0, COL + 2),
interconnect(ROW + 1, COL + 0), interconnect(ROW + 1, COL + 2),
interconnect(ROW + 2, COL + 0), interconnect(ROW + 2, COL + 1), interconnect(ROW + 2, COL + 2),
interconnect(ROW + 1, COL + 1));
end generate COL;
end generate ROW;
-- Starts dead test
process
variable dummy: integer range 0 to 1;
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert interconnect = ((0, 0, 0, 0),
(0, 0, 0, 0),
(0, 0, 0, 0),
(0, 0, 0, 0))
report "Board should start dead" severity error;
interconnect(0, 0) <= 1;
interconnect(0, 1) <= 1;
interconnect(0, 2) <= 1;
interconnect(0, 3) <= 1;
clock <= '0';
wait for 1 ns;
dummy := print_state(interconnect);
clock <= '1';
wait for 1 ns;
dummy := print_state(interconnect);
-- note downto ordering
assert interconnect = ((0, 0, 0, 0),
(0, 0, 0, 0),
(0, 1, 1, 0),
(1, 1, 1, 1))
report "Board should come alive" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
dummy := print_state(interconnect);
assert interconnect = ((0, 0, 0, 0),
(0, 0, 0, 0),
(0, 0, 0, 0),
(1, 1, 1, 1))
report "Board should die back" severity error;
interconnect(0, 0) <= 0;
interconnect(0, 1) <= 0;
interconnect(0, 2) <= 0;
interconnect(0, 3) <= 0;
interconnect(0, 0) <= 1;
interconnect(0, 1) <= 1;
interconnect(1, 0) <= 1;
interconnect(3, 2) <= 1;
interconnect(3, 3) <= 1;
interconnect(2, 3) <= 1;
clock <= '0';
wait for 1 ns;
assert interconnect = ((1, 1, 0, 0),
(1, 0, 0, 0),
(0, 0, 0, 1),
(0, 0, 1, 1))
report "Board should have reset to new test pattern" severity error;
dummy := print_state(interconnect);
clock <= '1';
wait for 1 ns;
dummy := print_state(interconnect);
assert interconnect = ((1, 1, 0, 0),
(1, 1, 0, 0),
(0, 0, 1, 1),
(0, 0, 1, 1));
wait;
end process;
end behavioural;
|
mit
|
e509428c541be75dba318fb96f975cf9
| 0.493922 | 3.65251 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_command_rec_fifo/simulation/fg_tb_top.vhd
| 1 | 6,308 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
bf9b57de58bdc8bf92447d1bc77b62ff
| 0.609068 | 4.106771 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RESPONSE_QUEUE/simulation/fg_tb_synth.vhd
| 1 | 10,349 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : RESPONSE_QUEUE_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
a36c82b2f2aae083257b85eae28ce8e6
| 0.460431 | 4.113275 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/read_data_fifo/simulation/fg_tb_top.vhd
| 4 | 6,020 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
75a9ab9814bc7e6444f5b973617e3131
| 0.61196 | 4.095238 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_POST_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,391 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RD_FLASH_POST_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
2c2edcabbaa2aee6ffe2194871c86bc2
| 0.502941 | 3.923872 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_selective_flushing_memory_disambiguation.vhd
| 3 | 8,800 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"008C6819_0202601B_00000020_00000020", -- Loc 0C, 08, 04, 00
X"11C40006_AC0C0000_8C890000_0182701B", -- Loc 1C, 18, 14, 10 -- corrected
X"8C840000_00030820_00020820_00232819", -- Loc 2C, 28, 24, 20
X"AC050014_AC0E0010_AC0C0010_0242601B", -- Loc 3C, 38, 34, 30
X"00000020_AC0C0020_AC04001C_AC010018", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"0180C01B_0182681B_0202601B_00000020", -- Loc 6C, 68, 64, 60
X"AC130004_AC120004_8DA90000_AC180004", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_AC09000C", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Sukhun Kang
-- Date : 07/27/09
--0202601B DIV $12, $16, $2 $12 = 16/2 = 8
--006C6819 MUL $13, $4, $12 $13 = 8*4 = 32
--0182701B DIV $14, $12, $2 $14 = 8/2 = 4
--8C890000 LW $9, 0($4) $9 = dmem(1) = 16
--AC0C0000 SD $12, 0($0) dmem(0) = 8
--11C40006 BEQ $14, $4, 6 IF $4 = $14, jump to the instruction after SD $12, 4($0) skips 6 instructions
--00232819 MUL $5, $1, $3 $5 = 1*3 = 3 * should be flushed*
--00020820 ADD $1, $0, $2 $1 = 0+2 = 2 *should be flushed*
--00030820 ADD $1, $0, $3 $1 = 0+3 = 3* should be flushed*
--8C840000 LD $4, 0($4) $4 = dmem(1) = 8 *should be flushed*
--0242601B DIV $12, $18, $2 $12 = 18/2 = 9 *should flushed*
--AC0C0010 SD $12, 16($0) dmem(4) = 9 *should flushed*
--AC0E0010 SD $14, 16($0) dmem(4) = 4 BRANCH TARGET
--AC050014 SD $5, 20($0) dmem(5) = $5 = 5 not 3
--AC010018 SD $1, 24($0) dmem(6) = $1 = 1 not 3
--AC04001C SD $4, 28($0) dmem(7) = $4 = 4 not 8
--AC0C0020 SD $12, 32($0) dmem(8) = $12 = 8 not 9
--************************************************
--************************************************
-- tag opcode mnemonics result
--************************************************
-- 0 0202601B div $12, $16, $2 $12 = (16/2 = 8)
-- 1 0182681B div $13, $12, $2 $13 = (8/2 = 4)
-- 2 0180C01B div $24, $12, $0 $24 = (8/0 = FFFFFFFF)
-- 3 AC180004 sw $24, 4($0) dmem(1) = FFFFFFFF
-- 4 8DA90000 lw $9, 0($13) $9 = dmem(1) = FFFFFFFF
-- 5 AC120004 sw $18, 4($0) dmem(1)= 18
-- 6 AC130004 sw $19, 4($0) dmem(1)= 19
-- 7 AC09000C sw $9, 12($0) dmem(3)= FFFFFFFFF
--*************************************************
-- "lw" will be waiting for $13 for about 16 clocks
-- for address calculation.
-- 1st "sw" will be waiting for $24 for about 24 clocks
-- the last two "sw"'s will wait until the "lw" has its address
-- then the last two "sw"'s will bypass "lw", count = 2, addbuffmatch = 2
-- then the first "sw" will leave and addbuffmatch = 3
-- then the first "sw" commits and addbuffmatch = 2
-- Now that the "lw" has no "sw" older in the queue and addbuffmatch = count
-- It gets issued.
-- We can see the CDB tag and CDB valid to recognize the order of appearance on CDB
-- ==================================================================================
-- *******************************************************
-- The expected order of appearance on CDB leaving NOP's
-- ******************************************************
-- first 0 0050601B div $12, $2, $16
-- second 1 004C681B div $13, $2, $12
-- third 5 AC120004 sw $18, 4($0)
-- fourth 6 AC130004 sw $19, 4($0)
-- fifth 2 000CC01B div $24, $0, $12
-- sixth 3 AC180004 sw $24, 4($0)
-- seventh 4 8DA90000 lw $9, 0($13)
-- *****************************************************
|
gpl-2.0
|
d32b88b735f29440ba582e782f4e870c
| 0.607614 | 2.912943 | false | false | false | false |
csrhau/sandpit
|
VHDL/GOL_simple/test_multicell_boundaries.vhdl
| 1 | 4,993 |
package gol_types is
constant ROWS: integer := 5;
constant COLS: integer := 5;
type board_state is array(ROWS downto 0, COLS downto 0) of integer range 0 to 1;
constant GLIDER: board_state := ((0, 0, 0, 0, 0, 0),
(0, 0, 1, 0, 0, 0),
(0, 0, 0, 1, 0, 0),
(0, 1, 1, 1, 0, 0),
(0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0));
end package gol_types;
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.gol_types.all;
entity test_multicell_boundaries is
end test_multicell_boundaries;
architecture behavioural of test_multicell_boundaries is
signal clock : std_logic;
component cell is
generic (
begin_alive : integer range 0 to 1
);
port (
clock : in std_logic;
nw, nn, ne : in integer range 0 to 1;
ww, ee : in integer range 0 to 1;
sw, ss, se : in integer range 0 to 1;
alive: out integer range 0 to 1
);
end component;
function print_state(mat: board_state)
return integer is
variable l : line;
begin
writeline (output, l);
for i in ROWS downto 0 loop
for j in COLS downto 0 loop
write (l, ' ');
write (l, mat(i,j));
end loop;
writeline (output, l);
end loop;
return 0;
end print_state;
signal interconnect: board_state;
begin
ROW:
for row in 0 to ROWS generate
COL:
for col in 0 to COLS generate
cellx: cell generic map (begin_alive => GLIDER(row, col))
port map (clock,
interconnect((row - 1) mod ROWS, (col - 1) mod COLS), interconnect((row - 1) mod ROWS, col), interconnect((row - 1) mod ROWS, (col + 1) mod COLS),
interconnect(row, (col - 1) mod COLS), interconnect(row, (col + 1) mod COLS),
interconnect((row + 1) mod ROWS, (col - 1) mod COLS), interconnect((row + 1) mod ROWS, col), interconnect((row + 1) mod ROWS, (col + 1) mod COLS),
interconnect(row, col));
end generate COL; -- COLS
end generate ROW; -- ROWS
-- Starts dead test
process
variable dummy: integer range 0 to 1;
constant T0: board_state := GLIDER;
constant T1: board_state := ((0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0),
(0, 1, 0, 1, 0, 0),
(0, 0, 1, 1, 0, 0),
(0, 0, 1, 0, 0, 0),
(0, 0, 0, 0, 0, 0));
constant T2: board_state := ((0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0),
(0, 0, 0, 1, 0, 0),
(0, 1, 0, 1, 0, 0),
(0, 0, 1, 1, 0, 0),
(0, 0, 0, 0, 0, 0));
constant T3: board_state := ((0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0),
(0, 0, 1, 0, 0, 0),
(0, 0, 0, 1, 1, 0),
(0, 0, 1, 1, 0, 0),
(0, 0, 0, 0, 0, 0));
-- T4 is the end of a cycle - glider is period 4.
constant T4: board_state := ((0, 0, 0, 0, 0, 0),
(0, 0, 0, 0, 0, 0),
(0, 0, 0, 1, 0, 0),
(0, 0, 0, 0, 1, 0),
(0, 0, 1, 1, 1, 0),
(0, 0, 0, 0, 0, 0));
begin
assert interconnect = T0
report "Board should start as glider" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert interconnect = T1
report "Board should proceed to state T1" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert interconnect = T2
report "Board should proceed to state T2" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert interconnect = T3
report "Board should proceed to state T3" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert interconnect = T4
report "Board should proceed to state T4" severity error;
-- At this point we've proven the glider progresses through one of its cycles,
-- but we still need to see it navigate the entire space and return to start.
-- This takes an extra 16 steps.
for i in 1 to 16 loop
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
end loop;
assert interconnect = T0
report "Board should proceed to state T4" severity error;
wait;
end process;
end behavioural;
|
mit
|
5edbfc2d40e68a4d53dbb4e3e6fc4903
| 0.457841 | 3.745686 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/tx_buf/simulation/fg_tb_top.vhd
| 2 | 5,967 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 101
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
f1dcd84dfe1563bc07c27425d52d14e9
| 0.613038 | 4.184432 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_lws.vhd
| 3 | 7,214 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (just sws)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/27/2008
--
----------------------------------------------------------
--- EXPECTED RESULT
-- Physical register values changes as follows :
-- 32 => 00000010(h)
-- 33 => 00000020(h)
-- 34 => 00000030(h)
-- 35 => 00000040(h)
-- 36 => 00000050(h)
-- 37 => 00000060(h)
-- 38 => 00000070(h)
-- 39 => 00000080(h)
-- 40 => 00000001(h)
-- 41 => 00000002(h)
-- 42 => 000000B0(h)
-- 43 => 000000C0(h)
-- 44 => 000000D0(h)
-- 45 => 000000E0(h)
-- 46 => 000000F0(h)
-- 47 => 00000100(h)
------------------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"8C9E000C_8C9E0008_8C9E0004_8C9E0000", -- Loc 0C, 08, 04, 00
X"8C9E001C_8C9E0018_8C9E0014_8C9E0010", -- Loc 1C, 18, 14, 10
X"8C9E002C_8C9E0028_8C9E0024_8C9E0020", -- Loc 2C, 28, 24, 20
X"8C9E003C_8C9E0038_8C9E0034_8C9E0030", -- Loc 3C, 38, 34, 30
-- 16 sw instructions changing 16 locations with the content of $30 which is decimal 30 (1D hex)
-- "00000000000000000000000000011110", -- $30
-- Location:() | LW $30 ,0( $4) -- 8C9E0000
-- Location:() | LW $30 ,4( $4) -- 8C9E0004
X"00000020_00000020_00000020_00000020", --- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- similar lines as above which read a word from the memory,
-- increment it, and then store it back to the same location.
-- There is only a RAW hazard, but other cases of memory disambiguation are not covered here.
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for a package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
gpl-2.0
|
757f585c666fc257fcd9985654489c4c
| 0.634184 | 2.954136 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/fifo_generator_v9_3/simulation/fifo_generator_v9_3_dverif.vhd
| 1 | 5,873 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_generator_v9_3_pkg.ALL;
ENTITY fifo_generator_v9_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fifo_generator_v9_3_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
apache-2.0
|
2c8012fa3297e4f555309ff28bec00c0
| 0.569726 | 3.978997 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/modulo1KHz.vhd
| 1 | 4,489 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: modulo1KHz.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity modulo1KHz is
Port ( clk_50MHz : in STD_LOGIC;
rst : in STD_LOGIC;
clk_1KHz : out STD_LOGIC;
pulso_1KHz : out STD_LOGIC);
end modulo1KHz;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of modulo1KHz is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal ena_aux: std_logic_vector(1 downto 0);
signal pulso_aux: std_logic;
signal force_rst: std_logic;
signal ff_startV3: std_logic;
-----------------------------------------------------------------------------
-- Declaracion de componentes
-----------------------------------------------------------------------------
COMPONENT cont255_V2
PORT(
clk : IN std_logic;
rst : IN std_logic;
ena: in std_logic;
fin : OUT std_logic
);
END COMPONENT;
COMPONENT cont255_V3
PORT(
clk : IN std_logic;
rst : IN std_logic;
ena : IN std_logic;
fin : OUT std_logic
);
END COMPONENT;
COMPONENT cont255_V4
PORT(
clk : IN std_logic;
rst : IN std_logic;
set_zero: in std_logic;
start : IN std_logic;
fin : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
pulso_1KHz <= pulso_aux;
force_rst <= rst or pulso_aux;
clk_1KHz <= pulso_aux;
-----------------------------------------------------------------------------
-- Instancia de componentes
-----------------------------------------------------------------------------
cont255_0: cont255_V2 port map(
clk => clk_50MHz,
rst => force_rst,
ena => '1',
fin => ena_aux(0)
);
cont255_153: cont255_V3 PORT MAP(
clk => clk_50MHz,
rst => force_rst,
ena => ena_aux(0),
fin => ena_aux(1)
);
cont255_2: cont255_V4 PORT MAP(
clk => clk_50MHz,
rst => rst,
set_zero => force_rst,
start => ff_startV3,
fin => pulso_aux
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_ff_startV3: process(clk_50MHz, force_rst)
begin
if force_rst = '1' then
ff_startV3 <= '0';
elsif rising_edge(clk_50MHz) then
if ena_aux(1) = '1' then
ff_startV3 <= '1';
else
ff_startV3 <= ff_startV3;
end if;
end if;
end process p_ff_startV3;
end rtl;
|
gpl-3.0
|
47187a23f67b974b5022cd4256a52eae
| 0.462001 | 4.446977 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/web_led.vhd
| 1 | 1,072 |
----------------------------------------------------------------------------------
-- Óñòðîéñòâî: ñâåòîäèîäû
-- Êîä: 0õ02
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity web_led is
port (
data_o: out std_logic_vector(7 downto 0); -- âûõîä
data_i: in std_logic_vector(7 downto 0); -- äàííûå íà óðîâíå ïëàòû
strobe_o: out std_logic;
ack_i: in std_logic;
rst_i: in std_logic;
clk: in std_logic
);
end web_led;
architecture LedArch of web_led is
begin
proc: process(clk, ack_i, rst_i)
variable prev_data: unsigned(7 downto 0) := (others => '0');
begin
if ack_i = '1' then
strobe_o <= '0';
elsif rst_i = '1' then
data_o <= X"00";
strobe_o <= '0';
elsif rising_edge(clk) then
if prev_data /= unsigned(data_i) then
prev_data := unsigned(data_i);
strobe_o <= '1';
data_o <= data_i;
end if;
end if;
end process;
end LedArch;
|
mit
|
7e497b412518f2956741f49afa65937f
| 0.505597 | 3.288344 | false | false | false | false |
tuura/fantasi
|
dependencies/comparator.vhdl
| 1 | 706 |
-- Generic comparator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Generic_comparator IS
GENERIC (N : integer := 8);
PORT (
AOP : IN std_logic_vector(N-1 downto 0);
BOP : IN std_logic_vector(N-1 downto 0);
EN : IN std_logic;
EQ : OUT std_logic);
END Generic_comparator;
ARCHITECTURE structural OF Generic_comparator IS
SIGNAL wires : std_logic_vector(N-1 downto 0);
SIGNAL equals : std_logic;
BEGIN
XNOR_GEN : for i in 0 to N-1 generate
wires(i) <= AOP(i) XNOR BOP(i);
end generate;
equals <= '1' when (wires = (wires'range => '1')) else '0';
EQ <= EN AND equals;
END structural;
|
mit
|
0cb007ab4da47f59cf62c283e55e6b5b
| 0.597734 | 3.283721 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/FIFO_DDR_DATA_IN/simulation/fg_tb_pkg.vhd
| 1 | 11,334 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT FIFO_DDR_DATA_IN_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
215e27b2e472e8cde00b7d3cb76104a8
| 0.503794 | 3.916379 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/master_control_signal_generator.vhd
| 1 | 7,036 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- master_control_signal_generator.vhd aka MCSG
--
-- Recv's commands from pport. Controls other components. Startup delay.
--
--**********************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.common.all;
use work.comp_pckgs.all;
ENTITY master_control_signal_generator IS
PORT
(
clk_50Mhz: in std_logic;
clk_12_5Mhz : in std_logic;
clk_pp: in std_logic;
rst: in std_logic;
cmd: in std_logic_vector(5 downto 0);
start_upload: out std_logic;
abort_upload: out std_logic;
start_addr: out std_logic_vector(22 downto 0);
end_addr: out std_logic_vector(22 downto 0);
init_cycle_complete: out std_logic;
init_KAC : out std_logic;
sync_KAC : out std_logic; -- out KAC sync pin
start_KAC : out std_logic;
done_KAC : in std_logic;
r_w_KAC : out std_logic; -- 0=read 1=write
Addr_KAC : out std_logic_vector(7 downto 0);
Data_KAC_in : out std_logic_vector(7 downto 0);
Data_KAC_out: in std_logic_vector(7 downto 0)
);
END master_control_signal_generator;
ARCHITECTURE MCSG_arch OF master_control_signal_generator IS
--KAC Signals
--States to control KAC via I2C
subtype state_KAC is integer range 3 downto 0;
signal current_state_KAC, next_state_KAC: state_KAC;
signal init_cycle_complete_r : std_logic;
signal delay_start : std_logic;
signal delay_complete : std_logic;
--PP signals
-- States to read commands from pc
subtype state is integer range 15 downto 0;
signal current_state, next_state: state;
signal start_addr_r, start_addr_next: std_logic_vector(22 downto 0);
signal end_addr_r, end_addr_next: std_logic_vector(22 downto 0);
signal start_upload_sig, abort_upload_sig: std_logic;
--Names for Parallel port commands
constant NOP: std_logic_vector(5 downto 0) := "000000";
constant STARTUPLOAD: std_logic_vector(5 downto 0) := "000001";
constant ABORTUPLOAD: std_logic_vector(5 downto 0) := "000010";
constant READ : std_logic := '0';
constant WRITE : std_logic := '1';
BEGIN
init_cycle_complete <= init_cycle_complete_r;
--KAC I2C stuff
sync_KAC <= '0'; -- out KAC sync pin
Start_KAC <= '1' when init_cycle_complete_r = '1' else '0';
r_w_KAC <= READ;
Addr_KAC <= x"0F";
Data_KAC_in <= x"55";
--PP
start_addr <= start_addr_r;
end_addr <= end_addr_r;
--signal oneshots. The commands are coming in off the parallel port so this state
--machine is controlled with that clock. The problem is, the start_upload and abort_upload
--signals to the memory controller will not match the 50MHz clock. If they are high
--for one state here, then they would be high for thousands of 50Mhz clk cycles. The one
--shot makes them just go high for 1 50MHz cycle.
start_upload_oneshot: one_shot
port map
(
CLK => clk_50Mhz,
RST => rst,
sig_in => start_upload_sig,
sig_out => start_upload
);
abort_upload_oneshot: one_shot
port map
(
CLK => clk_50Mhz,
RST => rst,
sig_in => abort_upload_sig,
sig_out => abort_upload
);
wait_for_KAC_to_init: ms_delay
PORT MAP
(
clk => clk_12_5Mhz,
rst => rst,
start => delay_start, --also starts on reset
delay_complete => delay_complete
);
------------------------------------------------------------------------------------
-- PC command reader
-- this is a huge state machine that can easily be reduced down.
-- States 1 - 9 could all be one state. The bit order for start and end addr look
-- a little funny but it's a right shift that makes the host software a little
-- easier.
pc_command_reader: process(current_state, cmd, start_addr_r, end_addr_r) is
begin
--default actions
next_state <= current_state;
start_addr_next <= start_addr_r;
end_addr_next <= end_addr_r;
start_upload_sig <= '0';
abort_upload_sig <= '0';
case current_state is
when 0 => --NOP
if cmd = STARTUPLOAD then
next_state <= 1;
elsif cmd = ABORTUPLOAD then
next_state <= 10;
else
next_state <= 0;
end if;
when 1 => --Start Upload
start_addr_next(5 downto 0) <= cmd;
next_state <= 2;
when 2 => --Load start addr
start_addr_next(11 downto 6) <= cmd;
next_state <= 3;
when 3 =>
start_addr_next(17 downto 12) <= cmd;
next_state <= 4;
when 4 =>
start_addr_next(22 downto 18) <= cmd(4 downto 0);
next_state <= 5;
when 5 =>
end_addr_next(5 downto 0) <= cmd;
next_state <= 6;
when 6 =>
end_addr_next(11 downto 6) <= cmd;
next_state <= 7;
when 7 =>
end_addr_next(17 downto 12) <= cmd;
next_state <= 8;
when 8 =>
end_addr_next(22 downto 18) <= cmd(4 downto 0);
next_state <= 9;
when 9 => -- Could also branch to any other action
start_upload_sig <= '1';
if cmd = STARTUPLOAD then
next_state <= 1;
elsif cmd = ABORTUPLOAD then
next_state <= 10;
else
next_state <= 0;
end if;
when 10 =>
abort_upload_sig <= '1';
start_addr_next <= (others=>'0');
end_addr_next <= (others=>'0');
next_state <= 0;
when others =>
next_state <= 0;
end case;
end process pc_command_reader;
--Change state on clock
state_reg: process( clk_pp, rst ) is
begin
if rst = '0' then
current_state <= 0;
start_addr_r <= (others=>'0');
end_addr_r <= (others=>'0');
elsif clk_pp'event and clk_pp='1' then
--Update state and registers
current_state <= next_state;
start_addr_r <= start_addr_next;
end_addr_r <= end_addr_next;
end if;
end process state_reg;
------------------------------------------------------------------------------------
-- KAC control
-- Cycle the init pulse on powerup.
-- 0 then 1 then wait 1ms then 0 and init_cycle_complete
-- is asserted until reset.
-- Also, SDRAM needs 200us of delay for startup
KAC_Control: process(current_state_KAC, delay_complete) is
begin
--default actions
next_state_KAC <= current_state_KAC;
delay_start <= '0';
init_cycle_complete_r <= '0';
init_KAC <= '0'; --'0' Active '1' standby mode
case current_state_KAC is
when 0 =>
next_state_KAC <= 1;
init_KAC <= '1';
when 1 =>
delay_start <= '1';
init_KAC <= '1';
if delay_complete = '1' then
next_state_KAC <= 2;
end if;
when 2 =>
delay_start <= '1';
if delay_complete = '1' then
next_state_KAC <= 3;
end if;
when 3 =>
init_cycle_complete_r <= '1';
end case;
end process KAC_Control;
--Change state on clock
KAC_state_update: process( clk_12_5Mhz, rst ) is
begin
if rst = '0' then
current_state_KAC <= 0;
elsif clk_12_5Mhz'event and clk_12_5Mhz='1' then
current_state_KAC <= next_state_KAC;
end if;
end process KAC_state_update;
END MCSG_arch;
|
gpl-3.0
|
d11f41104b9b8fed29f3d56529cd932a
| 0.60091 | 3.056473 | false | false | false | false |
csrhau/sandpit
|
VHDL/single_port_ram/ram.vhdl
| 1 | 751 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM is
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector(9 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end entity RAM;
architecture behavioural of RAM is
type memory is array(0 to 1023) of std_logic_vector(7 downto 0);
signal storage : memory := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
data_out <= storage(to_integer(unsigned(address)));
if write_enable = '1' then
storage(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
end behavioural;
|
mit
|
b095d6c844e6b1c1341e1d02da197314
| 0.651132 | 3.367713 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/divider_r2.vhd
| 1 | 9,498 |
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_SIGNED.ALL;
------------------------------------------------------------------------------
entity divider is
generic (
tag_width : integer := 6
);
port (
clk : IN std_logic;
Resetb : IN std_logic;
PhyReg_DivRsData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit
PhyReg_DivRtData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit --
Iss_RobTag : IN std_logic_vector( 4 downto 0); -- from divider issue queue unit
Iss_Div : IN std_logic; -- from issue unit
-------------------------------- Logic for the pics ( added by Atif) --------------------------------
Div_RdPhyAddr : out std_logic_vector(5 downto 0); -- output to CDB required
Div_RdWrite : out std_logic;
Iss_RdPhyAddr : in std_logic_vector(5 downto 0); -- incoming form issue queue, need to be carried as Iss_RobTag
Iss_RdWrite : in std_logic;
----------------------------------------------------------------------
-- translate_off
Iss_instructionDiv : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Div_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 ) ;
Div_Done : out std_logic ;
Div_RobTag : OUT std_logic_vector(4 downto 0);
Div_Rddata : OUT std_logic_vector(31 downto 0);
Div_ExeRdy : OUT std_logic -- divider is read for division ==> drives "div_exec_ready" in the TOP
);
end divider;
architecture behv of divider is
component divider_core is
Port ( Dividend : in std_logic_vector (31 downto 0 );
Divisor : in std_logic_vector ( 31 downto 0);
Rem_n_Quo : out std_logic_vector ( 31 downto 0)
);
end component divider_core;
-- component divider_core is
-- port ( DATA_A : in std_logic_vector (31 downto 0 );
-- DATA_B : in std_logic_vector (31 downto 0);
-- DIV_OUT : out std_logic_vector ( 31 downto 0)
-- );
-- end component divider_core;
subtype tag_type is std_logic_vector(4 downto 0);
type tag is array (0 to 5) of tag_type; -- changed from (0 to 4)
-- tag_valid: 0 through 5 for the 6 pipeline registers forming a 6-clock long combinational division
-- note: Since 1 clock is lost in holding the incoming operands in a register before starting the division
-- we can only take 6 clocks (including a clock long combinational logic upstream of the CDB mux)
signal tag_valid,rdwrite : std_logic_vector(5 downto 0); -- changed from (4 downto 0)
signal tag_div : tag;
subtype PhyAddr_Type is std_logic_vector(5 downto 0);
type PhyAddr is array (0 to 5) of PhyAddr_Type;
signal RdPhyAddr : PhyAddr;
-- signal div_rem_quo : std_logic_vector(31 downto 0);
-- signal result : std_logic_vector(31 downto 0);
signal divisor, dividend: std_logic_vector(31 downto 0);
signal rfd : std_logic; -- rfd = ready for division
signal BufferDepth :std_logic_vector ( 4 downto 0 ) ; -- for the instruction coming from the division issue queue
signal Buffer0Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer1Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer2Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer3Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer4Depth :std_logic_vector ( 4 downto 0 ) ;
signal Buffer5Depth :std_logic_vector ( 4 downto 0 ) ;
begin
div : divider_core
port map (
Dividend => dividend,
Divisor => divisor,
Rem_n_Quo => Div_Rddata
);
-- port map (
-- DATA_A => divisor,
-- DATA_B => dividend,
-- DIV_OUT => result
-- );
Div_ExeRdy <= rfd;
-- Div_Rddata <= div_rem_quo;
-- translate_off
Div_instruction <= Iss_instructionDiv ;
-- translate_on
Div_Done <= tag_valid(5) ; -- previously 3? -- are you doing only 0 to 3? -- let us do 0 to 5 as our diagrams show 0 to 5
Div_RobTag <= tag_div(5);
Div_RdPhyAddr <= RdPhyAddr(5);
Div_RdWrite <= rdwrite(5);
BufferDepth <= unsigned(Iss_RobTag) - unsigned(Rob_TopPtr) ;
Buffer0Depth <= unsigned(tag_div(0)) - unsigned(Rob_TopPtr) ;
Buffer1Depth <= unsigned(tag_div(1)) - unsigned(Rob_TopPtr) ;
Buffer2Depth <= unsigned(tag_div(2)) - unsigned(Rob_TopPtr) ;
Buffer3Depth <= unsigned(tag_div(3)) - unsigned(Rob_TopPtr) ;
Buffer4Depth <= unsigned(tag_div(4)) - unsigned(Rob_TopPtr) ;
-- Note: On the tick of the clock, the six pipeline registers (0 to 5) will move one step down.
-- The top-most register 0 will receive a tag from divider issue unit.
-- When Cdb_Flush is activated, we are responsible to invalidate appropriate Flip-Flops
-- by the end of the clock. So we take care of the six valid-bit FFs, tag_valid(0 to 5) by looking at the 5 depths.
-- The CDB shall take care of invalidiating the outgoing div instruction
-- (going out of multiplier and entering the CDB register). So CDB will worry about Buf5Depth!
-- Hence the following line is not needed here
-- Buffer5Depth <= unsigned(tag_div(5)) - unsigned(Rob_TopPtr) ;
tag_carry : process (clk, Resetb)
begin
if (Resetb = '0') then
for i in 0 to 5 loop -- 0 to 5
tag_div(i) <= (others => '0'); -- Though we could have these as don't cares (others => '-'), for the sake of easy debugging, let us make them zeros;
RdPhyAddr(i) <= (others=>'0');
end loop;
tag_valid <= (others => '0');
rdwrite <= (others => '0');
rfd <= '1';
divisor <= (others => '-');
dividend <= (others => '-');
elsif(clk'event and clk = '1') then
-- if an instruction is coming in from divide issue queue
if(Iss_Div = '1' and rfd = '1' and ( (Cdb_Flush = '0') or ( Cdb_Flush = '1' and BufferDepth < Cdb_RobDepth ) ) ) then
-- (Iss_Div = '1' and rfd = '1' ) ? it is enough to say (Iss_Div = '1') as Iss_Div can not be made '1' by the issue unit unless rfd was '1'
divisor <= PhyReg_DivRtData;
dividend <= PhyReg_DivRsData;
tag_div(0) <= Iss_RobTag;
RdPhyAddr(0)<= Iss_RdPhyAddr;
rdwrite(0) <= Iss_RdWrite;
tag_valid(0)<= '1';
rfd <= '0';
else
tag_div(0) <= (others => '0'); -- though it is not necessary, we wish to clear to make debugging easy
RdPhyAddr(0) <= (others => '0');
tag_valid(0)<= '0';
rdwrite(0)<='0';
end if;
if ( Cdb_Flush = '1' and
( -- if there is an ongoing div operation which does not leave the divisor by the end of the clock
( Buffer0Depth > Cdb_RobDepth and tag_valid(0) = '1' ) or
( Buffer1Depth > Cdb_RobDepth and tag_valid(1) = '1' ) or
( Buffer2Depth > Cdb_RobDepth and tag_valid(2) = '1' ) or
( Buffer3Depth > Cdb_RobDepth and tag_valid(3) = '1' ) or
( Buffer4Depth > Cdb_RobDepth and tag_valid(4) = '1' )
-- ( Buffer5Depth > Cdb_RobDepth and tag_valid(5) = '1' ) -- see the above note regarding Buffer5Depth
) ) then
rfd <= '1' ;
for i in 1 to 5 loop -- note: it's 1 to 5, not 0 to 4 as these items are on move!
tag_valid(i) <= '0' ;
rdwrite(i)<='0';
tag_div(i) <= (others => '0'); -- Though we could have these tags as don't cares (others => '-'), for the sake of easy debugging, let us make them zeros;
RdPhyAddr(i) <= (others => '0');
end loop;
else
for i in 1 to 5 loop
tag_valid(i) <= tag_valid(i-1); -- tag_valid(0) receives a 1 or 0 depending on whether a new div instruction is issued or not.
tag_div(i) <= tag_div(i-1);
rdwrite(i) <= rdwrite(i-1);
RdPhyAddr(i) <= RdPhyAddr(i-1) ;
end loop;
if (rfd = '0' and
( (tag_valid(5) = '1') or -- it is unnecessary to qaulify with (rfd = '0' ) as (tag_valid(5) = '1') is enough for this part of the clause
( (tag_valid(0) = '0') and (tag_valid(1) = '0') and (tag_valid(2) = '0') and (tag_valid(3) = '0') and (tag_valid(4) = '0') ) ) )
-- if all the upper 5 tag valid bits (bits 0 to 4) are zeros -- this is perhaps redundant
-- However, if you do keep this piece of the clause, you do need the(rfd = '0' ) as a qualifier.
-- This is not apparent at first sight. This is an artifact of HDL coding!
-- Notice that, if we are initiating a division, we are assigning a '0' to the rfd signal (with delta-T delay) on line 125 above.
-- Then we come down here and override that assignment with '1' in line 162, resulting rfd continuing to be 1 for 1 extra clock.
-- To avoid this problem, you need to have (rfd = '0' ) as a qualifier for this part of the clause.
-- In fact, if the tag_valid[0:4] = 00000 and (rfd = '0' ) , then (tag_valid(5) = '1') is true and hence this clause is redundant as stated before.
then
rfd <= '1';
end if;
-- if (rfd = '1')then
-- div_rem_quo <= result; -- another clock? Result shall go directly to the CDB mux
-- end if;
-- Div_RobTag <= tag_div(4);
end if;
end if ;
end process tag_carry;
end architecture behv;
|
gpl-2.0
|
6730672de14fada31399c167dbf2cdc8
| 0.589177 | 3.339662 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/TargetCmdFIFO/example_design/TargetCmdFIFO_top_wrapper.vhd
| 1 | 19,114 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: TargetCmdFIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity TargetCmdFIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end TargetCmdFIFO_top_wrapper;
architecture xilinx of TargetCmdFIFO_top_wrapper is
SIGNAL clk_i : std_logic;
component TargetCmdFIFO_top is
PORT (
CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : TargetCmdFIFO_top
PORT MAP (
CLK => clk_i,
ALMOST_FULL => almost_full,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
6b9d86201cb115c9b43c31aaa1ca6a4d
| 0.486345 | 3.992063 | false | false | false | false |
csrhau/sandpit
|
VHDL/GOL_simple/cell.vhdl
| 1 | 841 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cell is
generic (
begin_alive : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
nw, nn, ne : in integer range 0 to 1;
ww, ee : in integer range 0 to 1;
sw, ss, se : in integer range 0 to 1;
alive: out integer range 0 to 1 := begin_alive
);
end cell;
architecture behavioural of cell is
signal alive_s : integer range 0 to 1 := begin_alive;
begin
process (clock)
variable neighbours : natural range 0 to 8 := 0;
begin
if rising_edge(clock) then
neighbours := nw + nn + ne + ww + ee + sw + ss + se;
if neighbours = 3 or (neighbours = 2 and alive_s = 1) then
alive_s <= 1;
else
alive_s <= 0;
end if;
end if;
end process;
alive <= alive_s;
end behavioural;
|
mit
|
d8989203a87c6525e2598c5b21402294
| 0.600476 | 3.391129 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/issueque.vhd
| 1 | 52,726 |
-------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre,Prasanjeet Das
-- Company : University of Southern California
-- Updated : 03/15/2010, 07/13/2010
-- TASK : Complete the seven TODO sections
-------------------------------------------------------------------------------
--
-- File : issueque.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The issue queue stores instructions and dispatches instructions
-- to the issue block as and when they are ready to be executed
-- Higher priority is given to instructions which has been in the
-- queue for the longest time
-- This is the code for the integer issue queue, the codes for
-- Multiplier queue and divider queue are provided separately
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity issueque is
port (
-- Global Clk and dispatch Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Output of LsBuffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
Iss_Lsb : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Dis_Immediate : in std_logic_vector ( 15 downto 0 );
Dis_Branch : in std_logic;
Dis_BranchPredict : in std_logic;
Dis_BranchOtherAddr : in std_logic_vector ( 31 downto 0 );
Dis_BranchPCBits : in std_logic_vector ( 2 downto 0 ) ;
Issque_IntQueueFull : out std_logic ;
Issque_IntQueueTwoOrMoreVacant : out std_logic;
Dis_Jr31Inst : in std_logic;
Dis_JalInst : in std_logic;
Dis_JrRsInst : in std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy : out std_logic ;
Iss_Int : in std_logic ;
-- Interface with the Multiply execution unit
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrAlu : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit (ALU)
Iss_RdPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RobTagAlu : out std_logic_vector(4 downto 0);
Iss_OpcodeAlu : out std_logic_vector(2 downto 0) ; --add branch information
Iss_BranchAddrAlu : out std_logic_vector(31 downto 0);
Iss_BranchAlu : out std_logic;
Iss_RegWriteAlu : out std_logic;
Iss_BranchUptAddrAlu : out std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : out std_logic;
Iss_JalInstAlu : out std_logic;
Iss_JrInstAlu : out std_logic;
Iss_JrRsInstAlu : out std_logic;
Iss_ImmediateAlu : out std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end issueque;
-- Architecture
architecture behav of issueque is
-- Type declarations
-- Declarations of Register Array for the Issue Queue and Issue Priority Register
type array_8_5 is array (0 to 7) of std_logic_vector(4 downto 0) ; --TAG
type array_8_6 is array (0 to 7) of std_logic_vector(5 downto 0) ; --REG
type array_8_3 is array (0 to 7) of std_logic_vector(2 downto 0) ; --OPCODE
type array_8_32 is array(0 to 7) of std_logic_vector(31 downto 0) ; --BRANCHADDR
type array_8_16 is array(0 to 7) of std_logic_vector(15 downto 0) ; --IMMEDIATEADDR
type array_8_1 is array(0 to 7) of std_logic; --BRANCHPredict
-- Signals declarations.
signal Flush : std_logic_vector(7 downto 0);
signal En : std_logic_vector(7 downto 0);
signal OutSelect : std_logic_vector(2 downto 0);
signal OutSelecttemp : std_logic_vector(7 downto 0);
signal OutSelectEmpty : std_logic_vector(7 downto 0);
signal OutSelectJRrstemp : std_logic_vector(7 downto 0);
signal OutSelectJRrs : std_logic_vector(2 downto 0);
signal OutSelect_result : std_logic_vector(2 downto 0);
signal RtReadyTemp : std_logic_vector(7 downto 0);
signal RsReadyTemp : std_logic_vector(7 downto 0);
signal IssuedRdPhyAddr : std_logic_vector(5 downto 0);
SIGNAL IssuequeBranchPredict : array_8_1;
SIGNAL IssuequeJR : array_8_1;
SIGNAL IssuequeJRrs : array_8_1;
SIGNAL IssuequeJAL : array_8_1;
SIGNAL IssuequeBranch : array_8_1;
SIGNAL IssuequeRegWrite : array_8_1;
SIGNAL IssuequeBranchAddr : array_8_32;
-- translate_off
SIGNAL Issuequeinstruction : array_8_32;
-- translate_on
SIGNAL IssuequeBranchPCBits : array_8_3;
SIGNAL IssuequeRsPhyAddrReg : array_8_6;
SIGNAL IssuequeRtPhyAddrReg : array_8_6;
SIGNAL IssuequeRdPhyAddrReg : array_8_6;
SIGNAL IssuequeOpcodeReg : array_8_3;
SIGNAL IssuequeRobTag : array_8_5;
SIGNAL IssuequeImmediate : array_8_16;
SIGNAL IssuequeRtReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeRsReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeInstrValReg : std_logic_vector (7 DOWNTO 0);
SIGNAL Entemp : std_logic_vector (7 DOWNTO 0);
SIGNAL EnJRrstemp : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeReadyTemp , IssuequefullTemp_Upper, IssuequefullTemp_Lower, UpperHalf_Has_Two_or_More_vacant, LowerHalf_Has_Two_or_More_vacant : std_logic ;
SIGNAL Buffer0Depth , Buffer1Depth ,Buffer2Depth ,Buffer3Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL Buffer4Depth , Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL IssuedRegWrite : std_logic;
begin
----------------------Generating Issuque ready -------------------------------------
---DisJAL only Instruction valid.
--###############################################################################################
-- TODO 1: Generate the IssuequeReadyTemp signal which is asserted when
--################################################################################################
-- For anyone of the 8 entries in the issue queue
-- NOTE: where [i] is from 0 to 7
-- The instruction [i] is valid and
-- instruction [i] is JAL or (JR with Rs register ready) or (JRrs with Rs register ready) or other int type instructions with both Rs register and Rt register ready
IssuequeReadyTemp <= OutSelecttemp(0) or OutSelecttemp(1) or OutSelecttemp (2) or OutSelecttemp(3) or
OutSelecttemp(4) or OutSelecttemp(5) or OutSelecttemp (6) or OutSelecttemp(7);
IssInt_Rdy <= IssuequeReadyTemp ;
---------- ----------Done Generating issuque Ready --------------------------------
--##################################################################################################
--------------------- Generating Full Condition-------------------------------------
--**********************************************************************************
-- This process generates the issueque full signal :
-- If you are issuing an instruction then the issueque is not full otherwise
-- issueque is full if all the eight entries are valid
--***********************************************************************************
--###############################################################################################
-- TODO 2: Generate the Full control signal
--################################################################################################
process ( IssuequeInstrValReg ,Iss_Int ) --ISSUEBLKDONE FROM ISSUE UNIT telling you that a instruction is issued
begin
if ( Iss_Int = '1' ) then
IssuequefullTemp_Upper <= '0' ; --Fill in the initial values of these two signals.
IssuequefullTemp_Lower <= IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
else
IssuequefullTemp_Upper <=IssuequeInstrValReg(7) and IssuequeInstrValReg(6) and
IssuequeInstrValReg(5) and IssuequeInstrValReg(4);
IssuequefullTemp_Lower <=IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
end if ;
end process ;
Issque_IntQueueFull <= IssuequefullTemp_Upper and IssuequefullTemp_Lower; --Complete the right hand side of the expression
--##################################################################################################
--------------- Nearly Full Signal ------------------------------
--**********************************************************************************
-- This process generates the issueque Nearly full signal :
-- The nearly full signal is generated for the first stage of dispatch unit for the following case
-- where both the stages have instructions to be issued in the same queue.
-- 1. Only one slot vacant in issueque: The instruction in first stage cannot be issued by dispatch.
-- 2. Two or more slots vacant in issueque: The instruction in first stage of dispatch finds a slot in issueque.
--***********************************************************************************
--###############################################################################################
-- TODO 3: Generate the Nearly Full control signal
--################################################################################################
UpperHalf_Has_Two_or_More_vacant <=(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(6))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(5)) and not(IssuequeInstrValReg(4))) ;
LowerHalf_Has_Two_or_More_vacant <= (not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(2))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(1)) and not(IssuequeInstrValReg(0))) ;
Issque_IntQueueTwoOrMoreVacant <= UpperHalf_Has_Two_or_More_vacant or LowerHalf_Has_Two_or_More_vacant or
(not (IssuequefullTemp_Upper) and not (IssuequefullTemp_Lower)) ;
-- NOTE : Two or more vacant only if
-- (a) UpperHalf Has Two or More vacant
-- (b) LowerHalf Has Two or More vacant
-- (c) Identify the third case when you need to deal with both the halfs simultaneoulsy
-- i.e) atleast one slot vacant in lower half and atleast one slot vacant in upper half
------------------ Done Generating Full and Nearly Full Condition -------------------------------
--##################################################################################################
------------------- Generating OutSelect and En-----------------------------------------
-- issue the instruction if instruction and data are valid
OUT_SELECT:
for I in 0 to 7 generate
OutSelecttemp(I) <= (IssuequeInstrValReg(I) and (IssuequeJAL(I) or(IssuequeRsReadyReg(I) and (IssuequeRtReadyReg(I) or IssuequeJR(I) or IssuequeJRrs(I))))) ; -- this has the priority in being issued
OutSelectJRrstemp(I) <= (IssuequeInstrValReg(I) and IssuequeRsReadyReg(I) and IssuequeJRrs(I)) ;
end generate OUT_SELECT;
--***************************************************************************************
-- This process generates the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelecttemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelecttemp(0) = '1' ) then
OutSelect <= "000";
else
if ( OutSelecttemp(1) = '1' ) then
OutSelect <= "001";
else
if ( OutSelecttemp(2) = '1') then
OutSelect <= "010";
else
if ( OutSelecttemp(3) = '1') then
OutSelect <= "011";
else
if ( OutSelecttemp(4) = '1') then
OutSelect <= "100";
else
if ( OutSelecttemp(5) = '1') then
OutSelect <= "101";
else
if ( OutSelecttemp(6) = '1') then
OutSelect <= "110";
else
OutSelect <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
--***************************************************************************************
-- This process generates to give priority to JRrs instruction in the issue queue.
-- the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelectJRrstemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelectJRrstemp(0) = '1' ) then
OutSelectJRrs <= "000";
else
if ( OutSelectJRrstemp(1) = '1' ) then
OutSelectJRrs <= "001";
else
if ( OutSelectJRrstemp(2) = '1') then
OutSelectJRrs <= "010";
else
if ( OutSelectJRrstemp(3) = '1') then
OutSelectJRrs <= "011";
else
if ( OutSelectJRrstemp(4) = '1') then
OutSelectJRrs <= "100";
else
if ( OutSelectJRrstemp(5) = '1') then
OutSelectJRrs <= "101";
else
if ( OutSelectJRrstemp(6) = '1') then
OutSelectJRrs <= "110";
else
OutSelectJRrs <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
process ( OutSelect , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelect) is
when "000" => Entemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => Entemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
Entemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
Entemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
Entemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
Entemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
Entemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
process ( OutSelectJRrs , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelectJRrs) is
when "000" => EnJRrstemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => EnJRrstemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => EnJRrstemp <= "11111100" ;
when "011" => EnJRrstemp <= "11111000" ;
when "100" => EnJRrstemp <= "11110000" ;
when "101" => EnJRrstemp <= "11100000" ;
when "110" => EnJRrstemp <= "11000000" ;
when others => EnJRrstemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
EnJRrstemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
EnJRrstemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
EnJRrstemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
EnJRrstemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
EnJRrstemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
En <= EnJRrstemp when (OutSelectJRrstemp /= "00000000") else Entemp; -- To given JRrs priority
OutSelect_result <= OutSelectJRrs when (OutSelectJRrstemp /= "00000000") else OutSelect; -- To given JRrs priority
------------------------------------Done Generating Enable ------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 4: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= unsigned(IssuequeRobTag(0)) - unsigned(Rob_TopPtr);
Buffer1Depth <= unsigned(IssuequeRobTag(1)) - unsigned(Rob_TopPtr);
Buffer2Depth <= unsigned(IssuequeRobTag(2)) - unsigned(Rob_TopPtr);
Buffer3Depth <= unsigned(IssuequeRobTag(3)) - unsigned(Rob_TopPtr);
Buffer4Depth <= unsigned(IssuequeRobTag(4)) - unsigned(Rob_TopPtr);
Buffer5Depth <= unsigned(IssuequeRobTag(5)) - unsigned(Rob_TopPtr);
Buffer6Depth <= unsigned(IssuequeRobTag(6)) - unsigned(Rob_TopPtr);
Buffer7Depth <= unsigned(IssuequeRobTag(7)) - unsigned(Rob_TopPtr);
--################################################################################################
--***************************************************************************************************************
-- This process does the selective flushing, if the instruction is younger to branch and there is an intent to flush
-- Flush the instruction if it is a valid instruction, this is an additional qualification which is unnecessary
-- We are just flushing the valid instructions and not caring about invalid instructions
--*****************************************************************************************************************
--###############################################################################################
-- TODO 5: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth , Buffer4Depth , Buffer5Depth ,
Buffer6Depth , Buffer7Depth , En ,IssuequeInstrValReg)
begin
Flush <= (others => '0') ;
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then -- WHY THIS CONDITION?? CHECK WETHER THE INSTRUCTION IS AFTER BRANCH OR NOT(i.e, instruction is younger to branch)
if ( En(0) = '0' ) then -- NOT UPDATING HENCE FLUSH IF INSTRUCTION IS VALID
Flush(0) <= IssuequeInstrValReg(0) ; --just to make sure that flush only valid instruction
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then -- check for younger instructions
if ( En(0) = '1' ) then
Flush(0) <= IssuequeInstrValReg(1); --Hint: Take into account the shift mechanism so is it i or i+1 or i - 1?
else
Flush(1) <= IssuequeInstrValReg(1) ;-- NO UPDATION SO FLUSH(1) IS THE STATUS OF INSTRUCTION (1)
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( En(1) = '1' ) then
Flush(1) <= IssuequeInstrValReg(2);
else
Flush(2) <= IssuequeInstrValReg(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( En(2) = '1' ) then
Flush(2) <= IssuequeInstrValReg(3);
else
Flush(3) <= IssuequeInstrValReg(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( En(3) = '1' ) then
Flush(3) <= IssuequeInstrValReg(4);
else
Flush(4) <= IssuequeInstrValReg(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( En(4) = '1' ) then
Flush(4) <= IssuequeInstrValReg(5);
else
Flush(5) <= IssuequeInstrValReg(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( En(5) = '1' ) then
Flush(5) <= IssuequeInstrValReg(6);
else
Flush(6) <= IssuequeInstrValReg(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( En(6) = '1' ) then
Flush(6) <= IssuequeInstrValReg(7);
else
Flush(7) <= IssuequeInstrValReg(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--###############################################################################################
-- TODO 6: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RtReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction being issued for ALU Queue, load - store queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit and do the forwarding if necessary.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process ( IssuequeRtPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Lsbuf_RdWrite, Iss_Lsb, IssuequeRegWrite , IssuequeInstrValReg, IssuequeRtReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RtReadyTemp <= (others => '0') ;
if (( (IssuequeRtPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(0) ='0' and IssuequeInstrValReg(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RtReadyTemp(0) <= IssuequeRtReadyReg(0);
end if ;
if (( (IssuequeRtPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(1) ='0' and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RtReadyTemp(0) <= IssuequeRtReadyReg(1);
else
RtReadyTemp(1) <= IssuequeRtReadyReg(1);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(2) ='0' and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RtReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RtReadyTemp(1) <= IssuequeRtReadyReg(2);
else
RtReadyTemp(2) <= IssuequeRtReadyReg(2);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(3) ='0' and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RtReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RtReadyTemp(2) <= IssuequeRtReadyReg(3);
else
RtReadyTemp(3) <= IssuequeRtReadyReg(3);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(4) ='0' and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RtReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RtReadyTemp(3) <= IssuequeRtReadyReg(4);
else
RtReadyTemp(4) <= IssuequeRtReadyReg(4);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(5) ='0' and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RtReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RtReadyTemp(4) <= IssuequeRtReadyReg(5);
else
RtReadyTemp(5) <= IssuequeRtReadyReg(5);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(6) ='0' and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RtReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RtReadyTemp(5) <= IssuequeRtReadyReg(6);
else
RtReadyTemp(6) <= IssuequeRtReadyReg(6);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(7) ='0' and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RtReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RtReadyTemp(6) <= IssuequeRtReadyReg(7);
else
RtReadyTemp(7) <= IssuequeRtReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
--###############################################################################################
-- TODO 7: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RsReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for load - store queue, ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process (IssuequeRsPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Iss_Lsb, Lsbuf_RdWrite,IssuequeInstrValReg, IssuequeRsReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RsReadyTemp <= (others => '0');
if (( (IssuequeRsPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(0) ='0'and IssuequeInstrValReg(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RsReadyTemp(0) <= IssuequeRsReadyReg(0);
end if ;
if (( (IssuequeRsPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(1) ='0'and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RsReadyTemp(0) <= IssuequeRsReadyReg(1);
else
RsReadyTemp(1) <= IssuequeRsReadyReg(1);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(2) ='0'and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RsReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RsReadyTemp(1) <= IssuequeRsReadyReg(2);
else
RsReadyTemp(2) <= IssuequeRsReadyReg(2);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(3) ='0'and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RsReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RsReadyTemp(2) <= IssuequeRsReadyReg(3);
else
RsReadyTemp(3) <= IssuequeRsReadyReg(3);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or(IssuequeRsPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(4) ='0'and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RsReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RsReadyTemp(3) <= IssuequeRsReadyReg(4);
else
RsReadyTemp(4) <= IssuequeRsReadyReg(4);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(5) ='0'and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RsReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RsReadyTemp(4) <= IssuequeRsReadyReg(5);
else
RsReadyTemp(5) <= IssuequeRsReadyReg(5);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(6) ='0'and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RsReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RsReadyTemp(5) <= IssuequeRsReadyReg(6);
else
RsReadyTemp(6) <= IssuequeRsReadyReg(6);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(7) ='0'and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RsReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RsReadyTemp(6) <= IssuequeRsReadyReg(7);
else
RsReadyTemp(7) <= IssuequeRsReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
----------------------------------------------------------------------------------------------------
--------------------------------- ------------------------------
process ( clk , Resetb )
begin
if ( Resetb = '0' ) then
IssuequeInstrValReg <= (others => '0') ;
IssuequeRsReadyReg <= (others => '0');
IssuequeRtReadyReg <= (others => '0');
IssuequeJR <= (others => '0');
IssuequeJRrs <= (others => '0');
IssuequeJAL <= (others => '0');
elsif ( Clk'event and Clk = '1' ) then
IssuequeRsReadyReg <= RsReadyTemp;
IssuequeRtReadyReg <= RtReadyTemp;
-- end if;
for I in 6 downto 0 loop
if ( Flush(I) = '1' ) then
IssuequeInstrValReg(I) <= '0' ;
-- translate_off
Issuequeinstruction(I) <= (others => '0') ;
-- translate_on
else
if ( En(I) = '1' ) then --update
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I + 1) ;
IssuequeRsPhyAddrReg(I) <= IssuequeRsPhyAddrReg(I + 1);
IssuequeRdPhyAddrReg(I) <= IssuequeRdPhyAddrReg(I + 1);
IssuequeRtPhyAddrReg(I) <= IssuequeRtPhyAddrReg(I + 1);
IssuequeRobTag(I) <= IssuequeRobTag(I + 1);
IssuequeRegWrite(I) <= IssuequeRegWrite(I + 1);
IssuequeOpcodeReg(I) <= IssuequeOpcodeReg(I + 1);
IssuequeBranchPredict(I) <= IssuequeBranchPredict(I + 1);
IssuequeBranch(I) <= IssuequeBranch(I + 1);
IssuequeBranchAddr(I) <= IssuequeBranchAddr(I + 1);
IssuequeBranchPCBits(I) <= IssuequeBranchPCBits(I + 1);
IssuequeJR(I) <= IssuequeJR(I + 1);
IssuequeJRrs(I) <= IssuequeJRrs(I + 1);
IssuequeJAL(I) <= IssuequeJAL(I + 1);
IssuequeImmediate(I) <= IssuequeImmediate(I + 1);
-- translate_off
Issuequeinstruction(I) <= Issuequeinstruction(I + 1);
-- translate_on
else
---If can be removed ---
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I) ;
end if ;
end if ;
end loop;
if ( Flush(7) = '1' ) then
IssuequeInstrValReg(7) <= '0' ;
-- translate_off
Issuequeinstruction(7) <= (others => '0') ;
-- translate_on
else
if ( En(7) = '1' ) then
IssuequeInstrValReg(7) <= Dis_Issquenable;
IssuequeRdPhyAddrReg(7) <= Dis_NewRdPhyAddr ;
IssuequeOpcodeReg(7) <= Dis_Opcode ;
IssuequeRobTag(7) <= Dis_RobTag;
IssuequeRegWrite(7) <= Dis_RegWrite;
IssuequeRtPhyAddrReg(7) <= Dis_RtPhyAddr ;
IssuequeRsPhyAddrReg(7) <= Dis_RsPhyAddr ;
IssuequeBranchPredict(7) <= Dis_BranchPredict;
IssuequeBranch(7) <= Dis_Branch;
IssuequeBranchAddr(7) <= Dis_BranchOtherAddr;
IssuequeBranchPCBits(7) <= Dis_BranchPCBits;
IssuequeRsReadyReg(7) <= Dis_RsDataRdy;
IssuequeRtReadyReg(7) <= Dis_RtDataRdy;
IssuequeJR(7) <= Dis_Jr31Inst;
IssuequeJRrs(7) <= Dis_JrRsInst;
IssuequeJAL(7) <= Dis_JalInst;
IssuequeImmediate(7) <= Dis_Immediate;
-- translate_off
Issuequeinstruction(7) <= Dis_instruction;
-- translate_on
else
IssuequeInstrValReg(7) <= IssuequeInstrValReg(7) ;
end if ;
end if ;
end if ;
end process ;
--- Selecting the Output to Go to Execution Unit, Physical Register Filed, Issue Unit
Iss_RsPhyAddrAlu <= IssuequeRsPhyAddrReg(CONV_INTEGER (unsigned( OutSelect_result))) ;
Iss_RtPhyAddrAlu <= IssuequeRtPhyAddrReg (CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRdPhyAddr <= IssuequeRdPhyAddrReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRegWrite <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RdPhyAddrAlu <= IssuedRdPhyAddr;
Iss_OpcodeAlu <= IssuequeOpcodeReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RobTagAlu <= IssuequeRobTag(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RegWriteAlu <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchPredictAlu <= IssuequeBranchPredict(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAlu <= IssuequeBranch(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAddrAlu <= IssuequeBranchAddr(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchUptAddrAlu <= IssuequeBranchPCBits(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrInstAlu <= IssuequeJR(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JalInstAlu <= IssuequeJAL(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrRsInstAlu <= IssuequeJrRs(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_ImmediateAlu <= IssuequeImmediate(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_off
Iss_instructionAlu <= Issuequeinstruction(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_on
end behav ;
|
gpl-2.0
|
7984cda18a0ba8cf5c674076b69795ad
| 0.520711 | 4.802004 | false | false | false | false |
BBN-Q/APS2-TDM
|
testbenches/FileIO.vhd
| 1 | 3,317 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.textio.all;
use IEEE.std_logic_textio.all;
package FileIO is
type DataArray_t is array(integer range <>) of std_logic_vector(31 downto 0);
type SeqArray_t is array(integer range <>) of std_logic_vector(63 downto 0);
impure function read_wf_file(fileName : string ) return DataArray_t;
impure function read_seq_file(fileName : string ) return DataArray_t;
impure function read_seq_file(fileName : string ) return SeqArray_t;
impure function num_lines(fileName : string) return natural;
end FileIO;
package body FileIO is
impure function read_wf_file(fileName : string ) return DataArray_t is
--Read a waveform file into an array
--Expects a single signed 16 bit integer on each line
--Will pack into an array of 32 bit words
variable numLines : natural := num_lines(fileName);
variable dataArray : DataArray_t(0 to numLines/2-1);
file FID : text;
variable ln : line;
variable a,b : integer;
variable ct : natural := 0;
variable upperWord, lowerWord : std_logic_vector(15 downto 0) ;
begin
file_open(FID, fileName, read_mode);
lineReading : while not endfile(FID) loop
readline(FID, ln);
read(ln, a);
readline(FID, ln);
read(ln, b);
dataArray(ct) := std_logic_vector(to_signed(b, 16)) & std_logic_vector(to_signed(a, 16));
ct := ct + 1;
end loop lineReading;
file_close(FID);
return dataArray;
end read_wf_file;
impure function read_seq_file(fileName : string) return DataArray_t is
--Read a sequence file into an array.
--Expects 1 64bit entry per line as a hex string
--Will parse it into 2 32bit entries and pad a zero word at the top word
variable numLines : natural := num_lines(fileName);
variable dataArray : DataArray_t(0 to 2*numLines-1);
file FID : text;
variable ln : line;
variable seqWord : std_logic_vector(63 downto 0) ;
variable ct : natural := 0;
begin
file_open(FID, fileName, read_mode);
lineReading : while not endfile(FID) loop
readline(FID, ln);
hread(ln, seqWord);
for wordct in 1 to 2 loop
dataArray(ct) := seqWord(wordct*32-1 downto (wordct-1)*32);
ct := ct + 1;
end loop;
end loop lineReading;
file_close(FID);
return dataArray;
end read_seq_file;
impure function read_seq_file(fileName : string) return SeqArray_t is
--Read a sequence file into an array.
--Expects 1 64bit entry per line as a hex string
variable numLines : natural := num_lines(fileName);
variable dataArray : SeqArray_t(0 to numLines-1);
file FID : text;
variable ln : line;
variable seqWord : std_logic_vector(63 downto 0) ;
variable ct : natural := 0;
begin
file_open(FID, fileName, read_mode);
lineReading : while not endfile(FID) loop
readline(FID, ln);
hread(ln, dataArray(ct));
ct := ct + 1;
end loop lineReading;
file_close(FID);
return dataArray;
end read_seq_file;
impure function num_lines(fileName : string) return natural is
--Helper function to count the number of lines in a file
variable linect : natural := 0;
file FID : text;
variable ln : line;
begin
file_open(FID, fileName, read_mode);
lineReading : while not endfile(FID) loop
readline(FID, ln);
linect := linect + 1;
end loop lineReading;
file_close(FID);
return linect;
end num_lines;
end package body; -- FileIO
|
mpl-2.0
|
d21588d7389334eaa64b6f2cbe5e0090
| 0.70606 | 3.120414 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/pos_circundantes.vhd
| 1 | 2,861 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: fantasma3.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pos_circundantes is
Port ( my_x : in STD_LOGIC_VECTOR (2 downto 0);
my_y : in STD_LOGIC_VECTOR (2 downto 0);
addr_up : out STD_LOGIC_VECTOR (5 downto 0);
addr_dw : out STD_LOGIC_VECTOR (5 downto 0);
addr_rg : out STD_LOGIC_VECTOR (5 downto 0);
addr_lf : out STD_LOGIC_VECTOR (5 downto 0));
end pos_circundantes;
architecture arq of pos_circundantes is
COMPONENT incrCuenta3bits
PORT(
num_in : IN std_logic_vector(2 downto 0);
num_out : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
COMPONENT decrCuenta3bits
PORT(
num_in : IN std_logic_vector(2 downto 0);
num_out : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
signal my_y_add1: std_logic_vector(2 downto 0);
signal my_x_add1: std_logic_vector(2 downto 0);
signal my_y_sub1: std_logic_vector(2 downto 0);
signal my_x_sub1: std_logic_vector(2 downto 0);
begin
Inst_incrCuenta3bits_x: incrCuenta3bits PORT MAP(
num_in => my_x,
num_out => my_x_add1
);
Inst_incrCuenta3bits_y: incrCuenta3bits PORT MAP(
num_in => my_y,
num_out => my_y_add1
);
Inst_decrCuenta3bits_x: decrCuenta3bits PORT MAP(
num_in => my_x,
num_out => my_x_sub1
);
Inst_decrCuenta3bits_y: decrCuenta3bits PORT MAP(
num_in => my_y,
num_out => my_y_sub1
);
addr_up <= my_y_add1 & my_x;
addr_dw <= my_y_sub1 & my_x;
addr_rg <= my_y & my_x_add1;
addr_lf <= my_y & my_x_sub1;
end arq;
|
gpl-3.0
|
04e8748ab9072957cfcf93ef91ba1c49
| 0.595596 | 3.405952 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/issueque_div.vhd
| 1 | 41,420 |
-------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre
-- Company : University of Southern California
-- Updated : 03/15/2010
-------------------------------------------------------------------------------
--
-- File : issueque.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The issue queue stores instructions and dispatches instructions
-- to the issue block as and when they are ready to be executed
-- Higher priority is given to instructions which has been in the
-- queue for the longest time
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity issueque_div is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the LsBuffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Issque_DivQueueFull : out std_logic ;
Issque_DivQueueTwoOrMoreVacant : out std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssDiv_Rdy : out std_logic ;
Iss_Div : in std_logic ;
Iss_Int : in std_logic;
Iss_Lsb : in std_logic;
-- Interface with the Multiply execution unit
Iss_RdPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_PhyRegValidAlu : in std_logic;
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrDiv : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrDiv : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit
Iss_RdPhyAddrDiv : out std_logic_vector(5 downto 0) ;
Iss_RobTagDiv : out std_logic_vector(4 downto 0);
Iss_OpcodeDiv : out std_logic_vector(2 downto 0) ; --add branch information
Iss_RegWriteDiv : out std_logic;
-- translate_off
Iss_instructionDiv : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end issueque_div;
-- Architecture
architecture behav of issueque_div is
-- Type declarations
-- Declarations of Register Array for the Issue Queue and Issue Priority Register
type array_8_32 is array (0 to 7) of std_logic_vector(31 downto 0) ; --REG
type array_8_5 is array (0 to 7) of std_logic_vector(4 downto 0) ; --REG
type array_8_6 is array (0 to 7) of std_logic_vector(5 downto 0) ; --TAG
type array_8_3 is array (0 to 7) of std_logic_vector(2 downto 0) ; --OPCODE
type array_8_1 is array(0 to 7) of std_logic; --BRANCHPredict
-- Signals declarations.
signal Flush : std_logic_vector(7 downto 0);
signal En : std_logic_vector(7 downto 0);
signal OutSelect : std_logic_vector(2 downto 0);
signal OutSelecttemp : std_logic_vector(7 downto 0);
signal OutSelect_result : std_logic_vector(2 downto 0);
signal RtReadyTemp : std_logic_vector(7 downto 0);
signal RsReadyTemp : std_logic_vector(7 downto 0);
SIGNAL IssuequeRegWrite : array_8_1;
SIGNAL IssuequeRsPhyAddrReg : array_8_6;
SIGNAL IssuequeRtPhyAddrReg : array_8_6;
SIGNAL IssuequeRdPhyAddrReg : array_8_6;
SIGNAL IssuequeOpcodeReg : array_8_3;
SIGNAL IssuequeRobTag : array_8_5;
-- translate_off
SIGNAL Issuequeinstruction : array_8_32;
-- translate_on
SIGNAL IssuequeRtReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeRsReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeInstrValReg : std_logic_vector (7 DOWNTO 0);
SIGNAL Entemp : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeReadyTemp , IssuequefullTemp_Upper, IssuequefullTemp_Lower, UpperHalf_Has_Two_or_More_vacant, LowerHalf_Has_Two_or_More_vacant : std_logic ;
SIGNAL Buffer0Depth , Buffer1Depth ,Buffer2Depth ,Buffer3Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL Buffer4Depth , Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector( 4 downto 0 ) ;
begin
----------------------Generating Issuque ready -------------------------------------
---DisJAL only Instruction valid.
IssuequeReadyTemp <=((IssuequeInstrValReg(7) and IssuequeRsReadyReg(7) and IssuequeRtReadyReg(7) )or
(IssuequeInstrValReg(6) and IssuequeRsReadyReg(6) and IssuequeRtReadyReg(6) ) or
(IssuequeInstrValReg(5) and IssuequeRsReadyReg(5) and IssuequeRtReadyReg(5) )or
(IssuequeInstrValReg(4) and IssuequeRsReadyReg(4) and IssuequeRtReadyReg(4) ) or
(IssuequeInstrValReg(3) and IssuequeRsReadyReg(3) and IssuequeRtReadyReg(3) ) or
(IssuequeInstrValReg(2) and IssuequeRsReadyReg(2) and IssuequeRtReadyReg(2) ) or
(IssuequeInstrValReg(1) and IssuequeRsReadyReg(1) and IssuequeRtReadyReg(1) ) or
(IssuequeInstrValReg(0) and IssuequeRsReadyReg(0) and IssuequeRtReadyReg(0) )) ; -- when any of the instruction and corresponding operands are valid
IssDiv_Rdy <= IssuequeReadyTemp ;
---------- ----------Done Generating issuque Ready --------------------------------
--------------------- Generating Full Condition-------------------------------------
--**********************************************************************************
-- This process generates the issueque full signal :
-- If you are issueing an instruction then the issueque is not full otherwise
--issueque is full if all the four entries are valid
--***********************************************************************************
process ( IssuequeInstrValReg ,Iss_Div ) --ISSUEBLKDONE FROM ISSUE UNIT telling you that a instruction is issued
begin
if ( Iss_Div = '1' ) then
IssuequefullTemp_Upper <= '0' ; --because you just issued an instruction so the issue queue is not full
IssuequefullTemp_Lower <= IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
else
IssuequefullTemp_Upper <=IssuequeInstrValReg(7) and IssuequeInstrValReg(6) and
IssuequeInstrValReg(5) and IssuequeInstrValReg(4);
IssuequefullTemp_Lower <=IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
end if ;
end process ;
Issque_DivQueueFull <= IssuequefullTemp_Upper and IssuequefullTemp_Lower;
--------------- Nearly Full Signal ------------------------------
--**********************************************************************************
-- This process generates the issueque Nearly full signal :
-- The nearly full signal is generated for the first stage of dispatch unit for the following case
-- where both the stages have instructions to be issued in the same queue.
-- 1. Only one slot vacant in issueque: The instruction in first stage cannot be issued by dispatch.
-- 2. Two or more slots vacant in issueque: The instruction in first stage of dispatch finds a slot in issueque.
--***********************************************************************************
UpperHalf_Has_Two_or_More_vacant <=(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(6))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(5)) and not(IssuequeInstrValReg(4))) ;
LowerHalf_Has_Two_or_More_vacant <= (not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(2))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(1)) and not(IssuequeInstrValReg(0))) ;
Issque_DivQueueTwoOrMoreVacant <= UpperHalf_Has_Two_or_More_vacant or LowerHalf_Has_Two_or_More_vacant or ((not(IssuequefullTemp_Lower)) and (not(IssuequefullTemp_Upper)));
------------------ Done Generating Full and Nearly Full Condition -------------------------------
------------------- Generating OutSelect and En-----------------------------------------
-- issue the instruction if instruction and data are valid
OUT_SELECT:
for I in 0 to 7 generate
OutSelecttemp(I) <= (IssuequeInstrValReg(I) and IssuequeRsReadyReg(I) and IssuequeRtReadyReg(I) ) ; -- this has the priority in being issued
end generate OUT_SELECT;
--***************************************************************************************
-- This process generates the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelecttemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelecttemp(0) = '1' ) then
OutSelect <= "000";
else
if ( OutSelecttemp(1) = '1' ) then
OutSelect <= "001";
else
if ( OutSelecttemp(2) = '1') then
OutSelect <= "010";
else
if ( OutSelecttemp(3) = '1') then
OutSelect <= "011";
else
if ( OutSelecttemp(4) = '1') then
OutSelect <= "100";
else
if ( OutSelecttemp(5) = '1') then
OutSelect <= "101";
else
if ( OutSelecttemp(6) = '1') then
OutSelect <= "110";
else
OutSelect <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
process ( OutSelect , Iss_Div ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Div = '1' ) then
Case ( OutSelect) is
when "000" => Entemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => Entemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
Entemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
Entemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
Entemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
Entemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
Entemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
En <= Entemp;
OutSelect_result <= OutSelect;
------------------------------------Done Generating Enable ------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= unsigned(IssuequeRobTag (0)) - unsigned(Rob_TopPtr);
Buffer1Depth <= unsigned(IssuequeRobTag (1)) - unsigned(Rob_TopPtr);
Buffer2Depth <= unsigned(IssuequeRobTag (2)) - unsigned(Rob_TopPtr);
Buffer3Depth <= unsigned(IssuequeRobTag (3)) - unsigned(Rob_TopPtr);
Buffer4Depth <= unsigned(IssuequeRobTag (4)) - unsigned(Rob_TopPtr);
Buffer5Depth <= unsigned(IssuequeRobTag (5)) - unsigned(Rob_TopPtr);
Buffer6Depth <= unsigned(IssuequeRobTag (6)) - unsigned(Rob_TopPtr);
Buffer7Depth <= unsigned(IssuequeRobTag (7)) - unsigned(Rob_TopPtr);
--***************************************************************************************************************
-- This process does the selective flushing, if the instruction is younger to branch and there is an intent to flush
-- Flush the instruction if it is a valid instruction, this is an additional qualification which is unnecessary
-- We are just flushing the valid instructions and not caring about invalid instructions
--*****************************************************************************************************************
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth , Buffer4Depth , Buffer5Depth ,
Buffer6Depth , Buffer7Depth , En ,IssuequeInstrValReg)
begin
Flush <= (others => '0') ;
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then -- WHY THIS CONDITION?? CHECK WETHER THE INSTRUCTION IS AFTER BRANCH OR NOT(i.e, instruction is younger to branch)
if ( En(0) = '0' ) then -- NOT UPDATING HENCE FLUSH IF INSTRUCTION IS VALID
Flush(0) <= IssuequeInstrValReg(0) ; --just to make sure that flush only valid instruction
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then -- check for younger instructions
if ( En(0) = '1' ) then
Flush(0) <= IssuequeInstrValReg(1); -- UPDATE SO FLUSH (0) IS THE STATUS OF INSTRUCTION(1)
else
Flush(1) <= IssuequeInstrValReg(1) ;-- NO UPDATION SO FLUSH(1) IS THE STATUS OF INSTRUCTION (1)
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( En(1) = '1' ) then
Flush(1) <= IssuequeInstrValReg(2) ;
else
Flush(2) <= IssuequeInstrValReg(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( En(2) = '1' ) then
Flush(2) <= IssuequeInstrValReg(3);
else
Flush(3) <= IssuequeInstrValReg(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( En(3) = '1' ) then
Flush(3) <= IssuequeInstrValReg(4);
else
Flush(4) <= IssuequeInstrValReg(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( En(4) = '1' ) then
Flush(4) <= IssuequeInstrValReg(5);
else
Flush(5) <= IssuequeInstrValReg(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( En(5) = '1' ) then
Flush(5) <= IssuequeInstrValReg(6);
else
Flush(6) <= IssuequeInstrValReg(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( En(6) = '1' ) then
Flush(6) <= IssuequeInstrValReg(7);
else
Flush(7) <= IssuequeInstrValReg(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--*****************************************************************************************************************************
-- This processes does the updation of the various RtReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and 5th stage of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process ( IssuequeRtPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr , Lsbuf_RdWrite, Iss_Lsb, Iss_Int, IssuequeInstrValReg, IssuequeRtReadyReg, Iss_RdPhyAddrAlu, Iss_PhyRegValidAlu, En, Mul_RdPhyAddr, Div_RdPhyAddr, Mul_ExeRdy, Div_ExeRdy )
begin
RtReadyTemp <= (others => '0') ;
if (( (IssuequeRtPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(0) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(0) ='0' and IssuequeInstrValReg(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RtReadyTemp(0) <= IssuequeRtReadyReg(0);
end if ;
if (( (IssuequeRtPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(1) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(1) ='0' and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RtReadyTemp(0) <= IssuequeRtReadyReg(1);
else
RtReadyTemp(1) <= IssuequeRtReadyReg(1);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(2) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(2) ='0' and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RtReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RtReadyTemp(1) <= IssuequeRtReadyReg(2);
else
RtReadyTemp(2) <= IssuequeRtReadyReg(2);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(3) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(3) ='0' and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RtReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RtReadyTemp(2) <= IssuequeRtReadyReg(3);
else
RtReadyTemp(3) <= IssuequeRtReadyReg(3);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(4) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(4) ='0' and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RtReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RtReadyTemp(3) <= IssuequeRtReadyReg(4);
else
RtReadyTemp(4) <= IssuequeRtReadyReg(4);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(5) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(5) ='0' and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RtReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RtReadyTemp(4) <= IssuequeRtReadyReg(5);
else
RtReadyTemp(5) <= IssuequeRtReadyReg(5);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(6) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(6) ='0' and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RtReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RtReadyTemp(5) <= IssuequeRtReadyReg(6);
else
RtReadyTemp(6) <= IssuequeRtReadyReg(6);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(7) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRtPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRtReadyReg(7) ='0' and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RtReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RtReadyTemp(6) <= IssuequeRtReadyReg(7);
else
RtReadyTemp(7) <= IssuequeRtReadyReg(7);
end if;
end if ;
end process ;
--*****************************************************************************************************************************
-- This processes does the updation of the various RsReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and 5th stage of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process (IssuequeRsPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr , Lsbuf_RdWrite, Iss_Lsb, Iss_Int, IssuequeInstrValReg, IssuequeRsReadyReg, Iss_RdPhyAddrAlu, Iss_PhyRegValidAlu, En, Mul_RdPhyAddr, Div_RdPhyAddr, Mul_ExeRdy, Div_ExeRdy )
begin
RsReadyTemp <= (others => '0');
if (( (IssuequeRsPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(0) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(0) ='0'and IssuequeInstrValReg(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RsReadyTemp(0) <= IssuequeRsReadyReg(0);
end if ;
if (( (IssuequeRsPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(1) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(1) ='0'and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RsReadyTemp(0) <= IssuequeRsReadyReg(1);
else
RsReadyTemp(1) <= IssuequeRsReadyReg(1);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(2) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(2) ='0'and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RsReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RsReadyTemp(1) <= IssuequeRsReadyReg(2);
else
RsReadyTemp(2) <= IssuequeRsReadyReg(2);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(3) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(3) ='0'and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RsReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RsReadyTemp(2) <= IssuequeRsReadyReg(3);
else
RsReadyTemp(3) <= IssuequeRsReadyReg(3);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(4) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(4) ='0'and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RsReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RsReadyTemp(3) <= IssuequeRsReadyReg(4);
else
RsReadyTemp(4) <= IssuequeRsReadyReg(4);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(5) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(5) ='0'and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RsReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RsReadyTemp(4) <= IssuequeRsReadyReg(5);
else
RsReadyTemp(5) <= IssuequeRsReadyReg(5);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(6) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(6) ='0'and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RsReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RsReadyTemp(5) <= IssuequeRsReadyReg(6);
else
RsReadyTemp(6) <= IssuequeRsReadyReg(6);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(7) = Iss_RdPhyAddrAlu and Iss_PhyRegValidAlu = '1' and Iss_Int = '1') or (IssuequeRsPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1')) and IssuequeRsReadyReg(7) ='0'and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RsReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RsReadyTemp(6) <= IssuequeRsReadyReg(7);
else
RsReadyTemp(7) <= IssuequeRsReadyReg(7);
end if;
end if ;
end process ;
----------------------------------------------------------------------------------------------------
--------------------------------- ------------------------------
process ( Clk , Resetb )
begin
if ( Resetb = '0' ) then
IssuequeInstrValReg <= (others => '0') ;
elsif ( Clk'event and Clk = '1' ) then
IssuequeRsReadyReg <= RsReadyTemp;
IssuequeRtReadyReg <= RtReadyTemp;
for I in 6 downto 0 loop
if ( Flush(I) = '1' ) then
IssuequeInstrValReg(I) <= '0' ;
-- translate_off
Issuequeinstruction(I) <= (others => '0') ;
-- translate_on
else
if ( En(I) = '1' ) then --update
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I + 1) ;
IssuequeRsPhyAddrReg(I) <= IssuequeRsPhyAddrReg(I + 1);
IssuequeRdPhyAddrReg(I) <= IssuequeRdPhyAddrReg(I + 1);
IssuequeRtPhyAddrReg(I) <= IssuequeRtPhyAddrReg(I + 1);
IssuequeRobTag(I) <= IssuequeRobTag(I + 1);
IssuequeRegWrite(I) <= IssuequeRegWrite(I + 1);
IssuequeOpcodeReg(I) <= IssuequeOpcodeReg(I + 1);
-- translate_off
Issuequeinstruction(I) <= Issuequeinstruction(I + 1);
-- translate_on
else
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I) ;
end if ;
end if ;
end loop;
if ( Flush(7) = '1' ) then
IssuequeInstrValReg(7) <= '0' ;
-- translate_off
Issuequeinstruction(7) <= (others => '0') ;
-- translate_on
else
if ( En(7) = '1' ) then
IssuequeInstrValReg(7) <= Dis_Issquenable;
IssuequeRdPhyAddrReg(7) <= Dis_NewRdPhyAddr ;
IssuequeOpcodeReg(7) <= Dis_Opcode ;
IssuequeRobTag(7) <= Dis_RobTag;
IssuequeRegWrite(7) <= Dis_RegWrite;
IssuequeRtPhyAddrReg(7) <= Dis_RtPhyAddr ;
IssuequeRsPhyAddrReg(7) <= Dis_RsPhyAddr ;
IssuequeRsReadyReg(7) <= Dis_RsDataRdy;
IssuequeRtReadyReg(7) <= Dis_RtDataRdy;
-- translate_off
Issuequeinstruction(7) <= Dis_instruction;
-- translate_on
else
IssuequeInstrValReg(7) <= IssuequeInstrValReg(7) ;
end if ;
end if ;
end if ;
end process ;
--- Selecting the Output to Go to Execution Unit, Physical Register Filed, Issue Unit
Iss_RsPhyAddrDiv <= IssuequeRsPhyAddrReg(CONV_INTEGER (unsigned( OutSelect_result))) ;
Iss_RtPhyAddrDiv <= IssuequeRtPhyAddrReg (CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RdPhyAddrDiv <= IssuequeRdPhyAddrReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_OpcodeDiv <= IssuequeOpcodeReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RobTagDiv <= IssuequeRobTag(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RegWriteDiv <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result))) ;
-- translate_off
Iss_instructionDiv <= Issuequeinstruction(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_on
end behav ;
|
gpl-2.0
|
b8adca5dfb71c06b5cf2c94cdcc04a35
| 0.534162 | 4.640896 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_3/exercise_IQ_LSQ/Lsqcntrl_r1_NEW.vhd
| 1 | 54,975 |
-- CHECKED AND MODIFIED BY PRASANJEET
-------------------------------------------
--UPDATED ON: 7/9/09, 7/13/10
-- TASK : Complete the four TODO sections
-------------------------------------------
-------------------------------------------------------------------------------
--
-- Design : Load/Store Issue Cntrl
-- Project : Tomasulo Processor
-- Author : Rohit Goel
-- ComOppany : University of Southern California
--
-------------------------------------------------------------------------------
--
-- File : Lsqcntrl.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The Issue control controls the Issuque
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity Lsquectrl is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- cdb interface
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
Cdb_Valid : in std_logic ;
-- lsq interface
Opcode : in std_logic_vector(7 downto 0);
AddrReadyBit : in std_logic_vector(7 downto 0);
AddrUpdate : out std_logic_vector(7 downto 0);
AddrUpdateSel : out std_logic_vector(7 downto 0);
-- ROB Interface
Cdb_Flush : in std_logic ;
Rob_TopPtr : in std_logic_vector (4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector (4 downto 0 ) ;
-- Dispatch / issue unit interface
Dis_LdIssquenable : in std_logic ;
Iss_LdStIssued : in std_logic ;
DCE_ReadBusy : in std_logic;
Lsbuf_Done : in std_logic;
-- shift register inputs
InstructionValidBit : in std_logic_vector(7 downto 0); -- '1' indicates instruction is valid in the buffer
RsDataValidBit : in std_logic_vector(7 downto 0); -- '1' indicates rs data is valid in the buffer
Buffer0RsTag : in std_logic_vector(5 downto 0);
Buffer1RsTag : in std_logic_vector(5 downto 0);
Buffer2RsTag : in std_logic_vector(5 downto 0);
Buffer3RsTag : in std_logic_vector(5 downto 0);
Buffer4RsTag : in std_logic_vector(5 downto 0);
Buffer5RsTag : in std_logic_vector(5 downto 0);
Buffer6RsTag : in std_logic_vector(5 downto 0);
Buffer7RsTag : in std_logic_vector(5 downto 0);
Buffer0RdTag : in std_logic_vector(4 downto 0);
Buffer1RdTag : in std_logic_vector(4 downto 0);
Buffer2RdTag : in std_logic_vector(4 downto 0);
Buffer3RdTag : in std_logic_vector(4 downto 0);
Buffer4RdTag : in std_logic_vector(4 downto 0);
Buffer5RdTag : in std_logic_vector(4 downto 0);
Buffer6RdTag : in std_logic_vector(4 downto 0);
Buffer7RdTag : in std_logic_vector(4 downto 0);
IssuqueCounter0 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter1 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter2 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter3 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter4 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter5 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter6 : in std_logic_vector ( 2 downto 0 ) ;
IssuqueCounter7 : in std_logic_vector ( 2 downto 0 ) ;
-- output control signals - group 1
Sel0 : out std_logic; -- '1' indicates update from dispatch
Flush : out std_logic_vector(7 downto 0); -- '1' indicates invalidate instruction valid bit
Sel1Rs : out std_logic_vector(7 downto 0); -- '1' indicates update from cdb - highest priority
En : out std_logic_vector(7 downto 0); -- '1' indicates update / shift
OutSelect : out std_logic_vector(2 downto 0);
IncrementCounter : out std_logic_vector(7 downto 0 ) ;
-- issue que unit control signals
Issque_LdStQueueFull : out std_logic ;
IssuequefullTemp_Upper,IssuequefullTemp_Lower : out std_logic ;
Iss_LdStReady : out std_logic ;
-- Address Buffer Signal
AddrBuffFull : in std_logic;
AddrMatch0 : in std_logic ;
AddrMatch1 : in std_logic ;
AddrMatch2 : in std_logic ;
AddrMatch3 : in std_logic ;
AddrMatch4 : in std_logic ;
AddrMatch5 : in std_logic ;
AddrMatch6 : in std_logic ;
AddrMatch7 : in std_logic ;
AddrMatch0Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch1Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch2Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch3Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch4Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch5Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch6Num : in std_logic_vector ( 2 downto 0 ) ;
AddrMatch7Num : in std_logic_vector ( 2 downto 0 ) ;
ScanAddr0 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr1 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr2 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr3 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr4 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr5 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr6 : in std_logic_vector ( 31 downto 0 ) ;
ScanAddr7 : in std_logic_vector ( 31 downto 0 )
);
end Lsquectrl ;
architecture behavctrl of Lsquectrl is
signal OutTemp : std_logic_vector ( 2 downto 0 ) ;
signal OutSelectTemp , Entemp : std_logic_vector ( 7 downto 0 ) ;
signal IssuequeReadyTemp , IssuequefullTemp,IssuequefullTemp_Upper_sig,IssuequefullTemp_Lower_sig : std_logic ;
signal Buffer0Depth, Buffer1Depth ,Buffer2Depth ,Buffer3Depth, Buffer4Depth,
Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector(4 downto 0) ;
signal OutSelectTemp2 : std_logic_vector( 7 downto 0 ) ;
begin
----------------------Generating Issuque ready -------------------------------------
Iss_LdStReady <= IssuequeReadyTemp and ( not AddrBuffFull); --so you can't issue any lw/sw when address buffer is full!! NOTE: qualify for "sw" only
---------- ----------Done Generating issuque Ready --------------------------------
-------------------- Generating Full Condition-------------------------------------
--###############################################################################################
-- TODO 1: Generate the Full control signal
--################################################################################################
process ( InstructionValidBit ,Iss_LdStIssued )
begin
if ( Iss_LdStIssued = '1' ) then --when an instruction is issued issueque is not full
IssuequefullTemp <= '0' ;
IssuequefullTemp_Upper_sig <= ----- ; --Fill in the initial values of these two signals. //almost same as Issueque full signal
IssuequefullTemp_Lower_sig <= ----- ;
else
IssuequefullTemp_Upper_sig <=InstructionValidBit(7) and InstructionValidBit(6) and
InstructionValidBit(5) and InstructionValidBit(4);
IssuequefullTemp_Lower_sig <=InstructionValidBit(3) and InstructionValidBit(2) and
InstructionValidBit(1) and InstructionValidBit(0) ;
end if ;
end process ;
IssuequefullTemp_Upper<=IssuequefullTemp_Upper_sig;
IssuequefullTemp_Lower<=IssuequefullTemp_Lower_sig;
Issque_LdStQueueFull <= -- ------------------------------------------; --Complete the right hand side of the expression
------------------ Done Generating Full Condition -------------------------------
--################################################################################################
------------------- Generating OutSelect----------------------------------------
--these are simple output select signals based on the instruction and corresponding necessary operands being ready
OutSelectTemp (0)<= AddrReadyBit(0) and InstructionValidBit(0);
OutSelectTemp (1)<= AddrReadyBit(1) and InstructionValidBit(1) ;
OutSelectTemp (2)<= AddrReadyBit(2) and InstructionValidBit(2) ;
OutSelectTemp (3)<= AddrReadyBit(3) and InstructionValidBit(3) ;
OutSelectTemp (4)<= AddrReadyBit(4) and InstructionValidBit(4) ;
OutSelectTemp (5)<= AddrReadyBit(5) and InstructionValidBit(5) ;
OutSelectTemp (6)<= AddrReadyBit(6) and InstructionValidBit(6) ;
OutSelectTemp (7)<= AddrReadyBit(7) and InstructionValidBit(7) ;
--**********************************************************************************************************
--###############################################################################################
-- TODO 2: Complete the memory disambiguation
--################################################################################################
--*****************************************************************************************************************
-- Complete the processes to satisfy the memory disambiguation rules
-- do not issue a "lw" if number of address matches is greater than the number of "sw" skipping the "lw"
-- do not issue a "sw" if any lw with unkonwn address is lying ahead of it, you need the address of the lw to make an entry in the address buffer
-- as the sw is bypassing it.
--**************************************************************************************************************
-- These processes takes care of memory disambiguation
--=====================================================
-- 1. For an instruction being a valid "lw" it can only be issued when all the "sw"(with same address) in front of it had comitted
-- This case is substantiated by address match number being less than issuecounter signal which indicates that
-- all the "sw" that were issued earlier have comitted so one can issue the lw
-- 2. For an instruction being a valid "sw" it can be issued only if all the "lw" in front of it have their address ready, this
-- Precaution is needed because you need to store the address of any bypassing sw (for any lw) if the address matches
--**************************************************************************************************************
process ( AddrMatch0Num , AddrMatch0 , IssuqueCounter0 , Opcode ,InstructionValidBit,OutSelectTemp)
begin
OutSelectTemp2(0) <= OutSelectTemp(0) ; --initialize the signal OutSelectTemp2 = OutSelectTemp
if ( opcode(0) = '1' and InstructionValidBit(0) = '1' ) then --valid "lw"
if ( AddrMatch0 = '1' ) then
if ( AddrMatch0Num > IssuqueCounter0 ) then -- "lw" can not be issued only when no of matches is greater than no of "sw"s skipping "lw"
OutSelectTemp2(0) <= '0' ;
end if ;
end if ;
end if ;
end process ;
process ( AddrMatch1Num , AddrMatch1 , IssuqueCounter1 , OutSelectTemp ,
Opcode, AddrReadyBit, InstructionValidBit, ScanAddr0 , ScanAddr1)
begin
OutSelectTemp2(1) <= OutSelectTemp(1) ;
if ( InstructionValidBit(1) = '1' ) then
if ( opcode(1) = '1' ) then --"lw""
if ( AddrMatch1 = '1' ) then
if ( AddrMatch1Num > IssuqueCounter1 ) then
OutSelectTemp2(1) <= '0' ;
end if ;
end if ;
--**********************************************************************
-- -- Mod by PRASANJEET: 7/25/09
--**********************************************************************
if(InstructionValidBit(0)= '1' and (AddrReadyBit(0) = '0' or (AddrReadyBit(0) = '1' and ( ScanAddr0 = ScanAddr1 )))and opcode(0) = '0')then -- not ready "sw" in front
OutSelectTemp2(1)<='0';
end if;
--***********************************************************************
else -- this clause states that you can issue a "sw" in the following two cases: 1. there is a sw in fornt of it 2. it has lw with known address in fornt of it. NOTE: this portion of code emphasizes on the fact that a sw can't skip a lw with unknown address. (because you need to store the address of sw in the address buffer if it matches)
--//write code for OutSelectTemp 2, 3, 4, 5, 6, 7
--*****************************************************************************************
-- Mod by PRASANJEET: 7/26/09
--*****************************************************************************************
if( InstructionValidBit(0) = '1' and (opcode(0) = '1' and AddrReadyBit(0) = '0' )) then -- Mod by PRASANJEET: 7/26/09
OutSelectTemp2(1) <= '0';
end if;
--******************************************************************************************
end if ;
end if ;
end process ;
-- Going along the same lines complete the rest of the six processes
process ( AddrMatch2Num , AddrMatch2 , IssuqueCounter2 , Opcode ,OutSelectTemp ,
InstructionValidBit , AddrReadyBit, ScanAddr0 , ScanAddr1 , ScanAddr2)
begin
OutSelectTemp2(2) <= OutSelectTemp(2) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch3Num, InstructionValidBit , AddrMatch3 , IssuqueCounter3 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3 )
begin
OutSelectTemp2(3) <= OutSelectTemp(3) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch4Num, InstructionValidBit , AddrMatch4 , IssuqueCounter4 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4 )
begin
OutSelectTemp2(4) <= OutSelectTemp(4) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch5Num, InstructionValidBit , AddrMatch5 , IssuqueCounter5 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4, ScanAddr5 )
begin
OutSelectTemp2(5) <= OutSelectTemp(5) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch6Num, InstructionValidBit , AddrMatch6 , IssuqueCounter6 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6 )
begin
OutSelectTemp2(6) <= OutSelectTemp(6) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
process ( AddrMatch7Num, InstructionValidBit , AddrMatch7 , IssuqueCounter7 , Opcode ,OutSelectTemp,
AddrReadyBit, ScanAddr0 , ScanAddr1 , Scanaddr2, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7 )
begin
OutSelectTemp2(7) <= OutSelectTemp(7) ;
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
--------------------------------------------
end process ;
--##################################################################################################################
--***************************************************************************************
-- This process is used to assign priority so that only one instruction is issued even
-- when multiple instructions are ready to be issued
--***************************************************************************************
process ( OutSelectTemp2) --to issue only one at a time, priority is given over here
begin
Outtemp <= "000" ;
if ( OutSelectTemp2(0) = '1') then
Outtemp <= "000" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(1) = '1' ) then
Outtemp <= "001" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(2) = '1') then
Outtemp <= "010" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(3) = '1') then
Outtemp <= "011" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(4) = '1') then
Outtemp <= "100" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(5) = '1') then
Outtemp <= "101" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(6) = '1') then
Outtemp <= "110" ;
IssuequeReadyTemp <= '1' ;
else
if ( OutSelectTemp2(7) = '1') then
Outtemp <= "111" ;
IssuequeReadyTemp <= '1' ;
else
IssuequeReadyTemp <= '0' ;
end if ;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process ;
OutSelect <= Outtemp ;
------------------------------------Done Generating OutSelect ------------------------------------------
--********************************************************************************************************
-- These processes keep track of bypassing "sw" for every entry of "lw"
-- The increment counter signal is sort of count enable that increments the corresponding counter for a "lw"
-- If the bypassing "sw" has the same address
--***********************************************************************************************************
process ( Outtemp , opcode , ScanAddr0 , ScanAddr1 , ScanAddr2 , ScanAddr3,
ScanAddr4 , ScanAddr5 , ScanAddr6 , ScanAddr7,Iss_LdStIssued ) -- generating the done signal as well as incrementing the counter to make note of sw skipping lw
begin --gives the total no. of address matches
IncrementCounter(0) <= '0' ;
if ( opcode(0) = '1' and Iss_LdStIssued = '1' ) then -- an "lw/sw" instruction is about to be issued so make a note of it
case Outtemp is
when "000" => IncrementCounter(0) <= '0' ;
when "001" => if ( ScanAddr0 = ScanAddr1 ) then
IncrementCounter(0) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(0) <= '0' ;
end if ;
when "010" => if ( ScanAddr0 = ScanAddr2 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
when "011" => if ( ScanAddr0 = ScanAddr3 ) then
IncrementCounter(0) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(0) <= '0' ;
end if ;
when "100" => if ( ScanAddr0 = ScanAddr4 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
when "101" => if ( ScanAddr0 = ScanAddr5 ) then
IncrementCounter(0) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(0) <= '0' ;
end if ;
when "110" => if ( ScanAddr0 = ScanAddr6 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
when others => if ( ScanAddr0 = ScanAddr7 ) then
IncrementCounter(0) <= '1' ;
else
IncrementCounter(0) <= '0' ;
end if ;
end case ;
end if ;
end process ;
process ( Outtemp , opcode ,Iss_LdStIssued, ScanAddr1 , ScanAddr2 , ScanAddr3, ScanAddr4,
ScanAddr5, ScanAddr6, ScanAddr7)
begin
IncrementCounter(1) <= '0' ;
if ( opcode(1) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(1) <= '0' ;
when "001" => IncrementCounter(1) <= '0' ;
when "010" => if ( ScanAddr1 = ScanAddr2) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
when "011" => if ( ScanAddr1 = ScanAddr3 ) then
IncrementCounter(1) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(1) <= '0' ;
end if ;
when "100" => if ( ScanAddr1 = ScanAddr4 ) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
when "101" => if ( ScanAddr1 = ScanAddr5 ) then
IncrementCounter(1) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(1) <= '0' ;
end if ;
when "110" => if ( ScanAddr1 = ScanAddr6 ) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
when others => if ( ScanAddr1 = ScanAddr7 ) then
IncrementCounter(1) <= '1' ;
else
IncrementCounter(1) <= '0' ;
end if ;
end case ;
end if ;
end process ;
process ( Outtemp, opcode, ScanAddr2, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(2) <= '0' ;
if ( opcode(2) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(2) <= '0' ;
when "001" => IncrementCounter(2) <= '0' ;
when "010" => IncrementCounter(2) <= '0' ;
when "011" => if ( ScanAddr2 = ScanAddr3 ) then
IncrementCounter(2) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(2) <= '0' ;
end if ;
when "100" => if ( ScanAddr2 = ScanAddr4 ) then
IncrementCounter(2) <= '1' ;
else
IncrementCounter(2) <= '0' ;
end if ;
when "101" => if ( ScanAddr2 = ScanAddr5 ) then
IncrementCounter(2) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(2) <= '0' ;
end if ;
when "110" => if ( ScanAddr2 = ScanAddr6 ) then
IncrementCounter(2) <= '1' ;
else
IncrementCounter(2) <= '0' ;
end if ;
when others => if ( ScanAddr2 = ScanAddr7 ) then
IncrementCounter(2) <= '1' ;
else
IncrementCounter(2) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr3, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(3) <= '0' ;
if ( opcode(3) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(3) <= '0' ;
when "001" => IncrementCounter(3) <= '0' ;
when "010" => IncrementCounter(3) <= '0' ;
when "011" => IncrementCounter(3) <= '0' ;
when "100" => if ( ScanAddr3 = ScanAddr4 ) then
IncrementCounter(3) <= '1' ;
else
IncrementCounter(3) <= '0' ;
end if ;
when "101" => if ( ScanAddr3 = ScanAddr5 ) then
IncrementCounter(3) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(3) <= '0' ;
end if ;
when "110" => if ( ScanAddr3 = ScanAddr6 ) then
IncrementCounter(3) <= '1' ;
else
IncrementCounter(3) <= '0' ;
end if ;
when others => if ( ScanAddr3 = ScanAddr7 ) then
IncrementCounter(3) <= '1' ;
else
IncrementCounter(3) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr4, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(4) <= '0' ;
if ( opcode(4) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(4) <= '0' ;
when "001" => IncrementCounter(4) <= '0' ;
when "010" => IncrementCounter(4) <= '0' ;
when "011" => IncrementCounter(4) <= '0' ;
when "100" => IncrementCounter(4) <= '0' ;
when "101" => if ( ScanAddr4 = ScanAddr5 ) then
IncrementCounter(4) <= '1' ; -- it is sort of counter enable
else
IncrementCounter(4) <= '0' ;
end if ;
when "110" => if ( ScanAddr4 = ScanAddr6 ) then
IncrementCounter(4) <= '1' ;
else
IncrementCounter(4) <= '0' ;
end if ;
when others => if ( ScanAddr4 = ScanAddr7 ) then
IncrementCounter(4) <= '1' ;
else
IncrementCounter(4) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr5, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(5) <= '0' ;
if ( opcode(5) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(5) <= '0' ;
when "001" => IncrementCounter(5) <= '0' ;
when "010" => IncrementCounter(5) <= '0' ;
when "011" => IncrementCounter(5) <= '0' ;
when "100" => IncrementCounter(5) <= '0' ;
when "101" => IncrementCounter(5) <= '0' ;
when "110" => if ( ScanAddr5 = ScanAddr6 ) then
IncrementCounter(5) <= '1' ;
else
IncrementCounter(5) <= '0' ;
end if ;
when others => if ( ScanAddr5 = ScanAddr7 ) then
IncrementCounter(5) <= '1' ;
else
IncrementCounter(5) <= '0' ;
end if ;
end case ;
end if;
end process ;
process ( Outtemp, opcode, ScanAddr6, ScanAddr7, Iss_LdStIssued )
begin
IncrementCounter(6) <= '0' ;
if ( opcode(6) = '1' and Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" => IncrementCounter(6) <= '0' ;
when "001" => IncrementCounter(6) <= '0' ;
when "010" => IncrementCounter(6) <= '0' ;
when "011" => IncrementCounter(6) <= '0' ;
when "100" => IncrementCounter(6) <= '0' ;
when "101" => IncrementCounter(6) <= '0' ;
when "110" => IncrementCounter(6) <= '0' ;
when others => if ( ScanAddr6 = ScanAddr7 ) then
IncrementCounter(6) <= '1' ;
else
IncrementCounter(6) <= '0' ;
end if ;
end case ;
end if;
end process ;
IncrementCounter(7) <= '0' ; --since the last so will always be '0'
----------------------------------- Generating Address Update Condition--------------------
--********************************************************************************************************************************
-- This process takes care of address updating conditions, there are two control signals
-- 1. the addrupdate which tell i need to update the "rs" field data for address calculation on this entry
-- 2. The addrupdate sel which when "0" indicates that i have the valid rs field data with me so i update myself with my own data
-- when "1" indicates that i will get the updated rs field data from the entry above me
--*********************************************************************************************************************************
process ( RsDataValidBit, Entemp, Outtemp, AddrReadyBit, Iss_LdStIssued, InstructionValidBit)
begin
AddrUpdate <= "00000000" ; -- i want to update this address
AddrUpdateSel <= "00000000" ; -- whether to update from the one above me (1)/or from me(0)
if( Iss_LdStIssued = '1' ) then
case Outtemp is
when "000" =>
AddrUpdateSel (7 downto 0) <= '0' & RsDataValidBit (7 downto 1);
for i in 0 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit(i+1); -- if address is ready no need to update!!
end if;
end loop;
AddrUpdate (7) <= '0';
when "001" =>
if( (RsDataValidBit(0) ='1') and (AddrReadyBit(0) = '0') ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
AddrUpdateSel (7 downto 1) <= '0' & RsDataValidBit (7 downto 2);
for i in 1 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "010" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
AddrUpdateSel (7 downto 2) <= '0' & RsDataValidBit (7 downto 3);
for i in 2 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "011" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
AddrUpdateSel (7 downto 3) <= '0' & RsDataValidBit (7 downto 4);
for i in 3 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "100" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
AddrUpdateSel (7 downto 4) <= '0' & RsDataValidBit (7 downto 5);
for i in 4 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "101" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
if(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '0' ;
end if;
AddrUpdateSel (7 downto 5) <= '0' & RsDataValidBit (7 downto 6);
for i in 5 to 6 loop
if (RsDataValidBit (i+1) = '1') then
AddrUpdate (i) <= not AddrReadyBit (i+1);
end if;
end loop;
AddrUpdate (7) <= '0';
when "110" =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
if(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '0' ;
end if;
if(RsDataValidBit(5) = '1' and AddrReadyBit(5) = '0' ) then
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '0' ;
end if;
AddrUpdateSel (7 downto 6) <= '0' & RsDataValidBit (7);
if (RsDataValidBit (7) = '1') then
AddrUpdate (6) <= not AddrReadyBit (7);
end if;
AddrUpdate (7) <= '0';
when others =>
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
end if;
if(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '0' ;
end if;
if(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
end if;
if(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
end if;
if(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '0' ;
end if;
if(RsDataValidBit(5) = '1' and AddrReadyBit(5) = '0' ) then
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '0' ;
end if;
if(RsDataValidBit(6) = '1' and AddrReadyBit(6) = '0' ) then
AddrUpdate(6) <= '1';
AddrUpdateSel(6) <= '0' ;
end if;
AddrUpdate(7) <= '0';
AddrUpdateSel(7) <= '0' ;
end case ;
else
if(RsDataValidBit(0) = '1' and AddrReadyBit(0) = '0' ) then
AddrUpdate(0) <= '1';
AddrUpdateSel(0) <= '0' ;
elsif(RsDataValidBit(1) = '1' and AddrReadyBit(1) = '0' ) then
if ( Entemp(0) = '0' ) then
AddrUpdate(1) <= '1'; --not moving so update myself
AddrUpdateSel(1) <= '0' ;
else
AddrUpdate(0) <= '1'; -- update as per the below one is moving
AddrUpdateSel(0) <= '1' ;
end if ;
elsif(RsDataValidBit(2) = '1' and AddrReadyBit(2) = '0' ) then
if ( Entemp(1) = '0' ) then
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '0' ;
else
AddrUpdate(1) <= '1';
AddrUpdateSel(1) <= '1' ;
end if ;
elsif(RsDataValidBit(3) = '1' and AddrReadyBit(3) = '0' ) then
if ( Entemp(2) = '0' ) then
AddrUpdate(3) <= '1';
AddrUpdateSel(3) <= '0' ;
else
AddrUpdate(2) <= '1';
AddrUpdateSel(2) <= '1' ;
end if;
elsif(RsDataValidBit(4) = '1' and AddrReadyBit(4) = '0' ) then
if ( Entemp(3) = '0' ) then
AddrUpdate(4) <= '1'; --not moving so update myself
AddrUpdateSel(4) <= '0' ;
else
AddrUpdate(3) <= '1'; -- update as per the below one is moving
AddrUpdateSel(3) <= '1' ;
end if ;
elsif(RsDataValidBit(5) = '1' and AddrReadyBit(5) = '0' ) then
if ( Entemp(4) = '0' ) then
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '0' ;
else
AddrUpdate(4) <= '1';
AddrUpdateSel(4) <= '1' ;
end if ;
elsif(RsDataValidBit(6) = '1' and AddrReadyBit(6) = '0' ) then
if ( Entemp(5) = '0' ) then
AddrUpdate(6) <= '1';
AddrUpdateSel(6) <= '0' ;
else
AddrUpdate(5) <= '1';
AddrUpdateSel(5) <= '1' ;
end if;
elsif(RsDataValidBit(7) = '1' and AddrReadyBit(7) = '0' ) then
if ( Entemp(6) = '0' ) then
AddrUpdate(7) <= '1';
AddrUpdateSel(7) <= '0' ;
else
AddrUpdate(6) <= '1';
AddrUpdateSel(6) <= '1' ;
end if;
else
AddrUpdate <= "00000000" ; -- i want to update this address
AddrUpdateSel <= "00000000" ;
end if;
end if ;
end process;
-----------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- hereonwards same as in issuequeues
----------------------------------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 3: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= --------------------------; //unsigned subraction
Buffer1Depth <= --------------------------;
Buffer2Depth <= --------------------------;
Buffer3Depth <= --------------------------;
Buffer4Depth <= --------------------------;
Buffer5Depth <= --------------------------;
Buffer6Depth <= --------------------------;
Buffer7Depth <= --------------------------;
--################################################################################################
--****************************************************************************************
-- This process takes care of selective flushing and also takes care of shift aspect while
-- doing the selective flushing, i.e if 1 get a shift update signal then instead of flushing
-- myself 1 will be 0 instead (as 1 gets shifted to the place of 0) but remember when flushing
-- 1 you will be checking bufferdepth 1 and entemp(0) as entemp(0) means 1 is shifting to 0 place
--******************************************************************************************
--###############################################################################################
-- TODO 4: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth, Buffer4Depth, Buffer5Depth,
Buffer7Depth, Buffer6Depth, Entemp, InstructionValidBit)
begin
Flush <= "00000000";
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then --note this depth is calculated with respect to branch instruction
if ( EnTemp(0) = '0' ) then
Flush(0) <= InstructionValidBit(0) ;
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then
if ( Entemp(0) = '1' ) then
Flush(0) <= ---------------------------------------; Hint: Take into account the shift mechanism so is it i or i+1 or i - 1? -- flush only when instructionvalidbit is 1??? only flush the valid instructions //similar to integer_queue
else
Flush(1) <= InstructionValidBit(1) ;
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( Entemp(1) = '1' ) then
Flush(1) <= ---------------------------------------;
else
Flush(2) <= InstructionValidBit(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( Entemp(2) = '1' ) then
Flush(2) <= ---------------------------------------;
else
Flush(3) <= InstructionValidBit(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( Entemp(3) = '1' ) then
Flush(3) <= ---------------------------------------;
else
Flush(4) <= InstructionValidBit(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( Entemp(4) = '1' ) then
Flush(4) <= ---------------------------------------;
else
Flush(5) <= InstructionValidBit(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( Entemp(5) = '1' ) then
Flush(5) <= ---------------------------------------;
else
Flush(6) <= InstructionValidBit(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( Entemp(6) = '1' ) then
Flush(6) <= ---------------------------------------;
else
Flush(7) <= InstructionValidBit(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--################################################################################################
---------------------- Generating Rs and Rt Select for Queues to Update from Dispatch -----
Sel0 <= Dis_LdIssquenable ;
En <= Entemp ;
--***********************************************************************
-- this process deals with generation of enable temp signal
--***********************************************************************
process ( OutTemp, Iss_LdStIssued, InstructionValidBit, Dis_LdIssquenable )
begin
if ( Iss_LdStIssued = '1' ) then
Case (OutTemp) is
when "000" => Entemp <= "11111111" ;
when "001" => Entemp <= "11111110" ;
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else
Entemp(0) <= not (InstructionValidBit(0));
Entemp(1) <= ( not (InstructionValidBit(1))) or ( not (InstructionValidBit(0) )) ;
Entemp(2) <= (not (InstructionValidBit(2)))or (not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ));
Entemp(3) <= (not (InstructionValidBit(3))) or (not (InstructionValidBit(2) ))or
( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(4) <= (not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or
(not (InstructionValidBit(2) ))or( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(5) <= (not (InstructionValidBit(5))) or (not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or
(not (InstructionValidBit(2) ))or( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(6) <= (not (InstructionValidBit(6))) or (not (InstructionValidBit(5))) or
(not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or
(not (InstructionValidBit(2) ))or( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
Entemp(7) <= Dis_LdIssquenable or (not (InstructionValidBit(6))) or (not (InstructionValidBit(5))) or
(not (InstructionValidBit(4))) or (not (InstructionValidBit(3))) or(not (InstructionValidBit(2) )) or
( not (InstructionValidBit(1) )) or ( not (InstructionValidBit(0) ) ) ;
end if ;
end process ;
--*******************************************************************************************
-- This process does updation of rs data as done in issuequecntrl
--********************************************************************************************
process ( Buffer0RsTag ,Buffer1RsTag, Buffer2RsTag, Buffer3RsTag, InstructionValidBit,
Buffer7RsTag, Buffer4RsTag, Buffer5RsTag, Buffer6RsTag, Cdb_RdPhyAddr, Cdb_Valid, Entemp, RsDataValidBit,Cdb_PhyRegWrite)
begin
Sel1Rs <= "00000000" ;
if ( Cdb_Valid = '1' ) then --updation from CDB
if ( Buffer0RsTag = Cdb_RdPhyAddr and RsDataValidBit(0) ='0' and InstructionValidBit(0) = '1' and Cdb_PhyRegWrite ='1' ) then
Sel1Rs(0) <= '1' ;
end if ;
if ( Buffer1RsTag = Cdb_RdPhyAddr and RsDataValidBit(1) ='0'and InstructionValidBit(1) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (0) = '1' ) then
Sel1Rs(0) <= '1' ;
else
Sel1Rs(1) <= '1' ;
end if ;
end if ;
if ( Buffer2RsTag = Cdb_RdPhyAddr and RsDataValidBit(2) ='0'and InstructionValidBit(2) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (1) = '1' ) then
Sel1Rs(1) <= '1' ;
else
Sel1Rs(2) <= '1' ;
end if ;
end if ;
if ( Buffer3RsTag = Cdb_RdPhyAddr and RsDataValidBit(3) ='0'and InstructionValidBit(3) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (2) = '1' ) then
Sel1Rs(2) <= '1' ;
else
Sel1Rs(3) <= '1' ;
end if ;
end if ;
if ( Buffer4RsTag = Cdb_RdPhyAddr and RsDataValidBit(4) ='0'and InstructionValidBit(4) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (3) = '1' ) then
Sel1Rs(3) <= '1' ;
else
Sel1Rs(4) <= '1' ;
end if ;
end if ;
if ( Buffer5RsTag = Cdb_RdPhyAddr and RsDataValidBit(5) ='0'and InstructionValidBit(5) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (4) = '1' ) then
Sel1Rs(4) <= '1' ;
else
Sel1Rs(5) <= '1' ;
end if ;
end if ;
if ( Buffer6RsTag = Cdb_RdPhyAddr and RsDataValidBit(6) ='0'and InstructionValidBit(6) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (5) = '1' ) then
Sel1Rs(5) <= '1' ;
else
Sel1Rs(6) <= '1' ;
end if ;
end if ;
if ( Buffer7RsTag = Cdb_RdPhyAddr and RsDataValidBit(7) ='0' and InstructionValidBit(7) = '1' and Cdb_PhyRegWrite ='1' ) then
if ( Entemp (6) = '1' ) then
Sel1Rs(6) <= '1' ;
else
Sel1Rs(7) <= '1' ;
end if ;
end if ;
else
Sel1Rs <= "00000000" ;
end if ;
end process ;
end behavctrl ;
----------------------------------------------------------------------------------------------------
|
gpl-2.0
|
764b67d5fe072df0cb8f8c89066b728c
| 0.416789 | 4.851306 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/RAS.vhd
| 1 | 5,608 |
------------------------------------------------------------------------------------------------------------------------------------
--********************************************************************************************************************
-- Design : Return Address Stack
-- Project : EE560 Summer 2010
-- Entity : ras
-- Author : Varun Khadilkar
-- Company : University of Southern California
-- Last Updated : March 19, 2010
--********************************************************************************************************************
------------------------------------------------------------------------------------------------------------------------------------
--Comments:
--Mar 23 : Last location is never emptied. Added extra register to empty last locations.
--Mar 19 : TOSP, TOSP+1 changed from integer to counters. Removed ras_addr_valid. Now we give help from RAS all the time
--Mar 8 : Can we help even if RAS is empty? Keep driving output with last value. Change the code.
--Mar 5 : New code Complete.
--Mar 1 : Some singals needs to be continuously driven, e.g. Output ADDR by RAS. Change.
--Feb 25 : RAS in Dispatch. Code changed. Now component of Dipatch stage. Checkpoints removed.
--Feb 21 : RAS no longer in Fetch !! Change Design.
--Feb 16 : RAS Design updated. RAS to be checkpointed. Detail Circuit Diagram designed.
--Feb 12 : RAS Designed. 4 location. 32 wide. In Fetch.
------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_signed.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
------------------------------------------------------------------------------------------------------------------------------------
entity ras is
generic (size : integer :=4);
port(
--global signals
Resetb : in std_logic;
Clk : in std_logic;
-- Interface with Dispatch
--inputs
Dis_PcPlusFour : in std_logic_vector(31 downto 0); -- the PC+4 value carried forward for storing in RAS
Dis_RasJalInst : in std_logic; -- set to 1 if instruction is JAL
Dis_RasJr31Inst : in std_logic; -- set to 1 if instruction is JR
--outputs
Ras_Addr : out std_logic_vector(31 downto 0) -- The address given by RAS for JR
);
end ras;
-------------------------------------------------------------------------------------------------------------------------------------------
architecture ras_arch of ras is
-- RAS counter
-- Used to Keep track of how filled is Stack. "000" means Empty. "100" means Full.
-- Counter Saturates at "100". This means even if we push more data, we can have only latest 4 stored.
signal RasCounter : std_logic_vector (2 downto 0);
-- Top of the stack pointer
-- Tosp in this design Points to the FILLED LOCATION. Thus we always push at TospPlusOne. But Pop from Tosp.
signal Tosp : std_logic_vector (1 downto 0);
signal TospPlusOne : std_logic_vector (1 downto 0);
--RAS data
-- UseWhen Empty latches the last Poped address and drives output when RAS is empty.
-- Thus for external World, RAS is never empty. It keeps giving data which is a prediction and may be wrong.
signal UseWhenEmpty : std_logic_vector(31 downto 0);
subtype RasData is std_logic_vector(31 downto 0);
type RasDepth is array(0 to size-1) of RASData;
signal Ras : RasDepth;
-------------------------------------------------------------------------------------------------------------------------------------------
begin
--Ras_Addr is continueously giving address stored at location pointed by TOSP
--This way we can POP data stored in RAS without wasting a clock.
Ras_Addr <= Ras(CONV_INTEGER (unsigned( Tosp))) when RasCounter /= "000" else UseWhenEmpty;
process (Clk, Resetb)
begin
-- in Resetb, we set ras counter to zero (ras is empty)
-- tosp and tospplusone both point to zero. but its fine because as soon as we start filling ras, they are updated as desired.
--
if (Resetb = '0') then
Rascounter <= "000";
Tosp <= "11";
TospPlusOne <= "00";
UseWhenEmpty <= (others => '0');
for i in (size-1) downto 0 loop
Ras(i) <= (others => '0');
end loop;
elsif (Clk'event and Clk = '1') then
if (Dis_RasJalInst = '1') then
-- NOTE: we push on tospplusone and not tosp.
-- This is because in our design, top of the stack pointer (TOSP) always points to a filled location.
--Thus when we need to push data onto RAS, we have to do it at TOSP+1.
Ras(CONV_INTEGER (unsigned( TospPlusOne))) <= Dis_PcPlusFour;
--if instruction is JAL, we advise to push PC+4 in RAS at the next clock edge, increment TOSP and RASCON
Tosp <= Tosp + 1;
TospPlusOne <= TospPlusOne + 1;
Rascounter <= Rascounter + 1;
if (Rascounter = "100") then Rascounter <= "100"; end if;
end if;
--if instruction is JR, if RASCON is not zero, then we advise to decrement TOSP and RASCON on next clock edge.
if (Dis_RasJr31Inst = '1' ) then
if (Rascounter /= "000") then
TospPlusOne <= TospPlusOne - 1;
Tosp <= Tosp - 1;
Rascounter <= Rascounter - 1;
UseWhenEmpty <= Ras(CONV_INTEGER (unsigned( Tosp)));
end if;
end if;
end if;
end process;
end ras_arch;
-------------------------------------------------------------------------------------------------------------------------------------
|
gpl-2.0
|
be8408b7095945edb30b89c788765fb0
| 0.516049 | 4.197605 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Command_FIFO/simulation/fg_tb_synth.vhd
| 1 | 10,001 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : Command_FIFO_top
PORT MAP (
CLK => clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
5a4199e6d8ff9515387e9a47107cb2a9
| 0.457354 | 4.18627 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/one_shot.vhd
| 1 | 1,429 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- one_shot.vhd
--
-- Reduces when a positive edge is detected on the input signal, a 1 clock long
-- high is output on sig_out.
--
--**********************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ENTITY one_shot IS
PORT
(
clk: in std_logic;
sig_in: in std_logic;
rst: in std_logic;
sig_out: out std_logic
);
END one_shot;
ARCHITECTURE one_shot_arch OF one_shot IS
subtype state is integer range 2 downto 0;
SIGNAL current_state, next_state: state;
BEGIN
comb_state_change: process(current_state, sig_in) is
begin
--default actions
next_state <= current_state;
case current_state is
when 0 =>
sig_out <= '0';
if sig_in = '1' then
next_state <= 1;
end if;
when 1 =>
sig_out <= '1';
next_state <= 2;
when 2 =>
sig_out <= '0';
if sig_in = '0' then
next_state <= 0;
end if;
end case;
end process comb_state_change;
--Change state on clock
state_reg: process( clk, rst ) is
begin
if rst = '0' then
current_state <= 0;
elsif clk'event and clk='1' then
current_state <= next_state;
end if;
end process state_reg;
END one_shot_arch;
|
gpl-3.0
|
910053d51a29bbc1411b2fefb476e4a8
| 0.554234 | 3.233032 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/write_data_fifo/example_design/write_data_fifo_top_wrapper.vhd
| 1 | 19,554 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: write_data_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity write_data_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(256-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(13-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(13-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(13-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end write_data_fifo_top_wrapper;
architecture xilinx of write_data_fifo_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component write_data_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : write_data_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
4cdbb2e9082df9bc280fdda9cf538778
| 0.485118 | 3.9583 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/write_data_fifo/simulation/fg_tb_dgen.vhd
| 36 | 4,510 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
gpl-2.0
|
586d89b40dcb050cb9343d3685759a4f
| 0.598226 | 4.211018 | false | false | false | false |
PiJoules/Zybo-Vision-Processing
|
hdmi_passthrough_720p.srcs/sources_1/bd/design_1/ip/design_1_rgb2vga_0_0/synth/design_1_rgb2vga_0_0.vhd
| 1 | 4,991 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:rgb2vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_rgb2vga_0_0 IS
PORT (
rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pVDE : IN STD_LOGIC;
rgb_pHSync : IN STD_LOGIC;
rgb_pVSync : IN STD_LOGIC;
PixelClk : IN STD_LOGIC;
vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pHSync : OUT STD_LOGIC;
vga_pVSync : OUT STD_LOGIC
);
END design_1_rgb2vga_0_0;
ARCHITECTURE design_1_rgb2vga_0_0_arch OF design_1_rgb2vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rgb2vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb2vga IS
GENERIC (
VID_IN_DATA_WIDTH : INTEGER;
kRedDepth : INTEGER;
kGreenDepth : INTEGER;
kBlueDepth : INTEGER
);
PORT (
rgb_pData : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pVDE : IN STD_LOGIC;
rgb_pHSync : IN STD_LOGIC;
rgb_pVSync : IN STD_LOGIC;
PixelClk : IN STD_LOGIC;
vga_pRed : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pGreen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
vga_pBlue : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
vga_pHSync : OUT STD_LOGIC;
vga_pVSync : OUT STD_LOGIC
);
END COMPONENT rgb2vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rgb2vga_0_0_arch: ARCHITECTURE IS "rgb2vga,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rgb2vga_0_0_arch : ARCHITECTURE IS "design_1_rgb2vga_0_0,rgb2vga,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rgb_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in DATA";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF rgb_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 vid_in VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 signal_clock CLK";
BEGIN
U0 : rgb2vga
GENERIC MAP (
VID_IN_DATA_WIDTH => 24,
kRedDepth => 5,
kGreenDepth => 6,
kBlueDepth => 5
)
PORT MAP (
rgb_pData => rgb_pData,
rgb_pVDE => rgb_pVDE,
rgb_pHSync => rgb_pHSync,
rgb_pVSync => rgb_pVSync,
PixelClk => PixelClk,
vga_pRed => vga_pRed,
vga_pGreen => vga_pGreen,
vga_pBlue => vga_pBlue,
vga_pHSync => vga_pHSync,
vga_pVSync => vga_pVSync
);
END design_1_rgb2vga_0_0_arch;
|
unlicense
|
1ea49640dca0564b2b2907c1073aec94
| 0.707674 | 3.713542 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Move_FIFO_4KB/example_design/Move_FIFO_4KB_top_wrapper.vhd
| 1 | 19,274 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Move_FIFO_4KB_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Move_FIFO_4KB_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(16-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(11-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(11-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(11-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(11-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(8-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end Move_FIFO_4KB_top_wrapper;
architecture xilinx of Move_FIFO_4KB_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component Move_FIFO_4KB_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : Move_FIFO_4KB_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
11930c1e4710e65a2d745fcb7c9945c1
| 0.484643 | 3.9577 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/tx_buf/simulation/fg_tb_pkg.vhd
| 1 | 11,423 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT tx_buf_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
95034cb0903759c778689b5e0daa98dc
| 0.503108 | 3.937608 | false | false | false | false |
csrhau/sandpit
|
VHDL/test_utils/test_test_utils.vhdl
| 1 | 1,441 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_utils.all;
entity test_test_utils is
end test_test_utils;
architecture behavioural of test_test_utils is
begin
process
variable test_chr : character;
variable test_str : string(1 to 8);
begin
test_chr := '0';
assert sl2chr('0') = test_chr report "Mismatch" severity error;
test_chr := '1';
assert sl2chr('1') = test_chr report "Mismatch" severity error;
test_chr := 'X';
assert sl2chr('X') = test_chr report "Mismatch" severity error;
test_chr := 'U';
assert sl2chr('U') = test_chr report "Mismatch" severity error;
test_chr := 'H';
assert sl2chr('H') = test_chr report "Mismatch" severity error;
test_chr := 'L';
assert sl2chr('L') = test_chr report "Mismatch" severity error;
test_chr := 'Z';
assert sl2chr('Z') = test_chr report "Mismatch" severity error;
test_chr := '-';
assert sl2chr('-') = test_chr report "Mismatch" severity error;
-- Sanity check to make sure that I'm not just comparing chars (should not compile)
-- test_chr := 'Y';
-- assert sl2chr('Y') = test_chr report "Mismatch" severity error;
test_str := "01XUHLZ-";
assert slv2str("01XUHLZ-") = test_str report "Mismatch" severity error;
test_str := "01010101";
assert slv2str("01010101") = test_str report "Mismatch" severity error;
wait;
end process;
end behavioural;
|
mit
|
30b0aaa25d8438a716eb5628508425a6
| 0.650937 | 3.414692 | false | true | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/Free_register_list_exercise.vhd
| 3 | 3,142 |
-- Modified by Da Cheng in Summer 2010
-------------------------------------------------------------------------------
-- Description:
-- Free register list keeps track of physical register IDs, used to solve read/write dependency.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Entity declaration
entity Frl is
generic (WIDE:integer:= 6 ; DEEP:integer:=16 ; PTRWIDTH:integer:=5);
port (
--Inputs
Clk : in std_logic;
Resetb : in std_logic;
Cdb_Flush : in std_logic;
--Interface with Rob
Cfc_FrlHeadPtr : in std_logic_vector(PTRWIDTH-1 downto 0);
Rob_CommitPrePhyAddr : in std_logic_vector(WIDE-1 downto 0);
Rob_CommitRegWrite : in std_logic;
Rob_Commit : in std_logic;
--Intreface with Dis_FrlRead unit
Dis_FrlRead : in std_logic;
Frl_RdPhyAddr : out std_logic_vector(WIDE-1 downto 0);
Frl_Empty : out std_logic;
--Interface with Previous Head Pointer Stack
Frl_HeadPtr : out std_logic_vector(PTRWIDTH-1 downto 0)
);
end Frl;
architecture behav of Frl is
subtype freeregid is std_logic_vector(WIDE-1 downto 0);
type freeregid1 is array(0 to DEEP-1) of freeregid;
signal freereglist:freeregid1;
signal Frl_HeadPtr_temp : std_logic_vector(PTRWIDTH-1 downto 0) ;
signal Frl_TailPtr : std_logic_vector(PTRWIDTH-1 downto 0) ;
begin
-- Task 1: Fill in the process with how to update FRL
Process(Clk,Resetb)
--variable i:integer;
begin
if (Resetb = '0') then
-- Initialization of FRL contents: location 0 =physical register 32
-- location15 =physical register 47
freereglist(15) <= "101111";
freereglist(14) <= "101110";
freereglist(13) <= "101101";
freereglist(12) <= "101100";
freereglist(11) <= "101011";
freereglist(10) <= "101010";
freereglist(9) <= "101001";
freereglist(8) <= "101000";
freereglist(7) <= "100111";
freereglist(6) <= "100110";
freereglist(5) <= "100101";
freereglist(4) <= "100100";
freereglist(3) <= "100011";
freereglist(2) <= "100010";
freereglist(1) <= "100001";
freereglist(0) <= "100000";
Frl_HeadPtr_temp <= "00000";
Frl_TailPtr <= "10000";
elsif ( Clk'event and Clk = '1' ) then
-- Update head pointer when dispatch and flush
if (Cdb_Flush = '1') then --Phase 2, checkpoints and walk forward/backward?
Frl_HeadPtr_temp <= Cfc_FrlHeadPtr;
elsif (Dis_FrlRead = '1') then
Frl_HeadPtr_temp <= Frl_HeadPtr_temp + '1';
end if;
-- Update tail pointer when commit
-- Free physical registers when commit
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Frl_TailPtr <= Frl_TailPtr + '1';
freereglist( conv_integer(unsigned(Frl_TailPtr(3 downto 0))) ) <= Rob_CommitPrePhyAddr;
end if;
end if;
end process;
-- Task 2: generate the two signals: Frl_Empty and Frl_RdPhyAddr.
Frl_Empty <= '1' when (Frl_HeadPtr_temp = Frl_TailPtr) else '0';
Frl_RdPhyAddr <= freereglist( conv_integer(unsigned(Frl_HeadPtr_temp(3 downto 0))) );
Frl_HeadPtr <= Frl_HeadPtr_temp;
end architecture behav;
|
gpl-2.0
|
d1fc420af0b766d8fbaa2f3e23410a6e
| 0.640356 | 3.259336 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/ssd_command_fifo/example_design/ssd_command_fifo_top.vhd
| 2 | 5,011 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ssd_command_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ssd_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end ssd_command_fifo_top;
architecture xilinx of ssd_command_fifo_top is
SIGNAL clk_i : std_logic;
component ssd_command_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : ssd_command_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
ba7f9f94ece105ca6b9f74cf663ae327
| 0.524845 | 4.903131 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_send_fifo/simulation/fg_tb_pctrl.vhd
| 2 | 20,673 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-2.0
|
6e1a4837765abcba7ce6e8deaecc33a5
| 0.50786 | 3.18242 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
fifo_core.vhd
| 1 | 13,449 |
-- Greg Stitt
-- University of Florida
-- Description:
-- This file implements the fifo_core entity, which defines the architecture the
-- fifo entity (see fifo.vhd).
--
-- The entity contains architectures for using flips (FF) or memory (MEMORY)
-- when synthesized.
-- Notes:
-- The fifo protects against invalid writes (i.e. when full) and invalid reads
-- (i.e. when empty)
--
-- use_bram = true and same_cycle_output = true is not supported by
-- all FPGAs.
--
-- All FIFO depths are currently rounded up to the nearest power of two.
-- Used entities:
-- ram (in BRAM architecture)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : the width of the FIFO in bits (required)
-- depth : the depth of the FIFO in words (required)
-- almost_full_count : the amount of words in the FIFO when almost_full
-- is asserted (required)
-- use_bram : uses bram when true, uses LUTs/FFs when false (required)
-- same_cycle_output : output appears in same cycle as read when true, one
-- cycle later when false (required)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : clock input
-- rst : reset input (asynchronous)
-- rd : read input (active high)
-- wr : write input (active high)
-- empty : empty output (active high)
-- full : full output (active high)
-- almost_full : asserted when count >= almost_full_count (active high)
-- input : fifo input
-- output : fifo output
-------------------------------------------------------------------------------
entity fifo_core is
generic(width : positive;
depth : positive;
almost_full_count : natural;
use_bram : boolean;
same_cycle_output : boolean);
port(clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
almost_full : out std_logic;
count : out std_logic_vector(bitsNeeded(depth)-1 downto 0);
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end fifo_core;
-- FF architecture
-- This architecture implements the FIFO with flip-flops
architecture FF of fifo_core is
type reg_array is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal regs : reg_array;
signal count_r, next_count : unsigned(bitsNeeded(depth)-1 downto 0);
signal valid_wr : std_logic;
signal valid_rd : std_logic;
signal empty_s : std_logic;
signal full_s : std_logic;
begin
-- create a shift register to act as the fifo
-- always writes to register 0
process(clk, rst)
begin
if (rst = '1') then
-- initialize all registers to 0 (unnessary, useful for debugging)
for i in 0 to depth-1 loop
regs(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
-- shift in input everytime there is a valid write
if (valid_wr = '1') then
regs(0) <= input;
for i in 0 to depth-2 loop
regs(i+1) <= regs(i);
end loop;
end if;
end if;
end process;
-- assign the 1-cycle delayed output if applicable
U_OUTPUT_NEXT_CYCLE : if same_cycle_output = false generate
process(clk, rst)
begin
if (rst = '1') then
output <= (others => '0');
elsif(rising_edge(clk)) then
-- count-1 is the front of the fifo
if (count_r = 0) then
-- special case when fifo is empty. One alternative is to
-- increase the fifo depth to be a power of two,
-- in which case this isn't necessary.
output <= regs(0);
else
output <= regs(to_integer(count_r-1));
end if;
end if;
end process;
end generate;
-- assign the output in the same cycle if applicable
U_OUTPUT_SAME_CYCLE : if same_cycle_output = true generate
process(regs, count_r)
begin
-- count_r-1 is the front of the fifo
if (count_r = 0) then
-- special case when fifo is empty. One alternative is to
-- require the fifo depth to be a power of two,
-- in which case this isn't necessary.
output <= regs(0);
else
output <= regs(to_integer(count_r-1));
end if;
end process;
end generate;
-- update empty flag
empty_s <= '1' when count_r = 0 else '0';
empty <= empty_s;
-- update full flag
--full_s <= '0' when rd = '1' else
-- '1' when count_r = depth else '0';
full_s <= '1' when count_r = depth else '0';
full <= full_s;
-- update almost full flag
--almost_full <= '1' when count_r >= depth-almost_full_space else '0';
almost_full <= '1' when count_r >= almost_full_count else '0';
-- determine valid write and read
valid_wr <= wr and not full_s;
valid_rd <= rd and not empty_s;
-- update count_r based on read and write signals
process(valid_rd, valid_wr, count_r)
variable count_v : unsigned(bitsNeeded(depth)-1 downto 0);
begin
count_v := count_r;
if (valid_rd = '1' and valid_wr = '0') then
count_v := count_v - 1;
elsif (valid_rd = '0' and valid_wr = '1') then
count_v := count_v + 1;
end if;
next_count <= count_v;
end process;
-- create count register
process(clk, rst)
begin
if (rst = '1') then
count_r <= to_unsigned(0, count_r'length);
elsif (rising_edge(clk)) then
count_r <= next_count;
end if;
end process;
count <= std_logic_vector(count_r);
end FF;
architecture MEMORY of fifo_core is
signal rd_addr : unsigned(bitsNeeded(depth-1)-1 downto 0);
signal rd_addr_adjusted : unsigned(bitsNeeded(depth-1)-1 downto 0);
signal wr_addr : unsigned(bitsNeeded(depth-1)-1 downto 0);
signal ram_out : std_logic_vector(width-1 downto 0);
signal valid_wr : std_logic;
signal valid_rd : std_logic;
signal empty_s : std_logic;
signal full_s : std_logic;
signal count_r, next_count : unsigned(bitsNeeded(depth)-1 downto 0);
begin
-- implement FIFO using BRAM
BRAM : if use_bram = true generate
SAME_CYCLE : if same_cycle_output = true generate
-- adjust the rd address to account for the one cycle delay in the
-- block ram. This ensures that the correct output remains until
-- the the next read. When a read does occur, this reads the next
-- location in memory to ensure that data is available on the next
-- cycle.
rd_addr_adjusted <= rd_addr when valid_rd = '0' else rd_addr+1;
-- use RAM with synchronous read during write. This is necessary to
-- ensure that an output is available 1 cycle after a write, which
-- is the same time that the empty flag is cleared.
U_RAM : entity work.ram(SYNC_READ_DURING_WRITE)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- avoid warning about unused signal
output <= ram_out;
end generate SAME_CYCLE;
NOT_SAME_CYCLE : if same_cycle_output = false generate
-- avoids warning about unused signal for these generics
rd_addr_adjusted <= rd_addr;
-- use RAM with synchronous reads
U_RAM : entity work.ram(SYNC_READ)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- avoid warning about unused signal
output <= ram_out;
end generate NOT_SAME_CYCLE;
end generate BRAM;
-- implement FIFO using distributed RAM, LUTs, or any RAM that supports
-- asynchronous reads
-- synthesis tools might convert this to another resource if FPGA memory
-- does not support asynchronous reads
DIST_RAM : if use_bram = false generate
SAME_CYCLE : if same_cycle_output = true generate
-- avoids warning about unused signal for these generics
rd_addr_adjusted <= rd_addr;
-- use RAM with asynchronous reads (not supported by all FPGAs)
U_RAM : entity work.ram(ASYNC_READ)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- avoids warning about unused signal for these generics
output <= ram_out;
end generate SAME_CYCLE;
NOT_SAME_CYCLE : if same_cycle_output = false generate
-- avoids warning about unused signal for these generics
rd_addr_adjusted <= rd_addr;
-- use RAM with asynchronous reads (not supported by all FPGAs)
U_RAM : entity work.ram(ASYNC_READ)
generic map (
word_width => width,
addr_width => bitsNeeded(depth-1),
num_words => 2**bitsNeeded(depth-1))
port map (
clk => clk,
wen => valid_wr,
waddr => std_logic_vector(wr_addr),
wdata => input,
raddr => std_logic_vector(rd_addr_adjusted),
rdata => ram_out);
-- add a register to delay the output by a cycle
process(clk, rst)
begin
if (rst = '1') then
output <= (others => '0');
elsif (rising_edge(clk)) then
output <= ram_out;
end if;
end process;
end generate NOT_SAME_CYCLE;
end generate DIST_RAM;
-- update empty flag
--empty_s <= '1' when wr_addr = rd_addr else '0';
empty_s <= '1' when count_r = 0 else '0';
empty <= empty_s;
-- update full flag
--full_s <= '0' when rd = '1' else
-- '1' when wr_addr + 1 = rd_addr else '0';
full_s <= '1' when count_r = depth else '0';
full <= full_s;
-- update almost_full flag
almost_full <= '1' when count_r >= almost_full_count else '0';
-- determine valid write and read
valid_wr <= wr and not full_s;
valid_rd <= rd and not empty_s;
-- update wr and rd addresses
process(clk, rst)
begin
if (rst = '1') then
wr_addr <= (others => '0');
rd_addr <= (others => '0');
elsif rising_edge(clk) then
if (valid_rd = '1') then
rd_addr <= rd_addr + 1;
end if;
if (valid_wr = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
-- update count_r based on read and write signals
process(valid_rd, valid_wr, count_r)
variable count_v : unsigned(bitsNeeded(depth)-1 downto 0);
begin
count_v := count_r;
if (valid_rd = '1' and valid_wr = '0') then
count_v := count_v - 1;
elsif (valid_rd = '0' and valid_wr = '1') then
count_v := count_v + 1;
end if;
next_count <= count_v;
end process;
-- create count register
process(clk, rst)
begin
if (rst = '1') then
count_r <= to_unsigned(0, count_r'length);
elsif (rising_edge(clk)) then
count_r <= next_count;
end if;
end process;
count <= std_logic_vector(count_r);
end MEMORY;
|
gpl-3.0
|
b1c60db3f076d8315d581d94e54bc614
| 0.512678 | 4.23724 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/fifo_generator_v9_3/simulation/fifo_generator_v9_3_rng.vhd
| 1 | 3,920 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fifo_generator_v9_3_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fifo_generator_v9_3_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
apache-2.0
|
7460c126f863f5217546f6def482abc9
| 0.638776 | 4.317181 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/simulation/addr_gen.vhd
| 4 | 4,307 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: addr_gen.vhd
--
-- Description:
-- Address Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ADDR_GEN IS
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0')
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
LOAD :IN STD_LOGIC;
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
);
END ADDR_GEN;
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
BEGIN
ADDR_OUT <= ADDR_TEMP;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
ADDR_TEMP<= RST_VALUE;
ELSE
IF(EN='1') THEN
IF(LOAD='1') THEN
ADDR_TEMP <=LOAD_VALUE;
ELSE
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
ADDR_TEMP<= (OTHERS =>'0');
ELSE
ADDR_TEMP <= ADDR_TEMP + '1';
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-2.0
|
81d0672ad9f34e1bfdefcf82d3a20cce
| 0.577664 | 4.64617 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_add.vhd
| 3 | 7,087 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are add $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421020_00421020_00421020_00421020", -- Loc 0C, 08, 04, 00
X"00421020_00421020_00421020_00421020", -- Loc 1C, 18, 14, 10
X"00421020_00421020_00421020_00421020", -- Loc 2C, 28, 24, 20
X"00421020_00421020_00421020_00421020", -- Loc 3C, 38, 34, 30
X"00421020_00421020_00421020_00421020", -- Loc 4C, 48, 44, 40
X"00421020_00421020_00421020_00421020", -- Loc 5C, 58, 54, 50
X"00421020_00421020_00421020_00421020", -- Loc 6C, 68, 64, 60
X"00421020_00421020_00421020_00421020", -- Loc 7C, 78, 74, 70
X"00421020_00421020_00421020_00421020", -- Loc 8C, 88, 84, 80
X"00421020_00421020_00421020_00421020", -- Loc 9C, 98, 94, 90
X"00421020_00421020_00421020_00421020", -- Loc AC, A8, A4, A0
X"00421020_00421020_00421020_00421020", -- Loc BC, B8, B4, B0
X"00421020_00421020_00421020_00421020", -- Loc CC, C8, C4, C0
X"00421020_00421020_00421020_00421020", -- Loc DC, D8, D4, D0
X"00421020_00421020_00421020_00421020", -- Loc EC, E8, E4, E0
X"00421020_00421020_00421020_00421020", -- Loc FC, F8, F4, F0
X"00421020_00421020_00421020_00421020", -- Loc 10C, 108, 104, 100
X"00421020_00421020_00421020_00421020", -- Loc 11C, 118, 114, 110
X"00421020_00421020_00421020_00421020", -- Loc 12C, 128, 124, 120
X"00421020_00421020_00421020_00421020", -- Loc 13C, 138, 134, 130
X"00421020_00421020_00421020_00421020", -- Loc 14C, 148, 144, 140
X"00421020_00421020_00421020_00421020", -- Loc 15C, 158, 154, 150
X"00421020_00421020_00421020_00421020", -- Loc 16C, 168, 164, 160
X"00421020_00421020_00421020_00421020", -- Loc 17C, 178, 174, 170
X"00421020_00421020_00421020_00421020", -- Loc 18C, 188, 184, 180
X"00421020_00421020_00421020_00421020", -- Loc 19C, 198, 194, 190
X"00421020_00421020_00421020_00421020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421020_00421020_00421020_00421020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421020_00421020_00421020_00421020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421020_00421020_00421020_00421020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421020_00421020_00421020_00421020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421020_00421020_00421020_00421020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421020_00421020_00421020_00421020", -- Loc 20C, 208, 204, 200
X"00421020_00421020_00421020_00421020", -- Loc 21C, 218, 214, 221
X"00421020_00421020_00421020_00421020", -- Loc 22C, 228, 224, 220
X"00421020_00421020_00421020_00421020", -- Loc 23C, 238, 234, 230
X"00421020_00421020_00421020_00421020", -- Loc 24C, 248, 244, 240
X"00421020_00421020_00421020_00421020", -- Loc 25C, 258, 254, 250
X"00421020_00421020_00421020_00421020", -- Loc 26C, 268, 264, 260
X"00421020_00421020_00421020_00421020", -- Loc 27C, 278, 274, 270
X"00421020_00421020_00421020_00421020", -- Loc 28C, 288, 284, 280
X"00421020_00421020_00421020_00421020", -- Loc 29C, 298, 294, 290
X"00421020_00421020_00421020_00421020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421020_00421020_00421020_00421020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421020_00421020_00421020_00421020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421020_00421020_00421020_00421020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421020_00421020_00421020_00421020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421020_00421020_00421020_00421020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421020_00421020_00421020_00421020", -- Loc 30C, 308, 304, 300
X"00421020_00421020_00421020_00421020", -- Loc 31C, 318, 314, 331
X"00421020_00421020_00421020_00421020", -- Loc 32C, 328, 324, 320
X"00421020_00421020_00421020_00421020", -- Loc 33C, 338, 334, 330
X"00421020_00421020_00421020_00421020", -- Loc 34C, 348, 344, 340
X"00421020_00421020_00421020_00421020", -- Loc 35C, 358, 354, 350
X"00421020_00421020_00421020_00421020", -- Loc 36C, 368, 364, 360
X"00421020_00421020_00421020_00421020", -- Loc 37C, 378, 374, 370
X"00421020_00421020_00421020_00421020", -- Loc 38C, 388, 384, 380
X"00421020_00421020_00421020_00421020", -- Loc 39C, 398, 394, 390
X"00421020_00421020_00421020_00421020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421020_00421020_00421020_00421020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
gpl-2.0
|
3be8737218ddcb3f6ed11f2d38813935
| 0.638634 | 3.208239 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/fifo_generator_v9_3/example_design/fifo_generator_v9_3_exdes.vhd
| 1 | 5,140 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_generator_v9_3_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(25-1 DOWNTO 0);
DOUT : OUT std_logic_vector(25-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_generator_v9_3_exdes;
architecture xilinx of fifo_generator_v9_3_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component fifo_generator_v9_3 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(25-1 DOWNTO 0);
DOUT : OUT std_logic_vector(25-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : fifo_generator_v9_3
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
apache-2.0
|
0e49409214d2f7fa3c1930e3e5ede2a2
| 0.522763 | 4.741697 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/ssd_command_fifo/simulation/fg_tb_synth.vhd
| 2 | 10,029 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 6,
C_RD_PNTR_WIDTH => 6,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : ssd_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
46f10ec838ac35b5bbd3946aecb1930e
| 0.458869 | 4.170062 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/simulation/fg_tb_synth.vhd
| 1 | 11,231 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : RD_DATA_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
1b3f6fa201d1a88ab5fcd576d6593194
| 0.456059 | 3.964349 | false | false | false | false |
csrhau/sandpit
|
VHDL/fifo/test_fifo.vhdl
| 1 | 7,721 |
library ieee;
use ieee.std_logic_1164.all;
entity test_fifo is
end test_fifo;
architecture behavioural of test_fifo is
component FIFO is
generic (
addr_bits: natural
);
port (
clock : in std_logic;
push : in std_logic; -- Enable data write
pop : in std_logic; -- Enable data read if possible (push takes priority)
input : in std_logic_vector(7 downto 0); -- Data in
output : out std_logic_vector(7 downto 0); -- Data out
full : out std_logic;
empty : out std_logic
);
end component FIFO;
signal clock: std_logic;
signal push : std_logic := '0';
signal pop : std_logic := '0';
signal input : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
signal full : std_logic;
signal empty : std_logic;
procedure CYCLE(signal clock: out std_logic) is
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
end procedure;
procedure PUSH_IMPL(value : in std_logic_vector(7 downto 0);
signal clock : out std_logic;
signal push : out std_logic;
signal pop : out std_logic;
signal fifo_input : out std_logic_vector(7 downto 0)) is
begin
push <= '1';
pop <= '0';
fifo_input <= value;
CYCLE(clock);
end procedure;
procedure POP_IMPL(signal clock: out std_logic;
signal push: out std_logic;
signal pop : out std_logic) is
begin
push <= '0';
pop <= '1';
CYCLE(clock);
end procedure;
begin
queue : FIFO generic map(addr_bits => 3) -- fifo with 8 elements
port map (clock, push, pop, input, output, full, empty);
process
-- Helper macros
-- PUSH wrapper
procedure PUSH_MACRO(value: in std_logic_vector(7 downto 0)) is
begin
PUSH_IMPL(value, clock, push, pop, input);
end procedure;
-- POP wrapper
procedure POP_MACRO(value: out std_logic_vector(7 downto 0)) is
begin
POP_IMPL(clock, push, pop);
value := output;
end procedure;
variable retval : std_logic_vector(7 downto 0);
begin
wait for 1 ns;
assert full = '0'
report "Fresh queue should not be full"
severity error;
assert empty = '1'
report "Fresh queue should be empty"
severity error;
PUSH_MACRO("10101010");
assert full = '0'
report "1 element queue should not be full" severity error;
assert empty = '0'
report "1 element queue should not be empty" severity error;
for i in 1 to 6 loop
CYCLE(clock);
assert full = '0'
report "queue should not be full" severity error;
assert empty = '0'
report "queue should not be empty" severity error;
end loop;
CYCLE(clock);
assert full = '1'
report "8 element queue should be full" severity error;
assert empty = '0'
report "8 element queue should not be empty" severity error;
-- Ensure queue maintains size
push <= '0';
pop <= '0';
CYCLE(clock);
assert full = '1'
report "8 element queue should be full" severity error;
assert empty = '0'
report "8 element queue should not be empty" severity error;
-- Drain queue
for i in 1 to 7 loop
POP_MACRO(retval);
assert full = '0'
report "draining queue should not be full" severity error;
assert empty = '0'
report "draining queue should not be empty" severity error;
end loop;
POP_MACRO(retval);
assert full = '0'
report "Empty queue should not be full" severity error;
assert empty = '1'
report "Empty queue should be empty" severity error;
-- Ensure queue maintains size
push <= '0';
pop <= '0';
CYCLE(clock);
assert full = '0'
report "Empty queue should not be full" severity error;
assert empty = '1'
report "Empty queue should be empty" severity error;
PUSH_MACRO("00001111");
POP_MACRO(retval);
assert retval = "00001111"
report "Returned value should match pushed value" severity error;
PUSH_MACRO("00000001");
PUSH_MACRO("00000010");
PUSH_MACRO("00000100");
PUSH_MACRO("00001000");
POP_MACRO(retval);
assert retval = "00000001"
report "FIFO Queue should maintain FIFO ordering" severity error;
POP_MACRO(retval);
assert retval = "00000010"
report "FIFO Queue should maintain FIFO ordering" severity error;
POP_MACRO(retval);
assert retval = "00000100"
report "FIFO Queue should maintain FIFO ordering" severity error;
POP_MACRO(retval);
assert retval = "00001000"
report "FIFO Queue should maintain FIFO ordering" severity error;
assert empty = '1'
report "Queue should be empty here" severity error;
PUSH_MACRO("00000001"); -- 1
PUSH_MACRO("00000010"); -- 2
PUSH_MACRO("00000100"); -- 3
PUSH_MACRO("00001000"); -- 4
PUSH_MACRO("00010000"); -- 5
PUSH_MACRO("00100000"); -- 6
PUSH_MACRO("01000000"); -- 7
PUSH_MACRO("10000000"); -- 8
assert full = '1'
report "Queue should be full here"
severity error;
PUSH_MACRO("11111111"); -- Overflow
PUSH_MACRO("11111111"); -- Overflow
assert full = '1'
report "Queue should be full after overflow"
severity error;
POP_MACRO(retval);
assert retval = "00000001"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00000010"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00000100"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00001000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00010000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "00100000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "01000000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
POP_MACRO(retval);
assert retval = "10000000"
report "FIFO Queue should maintain FIFO ordering in the presence of overflow"
severity error;
assert empty = '1'
report "Queue should be fully drained here"
severity error;
POP_MACRO(retval);
assert retval = "10000000" -- Just keeps repeating last read value
report "FIFO Queue should have dropped the overflow values"
severity error;
assert empty = '1'
report "Queue should remain fully drained after over-emptying"
severity error;
assert full = '0'
report "Queue should remain fully drained after over-emptying"
severity error;
PUSH_MACRO("11110000");
assert empty = '0'
report "Queue should work correctly after over-emptying"
severity error;
assert full = '0'
report "Queue should work correctly after over-emptying"
severity error;
POP_MACRO(retval);
assert retval = "11110000";
assert empty = '1'
report "Queue should become fully drained here"
severity error;
assert full = '0'
report "Queue should become fully drained here"
severity error;
wait;
end process;
end behavioural;
|
mit
|
b0f7ec208d9db6314d5ddba5894a225c
| 0.628027 | 4.196196 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_mul.vhd
| 3 | 7,087 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are mul $2 $2 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"00421019_00421019_00421019_00421019", -- Loc 0C, 08, 04, 00
X"00421019_00421019_00421019_00421019", -- Loc 1C, 18, 14, 10
X"00421019_00421019_00421019_00421019", -- Loc 2C, 28, 24, 20
X"00421019_00421019_00421019_00421019", -- Loc 3C, 38, 34, 30
X"00421019_00421019_00421019_00421019", -- Loc 4C, 48, 44, 40
X"00421019_00421019_00421019_00421019", -- Loc 5C, 58, 54, 50
X"00421019_00421019_00421019_00421019", -- Loc 6C, 68, 64, 60
X"00421019_00421019_00421019_00421019", -- Loc 7C, 78, 74, 70
X"00421019_00421019_00421019_00421019", -- Loc 8C, 88, 84, 80
X"00421019_00421019_00421019_00421019", -- Loc 9C, 98, 94, 90
X"00421019_00421019_00421019_00421019", -- Loc AC, A8, A4, A0
X"00421019_00421019_00421019_00421019", -- Loc BC, B8, B4, B0
X"00421019_00421019_00421019_00421019", -- Loc CC, C8, C4, C0
X"00421019_00421019_00421019_00421019", -- Loc DC, D8, D4, D0
X"00421019_00421019_00421019_00421019", -- Loc EC, E8, E4, E0
X"00421019_00421019_00421019_00421019", -- Loc FC, F8, F4, F0
X"00421019_00421019_00421019_00421019", -- Loc 10C, 108, 104, 100
X"00421019_00421019_00421019_00421019", -- Loc 11C, 118, 114, 110
X"00421019_00421019_00421019_00421019", -- Loc 12C, 128, 124, 120
X"00421019_00421019_00421019_00421019", -- Loc 13C, 138, 134, 130
X"00421019_00421019_00421019_00421019", -- Loc 14C, 148, 144, 140
X"00421019_00421019_00421019_00421019", -- Loc 15C, 158, 154, 150
X"00421019_00421019_00421019_00421019", -- Loc 16C, 168, 164, 160
X"00421019_00421019_00421019_00421019", -- Loc 17C, 178, 174, 170
X"00421019_00421019_00421019_00421019", -- Loc 18C, 188, 184, 180
X"00421019_00421019_00421019_00421019", -- Loc 19C, 198, 194, 190
X"00421019_00421019_00421019_00421019", -- Loc 1AC, 1A8, 1A4, 1A0
X"00421019_00421019_00421019_00421019", -- Loc 1BC, 1B8, 1B4, 1B0
X"00421019_00421019_00421019_00421019", -- Loc 1CC, 1C8, 1C4, 1C0
X"00421019_00421019_00421019_00421019", -- Loc 1DC, 1D8, 1D4, 1D0
X"00421019_00421019_00421019_00421019", -- Loc 1EC, 1E8, 1E4, 1E0
X"00421019_00421019_00421019_00421019", -- Loc 1FC, 1F8, 1F4, 1F0
X"00421019_00421019_00421019_00421019", -- Loc 20C, 208, 204, 200
X"00421019_00421019_00421019_00421019", -- Loc 21C, 218, 214, 221
X"00421019_00421019_00421019_00421019", -- Loc 22C, 228, 224, 220
X"00421019_00421019_00421019_00421019", -- Loc 23C, 238, 234, 230
X"00421019_00421019_00421019_00421019", -- Loc 24C, 248, 244, 240
X"00421019_00421019_00421019_00421019", -- Loc 25C, 258, 254, 250
X"00421019_00421019_00421019_00421019", -- Loc 26C, 268, 264, 260
X"00421019_00421019_00421019_00421019", -- Loc 27C, 278, 274, 270
X"00421019_00421019_00421019_00421019", -- Loc 28C, 288, 284, 280
X"00421019_00421019_00421019_00421019", -- Loc 29C, 298, 294, 290
X"00421019_00421019_00421019_00421019", -- Loc 2AC, 2A8, 2A4, 2A0
X"00421019_00421019_00421019_00421019", -- Loc 2BC, 2B8, 2B4, 2B0
X"00421019_00421019_00421019_00421019", -- Loc 2CC, 2C8, 2C4, 2C0
X"00421019_00421019_00421019_00421019", -- Loc 2DC, 2D8, 2D4, 2D0
X"00421019_00421019_00421019_00421019", -- Loc 2EC, 2E8, 2E4, 2E0
X"00421019_00421019_00421019_00421019", -- Loc 2FC, 2F8, 2F4, 2F0
X"00421019_00421019_00421019_00421019", -- Loc 30C, 308, 304, 300
X"00421019_00421019_00421019_00421019", -- Loc 31C, 318, 314, 331
X"00421019_00421019_00421019_00421019", -- Loc 32C, 328, 324, 320
X"00421019_00421019_00421019_00421019", -- Loc 33C, 338, 334, 330
X"00421019_00421019_00421019_00421019", -- Loc 34C, 348, 344, 340
X"00421019_00421019_00421019_00421019", -- Loc 35C, 358, 354, 350
X"00421019_00421019_00421019_00421019", -- Loc 36C, 368, 364, 360
X"00421019_00421019_00421019_00421019", -- Loc 37C, 378, 374, 370
X"00421019_00421019_00421019_00421019", -- Loc 38C, 388, 384, 380
X"00421019_00421019_00421019_00421019", -- Loc 39C, 398, 394, 390
X"00421019_00421019_00421019_00421019", -- Loc 3AC, 3A8, 3A4, 3A0
X"00421019_00421019_00421019_00421019", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
gpl-2.0
|
578821be903596a6dd3d6285ebb0ce79
| 0.638634 | 3.208239 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/simulation/bmg_tb_top.vhd
| 2 | 4,389 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_top.vhd
--
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY BMG_TB_TOP IS
END ENTITY;
ARCHITECTURE BMG_TB_TOP_ARCH OF BMG_TB_TOP IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Simulation Complete"
SEVERITY FAILURE;
END IF;
END PROCESS;
BMG_TB_INST:ENTITY work.BMG_TB
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
gpl-2.0
|
995abb3d2793412b5a485ae7aa695799
| 0.611757 | 4.557632 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/fifo_generator_v9_3/simulation/fifo_generator_v9_3_pctrl.vhd
| 1 | 18,343 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_generator_v9_3_pkg.ALL;
ENTITY fifo_generator_v9_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fifo_generator_v9_3_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
apache-2.0
|
ff763124851d8e3a76c575848c41964c
| 0.509949 | 3.244252 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/rs232_reciever.vhd
| 1 | 3,177 |
-- RS232 receiver with Wishbone master interface and fixed, but generic,
-- baudrate and 8N1 mode.
--
-- This master sets stb_o to 1, after one byte was received and before the
-- stop is received. When the slave acknowledges the strobe with ack_i = 1,
-- stb_o is reset to 0.
--
-- Supported Whishbone cycles: MASTER, WRITE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity rs232_receiver is
generic(system_speed, baudrate: integer);
port(
ack_i: in std_logic;
clk_i: in std_logic;
dat_o: out unsigned(7 downto 0);
rst_i: in std_logic;
stb_o: out std_logic;
rx: in std_logic);
end entity rs232_receiver;
architecture rtl of rs232_receiver is
constant max_counter: natural := system_speed / baudrate;
type state_type is (
wait_for_rx_start,
wait_half_bit,
receive_bits,
wait_for_stop_bit);
signal state: state_type := wait_for_rx_start;
signal baudrate_counter: natural range 0 to max_counter := 0;
signal bit_counter: natural range 0 to 7 := 0;
signal shift_register: unsigned(7 downto 0) := (others => '0');
begin
update: process(clk_i, ack_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
state <= wait_for_rx_start;
dat_o <= (others => '0');
stb_o <= '0';
else
case state is
when wait_for_rx_start =>
if rx = '0' then
-- start bit received, wait for a half bit time
-- to sample bits in the middle of the signal
state <= wait_half_bit;
baudrate_counter <= max_counter / 2 - 1;
end if;
when wait_half_bit =>
if baudrate_counter = 0 then
-- now we are in the middle of the start bit,
-- wait a full bit for the middle of the first bit
state <= receive_bits;
bit_counter <= 7;
baudrate_counter <= max_counter - 1;
else
baudrate_counter <= baudrate_counter - 1;
end if;
when receive_bits =>
-- sample a bit
if baudrate_counter = 0 then
shift_register <= rx & shift_register(7 downto 1);
if bit_counter = 0 then
state <= wait_for_stop_bit;
else
bit_counter <= bit_counter - 1;
end if;
baudrate_counter <= max_counter - 1;
else
baudrate_counter <= baudrate_counter - 1;
end if;
when wait_for_stop_bit =>
-- wait for the middle of the stop bit
if baudrate_counter = 0 then
state <= wait_for_rx_start;
if rx = '1' then
dat_o <= shift_register;
stb_o <= '1';
-- else: missing stop bit, ignore
end if;
else
baudrate_counter <= baudrate_counter - 1;
end if;
end case;
end if;
end if;
-- when acknowledged, reset strobe
if ack_i = '1' then
stb_o <= '0';
end if;
end process;
end architecture rtl;
|
mit
|
4c19cac90a70b9fdceb0e41da5503764
| 0.543595 | 3.931931 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_PRE_FIFO/simulation/fg_tb_top.vhd
| 2 | 6,021 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 84
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
d18f78e239c4ac64f5f3dbd7e4c7852a
| 0.612025 | 4.095918 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/dispatch_xtend_BRAM.vhd
| 2 | 38,983 |
-------------------------------------------------------------------------------
--
-- Design : Dispatch Unit
-- Project : Tomasulo Processor
-- Entity : dispatch_unit
-- Author : Manpreet Billing
-- Company : University of Southern California
-- Last Updated : March 2, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity dispatch_unit is
port(
Clk : in std_logic ;
Resetb : in std_logic ;
-- Interface with Intsruction Fetch Queue
Ifetch_Instruction : in std_logic_vector(31 downto 0); -- instruction from IFQ
Ifetch_PcPlusFour : in std_logic_vector(31 downto 0); -- the PC+4 value carried forward for jumping and branching
Ifetch_EmptyFlag : in std_logic; -- signal showing that the ifq is empty,hence stopping any decoding and dispatch of the current if_inst
Dis_Ren : out std_logic; -- stalling caused due to issue queue being full
Dis_JmpBrAddr : out std_logic_vector(31 downto 0); -- the jump or branch address
Dis_JmpBr : out std_logic; -- validating that address to cause a jump or branch
Dis_JmpBrAddrValid : out std_logic; -- to tell if the jump or branch address is valid or not.. will be invalid for "jr $rs" inst
-------------------------------------------------------------------------
-- Interface with branch prediction buffer
Dis_CdbUpdBranch : out std_logic; -- indicates that a branch is processed by the cdb and gives the pred(wen to bpb)
Dis_CdbUpdBranchAddr : out std_logic_vector(2 downto 0);-- indiactes the least significant 3 bit PC[4:2] of the branch beign processed by cdb
Dis_CdbBranchOutcome : out std_logic; -- indiacates the outocome of the branch to the bpb
Bpb_BranchPrediction : in std_logic; -- this bit tells the dispatch what is the prediction based on bpb state-mc
Dis_BpbBranchPCBits : out std_logic_vector(2 downto 0);-- indiaces the 3 least sig bits of the PC value of the current instr being dis (PC[4:2])
Dis_BpbBranch : out std_logic; -- indiactes a branch instr (ren to the bpb)
--------------------------------------------------------------------------------
-- interface with the cdb
Cdb_Branch : in std_logic;
Cdb_BranchOutcome : in std_logic;
Cdb_BranchAddr : in std_logic_vector(31 downto 0);
Cdb_BrUpdtAddr : in std_logic_vector(2 downto 0);
Cdb_Flush : in std_logic;
Cdb_RobTag : in std_logic_vector(4 downto 0);
------------------------------------------------------------------------------
-- interface with checkpoint module (CFC)
Dis_CfcRsAddr : out std_logic_vector(4 downto 0); -- indicates the Rs Address to be read from Reg file
Dis_CfcRtAddr : out std_logic_vector(4 downto 0); -- indicates the Rt Address to be read from Reg file
Dis_CfcRdAddr : out std_logic_vector(4 downto 0); -- indicates the Rd Address to be written by instruction
-- goes to Dis_CfcRdAddr of ROB too
Cfc_RsPhyAddr : in std_logic_vector(5 downto 0); -- Rs Physical register Tag corresponding to Rs Addr
Cfc_RtPhyAddr : in std_logic_vector(5 downto 0); -- Rt Physical register Tag corresponding to Rt Addr
Cfc_RdPhyAddr : in std_logic_vector(5 downto 0); -- Rd Old Physical register Tag corresponding to Rd Addr
Cfc_Full : in std_logic ; -- indicates that all RATs are used and hence we stall in case of branch or Jr $31
Dis_CfcBranchTag : out std_logic_vector(4 downto 0) ; -- indicats the rob tag of the branch for which checkpoint is to be done
Dis_CfcRegWrite : out std_logic; -- indicates that the instruction in the dispatch is a register writing instruction and hence should update the active RAT with destination register tag.
Dis_CfcNewRdPhyAddr : out std_logic_vector(5 downto 0); -- indicates the new physical register to be assigned to Rd for the instruciton in first stage
Dis_CfcBranch : out std_logic; -- indicates if branch is there in first stage of dispatch... tells cfc to checkpoint
Dis_CfcInstValid : out std_logic;
--------------------------------------------------------------------------------
-- physical register interface
PhyReg_RsDataRdy : in std_logic ; -- indicating if the value of Rs is ready at the physical tag location
PhyReg_RtDataRdy : in std_logic ; -- indicating if the value of Rt is ready at the physical tag location
-- translate_off
Dis_Instruction : out std_logic_vector(31 downto 0);
-- translate_on
--------------------------------------------------------------------------------
-- interface with issue queues
Dis_RegWrite : out std_logic;
Dis_RsDataRdy : out std_logic; -- tells the queues that Rs value is ready in PRF and no need to snoop on CDB for that.
Dis_RtDataRdy : out std_logic; -- tells the queues that Rt value is ready in PRF and no need to snoop on CDB for that.
Dis_RsPhyAddr : out std_logic_vector(5 downto 0); -- tells the physical register mapped to Rs (as given by Cfc)
Dis_RtPhyAddr : out std_logic_vector(5 downto 0); -- tells the physical register mapped to Rt (as given by Cfc)
Dis_RobTag : out std_logic_vector(4 downto 0);
Dis_Opcode : out std_logic_vector(2 downto 0); -- gives the Opcode of the given instruction for ALU operation
Dis_IntIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_LdIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_DivIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_MulIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_Immediate : out std_logic_vector(15 downto 0); -- 15 bit immediate value for lw/sw address calculation and addi instruction
Issque_IntQueueFull : in std_logic;
Issque_LdStQueueFull : in std_logic;
Issque_DivQueueFull : in std_logic;
Issque_MulQueueFull : in std_logic;
Issque_IntQueTwoOrMoreVacant : in std_logic; -- indicates that 2 or more slots are available in integer queue
Issque_LdStQueTwoOrMoreVacant : in std_logic;
Issque_DivQueTwoOrMoreVacant : in std_logic;
Issque_MulQueTwoOrMoreVacant : in std_logic;
Dis_BranchOtherAddr : out std_logic_vector(31 downto 0); -- indicates 32 pins for carrying branch other address to be used incase of misprediction.
Dis_BranchPredict : out std_logic; -- indicates the prediction given by BPB for branch instruction
Dis_Branch : out std_logic;
Dis_BranchPCBits : out std_logic_vector(2 downto 0);
Dis_JrRsInst : out std_logic;
Dis_JalInst : out std_logic ; -- Indicating whether there is a call instruction
Dis_Jr31Inst : out std_logic;
----------------------------------------------------------------------------------
---- interface with the FRL---- accessed in first sage only so dont need NaerlyEmpty signal from Frl
Frl_RdPhyAddr : in std_logic_vector(5 downto 0); -- Physical tag for the next available free register
Dis_FrlRead : out std_logic ; -- indicating if free register given by FRL is used or not
Frl_Empty : in std_logic; -- indicates that there are no more free physical registers
----------------------------------------------------------------------------------
---- interface with the RAS
Dis_RasJalInst : out std_logic ; -- indicating whether there is a call instruction
Dis_RasJr31Inst : out std_logic;
Dis_PcPlusFour : out std_logic_vector(31 downto 0); -- represents the return address of Jal call instruction
Ras_Addr : in std_logic_vector(31 downto 0); -- popped RAS address from RAS
----------------------------------------------------------------------------------
---- interface with the rob
Dis_PrevPhyAddr : out std_logic_vector(5 downto 0); -- indicates old physical register mapped to Rd of the instruction
Dis_NewRdPhyAddr : out std_logic_vector(5 downto 0); -- indicates new physical register to be assigned to Rd (given by FRL)
Dis_RobRdAddr : out std_logic_vector(4 downto 0); -- indicates the Rd Address to be written by instruction -- send to Physical register file too.. so that he can make data ready bit "0"
Dis_InstValid : out std_logic ;
Dis_InstSw : out std_logic ;
Dis_SwRtPhyAddr : out std_logic_vector(5 downto 0); -- indicates physical register mapped to Rt of the Sw instruction
Rob_BottomPtr : in std_logic_vector(4 downto 0);
Rob_Full : in std_logic;
Rob_TwoOrMoreVacant : in std_logic
);
end dispatch_unit;
architecture behv of dispatch_unit is
signal Ifetch_Instruction_small :std_logic_vector(5 downto 0);
signal dispatch_rsaddr,dispatch_rtaddr,dispatch_rdaddr:std_logic_vector(4 downto 0);
signal sel_que_full ,sel_que_nearly_full: std_logic;
signal DisJal ,DisJr31 ,DisJrRs,RegWrite , jr_stall :std_logic ;
signal jr_rob_tag : std_logic_vector(4 downto 0);
signal StageReg_RdAddr ,Dis_CfcRdAddrTemp : std_logic_vector(4 downto 0);
signal IntIssquenable ,DivIssquenable,LdIssquenable,MulIssquenable , ren_var : std_logic ;
signal InstValid , InstSw ,Branch ,BranchPredict: std_logic ;
signal Opcode , BranchPCBits : std_logic_vector (2 downto 0);
signal ImmLdSt : std_logic_vector(15 downto 0);
signal StageReg_IntIssquenable ,StageReg_DivIssquenable,StageReg_LdIssquenable,StageReg_MulIssquenable : std_logic ;
signal StageReg_InstValid, StageReg_InstSw ,StageReg_Branch ,StageReg_RegWrite ,StageReg_BranchPredict: std_logic ;
signal StageReg_Opcode , StageReg_BranchPCBits : std_logic_vector (2 downto 0);
signal StageReg_ImmLdSt : std_logic_vector(15 downto 0);
signal StageReg_BranchOtherAddr , BranchOtherAddr: std_logic_vector(31 downto 0);
signal StageReg_JrRsInst ,StageReg_Jr31Inst,StageReg_JalInst : std_logic ;
signal StageReg_NewRdPhyAddr : std_logic_vector(5 downto 0);
signal StageReg_Instruction : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
--variable assignments---------------
Ifetch_Instruction_small <= Ifetch_Instruction(31 downto 26);
dispatch_rsaddr <=Ifetch_Instruction(25 downto 21);
dispatch_rtaddr <=Ifetch_Instruction(20 downto 16);
dispatch_rdaddr <=Ifetch_Instruction(15 downto 11);
---- process for interactions with IFETCH
ifetch_comm : process(Ifetch_Instruction,sel_que_full,Rob_Full,Ifetch_Instruction_small,
Cdb_Flush,Ifetch_PcPlusFour,Ifetch_EmptyFlag,Bpb_BranchPrediction,
Cdb_BranchAddr,DisJal,DisJr31,DisJrRs,RegWrite, sel_que_nearly_full,Rob_TwoOrMoreVacant,
StageReg_InstValid,StageReg_RegWrite, Cfc_Full , Branch,InstValid,
jr_stall, Frl_Empty, Cdb_RobTag, jr_rob_tag, Ras_Addr
)
variable branch_addr_sign_extended_var ,branch_target_addr:std_logic_vector(31 downto 0);
variable branch_addr_sign_extended_shifted_var :std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
-- Task1:
-- 1. Correct the sign-extension operation implemented in the if statement below
if (Ifetch_Instruction(15) = '1') then
branch_addr_sign_extended_var := X"FFFF" & Ifetch_Instruction(15 downto 0) ; -- This line is incorrect and you need to modify it
else
branch_addr_sign_extended_var := X"0000" & Ifetch_Instruction(15 downto 0) ; -- This line is incorrect and you need to modify it
end if ;
-- 2. Complete the branch target address calculation
branch_addr_sign_extended_shifted_var := branch_addr_sign_extended_var(29 downto 0)& "00";
branch_target_addr := branch_addr_sign_extended_shifted_var + Ifetch_PcPlusFour ; -- Complete this statement
-- End of Task1
----------------------------------------------------------
----------------------------------------------------------
-- Dis_Ren: In this process we generate the read enable signal of IFQ. When the 1st stage dispatch is stalled for one reason
-- or IFQ is empty then read enable should be 0 otherwise it going to be 1.
-- Dis_JmpBr: At the same time we generate the Dis_JmpBr signal. This signal is used to flush the IFQ and start fetching instruction
-- from other direction in any of the following cases: branch instr in dispatch predicted taken, jump instruction in dispatch,
-- Flush signal active due to misprediction, or Jr $rs instruction coming out of stall.
-- Dis_JmpBr has higher priority over Dis_Ren
-- NOTE : The two or more vacant slot condition of rob is checked with StageReg_InstValid to make sure that instruction in 2nd stage dispatch is a valid instruction
-- The same apply for Frl_empty which is checked with RegWrite signal to make sure that instruction in 1st stage dispatch is a register writing instruction
if ((sel_que_full= '1')or (sel_que_nearly_full = '1') or (Rob_Full= '1') or
(Rob_TwoOrMoreVacant = '0' and StageReg_InstValid = '1')or (Ifetch_EmptyFlag = '1') or
(jr_stall = '1') or (Frl_Empty = '1' and RegWrite = '1') or (Cfc_Full = '1' and (Branch = '1' or DisJr31 = '1'))) then
ren_var <= '0' ;
Dis_Ren<= '0';
else
ren_var <= '1' ;
Dis_Ren<= '1';
end if ;
-- Note : Bpb_BranchPrediction is "0" by default . It is "1" only if there is a branch instruction and the prediction is true in the prediction bit table
-- CONDITIONAL INSTRUCTIONS AND CDBFLUSH IS CHECKED HERE...
if ( (((Ifetch_Instruction_small= "000010") or (((DisJal = '1') or (DisJr31 = '1' or DisJrRs = '1')) and InstValid = '1')
or (Bpb_BranchPrediction = '1') )and Ifetch_EmptyFlag = '0') or (Cdb_Flush='1') or (jr_stall = '1' and Cdb_RobTag = jr_rob_tag))then -- confirm
Dis_JmpBr<= '1';
else
Dis_JmpBr<= '0';
end if ;
-- Dis_JmpBrAddrValid: Pin from dispatch to IFetch telling if JR addr is valid...
Dis_JmpBrAddrValid <= not (DisJrRs and InstValid) ; -- in ifetch this pin is checked along with disaptch_jm_br pin..
-- Thus keeping it "1" as default is harmless..But it should be "0" for "jr $rs" inst
----------------------------------------------------------
-- Task2: Complete the following piece of code to generate the next address from which you need to start fetching
-- incase Dis_JmpBr is set to 1.
-- Dis_JmpBrAddrValid
-- Note : Cdb has the responsibility of generating Cdb_Flush at mispredicted branches and mispredicted "jr $31" instructions
-- Have to jump when dispatch is waiting for jr $RS once it comes on Cdb
if (Cdb_Flush= '1' or (jr_stall = '1' and Cdb_RobTag = jr_rob_tag))then -- Cdb_Flush -- can't avoid as have to give priority to CDB flush over any conditional instruction in dispatch
Dis_JmpBrAddr<=Cdb_BranchAddr ;
else
-- have to give the default value to avoid latch
Dis_JmpBrAddr<=Cdb_BranchAddr ;
if ((Ifetch_Instruction_small = "000010") or (DisJal = '1')) then -- jump
Dis_JmpBrAddr <= Ifetch_PcPlusFour(31 downto 28) & branch_addr_sign_extended_shifted_var(27 downto 0); -- Complete this line
elsif (DisJr31 = '1') then -- JR $31 .. use address popped from RAS
Dis_JmpBrAddr <= Ras_Addr; -- Complete this line
elsif (Bpb_BranchPrediction = '1' ) then -- Branch predicted taken
Dis_JmpBrAddr <= branch_target_addr; -- Complete this line
end if ;
end if ;
-- End of Task2
----------------------------------------------------------
end process;
----------------------------------------------------------
-- selective_que_full Process:
-- This process is used to generate the sel_que_full signal which indicates if the desired instruction
-- issue queue is full or not. Basically, what we need to do is to investigate the opcode of the instruction
-- in the dispatch stage and then we check the full bit of the corresponding instr issue queue. If the
-- corresponding issue queue is full then we set the sel_que_full bit to '1' otherwise it is set to '0'.
selective_que_full:process(Ifetch_Instruction_small,Ifetch_Instruction,Issque_IntQueueFull,
Issque_DivQueueFull,Issque_MulQueueFull,Issque_LdStQueueFull )
begin
if ((( (Ifetch_Instruction_small="000000") and((Ifetch_Instruction(5 downto 0) = "100000") -- add
or (Ifetch_Instruction(5 downto 0) = "100010") or -- sub
(Ifetch_Instruction(5 downto 0) = "100100") or -- and
(Ifetch_Instruction(5 downto 0) = "100101") or --or
(Ifetch_Instruction(5 downto 0) = "101010"))) -- slt
or ( Ifetch_Instruction_small="001000" ) -- addi
or ( Ifetch_Instruction_small="000101" ) -- bne
or ( Ifetch_Instruction_small="000100" ) -- beq
or ( Ifetch_Instruction_small="000011" ) -- jal
or ( Ifetch_Instruction_small="000000" and (Ifetch_Instruction(5 downto 0) = "001000"))) -- jr
and Issque_IntQueueFull='1' -- jr
) then
sel_que_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011011") -- div
and (Issque_DivQueueFull='1')) then
sel_que_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011001") -- mul
and (Issque_MulQueueFull = '1' )) then
sel_que_full<='1';
elsif (((Ifetch_Instruction_small="100011") or (Ifetch_Instruction_small="101011")) -- load / store
and (Issque_LdStQueueFull = '1')) then
sel_que_full<='1';
else
sel_que_full<='0';
end if ;
end process;
----------------------------------------------------------
-- Task3: Complete the selective_que_nearly_full Process
-- This process is used to generate the sel_que_nearly_full signal which indicates if the desired instruction
-- issue queue has less than 2 vacancies ( 1 or 0) and the instruction in the 2nd dispatch stage is of the same
-- type.
-- Hint: This process is very similar to the selective_que_full process.
selective_que_nearly_full:process(Ifetch_Instruction_small,Ifetch_Instruction,Issque_IntQueTwoOrMoreVacant,
Issque_DivQueTwoOrMoreVacant,Issque_MulQueTwoOrMoreVacant,Issque_LdStQueTwoOrMoreVacant,
StageReg_IntIssquenable, StageReg_DivIssquenable, StageReg_MulIssquenable, StageReg_LdIssquenable -- Added by Vaibhav
)
begin
if ((( (Ifetch_Instruction_small="000000") and((Ifetch_Instruction(5 downto 0) = "100000") -- add
or (Ifetch_Instruction(5 downto 0) = "100010") or -- sub
(Ifetch_Instruction(5 downto 0) = "100100") or -- and
(Ifetch_Instruction(5 downto 0) = "100101") or --or
(Ifetch_Instruction(5 downto 0) = "101010"))) -- slt
or ( Ifetch_Instruction_small="001000" ) -- addi
or ( Ifetch_Instruction_small="000101" ) -- bne
or ( Ifetch_Instruction_small="000100" ) -- beq
or ( Ifetch_Instruction_small="000011" ) -- jal
or ( Ifetch_Instruction_small="000000" and (Ifetch_Instruction(5 downto 0) = "001000"))) -- jr
and Issque_IntQueTwoOrMoreVacant='0'
and Issque_IntQueueFull='0'
) then
sel_que_nearly_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011011") -- div
and (Issque_DivQueTwoOrMoreVacant='0')
and Issque_DivQueueFull='0') then
sel_que_nearly_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011001") -- mul
and (Issque_MulQueTwoOrMoreVacant = '0' )
and Issque_MulQueueFull='0') then
sel_que_nearly_full<='1';
elsif (((Ifetch_Instruction_small="100011") or (Ifetch_Instruction_small="101011")) -- load / store
and (Issque_LdStQueTwoOrMoreVacant = '0')
and Issque_LdStQueueFull='0') then
sel_que_nearly_full<='1';
else
sel_que_nearly_full<='0';
end if ;
end process;
-- End of Task3
----------------------------------------------------------
----------------------------------------------------------
-- make_rob_entry Process:
-- The name of the process may cause some confusion. In this process we generate 3 signals:
-- 1. InstValid signal: This signal indicates if the instruction in the 1st stage dispatch is valid or not. Invalid instructions
-- include the following:
-- if the flush signal is active then the instruction in dispatch is flushed
-- if the instruction is a jump instruction which executes in dispatch and then vanishes.
-- JR $rs: This is a special case, since we stall the pipeline until JR $rs completes and it appears on Cdb. In
-- we need an RobTag to identify when the instruction comes on Cdb but no Rob entry is needed as the instr
-- vanishes after the Cdb and does not enter ROB.
-- For Invalid instructions we don't need to assign an ROB entry for that instruction.
make_rob_entry: process(Cdb_Flush, ren_var,dispatch_rsaddr, dispatch_rtaddr , dispatch_rdaddr , Ifetch_Instruction_Small,Ifetch_Instruction)
begin
if ( (ren_var = '0') or (Cdb_Flush ='1') or (Ifetch_Instruction_small="000010")or
((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "001000") and (dispatch_rsaddr /= "11111")) )then
InstValid<='0';
else
InstValid<='1';
end if;
-- 2. InstSw signal: This signal indicates if the instruction in the 1st stage dispatch is a SW instruction.
if (Ifetch_Instruction_small="101011") then -- store word
InstSw <='1';
else
InstSw <='0';
end if ;
-- 3. Dis_CfcRdAddrTemp: This signal holds the Rd address of the instruction in dispatch
----------------------------------------------------------
-- Task4: Write an if-statement to generate Dis_CfcRdAddrTemp
-- Hint: R-type instructions use $rd field, lw and addi use $rt as destination, jal uses $31 as destination.
if (Ifetch_Instruction_small="000000") then --R-type
Dis_CfcRdAddrTemp <= dispatch_rdaddr;
elsif (Ifetch_Instruction_small="001000") then --addi
Dis_CfcRdAddrTemp <= dispatch_rtaddr;
elsif (Ifetch_Instruction_small="100011") then --lw
Dis_CfcRdAddrTemp <= dispatch_rtaddr;
elsif (Ifetch_Instruction_small="000011") then --jal
Dis_CfcRdAddrTemp <= ("11111");
else
Dis_CfcRdAddrTemp <= dispatch_rdaddr;
end if;
-- End of Task4
----------------------------------------------------------
end process ;
----------- Interface with issue queue-------------
-- This process is used to generate the enable signal for the desired issue queue. This signal acts
-- as a wen signal to update the desired issue queue. In addition, we generate the 3-bit ALUOpcode used
-- with r-type, addi, branch and ld/sw instructions.
process (Ifetch_Instruction_small,Ifetch_Instruction , ren_var,Cdb_Flush)
begin
DivIssquenable <= '0';
MulIssquenable <= '0';
IntIssquenable <= '0';
LdIssquenable <= '0' ;
Opcode <= "000";
if ((ren_var = '0') or (Cdb_Flush ='1') or (Ifetch_Instruction_small="000010")) then -- "000010" jump instruction
ImmLdSt <= Ifetch_Instruction(15 downto 0);
-- No entry in any queue is to be made. Queue enables has default value of "0"
else
ImmLdSt <= Ifetch_Instruction(15 downto 0);
case Ifetch_Instruction_small is
when "000000" =>
case Ifetch_Instruction(5 downto 0 ) is
when "011011" => ----div
DivIssquenable <= '1';
when "011001" => ---mul
MulIssquenable <= '1';
when "100000" => ---- add
IntIssquenable <= '1';
when "100010" => ---sub
IntIssquenable <= '1';
Opcode <= "001";
when "100100" => ---and
IntIssquenable <= '1';
Opcode <= "010";
when "100101" => ---or
IntIssquenable <= '1';
Opcode <= "011";
when "101010" => ---slt
IntIssquenable <= '1';
Opcode <= "101";
when "001000" => ---jr
IntIssquenable <= '1';
when others =>
Opcode <= "000";
end case;
when "001000" => -- addi
IntIssquenable <= '1';
Opcode <= "100";
when "000011" => -----jal
IntIssquenable <= '1';
when "000100" => -----beq
IntIssquenable <= '1';
Opcode <= "110";
when "000101" => -- bne
IntIssquenable <= '1';
Opcode <= "111";
when "100011" => -- Load
LdIssquenable <= '1';
Opcode(0)<= '1';
Opcode(2 downto 1)<= "00";
when "101011" => -- store
LdIssquenable <= '1';
Opcode(0)<= '0';
Opcode(2 downto 1)<= "00";
when others =>
Opcode <= "000";
end case ;
end if;
end process;
--- GENERATING RegWrite signal ------------------------------
-- Task5: Your task is to generate the RegWrite signal.
-- Hint1: Why do we need to include the Dis_CfcRdAddrTemp in the sensitivity list !!!
-- Hint2: For R-type instructions you need to check both opcode and the function field. Jr $rs and
-- Jr $31 have the same opcode as R-Type but are not register writing instruction.
process (Ifetch_Instruction_small, Ifetch_Instruction , Dis_CfcRdAddrTemp)
begin
--if (clk'event and clk='1') then
if (Ifetch_Instruction = X"00000020") then --NOP
RegWrite <= '0';
elsif (Ifetch_Instruction_small="000000" and Ifetch_Instruction(5 downto 0)/="001000") then --R-type except jr $31
RegWrite <= '1';
elsif (Dis_CfcRdAddrTemp ="00000") then --can't write reg$0
RegWrite <= '0';
elsif (Ifetch_Instruction_small="000100" --beq
or Ifetch_Instruction_small="000010" --jump
or Ifetch_Instruction_small="000101" --bne
or Ifetch_Instruction_small="101011") then --sw
RegWrite <= '0';
else
RegWrite <= '1';
-- end if;
end if;
-- End of Task5
----------------------------------------------------------
end process ;
-- Generating Jal , JrRs and Jr31 signals
process (Ifetch_Instruction_small, Ifetch_Instruction , dispatch_rsaddr)
begin
DisJr31 <= '0';
DisJrRs <= '0';
DisJal<= '0';
if ((Ifetch_Instruction_small = "000000") and (Ifetch_Instruction(5 downto 0 ) = "001000")) then-- jr
if (dispatch_rsaddr = "11111") then
DisJr31 <= '1';
else
DisJrRs <= '1';
end if;
elsif ( Ifetch_Instruction_small = "000011") then
DisJal<= '1';
end if;
end process ;
-- Generating Branch PC bits and Branch signal
bpb_comm_read:process(Ifetch_PcPlusFour,Ifetch_Instruction_small)
begin
BranchPCBits <= (Ifetch_PcPlusFour(4 downto 2) - 1); -- to get PC for instruction
if ((Ifetch_Instruction_small="000100") OR (Ifetch_Instruction_small="000101" )) then -- beq or bne
Branch <= '1'; -- queues and bpb
else
Branch <= '0';
end if ;
end process;
-- CLOCK PROCESS FOR GENERATING STALL SIGNAL ON JR $RS INSTRUCTION
-- This is a very important process which takes care of generating the stall signal required in case of Jr $rs
-- instruction. When there is a JR $rs instruction in dispatch, first we set the jr_stall flag which is used to stall
-- the dispatch stage. At the same time we record the Rob Tag mapped to the JR $rs instruction in a special register.
-- We snoop on the Cdb waiting for that Rob Tag in order to get the value of $rs which represents the jump address. At
-- that moment we can come out from the stall.
-- Note that the Jr $rs disappears after coming out on the Cdb and does not enter the ROB and hence no ROB entry is needed.
-- However, we still need to assign an Rob Tag for the Jr $rs instruction in order to use it for snooping on the Cdb.
-- Task6: The process is almost complete you just need to update the condition of two if statements
jr_process: process(Clk,Resetb)
begin
if (Resetb = '0') then
jr_stall <= '0';
jr_rob_tag <= "00000"; -- can be don't care also
elsif (Clk'event and Clk = '1') then
if (Cdb_Flush = '1') then
jr_stall <= '0' ;
else
if (Ifetch_Instruction(5 downto 0 )="001000" and Ifetch_Instruction_small = "000000")then -- if jr
-- Add the condition for the following if statement.
-- Hint: Single Condition
if (jr_stall = '0') then
jr_stall <= '1' ;
if (StageReg_InstValid = '0') then
jr_rob_tag <= Rob_BottomPtr ;
else
jr_rob_tag <= Rob_BottomPtr + 1 ;
end if;
end if ;
end if ; -- end of if jr
-- Complete the condition for the following if statement.
-- Hint: How do you know when to come out of the JR $rs stall!!
if (jr_stall = '1' and (Cdb_RobTag = jr_rob_tag-1)) then
jr_stall <= '0';
end if ;
end if ;-- if Cdb_Flush
end if ; -- if Resetb
-- End of Task6
----------------------------------------------------------
end process ;
----------------------------------------------------------
-- issue_queue_entry Process:
-- In this process we generate the BranchOtherAddr signal which is used in case of misprediction of branch instruction.
issue_queue_entry :process(Ifetch_Instruction,Ifetch_PcPlusFour,Bpb_BranchPrediction,DisJal, DisJr31,Ras_Addr)
variable branch_addr_sign_extended_var ,branch_target_addr:std_logic_vector(31 downto 0);
variable branch_addr_sign_extended_shifted_var :std_logic_vector(31 downto 0);
begin
if (Ifetch_Instruction(15) = '1') then
branch_addr_sign_extended_var := X"FFFF" & Ifetch_Instruction(15 downto 0) ;
else
branch_addr_sign_extended_var := X"0000" & Ifetch_Instruction(15 downto 0) ;
end if ;
branch_addr_sign_extended_shifted_var := branch_addr_sign_extended_var(29 downto 0)& "00";
branch_target_addr := branch_addr_sign_extended_shifted_var + Ifetch_PcPlusFour;
--------------------------- NOTE--------------------------------------------------
-- Dis_BranchOtherAddr pins carry the following :
-- a) In case of a branch , we sent the "other address" with branch. By "other address " we mean , the address to be taken in case the branch is mis-predicted
-- If the branch was predicted to be "not taken" , then we keep on executing the instructions from PC + 4 location only. In case of mis-prediction,
-- we need to jump to target address calculated , thus we send branch_target_Addr on these pins
-- If the branch was predicted to be "taken" , then we started executing instructions from "target address". In case of mis-prediction,
-- we actually need to execute instructions from PC+4 , thus we send PC+4 on the pins
-- b) In case of jr , the pins carry the address given by RAS (valid or invalid). Sending the invlaid address will be harmless. That address is compared with
-- the correct address from software stack and a flush signal is initiated in case of mis-match.
-- c) In case of jal, the pins carry PC+4 which is stored in register $31.
-----------------------------------------------------------------------------------------
if(Bpb_BranchPrediction = '1' or DisJal = '1') then
BranchOtherAddr <= Ifetch_PcPlusFour;
elsif (DisJr31 = '1') then
BranchOtherAddr <= Ras_Addr;
else
BranchOtherAddr <= branch_target_addr; -- put jr addr from RAS in case of jr
end if ;
end process;
-- PHYSICAL FILE SIGNALS (From second stage)
Dis_RsPhyAddr <= Cfc_RsPhyAddr;
Dis_RtPhyAddr <= Cfc_RtPhyAddr;
-- BPB SIGNALS... INTERFACE WITH BPB IS FROM FIRST STAGE
Dis_CdbUpdBranch <= Cdb_Branch;
Dis_CdbUpdBranchAddr<=Cdb_BrUpdtAddr;
Dis_CdbBranchOutcome<=Cdb_BranchOutcome; ---outcome bit from rob;
Dis_BpbBranchPCBits <= BranchPCBits ;
Dis_BpbBranch <= Branch ;
-- CFC SIGNALS.. INTERFACE WITH CFC IS FROM FIRST STAGE
Dis_CfcBranchTag <= Rob_BottomPtr when (StageReg_InstValid = '0') else Rob_BottomPtr + 1;
Dis_CfcRegWrite <= RegWrite and InstValid ;
Dis_CfcRsAddr <= dispatch_rsaddr ;
Dis_CfcRtAddr <= dispatch_rtaddr ;
Dis_CfcRdAddr <= Dis_CfcRdAddrTemp ;
Dis_CfcBranch <= Branch ;
Dis_CfcNewRdPhyAddr <= Frl_RdPhyAddr ;
Dis_CfcInstValid <= InstValid;
-- FRL SIGNALS.. INTERFACE WITH FRL IS FROM FIRST STAGE
Dis_FrlRead <= RegWrite and InstValid;
-- RAS SIGNALS.. INTERFACE WITH RAS IS FROM FIRST STAGE
Dis_PcPlusFour <= Ifetch_PcPlusFour ;
Dis_RasJalInst <= DisJal and InstValid;
Dis_RasJr31Inst <= DisJr31 and InstValid;
-- ISSUEQUE SIGNALS.. INTERFACE WITH ISSUEQUE IS FROM SECOND STAGE
-- translate_off
Dis_Instruction <= StageReg_Instruction ;
-- translate_on
Dis_RsDataRdy <= PhyReg_RsDataRdy ;
Dis_RtDataRdy <= PhyReg_RtDataRdy ;
Dis_RobTag <= Rob_BottomPtr ;
Dis_Opcode <= StageReg_Opcode;
Dis_IntIssquenable <= StageReg_IntIssquenable when (Cdb_Flush = '0') else '0';
Dis_LdIssquenable <= StageReg_LdIssquenable when (Cdb_Flush = '0') else '0';
Dis_DivIssquenable <= StageReg_DivIssquenable when (Cdb_Flush = '0') else '0';
Dis_MulIssquenable <= StageReg_MulIssquenable when (Cdb_Flush = '0') else '0';
Dis_Immediate <= StageReg_ImmLdSt ;
Dis_BranchOtherAddr <= StageReg_BranchOtherAddr ;
Dis_BranchPredict <= StageReg_BranchPredict;
Dis_Branch <= StageReg_Branch ;
Dis_BranchPCBits <= StageReg_BranchPCBits ;
Dis_JrRsInst <= StageReg_JrRsInst ;
Dis_Jr31Inst <= StageReg_Jr31Inst ;
Dis_JalInst <= StageReg_JalInst ;
-- ROB SIGNALS.. INTERFACE WITH ROB IS FROM SECOND STAGE
Dis_PrevPhyAddr <= Cfc_RdPhyAddr ;
Dis_NewRdPhyAddr <= StageReg_NewRdPhyAddr ;
Dis_RobRdAddr <= StageReg_RdAddr ;
Dis_InstValid <= StageReg_InstValid when (Cdb_Flush = '0') else '0';
Dis_InstSw <= StageReg_InstSw when (Cdb_Flush = '0') else '0';
Dis_RegWrite <= StageReg_RegWrite when (Cdb_Flush = '0') else '0'; -- signal for Queues too
Dis_SwRtPhyAddr <= Cfc_RtPhyAddr;
-- PROCESS FOR STAGE REGISTER of dispatch
process(Clk, Resetb)
begin
if (Resetb = '0') then
StageReg_InstValid <= '0';
StageReg_InstSw <= '0';
StageReg_RegWrite <= '0';
StageReg_IntIssquenable <= '0';
StageReg_LdIssquenable <= '0';
StageReg_DivIssquenable <= '0';
StageReg_MulIssquenable <= '0';
StageReg_Branch <= '0';
StageReg_JrRsInst <= '0';
StageReg_Jr31Inst <= '0';
StageReg_JalInst <= '0';
elsif (Clk'event and Clk = '1' ) then
StageReg_RdAddr <= Dis_CfcRdAddrTemp ;
StageReg_InstValid <= InstValid ;
StageReg_InstSw <= InstSw ;
StageReg_RegWrite <= RegWrite and InstValid; -- RegWrite , DisJrRs, DisJal and DisJr31 are generated in the process without checking the validity of instruciton . Thus needs to be validated with InstValid signal
StageReg_Instruction <= Ifetch_Instruction ;
StageReg_NewRdPhyAddr <= Frl_RdPhyAddr;
StageReg_Opcode <= Opcode;
StageReg_IntIssquenable <= IntIssquenable ;
StageReg_LdIssquenable <= LdIssquenable;
StageReg_DivIssquenable <= DivIssquenable;
StageReg_MulIssquenable <= MulIssquenable;
StageReg_ImmLdSt <= ImmLdSt ;
StageReg_BranchOtherAddr <= BranchOtherAddr ;
StageReg_BranchPredict <= Bpb_BranchPrediction ;
StageReg_Branch <= Branch ;
StageReg_BranchPCBits <= BranchPCBits ;
StageReg_JrRsInst <= DisJrRs and InstValid;
StageReg_Jr31Inst <= DisJr31 and InstValid;
StageReg_JalInst <= DisJal and InstValid;
end if ;
end process;
end behv ;
|
gpl-2.0
|
d33fe16a295921cd71980805d1a5cff8
| 0.585306 | 4.492682 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/example_design/RD_DATA_FIFO_top.vhd
| 1 | 5,226 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RD_DATA_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RD_DATA_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RD_DATA_FIFO_top;
architecture xilinx of RD_DATA_FIFO_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component RD_DATA_FIFO is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : RD_DATA_FIFO PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
22ff53ce196a9ed34f1ff7f9c70a276a
| 0.513012 | 4.750909 | false | false | false | false |
tuura/fantasi
|
dependencies/ffd.vhdl
| 1 | 564 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
LIBRARY work;
entity ffd is
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic
);
end entity ffd;
architecture Behavioral of ffd is
signal q_tmp : std_logic;
begin
process (CLK) is
begin
if rising_edge(CLK) then
if (RST='1') then
q_tmp <= '0';
elsif (EN='1') then
q_tmp <= D;
end if;
end if;
end process;
Q <= q_tmp;
end architecture Behavioral;
|
mit
|
e30f88b72e7d000fa46825cb35eefdc8
| 0.535461 | 3.133333 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_send_fifo/example_design/pcie_data_send_fifo_top_wrapper.vhd
| 1 | 19,795 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_data_send_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_data_send_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(256-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(11-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(11-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(11-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(11-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end pcie_data_send_fifo_top_wrapper;
architecture xilinx of pcie_data_send_fifo_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_data_send_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : pcie_data_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
b336811dd447005732d0f7bd586694d4
| 0.484516 | 3.963757 | false | false | false | false |
tuura/fantasi
|
dependencies/counter.vhdl
| 1 | 763 |
-- Generic counter
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_counter IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic_vector(N-1 downto 0));
END Generic_counter;
ARCHITECTURE behavioural OF Generic_counter IS
SIGNAL count : STD_LOGIC_VECTOR(N-1 downto 0);
BEGIN
process (CLK, RST)
begin
if RST = '1' then
count <= (others => '0');
elsif (CLK = '1' AND CLK'event) then
if EN = '1' then
count <= count + 1;
end if;
end if;
end process;
DOUT <= count;
END behavioural;
|
mit
|
46653e20b422c9193c8e3071fde2b3cc
| 0.547837 | 3.516129 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_data_rec_fifo/simulation/fg_tb_synth.vhd
| 1 | 11,825 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(12-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 12,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_data_rec_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
40378882d0858bcff229473703819657
| 0.455814 | 3.97212 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
delay.vhd
| 1 | 2,182 |
-- Greg Stitt
-- University of Florida
--
-- Entity: delay
-- Description: This entity delays an input by a specified number of cycles,
-- while also allowing stalls and specific output values on reset.
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic Descriptions
-- cycles : The length of the delay in cycles (required)
-- width : The width of the input signal (required)
-- init : An initial value (of width bits) for the first "cycles" output
-- after a reset (required)
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Port Description
-- clk : clock
-- rst : reset
-- en : enable (active high), '0' stalls the delay pipeline
-- input : The input to be delayed
-- output : The input after "cycles" pass (assuming no stalls from en='0')
-------------------------------------------------------------------------------
entity delay is
generic(cycles : natural;
width : positive;
init : std_logic_vector);
port( clk : in std_logic;
rst : in std_logic;
en : in std_logic := '1';
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end delay;
architecture FF of delay is
type reg_array is array (0 to cycles-1) of std_logic_vector(width-1 downto 0);
signal regs : reg_array;
begin -- BHV
U_CYCLES_GT_0 : if cycles > 0 generate
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to cycles-1 loop
regs(i) <= init;
end loop;
elsif (clk'event and clk = '1') then
if (en = '1') then
regs(0) <= input;
end if;
for i in 0 to cycles-2 loop
if (en = '1') then
regs(i+1) <= regs(i);
end if;
end loop;
end if;
end process;
output <= regs(cycles-1);
end generate U_CYCLES_GT_0;
U_CYCLES_EQ_0 : if cycles = 0 generate
output <= input;
end generate U_CYCLES_EQ_0;
end FF;
|
gpl-3.0
|
0074862bcd0e1d7f3a9299ed047b2e44
| 0.504583 | 4.070896 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_selective_flushing.vhd
| 3 | 6,758 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"0182701B_008C6819_0202601B_00000020", -- Loc 0C, 08, 04, 00
X"00232819_11C40006_AC0C0004_8C890000", -- Loc 1C, 18, 14, 10 -- corrected
X"0242601B_8C840000_00030820_00020820", -- Loc 2C, 28, 24, 20
X"00000020_00000020_AC0E0004_AC0C0004", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Sukhun Kang
-- Date : 07/27/09
--0202601B DIV $12, $16, $2 $12 = 16/2 = 8
--006C6819 MUL $13, $4, $12 $13 = 8*4 = 32
--0182701B DIV $14, $12, $2 $14 = 8/2 = 4
--8C890000 LW $9, 0($4) $9 = dmem(1) = 10H
--AC0C0004 SD $12, 4($0) dmem(1) = 8
--11C40006 BEQ $14, $4, 6 IF $4 = $14, jump to the instruction after SD $12, 4($0) skips 6 instructions
--00232819 MUL $5, $1, $3 $5 = 1*3 = 3 * should be flushed*
--00020820 ADD $1, $0, $2 $1 = 0+2 = 2 *should be flushed*
--00030820 ADD $1, $0, $3 $1 = 0+3 = 3* should be flushed*
--8C840000 LD $4, 0($4) $4 = dmem(1) = 2 *should be flushed*
--0242601B DIV $12, $18, $2 $12 = 18/2 = 9 *should flushed*
--AC0C0004 SD $12, 4($0) dmem(1) = 9 *should flushed*
--AC0E0004 SD $14, 4($0) dmem(1) = 4
--************************************************
|
gpl-2.0
|
57eb3078e4cc9d4f3cc812074d5b44a3
| 0.653448 | 2.889269 | false | false | false | false |
csrhau/sandpit
|
VHDL/vga_imdisplay/vga_sequencer.vhdl
| 2 | 2,571 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity vga_sequencer is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
output_enable : out std_logic := '0';
-- TODO make this out natural range vga_memory'range;
read_address : out natural range vga_memory'range := 0;
hsync : out std_logic := '1';
vsync : out std_logic := '1'
);
end vga_sequencer;
architecture behavioural of vga_sequencer is
type sync_state is (SRead, SUpdate, SDelay1, SDelay2);
signal state : sync_state := SDelay1; -- Give the system time to get ready
constant H_PULSE_START : natural := display_cols + 16; -- front porch is 16 columns
constant H_PULSE_END: natural := H_PULSE_START + 96; -- Pulse is 96 columns
constant H_LINE_END: natural := H_PULSE_END + 48 - 1; -- back porch is 48 columns
constant V_PULSE_START : natural := display_rows + 10; -- front porch is 10 rows
constant V_PULSE_END: natural := V_PULSE_START + 2; -- Pulse is 2 rows
constant V_LINE_END: natural := V_PULSE_END + 33 - 1; -- back porch is 33 rows
signal h_count : natural range H_LINE_END downto 0 := 0;
signal v_count : natural range V_LINE_END downto 0 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
case state is
when SRead =>
if h_count < display_cols and v_count < display_rows then
output_enable <= '1';
read_address <= v_count * display_cols + h_count;
else
output_enable <= '0';
read_address <= 0;
end if;
state <= SUpdate;
when SUpdate =>
if h_count >= H_PULSE_START and h_count < H_PULSE_END then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count >= V_PULSE_START and v_count < V_PULSE_END then
vsync <= '0';
else
vsync <= '1';
end if;
-- UPDATE COUNTERS
if h_count = H_LINE_END then
h_count <= 0;
if v_count = V_LINE_END then
v_count <= 0;
else
v_count <= v_count + 1;
end if;
else -- not at a row/col border
h_count <= h_count + 1;
end if;
state <= SDelay1;
when SDelay1 =>
state <= SDelay2;
when SDelay2 =>
state <= SRead;
end case;
end if; -- end rising_edge if
end process;
end behavioural;
|
mit
|
cc2f1dde697d647216a4440619f552ef
| 0.559315 | 3.699281 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/GC_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,316 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT GC_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
aae42db32d5183a02321430780e134ad
| 0.504065 | 3.930531 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RESPONSE_QUEUE/example_design/RESPONSE_QUEUE_top_wrapper.vhd
| 1 | 19,010 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RESPONSE_QUEUE_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RESPONSE_QUEUE_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(7-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(7-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(7-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(7-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(7-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(7-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(8-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(8-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(8-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end RESPONSE_QUEUE_top_wrapper;
architecture xilinx of RESPONSE_QUEUE_top_wrapper is
SIGNAL clk_i : std_logic;
component RESPONSE_QUEUE_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : RESPONSE_QUEUE_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
efe8f5311fe2e54068bb4f5bb5858a16
| 0.486796 | 3.97782 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_div.vhd
| 3 | 7,087 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- All instructions are div $2 $3 $2
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
(X"0062101B_0062101B_0062101B_0062101B", -- Loc 0C, 08, 04, 00
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1C, 18, 14, 10
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2C, 28, 24, 20
X"0062101B_0062101B_0062101B_0062101B", -- Loc 3C, 38, 34, 30
X"0062101B_0062101B_0062101B_0062101B", -- Loc 4C, 48, 44, 40
X"0062101B_0062101B_0062101B_0062101B", -- Loc 5C, 58, 54, 50
X"0062101B_0062101B_0062101B_0062101B", -- Loc 6C, 68, 64, 60
X"0062101B_0062101B_0062101B_0062101B", -- Loc 7C, 78, 74, 70
X"0062101B_0062101B_0062101B_0062101B", -- Loc 8C, 88, 84, 80
X"0062101B_0062101B_0062101B_0062101B", -- Loc 9C, 98, 94, 90
X"0062101B_0062101B_0062101B_0062101B", -- Loc AC, A8, A4, A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc BC, B8, B4, B0
X"0062101B_0062101B_0062101B_0062101B", -- Loc CC, C8, C4, C0
X"0062101B_0062101B_0062101B_0062101B", -- Loc DC, D8, D4, D0
X"0062101B_0062101B_0062101B_0062101B", -- Loc EC, E8, E4, E0
X"0062101B_0062101B_0062101B_0062101B", -- Loc FC, F8, F4, F0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 10C, 108, 104, 100
X"0062101B_0062101B_0062101B_0062101B", -- Loc 11C, 118, 114, 110
X"0062101B_0062101B_0062101B_0062101B", -- Loc 12C, 128, 124, 120
X"0062101B_0062101B_0062101B_0062101B", -- Loc 13C, 138, 134, 130
X"0062101B_0062101B_0062101B_0062101B", -- Loc 14C, 148, 144, 140
X"0062101B_0062101B_0062101B_0062101B", -- Loc 15C, 158, 154, 150
X"0062101B_0062101B_0062101B_0062101B", -- Loc 16C, 168, 164, 160
X"0062101B_0062101B_0062101B_0062101B", -- Loc 17C, 178, 174, 170
X"0062101B_0062101B_0062101B_0062101B", -- Loc 18C, 188, 184, 180
X"0062101B_0062101B_0062101B_0062101B", -- Loc 19C, 198, 194, 190
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1AC, 1A8, 1A4, 1A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1BC, 1B8, 1B4, 1B0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1CC, 1C8, 1C4, 1C0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1DC, 1D8, 1D4, 1D0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1EC, 1E8, 1E4, 1E0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 1FC, 1F8, 1F4, 1F0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 20C, 208, 204, 200
X"0062101B_0062101B_0062101B_0062101B", -- Loc 21C, 218, 214, 221
X"0062101B_0062101B_0062101B_0062101B", -- Loc 22C, 228, 224, 220
X"0062101B_0062101B_0062101B_0062101B", -- Loc 23C, 238, 234, 230
X"0062101B_0062101B_0062101B_0062101B", -- Loc 24C, 248, 244, 240
X"0062101B_0062101B_0062101B_0062101B", -- Loc 25C, 258, 254, 250
X"0062101B_0062101B_0062101B_0062101B", -- Loc 26C, 268, 264, 260
X"0062101B_0062101B_0062101B_0062101B", -- Loc 27C, 278, 274, 270
X"0062101B_0062101B_0062101B_0062101B", -- Loc 28C, 288, 284, 280
X"0062101B_0062101B_0062101B_0062101B", -- Loc 29C, 298, 294, 290
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2AC, 2A8, 2A4, 2A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2BC, 2B8, 2B4, 2B0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2CC, 2C8, 2C4, 2C0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2DC, 2D8, 2D4, 2D0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2EC, 2E8, 2E4, 2E0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 2FC, 2F8, 2F4, 2F0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 30C, 308, 304, 300
X"0062101B_0062101B_0062101B_0062101B", -- Loc 31C, 318, 314, 331
X"0062101B_0062101B_0062101B_0062101B", -- Loc 32C, 328, 324, 320
X"0062101B_0062101B_0062101B_0062101B", -- Loc 33C, 338, 334, 330
X"0062101B_0062101B_0062101B_0062101B", -- Loc 34C, 348, 344, 340
X"0062101B_0062101B_0062101B_0062101B", -- Loc 35C, 358, 354, 350
X"0062101B_0062101B_0062101B_0062101B", -- Loc 36C, 368, 364, 360
X"0062101B_0062101B_0062101B_0062101B", -- Loc 37C, 378, 374, 370
X"0062101B_0062101B_0062101B_0062101B", -- Loc 38C, 388, 384, 380
X"0062101B_0062101B_0062101B_0062101B", -- Loc 39C, 398, 394, 390
X"0062101B_0062101B_0062101B_0062101B", -- Loc 3AC, 3A8, 3A4, 3A0
X"0062101B_0062101B_0062101B_0062101B", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
gpl-2.0
|
0c12f92c839434785e018f02b31d07e3
| 0.638634 | 2.893834 | false | false | false | false |
BBN-Q/APS2-TDM
|
testbenches/ApsCfgConstants.vhd
| 1 | 4,372 |
-- ApsCfgConstants.vhd
--
-- This provides menmonic definitions for the Config interface
--
--
-- REVISIONS
--
-- 7/9/2013 CRJ
-- Created
--
-- 8/13/2013 CRJ
-- Initial release
--
-- END REVISIONS
--
library ieee;
use ieee.std_logic_1164.all;
package ApsCfgConstants is
-- Constants used for the configuration I/O interface
-- Config Command Word Format:
--
-- D<15:8> Command Dependent
-- D<7> R/!W
-- D<6:4> Target: 000 = EPROM, 001 = DRAM, 010 = Control/Status Registers, others = reserved.
-- D<3:0> Command Code
-- Commands Processed by the Config Chip. The command code uses the above fields to define the command
-- This interface is only available to ZRL code in the FPGA. All other code goes through the ZRL code,
-- so user commands are translated into this format.
-- These definitions are required by the ApsMsgProc module
-- Define the bit fields in the command word
constant CFG_RW_BIT : natural := 7;
subtype CFG_CMD_RANGE is natural range 3 downto 0;
subtype CFG_TARG_RANGE is natural range 6 downto 4;
-- R/W EPROM
constant CFG_READ_NVM : std_logic_vector(7 downto 0) := x"91";
constant CFG_WRITE_NVM : std_logic_vector(7 downto 0) := x"11";
constant CFG_ERASE_NVM : std_logic_vector(7 downto 0) := x"92"; -- Non-write, so mark as a read
constant CFG_RUN_NVM : std_logic_vector(7 downto 0) := x"98"; -- MSB of command code set for non R/W command
constant CFG_LDFRM_NVM : std_logic_vector(7 downto 0) := x"99";
-- R/W DRAM
constant CFG_READ_DRAM : std_logic_vector(7 downto 0) := x"A1";
constant CFG_WRITE_DRAM : std_logic_vector(7 downto 0) := x"21";
constant CFG_CAL_DRAM : std_logic_vector(7 downto 0) := x"A8"; -- MSB of command code set for non R/W command
constant CFG_LDFRM_DRAM : std_logic_vector(7 downto 0) := x"A9";
-- LDFRM from either DRAM or EPROM is the same in the LSB. Saves logic for checking
constant CFG_LDFRM : std_logic_vector(3 downto 0) := x"9";
-- R/W Registers. Not used on APS
constant CFG_READ_REG : std_logic_vector(7 downto 0) := x"B1";
constant CFG_WRITE_REG : std_logic_vector(7 downto 0) := x"31";
-- Encoded SPI command. Data portion contains one or more 32 bit command/data words from the FPGA.
-- Address fields not used, since taget is in the SPI data packets
-- Subsequent read returns any pending read data store in a FIFO.
-- Only used on APS
constant CFG_SPI_READ : std_logic_vector(7 downto 0) := x"C1";
constant CFG_SPI_CMD : std_logic_vector(7 downto 0) := x"41";
-- Chip Packet Command Format:
-- D[31..24] = Target
-- D[23..16] = Data/Cnt. Data for single byte command, count of bytes for multi byte command
-- D[15..0] = SPI Instruction
-- Next DWORDs = Data if not single byte instruction
-- Target codes for the Config I/O packet data from the host
-- 0x00 ........................Pause commands stream for 100ns times the count in D<23:0>
-- 0xC0/0xC8 ...................DAC Channel 0 Access (AD9736)
-- 0xC1/0xC9 ...................DAC Channel 1 Access (AD9736)
-- 0xD0/0xD8 ...................PLL Clock Generator Access (AD518-1)
-- 0xE0 ........................VCXO Controller Access (CDC7005)
-- 0xFF ........................End of list
constant TARG_BYTE : natural := 3; -- Bit 3 set if it is a single byte command with the data in the count field
-- Defined so that you upper 3 bits decodes the target
constant TARG_PAUSE : std_logic_vector(7 downto 0) := x"00";
constant TARG_DAC : std_logic_vector(7 downto 0) := x"C0"; -- Bit 0 = 0 for DAC0 and 1 for DAC1
constant TARG_DAC_BYTE : std_logic_vector(7 downto 0) := x"C8"; -- Bit 0 = 0 for DAC0 and 1 for DAC1
constant TARG_PLL : std_logic_vector(7 downto 0) := x"D0";
constant TARG_PLL_BYTE : std_logic_vector(7 downto 0) := x"D8";
constant TARG_VCXO : std_logic_vector(7 downto 0) := x"E0";
constant TARG_EOL : std_logic_vector(7 downto 0) := x"FF";
-- Bit definitions for the status that is driven when STAT_OE is asserted
-- These bits are returned as part of the Status command
constant DAC0_IRQ_BIT : natural := 0;
constant DAC1_IRQ_BIT : natural := 1;
constant PLL_STATUS_BIT : natural := 2;
constant PLL_REFMON_BIT : natural := 3;
constant PLL_LD_BIT : natural := 4;
constant VCXO_LOCK_BIT : natural := 5;
constant VCXO_REF_BIT : natural := 6;
constant VCXO_VCXO_BIT : natural := 7;
end package ApsCfgConstants;
|
mpl-2.0
|
8a2e9df54521cd2aae5523b7f2371523
| 0.669716 | 3.205279 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_jal_jr.vhd
| 3 | 7,778 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- $0 : 0
-- $1 : 1
-- $2 : 2
-- $3 : 3
-- $4 : 4
-- $5 : 5
-- $29: contains fixed bottom of stack for $31 values
--
-- add $2, $0, $0
-- add $3, $1, $1 ---
-- jal subroutine ---
-- add $3, $2, $3 ---store final ans. in $3
-- nop
-- nop
-- nop
-- jump exit
-- subroutine:
-- add $2, $1, $2
-- add $3, $1, $3
-- jr $31
-- nop
-- nop
-- nop
-- nop
-- exit:
-- lots of nop
--- EXPECTED RESULT
--- PHYSICAL REG FILE CONTENTS CHANGE AS FOLLOWS :
-- 32 => 0(d)
-- 33 => 2(d)
-- 34 => 12(d)
-- 35 => 1(d)
-- 36 => 3(d)
-- 37 => 4(d)
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
( X"00621820_0C000008_00211820_00001020", -- Loc 0C, 08, 04, 00 sw_addi_add_add
X"08000010_00000020_00000020_00000020", -- Loc 1C, 18, 14, 10 jump_nop_add_jal
X"00000020_03E00008_00611820_00221020", -- Loc 2C, 28, 24, 20 addi_lw_add_add
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30 nop_nop_nop_jr
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_nop_nop_nop
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
gpl-2.0
|
663450be46f8e0e9adbbc99c06cd6c58
| 0.617768 | 3.073094 | false | false | false | false |
csrhau/sandpit
|
VHDL/mux/test_mux.vhdl
| 1 | 1,033 |
library ieee;
use ieee.std_logic_1164.all;
entity test_mux is
end entity test_mux;
architecture behavioural of test_mux is
component MUX is
port (
selector : in std_logic;
input_a : in std_logic_vector(7 downto 0);
input_b : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end component MUX;
signal selector : std_logic;
signal input_a : std_logic_vector(7 downto 0);
signal input_b : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
begin
multiplexer : MUX port map (selector, input_a, input_b, output);
process
begin
input_a <= "00001111";
input_b <= "11110000";
selector <= '0';
wait for 1 ns;
assert output = input_a
report "MUX should output input_a when selector is zero" severity error;
selector <= '1';
wait for 1 ns;
assert output = input_b
report "MUX should output input_b when selector is zero" severity error;
wait;
end process;
end behavioural;
|
mit
|
0835b0c447c74388f34d91dc4fad9fb6
| 0.652469 | 3.562069 | false | true | false | false |
csrhau/sandpit
|
VHDL/single_port_ram/test_ram.vhdl
| 1 | 1,442 |
library ieee;
use ieee.std_logic_1164.all;
entity test_ram is
end test_ram;
architecture behavioural of test_ram is
component RAM is
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector(9 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end component RAM;
signal clock : std_logic;
signal write_enable : std_logic;
signal address : std_logic_vector(9 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
begin
ramcell : RAM port map (clock, write_enable, address, data_in, data_out);
process
begin
clock <= '0';
wait for 1 ns;
address <= "0000000000";
write_enable <= '1';
data_in <= "01010101";
clock <= '1';
wait for 1 ns;
assert data_out = "00000000"
report "RAM should be zero initialized" severity error;
clock <= '0';
wait for 1 ns;
write_enable <= '0';
data_in <= "11110000";
clock <= '1';
wait for 1 ns;
assert data_out = "01010101"
report "data should have been written and returned" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_out = "01010101"
report "data should not be overwritten with write_enable false" severity error;
wait;
end process;
end behavioural;
|
mit
|
bbbd23be26695517865a35223bb54eed
| 0.619279 | 3.542998 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_PRE_FIFO/simulation/fg_tb_top.vhd
| 1 | 6,021 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 68
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
69c30de2c046e4ecb9c0315354282ad2
| 0.612025 | 4.095918 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/clk_wiz_v3_6.vhd
| 1 | 6,209 |
-- file: clk_wiz_v3_6.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____20.000______0.000______50.0_____1200.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary___________50.00____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_6 is
port
(-- Clock in ports
clk : in std_logic;
-- Clock out ports
clk_20MHz : out std_logic
);
end clk_wiz_v3_6;
architecture xilinx of clk_wiz_v3_6 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => clk);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.500,
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => clk_20MHz,
I => clkfx);
end xilinx;
|
apache-2.0
|
7f7b8e5c2c380961f5980c6ae03c2b04
| 0.572395 | 4.246922 | false | false | false | false |
BBN-Q/APS2-TDM
|
src/PWMA8.vhd
| 1 | 628 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PWMA8 is
port
(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector (7 downto 0) := "00000000";
PWM_OUT : out std_logic
);
end PWMA8;
architecture behavior of PWMA8 is
signal PWM_Accumulator : std_logic_vector(8 downto 0);
begin
process(CLK, RESET)
begin
if RESET = '1' then
PWM_Accumulator <= (others => '0');
elsif rising_edge(CLK) then
PWM_Accumulator <= ("0" & PWM_Accumulator(7 downto 0)) + ("0" & DIN);
end if;
end process;
PWM_OUT <= PWM_Accumulator(8);
end behavior;
|
mpl-2.0
|
79b9660023b5cea632e948496b9fa6a5
| 0.64172 | 3.078431 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/ee560_debounce_DPB_SCEN_CCEN_MCEN.vhd
| 1 | 9,878 |
------------------------------------------------------------------------------
-- File name: ee560_debounce_DPB_SCEN_CCEN_MCEN.vhd
-- Date: 6/10/2009
-- (C) Copyright 2009 Gandhi Puvvada
-- Description:
-- A vhdl design for debouncing a Push Button (PB) and produce the following:
-- (1) a debounced pulse DPB (DPB = debounced PB)
-- (2) a single clock-enable pulse, SCEN, after 0.084 sec, for single-stepping user design using a push button,
-- (3) a contunuous clock-enable pulse, CCEN, after another 0.16 sec., for running at full-speed
-- (4) a sequence of (multiple of) clock-enable pulses, MCEN, after every 0.084 sec after the 0.16 sec, for multi-stepping
--
-- Once 'PB' is pressed, after the initial bouncing finishes in the WQ (wait quarter second (actaully 0.084 sec)) state, the DPB is activated,
-- and all three pulses (SCEN, CCEN, and MCEN) are produced just for *one clock* in SCEN_state.
-- Then, after waiting another half second in the WH (wait half second) (actaully 0.168 sec)) state, the MCEN goes active for 1 clock every
-- quarter second and the CCEN goes active continuously. in MCEN_state. Finally, if the PB is released, we wait in WFCR
-- (Wait for a complete release) state for a quarter second and return to the INI state. Please see the state diagram or
-- read the code to understand the exact behavior.
-- The additional half-second (actually 0.168 sec) waiting after producing the first single-clock wide pulse allows the user
-- to release the button in time to avoid multi-stepping or running at full-speed even if he/she has used MCEN or CCEN
-- in his/her design.
-- To achieve the above and generate the outputs without asny glitches (though this is not necessary), let us use output coding.
-- In output coding the state memory bits are thoughtfully chosen in order to form the needed outputs.
-- In this case DPB, SCEN, MCEN, and CCEN are thos outputs. However, the output combinations may repeat in different states.
-- So we need here two tie-breakers.
-- State State DPB SCEN MCEN CCEN Tie-Breaker1 Tie-Breaker0
-- initial INI 0 0 0 0 0 0
-- wait quarter WQ 0 0 0 0 0 1
-- SCEN_state SCEN_st 1 1 1 1 - -
-- wait half WH 1 0 0 0 0 0
-- MCEN_state MCEN_st 1 0 1 1 - -
-- CCEN_state CCEN_st 1 0 0 1 - -
-- Counter Clear CCR 1 0 0 0 0 1
-- WFCR_state WFCR 1 0 0 0 1 -
-- Timers (Counters to keep time): 2**19 clocks of 20ns = 2**20 of 10ns = approximately 10 milliseconds = accurately 10.48576 ms
-- So, instead of quarter second, let us wait for 2**22 clocks ( 0.084 sec.) and instead of half second,
-- let us wait for 2**23 clocks (0.168 seconds).
-- If we use a 24-bit counter, count(23 downto 0), and start it with 0, then the first time, count(22) goes high,
-- we know that the lower 22 bits (21:0) have gone through their 2**22 combinations. So count(22) is used as
-- the 0.084 sec timer and the count(23) is used as the 0.168 sec timer.
-- We will use a generic parameter called N_dc (dc for debounce count) in place of 23 (and N_dc-1 in place of 22),
-- so that N_dc can be made 4 during behavioral simulation to test this debouncing module.
-- As the names say, the SCEN, MCEN, and the CCEN are clock enables and are not clocks by themselves. If you use
-- SCEN (or MCEN) as a "clock" by itself, then you would be creating a lot of sckew as these outputs of the internal
-- state machine take ordinary routes and do not get to go on the special routes used for clock distribution.
-- However, when they are used as clock enables, the static timing analyzer checks timing of these signals with respect
-- to the main clock signal (50 MHz clock) properly. This results in a good timing design. Moreover, you can use different
-- clock enables in different parts of the control unit so that the system is single stepped in some critical areas and
-- multi-stepped or made to run at full speed. This will not be possible if you try to use both SCEN and MCEN as clocks
-- as you should not be using multiple clocks in a supposedly single-clock system.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ee560_debounce is
generic (N_dc: positive := 23);
port (CLK, RESETB_DEBOUNCE :in std_logic; -- CLK = 50 MHz
PB :in std_logic; -- push button
DPB, SCEN, MCEN, CCEN :out std_logic -- debounced PB, single_CEN, multi_CEN, continuous CEN
);
end ee560_debounce ;
-------------------------------------------------------------------------------
architecture debounce_RTL of ee560_debounce is
-- Note: The most common RTL coding in VHDL is to use symbolic names for states
-- and leave it to the synthesis tool to tie these symbolic names to encoded bit combinations.
-- Designers define a suitable enumerated state type as shown below.
-- type debounce_state_type is (INI, WQ, SCEN_St, WH, MCEN_St, CCEN_St, CCR, WFCR);
-- signal debounce_state: debounce_state_type;
-- However, in this design, we would like to use output coding and we want enforce state assignments.
-- Hence, we define constants bearing the symbolic state names and initialize them to the bit
-- combinations of our choice.
-- By default, the synthesis tool (with default XST option "auto" for FSM encoding) will extract the state machine and will perform
attribute fsm_encoding: string; -- Refer to XST user guide -- FSM encoding
signal debounce_state: std_logic_vector(5 downto 0); -- 6-bit combination
-- DPB SCEN MCEN CCEN TieB1 TieB0
constant INI: std_logic_vector(5 downto 0) := ('0' & '0' & '0' & '0' & '0' & '0');
constant WQ: std_logic_vector(5 downto 0) := ('0' & '0' & '0' & '0' & '0' & '1');
constant SCEN_st: std_logic_vector(5 downto 0) := ('1' & '1' & '1' & '1' & '0' & '0');
constant WH: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '0' & '0');
constant MCEN_St: std_logic_vector(5 downto 0) := ('1' & '0' & '1' & '1' & '0' & '0');
constant CCEN_St: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '1' & '0' & '0');
constant CCR: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '0' & '1');
constant WFCR: std_logic_vector(5 downto 0) := ('1' & '0' & '0' & '0' & '1' & '0');
attribute fsm_encoding of debounce_state: signal is "user";
-- The enumerated state type allows the display of state name in symbolic form (ASCII form) in the waveform which is easy to read.
-- So, to provide this convenience, let us define an enumerated state signal called d_state here, and later assign values to it.
type debounce_state_type is (INI_s, WQ_s, SCEN_St_s, WH_s, MCEN_St_s, CCEN_St_s, CCR_s, WFCR_s);
signal d_state: debounce_state_type;
signal debounce_count: std_logic_vector(N_dc downto 0);
-- signal DPB_int, SCEN_int, MCEN_int, CCEN_int: std_logic; -- internal signals
-- signal tie-breaker1, tie-breaker0: std_logic; -- internal signals
begin
-- concurrent signal assignment statements
(DPB, SCEN, MCEN, CCEN) <= debounce_state(5 downto 2); -- this is because of output coding
-- for the purpose of displaying in the waveform
d_state <= INI_s when (debounce_state = INI) else
WQ_s when (debounce_state = WQ) else
SCEN_St_s when (debounce_state = SCEN_St) else
WH_s when (debounce_state = WH) else
MCEN_St_s when (debounce_state = MCEN_St) else
CCEN_St_s when (debounce_state = CCEN_St) else
CCR_s when (debounce_state = CCR) else
WFCR_s; -- when (debounce_state = WFCR);
debounce: process (CLK, RESETB_DEBOUNCE)
begin
if (RESETB_DEBOUNCE = '0') then
debounce_count <= (others => 'X');
debounce_state <= INI;
elsif (CLK'event and CLK = '1') then
case debounce_state is
when INI =>
debounce_count <= (others => '0');
if (PB = '1') then
debounce_state <= WQ;
end if;
when WQ =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= INI;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= SCEN_St;
end if;
when SCEN_St =>
debounce_count <= (others => '0');
debounce_state <= WH;
when WH =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= CCR;
elsif (debounce_count(N_dc) = '1') then
debounce_state <= MCEN_St;
end if;
when MCEN_St =>
debounce_count <= (others => '0');
debounce_state <= CCEN_St;
when CCEN_St =>
debounce_count <= debounce_count + 1;
if (PB = '0') then
debounce_state <= CCR;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= MCEN_St;
end if;
when CCR =>
debounce_count <= (others => '0');
debounce_state <= WFCR;
when others => -- when WFCR =>
debounce_count <= debounce_count + 1;
if (PB = '1') then
debounce_state <= WH;
elsif (debounce_count(N_dc-1) = '1') then
debounce_state <= INI;
end if;
end case;
end if;
end process debounce;
----------------------------
end debounce_RTL ;
|
gpl-2.0
|
06e2f7924ae8d2cf1fdcc58687211afc
| 0.59921 | 3.478169 | false | false | false | false |
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