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stringlengths 32
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float64 0.25
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classes | has_no_keywords
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class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
gxliu/ARM-Cortex-M0
|
hdl/memory_no_clk.vhd
| 1 | 2,264 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity memory_no_clk is
generic ( N : integer := 1);
port ( clk : in std_logic;
write_en: in std_logic;
addr_1 : in std_logic_vector (31 downto 0);
addr_2 : in std_logic_vector (31 downto 0);
data_w2 : in std_logic_vector (31 downto 0);
data_r1 : out std_logic_vector (31 downto 0);
data_r2 : out std_logic_vector (31 downto 0));
end memory_no_clk;
architecture Behavioral of memory_no_clk is
type type_mem_file is array(0 to N) of bit_vector(31 downto 0);
impure function load_from_mem (ram_file_name : in string) return type_mem_file is
file ram_file : text is in ram_file_name;
variable line_name : line;
variable ram_name : type_mem_file;
begin
for I in type_mem_file'range loop
readline (ram_file, line_name);
read (line_name, ram_name(I));
end loop;
return ram_name;
end function;
signal mem_file : type_mem_file := load_from_mem("push");
signal addr_1_tmp, addr_2_tmp : std_logic_vector (31 downto 0);
begin
write_port : process(clk)
begin
if rising_edge(clk) then
if write_en = '1' then
mem_file(conv_integer(addr_2)) <= to_bitvector(data_w2);
end if;
end if;
end process;
addr_1_tmp <= addr_1 when conv_integer(addr_1) < N and conv_integer(addr_1) > 0 else (others=>'0');
addr_2_tmp <= addr_2 when conv_integer(addr_2) < N and conv_integer(addr_2) > 0 else (others=>'0');
data_r1 <= to_stdlogicvector(mem_file(conv_integer(addr_1_tmp))) when conv_integer(addr_1) < N and conv_integer(addr_1) > 0 else (others=>'0');
data_r2 <= to_stdlogicvector(mem_file(conv_integer(addr_2_tmp))) when conv_integer(addr_2) < N and conv_integer(addr_2) > 0 else (others=>'0');
end Behavioral;
|
mit
|
ef99dc65aad6224dcef283335c8eb4bb
| 0.529152 | 3.593651 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/rgb_conv.vhd
| 1 | 2,916 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: rgb_conv.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity rgb_conv is
Port ( r : in STD_LOGIC;
g : in STD_LOGIC;
b : in STD_LOGIC;
pos_h : in std_logic_vector(9 downto 0);
pos_v : in std_logic_vector(9 downto 0);
r_out : out STD_LOGIC_VECTOR (2 downto 0);
g_out : out STD_LOGIC_VECTOR (2 downto 0);
b_out : out STD_LOGIC_VECTOR (1 downto 0));
end rgb_conv;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture arq of rgb_conv is
begin
-- Proceso de conversion de rgb de 3 bits a rgb de 8 bits:
-----------------------------------------------------------
p_outputs: process(r, g, b, pos_h, pos_v)
begin
-- Si estamos fuera del rango del tablero pintaremos negro.
if pos_h >= "0010000000" and pos_h < "0100000000" and pos_v >= "0010000000" and pos_v < "0100000000" then
if r = '1' then
r_out <= "111";
else
r_out <= "000";
end if;
if g = '1' then
g_out <= "111";
else
g_out <= "000";
end if;
if b = '1' then
b_out <= "11";
else
b_out <= "00";
end if;
else
r_out <= (others => '0');
g_out <= (others => '0');
b_out <= (others => '0');
end if;
end process p_outputs;
end arq;
|
gpl-3.0
|
7c9c136c9ae05a86324d8f133c1f3c33
| 0.473576 | 4.254015 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/divider_core.vhd
| 1 | 2,671 |
------------------------------------------------------------------------------
-- Create/rivision Date: 07/19/09
-- Design Name: Tomasulo Execution Units
-- Module Name: DIVIDER_CORE
-- Author: Rahul Tekawade, Ketan Sharma, Gandhi Puvvada
------------------------------------------------------------------------------
-- This is a combinational divider, which is given multiple clocks to finish its operation.
-- Multiple Clock Cycle constraint is placed in the .ucf file for paths passing through it.
-- This divider_core is instanted by a divider wrapper.
-- The wrapper carries ROB Tag, etc and it takes care of selective flushing the on-going division if needed.
-- This is actually a 16-bit unsigned division. However, the inputs, Dividend and Divisor, are both 32 bits each.
-- The assumption is that the upper 16 bits of these 32 bit operands are always zeros..
-- The 16-bit remainder and the 16 bit quotient are concatenated into one 32-bit word (called Rem_n_Quo) and returned as output.
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- use IEEE.STD_LOGIC_UNSIGNED.ALL;
------------------------------------------------------------------------------
entity divider_core is
Port ( Dividend : in std_logic_vector (31 downto 0 );
Divisor : in std_logic_vector ( 31 downto 0);
Rem_n_Quo : out std_logic_vector ( 31 downto 0)
);
end divider_core;
------------------------------------------------------------------------------
architecture behv of divider_core is
--signal div_rem_n_quo : std_logic_vector(31 downto 0); --Mod by PRASANJEET 7/25/09
begin
division_combi: process ( Dividend, Divisor)
variable Dvd : std_logic_vector ( 31 downto 0); -- dividend
variable Dvr : std_logic_vector ( 31 downto 0); -- divisor
variable Quo : std_logic_vector ( 15 downto 0); -- quotient
variable Remain : std_logic_vector ( 15 downto 0); -- remainder
begin
Remain := (others => '0');
Dvd := Dividend ;
Dvr := Divisor ;
IF ( Dvr = X"00000000") THEN -- DIVIDE BY ZERO
Remain := X"FFFF";
Quo := X"FFFF";
ELSE
for i in 0 to 15 loop
Remain := Remain(14 downto 0) & Dvd(15 - i);
IF ( unsigned(Remain) >= unsigned(Dvr) ) THEN
Remain := unsigned(Remain) - unsigned(Dvr(15 downto 0));
Quo(15 - i) := '1';
ELSE
Quo(15 - i) := '0';
END IF;
end loop;
END IF;
--div_rem_n_quo <= --Mod by PRASANJEET 7/25/09
Rem_n_Quo <= Remain & Quo;
end process division_combi;
end behv;
|
gpl-2.0
|
59e56926ad397bdc2fdeacfea416da8b
| 0.5541 | 4.071646 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/echo.vhd
| 1 | 5,130 |
----------------------------------------------------------------------------------
-- Óñòðîéñòâî: ýõî ïåðåäàò÷èê. Äëÿ îòëàäêè
-- Êîä: 0x01
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity echo is
port (
-- receive
-- data_i: in std_logic_vector(7 downto 0); -- âõîäíîé áàéò
-- stb_i: in std_logic; -- ôëàã íàëè÷èÿ áàéòà íà âõîäå
-- ack_rec_o: out std_logic; -- ôëàã ðàçðåøåíèÿ ïðèåìà áàéòà
-- ready_receive_o: out std_logic; -- ôëàã ãîòîâíîñòè ïðèåìà
--
-- -- send
-- data_o: out std_logic_vector(7 downto 0); -- âûõîäíîé áàéò
-- stb_o: out std_logic; -- ôëàã íàëè÷èÿ áàéòà äëÿ ïåðåäà÷è
-- ack_send_i: in std_logic; -- ôëàã ðàçðåøåíèÿ ïåðåäà÷è
-- ready_send_o: out std_logic; -- ôëàã ãîòîâíîñòè ïåðåäà÷è
--
--
-- done_i: in std_logic; -- ôëàã çàâåðøåíèÿ ïðèåìà ïàêåòà
-- package_length_o: out std_logic_vector(15 downto 0); -- äëèíà âîçâðàùàåìîãî ïàêåòà äàííûõ
data_i: in std_logic_vector(7 downto 0); -- âõîäíîé áàéò
data_o: out std_logic_vector(7 downto 0); -- âûõîäíîé áàéò
read_i: in std_logic;
write_i: in std_logic;
length_o: out std_logic_vector(3 downto 0); -- äëèíà âîçâðàùàåìîãî ïàêåòà äàííûõ
full_o: out std_logic;
empty_o: out std_logic;
clk: in std_logic;
reset: in std_logic
);
end echo;
architecture Behavioral of echo is
-- òèï áóôôåðà äëÿ ïàêåòà äàííûõ
type bufer_type is array (0 to 15) of std_logic_vector(7 downto 0);
-- òèï ñîñòîÿíèé êîìïîíåíòà
-- type state_type is (
-- ready_rec,
-- receive_byte, -- ïðèåì áàéòà
-- middleware, -- ïðîìåæóòî÷íàÿ îáðàáîòêà
-- send_byte -- ïåðåäà÷à áàéòà
-- );
-- Òèï ñîñòîÿíèé äëÿ ïàðñåðà
signal buff : bufer_type:= (others => (others => '0'));
-- signal state: state_type := ready_rec;
-- signal is_first_byte_send: std_logic := '1';
signal tail, head, length: unsigned(3 downto 0) := (others => '0');
signal looped, empty, full: std_logic := '0';
-- signal strobe_prev: std_logic := '0';
begin
length_o <= std_logic_vector(length);
empty <= '1' when tail = head and looped /= '1' else '0';
full <= '1' when tail = head and looped = '1' else '0';
full_o <= full;
empty_o <= empty;
main_proc: process(clk, reset)
begin
if reset = '1' then
looped <= '0';
length <= "0000";
tail <= "0000";
head <= "0000";
elsif rising_edge(clk) then
if read_i = '1' and empty = '0' then
data_o <= buff(to_integer(tail));
length <= length - 1;
if tail = "1111" then
tail <= "0000";
looped <= '0';
else
tail <= tail + 1;
end if;
end if;
if write_i = '1' and full = '0' then
buff(to_integer(head)) <= data_i;
length <= length + 1;
if head = "1111" then
head <= "0000";
looped <= '1';
else
head <= head + 1;
end if;
end if;
end if;
end process;
--e 0
--f 0
--
--0 1 2 3 4 5 6 7 8 9
--H ^
--T ^
-- main_proc: process(clk)
-- variable ofs: integer := 0; -- natural
-- variable i: integer := 0; -- natural
-- begin
-- if rising_edge(clk) then
-- --
-- case state is
-- when ready_rec =>
-- ready_send_o <= '0';
-- ready_receive_o <= '1';
-- stb_o <= '0';
-- ack_rec_o <= '0';
-- -- åñëè åñòü áàéò íà âõîäå
-- if stb_i = '1' then
-- ready_receive_o <= '0';
-- state <= receive_byte;
-- end if;
-- -- ïðèåì ïàêåòà
-- when receive_byte =>
-- -- çàïèñûâàåì åãî â áóôôåð
-- buff(ofs) <= data_i;
-- -- óâåëè÷èâàåì ñìåùåíèå
-- ofs := ofs + 1;
-- -- åñëè ïàêåò ïðèíÿò ïîëíîñòüþ, ïåðåõîä ê ñëåäóþùåìó ñîñòîÿíèþ
-- if done_i = '1' then
-- state <= middleware;
-- ack_rec_o <= '0';
-- is_first_byte_send <= '1';
-- i := 0;
-- else
-- state <= ready_rec;
-- -- ñîîáùàåì î ïðèåìå áàéòà
-- ack_rec_o <= '1';
-- end if;
-- -- ïðîìåæóòî÷íàÿ îáðàáîòêà
-- when middleware =>
-- state <= send_byte;
-- ready_send_o <= '1';
-- -- ïåðåäà÷à ïàêåòà
-- when send_byte =>
-- -- åñëè ïàêåò ìîæíî ïåðåäàâàòü
-- if ack_send_i = '1' then
-- -- åñëè äàííûõ íåò
-- if i = ofs then
-- -- ïåðåõîäèì ê ïðèåìó ïàêåòà
-- state <= ready_rec;
-- ofs := 0;
-- stb_o <= '0';
-- else -- åñëè äàííûå åñòü
-- if is_first_byte_send = '1' then
-- -- ïåðåäàåì äëèíó
-- package_length_o <= std_logic_vector(to_unsigned(ofs, package_length_o'length));
-- is_first_byte_send <= '0';
-- else
-- -- ïåðåäàåì áàéò
-- data_o <= buff(i);
-- i := i + 1;
-- end if;
-- stb_o <= '1';
-- end if;
-- end if;
-- end case;
-- end if;
-- end process;
end Behavioral;
|
mit
|
f11c868971a5e5ce4a16f4bc60bbfabe
| 0.501754 | 2.911464 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/example_design/RAM_WRITE_top.vhd
| 1 | 5,383 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY RAM_WRITE_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END RAM_WRITE_top;
ARCHITECTURE xilinx OF RAM_WRITE_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT RAM_WRITE IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : RAM_WRITE
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
gpl-2.0
|
7b5c4a63f1292772aca4ac0223ae31a9
| 0.551365 | 4.56961 | false | false | false | false |
csrhau/sandpit
|
VHDL/dual_port_vram/ram.vhdl
| 1 | 945 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM is
port (
clock : in std_logic;
-- Port a has read and write
a_addr : in std_logic_vector(9 downto 0);
a_write : in std_logic;
a_din : in std_logic_vector(7 downto 0);
a_dout : out std_logic_vector(7 downto 0);
-- Port b is read only
b_addr : in std_logic_vector(9 downto 0);
b_dout : out std_logic_vector(7 downto 0)
);
end entity RAM;
architecture behavioural of RAM is
type memory is array(0 to 1023) of std_logic_vector(7 downto 0);
signal storage : memory := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
a_dout <= storage(to_integer(unsigned(a_addr)));
b_dout <= storage(to_integer(unsigned(b_addr)));
if a_write = '1' then
storage(to_integer(unsigned(a_addr))) <= a_din;
end if;
end if;
end process;
end behavioural;
|
mit
|
66c834b0ebc8eb6426570f1c1fa5e285
| 0.627513 | 3.160535 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_POST_FIFO/simulation/fg_tb_synth.vhd
| 1 | 11,229 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 8,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : RD_FLASH_POST_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
7188dcd5e03d047537629a3ffeddc9cb
| 0.455428 | 3.969247 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/example_design/RD_DATA_FIFO_top_wrapper.vhd
| 1 | 19,269 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RD_DATA_FIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RD_DATA_FIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(256-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(256-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end RD_DATA_FIFO_top_wrapper;
architecture xilinx of RD_DATA_FIFO_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component RD_DATA_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : RD_DATA_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
3873ed1347246d7279899d2e02253e44
| 0.484768 | 3.956674 | false | false | false | false |
lvoudour/arty-uart
|
src/uart_tx.vhd
| 1 | 3,793 |
--------------------------------------------------------------------------------
-- UART Tx module
--
-- 8 bit data, 1 stop bit, no parity. Intended for the Digilent Arty Artix-7
-- FPGA board, but can be easily used in other projects without modification.
--
-- Signals:
-- clk : clock of frequency G_CLOCK_FREQ
-- rst : active high synchronous reset
-- tx_out : Tx data line. Should be routed the Rx pin of the external
-- UART device.
-- tx_en_in : Set high for at least 1 clk cycle to initate data transfer.
-- Will be ignored if the module is busy (tx_ready_out low)
-- tx_data_in : 8 bit data to send
-- tx_ready_out : high = module is ready to transfer new data
-- low = module is currently busy and cannot accept new data
--
-- Parameters:
-- G_BAUD_RATE : UART baud rate
-- G_CLOCK_FREQ : clk frequency. Can be fractional
--
-- Not optimal for high clk rates/low baud rates, as the dividing counter can
-- become unnecessarily large.
--
-- Arty FPGA board specific notes:
-- The FT2232H chip does not support baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud
-- and 11 Mbaud.
-- http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf
--
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity uart_tx is
generic(
G_BAUD_RATE : positive := 1250000;
G_CLOCK_FREQ : real := 100.0e6
);
port(
clk : in std_logic;
rst : in std_logic;
tx_data_in : in std_logic_vector(7 downto 0);
tx_en_in : in std_logic;
tx_ready_out : out std_logic;
tx_out : out std_logic
);
end entity uart_tx;
architecture rtl of uart_tx is
constant C_CLK_DIVISOR : positive := positive(round(G_CLOCK_FREQ / real(G_BAUD_RATE)));
constant C_DIV_WIDTH : positive := positive(ceil(log2(real(C_CLK_DIVISOR))));
type fsm_tx_type is (
TX_IDLE,
TX_SHIFT_WORD
);
signal fsm_tx_state : fsm_tx_type := TX_IDLE;
signal cnt_div_r : unsigned(C_DIV_WIDTH-1 downto 0) := (others=>'0');
signal cnt_shift_r : unsigned(9 downto 0) := (others=>'0');
signal tx_data_sr : std_logic_vector(9 downto 0) := (others=>'0');
signal tx_ready_r : std_logic := '0';
signal tx_r : std_logic := '1';
begin
proc_fsm_tx:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
tx_r <= '1';
tx_ready_r <= '0';
fsm_tx_state <= TX_IDLE;
else
case fsm_tx_state is
when TX_IDLE =>
tx_r <= '1';
tx_ready_r <= '1';
cnt_shift_r <= (others=>'0');
cnt_div_r <= (others=>'0');
if (tx_en_in = '1') then
tx_ready_r <= '0';
tx_data_sr <= '1' & tx_data_in & '0';
fsm_tx_state <= TX_SHIFT_WORD;
end if;
when TX_SHIFT_WORD =>
tx_r <= tx_data_sr(0);
if (cnt_div_r = C_CLK_DIVISOR-1) then
cnt_div_r <= (others=>'0');
tx_data_sr <= '1' & tx_data_sr(9 downto 1);
if (cnt_shift_r = 9) then
fsm_tx_state <= TX_IDLE;
else
cnt_shift_r <= cnt_shift_r + 1;
end if;
else
cnt_div_r <= cnt_div_r + 1;
end if;
end case;
end if;
end if;
end process;
tx_ready_out <= tx_ready_r;
tx_out <= tx_r;
end architecture;
|
mit
|
3822491c5c0130d6e3d1a7bc1b9ee05e
| 0.518587 | 3.398746 | false | false | false | false |
PiJoules/Zybo-Vision-Processing
|
hdmi_passthrough_720p.srcs/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/sim/design_1_dvi2rgb_0_0.vhd
| 1 | 6,754 |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.4
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_dvi2rgb_0_0 IS
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC
);
END design_1_dvi2rgb_0_0;
ARCHITECTURE design_1_dvi2rgb_0_0_arch OF design_1_dvi2rgb_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dvi2rgb_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT dvi2rgb IS
GENERIC (
kEmulateDDC : BOOLEAN;
kRstActiveHigh : BOOLEAN;
kClkRange : INTEGER;
kIDLY_TapValuePs : INTEGER;
kIDLY_TapWidth : INTEGER
);
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
SerialClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END COMPONENT dvi2rgb;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N";
ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T";
BEGIN
U0 : dvi2rgb
GENERIC MAP (
kEmulateDDC => true,
kRstActiveHigh => true,
kClkRange => 2,
kIDLY_TapValuePs => 78,
kIDLY_TapWidth => 5
)
PORT MAP (
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
TMDS_Data_p => TMDS_Data_p,
TMDS_Data_n => TMDS_Data_n,
RefClk => RefClk,
aRst => aRst,
aRst_n => '1',
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => PixelClk,
aPixelClkLckd => aPixelClkLckd,
DDC_SDA_I => DDC_SDA_I,
DDC_SDA_O => DDC_SDA_O,
DDC_SDA_T => DDC_SDA_T,
DDC_SCL_I => DDC_SCL_I,
DDC_SCL_O => DDC_SCL_O,
DDC_SCL_T => DDC_SCL_T,
pRst => pRst,
pRst_n => '1'
);
END design_1_dvi2rgb_0_0_arch;
|
unlicense
|
b20e7c9d87e7266463905d7b785c642b
| 0.686112 | 3.477858 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_2/rob_frl_files/top_tb_withFRLComp_r1.vhd
| 1 | 8,154 |
-------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Reorder Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
library ee560;
use ee560.all;
-----------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_ROB of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden FRL)
signal Frl_RdPhyAddr_gold : std_logic_vector(5 downto 0);
signal Frl_Empty_gold : std_logic;
signal Frl_HeadPtr_gold : std_logic_vector(4 downto 0);
-- Signals for the student's DUT (FRL)
signal Resetb : std_logic;
signal Cdb_Flush : std_logic;
signal Rob_CommitPrePhyAddr : std_logic_vector(5 downto 0);
signal Rob_Commit : std_logic ;
signal Rob_CommitRegWrite : std_logic;
signal Cfc_FrlHeadPtr : std_logic_vector(4 downto 0) ;
signal Dis_FrlRead : std_logic ;
signal Frl_RdPhyAddr : std_logic_vector(5 downto 0);
signal Frl_Empty : std_logic;
signal Frl_HeadPtr : std_logic_vector(4 downto 0);
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
--digi_address : in std_logic_vector(5 downto 0); -- input ID for the register we want to see
--digi_data : out std_logic_vector(31 downto 0); -- output data given by the register
Clk : in std_logic;
-- signals corresponding to Instruction memory
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component Frl is
generic (WIDE : integer := 6;DEEP : integer:=16;PTRWIDTH:integer:=5);
port (
--Inputs
Clk : in std_logic;
Resetb : in std_logic;
Cdb_Flush : in std_logic ;
--Interface with Rob
Rob_CommitPrePhyAddr : in std_logic_vector(WIDE-1 downto 0) ;
Rob_Commit : in std_logic ;
Rob_CommitRegWrite : in std_logic;
Cfc_FrlHeadPtr: in std_logic_vector(PTRWIDTH-1 downto 0) ;
--Intreface with Dis_FrlRead unit
Frl_RdPhyAddr : out std_logic_vector(WIDE-1 downto 0) ;
Dis_FrlRead : in std_logic ;
Frl_Empty : out std_logic ;
--Interface with Previous Head Pointer Stack
Frl_HeadPtr : out std_logic_vector(PTRWIDTH-1 downto 0)
);
end component Frl;
------------------------------------------
for FRL_UUT: frl use entity work.frl(behav);
------------------------------------------
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
FRL_UUT: frl
port map (
Clk => Clk,
Resetb => Resetb,
Cdb_Flush => Cdb_Flush,
Rob_CommitPrePhyAddr => Rob_CommitPrePhyAddr,
Rob_Commit => Rob_Commit,
Rob_CommitRegWrite => Rob_CommitRegWrite,
Cfc_FrlHeadPtr => Cfc_FrlHeadPtr,
Frl_RdPhyAddr => Frl_RdPhyAddr,
Dis_FrlRead => Dis_FrlRead,
Frl_Empty => Frl_Empty,
Frl_HeadPtr => Frl_HeadPtr
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of FRL only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (Frl_RdPhyAddr_gold /= Frl_RdPhyAddr) then
write (my_outline, string'("ERROR! Frl_RdPhyAddr of TEST does not match Frl_RdPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Frl_Empty_gold /= Frl_Empty) then
write (my_outline, string'("ERROR! Frl_Empty of TEST does not match Frl_Empty_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Frl_HeadPtr_gold /= Frl_HeadPtr) then
write (my_outline, string'("ERROR! Frl_HeadPtr of TEST does not match Frl_HeadPtr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/Resetb","Resetb",0);
init_signal_spy("/UUT/Cdb_Flush","Cdb_Flush",1,1);
enable_signal_spy("/UUT/Cdb_Flush","Cdb_Flush",0);
init_signal_spy("/UUT/Rob_CommitPrePhyAddr","Rob_CommitPrePhyAddr",1,1);
enable_signal_spy("/UUT/Rob_CommitPrePhyAddr","Rob_CommitPrePhyAddr",0);
init_signal_spy("/UUT/Rob_Commit","Rob_Commit",1,1);
enable_signal_spy("/UUT/Rob_Commit","Rob_Commit",0);
init_signal_spy("/UUT/Rob_CommitRegWrite","Rob_CommitRegWrite",1,1);
enable_signal_spy("/UUT/Rob_CommitRegWrite","Rob_CommitRegWrite",0);
init_signal_spy("/UUT/Cfc_FrlHeadPtr","Cfc_FrlHeadPtr",1,1);
enable_signal_spy("/UUT/Cfc_FrlHeadPtr","Cfc_FrlHeadPtr",0);
init_signal_spy("/UUT/Dis_FrlRead","Dis_FrlRead",1,1);
enable_signal_spy("/UUT/Dis_FrlRead","Dis_FrlRead",0);
--outputs--
init_signal_spy("/UUT/Frl_RdPhyAddr","Frl_RdPhyAddr_gold",1,1);
enable_signal_spy("/UUT/Frl_RdPhyAddr","Frl_RdPhyAddr_gold",0);
init_signal_spy("/UUT/Frl_Empty","Frl_Empty_gold",1,1);
enable_signal_spy("/UUT/Frl_Empty","Frl_Empty_gold",0);
init_signal_spy("/UUT/Frl_HeadPtr","Frl_HeadPtr_gold",1,1);
enable_signal_spy("/UUT/Frl_HeadPtr","Frl_HeadPtr_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_ROB;
|
gpl-2.0
|
ad6acbaa5fda53c15f1d763083f1db39
| 0.628158 | 3.114591 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_PRE_FIFO/simulation/fg_tb_synth.vhd
| 1 | 11,227 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : WR_FLASH_PRE_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
f43111d550e55657d3ee149e6f28ada1
| 0.455331 | 3.96854 | false | false | false | false |
gxliu/ARM-Cortex-M0
|
hdl/badd32.vhd
| 1 | 2,465 |
library ieee;
use ieee.std_logic_1164.all;
entity badd32 is
port ( a : in std_logic_vector(2 downto 0); -- Booth multiplier
b : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sum input
sum_out : out std_logic_vector(31 downto 0); -- sum output
prod : out std_logic_vector(1 downto 0)); -- 2 bits of product
end entity badd32;
architecture Behavioral of badd32 is
-- Note: Most of the multiply algorithm is performed in here.
-- multiplier action
-- a bb
-- i+1 i i-1 multiplier, shift partial result two places each stage
-- 0 0 0 0 pass along
-- 0 0 1 +b add
-- 0 1 0 +b add
-- 0 1 1 +2b shift add
-- 1 0 0 -2b shift subtract
-- 1 0 1 -b subtract
-- 1 1 0 -b subtract
-- 1 1 1 0 pass along
component add32
port ( a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in std_logic;
sum : out std_logic_vector(31 downto 0);
cout : out std_logic);
end component add32;
component fadd
port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end component fadd;
subtype word is std_logic_vector(31 downto 0);
signal bb : word;
signal psum : word;
signal b_bar : word;
signal two_b : word;
signal two_b_bar : word;
signal cout : std_logic;
signal cin : std_logic;
signal topbit : std_logic;
signal topout : std_logic;
signal nc1 : std_logic;
begin
b_bar <= not b;
two_b <= b(30 downto 0) & '0';
two_b_bar <= not two_b;
bb <= b when a="001" or a="010" -- 5-input mux
else two_b when a="011"
else two_b_bar when a="100" -- cin=1
else b_bar when a="101" or a="110" -- cin=1
else x"00000000";
cin <= '1' when a="100" or a="101" or a="110"
else '0';
topbit <= b(31) when a="001" or a="010" or a="011"
else b_bar(31) when a="100" or a="101" or a="110"
else '0';
a1: add32 port map(sum_in, bb, cin, psum, cout);
a2: fadd port map(sum_in(31), topbit, cout, topout, nc1);
sum_out(29 downto 0) <= psum(31 downto 2);
sum_out(31) <= topout;
sum_out(30) <= topout;
prod <= psum(1 downto 0);
end Behavioral;
|
mit
|
f13d1bf74542649c1ec7df65c1072f50
| 0.544828 | 3.03198 | false | false | false | false |
tuura/fantasi
|
dependencies/shift-register-input.vhdl
| 1 | 1,792 |
-- Generic size shift register with the input synchronised just once
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_shift_register_input IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
START : IN std_logic;
DIN : IN std_logic;
DOUT : OUT std_logic_vector(N-1 downto 0));
END Generic_shift_register_input;
ARCHITECTURE structural OF Generic_shift_register_input IS
COMPONENT SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic);
END COMPONENT;
COMPONENT ffd is
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic
);
end COMPONENT;
SIGNAL data : std_logic_vector(N downto 0);
SIGNAL sync_data : std_logic;
SIGNAL sync_en : std_logic;
BEGIN
SYNC_D : SYNC_LATCH PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
DIN => DIN,
DOUT => sync_data);
SYNC_E : SYNC_LATCH PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
DIN => START,
DOUT => sync_en);
REG_GENERATOR : for i in 0 to N-1 generate
FFD_I : ffd PORT MAP (
CLK => CLK,
RST => RST,
EN => sync_en,
D => data(i),
Q => data(i+1));
DOUT(i) <= data(i+1);
END GENERATE;
data(0) <= sync_data;
END structural;
|
mit
|
7ba890504e9dab2a8e912352c01cc5c3
| 0.481027 | 3.446154 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Move_FIFO_4KB/simulation/fg_tb_pkg.vhd
| 1 | 11,384 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT Move_FIFO_4KB_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
ff5acd0ddae61a0f2a2a25d5f9dd411e
| 0.502723 | 3.922812 | false | false | false | false |
csrhau/sandpit
|
VHDL/flexible_single_port_ram/test_file_ram.vhdl
| 1 | 1,843 |
library ieee;
use ieee.std_logic_1164.all;
entity test_file_RAM is
end test_file_RAM;
architecture behavioural of test_file_RAM is
component file_RAM is
generic (
filename: string
);
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector
);
end component file_RAM;
signal write_enable : std_logic;
signal address : std_logic_vector(9 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
signal period: time := 10 ns;
signal clock : std_logic := '0';
signal finished : std_logic := '0';
begin
clock <= not clock after period/2 when finished='0';
memory : file_RAM generic map (filename => "ram_1024.mif")
port map (clock, write_enable, address, data_in, data_out);
process
begin
address <= "0000000000";
write_enable <= '1';
data_in <= "01010101";
wait for period;
assert data_out = "00000000"
report "file_RAM should start at zero" severity error;
address <= "0000000000";
write_enable <= '1';
data_in <= "01010101";
wait for period;
assert data_out = "01010101"
report "file_RAM should store values" severity error;
address <= "0000000001";
wait for period;
assert data_out = "00000001"
report "data should be sequential in ram" severity error;
address <= "0000000010";
wait for period;
assert data_out = "00000010"
report "data should be sequential in ram" severity error;
address <= "0000010010";
wait for period;
assert data_out = "00010010"
report "data should be sequential in ram" severity error;
finished <= '1';
wait;
end process;
end behavioural;
|
mit
|
b73aca4e5604df3177dbe2129eddddf4
| 0.634835 | 3.792181 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/gc_command_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,378 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT gc_command_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
6af2f3c060c9a52613bab593590589db
| 0.503603 | 3.934302 | false | false | false | false |
BBN-Q/APS2-TDM
|
src/status_leds.vhd
| 1 | 7,727 |
-- Drive front-panel LED status indicators
--
---- Comms is top LED(3 downto 2):
-- No connection - dark
-- Idle connection - heartbeat green
-- Packet recieved or sent - flash green
-- Error in Ethernet DMA - red
--
-- SATA connections are bottom LED(1 downto 0)
-- Idle - dark
-- Valid recevied - flash green
-- Original author: Colm Ryan
-- Copyright 2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity status_leds is
port (
clk : in std_logic;
rst : in std_logic;
link_established : in std_logic;
comms_active : in std_logic;
comms_error : in std_logic;
inputs_latched : in std_logic;
trigger_enabled : in std_logic;
leds : out std_logic_vector(3 downto 0)
);
end entity;
architecture behavioral of status_leds is
-- LED output: drive "10" for RED and "01" for GREEN.
constant RED : std_logic_vector(1 downto 0) := "10";
constant GREEN : std_logic_vector(1 downto 0) := "01";
constant DARK : std_logic_vector(1 downto 0) := "00";
--Clock frequencies
constant CLK_FREQ : natural := 100_000_000; --Assume clocked off AXI clock at 100MHz
constant PWM_FREQ : natural := 256_000; -- modulate the LED at 1kHz
constant HEARTBEAT_FREQ : natural := 256/4; -- step through the heart beat in 4 seconds
signal enablePWM, enableHB : boolean := false;
signal hbGreen : std_logic_vector(1 downto 0);
signal comms_led, trigger_led : std_logic_vector(1 downto 0) := DARK;
--status signals synced to module clock
signal link_established_int, comms_active_int, comms_error_int : std_logic;
signal khz_enable : boolean := false;
constant KHZ_COUNT : natural := CLK_FREQ/1000;
-- Sinusoidal modulation of LED dimming.
-- Actually 1 - abs(sin(x)) for x in 0 to pi
-- May need correction for eye non-linearity
type byteArray is array (integer range <>) of unsigned(7 downto 0) ;
constant sineData : byteArray(0 to 255) := (
x"ff", x"fc", x"f9", x"f6", x"f2", x"ef", x"ec", x"e9", x"e6", x"e3",
x"e0", x"dd", x"d9", x"d6", x"d3", x"d0", x"cd", x"ca", x"c7", x"c4",
x"c1", x"be", x"bb", x"b8", x"b5", x"b2", x"af", x"ac", x"a9", x"a6",
x"a3", x"a0", x"9d", x"9a", x"97", x"94", x"92", x"8f", x"8c", x"89",
x"86", x"84", x"81", x"7e", x"7b", x"79", x"76", x"73", x"71", x"6e",
x"6c", x"69", x"67", x"64", x"62", x"5f", x"5d", x"5a", x"58", x"56",
x"53", x"51", x"4f", x"4c", x"4a", x"48", x"46", x"44", x"41", x"3f",
x"3d", x"3b", x"39", x"37", x"35", x"34", x"32", x"30", x"2e", x"2c",
x"2a", x"29", x"27", x"25", x"24", x"22", x"21", x"1f", x"1e", x"1c",
x"1b", x"19", x"18", x"17", x"15", x"14", x"13", x"12", x"11", x"10",
x"0e", x"0d", x"0c", x"0c", x"0b", x"0a", x"09", x"08", x"07", x"07",
x"06", x"05", x"05", x"04", x"04", x"03", x"03", x"02", x"02", x"01",
x"01", x"01", x"01", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"01", x"01", x"01", x"01", x"02", x"02", x"03",
x"03", x"04", x"04", x"05", x"05", x"06", x"07", x"07", x"08", x"09",
x"0a", x"0b", x"0c", x"0c", x"0d", x"0e", x"10", x"11", x"12", x"13",
x"14", x"15", x"17", x"18", x"19", x"1b", x"1c", x"1e", x"1f", x"21",
x"22", x"24", x"25", x"27", x"29", x"2a", x"2c", x"2e", x"30", x"32",
x"34", x"35", x"37", x"39", x"3b", x"3d", x"3f", x"41", x"44", x"46",
x"48", x"4a", x"4c", x"4f", x"51", x"53", x"56", x"58", x"5a", x"5d",
x"5f", x"62", x"64", x"67", x"69", x"6c", x"6e", x"71", x"73", x"76",
x"79", x"7b", x"7e", x"81", x"84", x"86", x"89", x"8c", x"8f", x"92",
x"94", x"97", x"9a", x"9d", x"a0", x"a3", x"a6", x"a9", x"ac", x"af",
x"b2", x"b5", x"b8", x"bb", x"be", x"c1", x"c4", x"c7", x"ca", x"cd",
x"d0", x"d3", x"d6", x"d9", x"dd", x"e0", x"e3", x"e6", x"e9", x"ec",
x"ef", x"f2", x"f6", x"f9", x"fc", x"ff");
begin
leds(1 downto 0) <= comms_led;
leds(3 downto 2) <= trigger_led;
--Divide down the AXI clock to something on the human timescale
enableGenerator : process( clk )
variable ctPWM, ctHB : natural;
begin
if rising_edge(clk) then
if rst = '1' then
enablePWM <= false;
enableHB <= false;
ctPWM := 0;
ctHB := 0;
else
enablePWM <= false;
enableHB <= false;
ctPWM := ctPWM + 1;
ctHB := ctHB + 1;
if ctPWM = CLK_FREQ/PWM_FREQ then
enablePWM <= true;
ctPWM := 0;
end if;
if ctHB = CLK_FREQ/HEARTBEAT_FREQ then
enableHB <= true;
ctHB := 0;
end if;
end if;
end if ;
end process ; -- enableGenerator
heart_beat_pro : process( clk )
variable ctHB, ctPWM : unsigned(7 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
ctPWM := (others => '0');
ctHB := (others => '0');
hbGreen <= DARK;
else
if enableHB then
ctHB := ctHB + 1;
end if;
--Drive a green version
if enablePWM then
ctPWM := ctPWM + 1;
if ctPWM <= sineData(to_integer(ctHB)) then
hbGreen <= GREEN;
else
hbGreen <= DARK;
end if;
end if;
end if ;
end if ;
end process ; -- heart_beat_pro
--Divide clock down to 1kHz for blinking counts
khz_enable_pro : process(clk)
variable ct : natural range 0 to KHZ_COUNT := 0;
begin
if rising_edge(clk) then
if rst = '1' then
ct := 0;
khz_enable <= false;
else
if ct = KHZ_COUNT then
ct := 0;
khz_enable <= true;
else
ct := ct + 1;
khz_enable <= false;
end if;
end if;
end if;
end process;
--Synchronize comms signals
sync_link_established: entity work.synchronizer
port map ( rst => rst, clk => clk, data_in => link_established, data_out => link_established_int);
sync_comms_active: entity work.synchronizer
port map ( rst => rst, clk => clk, data_in => comms_active, data_out => comms_active_int);
sync_comms_error: entity work.synchronizer
port map ( rst => rst, clk => clk, data_in => comms_error, data_out => comms_error_int);
--Comms logic
commsLogic : process( clk )
type state_t is (IDLE, BLINK_DARK, BLINK_GREEN);
variable state : state_t := IDLE;
variable blink_ct : natural range 0 to 1000;
begin
if rising_edge(clk) then
--No connection heart beat
if link_established_int = '0' then
comms_led <= hbGreen;
state := IDLE;
elsif comms_error_int = '1' then
comms_led <= RED;
state := IDLE;
else
case( state ) is
when IDLE =>
comms_led <= GREEN;
blink_ct := 0;
--catch packet transmission
if comms_active_int = '1' then
state := BLINK_DARK;
end if;
when BLINK_DARK =>
comms_led <= DARK;
if blink_ct = 50 then
blink_ct := 0;
state := BLINK_GREEN;
elsif khz_enable then
blink_ct := blink_ct + 1;
end if;
when BLINK_GREEN =>
comms_led <= GREEN;
if blink_ct = 50 then
blink_ct := 0;
state := IDLE;
elsif khz_enable then
blink_ct := blink_ct + 1;
end if;
end case ;
end if ;
end if ;
end process ; -- commsLogic
trigger_logic : process(clk)
type state_t is (IDLE, BLINK_DARK, BLINK_GREEN);
variable state : state_t := IDLE;
variable idle_led : std_logic_vector(1 downto 0) := b"00";
variable blink_ct : natural range 0 to 1000;
begin
if rising_edge(clk) then
if trigger_enabled = '1' then
idle_led := GREEN;
else
idle_led := DARK;
end if;
case( state ) is
when IDLE =>
trigger_led <= idle_led;
if inputs_latched = '1' then
state := BLINK_DARK;
end if;
when BLINK_DARK =>
trigger_led <= DARK;
if blink_ct = 50 then
blink_ct := 0;
state := BLINK_GREEN;
elsif khz_enable then
blink_ct := blink_ct + 1;
end if;
when BLINK_GREEN =>
trigger_led <= GREEN;
if blink_ct = 50 then
blink_ct := 0;
state := IDLE;
elsif khz_enable then
blink_ct := blink_ct + 1;
end if;
end case;
end if;
end process;
end architecture;
|
mpl-2.0
|
e6a60bfe30a78281757ffd11528e9ef9
| 0.583279 | 2.494995 | false | false | false | false |
csrhau/sandpit
|
VHDL/stencil_buffer/test_ring_buffer.vhdl
| 1 | 1,539 |
library ieee;
use ieee.std_logic_1164.all;
entity test_ring_buffer is
end test_ring_buffer;
architecture behavioural of test_ring_buffer is
component ring_buffer is
port (
clock : in std_logic;
advance: in std_logic;
address: in std_logic_vector;
input : in std_logic_vector;
output : out std_logic_vector
);
end component ring_buffer;
signal clock : std_logic := '0';
signal finished : std_logic := '0';
signal advance : std_logic := '0';
signal input : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
signal address : std_logic_vector (2 downto 0) := "000"; -- 8 places
signal period: time := 10 ns;
begin
clock <= not clock after period/2 when finished='0';
BUFF: ring_buffer port map (clock, advance, address, input, output);
process
begin
-- Fill test
input <= "11001100";
advance <= '1';
wait for period;
advance <= '0';
address <= "000";
wait for period;
assert output = "11001100"
report "Ripple buffer should be content addressable" severity error;
address <= "001";
wait for period;
assert output = "00000000"
report "Only the first element should be written" severity error;
advance <= '1';
wait for period;
advance <= '0';
address <= "001";
wait for period;
assert output = "11001100"
report "The queue should now advance by one" severity error;
wait for 10 * period;
finished <= '1';
wait;
end process;
end behavioural;
|
mit
|
55120f8303835be92035a06b97021a9e
| 0.636777 | 3.828358 | false | true | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_FIFO/simulation/fg_tb_synth.vhd
| 1 | 11,228 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : WR_FLASH_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
05926885ace00f70a8003bf94b5d0715
| 0.455914 | 3.96329 | false | false | false | false |
corneydavid/HT_FPGA
|
Exercises/Demonstrations/Creating CLIP/PllClip.vhd
| 1 | 5,084 |
Library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.numeric_std.all;
library UNISIM; -- include this library and use statement to ensure that the PLL component can be found by the Xilinx compiler.
use UNISIM.Vcomponents.ALL;
entity PllClip is
port(
-- Asynchronous reset signal from the LabVIEW FPGA environment.
aReset : in std_logic; -- this signal will be used to reset the PLL
-- LabVIEW FPGA I/O
-- PLL I/O
CLKIN1_IN : in std_logic; -- reference clock input from the LVFPGA diagram
LOCKED_OUT : out std_logic; -- indicate to the LVFPGA diagram that the PLL has locked to the reference clock
CLKOUT0_OUT : out std_logic --PLL clock output to the LVFPGA diagram
);
end PllClip;
architecture behavioral of PllClip is
-- Internal clock signals
signal UserGClk0 : std_logic; -- this internal signal will be used to route the PLL output clock back to LVFPGA and out a GPIO line
signal ClkOut0Ddr: std_logic; -- output of DDR routed to GPIO line
-- PLL Internal Signals
signal CLKFBOUT_CLKFBIN : std_logic; -- internal feedback signal for PLL
signal CLKOUT0_BUF : std_logic; -- signal routed to global clock buffer from PLL
-- Internal signals created by core generator and are used to configure the PLL
signal GND_BIT : std_logic;
signal GND_BUS_5 : std_logic_vector (4 downto 0);
signal GND_BUS_16 : std_logic_vector (15 downto 0);
signal VCC_BIT : std_logic;
-- Reset signals
signal rDelayRstReg : std_logic_vector(15 downto 0) := x"ffff";
signal rDelayGo, rDelayGo_ms : boolean := false;
begin
---------------------------
-- Reset logic
---------------------------
--Double sync to come out of reset safely. This relies on the
--default condition of the registers
PllGoSync: process (CLKIN1_IN)
begin
if(rising_edge(CLKIN1_IN)) then
rDelayGo_ms <= true;
rDelayGo <= rDelayGo_ms;
end if;
end process;
-- IODELAYCTRL must be held in reset for several clock cycles (50 ns)
IoDelayReset: process (aReset, CLKIN1_IN)
begin
if(rising_edge(CLKIN1_IN)) then
if(rDelayGo) then
rDelayRstReg <= '0' & rDelayRstReg(rDelayRstReg'left downto 1);
end if;
end if;
end process;
-- Assign bit values to the internal signals
GND_BIT <= '0';
GND_BUS_5(4 downto 0) <= "00000";
GND_BUS_16(15 downto 0) <= "0000000000000000";
VCC_BIT <= '1';
-- Instantiate the PLL for LabVIEW FPGA
-- The formatting has been modified but the instantiation is identical to the code component created by core generator.
PLL_ADV_INST : PLL_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => 25.000, -- input clock period of 40 MHz
CLKIN2_PERIOD => 10.000,
CLKOUT0_DIVIDE => 7, -- output clock divide value O
CLKOUT1_DIVIDE => 8,
CLKOUT2_DIVIDE => 8,
CLKOUT3_DIVIDE => 8,
CLKOUT4_DIVIDE => 8,
CLKOUT5_DIVIDE => 8,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500, -- output clock duty cycle
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- output clock D value
CLKFBOUT_MULT => 13, -- output clock M value
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.000000)
port map (
CLKFBIN => CLKFBOUT_CLKFBIN, -- route the feedback signal in
CLKINSEL => VCC_BIT,
CLKIN1 => CLKIN1_IN,
CLKIN2 => GND_BIT,
DADDR(4 downto 0) => GND_BUS_5(4 downto 0),
DCLK => GND_BIT,
DEN => GND_BIT,
DI(15 downto 0) => GND_BUS_16(15 downto 0),
DWE => GND_BIT,
REL => GND_BIT,
RST => rDelayRstReg(0), -- attach LVFPGA diagram reset to PLL; a more robust reset design will be required for shipping designs
CLKFBDCM => open,
CLKFBOUT => CLKFBOUT_CLKFBIN,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => CLKOUT0_BUF,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => LOCKED_OUT);
CLKOUT0_BUFG_INST : BUFG -- route the output clock from the PLL to a global clock buffer
port map (
I=> CLKOUT0_BUF,
O=> CLKOUT0_OUT);
end behavioral;
|
apache-2.0
|
00243e5e6fa729a64f46b3b97b6b33a4
| 0.576908 | 3.910769 | false | false | false | false |
csrhau/sandpit
|
VHDL/flexible_single_port_ram/ram.vhdl
| 1 | 749 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RAM is
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector
);
end entity RAM;
architecture behavioural of RAM is
type memory is array(integer range 0 to (2**address'length-1)) of std_logic_vector(data_in'range);
signal storage : memory := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
data_out <= storage(to_integer(unsigned(address)));
if write_enable = '1' then
storage(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
end behavioural;
|
mit
|
10ffba11bd811dad3ed520731fe7b4a4
| 0.655541 | 3.38914 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/write_data_fifo/example_design/write_data_fifo_top.vhd
| 2 | 5,652 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: write_data_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity write_data_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end write_data_fifo_top;
architecture xilinx of write_data_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component write_data_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : write_data_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
f29acc23d8b144a632422c6ce9c1405e
| 0.511854 | 4.663366 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_PRE_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,390 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT WR_FLASH_PRE_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
cd70c2f86b537f60d51aaae9b65e6d43
| 0.502897 | 3.923527 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_3/complete/Cfc_withBRAM.vhd
| 1 | 21,111 |
-------------------------------------------------------------------------------
--
-- Design : CFC Unit
-- Project : Tomasulo Processor
-- Entity : CFC
-- Author : Rajat Shah
-- Company : University of Southern California
-- Last Updated : April 15th, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cfc is
port ( --global signals
Clk :in std_logic; --Global Clock Signal
Resetb :in std_logic; --Global Reset Signal
--interface with dispatch unit
Dis_InstValid :in std_logic; --Flag indicating if the instruction dispatched is valid or not
Dis_CfcBranchTag :in std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
Dis_CfcRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address
Dis_CfcRsAddr :in std_logic_vector(4 downto 0); --Rs Logical Address
Dis_CfcRtAddr :in std_logic_vector(4 downto 0); --Rt Logical Address
Dis_CfcNewRdPhyAddr :in std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
Dis_CfcRegWrite :in std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
Dis_CfcBranch :in std_logic; --Flag indicating whether current instruction being dispatched is branch or not
Dis_Jr31Inst :in std_logic; --Flag indicating if the current instruction is Jr 31 or not
Cfc_RdPhyAddr :out std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
Cfc_RsPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
Cfc_RtPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
Cfc_Full :out std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
Rob_TopPtr :in std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
Rob_Commit :in std_logic; --Flag indicating whether instruction is committing in this cycle or not
Rob_CommitRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
Rob_CommitRegWrite :in std_logic; --Indicates if instruction is writing to register or not
Rob_CommitCurrPhyAddr :in std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag :out std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
Frl_HeadPtr :in std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
Cfc_FrlHeadPtr :out std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cdb_RobTag :in std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
Cdb_RobDepth :in std_logic_vector(4 downto 0) --Depth of mispredicted branch from ROB Top
);
end cfc;
architecture cfc_arch of cfc is
--Signal declaration for 8 copies of checkpoints - Each 32 deep and 6 bit wide
type cfc_checkpoint_type is array(0 to 255) of std_logic_vector(5 downto 0);
signal Cfc_RsList, Cfc_RtList, Cfc_RdList : cfc_checkpoint_type; --3 BRAM, each containing flattened 8 tables
--Signal declaration for committed checkpoint (Retirement RAT) - 32 deep and 6 bit wide
type committed_type is array(0 to 31) of std_logic_vector(5 downto 0);
signal Committed_RsList, Committed_RtList, Committed_RdList : committed_type :=(
"000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111"); -- 3 copies of committed list initialize to 0 to 31
--Signal declaration for 8 copies of Dirty Flag Array(DFA) validating each checkpoints - Each 32 deep and 1 bit wide
type dfa_checkpoint_type is array(0 to 31) of std_logic;
type dfa_array_type is array (0 to 7) of dfa_checkpoint_type;
signal Dfa_List : dfa_array_type;
type checkpoint_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Checkpoint_TagArray: checkpoint_tag_type; --8 deep and 5 bit wide array for storing ROB tag of checkpointed branch instructions
type Frl_HeadPtrArray_type is array (0 to 7) of std_logic_vector (4 downto 0);
signal Frl_HeadPtrArray: Frl_HeadPtrArray_type;
type depth_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Depth_Array: depth_tag_type;
type Cfc_Valid_Array_type is array (0 to 7) of std_logic;
signal Cfc_ValidArray: Cfc_Valid_Array_type;
signal Full, Empty : std_logic; --flag indicating if all 8 checkpoints are used or empty
signal Head_Pointer, Tail_Pointer: std_logic_vector(2 downto 0); --Head Pointer indicates active checkpoint while tail pointer indicates oldest uncommitted branch
signal Checkpoint_MatchArray: std_logic_vector (7 downto 0); --Array indicating if the instruction on CDB matches any checkpointed branch
signal DFA_RsValid, DFA_RtValid, DFA_RdValid: std_logic;
signal Cfc_RsList_temp, Cfc_RtList_temp, Cfc_RdList_temp: std_logic_vector (5 downto 0);
signal Committed_RsList_temp, Committed_RtList_temp, Committed_RdList_temp: std_logic_vector (5 downto 0);
signal Next_Head_Pointer: std_logic_vector (2 downto 0); --Temporary Head_pointer generated during CDB Flush
begin
Depth_Array(0) <= Checkpoint_TagArray(0) - Rob_TopPtr; -- std_logic_vector is treated as unsigned because of library declaration IEEE_STD_LOGIC_UNSIGNED
Depth_Array(1) <= Checkpoint_TagArray(1) - Rob_TopPtr;
Depth_Array(2) <= Checkpoint_TagArray(2) - Rob_TopPtr;
Depth_Array(3) <= Checkpoint_TagArray(3) - Rob_TopPtr;
Depth_Array(4) <= Checkpoint_TagArray(4) - Rob_TopPtr;
Depth_Array(5) <= Checkpoint_TagArray(5) - Rob_TopPtr;
Depth_Array(6) <= Checkpoint_TagArray(6) - Rob_TopPtr;
Depth_Array(7) <= Checkpoint_TagArray(7) - Rob_TopPtr;
--Combinational assignment determining if the instruction on CDB is a frozen branch or not
Checkpoint_MatchArray(0) <= '1' when ((Checkpoint_TagArray(0) = Cdb_RobTag) and (Cfc_ValidArray(0) = '1')) else
'0';
Checkpoint_MatchArray(1) <= '1' when ((Checkpoint_TagArray(1) = Cdb_RobTag) and (Cfc_ValidArray(1) = '1')) else
'0';
Checkpoint_MatchArray(2) <= '1' when ((Checkpoint_TagArray(2) = Cdb_RobTag) and (Cfc_ValidArray(2) = '1')) else
'0';
Checkpoint_MatchArray(3) <= '1' when ((Checkpoint_TagArray(3) = Cdb_RobTag) and (Cfc_ValidArray(3) = '1')) else
'0';
Checkpoint_MatchArray(4) <= '1' when ((Checkpoint_TagArray(4) = Cdb_RobTag) and (Cfc_ValidArray(4) = '1')) else
'0';
Checkpoint_MatchArray(5) <= '1' when ((Checkpoint_TagArray(5) = Cdb_RobTag) and (Cfc_ValidArray(5) = '1')) else
'0';
Checkpoint_MatchArray(6) <= '1' when ((Checkpoint_TagArray(6) = Cdb_RobTag) and (Cfc_ValidArray(6) = '1')) else
'0';
Checkpoint_MatchArray(7) <= '1' when ((Checkpoint_TagArray(7) = Cdb_RobTag) and (Cfc_ValidArray(7) = '1')) else
'0';
Cfc_Full <= Full;
--Task 0: Complete the Full and empty conditions depending on the Head_Pointer and Tail_pointer values
Full <= '1' when (unsigned(Tail_Pointer-Head_Pointer)=1) else '0';
Empty <= '1' when (Head_Pointer = Tail_Pointer) else '0'; --Flag indicating that there is no frozen checkpoint
Cfc_FrlHeadPtr <= Frl_HeadPtrArray(conv_integer(Next_Head_Pointer));
Cfc_RobTag <= Checkpoint_Tagarray(conv_integer(Next_Head_Pointer));
CfcUpdate: process (Clk, Resetb)
begin
if(Resetb = '0') then
Head_Pointer <= "000"; --Here the Head_Pointer points to the active checkpoint and not to the empty location
Tail_Pointer <= "000";
for I in 0 to 7 loop
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
Cfc_ValidArray(I) <= '0';
end loop;
elsif (Clk'event and Clk = '1') then
--Releasing the oldest checkpoint if the branch reaches top of ROB
if ((Rob_Commit = '1') and (Rob_TopPtr = Checkpoint_TagArray(conv_integer(Tail_Pointer))) and ((Tail_Pointer - Next_Head_Pointer) /= "00")) then
Tail_Pointer <= Tail_Pointer + '1';
Cfc_ValidArray(conv_integer(Tail_Pointer)) <= '0';
for I in 0 to 31 loop
Dfa_List(conv_integer(Tail_Pointer))(I) <= '0';
end loop;
end if;
if (Cdb_Flush = '1') then
---- ADDED BY MANPREET--- need to invalidate the active rat dfa bits
for J in 0 to 31 loop
Dfa_List(conv_integer(Head_Pointer))(J) <= '0';
end loop;
-----------------------------
for I in 0 to 7 loop
-- changed by Manpreet.. shouldnt invalidate the rat corresponding to branch_tag = cdb_robtag as
-- it contains instructions before the flushed branch and will become the active rat
if (Cdb_RobDepth < Depth_Array(I)) then --Invalidating all the younger checkpoints and clearing the Dfa_List
Cfc_ValidArray(I)<='0';
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
end if;
if (Cdb_RobDepth = Depth_Array(I)) then
Cfc_ValidArray(I)<='0';
end if ;
end loop;
Head_Pointer <= Next_Head_Pointer;
else
-- Task 1: Update the DFA bit of the Active Checkpoint on dispatch of Register Writing Instruction
if (Dis_InstValid='1' and Dis_CfcRegWrite='1') then
Dfa_List(conv_integer(Head_Pointer)) (conv_integer(Dis_CfcRdAddr)) <= '1';
end if;
-- Task 2: Create a new checkpoint for dispatched branch (i.e. freeze the active checkpoint)
if ((Dis_CfcBranch = '1' or Dis_Jr31Inst = '1')and Dis_InstValid = '1' and ((Full /= '1') or ((Rob_Commit = '1') and (Full = '1') ))) then -- Task 2.1 - some conditions missing - think structural hazard - can't dispatch branch if all checkpoints are in use. But what if a branch is committing as well?
Checkpoint_TagArray (conv_integer(Head_Pointer)) <= Dis_CfcBranchTag;
Cfc_ValidArray (conv_integer(Head_Pointer)) <= '1';
Frl_HeadPtrArray(conv_integer(Head_Pointer)) <= Frl_HeadPtr;
Head_Pointer <= Head_Pointer + 1;
-- Task 2.2 - what things need to be done for a new checkpoint? Tagarray, validarray, FRL headpointer and the headpointer should be updated.
end if;
end if;
end if;
end process;
--Combinational Process to determine new head pointer during branch misprediction
CDB_Flush_Process: process (Cdb_Flush, Checkpoint_MatchArray, Frl_HeadPtrArray, Checkpoint_TagArray, Head_Pointer)
begin
Next_Head_Pointer <= Head_Pointer;
if (Cdb_Flush = '1') then
Case Checkpoint_MatchArray is --Case statement to move the head pointer on branch misprediction to corresponding frozen checkpoint
when "00000001" =>
Next_Head_Pointer <= "000";
when "00000010" =>
Next_Head_Pointer <= "001";
when "00000100" =>
Next_Head_Pointer <= "010";
when "00001000" =>
Next_Head_Pointer <= "011";
when "00010000" =>
Next_Head_Pointer <= "100";
when "00100000" =>
Next_Head_Pointer <= "101";
when "01000000" =>
Next_Head_Pointer <= "110";
when "10000000" =>
Next_Head_Pointer <= "111";
when others =>
Next_Head_Pointer <= "XXX";
end case;
end if;
end process;
--Process to find the latest value of Rs to be given to Dispatch
Dispatch_RsRead_Process: process (Clk,Resetb)
variable found_Rs1, found_Rs2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RsPointer: std_logic_vector(2 downto 0);
begin
if (Resetb = '0') then
Committed_RsList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rs1 := '1';
exit;
else
found_Rs1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rs2 := '1';
exit;
else
found_Rs2 := '0';
end if;
end if;
end loop;
-- Task 3: Use found_Rs1, found_Rs2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rspointer and Dfa_RsValid
-- Dfa_RsValid tells if the Rs register is present in any of the 8 checkpoints or not
-- BRAM_Rspointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RsValid <= found_Rs1 or found_Rs2;
if (found_Rs1 = '1') then
BRAM_Rspointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rs2 = '1') then
BRAM_Rspointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rspointer := (others => '0');
end if;
-- Task 4: Update Committed_Rslist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rslist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RsList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RsList_temp <= Cfc_RsList(conv_integer(BRAM_RsPointer & Dis_CfcRsAddr)); --concatenating the pointer & logical Rs address value to read BRAM
Committed_RsList_temp <= Committed_RsList(conv_integer(Dis_CfcRsAddr));
end if;
end if;
end process;
process (Dfa_RsValid, Cfc_RsList_temp, Committed_RsList_temp)--mux to select between the checkpoint value or committed value
begin
if (Dfa_RsValid = '1') then
Cfc_RsPhyAddr <= Cfc_RsList_temp;
else
Cfc_RsPhyAddr <= Committed_RsList_temp;
end if;
end process;
-- Task 5: same process as above for finding the latest value of Rt
Dispatch_RtRead_Process: process(Clk,Resetb)
variable found_Rt1, found_Rt2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RtPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RtList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRtAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rt1 := '1';
exit;
else
found_Rt1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRtAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rt2 := '1';
exit;
else
found_Rt2 := '0';
end if;
end if;
end loop;
-- Use found_Rt1, found_Rt2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rtpointer and Dfa_RtValid
-- Dfa_RtValid tells if the Rt register is present in any of the 8 checkpoints or not
-- BRAM_Rtpointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RtValid <= found_Rt1 or found_Rt2;
if (found_Rt1 = '1') then
BRAM_Rtpointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rt2 = '1') then
BRAM_Rtpointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rtpointer := (others => '0');
end if;
-- Task 4: Update Committed_Rtlist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rtlist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RtList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RtList_temp <= Cfc_RtList(conv_integer(BRAM_RtPointer & Dis_CfcRtAddr)); --concatenating the pointer & logical Rt address value to read BRAM
Committed_RtList_temp <= Committed_RtList(conv_integer(Dis_CfcRtAddr));
end if;
end if;
end process;
process (Dfa_RtValid, Cfc_RtList_temp, Committed_RtList_temp)
begin
if (Dfa_RtValid = '1') then
Cfc_RtPhyAddr <= Cfc_RtList_temp;
else
Cfc_RtPhyAddr <= Committed_RtList_temp;
end if;
end process;
-- Task 6: same process as above for finding the latest value of Rd
Dispatch_RdRead_Process: process(Clk,Resetb)
variable found_Rd1, found_Rd2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RdPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RdList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRdAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rd1 := '1';
exit;
else
found_Rd1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRdAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rd2 := '1';
exit;
else
found_Rd2 := '0';
end if;
end if;
end loop;
-- Use found_Rd1, found_Rd2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rdpointer and Dfa_RdValid
-- Dfa_RdValid tells if the Rd register is present in any of the 8 checkpoints or not
-- BRAM_Rdpointer gives which checkpoint it is present in. Set it to "000" by default.
Dfa_RdValid <= found_Rd1 or found_Rd2;
if (found_Rd1 = '1') then
BRAM_Rdpointer := conv_std_logic_vector(BRAM_pointer1, 3);
elsif (found_Rd2 = '1') then
BRAM_Rdpointer := conv_std_logic_vector(BRAM_pointer2, 3);
else
BRAM_Rdpointer := (others => '0');
end if;
-- Task 4: Update Committed_Rdlist when a register-writing instruction is committed
if (Rob_Commit = '1' and Rob_CommitRegWrite = '1') then
Committed_Rdlist(conv_integer(Rob_CommitRdAddr)) <= Rob_CommitCurrPhyAddr;
end if;
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RdList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RdList_temp <= Cfc_RdList(conv_integer(BRAM_RdPointer & Dis_CfcRdAddr)); --concatenating the pointer & logical Rd address value to read BRAM
Committed_RdList_temp <= Committed_RdList(conv_integer(Dis_CfcRdAddr));
end if;
end if;
end process;
process (Dfa_RdValid, Cfc_RdList_temp, Committed_RdList_temp)
begin
if (Dfa_RdValid = '1') then
Cfc_RdPhyAddr <= Cfc_RdList_temp;
else
Cfc_RdPhyAddr <= Committed_RdList_temp;
end if;
end process;
end cfc_arch;
|
gpl-2.0
|
22fcecf23c0c54abf8e604e7671e4243
| 0.66354 | 3.564843 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
fifo_vw.vhd
| 1 | 12,705 |
-- Greg Stitt
-- University of Florida
-- Description:
-- fifo_vw (variable write)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generic Descriptions
-- data_width : The width of a single element stored in the FIFO
-- parallel_io : The maximum number of parallel inputs written simulateously,
-- and the exact number of outputs provided by the FIFO.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Descriptions
-- clk: clock
-- rst: reset
-- rd : read data from the buffer (does nothing when empty is asserted)
-- wr : writes up to parallel_io inputs into the buffer, based on status
-- of valid_in (does nothing when full is asserted)
-- valid_in : specifies valid status of all parallel_io inputs (1 bit for each).
-- The fifo will ignore any inputs whose valid_in bit is
-- not asserted. NOTE: the FIFO does not allow invalid inputs
-- with an index higher than valid inputs. e.g. for
-- parallel_io = 4, "1100" would be legal, but "0101" would be
-- illegal.
-- empty : asserted when the buffer is empty (has less than parallel_io
-- elements in fifo)
-- full : asserted when there isn't room to write parallel_io inputs.
-- input : parallel_io input values, concatenated into a big std_logic_vector
-- output : max_outputs outputs. When rd_amount < max_outputs, the higher bits
-- contains valid datas.
-------------------------------------------------------------------------------
entity fifo_vw is
generic (
data_width : positive := 16;
parallel_io : positive := 16);
port (
clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
--valid_in : in std_logic_vector(parallel_io-1 downto 0);
valid_count : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
empty : out std_logic;
full : out std_logic;
input : in std_logic_vector(parallel_io*data_width-1 downto 0);
output : out std_logic_vector(parallel_io*data_width-1 downto 0));
end fifo_vw;
--architecture old of fifo_vw is
-- type data_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0);
-- -- -1 is hack for simulation error, should be -2
-- signal front : integer range 0 to parallel_io*2-1;
-- signal valid_in_count : integer range 0 to parallel_io;
-- signal inputs : data_array(0 to parallel_io-1);
-- signal regs : data_array(0 to parallel_io*2-1);
-- signal valid_wr : std_logic;
-- signal valid_rd : std_logic;
-- signal full_s : std_logic;
-- signal empty_s : std_logic;
--begin
-- -- empty when there less than parallel_io valid elements stored
-- empty_s <= '1' when front < parallel_io else '0';
-- empty <= empty_s;
-- -- full when there are >= parallel_io elements, but not when a read is
-- -- currently occuring
-- full_s <= '1' when front >= parallel_io and valid_rd = '0' else '0';
-- full <= full_s;
-- -- check for valid rd/wr to avoid data loss
-- valid_wr <= wr and not full_s;
-- valid_rd <= rd and not empty_s;
-- -- devectorize the input vector into an array
-- -- not necessary, but makes other code more concise
-- process(input)
-- begin
-- for i in 0 to parallel_io-1 loop
-- inputs(i) <= input(input'length-i*data_width-1 downto input'length-(i+1)*data_width);
-- end loop;
-- end process;
-- -- calculate the number of valid inputs
-- process(valid_in)
-- variable temp : integer range 0 to parallel_io;
-- begin
-- temp := 0;
-- for i in parallel_io-1 downto 0 loop
-- exit when valid_in(i) = '0';
---- if (valid_in(i) = '1') then
-- temp := temp + 1;
-- -- end if;
-- end loop;
-- valid_in_count <= temp;
-- end process;
-- -- vectorize the parallel_io registers into the output signal
-- process(regs)
-- begin
-- for i in 0 to parallel_io-1 loop
-- output(input'length-i*data_width-1 downto input'length-(i+1)*data_width) <= regs(i);
-- end loop;
-- end process;
-- process(clk, rst)
-- -- -1 is hack for simulation error, should be -2
-- variable new_front : integer range 0 to parallel_io*2-1;
-- begin
-- if (rst = '1') then
-- for i in 0 to parallel_io*2-1 loop
-- regs(i) <= (others => '0');
-- end loop;
-- front <= 0;
-- elsif (rising_edge(clk)) then
-- new_front := front;
-- if (valid_rd = '1') then
-- -- every read should move the front index by parallel_io
-- new_front := new_front - parallel_io;
-- -- move the top half of the buffer to the bottom
-- for i in 0 to parallel_io-1 loop
-- regs(i) <= regs(i+parallel_io);
-- end loop;
-- end if;
-- -- write new data to the parallel_io registers starting at new_front
-- if (valid_wr = '1') then
-- for i in 0 to parallel_io-1 loop
-- regs(new_front+i) <= inputs(i);
-- end loop;
-- new_front := new_front + valid_in_count;
-- end if;
-- front <= new_front;
-- end if;
-- end process;
--end OLD;
architecture HIGH_FREQ of fifo_vw is
constant LEVELS : positive := bitsNeeded(PARALLEL_IO-1);
type count_array is array (integer range <>) of unsigned(bitsNeeded(PARALLEL_IO)-1 downto 0);
signal buf : std_logic_vector(input'length*2-1 downto 0);
signal buf_count : unsigned(bitsNeeded(2*parallel_io)-1 downto 0);
signal count : count_array(0 to LEVELS-1);
signal offset : count_array(0 to LEVELS-1);
signal shift_amount : std_logic_vector(bitsNeeded(parallel_io-1)-1 downto 0);
signal shift_done : std_logic;
signal full_s : std_logic;
signal empty_s : std_logic;
signal valid_wr : std_logic;
signal valid_rd : std_logic;
signal input_extended : std_logic_vector(input'length*2-1 downto 0);
signal input_aligned : std_logic_vector(input'length*2-1 downto 0);
signal shift_en : std_logic;
signal input_fifo_rd : std_logic;
signal input_fifo_empty : std_logic;
signal input_fifo_full : std_logic;
signal input_fifo_data_out : std_logic_vector(input'range);
signal count_fifo_data_out : std_logic_vector(valid_count'range);
constant FIFO_DEPTH : positive := 4;
begin
-- FIFOs to decouple reads and writes, used to improve timing
U_INPUT_FIFO : entity work.fifo
generic map (
width => input'length,
depth => FIFO_DEPTH,
same_cycle_output => true)
port map (
clk => clk,
rst => rst,
rd => input_fifo_rd,
wr => valid_wr,
empty => input_fifo_empty,
full => input_fifo_full,
almost_full => open,
input => input,
output => input_fifo_data_out);
input_fifo_rd <= not full_s and not input_fifo_empty;
U_COUNT_FIFO : entity work.fifo
generic map (
width => valid_count'length,
depth => FIFO_DEPTH,
same_cycle_output => true)
port map (
clk => clk,
rst => rst,
rd => input_fifo_rd,
wr => valid_wr,
empty => open,
full => open,
almost_full => open,
input => valid_count,
output => count_fifo_data_out);
input_extended <= input_fifo_data_out & std_logic_vector(to_unsigned(0, input'length));
U_SHIFT_INPUT : entity work.right_shift
generic map (
shift_bits => LEVELS,
word_width => data_width,
num_words => 2*PARALLEL_IO)
port map (
clk => clk,
rst => rst,
en => shift_en,
input => input_extended,
output => input_aligned,
shift_amount => shift_amount,
valid_in => input_fifo_rd,
valid_out => shift_done);
shift_en <= not full_s or valid_rd;
full_s <= '1' when buf_count >= parallel_io and valid_rd = '0' else '0';
empty_s <= '1' when buf_count < parallel_io else '0';
full <= input_fifo_full;
empty <= empty_s;
valid_wr <= '1' when wr = '1' and input_fifo_full = '0' and unsigned(valid_count) > 0 else '0';
valid_rd <= rd and not empty_s;
shift_amount <= std_logic_vector(offset(0)(shift_amount'range));
process(clk, rst)
variable next_buf : std_logic_vector(buf'range);
variable next_buf_count : unsigned(buf_count'range);
begin
if (rst = '1') then
buf <= (others => '0');
buf_count <= (others => '0');
for i in 0 to bitsNeeded(parallel_io-1)-1 loop
count(i) <= (others => '0');
offset(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
-- shift the counts of each level
if (shift_en = '1') then
count(0) <= (others => '0');
for i in 0 to bitsNeeded(parallel_io-1)-2 loop
count(i+1) <= count(i);
offset(i+1) <= offset(i);
end loop;
end if;
-- update the count at the first level
if (input_fifo_rd = '1') then
count(0) <= unsigned(count_fifo_data_out);
-- make sure the count is between 0 and parallel_io-1
if (offset(0) + unsigned(count_fifo_data_out) >= parallel_io) then
offset(0) <= offset(0) + unsigned(count_fifo_data_out) - parallel_io;
else
offset(0) <= offset(0) + unsigned(count_fifo_data_out);
end if;
-- else
-- count(0) <= (others => '0');
end if;
-- shift the counts of each level
if (shift_en = '1') then
for i in 0 to bitsNeeded(parallel_io-1)-2 loop
count(i+1) <= count(i);
offset(i+1) <= offset(i);
end loop;
end if;
next_buf_count := buf_count;
next_buf := buf;
-- update the count of the internal buffer
if (valid_rd = '1') then
-- get the count of the buffer after the read but before
-- writing anything new
next_buf_count := next_buf_count - parallel_io;
-- shift by parallel_io on a read to align extra data
next_buf := buf(buf'length/2-1 downto 0) & std_logic_vector(to_unsigned(0, buf'length/2));
end if;
-- if the shifter has a valid output and isn't stalled
-- then update the internal buffer
if (shift_done = '1' and shift_en = '1') then
-- update all the invalid elements in the buffer
for i in next_buf'range loop
if ((next_buf'length-(i+1)) / data_width >= next_buf_count) then
next_buf(i) := input_aligned(i);
end if;
end loop;
next_buf_count := next_buf_count + count(LEVELS-1);
end if;
buf_count <= next_buf_count;
buf <= next_buf;
end if;
end process;
-- the output is always the top half of the buffer
output <= buf(buf'length-1 downto buf'length/2);
end HIGH_FREQ;
|
gpl-3.0
|
34f1da0b2abcaf886fcb1bbf85dd1593
| 0.497757 | 3.836051 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/comp_pckgs.vhd
| 1 | 11,063 |
--****************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- comp_pckgs.vhd
--
-- Contains packages common and comp_pckgs. package common
-- defines some constants and functions used in the design.
-- comp_pckgs define components for entities in the desin
-- so they can be instantiated and used. Was easier to keep them
-- here in one place then spread them throughout the design
-- by defining them in the architectures.
--****************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package common is
constant YES: std_logic := '1';
constant NO: std_logic := '0';
constant HI: std_logic := '1';
constant LO: std_logic := '0';
function log2(v: in natural) return natural;
end package common;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package body common is
function log2(v: in natural) return natural is
variable n: natural;
variable logn: natural;
begin
n := 1;
for i in 0 to 128 loop
logn := i;
exit when (n>=v);
n := n * 2;
end loop;
return logn;
end function log2;
end package body common;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package comp_pckgs is
-- Xilinx specific components
component IBUFG
port(
O: out std_ulogic;
I: in std_ulogic
);
end component;
component BUFG
port(
O: out std_ulogic;
I: in std_ulogic
);
end component;
component BUF
port(
O: out std_ulogic;
I: in std_ulogic
);
end component;
component OBUF
port(
O: out std_ulogic;
I: in std_ulogic
);
end component;
component IBUF
port(
O: out std_ulogic;
I: in std_ulogic
);
end component;
component CLKDLL
generic ( CLKDV_DIVIDE : natural := 2);
port(
CLKIN: in std_ulogic := '0';
CLKFB: in std_ulogic := '0';
RST: in std_ulogic := '0';
CLK0: out std_ulogic := '0';
CLK90: out std_ulogic := '0';
CLK180: out std_ulogic := '0';
CLK270: out std_ulogic := '0';
CLK2X: out std_ulogic := '0';
CLKDV: out std_ulogic := '0';
LOCKED: out std_ulogic := '0'
);
end component;
-- Entities defined by me
component signal_debounce
generic
(
delay: natural := 4 -- must be a power of 2! 2, 4, 8, 16...
);
PORT
(
clk_50Mhz: in std_logic;
sig_in: in std_logic; --in unbuffered from the parallel port
rst: in std_logic;
sig_out: out std_logic
);
end component;
component clock_generation
PORT
(
bufclkin : in std_logic;
rst_n : in std_logic;
bufsclkfb : in std_logic; --feedback clock from sdram
rst_int : out std_logic;
clk_12_5Mhz : out std_logic;
clk_50Mhz : out std_logic;
clk_100Mhz : out std_logic;
sclk : out std_logic
);
end component;
component clockdivider
GENERIC ( divide_by : natural );
PORT(
clk, rst : in std_logic;
slow_clk : out std_logic
);
end component;
component ms_delay
PORT(
clk, rst, start : in std_logic;
delay_complete : out std_logic
);
end component;
component LEDDecoder
Port ( d : in std_logic_vector(3 downto 0);
s : out std_logic_vector(6 downto 0));
end component;
component one_shot
PORT
(
clk: in std_logic;
sig_in: in std_logic; --in unbuffered from the parallel port
rst: in std_logic;
sig_out: out std_logic
);
end component;
component master_control_signal_generator
PORT
(
clk_50Mhz: in std_logic;
clk_12_5Mhz : in std_logic;
clk_pp: in std_logic;
rst: in std_logic;
cmd: in std_logic_vector(5 downto 0);
start_upload: out std_logic;
abort_upload: out std_logic;
start_addr: out std_logic_vector(22 downto 0);
end_addr: out std_logic_vector(22 downto 0);
init_cycle_complete: out std_logic;
init_KAC : out std_logic;
sync_KAC : out std_logic; -- out KAC sync pin
start_KAC : out std_logic;
done_KAC : in std_logic;
r_w_KAC : out std_logic; -- 0=read 1=write
Addr_KAC : out std_logic_vector(7 downto 0);
Data_KAC_in : out std_logic_vector(7 downto 0);
Data_KAC_out: in std_logic_vector(7 downto 0)
);
end component;
component ram_control
PORT
(
clk_50Mhz: in std_logic;
rst: in std_logic;
-- PP ram access. Control provided by MCSG
pp_data_out : out std_logic_vector(15 downto 0);
start_upload : in std_logic;
abort_upload : in std_logic;
start_addr_upload : in std_logic_vector(22 downto 0);
end_addr_upload : in std_logic_vector(22 downto 0);
pp_fifo_wr_en : out std_logic;
pp_fifo_need_data : in std_logic;
-- Internal logic I/O
rd_en_KAC : out std_logic;
dout_KAC : in std_logic_vector(15 downto 0);
dump_data_req_KAC : in std_logic;
start_new_frame : in std_logic;
-- SDRAM side
cke : out std_logic; -- clock-enable to SDRAM
cs_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- command input to SDRAM
cas_n : out std_logic; -- command input to SDRAM
we_n : out std_logic; -- command input to SDRAM
ba : out unsigned(1 downto 0); -- SDRAM bank address bits
sAddr : out unsigned(12-1 downto 0); -- SDRAM row/column address
sData : inout unsigned(16-1 downto 0);-- SDRAM in/out databus
dqmh : out std_logic; -- high databits I/O mask
dqml : out std_logic -- low databits I/O mask
);
end component;
component pp_upload
PORT
(
clk_50Mhz: in std_logic;
clk_pp: buffer std_logic; --debounced clk from pport
rst: in std_logic;
pps: out std_logic_vector(6 downto 3);
ppd: in std_logic_vector(6 downto 0);
upload_data: in std_logic_vector(15 downto 0); --input to fifo
wr_en: in std_logic;
need_data: out std_logic; --indicats fifo status, use to control wr_en
start_upload : in std_logic;
cmd: out std_logic_vector(5 downto 0)
);
end component;
-- EDIF pulled in during P&R.
component block_ram_2kx16
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
sinit: IN std_logic;
we: IN std_logic);
end component;
-- This is using a block ram... some of the outputs are dangling... fix it
-- Parallel port
component asyn_fifo_distrib
port (
din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
almost_full: OUT std_logic;
almost_empty: OUT std_logic;
wr_count: OUT std_logic_VECTOR(3 downto 0));
end component;
-- For KAC
component asyn_fifo_distrib_64
port (
din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
almost_full: OUT std_logic;
almost_empty: OUT std_logic;
wr_count: OUT std_logic_VECTOR(3 downto 0);
rd_count: OUT std_logic_VECTOR(3 downto 0));
end component;
component KAC_i2c
generic ( I2C_ADDR : std_logic_vector(6 downto 0) );
port (
clk : in std_logic;
nReset : in std_logic;
start_KAC : in std_logic;
done_KAC : out std_logic;
r_w_KAC : in std_logic; --0=read 1=write
Addr_KAC : in std_logic_vector(7 downto 0);
Data_KAC_in : in std_logic_vector(7 downto 0);
Data_KAC_out: out std_logic_vector(7 downto 0);
SCL : inout std_logic;
SDA : inout std_logic
);
end component;
component KAC_data
PORT
(
clk_50Mhz : in std_logic;
clk_12_5Mhz : in std_logic;
rst : in std_logic;
-- Internal logic I/O
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);
dump_data_req : out std_logic;
start_new_frame : out std_logic;
init_cycle_complete : in std_logic;
-- KAC-1310 I/O
sof_KAC : in std_logic;
vclk_KAC : in std_logic;
hclk_KAC : in std_logic;
pix_KAC : in std_logic_vector(9 downto 0)
);
END component;
component sdramCntl
generic(
FREQ: natural := 50_000; -- operating frequency in KHz
DATA_WIDTH: natural := 16; -- host & SDRAM data width
HADDR_WIDTH: natural := 23; -- host-side address width
SADDR_WIDTH: natural := 12 -- SDRAM-side address width
);
port(
clk : in std_logic; -- master clock
-- host side
rst : in std_logic; -- reset
rd : in std_logic; -- read data
wr : in std_logic; -- write data
done : out std_logic; -- read/write op done
hAddr : in unsigned(HADDR_WIDTH-1 downto 0); -- address from host
hDIn : in unsigned(DATA_WIDTH-1 downto 0); -- data from host
hDOut : out unsigned(DATA_WIDTH-1 downto 0); -- data to host
sdramCntl_state: out std_logic_vector(3 downto 0);
-- SDRAM side
cke : out std_logic; -- clock-enable to SDRAM
cs_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- command input to SDRAM
cas_n : out std_logic; -- command input to SDRAM
we_n : out std_logic; -- command input to SDRAM
ba : out unsigned(1 downto 0); -- SDRAM bank address bits
sAddr : out unsigned(SADDR_WIDTH-1 downto 0); -- row/column address
sData : inout unsigned(DATA_WIDTH-1 downto 0);-- SDRAM in/out databus
dqmh : out std_logic; -- high databits I/O mask
dqml : out std_logic -- low databits I/O mask
);
end component;
-- Used by test bench
component digital_camera
PORT
(
-- Test Ports
init_cycle_complete_test_port: out std_logic;
-- XSA-100 MISC
clkin : in std_logic;
rst : in std_logic;
s : out std_logic_vector(6 downto 0); -- Segments
ce_n : out std_logic; -- Flash enable
dips : in std_logic_vector(3 downto 0); -- 4 Dip switches
pps : out std_logic_vector(6 downto 3); -- Status pins for upload
ppd : in std_logic_vector(6 downto 0); -- For download
-- XSA-100 SDRAM
sclkfb : in std_logic;
sclk : out std_logic;
cke : out std_logic; -- clock-enable to SDRAM
cs_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- command input to SDRAM
cas_n : out std_logic; -- command input to SDRAM
we_n : out std_logic; -- command input to SDRAM
ba : out unsigned(1 downto 0); -- SDRAM bank address bits
sAddr : out unsigned(12-1 downto 0); -- SDRAM row/column address
sData : inout unsigned(16-1 downto 0);-- SDRAM in/out databus
dqmh : out std_logic; -- high databits I/O mask
dqml : out std_logic; -- low databits I/O mask
--KAC-1310
mclk_KAC : out std_logic;
init_KAC : out std_logic;
-- sync_KAC : out std_logic;
sof_KAC : in std_logic; --Start of frame
vclk_KAC : in std_logic; --Start of line
hclk_KAC : in std_logic; --Pixel clk
pix_KAC : in std_logic_vector(9 downto 0); -- Pixel data
scl : inout std_logic;
sda : inout std_logic
);
END component;
end package comp_pckgs;
|
gpl-3.0
|
a98b4121b4bf68e3b38c81320acc445c
| 0.634457 | 2.796512 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/user_code_tpl.vhd
| 1 | 1,799 |
---------------------------------------------------------
-- Çäåñ êîä, êîòîðûé ìîæåò èñïîëüçîâàòü âñå óòñðîéñòâà --
---------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity user_code is
port(
buttons: in std_logic_vector(7 downto 0);
led: out std_logic_vector(7 downto 0);
web_output_write_o: out std_logic;
web_output_data_o: out std_logic_vector(7 downto 0);
web_output_ready_i: in std_logic;
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
reset_o: out std_logic;
clk: in std_logic
);
end user_code;
architecture Behavioral of user_code is
signal reset : std_logic := '1';
begin
reset_o <= reset;
proc: process(clk)
variable store_rot_center : std_logic := '0';
variable store_rot_a : std_logic := '0';
variable store_rot_b : std_logic := '0';
begin
if rising_edge(clk) then
if reset = '1' then
reset <= '0';
end if;
led <= buttons;
if rot_center = '1' then
led <= buttons(7 downto 3) & rot_center & rot_b & rot_a;
--web_output_write_o <= '1';
--web_output_data_o <= "00000" & rot_center & rot_b & rot_a;
else
web_output_write_o <= '0';
end if;
-- if rot_center /= store_rot_center or rot_a /= store_rot_a or rot_b /= store_rot_b then
-- store_rot_center := rot_center;
-- store_rot_a := rot_a;
-- store_rot_b := rot_b;
-- web_output_write_o <= '1';
-- web_output_data_o <= "00000" & rot_center & rot_b & rot_a;
-- led <= "00000" & rot_center & rot_b & rot_a;
-- else
-- web_output_write_o <= '0';
-- end if;
end if;
end process;
end Behavioral;
|
mit
|
9ef25880a62e6e91ff98e51b05c97aec
| 0.539188 | 3.008361 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RESPONSE_QUEUE/example_design/RESPONSE_QUEUE_top.vhd
| 1 | 4,798 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RESPONSE_QUEUE_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RESPONSE_QUEUE_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RESPONSE_QUEUE_top;
architecture xilinx of RESPONSE_QUEUE_top is
SIGNAL clk_i : std_logic;
component RESPONSE_QUEUE is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : RESPONSE_QUEUE PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
421bed6acd00b56ef0ed33434602e478
| 0.528554 | 4.987526 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/multiplier_r1.vhd
| 1 | 6,797 |
------------------------------------------------------------------------------
-- File: multiplier_r1.vhd (earlier multiplier.vhd) was revised)
-- EE560 Tomasulo with ROB project
-- July 23, 2009
-- Rohit Goel , Gandhi Puvvada
------------------------------------------------------------------------------
-- This is a wrapper which instantiates the multiplier_core
-- It carries the tag and valid bit of the mult instruction trhough 3 stage registers.
-- It also supports selective flushing due to mispredicted branches (when Cdb_Flush is true).
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
------------------------------------------------------------------------------
entity multiplier is
generic (
tag_width : integer := 6
);
port (
clk : in std_logic;
Resetb : in std_logic;
Iss_Mult : in std_logic ; -- from issue unit
PhyReg_MultRsData : in std_logic_VECTOR(31 downto 0); -- from issue queue mult
PhyReg_MultRtData : in std_logic_VECTOR(31 downto 0); -- from issue queue mult
Iss_RobTag : in std_logic_vector(4 downto 0); -- from issue queue mult
-------------------------------- Logic for the pins ( added by Atif) --------------------------------
Mul_RdPhyAddr : out std_logic_vector(5 downto 0); -- output to CDB required
Mul_RdWrite : out std_logic;
Iss_RdPhyAddr : in std_logic_vector(5 downto 0); -- incoming form issue queue, need to be carried as Iss_RobTag
Iss_RdWrite : in std_logic;
----------------------------------------------------------------------
-- translate_off
Iss_instructionMul : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Mul_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Mul_RdData : out std_logic_VECTOR(31 downto 0); -- output to CDB unit (to CDB Mux)
Mul_RobTag : out std_logic_vector(4 downto 0); -- output to CDB unit (to CDB Mux)
Mul_Done : out std_logic ; -- output to CDB unit ( to control Mux selection)
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
);
end multiplier;
architecture multiply of multiplier is
component multiplier_core is
Port ( m: in std_logic_vector (15 downto 0 ); -- multiplicand (input 1)
q: in std_logic_vector ( 15 downto 0); -- multiplier (input 2)
P: out std_logic_vector ( 31 downto 0); -- the output product
clk: in std_logic
);
end component multiplier_core;
-- component multiplier_core is
-- Port ( DATA_A : in std_logic_vector (31 downto 0 );
-- DATA_B : in std_logic_vector ( 31 downto 0);
-- MULT_OUT : out std_logic_vector ( 31 downto 0)
-- );
-- end component multiplier_core;
subtype tag_type is std_logic_vector(4 downto 0);
type tag is array (0 to 2) of tag_type;
signal tag_mul : tag;
-- signal mul_res_reg, mul_res_out : std_logic_vector(31 downto 0);
-- signal mul_pipe_reg_a, mul_pipe_reg_b : std_logic_vector(31 downto 0);
subtype phy_addr is std_logic_vector(5 downto 0);
type phyaddr is array (0 to 2) of phy_addr;
signal RdPhyAddr : phyaddr;
signal tag_valid,RdWrite : std_logic_vector ( 0 to 2 ) ;
signal BufDepth , Buf0Depth : std_logic_vector ( 4 downto 0 );
signal Buf1Depth , Buf2Depth : std_logic_vector ( 4 downto 0 ); -- Note: Buf2Depth is not needed here!
begin
BufDepth <= unsigned(Iss_RobTag) - unsigned(Rob_TopPtr) ; -- depth of incoming instruction
Buf0Depth <= unsigned(tag_mul(0)) - unsigned(Rob_TopPtr) ; -- depth of instruction 0 in pipe
Buf1Depth <= unsigned(tag_mul(1)) - unsigned(Rob_TopPtr) ; -- depth of instruction 1 in pipe
-- Note: On the tick of the clock, the incoming instruction, and the instructions 0 and 1 will take postion
-- in register 0, 1, and 2 respectively. When Cdb_Flush is activated, we are responsible to invalidate appropriate Flip-Flops
-- by the end of the clock. So we take care of the three valid-bit FFs, tag_valid(0 to 2). The CDB shall take care of invalidiating
-- the outgoing mult instruction (going out of multiplier and entering the CDB register). So CDB will worry about Buf3Depth!
-- Hence the following line is not needed here
-- Buf2Depth <= unsigned(tag_mul(2)) - unsigned(Rob_TopPtr) ; -- depth of instruction 2 in pipe
-- mult : multiplier_core
-- port map (
-- DATA_A => mul_pipe_reg_a,
-- DATA_B => mul_pipe_reg_b,
-- MULT_OUT => mul_res_out
-- );
mult : multiplier_core
port map (
m => PhyReg_MultRsData (15 downto 0),
q => PhyReg_MultRtData (15 downto 0),
p => Mul_RdData,
clk => clk
);
Mul_RobTag <= tag_mul(2);
Mul_Done <= tag_valid(2) ; -- needed for controlling the CDB mux
Mul_RdPhyAddr <= RdPhyAddr(2);
Mul_RdWrite <= RdWrite(2);
-- translate_off
Mul_instruction <= Iss_instructionMul ;
-- translate_on
tag_carry : process (clk, Resetb)
begin
if(Resetb = '0') then
for i in 0 to 2 loop
tag_mul(i) <= (others => '-');
RdPhyAddr(i) <= (others=>'-');
tag_valid(i) <= '0' ;
RdWrite(i) <= '0';
RdPhyAddr(i) <= (others=>'-');
end loop;
elsif(clk'event and clk = '1') then
tag_mul(0) <= Iss_RobTag; -- we do not have to inhibit tag from entering
tag_mul(1) <= tag_mul(0);
tag_mul(2) <= tag_mul(1);
RdPhyAddr(0) <= Iss_RdPhyAddr;
RdPhyAddr(1) <= RdPhyAddr(0);
RdPhyAddr(2) <= RdPhyAddr(1);
RdWrite(0) <= Iss_RdWrite;
RdWrite(1) <= RdWrite(0);
RdWrite(2) <= RdWrite(1);
if ( Cdb_Flush = '1' ) then
if ( BufDepth > Cdb_RobDepth ) then -- Note: It is BufDepth of the incoming instruction and not Buf0Depth
tag_valid(0) <= '0' ;
else
tag_valid(0) <= Iss_Mult ;
end if ;
if ( Buf0Depth > Cdb_RobDepth and tag_valid(0) = '1' ) then
tag_valid(1) <= '0' ;
else
tag_valid(1) <= tag_valid(0) ;
end if ;
-- The above is same as
-- if ( Buf0Depth > Cdb_RobDepth ) then
-- tag_valid(1) <= '0' ;
-- else
-- tag_valid(1) <= tag_valid(0) ;
-- end if ;
if ( Buf1Depth > Cdb_RobDepth and tag_valid(1) = '1' ) then
tag_valid(2) <= '0' ;
else
tag_valid(2) <= tag_valid(1) ;
end if ;
else
tag_valid(0) <= Iss_Mult ;
tag_valid(1) <= tag_valid(0) ;
tag_valid(2) <= tag_valid(1) ;
end if ;
end if;
end process tag_carry;
end architecture multiply;
|
gpl-2.0
|
eca19c86403836cfc90173d47bcc030c
| 0.570252 | 3.467857 | false | false | false | false |
chronos38/DSD-Projekt
|
dezctr/ioctrl/decoder/decoder_struc.vhd
| 1 | 1,117 |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture rtl of decoder is
begin
p_decode : process(clk50)
begin
if rising_edge(clk50) then
case cntr_i is
when "0000" => ss_o <= "11000000"; -- 0
when "0001" => ss_o <= "11111001"; -- 1
when "0010" => ss_o <= "10100100"; -- 2
when "0011" => ss_o <= "10110000"; -- 3
when "0100" => ss_o <= "10011001"; -- 4
when "0101" => ss_o <= "10010010"; -- 5
when "0110" => ss_o <= "10000010"; -- 6
when "0111" => ss_o <= "11111000"; -- 7
when "1000" => ss_o <= "10000000"; -- 8
when "1001" => ss_o <= "10010000"; -- 9
when others => ss_o <= "11111111"; -- hurr
end case;
end if;
end process;
end rtl;
|
gpl-3.0
|
adeb59fb3e5763c0a9323e6b88b3e9f5
| 0.430618 | 4.032491 | false | false | false | false |
csrhau/sandpit
|
VHDL/stencil_buffer/ring_buffer.vhdl
| 1 | 903 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ring_buffer is
port (
clock : in std_logic;
advance: in std_logic;
address: in std_logic_vector;
input : in std_logic_vector;
output : out std_logic_vector
);
end entity ring_buffer;
architecture behavioural of ring_buffer is
type neighbourhood_t is array(integer range 0 to (2**address'length-1)) of std_logic_vector(input'range);
signal neighbourhood : neighbourhood_t := (others => (others => '0'));
signal head : std_logic_vector(address'range) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
if advance = '1' then
neighbourhood(to_integer(unsigned(head))) <= input;
head <= std_logic_vector(unsigned(head) + 1);
end if;
output <= neighbourhood(to_integer(unsigned(address)));
end if;
end process;
end behavioural;
|
mit
|
fc3c916ea8d87f06efc1be9353c8b910
| 0.668882 | 3.541176 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/fifo_generator_v9_3/simulation/fifo_generator_v9_3_dgen.vhd
| 1 | 4,580 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_generator_v9_3_pkg.ALL;
ENTITY fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo_generator_v9_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo_generator_v9_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
apache-2.0
|
e50398b1e8a13b6351ac184b52b6dd90
| 0.602183 | 4.178832 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/KAC_i2c.vhd
| 1 | 6,089 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- KAC_i2c.vhd
--
-- Provides direct access to control registers in image sensor. SRAM like interface
-- makes I2C interface transparent to MCSG. Adapted from Dallas 1621 interface
-- by Richard Herveille OpenCores.
--
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.i2c.all;
entity KAC_i2c is
generic ( I2C_ADDR : std_logic_vector(6 downto 0) );
port (
clk : in std_logic;
nReset : in std_logic;
start_KAC : in std_logic;
done_KAC : out std_logic;
r_w_KAC : in std_logic; --0=read 1=write
Addr_KAC : in std_logic_vector(7 downto 0);
Data_KAC_in : in std_logic_vector(7 downto 0);
Data_KAC_out: out std_logic_vector(7 downto 0);
SCL : inout std_logic;
SDA : inout std_logic
);
end entity KAC_i2c;
architecture KAC_i2c_arch of KAC_i2c is
-- Remove the generic defining the constant
constant SLAVE_ADDR : std_logic_vector(6 downto 0) := I2C_ADDR;
constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(100, 8); --from 50Mhz
signal cmd_ack : std_logic;
signal D : std_logic_vector(7 downto 0);
signal lack, store_dout : std_logic;
signal start, read, write, ack, stop : std_logic;
signal i2c_dout : std_logic_vector(7 downto 0);
begin
-- hookup I2C controller
u1: simple_i2c
port map ( clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset,
read => read, write => write, start => start, stop => stop,
ack_in => ack, cmd_ack => cmd_ack, Din => D, Dout => i2c_dout,
ack_out => lack, SCL => SCL, SDA => SDA);
init_statemachine : block
type states is (i1, i2, i3, t1, t2, t3, t4, ack_wait_read,
ack_wait_write, idle);
signal state : states;
begin
-- There are a bunch of signals that should be in this sensitivity list,
-- but when I added them, things stopped working. I'll just leave it alone.
nxt_state_decoder: process(clk, nReset, state, start_KAC, r_w_KAC)
variable nxt_state : states;
variable iD : std_logic_vector(7 downto 0);
variable ierr : std_logic;
variable istart, iread, iwrite, iack, istop : std_logic;
variable istore_dout : std_logic;
variable wait_for_ack : std_logic;
begin
nxt_state := state;
ierr := '0';
istore_dout := '0';
done_KAC <= '0';
istart := start;
iread := read;
iwrite := write;
iack := ack;
istop := stop;
iD := D;
case (state) is
-- Write Sequence
when i1 => -- send start condition, sent slave address + write
nxt_state := i2;
istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '0'); -- write to slave (R/W = '0')
when i2 => -- send reg addr
if (cmd_ack = '1') then
nxt_state := i3;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := Addr_KAC;
end if;
when i3 => -- send data to write there
if (cmd_ack = '1') then
nxt_state := ack_wait_write;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '1';
iD := Data_KAC_in;
end if;
-- Read Sequence
when t1 => -- send start condition, sent slave address + write
-- if (cmd_ack = '1') then
nxt_state := t2;
istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '0'); -- write to slave (R/W = '0')
-- end if;
when t2 => -- send reg addr
if (cmd_ack = '1') then
nxt_state := t3;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := Addr_KAC;
end if;
-- send (repeated) start condition, send slave address + read
when t3 =>
if (cmd_ack = '1') then
nxt_state := t4;
istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '1'); -- read from slave (R/W = '1')
end if;
when t4 =>
if (cmd_ack = '1') then
nxt_state := ack_wait_read;
istart := '0';
iread := '1';
iwrite := '0';
iack := '1'; --ACK
istop := '1';
--istore_dout := '1';
end if;
when ack_wait_read =>
if (cmd_ack = '1') then
nxt_state := idle;
istart := '0';
iread := '0';
iwrite := '0';
iack := '0';
istop := '0';
iD := x"00";
done_KAC <= '1';
istore_dout := '1'; -- Capture the value read
end if;
when ack_wait_write =>
if (cmd_ack = '1') then
nxt_state := idle;
istart := '0';
iread := '0';
iwrite := '0';
iack := '0';
istop := '0';
iD := x"00";
done_KAC <= '1';
end if;
when idle =>
if start_KAC = '1' then
if r_w_KAC = '0' then
nxt_state := t1; --do read
else
nxt_state := i1; --do write
end if;
end if;
--safe idle conditions and done
istart := '0';
iread := '0';
iwrite := '0';
iack := '0';
istop := '0';
iD := x"00";
done_KAC <= '1';
end case;
-- genregs
if (nReset = '0') then
state <= idle;
store_dout <= '0';
start <= '0';
read <= '0';
write <= '0';
ack <= '0';
stop <= '0';
D <= (others => '0');
wait_for_ack := '0';
elsif (clk'event and clk = '1') then
state <= nxt_state;
store_dout <= istore_dout;
start <= istart;
read <= iread;
write <= iwrite;
ack <= iack;
stop <= istop;
D <= iD;
end if;
end process nxt_state_decoder;
end block init_statemachine;
-- store temp
gen_dout : process(clk)
begin
if (clk'event and clk = '1') then
if (store_dout = '1') then
Data_KAC_out <= i2c_dout;
end if;
end if;
end process gen_dout;
end architecture KAC_i2c_arch;
|
gpl-3.0
|
2d3b533686f75396262257063a1bcba6
| 0.514534 | 2.924592 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_command_rec_fifo/simulation/fg_tb_synth.vhd
| 1 | 11,716 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_command_rec_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
3962a5db14b84567148ac21ef54ba09c
| 0.456726 | 3.964805 | false | false | false | false |
csrhau/sandpit
|
VHDL/striped_gol/test_gol_processor.vhdl
| 1 | 2,458 |
library ieee;
use ieee.std_logic_1164.all;
entity test_gol_processor is
type input_deck is array(integer range <>) of std_logic_vector(9 downto 0);
type output_deck is array(integer range <>) of std_logic_vector(7 downto 0);
end test_gol_processor;
architecture behavioural of test_gol_processor is
component gol_processor is
port (
clock : in std_logic;
input : in std_logic_vector(9 downto 0);
output: out std_logic_vector(8 downto 1)
);
end component gol_processor;
signal clock : std_logic;
signal input : std_logic_vector(9 downto 0);
signal output : std_logic_vector(7 downto 0);
constant test_input : input_deck(0 to 8) := (
0 => "1110000111",
1 => "0000000001",
2 => "0000000010",
3 => "0000000011",
4 => "1110001000",
5 => "1010011100",
6 => "1110001000",
7 => "0000000000",
8 => "0000000000"
);
constant test_output: output_deck(0 to 8) := (
0 => "10000001", -- 0000000000,
-- 0000000000, => _10000001_
-- 1110000111
1 => "10000001", -- 0000000000
-- 1110000111 => _10000001_
-- 0000000001
2 => "10000010", -- 1110000111
-- 0000000001 => _10000010_
-- 0000000010
3 => "00000001", -- 0000000001
-- 0000000010 => _00000001_
-- 0000000011
4 => "10000011", -- 0000000010
-- 0000000011 => _10000011_
-- 1110001000
5 => "01001101", -- 0000000011
-- 1110001000 => _01001101_
-- 1010011100
6 => "00101010", -- 1110001000
-- 1010011100 => _00101010_
-- 1110001000
7 => "01001110", -- 1010011100
-- 1110001000 => _01001110_
-- 0000000000
8 => "10000000" -- 1110001000
-- 0000000000 => _10000000_
-- 0000000000
);
begin
PROCESSOR : gol_processor port map (clock, input, output);
process
begin
for i in 0 to 8 loop
clock <= '0';
wait for 1 ns;
input <= test_input(i);
clock <= '1';
wait for 1 ns;
assert output = test_output(i)
report "Expectation mismatch on iteration " & integer'image(i) severity error;
end loop;
wait;
end process;
end behavioural;
|
mit
|
a7a45b6490bfaf3e4f753b6ac194bc47
| 0.51668 | 4.365897 | false | true | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_1/exercise_IU_BPB_SB_SAB_ee560/issue_unit_NEW.vhd
| 1 | 6,669 |
--==========================================================================================================================
-- FILE NAME : issue_unit.vhd
-- DESCRIPTION : issue unit helps to issue one instruction at a time even when multiple instructions are ready to be issued.
-- the priority depends on LRU bit and also the latency of instruction, long latency instructions are given
-- priority , so the priority order is - div, mult, ( int type and lw/sw depending on LRU bit).
-- AUTHOR : PRASANJEET DAS, VAIBHAV DHOTRE
-- DATE : 6/17/10, 6/23/06
-- TASK : COMPLETE THE SIX TODO SECTIONS.
--===========================================================================================================================
-------------------------------------------
-- LIBRARY DECLARATION
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.tmslopkg.all
--ENTITY DECLARATION
entity issue_unit is
generic(
Resetb_ACTIVE_VALUE : std_logic := '0' -- ACTIVE LOW Resetb
);
port(
Clk : in std_logic;
Resetb : in std_logic;
-- ready signals from each of the queues
IssInt_Rdy : in std_logic;
IssMul_Rdy : in std_logic;
IssDiv_Rdy : in std_logic;
IssLsb_Rdy : in std_logic;
-- signal from the division execution unit to indicate that it is currently available
Div_ExeRdy : in std_logic;
--issue signals as acknowledgement from issue unit to each of the queues
Iss_Int : out std_logic;
Iss_Mult : out std_logic;
Iss_Div : out std_logic;
Iss_Lsb : out std_logic
);
end issue_unit;
-- ARCHITECTURE DECLARATION
architecture Behavioral of issue_unit is
signal CDB_Slot : std_logic_vector(5 downto 0); -- the CDB reservation register
signal LRU_bit : std_logic;
-- you can declare your own signals here
begin
--NOTE:
--================================================================================================================================================================================================
-- 1. simple approach to decide priority between int type and "lw/sw" type instructions
-- depending on the LRU bit issue the Least recently used instruction, use a LRU bit for the same which gets updated every time
-- and instruction is issued.
-- FOR SIMPLICITY ASSUME LRU BIT WHEN AN INT TYPE INSTRUCTION IS ISSUED IS "0" AND WHEN A LW/SW TYPE INSTRUCTION IS ISSUED IS "1"
-- PRECAUTION to be taken only issue the one whose corresponding issueque_ready signal is asserted ( = '1')
--2. issue mult insturction when the CDB_slot (3) is free and the corresponding issueque_ready signal is asserted (= '1') --remember the 4 clock latency
--3. issue div instruction when the Div_ExeRdy indicates that divider execution unit is ready and corresponding issueque_ready signal is asserted (= '1') -- remember the 7 clock latency
--4. don't forget to update the CDB register on every clock as per the required conditions.
--==================================================================================================================================================================================================
process(Resetb, Clk)
begin
if (Resetb = '0') then
-- TODO 1: INITIALIZE CDB and LRU Bit
CDB_Slot <= (others => '0');
LRU_bit <= '0';
elsif ( Clk'event and Clk = '1' ) then
--CDB_Slot <= -- TODO 2: COMPLETE THE SHIFT MECHANISM
CDB_Slot(5) <= '0'; --Iss_Div;
CDB_Slot(4) <= CDB_Slot(5);
CDB_Slot(3) <= CDB_Slot(4);
CDB_Slot(2) <= CDB_Slot(3); -- when (Iss_Mult = '0') else '1';
CDB_Slot(1) <= CDB_Slot(2);
CDB_Slot(0) <= CDB_Slot(1);
if (CDB_Slot(0) = '0') then -- TODO 3: -- FILLUP THE LRU UPDATION MECHANISM WHEN ISSUING TO EITHER INT QUE OR LW/SW QUE
-- Three cases to be considered here:
-- Case 1: when only int type instructions get ready
if (IssInt_Rdy = '1' and IssLsb_Rdy = '0') then
LRU_bit <= '0';
-- Case 2: when only lw/sw type instructions get ready
elsif (IssInt_Rdy = '0' and IssLsb_Rdy = '1') then
LRU_bit <= '1';
-- Case 3: when both int type and lw/sw instructions get ready
elsif (IssInt_Rdy = '1' and IssLsb_Rdy = '1') then
if (LRU_bit = '1') then --toggle LRU_bit
LRU_bit <= '0';
else
LRU_bit <= '1';
end if;
end if;
end if;
-- TODO 4: reserve CDB slot for issuing a div instruction -- 7 CLOCK LATENCY
if (IssDiv_Rdy = '1') then
CDB_Slot(5) <= '1';
end if;
-- TODO 5: reserve CDB slot for issuing a mult instruction -- 4 CLOCK LATENCY
if (CDB_Slot(3) = '0' and IssMul_Rdy = '1') then
CDB_Slot(2) <= '1';
end if;
-- NOTE: THE LATENCY CALCULATION IS INSIDE A CLOCKED PROCESS SO 1 CLOCK LATENCY WILL BE AUTOMATICALLY TAKEN CARE OF.
-- IN OTHER WORDS YOU NEED TO FIGURE OUT THAT IF YOU NEED TO HAVE A LATENCY OF "N" WHICH CDB REGISTER NEEDS TO BE UPDATED
-- IS IT REGISTER "N", REGISTER "N+1" OR REGISTER "N - 1 " ????
end if;
end process;
process(LRU_bit, IssLsb_Rdy, IssInt_Rdy, IssDiv_Rdy, IssMul_Rdy, Div_ExeRdy, CDB_Slot) -- TODO 6: GENERATE THE ISSUE SIGNALS
begin
-- FILL UP THE CODE FOR ISSUING EITHER LW/SW OR INT TYPE INSTRUCTION DEPENDING ON LRU BIT
-- MULTIPLE CASES NEED TO BE CONSIDERED SUCH AS WHEN ONLY ONE TYPE OF INSTRUCTION IS READY
-- OR WHEN BOTH TYPES OF INSTRUCTIONS ARE READY SIMULTANEOUSLY.
-- REFER TO THE THREE CASES MENTIONED IN THE SECTION "TODO 3"
if (IssInt_Rdy = '1' and IssLsb_Rdy = '0') then --Case 1
Iss_Int <= '1';
Iss_Lsb <= '0';
elsif (IssInt_Rdy = '0' and IssLsb_Rdy = '1') then --Case 2
Iss_Int <= '0';
Iss_Lsb <= '1';
elsif (IssInt_Rdy = '1' and IssLsb_Rdy = '1') then --Case 3
if(LRU_bit = '1') then
Iss_Int <= '1'; --switched to LRU (was MRU)//should be switched?
Iss_Lsb <= '0';
else
Iss_Int <= '0';
Iss_Lsb <= '1';
end if;
else
Iss_Int <= '0';
Iss_Lsb <= '0';
end if;
-- FILL UP THE CODE TO ISSUE A DIV TYPE INSTRUCTION
if (IssDiv_Rdy = '1' and Div_ExeRdy = '1') then
Iss_Div <= '1';
else
Iss_Div <= '0';
end if;
-- FILL UP THE CODE TO ISSUE A MULT TYPE INSTRUCTION
if (IssMul_Rdy = '1') then -- and CDB_Slot(3) = '0') then
Iss_Mult <= '1';
else
Iss_Mult <= '0';
end if;
end process;
end Behavioral;
|
gpl-2.0
|
1bad2f6ce6c386c3b6624605dd9a1439
| 0.550457 | 3.780612 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
fifo_vr_tb.vhd
| 1 | 11,196 |
-- FIFO_vr Testbench
-- Author: Eric Schwartz
-- Greg Stitt
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.tb_pkg.all;
entity fifo_vr_tb is
generic(
parallel_io : positive := 4;
data_width : positive := 8;
input0_at_MSB : boolean := true;
output0_at_MSB : boolean := false;
test_size : positive := 10000;
input_delay_prob : real range 0.0 to 1.0 := 0.25;
min_input_delay : natural := 1;
max_input_delay : natural := 10;
output_delay_prob : real range 0.0 to 1.0 := 0.1;
min_output_delay : natural := 1;
max_output_delay : natural := 10;
stall_prob : real range 0.0 to 1.0 := 0.1;
min_stall_delay : natural := 1;
max_stall_delay : natural := 10
);
end fifo_vr_tb;
architecture TB of fifo_vr_tb is
-- ensure that that input size is a multiple of parallel_io. This will
-- round up test_size to the next multiple
constant adjusted_input_size : integer := integer(ceil(real(test_size) / real(parallel_io)))*parallel_io;
type data_array is array (0 to adjusted_input_size-1) of std_logic_vector(data_width-1 downto 0);
signal input_array : data_array;
signal output_array : data_array;
signal clk_en : std_logic := '1';
signal clk, rst, rd, wr : std_logic := '0';
signal empty, full : std_logic;
signal rd_amount : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0) := (others => '0');
signal count : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0);
signal input : std_logic_vector(parallel_io*data_width-1 downto 0) := (others => '0');
signal output : std_logic_vector(parallel_io*data_width-1 downto 0);
signal valid_out : std_logic_vector(parallel_io-1 downto 0);
signal input_ready : std_logic := '0';
signal output_ready : std_logic := '0';
signal input_done : std_logic := '0';
signal all_outputs : boolean := false;
type count_array is array (0 to adjusted_input_size-1) of integer;
signal counts : count_array;
signal stall : std_logic := '0';
begin
U_FIFO_VR : entity work.fifo_vr
generic map(
data_width => data_width,
parallel_io => parallel_io,
input0_at_MSB => input0_at_MSB,
output0_at_MSB => output0_at_MSB)
port map(
clk => clk,
rst => rst,
rd => rd,
rd_amount => rd_amount,
wr => wr,
stall => stall,
empty => empty,
full => full,
input => input,
output => output,
count => count,
valid_out => valid_out
);
clk <= not clk after 10 ns when clk_en = '1' else '0';
-- determine when to write
process(full, input_ready, rst, input_done)
begin
-- input_ready includes random delays
wr <= input_ready and not full and not rst and not input_done;
end process;
-- set the inputs during a writes
process(clk, wr, rst)
variable input_count : integer := parallel_io+1;
begin
if (rst = '1') then
if (input0_at_MSB) then
for j in 0 to parallel_io-1 loop
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(j);
end loop;
else
for j in 0 to parallel_io-1 loop
input((j+1)*data_width-1 downto j*data_width) <= input_array(j);
end loop;
end if;
input_count := parallel_io;
-- set the inputs for each write
elsif (rising_edge(clk) and wr = '1' and rst = '0') then
if (input_count = adjusted_input_size) then
input_done <= '1';
else
for j in 0 to parallel_io-1 loop
if (input_count < adjusted_input_size) then
-- set input order depending on configuration
if (input0_at_MSB) then
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(input_count);
else
input((j+1)*data_width-1 downto j*data_width) <= input_array(input_count);
end if;
input_count := input_count + 1;
end if;
end loop;
end if;
end if;
end process;
-- randomly vary write timings
process
variable s1, s2 : positive; -- seeds for rand function
begin
input_ready <= '0';
wait until rst = '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
while (input_done = '0') loop
input_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, input_delay_prob, min_input_delay, max_input_delay);
input_ready <= '1';
wait until rising_edge(clk);
end loop;
input_ready <= '0';
wait;
end process;
-- initialize the simulation
process
variable rand : integer; -- random inputs to be written to fifo
variable s1, s2 : positive; -- seeds for rand function
variable input_count : integer;
begin
-- initialize inputs
for i in 0 to adjusted_input_size-1 loop
-- randomInt(s1, s2, 0, 2**data_width-1, rand);
-- input_array(i) <= std_logic_vector(to_unsigned(rand, data_width));
input_array(i) <= std_logic_vector(to_unsigned(i, data_width));
end loop;
--Reset the entity and initialize the wr and input to zero
rst <= '1';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
rst <= '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
wait;
end process;
vary_stall : process
variable s1, s2 : positive; -- seeds for rand function
begin
while (not all_outputs) loop
stall <= '1';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, stall_prob, min_stall_delay, max_stall_delay);
stall <= '0';
wait until rising_edge(clk);
end loop;
wait;
end process;
-- randomly vary read timings
vary_read_timing : process
variable s1, s2 : positive; -- seeds for rand function
begin
while (not all_outputs) loop
output_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, output_delay_prob, min_output_delay, max_output_delay);
output_ready <= '1';
wait until rising_edge(clk);
end loop;
wait;
end process;
-- determine when reads occur
-- TODO: Extend with stall functionality
process(empty, output_ready)
begin
rd <= not empty and output_ready and not stall;
end process;
-- set read amounts
read_amounts: process
variable output_count : integer := 0;
variable s1, s2 : positive;
variable rd_amount_v : integer;
variable output_advance : integer;
variable num_reads : integer := 0;
begin
-- while there are still outputs to check
while (output_count < adjusted_input_size) loop
--randomize the number of elements to be read, up to parallel_io
randomInt(s1, s2, 0, parallel_io+1, rd_amount_v);
rd_amount <= std_logic_vector(to_unsigned(rd_amount_v, rd_amount'length));
-- wait until the data is read
wait until rising_edge(clk) and rd = '1';
-- determine how much to advance the output
-- count is the amount of data that was actually available, so
-- never advance more than that
if (unsigned(count) < rd_amount_v) then
output_advance := to_integer(unsigned(count));
else
output_advance := rd_amount_v;
end if;
-- Save outputs in output_array
if (output_advance > 0) then
-- save the count that was used
counts(num_reads) <= output_advance;
num_reads := num_reads + 1;
end if;
output_count := output_count + output_advance;
end loop;
wait until all_outputs;
report "SIMULATION COMPLETE!!!";
clk_en <= '0';
wait;
end process;
check_outputs : process(clk)
variable current_count : integer := 0;
variable out_ind_count : integer := 0;
variable output_temp : std_logic_vector(data_width-1 downto 0) := (others => '0');
variable out_group_count : integer := 0;
begin
-- if there is a valid output, verify it
if (rising_edge(clk) and valid_out /= std_logic_vector(to_unsigned(0, valid_out'length)) and stall = '0') then
-- get the corresponding count for the read that is currently on
-- the output
current_count := counts(out_group_count);
-- make sure the valid out bits match the count
for i in 0 to current_count-1 loop
if (output0_at_MSB) then
assert(valid_out(parallel_io-i-1) = '1') report "Valid out not asserted.";
-- report integer'image(count_temp) & " " & integer'image(to_integer(unsigned(valid_out)));
else
assert(valid_out(i) = '1') report "Valid out not asserted.";
end if;
end loop;
-- check the outputs
for i in 0 to current_count-1 loop
if (output0_at_MSB) then
output_temp := output((parallel_io-i)*data_width-1 downto (parallel_io-i-1)*data_width);
else
output_temp := output((i+1)*data_width-1 downto i*data_width);
end if;
assert(output_temp = input_array(out_ind_count)) report "Output incorrect.";
out_ind_count := out_ind_count + 1;
end loop;
out_group_count := out_group_count + 1;
end if;
if (out_ind_count = adjusted_input_size) then
all_outputs <= true;
end if;
end process;
end TB;
|
gpl-3.0
|
08565967b3eeead05a618528ca13964a
| 0.526974 | 4.050651 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/AddBuff_r2_NEW.vhd
| 2 | 23,639 |
-- CHECKED AND MODIFIED BY PRASANJEET
-------------------------------------------
--UPDATED ON: 7/9/09
-------------------------------------------
-- CHECKED AND MODIFIED BY WALEED
-------------------------------------------
--UPDATED ON: 6/4/10
-------------------------------------------
-------------------------------------------------------------------------------
--
-- Design : Load/Store Address Buff
-- Project : Tomasulo Processor
-- Author : Rohit Goel
-- Company : University of Southern California
--
-------------------------------------------------------------------------------
--
-- File : AddBuff.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The Issue control controls the Issuque
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity AddBuff is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic;
Resetb : in std_logic;
AddrBuffFull : out std_logic; --buffer full
AddrMatch0 : out std_logic;
AddrMatch1 : out std_logic;
AddrMatch2 : out std_logic;
AddrMatch3 : out std_logic;
AddrMatch4 : out std_logic;
AddrMatch5 : out std_logic;
AddrMatch6 : out std_logic;
AddrMatch7 : out std_logic;
AddrMatch0Num : out std_logic_vector (2 downto 0);
AddrMatch1Num : out std_logic_vector (2 downto 0);
AddrMatch2Num : out std_logic_vector (2 downto 0);
AddrMatch3Num : out std_logic_vector (2 downto 0);
AddrMatch4Num : out std_logic_vector (2 downto 0);
AddrMatch5Num : out std_logic_vector (2 downto 0);
AddrMatch6Num : out std_logic_vector (2 downto 0);
AddrMatch7Num : out std_logic_vector (2 downto 0);
ScanAddr0 : in std_logic_vector (31 downto 0); --scan address (address of entries in lsq)
ScanAddr1 : in std_logic_vector (31 downto 0);
ScanAddr2 : in std_logic_vector (31 downto 0);
ScanAddr3 : in std_logic_vector (31 downto 0);
ScanAddr4 : in std_logic_vector (31 downto 0); --scan address (address of entries in lsq)
ScanAddr5 : in std_logic_vector (31 downto 0);
ScanAddr6 : in std_logic_vector (31 downto 0);
ScanAddr7 : in std_logic_vector (31 downto 0);
LsqSwAddr : in std_logic_vector (36 downto 0); --ld/sw address
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector (4 downto 0);
Cdb_RobDepth : in std_logic_vector (4 downto 0);
StrAddr : in std_logic; -- control signal indicating to store address
SB_FlushSw : in std_logic; --flush store
SB_FlushSwTag : in std_logic_vector (1 downto 0); --flush store tag
SBTag_counter : in std_logic_vector (1 downto 0);
--Interface with ROB
Rob_CommitMemWrite : in std_logic
);
end AddBuff;
architecture behave of AddBuff is
type array_8_32 is array (0 to 7) of std_logic_vector(31 downto 0); --data
type array_8_6 is array (0 to 7) of std_logic_vector(4 downto 0); --ROBtag
type array_8_2 is array (0 to 7) of std_logic_vector(1 downto 0); --SBtag
type array_8_1 is array (0 to 7) of std_logic; --tagSelect
signal BuffAdd : array_8_32;
signal BuffRobTag : array_8_6;
signal BufValid : std_logic_vector (7 downto 0); --buffer valid
signal BufferDepth : array_8_6;
signal BuffSBTag : array_8_2;
signal BuffTagSel : array_8_1;
---Mod OAR: 24 Jul 09: Added one Flush
signal Flush : std_logic_vector ( 8 downto 0);
signal En : std_logic_vector ( 6 downto 0);
signal AddrMatch0NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch1NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch2NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch3NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch4NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch5NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch6NumTemp : std_logic_vector(2 downto 0);
signal AddrMatch7NumTemp : std_logic_vector(2 downto 0);
begin
--***********************************************************************************************
-- The following 7 processes are used to perform associative search required for Memory Disambiguation.
-- Since we have 8 entries in the load/store issue queue (LSQ) then we need 8 processes one for each memory
-- address (ScanAddr). The associative search is combinational and is implemented for every memory address
-- in LSQ regardless whether the instruction in LSQ is Load or Store. However, we just need the results of the
-- associative search for Load instructions.
-- Task1: You are given the code completed for generating the number of matches for the first 7 addresses in
-- LSQ (ScanAddr0 to ScanAddr6). You are required to Add the code for the associative search of matches to
-- "ScanAddr7".
--***********************************************************************************************
process (ScanAddr0 ,BuffAdd ,BufValid)
variable Add0MatchTemp : std_logic_vector (2 downto 0);
begin
Add0MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr0 and BufValid(i) = '1') then --valid and address matched
Add0MatchTemp := unsigned(Add0MatchTemp) + 1; -- increment address match index
else
Add0MatchTemp := Add0MatchTemp;
end if;
end loop;
AddrMatch0NumTemp <= Add0MatchTemp;
end process;
process (ScanAddr1 ,BuffAdd,BufValid )
variable Add1MatchTemp : std_logic_vector (2 downto 0);
begin
Add1MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr1 and BufValid(i) = '1') then
Add1MatchTemp := unsigned(Add1MatchTemp) + 1;
else
Add1MatchTemp := Add1MatchTemp;
end if;
end loop;
AddrMatch1NumTemp <= Add1MatchTemp;
end process;
process (ScanAddr2 ,BuffAdd ,BufValid)
variable Add2MatchTemp : std_logic_vector (2 downto 0);
begin
Add2MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr2 and BufValid(i) = '1') then
Add2MatchTemp := unsigned(Add2MatchTemp) + 1;
else
Add2MatchTemp := Add2MatchTemp;
end if;
end loop;
AddrMatch2NumTemp <=Add2MatchTemp;
end process ;
process (ScanAddr3 ,BuffAdd ,BufValid)
variable Add3MatchTemp : std_logic_vector (2 downto 0);
begin
Add3MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr3 and BufValid(i) = '1') then
Add3MatchTemp := unsigned(Add3MatchTemp) + 1;
else
Add3MatchTemp := Add3MatchTemp;
end if;
end loop;
AddrMatch3NumTemp <= Add3MatchTemp;
end process ;
process (ScanAddr4 ,BuffAdd ,BufValid)
variable Add4MatchTemp : std_logic_vector (2 downto 0);
begin
Add4MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr4 and BufValid(i) = '1') then
Add4MatchTemp := unsigned(Add4MatchTemp) + 1;
else
Add4MatchTemp := Add4MatchTemp;
end if;
end loop;
AddrMatch4NumTemp <= Add4MatchTemp;
end process ;
process (ScanAddr5 ,BuffAdd ,BufValid)
variable Add5MatchTemp : std_logic_vector (2 downto 0);
begin
Add5MatchTemp := "000";
for i in 0 to 7 loop
if ( BuffAdd(i) = ScanAddr5 and BufValid(i) = '1' ) then
Add5MatchTemp := unsigned(Add5MatchTemp) + 1;
else
Add5MatchTemp := Add5MatchTemp;
end if;
end loop;
AddrMatch5NumTemp <= Add5MatchTemp;
end process;
process (ScanAddr6 ,BuffAdd ,BufValid)
variable Add6MatchTemp : std_logic_vector (2 downto 0);
begin
Add6MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr6 and BufValid(i) = '1') then
Add6MatchTemp := unsigned(Add6MatchTemp) + 1;
else
Add6MatchTemp := Add6MatchTemp;
end if;
end loop;
AddrMatch6NumTemp <= Add6MatchTemp;
end process;
process (ScanAddr7 ,BuffAdd ,BufValid)
variable Add7MatchTemp : std_logic_vector (2 downto 0);
begin
Add7MatchTemp := "000";
for i in 0 to 7 loop
if (BuffAdd(i) = ScanAddr7 and BufValid(i) = '1') then
Add7MatchTemp := unsigned(Add7MatchTemp) + 1;
else
Add7MatchTemp := Add7MatchTemp;
end if;
end loop;
AddrMatch7NumTemp <= Add7MatchTemp;
end process;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- After we generate the internal Signals for the number of matches for each of the memory addresses
-- in LSQ (ScanAddr0 to ScanAddr7). We need to map the internal signals to the corresponding output ports
-- (AddrMatch0Num to AddrMatch7Match). At the same time we set the bit that indicates that there was at
-- least one match for each of the input addresses.
-- Task2: Add you code to map the matching results of ScanAddr7 to their respective output ports.
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
process (AddrMatch0NumTemp) --depending upon address match index
begin
AddrMatch0 <= '0';
AddrMatch0Num <= "000";
if (AddrMatch0NumTemp > "000") then
AddrMatch0 <= '1'; --just make a note that address is matched
AddrMatch0Num <= AddrMatch0NumTemp;
end if;
end process ;
process (AddrMatch1NumTemp)
begin
AddrMatch1 <= '0';
AddrMatch1Num <= "000";
if (AddrMatch1NumTemp > "000") then
AddrMatch1 <= '1';
AddrMatch1Num <= AddrMatch1NumTemp;
end if;
end process;
process (AddrMatch2NumTemp)
begin
AddrMatch2 <= '0';
AddrMatch2Num <= "000";
if ( AddrMatch2NumTemp > "000") then
AddrMatch2 <= '1';
AddrMatch2Num <= AddrMatch2NumTemp;
end if;
end process;
process (AddrMatch3NumTemp)
begin
AddrMatch3 <= '0';
AddrMatch3Num <= "000";
if (AddrMatch3NumTemp > "000") then
AddrMatch3 <= '1';
AddrMatch3Num <= AddrMatch3NumTemp;
end if;
end process;
process (AddrMatch4NumTemp)
begin
AddrMatch4 <= '0';
AddrMatch4Num <= "000";
if (AddrMatch4NumTemp > "000") then
AddrMatch4 <= '1';
AddrMatch4Num <= AddrMatch4NumTemp;
end if;
end process;
process (AddrMatch5NumTemp)
begin
AddrMatch5 <= '0';
AddrMatch5Num <= "000";
if (AddrMatch5NumTemp > "000") then
AddrMatch5 <= '1';
AddrMatch5Num <= AddrMatch5NumTemp;
end if;
end process;
process (AddrMatch6NumTemp)
begin
AddrMatch6 <= '0';
AddrMatch6Num <= "000";
if (AddrMatch6NumTemp > "000") then
AddrMatch6 <= '1';
AddrMatch6Num <= AddrMatch6NumTemp;
end if;
end process;
process (AddrMatch7NumTemp)
begin
AddrMatch7 <= '0';
AddrMatch7Num <= "000";
if (AddrMatch7NumTemp > "000") then
AddrMatch7 <= '1';
AddrMatch7Num <= AddrMatch7NumTemp;
end if;
end process;
--*************************************************************************************************************
-- This process is used to calculate Rob depth of all entries in address buffer to perform selective flushing in case of
-- branch misprediction. The Rob depth is the distance between the Rob entry of the instruction in the address buffer
-- and the Rob top pointer taking into consideration the fact that ROB is implemented as a circular buffer.
-- Task3: In this task we want to use the RobTag field of each address buffer entry (BuffRobTag array) to calculate
-- the Rob depth field of each entry (BufferDepth array).
--*************************************************************************************************************
process (BuffRobTag,Rob_TopPtr) --using buffer tag and rob pointer
begin
for i in 0 to 7 loop
BufferDepth(i) <= unsigned(BuffRobTag(i)) - unsigned(Rob_TopPtr);
end loop;
end process;
--********************************************************************************************************************
-- The value of the Depth you calculated in the previous process is used to decide whether the address buffer entry
-- must be flushed in case of branch misprediction or not. This of course depends on the Rob Depth of the mispredicted
-- branch and Rob Depth of the store instruction in the address buffer. When the branch Rob depth is smaller than the
-- Rob depth of address buffer entry then that entry is younger than the branch and hence must be flushed. This is known as
-- selective Flushing and is done once the branch instruction appears on Cdb and is mispredicted.
-- The following process is a very important process which takes care of generating the Flush signal of every
-- entry in the address buffer. There are two reasons for flushing address buffer entries:
-- 1) Selective flushing due to branch misprediction provided that the entry Rob depth is larger than that of the
-- mispredicted branch.
-- 2) When a store instruction writes to the cache and leaves the store buffer, we need to flush the corresponding
-- entry of that store in the address buffer. In this case need to use the SBTag to identify the address buffer
-- entry that must be flushed becasue the RobTag is released when the store instruction leaves the top of the
-- and enters the store buffer.
-- Task4: Write the code of the flushing process:
-- Hints: 1. Cdb_RobDepth in the sensitivity list is the Rob depth of the instruction that is currently on Cdb, so before decide
-- if you need to flush or not, you have to check Cdb_Flush input signal that indicates that the instruction on Cdb is
-- a mispredicted branch.
-- 2. You need to check the TagSel when you flush. if you are doing selective flushing and TagSel of one entry is set to 1
-- then there is no need to flush that entry because it belongs to a store instruction that has already left ROB and is
-- waiting in the store buffer to write to the cache. The same thing happen when you are flushing the entry of the store
-- which just finished writing to the cache, you need to check the TagSel, if it set to 0 then that entry belongs to a store
-- instruction which still in the ROB and hence it can NOT be the desired entry.
-- 3. There is only a single Flush bit per address buffer entry. This is enough because once a store instruction leaves ROB it
-- should never be flushed due to mis-prediction buffer but it needs to be flushed when the store leaves store buffer. This means
-- you can check both flush conditions mentioned above concurrently for each address buffer entry but at most one of the conditions
-- will set the Flush bit of that entry.
-- Flush(8) Special Case: Although we have 8 entries in address buffer and hence we just need 8-bit Flush signal (Flush[7:0]), we
-- one more additional bit namely (Flush[8]) to count for the case when a new store instruction is writing its address to the address
-- buffer at the same time when the Cdb_Flush signal becomes active. This case is already completed for you.
--********************************************************************************************************************
Flush(8) <= '1' when ((StrAddr = '1') AND (((unsigned(LsqSwAddr(36 downto 32))-unsigned(Rob_TopPtr))>Cdb_RobDepth)and Cdb_Flush = '1'))
else '0';
process (Cdb_Flush,Cdb_RobDepth,SB_FlushSw,SB_FlushSwTag,BufferDepth,BuffSBTag,BuffTagSel)
begin
for i in 0 to 7 loop
if (BufferDepth(i) > Cdb_RobDepth and Cdb_Flush = '1' and BuffTagSel(i) = '0') then
Flush(i) <= '1';
elsif (SB_FlushSw = '1' and SB_FlushSwTag = BuffSBTag(i) and BuffTagSel(i) = '1') then
Flush(i) <= '1';
else
Flush(i) <= '0';
end if;
end loop;
end process;
-- **************************************************************************************************
-- This process generates the shift enable signal that shifts all the entries in the address buffer.
-- As soon as you get a hole (empty entry) you shift all the upper entries down to fill it so that
-- A new entry is always written to the topmost location
-- **************************************************************************************************
process ( BufValid )
begin
if (BufValid(0) = '0') then
En(6 downto 0) <= "1111111"; --bottom is invalid(issued) so update all
elsif(BufValid(1) = '0') then
En(6 downto 0) <= "1111110";
elsif (BufValid(2) = '0' ) then
En(6 downto 0) <= "1111100";
elsif(BufValid(3) = '0') then
En(6 downto 0) <= "1111000";
elsif (BufValid(4) = '0' ) then
En(6 downto 0) <= "1110000";
elsif(BufValid(5) = '0') then
En(6 downto 0) <= "1100000";
elsif (BufValid(6) = '0' ) then
En(6 downto 0) <= "1000000";
else
En(6 downto 0) <= "0000000"; -- since except the top most others contain valid instruction so can't update, actually this allows the valid instruction to shift down
end if;
end process;
--if all entries are valid then address buffer full
AddrBuffFull <= Bufvalid(7) and BufValid(6) and Bufvalid(5) and Bufvalid(4) and BufValid(3)
and BufValid(2) and BufValid(1) and BufValid(0);
-- **************************************************************************************************
-- This is core clocked process used to update the address buffer entries. At Reset we set the Valid and the TagSel bits to '0'.
-- Since new store instructions write to the top most entry (entry(7)), we have a separate if statement for entry 7. For all other
-- entries (entry(6) to entry(0) we use a for loop.
-- Task5 is divided into two parts:
-- 1) You need to complete the last elsif condition for address buffer entry(7). This condition handles the communication
-- with the ROB. Basically you need to decide how should you update the different fields of address buffer entry(7) especially
-- SBTag field and TagSel field.
-- 2) You need to complete the else codition in for loop below. This else condition handle the case when no shift is required. How
-- would you update the different fields of the address buffer entries(6 to 0).
-- Hint: In Both parts give careful thinking on what you are going to write in SBTag and TagSel fields. You may need to include a nested
-- if statement.
-- **************************************************************************************************
process (Clk,Resetb)
begin
if (Resetb = '0') then
BufValid <= "00000000";
BuffTagSel <= "00000000";
elsif (Clk'event and Clk = '1') then
-- store the "sw" information always at the top
if (Flush(8) = '1') then ---if it's to be flushed don't update
BuffAdd(7) <= (others => '0');
BuffRobTag(7) <= (others => '0');
BufValid(7) <= '0';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (straddr = '1') then ---else put the incoming value on the top location.
BuffAdd(7) <= LsqSwAddr( 31 downto 0 );
BuffRobTag(7) <= LsqSwAddr( 36 downto 32 );
BufValid(7) <= '1';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (En(6) = '1') then ---else the next person is getting my values so I must go empty.
BuffAdd(7) <= (others => '0');
BuffRobTag(7) <= (others => '0');
BufValid(7) <= '0';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (Flush(7) = '1') then ---there is an instruction at the 7th location that is decided to be flushed. Mod25Jul09.
BuffAdd(7) <= (others => '0');
BuffRobTag(7) <= (others => '0');
BufValid(7) <= '0';
BuffSBTag(7) <= (others => '0');
BuffTagSel(7) <= '0';
elsif (Rob_CommitMemWrite = '1') then
if (BuffRobTag(7) = Rob_TopPtr and (BuffTagSel(7) = '0')) then
BuffSBTag(7) <= SBTag_counter;
BuffTagSel(7) <= '1';
end if;
end if;
for i in 0 to 6 loop --shift the others accordingly
if (Flush(i) = '1' and En(i) = '0') then
BuffAdd(i) <= (others => '0');
BuffRobTag(i) <= (others => '0');
BufValid(i) <= '0';
BuffSBTag(i) <= (others => '0');
BuffTagSel(i) <= '0';
else
if (En(i) = '1') then --shift update
BuffAdd(i) <= BuffAdd(i+1);
BuffRobTag(i) <= BuffRobTag(i+1);
BufValid(i) <= BufValid(i+1) and (not Flush(i+1)); --update , note the use of flush signal while updation
if ((Rob_CommitMemWrite = '1') and (BuffRobTag(i+1) = Rob_TopPtr) and (BuffTagSel(i+1) = '0'))then
BuffSBTag(i) <= SBTag_counter;
BuffTagSel(i) <= '1';
else
BuffSBTag(i) <= BuffSBTag(i+1);
BuffTagSel(i) <= BuffTagSel(i+1);
end if;
else
if (BuffRobTag(i) = Rob_TopPtr and (BuffTagSel(i) = '0') and (Rob_CommitMemWrite = '1')) then
BuffSBTag(i) <= SBTag_counter;
BuffTagSel(i) <= '1';
end if;
end if;
end if;
end loop;
end if;
end process;
end behave;
|
gpl-2.0
|
46316d0198f6da30b0ac937b42712794
| 0.542832 | 4.372734 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/TargetCmdFIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,305 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT TargetCmdFIFO_top IS
PORT (
CLK : IN std_logic;
ALMOST_FULL : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
3028654c5034c60a1742a3041e946aee
| 0.504113 | 3.940397 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/cont255_V4.vhd
| 1 | 3,927 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont255_V4.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity cont255_V4 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
set_zero: in std_logic;
start: in STD_LOGIC;
fin : out STD_LOGIC
);
end cont255_V4;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of cont255_V4 is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal reg_cuenta: std_logic_vector(7 downto 0);
signal reg_cuenta_in: std_logic_vector(7 downto 0);
signal lim_cuenta: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT incrementadorCuenta8bits
PORT(
num_in : IN std_logic_vector(7 downto 0);
num_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
fin <= lim_cuenta;
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
incr_0: incrementadorCuenta8bits PORT MAP(
num_in => reg_cuenta,
num_out => reg_cuenta_in
--fin => disconnected
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_cuenta: process(rst, clk, start)
begin
if rst = '1' then
reg_cuenta <= (others => '0');
lim_cuenta <= '0';
elsif rising_edge(clk) then
if set_zero = '1' then
reg_cuenta <= (others => '0');
lim_cuenta <= '0';
elsif reg_cuenta = "10001010" then
lim_cuenta <= '1';
reg_cuenta <= reg_cuenta;
elsif start = '1' then --!!!
lim_cuenta <= '0';
reg_cuenta <= reg_cuenta_in; -- cuenta++
else
lim_cuenta <= lim_cuenta;
reg_cuenta <= reg_cuenta;
end if;
end if;
end process p_cuenta;
end rtl;
|
gpl-3.0
|
c3ebfca15b0b3a1193d554f40b0eb8f6
| 0.412994 | 4.993639 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/ram_control.vhd
| 1 | 8,256 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- ram_control.vhd
--
--
-- Memory arbitrator. Handle access to memory. Control the FIFOs in other modules
-- Incorporates SDRAM controller.
--**********************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.common.all;
use work.comp_pckgs.all;
ENTITY ram_control IS
PORT
(
clk_50Mhz: in std_logic;
rst: in std_logic;
-- PP RAM access. Control provided by MCSG
pp_data_out : out std_logic_vector(15 downto 0);
start_upload : in std_logic;
abort_upload : in std_logic;
start_addr_upload : in std_logic_vector(22 downto 0);
end_addr_upload : in std_logic_vector(22 downto 0);
pp_fifo_wr_en : out std_logic;
pp_fifo_need_data : in std_logic;
-- KAC RAM access
rd_en_KAC : out std_logic;
dout_KAC : in std_logic_vector(15 downto 0);
dump_data_req_KAC : in std_logic;
start_new_frame : in std_logic;
-- SDRAM side
cke: out std_logic; -- clock-enable to SDRAM
cs_n: out std_logic; -- chip-select to SDRAM
ras_n: out std_logic; -- command input to SDRAM
cas_n: out std_logic; -- command input to SDRAM
we_n: out std_logic; -- command input to SDRAM
ba: out unsigned(1 downto 0); -- SDRAM bank address bits
sAddr: out unsigned(12-1 downto 0); -- SDRAM row/column address
sData: inout unsigned(16-1 downto 0); -- SDRAM in/out databus
dqmh: out std_logic; -- high databits I/O mask
dqml: out std_logic -- low databits I/O mask
);
END ram_control;
ARCHITECTURE ram_control_arch OF ram_control IS
-- Constants
constant HRES : natural := 1280;
constant VRES : natural := 1024;
--Flags pport, misc
signal uploading : std_logic;
signal pp_addr_pointer : unsigned(19 downto 0);
signal pp_ram_page : unsigned(2 downto 0); --Current readout page
signal ram_page_full : unsigned(2 downto 0); --Complete frame
signal ram_addr : unsigned(22 downto 0);
type semaphore is (NOBODY, KAC, PPORT);
signal SDRAM_used_by : semaphore;
--KAC signals
signal addr_ptr_KAC : unsigned(19 downto 0);
signal ram_page_KAC : unsigned(2 downto 0); --Current writeout page
--SDRAM Signals and constants
signal rd, rd_next : std_logic;
signal wr : std_logic;
signal done : std_logic;
signal hDOut : unsigned(16-1 downto 0); -- Type conversion
signal sdramCntl_state : std_logic_vector(3 downto 0);
BEGIN
pp_fifo_wr_en <= '1' when done = '1' and rd = '1' else '0';
rd_en_KAC <= '1' when done = '1' and wr = '1' else '0';
pp_data_out <= std_logic_vector(hDOut); --Conversions are fun!
-- The rd_en for the KAC_data fifo also can enable the write for the memory.
-- Data in: Enable KAC_data fifo read and RAM Write
-- Data out: Enable PP_Fifo write and RAM read
-- B5 : block_ram_2kx16
-- port map
-- (
-- addr => std_logic_vector(ram_addr(10 downto 0)),
-- clk => clk_50Mhz,
-- sinit => not_rst,
-- din => dout_KAC,
-- dout => pp_data_out,
-- we => rd_en_KAC_sig
-- );
-- SDRAM memory controller module
u1: sdramCntl
generic map(
FREQ => 50_000, -- 50 MHz operation
DATA_WIDTH => 16,
HADDR_WIDTH => 23,
SADDR_WIDTH => 12
)
port map(
clk => clk_50Mhz, -- master clock
rst => rst, -- active high reset
rd => rd, -- SDRAM read control
wr => wr, -- SDRAM write control
done => done, -- SDRAM memory read/write done indicator
hAddr => ram_addr, -- host-side address from memory tester
hDIn => unsigned(dout_KAC), -- Data into sdram controller
hDOut => hDOut, -- data from SDRAM
sdramCntl_state => sdramCntl_state, -- (for testing)
cke => cke, -- SDRAM clock enable
cs_n => cs_n, -- SDRAM chip-select
ras_n => ras_n, -- SDRAM RAS
cas_n => cas_n, -- SDRAM CAS
we_n => we_n, -- SDRAM write-enable
ba => ba, -- SDRAM bank address
sAddr => sAddr, -- SDRAM address
sData => sData, -- SDRAM databus
dqmh => dqmh, -- SDRAM DQMH
dqml => dqml -- SDRAM DQML
);
-- Determine which address to use for ram
ram_addr <= (others=>'0') when rst = '0' else
ram_page_KAC & addr_ptr_KAC when wr = '1' else
pp_ram_page & pp_addr_pointer;
-- Page the memory to prevent over writing
ram_page: process (rst, clk_50Mhz, start_new_frame, ram_page_full, pp_ram_page,
ram_page_KAC, start_upload ) is
--Do I need to make a temp variable for the swap? NOPE!
begin
if rst = '0' then
ram_page_KAC <= "000";
ram_page_full <= "001";
pp_ram_page <= "010";
elsif clk_50Mhz'event and clk_50Mhz = '1' then
-- They both could happen in the same 50Mhz clock. unlikely,
-- but possible
if start_new_frame = '1' and start_upload = '1' then
pp_ram_page <= ram_page_KAC;
elsif start_new_frame = '1' then
ram_page_full <= ram_page_KAC;
ram_page_KAC <= ram_page_full;
elsif start_upload = '1' then
pp_ram_page <= ram_page_full;
ram_page_full <= pp_ram_page;
end if;
end if;
end process ram_page;
-- Control access to the SDRAM with a semaphore. When a FIFO request action,
-- respond by locking control of the memory, or waiting. If memory is
-- available, signal the fifo to start transfering, and set SDRAM control
-- bits rd and wr.
sem_control: process(clk_50Mhz, rst, SDRAM_used_by, pp_fifo_need_data,
dump_data_req_KAC, uploading, addr_ptr_KAC) is
begin
if rst='0' then
rd_next <= '0';
rd <= '0';
SDRAM_used_by <= NOBODY;
wr <= '0';
else
--take semaphore
if pp_fifo_need_data = '1' and uploading = '1'
and (SDRAM_used_by = NOBODY or SDRAM_used_by = PPORT) then
SDRAM_used_by <= PPORT;
rd_next <= '1'; --SDRAM read
elsif dump_data_req_KAC = '1'
and (SDRAM_used_by = NOBODY or SDRAM_used_by = KAC) then
SDRAM_used_by <= KAC;
wr <= '1';
else
-- Default values if not specified below
-- Done with transfer, release control of memory
-- or it's not needed
rd_next <= '0';
wr <= '0';
SDRAM_used_by <= NOBODY;
end if;
-- Delay the pp_fifo_wr_en signal by one clock to account for delay
if clk_50Mhz'event and clk_50Mhz = '1' then
rd <= rd_next;
end if;
end if;
end process sem_control;
-- Control the KAC address pointer. Reset it when a new frame is signaled.
-- Only increment it once after a write is completed. Prevent writing into
-- next frame if there is no new frame signal
KAC_fifo_empty: process(clk_50Mhz, rst, start_new_frame, wr, done,
addr_ptr_KAC ) is
begin
if rst='0' then
addr_ptr_KAC <= (others=>'0');
elsif clk_50Mhz'event and clk_50Mhz='1' then
if start_new_frame = '1' then
addr_ptr_KAC <= (others=>'0');
elsif wr = '1' and done = '1' then
if addr_ptr_KAC < 655360 then -- Don't wrap around
addr_ptr_KAC <= addr_ptr_KAC + 1;
end if;
end if;
end if;
end process KAC_fifo_empty;
-- When the fifo needs data, check to see if memory is available, then set the
-- write flag and start clocking data at the fifo until it lowers need_data.
-- Update process to add new sdram stuff. Control how the address for the pport
-- is set
pp_fifo_fill: process(clk_50Mhz, rst, pp_fifo_need_data, start_upload,
abort_upload, start_addr_upload, end_addr_upload, pp_addr_pointer) is
begin
if rst='0' then
pp_addr_pointer <= (others=>'0');
uploading <= '0';
else
--clocked events
if clk_50Mhz'event and clk_50Mhz='1' then
if start_upload = '1' then
uploading <= '1';
pp_addr_pointer <= unsigned(start_addr_upload(19 downto 0));
elsif abort_upload = '1' or pp_addr_pointer >
unsigned(end_addr_upload(19 downto 0)) then
uploading <= '0';
pp_addr_pointer <= (others=>'0');
-- Inc on done signal generated by sdram
elsif rd = '1' and done = '1' then
pp_addr_pointer <= pp_addr_pointer + 1;
end if;
end if;
end if;
end process pp_fifo_fill;
END ram_control_arch;
|
gpl-3.0
|
985d018f9e39bf45fcda86dcb41f17c9
| 0.613251 | 2.976208 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Finished_Cmd_FIFO/example_design/Finished_Cmd_FIFO_top.vhd
| 1 | 4,819 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Finished_Cmd_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Finished_Cmd_FIFO_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end Finished_Cmd_FIFO_top;
architecture xilinx of Finished_Cmd_FIFO_top is
SIGNAL clk_i : std_logic;
component Finished_Cmd_FIFO is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : Finished_Cmd_FIFO PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
3821176795141a65bd2e9cd42fc51f9a
| 0.52874 | 4.947639 | false | false | false | false |
tuura/fantasi
|
dependencies/FSM.vhdl
| 1 | 3,594 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY FSM IS
GENERIC (DATA_WIDTH : integer := 19;
NODES : integer := 15);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
GO : IN std_logic;
COMPL : OUT std_logic;
EN_NODES: in std_logic_vector(NODES-1 downto 0);
RESULT : OUT std_logic_vector(DATA_WIDTH downto 0));
END FSM;
ARCHITECTURE FSM_S OF FSM IS
COMPONENT FANTASI IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
RST_SHIFT : IN std_logic;
EN : IN std_logic;
EN_NODES : IN std_logic_vector(NODES-1 downto 0);
START : IN std_logic;
DIN : IN std_logic;
DONE : OUT std_logic;
COMPLETE : OUT std_logic;
RESULT : OUT std_logic_vector(DATA_WIDTH-1 downto 0));
END COMPONENT;
COMPONENT Generic_accumulator IS
GENERIC (N : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT: OUT std_logic_vector(N downto 0));
END COMPONENT;
type state is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal CR, NX: state;
signal en, start, din, rstf, rsts, complete, done, sum : std_logic;
signal res : std_logic_vector(DATA_WIDTH-1 downto 0);
BEGIN
process (CLK,RST)
begin
if (RST='1') then
CR <= S0;
elsif (CLK'event and CLK='1') then
CR <= NX;
end if;
end process;
process (CR, GO, complete, done)
begin
case CR is
when S0 =>
rstf <= '0';
rsts <= '0';
start <= '0';
din <= '0';
en <= '0';
sum <= '0';
NX <= S1;
when S1 =>
rstf <= '1';
rsts <= '1';
start <= '0';
din <= '0';
en <= '0';
sum <= '0';
if GO = '1' then
NX <= S2;
else
NX <= S1;
end if;
when S2 =>
rstf <= '0';
rsts <= '0';
start <= '1';
din <= '1';
en <= '1';
sum <= '0';
NX <= S3;
when S3 =>
rstf <= '0';
rsts <= '0';
start <= '1';
din <= '1';
en <= '1';
sum <= '0';
if (done = '1') then
NX <= S4;
else
NX <= S3;
end if;
when S4 =>
rstf <= '0';
rsts <= '0';
start <= '0';
din <= '0';
en <= '1';
sum <= '1';
NX <= S5;
when S5 =>
rstf <= '1';
rsts <= '0';
start <= '0';
din <= '0';
en <= '1';
sum <= '0';
NX <= S6;
when S6 =>
rstf <= '0';
rsts <= '0';
start <= '0';
din <= '0';
en <= '1';
sum <= '0';
NX <= S7;
when S7 =>
rstf <= '0';
rsts <= '0';
start <= '1';
din <= '0';
en <= '1';
sum <= '0';
NX <= S8;
when S8 =>
rstf <= '0';
rsts <= '0';
start <= '1';
din <= '0';
en <= '1';
sum <= '0';
if (complete = '1') then
NX <= S9;
elsif (done = '1') then
NX <= S4;
else
NX <= S8;
end if;
when S9 =>
rstf <= '0';
rsts <= '0';
start <= '1';
din <= '0';
en <= '1';
sum <= '0';
NX <= S9;
end case;
end process;
TEST_STRUCTURE : FANTASI
PORT MAP(
CLK => CLK,
RST => rstf,
RST_SHIFT => rsts,
EN => en,
EN_NODES => EN_NODES,
START => start,
DIN => din,
DONE => done,
COMPLETE => complete,
RESULT => res);
ACCUMULATOR : Generic_accumulator
GENERIC MAP(DATA_WIDTH)
PORT MAP(
CLK => CLK,
RST => RST,
EN => sum,
DIN => res,
DOUT => RESULT);
COMPL <= complete;
END FSM_S;
|
mit
|
f9f18620b3befb0387da720d9e2dd222
| 0.443517 | 2.421833 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/rs232_sender.vhd
| 1 | 3,561 |
-- RS232 sender with Wishbone slave interface and fixed, but generic,
-- baudrate and 8N1 mode.
--
-- The master sends data to this slave by setting dat_i to the byte to send
-- and stb_i to 1 at the rising edge of clk_i. This slave acknowledge the
-- request with ack_o = 1 at the next rising edge of clk_i. Then the master
-- resets stb_i to 0 and the slave acknowledges this by setting ack_o to 0.
-- The slave acknowledges the next stb_i signal after the current byte is
-- sent to the RS232 port.
--
-- Supported Whishbone cycles: SLAVE, WRITE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rs232_sender is
generic(
system_speed, -- clk_i speed, in hz
baudrate: integer); -- baudrate, in bps
port(
ack_o: out std_logic; -- Wishbone ACK_O signal
clk_i: in std_logic; -- Wishbone CLK_i signal
dat_i: in unsigned(7 downto 0); -- Wishbone DAT_i signal
rst_i: in std_logic; -- Wishbone RST_i signal
stb_i: in std_logic; -- Wishbone STB_i signal
tx: out std_logic); -- RS232 transmit pin
end entity rs232_sender;
architecture rtl of rs232_sender is
constant max_counter: natural := system_speed / baudrate;
type state_type is (
wait_for_strobe,
send_start_bit,
send_bits,
send_stop_bit);
signal state: state_type := wait_for_strobe;
signal baudrate_counter: natural range 0 to max_counter := 0;
signal bit_counter: natural range 0 to 7 := 0;
signal shift_register: unsigned(7 downto 0) := (others => '0');
signal data_sending_started: std_logic := '0';
begin
-- acknowledge, when sending process was started
ack_o <= data_sending_started and stb_i;
update: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
tx <= '1';
data_sending_started <= '0';
state <= wait_for_strobe;
else
case state is
-- wait until the master asserts valid data
when wait_for_strobe =>
if stb_i = '1' then
state <= send_start_bit;
baudrate_counter <= max_counter - 1;
tx <= '0';
shift_register <= dat_i;
data_sending_started <= '1';
else
tx <= '1';
end if;
when send_start_bit =>
if baudrate_counter = 0 then
state <= send_bits;
baudrate_counter <= max_counter - 1;
tx <= shift_register(0);
bit_counter <= 7;
else
baudrate_counter <= baudrate_counter - 1;
end if;
when send_bits =>
if baudrate_counter = 0 then
if bit_counter = 0 then
state <= send_stop_bit;
tx <= '1';
else
tx <= shift_register(1);
shift_register <= shift_right(shift_register, 1);
bit_counter <= bit_counter - 1;
end if;
baudrate_counter <= max_counter - 1;
else
baudrate_counter <= baudrate_counter - 1;
end if;
when send_stop_bit =>
if baudrate_counter = 0 then
state <= wait_for_strobe;
else
baudrate_counter <= baudrate_counter - 1;
end if;
end case;
-- this resets acknowledge until all bits are sent
if stb_i = '0' and data_sending_started = '1' then
data_sending_started <= '0';
end if;
end if;
end if;
end process;
end architecture rtl;
|
mit
|
6453219bb151511e09c41f4b74964c33
| 0.565852 | 3.913187 | false | false | false | false |
chronos38/DSD-Projekt
|
dezctr/dezctr_struc.vhd
| 1 | 2,912 |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture behavioral of dezctr is
component ioctrl
port (
clk50 : in std_logic;
reset_n : in std_logic;
sw_i : in std_logic_vector(9 downto 0);
pb_i : in std_logic_vector(1 downto 0);
cntr0 : in std_logic_vector(3 downto 0);
cntr1 : in std_logic_vector(3 downto 0);
cntr2 : in std_logic_vector(3 downto 0);
cntr3 : in std_logic_vector(3 downto 0);
ss0_o : out std_logic_vector(7 downto 0);
ss1_o : out std_logic_vector(7 downto 0);
ss2_o : out std_logic_vector(7 downto 0);
ss3_o : out std_logic_vector(7 downto 0);
swsync_o : out std_logic_vector(9 downto 0);
pbsync_o : out std_logic_vector(1 downto 0));
end component;
component cntr
port (
clk50 : in std_logic;
reset_n : in std_logic;
ctup_i : in std_logic;
ctdown_i : in std_logic;
ctreset_i : in std_logic;
cthold_i : in std_logic;
cntr0_o : out std_logic_vector(3 downto 0);
cntr1_o : out std_logic_vector(3 downto 0);
cntr2_o : out std_logic_vector(3 downto 0);
cntr3_o : out std_logic_vector(3 downto 0));
end component;
signal s_swsync_o : std_logic_vector(9 downto 0) := (others => '0');
signal s_pbsync_o : std_logic_vector(1 downto 0) := (others => '0');
signal s_cntr0,s_cntr1,
s_cntr2,s_cntr3 : std_logic_vector(3 downto 0) := (others => '0');
begin
i_ioctrl : ioctrl
port map(
clk50 => clk50,
reset_n => reset_n,
sw_i => sw_i,
pb_i => pb_i,
cntr0 => s_cntr0,
cntr1 => s_cntr1,
cntr2 => s_cntr2,
cntr3 => s_cntr3,
ss0_o => ss0_o,
ss1_o => ss1_o,
ss2_o => ss2_o,
ss3_o => ss3_o,
swsync_o => s_swsync_o,
pbsync_o => s_pbsync_o
);
i_cntr : cntr
port map(
clk50 => clk50,
reset_n => reset_n,
ctup_i => s_pbsync_o(0),
ctdown_i => s_pbsync_o(1),
ctreset_i=> s_swsync_o(0),
cthold_i => s_swsync_o(1),
cntr0_o => s_cntr0,
cntr1_o => s_cntr1,
cntr2_o => s_cntr2,
cntr3_o => s_cntr3
);
end architecture;
|
gpl-3.0
|
7d5e2c4cebfed00d1d149e1a5544e4f7
| 0.442995 | 3.446154 | false | false | false | false |
csrhau/sandpit
|
VHDL/clocked_enable/clocked_enable.vhdl
| 1 | 557 |
library ieee;
use ieee.std_logic_1164.all;
entity clocked_enable is
generic (period : integer);
port (clock : in std_logic;
enable: out std_logic :='0');
end clocked_enable;
architecture behavioural of clocked_enable is
signal pcount : integer range period-1 downto 0 := 0;
begin
process(clock)
begin
if rising_edge(clock) then
if pcount = period - 1 then
enable <= '1';
pcount <= 0;
else
enable <= '0';
pcount <= pcount + 1;
end if;
end if;
end process;
end behavioural;
|
mit
|
604b7376fa1a1a89a5ccefd65e5b745d
| 0.610413 | 3.763514 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_sort.vhd
| 3 | 12,125 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"00000020_00BF1019_0080F820_00000020", -- Loc 0C, 08, 04, 00
X"10C0000C_0082302A_007F2020_00001820", -- Loc 1C, 18, 14, 10
X"10C00002_01CD302A_8C8E0000_8C6D0000", -- Loc 2C, 28, 24, 20
X"009F2020_007F1820_AC8D0000_AC6E0000", -- Loc 3C, 38, 34, 30
X"08000004_005F1022_10C1FFF6_0082302A", -- Loc 4C, 48, 44, 40
X"00BFE019_035FD820_0000D020_00000020", -- Loc 5C, 58, 54, 50
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 6C, 68, 64, 60
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 7C, 78, 74, 70
X"00000020_00000020_1000FFF7_137C0001", -- Loc 8C, 88, 84, 80
X"01215020_00BF4820_00A01020_00000020", -- Loc 9C, 98, 94, 90
X"007F6819_00612020_00A01820_00003020", -- Loc AC, A8, A4, A0
X"009F7019_02E0B020_01A06020_8DB70000", -- Loc BC, B8, B4, B0
X"01C06020_10C00002_0316302A_8DD80000", -- Loc CC, C8, C4, C0
X"1000FFF7_108A0001_00812020_0300B020", -- Loc DC, D8, D4, D0
X"00611820_AD970001_ADB60001_00000020", -- Loc EC, E8, E4, E0
X"00000020_1000FFEC_10690001_00612020", -- Loc FC, F8, F4, F0
X"00BFE019_035FD820_00BFD019_00000020", -- Loc 10C, 108, 104, 100
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 11C, 118, 114, 110
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 12C, 128, 124, 120
X"00000020_00000020_1000FFF7_137C0001", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- BUBBLE SORT & SELECTION SORT
--
-- Preconditions on Register file
-- Registers set to their register number
-- ex) $0 = 0, $1 = 1, $2 = 2 ...... $31 = 31
-- Preconditions on Data Memory
-- None. Any data in the first 5 locations will be sorted by Bubble sort.
-- The next 5 data will be sorted by Selection sort.
--
-- Author: Byung-Yeob Kim, EE560 TA
-- Modified: Aug-01-2008
-- University of Southern California
--
--000 00000020 add $0, $0, $0 -- nop *** INITIALIZATION FOR BUBBLE SORT ***
--004 0080F820 add $31, $4, $0 -- $31 = 4
--008 00BF1019 mul $2, $5, $31 -- ak = 4 * num_of_items
--00c 00000020 add $0, $0, $0 -- noop
--
--010 00001820 add $3, $0, $0 -- ai = 0 *** BUBBLE SORT STARTS ***
--014 007F2020 add $4, $3, $31 -- aj = ai + 4
--018 0082302A slt $6, $4, $2 -- (aj < ak) ?
--01c 10C0000C beq $6, $0, 12 -- if no, program finishes. goto chcker
--
--020 8C6D0000 lw $13, 0($3) -- mi = M(ai) (LABEL: LOAD)
--024 8C8E0000 lw $14, 0($4) -- mj = M(aj)
--028 01CD302A slt $6, $14, $13 -- (mj < mi) ?
--02c 10C00002 beq $6, $0, 2 -- if no, skip swap
--
--030 AC6E0000 sw $14, 0($3) -- M(ai) = mj // swap
--034 AC8D0000 sw $13, 0($4) -- M(aj) = mi // swap
--038 007F1820 add $3, $3, $31 -- ai = ai + 4 (LABEL: SKIP SWAP)
--03c 009F2020 add $4, $4, $31 -- aj = aj + 4
--
--
--040 0082302A slt $6, $4, $2 -- (aj < ak) ?
--044 10C1FFF6 beq $6, $1, -10 -- if yes, goto LOAD
--048 005F1022 sub $2, $2, $31 -- ak = ak - 4
--04c 08000004 jmp 4 -- goto BEGIN
--
--050 00000020 add $0, $0, $0 -- nop *** CHECKER FOR FIRST 5 ITEMS ***
--054 0000D020 add $26, $0, $0 -- addr1 = 0
--058 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--05c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--060 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--064 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--068 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ?
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data
--074 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--078 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--07c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--
--080 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--084 1000FFF7 beq $0, $0, -9 -- else test next data
--088 00000020 add $0, $0, $0 -- noop
--08c 00000020 add $0, $0, $0 -- noop
--
--090 00000020 add $0, $0, $0 -- nop *** INITIALIZATION FOR SELECTION SORT ***
--094 00A01020 add $2, $5, $0 -- set min = 5
--098 00BF4820 add $9, $5, $31 -- $9 = 9
--09c 01215020 add $10, $9, $1 -- $10 = 10
--
--0A0 00003020 add $6, $0, $0 -- slt_result = 0
--0A4 00A01820 add $3, $5, $0 -- i = 5
--0A8 00612020 add $4, $3, $1 -- j = i+1 *** SELECTION SORT STARTS HERE ***
--0Ac 007F6819 mul $13, $3, $31 -- ai = i*4
--
--0B0 8DB70000 lw $23, 0($13) -- mi = M(ai)
--0B4 01A06020 add $12, $13, $0 -- amin = ai
--0B8 02E0B020 add $22, $23, $0 -- mmin = mi
--0Bc 009F7019 mul $14, $4, $31 -- aj = j*4
--
--
--0C0 8DD80000 lw $24, 0($14) -- mj = M(aj)
--0C4 0316302A slt $6, $24, $22 -- (mj < mmin)
--0C8 10C00002 beq $6, $0, 2 -- if(no)
--0Cc 01C06020 add $12, $14, $0 -- amin = aj
--
--0D0 0300B020 add $22, $24, $0 -- mmin = mj
--0D4 00812020 add $4, $4, $1 -- j++
--0D8 108A0001 beq $4, $10, 1 -- (j = 10)
--0Dc 1000FFF7 beq $0, $0, -9 -- if(no)
--
--0E0 00000020 add $0, $0, $0 -- nop
--0E4 ADB60001 sw $22, 0 ($13) -- M(ai) = mmin // swap
--0E8 AD970001 sw $23, 0 ($12) -- M(amin) = mi // swap
--0Ec 00611820 add $3, $3, $1 -- i++
--
--0F0 00612020 add $4, $3, $1 -- j = i+1
--0F4 10690001 beq $3, $9, 1 -- (i==9)
--0F8 1000FFEC beq $0, $0, -20 -- if(no)
--0Fc 00000020 add $0, $0, $0 -- nop
--
--
--100 00000020 add $0, $0, $0 -- *** CHECKER FOR THE NEXT 5 ITEMS ***
--104 00BFD019 mul $26, $5, $31 -- addr1 = num_of_items * 4
--108 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--10c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--110 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--114 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--118 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ? -- corrected
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data -- corrected
--124 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--128 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--12c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--130 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--134 1000FFF7 beq $0, $0, -9 -- else test next data
--138 00000020 add $0, $0, $0 -- noop
--13c 00000020 add $0, $0, $0 -- noop
--
--
--REG FILE USED BY BUBBLE SORT
--Initilaly, the content of a register is assumed to be same as its register number.
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> ak address of k
--$3 ----> ai address of i
--$4 ----> aj address of j
--$5 ----> 5 num_of_items (items at location 0~4 will be sorted)
--$6 ----> result_of_slt
--$13 ----> mi M(ai)
--$14 ----> mj M(aj)
--$25~$30 -> RESERVED for the checker
--$31 ----> 4 conatant for calculating word address
--
--REG FILE USED BY SELECTION SORT
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> min index of the minimum value
--$3 ----> i index i
--$4 ----> j index j
--$5 ----> 5 num_of_items (items at location 5~9 will be sorted)
--$6 ----> result of slt
--$9 ----> 9 constant
--$10 ----> 10 constant
--$12 ----> amin address of min
--$13 ----> ai address of i
--$14 ----> aj address of j
--$15~$21 -> don't care
--$22 ----> mmin M(amin)
--$23 ----> mi M(ai)
--$24 ----> mj M(aj)
--$25~$30 -> RESERVED for checker
--$31 ----> 4 for calculating word address
--
--REG FILE USED BY CHECKER
--
--$26 ----> addr1 starting point
--$27 ----> addr2 ending point
--$28 ----> addr3 bound
--$29 ----> maddr1 M(addr1)
--$30 ----> maddr2 M(addr2)
--
|
gpl-2.0
|
403eef2a9db4b71592a169a2a764b0ef
| 0.597526 | 2.654335 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_POST_FIFO/simulation/fg_tb_synth.vhd
| 1 | 11,218 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 7,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : WR_FLASH_POST_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
1d7f09fed4b2c5cfd34adaaabe952559
| 0.454894 | 3.965359 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/adder4bits_comb_noCout.vhd
| 1 | 3,506 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: adder4bits_comb_noCout.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity adder4bits_comb_noCout is
port ( A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
Z : out std_logic_vector (3 downto 0)
);
end adder4bits_comb_noCout;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of adder4bits_comb_noCout is
signal c_aux: std_logic_vector(3 downto 0);
-----------------------------------------------------------------------------
-- Componentes auxiliares
-----------------------------------------------------------------------------
component adder1bit_comb
port(
A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Z : out std_logic;
Cout : out std_logic
);
end component;
COMPONENT adder1bit_noCout
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Instacia de componentes
-----------------------------------------------------------------------------
adder_0: adder1bit_comb port map(
A => A(0),
B => B(0),
Cin => c_aux(0),
Z => Z(0),
Cout => c_aux(1)
);
adder_1: adder1bit_comb port map(
A => A(1),
B => B(1),
Cin => c_aux(1),
Z => Z(1),
Cout => c_aux(2)
);
adder_2: adder1bit_comb port map(
A => A(2),
B => B(2),
Cin => c_aux(2),
Z => Z(2),
Cout => c_aux(3)
);
adder_3: adder1bit_noCout PORT MAP(
A => A(3),
B => B(3),
Cin => c_aux(3),
Z => Z(3)
);
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
c_aux(0) <= Cin;
end rtl;
|
gpl-3.0
|
09f5ebc173aa4232b9985138731c3b0c
| 0.425228 | 4.237001 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/read_data_fifo_0/simulation/fg_tb_pkg.vhd
| 1 | 11,539 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT read_data_fifo_0_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
4570c1181065e8faadad1a8154d41b23
| 0.503163 | 3.915507 | false | false | false | false |
tuura/fantasi
|
dependencies/Xilinx_Virtex7/top.vhd
| 1 | 202,654 |
--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.1 (win64) Build 2188600 Wed Apr 4 18:40:38 MDT 2018
--Date : Sat Jun 30 04:03:51 2018
--Host : EEEAYRA04 running 64-bit Service Pack 1 (build 7601)
--Command : generate_target top.bd
--Design : top
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_FAIRLI is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_FAIRLI;
architecture STRUCTURE of m00_couplers_imp_FAIRLI is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m00_couplers_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m00_couplers_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_couplers_to_m00_couplers_BREADY;
M_AXI_rready <= m00_couplers_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_couplers_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_couplers_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_couplers_RVALID;
S_AXI_wready <= m00_couplers_to_m00_couplers_WREADY;
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_couplers_to_m00_couplers_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_couplers_to_m00_couplers_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_couplers_BREADY <= S_AXI_bready;
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY <= S_AXI_rready;
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1T2T38Z is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1T2T38Z;
architecture STRUCTURE of m01_couplers_imp_1T2T38Z is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_O7LC3H is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_O7LC3H;
architecture STRUCTURE of m02_couplers_imp_O7LC3H is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_12IU86W is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_12IU86W;
architecture STRUCTURE of m03_couplers_imp_12IU86W is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_1WPMAOW is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_1WPMAOW;
architecture STRUCTURE of m04_couplers_imp_1WPMAOW is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_BPII3P is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_BPII3P;
architecture STRUCTURE of m05_couplers_imp_BPII3P is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_165ZWTN is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_165ZWTN;
architecture STRUCTURE of m06_couplers_imp_165ZWTN is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m06_couplers_to_m06_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity microblaze_0_local_memory_imp_1PW29UC is
port (
DLMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_addrstrobe : in STD_LOGIC;
DLMB_be : in STD_LOGIC_VECTOR ( 0 to 3 );
DLMB_ce : out STD_LOGIC;
DLMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_readstrobe : in STD_LOGIC;
DLMB_ready : out STD_LOGIC;
DLMB_ue : out STD_LOGIC;
DLMB_wait : out STD_LOGIC;
DLMB_writedbus : in STD_LOGIC_VECTOR ( 0 to 31 );
DLMB_writestrobe : in STD_LOGIC;
ILMB_abus : in STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_addrstrobe : in STD_LOGIC;
ILMB_ce : out STD_LOGIC;
ILMB_readdbus : out STD_LOGIC_VECTOR ( 0 to 31 );
ILMB_readstrobe : in STD_LOGIC;
ILMB_ready : out STD_LOGIC;
ILMB_ue : out STD_LOGIC;
ILMB_wait : out STD_LOGIC;
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC
);
end microblaze_0_local_memory_imp_1PW29UC;
architecture STRUCTURE of microblaze_0_local_memory_imp_1PW29UC is
component top_dlmb_v10_1 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component top_dlmb_v10_1;
component top_ilmb_v10_1 is
port (
LMB_Clk : in STD_LOGIC;
SYS_Rst : in STD_LOGIC;
LMB_Rst : out STD_LOGIC;
M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_ReadStrobe : in STD_LOGIC;
M_WriteStrobe : in STD_LOGIC;
M_AddrStrobe : in STD_LOGIC;
M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_ReadStrobe : out STD_LOGIC;
LMB_WriteStrobe : out STD_LOGIC;
LMB_AddrStrobe : out STD_LOGIC;
LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
LMB_Ready : out STD_LOGIC;
LMB_Wait : out STD_LOGIC;
LMB_UE : out STD_LOGIC;
LMB_CE : out STD_LOGIC;
LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
);
end component top_ilmb_v10_1;
component top_dlmb_bram_if_cntlr_1 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component top_dlmb_bram_if_cntlr_1;
component top_ilmb_bram_if_cntlr_1 is
port (
LMB_Clk : in STD_LOGIC;
LMB_Rst : in STD_LOGIC;
LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
LMB_AddrStrobe : in STD_LOGIC;
LMB_ReadStrobe : in STD_LOGIC;
LMB_WriteStrobe : in STD_LOGIC;
LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
Sl_Ready : out STD_LOGIC;
Sl_Wait : out STD_LOGIC;
Sl_UE : out STD_LOGIC;
Sl_CE : out STD_LOGIC;
BRAM_Rst_A : out STD_LOGIC;
BRAM_Clk_A : out STD_LOGIC;
BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_EN_A : out STD_LOGIC;
BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
);
end component top_ilmb_bram_if_cntlr_1;
component top_lmb_bram_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC
);
end component top_lmb_bram_1;
signal SYS_Rst_1 : STD_LOGIC;
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_dlmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_CE : STD_LOGIC;
signal microblaze_0_dlmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_READY : STD_LOGIC;
signal microblaze_0_dlmb_UE : STD_LOGIC;
signal microblaze_0_dlmb_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_bus_CE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_bus_READY : STD_LOGIC;
signal microblaze_0_dlmb_bus_UE : STD_LOGIC;
signal microblaze_0_dlmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_dlmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_dlmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_CE : STD_LOGIC;
signal microblaze_0_ilmb_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_READY : STD_LOGIC;
signal microblaze_0_ilmb_UE : STD_LOGIC;
signal microblaze_0_ilmb_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_ilmb_bus_CE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_bus_READY : STD_LOGIC;
signal microblaze_0_ilmb_bus_UE : STD_LOGIC;
signal microblaze_0_ilmb_bus_WAIT : STD_LOGIC;
signal microblaze_0_ilmb_bus_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_bus_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_CLK : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_DIN : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_cntlr_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_ilmb_cntlr_EN : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_RST : STD_LOGIC;
signal microblaze_0_ilmb_cntlr_WE : STD_LOGIC_VECTOR ( 0 to 3 );
signal NLW_dlmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_ilmb_v10_LMB_Rst_UNCONNECTED : STD_LOGIC;
signal NLW_lmb_bram_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_lmb_bram_rstb_busy_UNCONNECTED : STD_LOGIC;
attribute BMM_INFO_ADDRESS_SPACE : string;
attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x00000000 32 > top microblaze_0_local_memory/lmb_bram";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of dlmb_bram_if_cntlr : label is "yes";
begin
DLMB_ce <= microblaze_0_dlmb_CE;
DLMB_readdbus(0 to 31) <= microblaze_0_dlmb_READDBUS(0 to 31);
DLMB_ready <= microblaze_0_dlmb_READY;
DLMB_ue <= microblaze_0_dlmb_UE;
DLMB_wait <= microblaze_0_dlmb_WAIT;
ILMB_ce <= microblaze_0_ilmb_CE;
ILMB_readdbus(0 to 31) <= microblaze_0_ilmb_READDBUS(0 to 31);
ILMB_ready <= microblaze_0_ilmb_READY;
ILMB_ue <= microblaze_0_ilmb_UE;
ILMB_wait <= microblaze_0_ilmb_WAIT;
SYS_Rst_1 <= SYS_Rst;
microblaze_0_Clk <= LMB_Clk;
microblaze_0_dlmb_ABUS(0 to 31) <= DLMB_abus(0 to 31);
microblaze_0_dlmb_ADDRSTROBE <= DLMB_addrstrobe;
microblaze_0_dlmb_BE(0 to 3) <= DLMB_be(0 to 3);
microblaze_0_dlmb_READSTROBE <= DLMB_readstrobe;
microblaze_0_dlmb_WRITEDBUS(0 to 31) <= DLMB_writedbus(0 to 31);
microblaze_0_dlmb_WRITESTROBE <= DLMB_writestrobe;
microblaze_0_ilmb_ABUS(0 to 31) <= ILMB_abus(0 to 31);
microblaze_0_ilmb_ADDRSTROBE <= ILMB_addrstrobe;
microblaze_0_ilmb_READSTROBE <= ILMB_readstrobe;
dlmb_bram_if_cntlr: component top_dlmb_bram_if_cntlr_1
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_dlmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_dlmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_dlmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_dlmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_dlmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_dlmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_dlmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_dlmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_dlmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_dlmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_dlmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_dlmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_dlmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_dlmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_dlmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_dlmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_dlmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_dlmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_dlmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_dlmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_dlmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_dlmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_dlmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_dlmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_dlmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_dlmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_dlmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_dlmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_dlmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_dlmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_dlmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_dlmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_dlmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_dlmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_dlmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_dlmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_dlmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_dlmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1,
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_dlmb_bus_READY,
Sl_UE => microblaze_0_dlmb_bus_UE,
Sl_Wait => microblaze_0_dlmb_bus_WAIT
);
dlmb_v10: component top_dlmb_v10_1
port map (
LMB_ABus(0 to 31) => microblaze_0_dlmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_dlmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_dlmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_dlmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_dlmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_dlmb_bus_READSTROBE,
LMB_Ready => microblaze_0_dlmb_READY,
LMB_Rst => NLW_dlmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_dlmb_UE,
LMB_Wait => microblaze_0_dlmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_dlmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_dlmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_dlmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_dlmb_ADDRSTROBE,
M_BE(0 to 3) => microblaze_0_dlmb_BE(0 to 3),
M_DBus(0 to 31) => microblaze_0_dlmb_WRITEDBUS(0 to 31),
M_ReadStrobe => microblaze_0_dlmb_READSTROBE,
M_WriteStrobe => microblaze_0_dlmb_WRITESTROBE,
SYS_Rst => SYS_Rst_1,
Sl_CE(0) => microblaze_0_dlmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_dlmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_dlmb_bus_READY,
Sl_UE(0) => microblaze_0_dlmb_bus_UE,
Sl_Wait(0) => microblaze_0_dlmb_bus_WAIT
);
ilmb_bram_if_cntlr: component top_ilmb_bram_if_cntlr_1
port map (
BRAM_Addr_A(0 to 31) => microblaze_0_ilmb_cntlr_ADDR(0 to 31),
BRAM_Clk_A => microblaze_0_ilmb_cntlr_CLK,
BRAM_Din_A(0) => microblaze_0_ilmb_cntlr_DOUT(31),
BRAM_Din_A(1) => microblaze_0_ilmb_cntlr_DOUT(30),
BRAM_Din_A(2) => microblaze_0_ilmb_cntlr_DOUT(29),
BRAM_Din_A(3) => microblaze_0_ilmb_cntlr_DOUT(28),
BRAM_Din_A(4) => microblaze_0_ilmb_cntlr_DOUT(27),
BRAM_Din_A(5) => microblaze_0_ilmb_cntlr_DOUT(26),
BRAM_Din_A(6) => microblaze_0_ilmb_cntlr_DOUT(25),
BRAM_Din_A(7) => microblaze_0_ilmb_cntlr_DOUT(24),
BRAM_Din_A(8) => microblaze_0_ilmb_cntlr_DOUT(23),
BRAM_Din_A(9) => microblaze_0_ilmb_cntlr_DOUT(22),
BRAM_Din_A(10) => microblaze_0_ilmb_cntlr_DOUT(21),
BRAM_Din_A(11) => microblaze_0_ilmb_cntlr_DOUT(20),
BRAM_Din_A(12) => microblaze_0_ilmb_cntlr_DOUT(19),
BRAM_Din_A(13) => microblaze_0_ilmb_cntlr_DOUT(18),
BRAM_Din_A(14) => microblaze_0_ilmb_cntlr_DOUT(17),
BRAM_Din_A(15) => microblaze_0_ilmb_cntlr_DOUT(16),
BRAM_Din_A(16) => microblaze_0_ilmb_cntlr_DOUT(15),
BRAM_Din_A(17) => microblaze_0_ilmb_cntlr_DOUT(14),
BRAM_Din_A(18) => microblaze_0_ilmb_cntlr_DOUT(13),
BRAM_Din_A(19) => microblaze_0_ilmb_cntlr_DOUT(12),
BRAM_Din_A(20) => microblaze_0_ilmb_cntlr_DOUT(11),
BRAM_Din_A(21) => microblaze_0_ilmb_cntlr_DOUT(10),
BRAM_Din_A(22) => microblaze_0_ilmb_cntlr_DOUT(9),
BRAM_Din_A(23) => microblaze_0_ilmb_cntlr_DOUT(8),
BRAM_Din_A(24) => microblaze_0_ilmb_cntlr_DOUT(7),
BRAM_Din_A(25) => microblaze_0_ilmb_cntlr_DOUT(6),
BRAM_Din_A(26) => microblaze_0_ilmb_cntlr_DOUT(5),
BRAM_Din_A(27) => microblaze_0_ilmb_cntlr_DOUT(4),
BRAM_Din_A(28) => microblaze_0_ilmb_cntlr_DOUT(3),
BRAM_Din_A(29) => microblaze_0_ilmb_cntlr_DOUT(2),
BRAM_Din_A(30) => microblaze_0_ilmb_cntlr_DOUT(1),
BRAM_Din_A(31) => microblaze_0_ilmb_cntlr_DOUT(0),
BRAM_Dout_A(0 to 31) => microblaze_0_ilmb_cntlr_DIN(0 to 31),
BRAM_EN_A => microblaze_0_ilmb_cntlr_EN,
BRAM_Rst_A => microblaze_0_ilmb_cntlr_RST,
BRAM_WEN_A(0 to 3) => microblaze_0_ilmb_cntlr_WE(0 to 3),
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_Clk => microblaze_0_Clk,
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Rst => SYS_Rst_1,
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
Sl_CE => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready => microblaze_0_ilmb_bus_READY,
Sl_UE => microblaze_0_ilmb_bus_UE,
Sl_Wait => microblaze_0_ilmb_bus_WAIT
);
ilmb_v10: component top_ilmb_v10_1
port map (
LMB_ABus(0 to 31) => microblaze_0_ilmb_bus_ABUS(0 to 31),
LMB_AddrStrobe => microblaze_0_ilmb_bus_ADDRSTROBE,
LMB_BE(0 to 3) => microblaze_0_ilmb_bus_BE(0 to 3),
LMB_CE => microblaze_0_ilmb_CE,
LMB_Clk => microblaze_0_Clk,
LMB_ReadDBus(0 to 31) => microblaze_0_ilmb_READDBUS(0 to 31),
LMB_ReadStrobe => microblaze_0_ilmb_bus_READSTROBE,
LMB_Ready => microblaze_0_ilmb_READY,
LMB_Rst => NLW_ilmb_v10_LMB_Rst_UNCONNECTED,
LMB_UE => microblaze_0_ilmb_UE,
LMB_Wait => microblaze_0_ilmb_WAIT,
LMB_WriteDBus(0 to 31) => microblaze_0_ilmb_bus_WRITEDBUS(0 to 31),
LMB_WriteStrobe => microblaze_0_ilmb_bus_WRITESTROBE,
M_ABus(0 to 31) => microblaze_0_ilmb_ABUS(0 to 31),
M_AddrStrobe => microblaze_0_ilmb_ADDRSTROBE,
M_BE(0 to 3) => B"0000",
M_DBus(0 to 31) => B"00000000000000000000000000000000",
M_ReadStrobe => microblaze_0_ilmb_READSTROBE,
M_WriteStrobe => '0',
SYS_Rst => SYS_Rst_1,
Sl_CE(0) => microblaze_0_ilmb_bus_CE,
Sl_DBus(0 to 31) => microblaze_0_ilmb_bus_READDBUS(0 to 31),
Sl_Ready(0) => microblaze_0_ilmb_bus_READY,
Sl_UE(0) => microblaze_0_ilmb_bus_UE,
Sl_Wait(0) => microblaze_0_ilmb_bus_WAIT
);
lmb_bram: component top_lmb_bram_1
port map (
addra(31) => microblaze_0_dlmb_cntlr_ADDR(0),
addra(30) => microblaze_0_dlmb_cntlr_ADDR(1),
addra(29) => microblaze_0_dlmb_cntlr_ADDR(2),
addra(28) => microblaze_0_dlmb_cntlr_ADDR(3),
addra(27) => microblaze_0_dlmb_cntlr_ADDR(4),
addra(26) => microblaze_0_dlmb_cntlr_ADDR(5),
addra(25) => microblaze_0_dlmb_cntlr_ADDR(6),
addra(24) => microblaze_0_dlmb_cntlr_ADDR(7),
addra(23) => microblaze_0_dlmb_cntlr_ADDR(8),
addra(22) => microblaze_0_dlmb_cntlr_ADDR(9),
addra(21) => microblaze_0_dlmb_cntlr_ADDR(10),
addra(20) => microblaze_0_dlmb_cntlr_ADDR(11),
addra(19) => microblaze_0_dlmb_cntlr_ADDR(12),
addra(18) => microblaze_0_dlmb_cntlr_ADDR(13),
addra(17) => microblaze_0_dlmb_cntlr_ADDR(14),
addra(16) => microblaze_0_dlmb_cntlr_ADDR(15),
addra(15) => microblaze_0_dlmb_cntlr_ADDR(16),
addra(14) => microblaze_0_dlmb_cntlr_ADDR(17),
addra(13) => microblaze_0_dlmb_cntlr_ADDR(18),
addra(12) => microblaze_0_dlmb_cntlr_ADDR(19),
addra(11) => microblaze_0_dlmb_cntlr_ADDR(20),
addra(10) => microblaze_0_dlmb_cntlr_ADDR(21),
addra(9) => microblaze_0_dlmb_cntlr_ADDR(22),
addra(8) => microblaze_0_dlmb_cntlr_ADDR(23),
addra(7) => microblaze_0_dlmb_cntlr_ADDR(24),
addra(6) => microblaze_0_dlmb_cntlr_ADDR(25),
addra(5) => microblaze_0_dlmb_cntlr_ADDR(26),
addra(4) => microblaze_0_dlmb_cntlr_ADDR(27),
addra(3) => microblaze_0_dlmb_cntlr_ADDR(28),
addra(2) => microblaze_0_dlmb_cntlr_ADDR(29),
addra(1) => microblaze_0_dlmb_cntlr_ADDR(30),
addra(0) => microblaze_0_dlmb_cntlr_ADDR(31),
addrb(31) => microblaze_0_ilmb_cntlr_ADDR(0),
addrb(30) => microblaze_0_ilmb_cntlr_ADDR(1),
addrb(29) => microblaze_0_ilmb_cntlr_ADDR(2),
addrb(28) => microblaze_0_ilmb_cntlr_ADDR(3),
addrb(27) => microblaze_0_ilmb_cntlr_ADDR(4),
addrb(26) => microblaze_0_ilmb_cntlr_ADDR(5),
addrb(25) => microblaze_0_ilmb_cntlr_ADDR(6),
addrb(24) => microblaze_0_ilmb_cntlr_ADDR(7),
addrb(23) => microblaze_0_ilmb_cntlr_ADDR(8),
addrb(22) => microblaze_0_ilmb_cntlr_ADDR(9),
addrb(21) => microblaze_0_ilmb_cntlr_ADDR(10),
addrb(20) => microblaze_0_ilmb_cntlr_ADDR(11),
addrb(19) => microblaze_0_ilmb_cntlr_ADDR(12),
addrb(18) => microblaze_0_ilmb_cntlr_ADDR(13),
addrb(17) => microblaze_0_ilmb_cntlr_ADDR(14),
addrb(16) => microblaze_0_ilmb_cntlr_ADDR(15),
addrb(15) => microblaze_0_ilmb_cntlr_ADDR(16),
addrb(14) => microblaze_0_ilmb_cntlr_ADDR(17),
addrb(13) => microblaze_0_ilmb_cntlr_ADDR(18),
addrb(12) => microblaze_0_ilmb_cntlr_ADDR(19),
addrb(11) => microblaze_0_ilmb_cntlr_ADDR(20),
addrb(10) => microblaze_0_ilmb_cntlr_ADDR(21),
addrb(9) => microblaze_0_ilmb_cntlr_ADDR(22),
addrb(8) => microblaze_0_ilmb_cntlr_ADDR(23),
addrb(7) => microblaze_0_ilmb_cntlr_ADDR(24),
addrb(6) => microblaze_0_ilmb_cntlr_ADDR(25),
addrb(5) => microblaze_0_ilmb_cntlr_ADDR(26),
addrb(4) => microblaze_0_ilmb_cntlr_ADDR(27),
addrb(3) => microblaze_0_ilmb_cntlr_ADDR(28),
addrb(2) => microblaze_0_ilmb_cntlr_ADDR(29),
addrb(1) => microblaze_0_ilmb_cntlr_ADDR(30),
addrb(0) => microblaze_0_ilmb_cntlr_ADDR(31),
clka => microblaze_0_dlmb_cntlr_CLK,
clkb => microblaze_0_ilmb_cntlr_CLK,
dina(31) => microblaze_0_dlmb_cntlr_DIN(0),
dina(30) => microblaze_0_dlmb_cntlr_DIN(1),
dina(29) => microblaze_0_dlmb_cntlr_DIN(2),
dina(28) => microblaze_0_dlmb_cntlr_DIN(3),
dina(27) => microblaze_0_dlmb_cntlr_DIN(4),
dina(26) => microblaze_0_dlmb_cntlr_DIN(5),
dina(25) => microblaze_0_dlmb_cntlr_DIN(6),
dina(24) => microblaze_0_dlmb_cntlr_DIN(7),
dina(23) => microblaze_0_dlmb_cntlr_DIN(8),
dina(22) => microblaze_0_dlmb_cntlr_DIN(9),
dina(21) => microblaze_0_dlmb_cntlr_DIN(10),
dina(20) => microblaze_0_dlmb_cntlr_DIN(11),
dina(19) => microblaze_0_dlmb_cntlr_DIN(12),
dina(18) => microblaze_0_dlmb_cntlr_DIN(13),
dina(17) => microblaze_0_dlmb_cntlr_DIN(14),
dina(16) => microblaze_0_dlmb_cntlr_DIN(15),
dina(15) => microblaze_0_dlmb_cntlr_DIN(16),
dina(14) => microblaze_0_dlmb_cntlr_DIN(17),
dina(13) => microblaze_0_dlmb_cntlr_DIN(18),
dina(12) => microblaze_0_dlmb_cntlr_DIN(19),
dina(11) => microblaze_0_dlmb_cntlr_DIN(20),
dina(10) => microblaze_0_dlmb_cntlr_DIN(21),
dina(9) => microblaze_0_dlmb_cntlr_DIN(22),
dina(8) => microblaze_0_dlmb_cntlr_DIN(23),
dina(7) => microblaze_0_dlmb_cntlr_DIN(24),
dina(6) => microblaze_0_dlmb_cntlr_DIN(25),
dina(5) => microblaze_0_dlmb_cntlr_DIN(26),
dina(4) => microblaze_0_dlmb_cntlr_DIN(27),
dina(3) => microblaze_0_dlmb_cntlr_DIN(28),
dina(2) => microblaze_0_dlmb_cntlr_DIN(29),
dina(1) => microblaze_0_dlmb_cntlr_DIN(30),
dina(0) => microblaze_0_dlmb_cntlr_DIN(31),
dinb(31) => microblaze_0_ilmb_cntlr_DIN(0),
dinb(30) => microblaze_0_ilmb_cntlr_DIN(1),
dinb(29) => microblaze_0_ilmb_cntlr_DIN(2),
dinb(28) => microblaze_0_ilmb_cntlr_DIN(3),
dinb(27) => microblaze_0_ilmb_cntlr_DIN(4),
dinb(26) => microblaze_0_ilmb_cntlr_DIN(5),
dinb(25) => microblaze_0_ilmb_cntlr_DIN(6),
dinb(24) => microblaze_0_ilmb_cntlr_DIN(7),
dinb(23) => microblaze_0_ilmb_cntlr_DIN(8),
dinb(22) => microblaze_0_ilmb_cntlr_DIN(9),
dinb(21) => microblaze_0_ilmb_cntlr_DIN(10),
dinb(20) => microblaze_0_ilmb_cntlr_DIN(11),
dinb(19) => microblaze_0_ilmb_cntlr_DIN(12),
dinb(18) => microblaze_0_ilmb_cntlr_DIN(13),
dinb(17) => microblaze_0_ilmb_cntlr_DIN(14),
dinb(16) => microblaze_0_ilmb_cntlr_DIN(15),
dinb(15) => microblaze_0_ilmb_cntlr_DIN(16),
dinb(14) => microblaze_0_ilmb_cntlr_DIN(17),
dinb(13) => microblaze_0_ilmb_cntlr_DIN(18),
dinb(12) => microblaze_0_ilmb_cntlr_DIN(19),
dinb(11) => microblaze_0_ilmb_cntlr_DIN(20),
dinb(10) => microblaze_0_ilmb_cntlr_DIN(21),
dinb(9) => microblaze_0_ilmb_cntlr_DIN(22),
dinb(8) => microblaze_0_ilmb_cntlr_DIN(23),
dinb(7) => microblaze_0_ilmb_cntlr_DIN(24),
dinb(6) => microblaze_0_ilmb_cntlr_DIN(25),
dinb(5) => microblaze_0_ilmb_cntlr_DIN(26),
dinb(4) => microblaze_0_ilmb_cntlr_DIN(27),
dinb(3) => microblaze_0_ilmb_cntlr_DIN(28),
dinb(2) => microblaze_0_ilmb_cntlr_DIN(29),
dinb(1) => microblaze_0_ilmb_cntlr_DIN(30),
dinb(0) => microblaze_0_ilmb_cntlr_DIN(31),
douta(31 downto 0) => microblaze_0_dlmb_cntlr_DOUT(31 downto 0),
doutb(31 downto 0) => microblaze_0_ilmb_cntlr_DOUT(31 downto 0),
ena => microblaze_0_dlmb_cntlr_EN,
enb => microblaze_0_ilmb_cntlr_EN,
rsta => microblaze_0_dlmb_cntlr_RST,
rsta_busy => NLW_lmb_bram_rsta_busy_UNCONNECTED,
rstb => microblaze_0_ilmb_cntlr_RST,
rstb_busy => NLW_lmb_bram_rstb_busy_UNCONNECTED,
wea(3) => microblaze_0_dlmb_cntlr_WE(0),
wea(2) => microblaze_0_dlmb_cntlr_WE(1),
wea(1) => microblaze_0_dlmb_cntlr_WE(2),
wea(0) => microblaze_0_dlmb_cntlr_WE(3),
web(3) => microblaze_0_ilmb_cntlr_WE(0),
web(2) => microblaze_0_ilmb_cntlr_WE(1),
web(1) => microblaze_0_ilmb_cntlr_WE(2),
web(0) => microblaze_0_ilmb_cntlr_WE(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_17UPS7G is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_17UPS7G;
architecture STRUCTURE of s00_couplers_imp_17UPS7G is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= s00_couplers_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= s00_couplers_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= s00_couplers_to_s00_couplers_AWVALID(0);
M_AXI_bready(0) <= s00_couplers_to_s00_couplers_BREADY(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= s00_couplers_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= s00_couplers_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= s00_couplers_to_s00_couplers_WVALID(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_awready(0) <= s00_couplers_to_s00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_s00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= s00_couplers_to_s00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
S_AXI_wready(0) <= s00_couplers_to_s00_couplers_WREADY(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_s00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_s00_couplers_AWREADY(0) <= M_AXI_awready(0);
s00_couplers_to_s00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
s00_couplers_to_s00_couplers_BREADY(0) <= S_AXI_bready(0);
s00_couplers_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s00_couplers_to_s00_couplers_BVALID(0) <= M_AXI_bvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
s00_couplers_to_s00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_s00_couplers_WREADY(0) <= M_AXI_wready(0);
s00_couplers_to_s00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_s00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top_microblaze_0_axi_periph_1 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC;
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end top_microblaze_0_axi_periph_1;
architecture STRUCTURE of top_microblaze_0_axi_periph_1 is
component top_xbar_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component top_xbar_1;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC;
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m00_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m05_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_ARREADY : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_ARVALID : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_AWREADY : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_AWVALID : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_BREADY : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_BVALID : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RREADY : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_RVALID : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WREADY : STD_LOGIC;
signal m06_couplers_to_microblaze_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m06_couplers_to_microblaze_0_axi_periph_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_ACLK_net : STD_LOGIC;
signal microblaze_0_axi_periph_ARESETN_net : STD_LOGIC;
signal microblaze_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WSTRB : STD_LOGIC_VECTOR ( 27 downto 24 );
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid <= m00_couplers_to_microblaze_0_axi_periph_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid <= m00_couplers_to_microblaze_0_axi_periph_AWVALID;
M00_AXI_bready <= m00_couplers_to_microblaze_0_axi_periph_BREADY;
M00_AXI_rready <= m00_couplers_to_microblaze_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_microblaze_0_axi_periph_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid <= m01_couplers_to_microblaze_0_axi_periph_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid <= m01_couplers_to_microblaze_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_microblaze_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_microblaze_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_microblaze_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid <= m02_couplers_to_microblaze_0_axi_periph_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid <= m02_couplers_to_microblaze_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_microblaze_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_microblaze_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_microblaze_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_microblaze_0_axi_periph_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_microblaze_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_microblaze_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_microblaze_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_microblaze_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_microblaze_0_axi_periph_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_microblaze_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_microblaze_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_microblaze_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_microblaze_0_axi_periph_WVALID;
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1 <= M05_ARESETN;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_microblaze_0_axi_periph_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_microblaze_0_axi_periph_AWVALID;
M05_AXI_bready <= m05_couplers_to_microblaze_0_axi_periph_BREADY;
M05_AXI_rready <= m05_couplers_to_microblaze_0_axi_periph_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_microblaze_0_axi_periph_WVALID;
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1 <= M06_ARESETN;
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0);
M06_AXI_arvalid <= m06_couplers_to_microblaze_0_axi_periph_ARVALID;
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0);
M06_AXI_awvalid <= m06_couplers_to_microblaze_0_axi_periph_AWVALID;
M06_AXI_bready <= m06_couplers_to_microblaze_0_axi_periph_BREADY;
M06_AXI_rready <= m06_couplers_to_microblaze_0_axi_periph_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wstrb(3 downto 0) <= m06_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0);
M06_AXI_wvalid <= m06_couplers_to_microblaze_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready(0) <= microblaze_0_axi_periph_to_s00_couplers_ARREADY(0);
S00_AXI_awready(0) <= microblaze_0_axi_periph_to_s00_couplers_AWREADY(0);
S00_AXI_bresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_BVALID(0);
S00_AXI_rdata(31 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rresp(1 downto 0) <= microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= microblaze_0_axi_periph_to_s00_couplers_RVALID(0);
S00_AXI_wready(0) <= microblaze_0_axi_periph_to_s00_couplers_WREADY(0);
m00_couplers_to_microblaze_0_axi_periph_ARREADY <= M00_AXI_arready;
m00_couplers_to_microblaze_0_axi_periph_AWREADY <= M00_AXI_awready;
m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_BVALID <= M00_AXI_bvalid;
m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_microblaze_0_axi_periph_RVALID <= M00_AXI_rvalid;
m00_couplers_to_microblaze_0_axi_periph_WREADY <= M00_AXI_wready;
m01_couplers_to_microblaze_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_microblaze_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_microblaze_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_microblaze_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_microblaze_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_microblaze_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_microblaze_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_microblaze_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_microblaze_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_microblaze_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_microblaze_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_microblaze_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_microblaze_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_microblaze_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_microblaze_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_microblaze_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_microblaze_0_axi_periph_WREADY <= M04_AXI_wready;
m05_couplers_to_microblaze_0_axi_periph_ARREADY <= M05_AXI_arready;
m05_couplers_to_microblaze_0_axi_periph_AWREADY <= M05_AXI_awready;
m05_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_microblaze_0_axi_periph_BVALID <= M05_AXI_bvalid;
m05_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_microblaze_0_axi_periph_RVALID <= M05_AXI_rvalid;
m05_couplers_to_microblaze_0_axi_periph_WREADY <= M05_AXI_wready;
m06_couplers_to_microblaze_0_axi_periph_ARREADY <= M06_AXI_arready;
m06_couplers_to_microblaze_0_axi_periph_AWREADY <= M06_AXI_awready;
m06_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_microblaze_0_axi_periph_BVALID <= M06_AXI_bvalid;
m06_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_microblaze_0_axi_periph_RVALID <= M06_AXI_rvalid;
m06_couplers_to_microblaze_0_axi_periph_WREADY <= M06_AXI_wready;
microblaze_0_axi_periph_ACLK_net <= ACLK;
microblaze_0_axi_periph_ARESETN_net <= ARESETN;
microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
microblaze_0_axi_periph_to_s00_couplers_AWVALID(0) <= S00_AXI_awvalid(0);
microblaze_0_axi_periph_to_s00_couplers_BREADY(0) <= S00_AXI_bready(0);
microblaze_0_axi_periph_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
microblaze_0_axi_periph_to_s00_couplers_WVALID(0) <= S00_AXI_wvalid(0);
m00_couplers: entity work.m00_couplers_imp_FAIRLI
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m00_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m00_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m00_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m00_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m00_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1T2T38Z
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m01_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m01_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_O7LC3H
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m02_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m02_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_12IU86W
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_1WPMAOW
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_BPII3P
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN => M05_ARESETN_1,
M_AXI_araddr(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m05_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m05_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m05_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_165ZWTN
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN => M06_ARESETN_1,
M_AXI_araddr(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m06_couplers_to_microblaze_0_axi_periph_ARREADY,
M_AXI_arvalid => m06_couplers_to_microblaze_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m06_couplers_to_microblaze_0_axi_periph_AWREADY,
M_AXI_awvalid => m06_couplers_to_microblaze_0_axi_periph_AWVALID,
M_AXI_bready => m06_couplers_to_microblaze_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_microblaze_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_microblaze_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_microblaze_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_microblaze_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_microblaze_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_microblaze_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_microblaze_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m06_couplers_to_microblaze_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m06_couplers_to_microblaze_0_axi_periph_WVALID,
S_ACLK => microblaze_0_axi_periph_ACLK_net,
S_ARESETN => microblaze_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m06_couplers_WSTRB(27 downto 24),
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_17UPS7G
port map (
M_ACLK => microblaze_0_axi_periph_ACLK_net,
M_ARESETN => microblaze_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready(0) => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
M_AXI_bready(0) => s00_couplers_to_xbar_BREADY(0),
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready(0) => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid(0) => s00_couplers_to_xbar_WVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => microblaze_0_axi_periph_to_s00_couplers_ARREADY(0),
S_AXI_arvalid(0) => microblaze_0_axi_periph_to_s00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => microblaze_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => microblaze_0_axi_periph_to_s00_couplers_AWREADY(0),
S_AXI_awvalid(0) => microblaze_0_axi_periph_to_s00_couplers_AWVALID(0),
S_AXI_bready(0) => microblaze_0_axi_periph_to_s00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => microblaze_0_axi_periph_to_s00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => microblaze_0_axi_periph_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => microblaze_0_axi_periph_to_s00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => microblaze_0_axi_periph_to_s00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => microblaze_0_axi_periph_to_s00_couplers_WVALID(0)
);
xbar: component top_xbar_1
port map (
aclk => microblaze_0_axi_periph_ACLK_net,
aresetn => microblaze_0_axi_periph_ARESETN_net,
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(20 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(20 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(27 downto 24) => xbar_to_m06_couplers_WSTRB(27 downto 24),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID(0),
s_axi_bready(0) => s00_couplers_to_xbar_BREADY(0),
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity top is
port (
reset : in STD_LOGIC;
rs232_uart_rxd : in STD_LOGIC;
rs232_uart_txd : out STD_LOGIC;
sys_diff_clock_clk_n : in STD_LOGIC;
sys_diff_clock_clk_p : in STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of top : entity is "top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=top,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=40,numReposBlks=30,numNonXlnxBlks=0,numHierBlks=10,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=5,da_board_cnt=4,da_clkrst_cnt=2,da_mb_cnt=2,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of top : entity is "top.hwdef";
end top;
architecture STRUCTURE of top is
component top_microblaze_0_0 is
port (
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Interrupt : in STD_LOGIC;
Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
IFetch : out STD_LOGIC;
I_AS : out STD_LOGIC;
IReady : in STD_LOGIC;
IWAIT : in STD_LOGIC;
ICE : in STD_LOGIC;
IUE : in STD_LOGIC;
Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
D_AS : out STD_LOGIC;
Read_Strobe : out STD_LOGIC;
Write_Strobe : out STD_LOGIC;
DReady : in STD_LOGIC;
DWait : in STD_LOGIC;
DCE : in STD_LOGIC;
DUE : in STD_LOGIC;
Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_AWVALID : out STD_LOGIC;
M_AXI_DP_AWREADY : in STD_LOGIC;
M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_DP_WVALID : out STD_LOGIC;
M_AXI_DP_WREADY : in STD_LOGIC;
M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_BVALID : in STD_LOGIC;
M_AXI_DP_BREADY : out STD_LOGIC;
M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_DP_ARVALID : out STD_LOGIC;
M_AXI_DP_ARREADY : in STD_LOGIC;
M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_DP_RVALID : in STD_LOGIC;
M_AXI_DP_RREADY : out STD_LOGIC;
Dbg_Clk : in STD_LOGIC;
Dbg_TDI : in STD_LOGIC;
Dbg_TDO : out STD_LOGIC;
Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Shift : in STD_LOGIC;
Dbg_Capture : in STD_LOGIC;
Dbg_Update : in STD_LOGIC;
Debug_Rst : in STD_LOGIC;
Dbg_Disable : in STD_LOGIC
);
end component top_microblaze_0_0;
component top_microblaze_0_axi_intc_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 1 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component top_microblaze_0_axi_intc_1;
component top_microblaze_0_xlconcat_1 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component top_microblaze_0_xlconcat_1;
component top_mdm_1_1 is
port (
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
Interrupt : out STD_LOGIC;
Debug_SYS_Rst : out STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
Dbg_Clk_0 : out STD_LOGIC;
Dbg_TDI_0 : out STD_LOGIC;
Dbg_TDO_0 : in STD_LOGIC;
Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
Dbg_Capture_0 : out STD_LOGIC;
Dbg_Shift_0 : out STD_LOGIC;
Dbg_Update_0 : out STD_LOGIC;
Dbg_Rst_0 : out STD_LOGIC;
Dbg_Disable_0 : out STD_LOGIC
);
end component top_mdm_1_1;
component top_clk_wiz_1_1 is
port (
clk_in1_p : in STD_LOGIC;
clk_in1_n : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component top_clk_wiz_1_1;
component top_rst_clk_wiz_1_100M_1 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component top_rst_clk_wiz_1_100M_1;
component top_axi_uartlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
interrupt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
rx : in STD_LOGIC;
tx : out STD_LOGIC
);
end component top_axi_uartlite_0_0;
component top_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component top_axi_gpio_0_0;
component top_axi_gpio_0_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component top_axi_gpio_0_1;
component top_axi_gpio_0_2 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component top_axi_gpio_0_2;
component top_axi_gpio_0_3 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component top_axi_gpio_0_3;
component top_xlslice_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component top_xlslice_0_0;
component top_xlslice_0_1 is
port (
Din : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component top_xlslice_0_1;
component top_xlslice_0_2 is
port (
Din : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component top_xlslice_0_2;
component top_xlslice_0_3 is
port (
Din : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component top_xlslice_0_3;
component top_xlslice_0_4 is
port (
Din : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component top_xlslice_0_4;
component top_xlslice_5_0 is
port (
Din : in STD_LOGIC_VECTOR ( 31 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
end component top_xlslice_5_0;
component top_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component top_xlconstant_0_0;
component top_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 29 downto 0 );
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component top_xlconcat_0_0;
component top_xlconstant_1_0 is
port (
dout : out STD_LOGIC_VECTOR ( 29 downto 0 )
);
end component top_xlconstant_1_0;
component top_xlconcat_1_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
In1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component top_xlconcat_1_0;
component top_xlconstant_2_0 is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component top_xlconstant_2_0;
component top_FSM_0_0 is
port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
GO : in STD_LOGIC;
COMPL : out STD_LOGIC;
EN_NODES : in STD_LOGIC_VECTOR ( 1627 downto 0 );
RESULT : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component top_FSM_0_0;
component top_FSM_ENABLE_NODES_0_0 is
port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
EN : in STD_LOGIC;
M_SET : in STD_LOGIC;
ZERO : in STD_LOGIC;
ONE : in STD_LOGIC;
DIN : in STD_LOGIC_VECTOR ( 10 downto 0 );
SH_DONE : out STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR ( 1627 downto 0 )
);
end component top_FSM_ENABLE_NODES_0_0;
signal FSM_0_COMPL : STD_LOGIC;
signal FSM_0_RESULT : STD_LOGIC_VECTOR ( 23 downto 0 );
signal FSM_ENABLE_NODES_0_DOUT : STD_LOGIC_VECTOR ( 1627 downto 0 );
signal FSM_ENABLE_NODES_0_SH_DONE : STD_LOGIC;
signal axi_gpio_0_gpio_io_o : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_gpio_2_gpio_io_o : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_uartlite_0_UART_RxD : STD_LOGIC;
signal axi_uartlite_0_UART_TxD : STD_LOGIC;
signal axi_uartlite_0_interrupt : STD_LOGIC;
signal clk_wiz_1_locked : STD_LOGIC;
signal mdm_1_Interrupt : STD_LOGIC;
signal mdm_1_debug_sys_rst : STD_LOGIC;
signal microblaze_0_Clk : STD_LOGIC;
signal microblaze_0_axi_dp_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_ARVALID : STD_LOGIC;
signal microblaze_0_axi_dp_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal microblaze_0_axi_dp_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_AWVALID : STD_LOGIC;
signal microblaze_0_axi_dp_BREADY : STD_LOGIC;
signal microblaze_0_axi_dp_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_RREADY : STD_LOGIC;
signal microblaze_0_axi_dp_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_dp_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_dp_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal microblaze_0_axi_dp_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_dp_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M05_AXI_WVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_BREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_RREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal microblaze_0_axi_periph_M06_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_axi_periph_M06_AXI_WVALID : STD_LOGIC;
signal microblaze_0_debug_CAPTURE : STD_LOGIC;
signal microblaze_0_debug_CLK : STD_LOGIC;
signal microblaze_0_debug_DISABLE : STD_LOGIC;
signal microblaze_0_debug_REG_EN : STD_LOGIC_VECTOR ( 0 to 7 );
signal microblaze_0_debug_RST : STD_LOGIC;
signal microblaze_0_debug_SHIFT : STD_LOGIC;
signal microblaze_0_debug_TDI : STD_LOGIC;
signal microblaze_0_debug_TDO : STD_LOGIC;
signal microblaze_0_debug_UPDATE : STD_LOGIC;
signal microblaze_0_dlmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal microblaze_0_dlmb_1_CE : STD_LOGIC;
signal microblaze_0_dlmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_dlmb_1_READY : STD_LOGIC;
signal microblaze_0_dlmb_1_UE : STD_LOGIC;
signal microblaze_0_dlmb_1_WAIT : STD_LOGIC;
signal microblaze_0_dlmb_1_WRITEDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_dlmb_1_WRITESTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_ABUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_ADDRSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_CE : STD_LOGIC;
signal microblaze_0_ilmb_1_READDBUS : STD_LOGIC_VECTOR ( 0 to 31 );
signal microblaze_0_ilmb_1_READSTROBE : STD_LOGIC;
signal microblaze_0_ilmb_1_READY : STD_LOGIC;
signal microblaze_0_ilmb_1_UE : STD_LOGIC;
signal microblaze_0_ilmb_1_WAIT : STD_LOGIC;
signal microblaze_0_intc_axi_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_ARREADY : STD_LOGIC;
signal microblaze_0_intc_axi_ARVALID : STD_LOGIC;
signal microblaze_0_intc_axi_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_AWREADY : STD_LOGIC;
signal microblaze_0_intc_axi_AWVALID : STD_LOGIC;
signal microblaze_0_intc_axi_BREADY : STD_LOGIC;
signal microblaze_0_intc_axi_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_BVALID : STD_LOGIC;
signal microblaze_0_intc_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_RREADY : STD_LOGIC;
signal microblaze_0_intc_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_intc_axi_RVALID : STD_LOGIC;
signal microblaze_0_intc_axi_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_intc_axi_WREADY : STD_LOGIC;
signal microblaze_0_intc_axi_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_intc_axi_WVALID : STD_LOGIC;
signal microblaze_0_interrupt_ACK : STD_LOGIC_VECTOR ( 0 to 1 );
signal microblaze_0_interrupt_ADDRESS : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_interrupt_INTERRUPT : STD_LOGIC;
signal microblaze_0_intr : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_mdm_axi_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_mdm_axi_ARREADY : STD_LOGIC;
signal microblaze_0_mdm_axi_ARVALID : STD_LOGIC;
signal microblaze_0_mdm_axi_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_mdm_axi_AWREADY : STD_LOGIC;
signal microblaze_0_mdm_axi_AWVALID : STD_LOGIC;
signal microblaze_0_mdm_axi_BREADY : STD_LOGIC;
signal microblaze_0_mdm_axi_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_mdm_axi_BVALID : STD_LOGIC;
signal microblaze_0_mdm_axi_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_mdm_axi_RREADY : STD_LOGIC;
signal microblaze_0_mdm_axi_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal microblaze_0_mdm_axi_RVALID : STD_LOGIC;
signal microblaze_0_mdm_axi_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal microblaze_0_mdm_axi_WREADY : STD_LOGIC;
signal microblaze_0_mdm_axi_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal microblaze_0_mdm_axi_WVALID : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rst_clk_wiz_1_100M_bus_struct_reset : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_clk_wiz_1_100M_mb_reset : STD_LOGIC;
signal rst_clk_wiz_1_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal sys_diff_clock_1_CLK_N : STD_LOGIC;
signal sys_diff_clock_1_CLK_P : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xlconcat_1_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconstant_1_dout : STD_LOGIC_VECTOR ( 29 downto 0 );
signal xlconstant_2_dout : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xlslice_0_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlslice_1_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlslice_2_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlslice_3_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlslice_4_Dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlslice_5_Dout : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_axi_gpio_0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_gpio_1_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_gpio_1_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_gpio_2_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_gpio_3_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_gpio_3_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BMM_INFO_PROCESSOR : string;
attribute BMM_INFO_PROCESSOR of microblaze_0 : label is "microblaze-le > top microblaze_0_local_memory/dlmb_bram_if_cntlr";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of microblaze_0 : label is "yes";
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of reset : signal is "xilinx.com:signal:reset:1.0 RST.RESET RST";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of reset : signal is "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH";
attribute X_INTERFACE_INFO of rs232_uart_rxd : signal is "xilinx.com:interface:uart:1.0 rs232_uart RxD";
attribute X_INTERFACE_INFO of rs232_uart_txd : signal is "xilinx.com:interface:uart:1.0 rs232_uart TxD";
attribute X_INTERFACE_INFO of sys_diff_clock_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 sys_diff_clock CLK_N";
attribute X_INTERFACE_PARAMETER of sys_diff_clock_clk_n : signal is "XIL_INTERFACENAME sys_diff_clock, CAN_DEBUG false, FREQ_HZ 200000000";
attribute X_INTERFACE_INFO of sys_diff_clock_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 sys_diff_clock CLK_P";
begin
axi_uartlite_0_UART_RxD <= rs232_uart_rxd;
reset_1 <= reset;
rs232_uart_txd <= axi_uartlite_0_UART_TxD;
sys_diff_clock_1_CLK_N <= sys_diff_clock_clk_n;
sys_diff_clock_1_CLK_P <= sys_diff_clock_clk_p;
FSM_0: component top_FSM_0_0
port map (
CLK => microblaze_0_Clk,
COMPL => FSM_0_COMPL,
EN_NODES(1627 downto 0) => FSM_ENABLE_NODES_0_DOUT(1627 downto 0),
GO => xlslice_1_Dout(0),
RESULT(23 downto 0) => FSM_0_RESULT(23 downto 0),
RST => xlslice_0_Dout(0)
);
FSM_ENABLE_NODES_0: component top_FSM_ENABLE_NODES_0_0
port map (
CLK => microblaze_0_Clk,
DIN(10 downto 0) => xlslice_5_Dout(10 downto 0),
DOUT(1627 downto 0) => FSM_ENABLE_NODES_0_DOUT(1627 downto 0),
EN => xlconstant_0_dout(0),
M_SET => xlslice_2_Dout(0),
ONE => xlslice_4_Dout(0),
RST => xlslice_0_Dout(0),
SH_DONE => FSM_ENABLE_NODES_0_SH_DONE,
ZERO => xlslice_3_Dout(0)
);
axi_gpio_0: component top_axi_gpio_0_0
port map (
gpio_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio_io_o(31 downto 0) => axi_gpio_0_gpio_io_o(31 downto 0),
gpio_io_t(31 downto 0) => NLW_axi_gpio_0_gpio_io_t_UNCONNECTED(31 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M03_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M03_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID
);
axi_gpio_1: component top_axi_gpio_0_1
port map (
gpio_io_i(31 downto 0) => xlconcat_0_dout(31 downto 0),
gpio_io_o(31 downto 0) => NLW_axi_gpio_1_gpio_io_o_UNCONNECTED(31 downto 0),
gpio_io_t(31 downto 0) => NLW_axi_gpio_1_gpio_io_t_UNCONNECTED(31 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M04_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M04_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M04_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M04_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M04_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M04_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M04_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M04_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M04_AXI_WVALID
);
axi_gpio_2: component top_axi_gpio_0_2
port map (
gpio_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio_io_o(31 downto 0) => axi_gpio_2_gpio_io_o(31 downto 0),
gpio_io_t(31 downto 0) => NLW_axi_gpio_2_gpio_io_t_UNCONNECTED(31 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M05_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M05_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M05_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M05_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M05_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M05_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M05_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M05_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M05_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M05_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M05_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M05_AXI_WVALID
);
axi_gpio_3: component top_axi_gpio_0_3
port map (
gpio_io_i(31 downto 0) => xlconcat_1_dout(31 downto 0),
gpio_io_o(31 downto 0) => NLW_axi_gpio_3_gpio_io_o_UNCONNECTED(31 downto 0),
gpio_io_t(31 downto 0) => NLW_axi_gpio_3_gpio_io_t_UNCONNECTED(31 downto 0),
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_axi_periph_M06_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M06_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M06_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => microblaze_0_axi_periph_M06_AXI_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_axi_periph_M06_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M06_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M06_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M06_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M06_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M06_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M06_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M06_AXI_WVALID
);
axi_uartlite_0: component top_axi_uartlite_0_0
port map (
interrupt => axi_uartlite_0_interrupt,
rx => axi_uartlite_0_UART_RxD,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(3 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(3 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID,
s_axi_awaddr(3 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(3 downto 0),
s_axi_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID,
s_axi_bready => microblaze_0_axi_periph_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => microblaze_0_axi_periph_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID,
tx => axi_uartlite_0_UART_TxD
);
clk_wiz_1: component top_clk_wiz_1_1
port map (
clk_in1_n => sys_diff_clock_1_CLK_N,
clk_in1_p => sys_diff_clock_1_CLK_P,
clk_out1 => microblaze_0_Clk,
locked => clk_wiz_1_locked,
reset => reset_1
);
mdm_1: component top_mdm_1_1
port map (
Dbg_Capture_0 => microblaze_0_debug_CAPTURE,
Dbg_Clk_0 => microblaze_0_debug_CLK,
Dbg_Disable_0 => microblaze_0_debug_DISABLE,
Dbg_Reg_En_0(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Rst_0 => microblaze_0_debug_RST,
Dbg_Shift_0 => microblaze_0_debug_SHIFT,
Dbg_TDI_0 => microblaze_0_debug_TDI,
Dbg_TDO_0 => microblaze_0_debug_TDO,
Dbg_Update_0 => microblaze_0_debug_UPDATE,
Debug_SYS_Rst => mdm_1_debug_sys_rst,
Interrupt => mdm_1_Interrupt,
S_AXI_ACLK => microblaze_0_Clk,
S_AXI_ARADDR(3 downto 0) => microblaze_0_mdm_axi_ARADDR(3 downto 0),
S_AXI_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S_AXI_ARREADY => microblaze_0_mdm_axi_ARREADY,
S_AXI_ARVALID => microblaze_0_mdm_axi_ARVALID,
S_AXI_AWADDR(3 downto 0) => microblaze_0_mdm_axi_AWADDR(3 downto 0),
S_AXI_AWREADY => microblaze_0_mdm_axi_AWREADY,
S_AXI_AWVALID => microblaze_0_mdm_axi_AWVALID,
S_AXI_BREADY => microblaze_0_mdm_axi_BREADY,
S_AXI_BRESP(1 downto 0) => microblaze_0_mdm_axi_BRESP(1 downto 0),
S_AXI_BVALID => microblaze_0_mdm_axi_BVALID,
S_AXI_RDATA(31 downto 0) => microblaze_0_mdm_axi_RDATA(31 downto 0),
S_AXI_RREADY => microblaze_0_mdm_axi_RREADY,
S_AXI_RRESP(1 downto 0) => microblaze_0_mdm_axi_RRESP(1 downto 0),
S_AXI_RVALID => microblaze_0_mdm_axi_RVALID,
S_AXI_WDATA(31 downto 0) => microblaze_0_mdm_axi_WDATA(31 downto 0),
S_AXI_WREADY => microblaze_0_mdm_axi_WREADY,
S_AXI_WSTRB(3 downto 0) => microblaze_0_mdm_axi_WSTRB(3 downto 0),
S_AXI_WVALID => microblaze_0_mdm_axi_WVALID
);
microblaze_0: component top_microblaze_0_0
port map (
Byte_Enable(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
Clk => microblaze_0_Clk,
DCE => microblaze_0_dlmb_1_CE,
DReady => microblaze_0_dlmb_1_READY,
DUE => microblaze_0_dlmb_1_UE,
DWait => microblaze_0_dlmb_1_WAIT,
D_AS => microblaze_0_dlmb_1_ADDRSTROBE,
Data_Addr(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
Data_Read(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
Data_Write(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
Dbg_Capture => microblaze_0_debug_CAPTURE,
Dbg_Clk => microblaze_0_debug_CLK,
Dbg_Disable => microblaze_0_debug_DISABLE,
Dbg_Reg_En(0 to 7) => microblaze_0_debug_REG_EN(0 to 7),
Dbg_Shift => microblaze_0_debug_SHIFT,
Dbg_TDI => microblaze_0_debug_TDI,
Dbg_TDO => microblaze_0_debug_TDO,
Dbg_Update => microblaze_0_debug_UPDATE,
Debug_Rst => microblaze_0_debug_RST,
ICE => microblaze_0_ilmb_1_CE,
IFetch => microblaze_0_ilmb_1_READSTROBE,
IReady => microblaze_0_ilmb_1_READY,
IUE => microblaze_0_ilmb_1_UE,
IWAIT => microblaze_0_ilmb_1_WAIT,
I_AS => microblaze_0_ilmb_1_ADDRSTROBE,
Instr(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
Instr_Addr(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
Interrupt => microblaze_0_interrupt_INTERRUPT,
Interrupt_Ack(0 to 1) => microblaze_0_interrupt_ACK(0 to 1),
Interrupt_Address(0) => microblaze_0_interrupt_ADDRESS(31),
Interrupt_Address(1) => microblaze_0_interrupt_ADDRESS(30),
Interrupt_Address(2) => microblaze_0_interrupt_ADDRESS(29),
Interrupt_Address(3) => microblaze_0_interrupt_ADDRESS(28),
Interrupt_Address(4) => microblaze_0_interrupt_ADDRESS(27),
Interrupt_Address(5) => microblaze_0_interrupt_ADDRESS(26),
Interrupt_Address(6) => microblaze_0_interrupt_ADDRESS(25),
Interrupt_Address(7) => microblaze_0_interrupt_ADDRESS(24),
Interrupt_Address(8) => microblaze_0_interrupt_ADDRESS(23),
Interrupt_Address(9) => microblaze_0_interrupt_ADDRESS(22),
Interrupt_Address(10) => microblaze_0_interrupt_ADDRESS(21),
Interrupt_Address(11) => microblaze_0_interrupt_ADDRESS(20),
Interrupt_Address(12) => microblaze_0_interrupt_ADDRESS(19),
Interrupt_Address(13) => microblaze_0_interrupt_ADDRESS(18),
Interrupt_Address(14) => microblaze_0_interrupt_ADDRESS(17),
Interrupt_Address(15) => microblaze_0_interrupt_ADDRESS(16),
Interrupt_Address(16) => microblaze_0_interrupt_ADDRESS(15),
Interrupt_Address(17) => microblaze_0_interrupt_ADDRESS(14),
Interrupt_Address(18) => microblaze_0_interrupt_ADDRESS(13),
Interrupt_Address(19) => microblaze_0_interrupt_ADDRESS(12),
Interrupt_Address(20) => microblaze_0_interrupt_ADDRESS(11),
Interrupt_Address(21) => microblaze_0_interrupt_ADDRESS(10),
Interrupt_Address(22) => microblaze_0_interrupt_ADDRESS(9),
Interrupt_Address(23) => microblaze_0_interrupt_ADDRESS(8),
Interrupt_Address(24) => microblaze_0_interrupt_ADDRESS(7),
Interrupt_Address(25) => microblaze_0_interrupt_ADDRESS(6),
Interrupt_Address(26) => microblaze_0_interrupt_ADDRESS(5),
Interrupt_Address(27) => microblaze_0_interrupt_ADDRESS(4),
Interrupt_Address(28) => microblaze_0_interrupt_ADDRESS(3),
Interrupt_Address(29) => microblaze_0_interrupt_ADDRESS(2),
Interrupt_Address(30) => microblaze_0_interrupt_ADDRESS(1),
Interrupt_Address(31) => microblaze_0_interrupt_ADDRESS(0),
M_AXI_DP_ARADDR(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
M_AXI_DP_ARPROT(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
M_AXI_DP_ARREADY => microblaze_0_axi_dp_ARREADY(0),
M_AXI_DP_ARVALID => microblaze_0_axi_dp_ARVALID,
M_AXI_DP_AWADDR(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
M_AXI_DP_AWPROT(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
M_AXI_DP_AWREADY => microblaze_0_axi_dp_AWREADY(0),
M_AXI_DP_AWVALID => microblaze_0_axi_dp_AWVALID,
M_AXI_DP_BREADY => microblaze_0_axi_dp_BREADY,
M_AXI_DP_BRESP(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
M_AXI_DP_BVALID => microblaze_0_axi_dp_BVALID(0),
M_AXI_DP_RDATA(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
M_AXI_DP_RREADY => microblaze_0_axi_dp_RREADY,
M_AXI_DP_RRESP(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
M_AXI_DP_RVALID => microblaze_0_axi_dp_RVALID(0),
M_AXI_DP_WDATA(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
M_AXI_DP_WREADY => microblaze_0_axi_dp_WREADY(0),
M_AXI_DP_WSTRB(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
M_AXI_DP_WVALID => microblaze_0_axi_dp_WVALID,
Read_Strobe => microblaze_0_dlmb_1_READSTROBE,
Reset => rst_clk_wiz_1_100M_mb_reset,
Write_Strobe => microblaze_0_dlmb_1_WRITESTROBE
);
microblaze_0_axi_intc: component top_microblaze_0_axi_intc_1
port map (
interrupt_address(31 downto 0) => microblaze_0_interrupt_ADDRESS(31 downto 0),
intr(1 downto 0) => microblaze_0_intr(1 downto 0),
irq => microblaze_0_interrupt_INTERRUPT,
processor_ack(1) => microblaze_0_interrupt_ACK(0),
processor_ack(0) => microblaze_0_interrupt_ACK(1),
processor_clk => microblaze_0_Clk,
processor_rst => rst_clk_wiz_1_100M_mb_reset,
s_axi_aclk => microblaze_0_Clk,
s_axi_araddr(8 downto 0) => microblaze_0_intc_axi_ARADDR(8 downto 0),
s_axi_aresetn => rst_clk_wiz_1_100M_peripheral_aresetn(0),
s_axi_arready => microblaze_0_intc_axi_ARREADY,
s_axi_arvalid => microblaze_0_intc_axi_ARVALID,
s_axi_awaddr(8 downto 0) => microblaze_0_intc_axi_AWADDR(8 downto 0),
s_axi_awready => microblaze_0_intc_axi_AWREADY,
s_axi_awvalid => microblaze_0_intc_axi_AWVALID,
s_axi_bready => microblaze_0_intc_axi_BREADY,
s_axi_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
s_axi_bvalid => microblaze_0_intc_axi_BVALID,
s_axi_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
s_axi_rready => microblaze_0_intc_axi_RREADY,
s_axi_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
s_axi_rvalid => microblaze_0_intc_axi_RVALID,
s_axi_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
s_axi_wready => microblaze_0_intc_axi_WREADY,
s_axi_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
s_axi_wvalid => microblaze_0_intc_axi_WVALID
);
microblaze_0_axi_periph: entity work.top_microblaze_0_axi_periph_1
port map (
ACLK => microblaze_0_Clk,
ARESETN => rst_clk_wiz_1_100M_interconnect_aresetn(0),
M00_ACLK => microblaze_0_Clk,
M00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => microblaze_0_intc_axi_ARADDR(31 downto 0),
M00_AXI_arready => microblaze_0_intc_axi_ARREADY,
M00_AXI_arvalid => microblaze_0_intc_axi_ARVALID,
M00_AXI_awaddr(31 downto 0) => microblaze_0_intc_axi_AWADDR(31 downto 0),
M00_AXI_awready => microblaze_0_intc_axi_AWREADY,
M00_AXI_awvalid => microblaze_0_intc_axi_AWVALID,
M00_AXI_bready => microblaze_0_intc_axi_BREADY,
M00_AXI_bresp(1 downto 0) => microblaze_0_intc_axi_BRESP(1 downto 0),
M00_AXI_bvalid => microblaze_0_intc_axi_BVALID,
M00_AXI_rdata(31 downto 0) => microblaze_0_intc_axi_RDATA(31 downto 0),
M00_AXI_rready => microblaze_0_intc_axi_RREADY,
M00_AXI_rresp(1 downto 0) => microblaze_0_intc_axi_RRESP(1 downto 0),
M00_AXI_rvalid => microblaze_0_intc_axi_RVALID,
M00_AXI_wdata(31 downto 0) => microblaze_0_intc_axi_WDATA(31 downto 0),
M00_AXI_wready => microblaze_0_intc_axi_WREADY,
M00_AXI_wstrb(3 downto 0) => microblaze_0_intc_axi_WSTRB(3 downto 0),
M00_AXI_wvalid => microblaze_0_intc_axi_WVALID,
M01_ACLK => microblaze_0_Clk,
M01_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => microblaze_0_mdm_axi_ARADDR(31 downto 0),
M01_AXI_arready => microblaze_0_mdm_axi_ARREADY,
M01_AXI_arvalid => microblaze_0_mdm_axi_ARVALID,
M01_AXI_awaddr(31 downto 0) => microblaze_0_mdm_axi_AWADDR(31 downto 0),
M01_AXI_awready => microblaze_0_mdm_axi_AWREADY,
M01_AXI_awvalid => microblaze_0_mdm_axi_AWVALID,
M01_AXI_bready => microblaze_0_mdm_axi_BREADY,
M01_AXI_bresp(1 downto 0) => microblaze_0_mdm_axi_BRESP(1 downto 0),
M01_AXI_bvalid => microblaze_0_mdm_axi_BVALID,
M01_AXI_rdata(31 downto 0) => microblaze_0_mdm_axi_RDATA(31 downto 0),
M01_AXI_rready => microblaze_0_mdm_axi_RREADY,
M01_AXI_rresp(1 downto 0) => microblaze_0_mdm_axi_RRESP(1 downto 0),
M01_AXI_rvalid => microblaze_0_mdm_axi_RVALID,
M01_AXI_wdata(31 downto 0) => microblaze_0_mdm_axi_WDATA(31 downto 0),
M01_AXI_wready => microblaze_0_mdm_axi_WREADY,
M01_AXI_wstrb(3 downto 0) => microblaze_0_mdm_axi_WSTRB(3 downto 0),
M01_AXI_wvalid => microblaze_0_mdm_axi_WVALID,
M02_ACLK => microblaze_0_Clk,
M02_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready => microblaze_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => microblaze_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready => microblaze_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => microblaze_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => microblaze_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => microblaze_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => microblaze_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => microblaze_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => microblaze_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => microblaze_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => microblaze_0_Clk,
M03_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => microblaze_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => microblaze_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => microblaze_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => microblaze_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => microblaze_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => microblaze_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => microblaze_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => microblaze_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => microblaze_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => microblaze_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => microblaze_0_Clk,
M04_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => microblaze_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => microblaze_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => microblaze_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => microblaze_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => microblaze_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => microblaze_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => microblaze_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => microblaze_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => microblaze_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => microblaze_0_axi_periph_M04_AXI_WVALID,
M05_ACLK => microblaze_0_Clk,
M05_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => microblaze_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid => microblaze_0_axi_periph_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => microblaze_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid => microblaze_0_axi_periph_M05_AXI_AWVALID,
M05_AXI_bready => microblaze_0_axi_periph_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => microblaze_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => microblaze_0_axi_periph_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => microblaze_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => microblaze_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => microblaze_0_axi_periph_M05_AXI_WVALID,
M06_ACLK => microblaze_0_Clk,
M06_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
M06_AXI_araddr(31 downto 0) => microblaze_0_axi_periph_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready => microblaze_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid => microblaze_0_axi_periph_M06_AXI_ARVALID,
M06_AXI_awaddr(31 downto 0) => microblaze_0_axi_periph_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready => microblaze_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid => microblaze_0_axi_periph_M06_AXI_AWVALID,
M06_AXI_bready => microblaze_0_axi_periph_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => microblaze_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => microblaze_0_axi_periph_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => microblaze_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => microblaze_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => microblaze_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => microblaze_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wstrb(3 downto 0) => microblaze_0_axi_periph_M06_AXI_WSTRB(3 downto 0),
M06_AXI_wvalid => microblaze_0_axi_periph_M06_AXI_WVALID,
S00_ACLK => microblaze_0_Clk,
S00_ARESETN => rst_clk_wiz_1_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => microblaze_0_axi_dp_ARADDR(31 downto 0),
S00_AXI_arprot(2 downto 0) => microblaze_0_axi_dp_ARPROT(2 downto 0),
S00_AXI_arready(0) => microblaze_0_axi_dp_ARREADY(0),
S00_AXI_arvalid(0) => microblaze_0_axi_dp_ARVALID,
S00_AXI_awaddr(31 downto 0) => microblaze_0_axi_dp_AWADDR(31 downto 0),
S00_AXI_awprot(2 downto 0) => microblaze_0_axi_dp_AWPROT(2 downto 0),
S00_AXI_awready(0) => microblaze_0_axi_dp_AWREADY(0),
S00_AXI_awvalid(0) => microblaze_0_axi_dp_AWVALID,
S00_AXI_bready(0) => microblaze_0_axi_dp_BREADY,
S00_AXI_bresp(1 downto 0) => microblaze_0_axi_dp_BRESP(1 downto 0),
S00_AXI_bvalid(0) => microblaze_0_axi_dp_BVALID(0),
S00_AXI_rdata(31 downto 0) => microblaze_0_axi_dp_RDATA(31 downto 0),
S00_AXI_rready(0) => microblaze_0_axi_dp_RREADY,
S00_AXI_rresp(1 downto 0) => microblaze_0_axi_dp_RRESP(1 downto 0),
S00_AXI_rvalid(0) => microblaze_0_axi_dp_RVALID(0),
S00_AXI_wdata(31 downto 0) => microblaze_0_axi_dp_WDATA(31 downto 0),
S00_AXI_wready(0) => microblaze_0_axi_dp_WREADY(0),
S00_AXI_wstrb(3 downto 0) => microblaze_0_axi_dp_WSTRB(3 downto 0),
S00_AXI_wvalid(0) => microblaze_0_axi_dp_WVALID
);
microblaze_0_local_memory: entity work.microblaze_0_local_memory_imp_1PW29UC
port map (
DLMB_abus(0 to 31) => microblaze_0_dlmb_1_ABUS(0 to 31),
DLMB_addrstrobe => microblaze_0_dlmb_1_ADDRSTROBE,
DLMB_be(0 to 3) => microblaze_0_dlmb_1_BE(0 to 3),
DLMB_ce => microblaze_0_dlmb_1_CE,
DLMB_readdbus(0 to 31) => microblaze_0_dlmb_1_READDBUS(0 to 31),
DLMB_readstrobe => microblaze_0_dlmb_1_READSTROBE,
DLMB_ready => microblaze_0_dlmb_1_READY,
DLMB_ue => microblaze_0_dlmb_1_UE,
DLMB_wait => microblaze_0_dlmb_1_WAIT,
DLMB_writedbus(0 to 31) => microblaze_0_dlmb_1_WRITEDBUS(0 to 31),
DLMB_writestrobe => microblaze_0_dlmb_1_WRITESTROBE,
ILMB_abus(0 to 31) => microblaze_0_ilmb_1_ABUS(0 to 31),
ILMB_addrstrobe => microblaze_0_ilmb_1_ADDRSTROBE,
ILMB_ce => microblaze_0_ilmb_1_CE,
ILMB_readdbus(0 to 31) => microblaze_0_ilmb_1_READDBUS(0 to 31),
ILMB_readstrobe => microblaze_0_ilmb_1_READSTROBE,
ILMB_ready => microblaze_0_ilmb_1_READY,
ILMB_ue => microblaze_0_ilmb_1_UE,
ILMB_wait => microblaze_0_ilmb_1_WAIT,
LMB_Clk => microblaze_0_Clk,
SYS_Rst => rst_clk_wiz_1_100M_bus_struct_reset(0)
);
microblaze_0_xlconcat: component top_microblaze_0_xlconcat_1
port map (
In0(0) => axi_uartlite_0_interrupt,
In1(0) => mdm_1_Interrupt,
dout(1 downto 0) => microblaze_0_intr(1 downto 0)
);
rst_clk_wiz_1_100M: component top_rst_clk_wiz_1_100M_1
port map (
aux_reset_in => '1',
bus_struct_reset(0) => rst_clk_wiz_1_100M_bus_struct_reset(0),
dcm_locked => clk_wiz_1_locked,
ext_reset_in => reset_1,
interconnect_aresetn(0) => rst_clk_wiz_1_100M_interconnect_aresetn(0),
mb_debug_sys_rst => mdm_1_debug_sys_rst,
mb_reset => rst_clk_wiz_1_100M_mb_reset,
peripheral_aresetn(0) => rst_clk_wiz_1_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_clk_wiz_1_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => microblaze_0_Clk
);
xlconcat_0: component top_xlconcat_0_0
port map (
In0(0) => FSM_0_COMPL,
In1(0) => FSM_ENABLE_NODES_0_SH_DONE,
In2(29 downto 0) => xlconstant_1_dout(29 downto 0),
dout(31 downto 0) => xlconcat_0_dout(31 downto 0)
);
xlconcat_1: component top_xlconcat_1_0
port map (
In0(23 downto 0) => FSM_0_RESULT(23 downto 0),
In1(7 downto 0) => xlconstant_2_dout(7 downto 0),
dout(31 downto 0) => xlconcat_1_dout(31 downto 0)
);
xlconstant_0: component top_xlconstant_0_0
port map (
dout(0) => xlconstant_0_dout(0)
);
xlconstant_1: component top_xlconstant_1_0
port map (
dout(29 downto 0) => xlconstant_1_dout(29 downto 0)
);
xlconstant_2: component top_xlconstant_2_0
port map (
dout(7 downto 0) => xlconstant_2_dout(7 downto 0)
);
xlslice_0: component top_xlslice_0_0
port map (
Din(31 downto 0) => axi_gpio_0_gpio_io_o(31 downto 0),
Dout(0) => xlslice_0_Dout(0)
);
xlslice_1: component top_xlslice_0_1
port map (
Din(31 downto 0) => axi_gpio_0_gpio_io_o(31 downto 0),
Dout(0) => xlslice_1_Dout(0)
);
xlslice_2: component top_xlslice_0_2
port map (
Din(31 downto 0) => axi_gpio_0_gpio_io_o(31 downto 0),
Dout(0) => xlslice_2_Dout(0)
);
xlslice_3: component top_xlslice_0_3
port map (
Din(31 downto 0) => axi_gpio_0_gpio_io_o(31 downto 0),
Dout(0) => xlslice_3_Dout(0)
);
xlslice_4: component top_xlslice_0_4
port map (
Din(31 downto 0) => axi_gpio_0_gpio_io_o(31 downto 0),
Dout(0) => xlslice_4_Dout(0)
);
xlslice_5: component top_xlslice_5_0
port map (
Din(31 downto 0) => axi_gpio_2_gpio_io_o(31 downto 0),
Dout(10 downto 0) => xlslice_5_Dout(10 downto 0)
);
end STRUCTURE;
|
mit
|
6e16bbe7bcaaf7057010b2820ede9411
| 0.675649 | 2.889361 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_1/spy_tb/top_tb_withBPBComp_r1.vhd
| 1 | 6,813 |
-------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Branch Prediction Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- synopsys translate_off
--use reverseAssemblyFunctionPkg.all; --modified by sabya - not needed in top!
-- synopsys translate_on
-----------------------------------------------------------------------------
--added by Sabya to use compiled library
library ee560;
use ee560.all;
------------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_ROB of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden BPB)
signal Bpb_BranchPrediction_gold :std_logic;
-- Signals for the student's DUT (BPB)
signal Resetb :std_logic;
signal Dis_CdbUpdBranch :std_logic;
signal Dis_CdbUpdBranchAddr :std_logic_vector(2 downto 0);
signal Dis_CdbBranchOutcome :std_logic;
signal Bpb_BranchPrediction :std_logic;
signal Dis_BpbBranchPCBits :std_logic_vector(2 downto 0) ;
signal Dis_BpbBranch :std_logic;
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
Clk : in std_logic;
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component bpb
port (
Clk : in std_logic;
Resetb : in std_logic;
Dis_CdbUpdBranch : in std_logic;
Dis_CdbUpdBranchAddr : in std_logic_vector(2 downto 0);
Dis_CdbBranchOutcome : in std_logic;
Bpb_BranchPrediction : out std_logic;
Dis_BpbBranchPCBits : in std_logic_vector(2 downto 0) ;
Dis_BpbBranch : in std_logic
);
end component bpb;
for BPB_UUT: bpb use entity work.bpb(behv);
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
BPB_UUT: bpb
port map (
Clk => Clk,
Resetb => Resetb,
Dis_CdbUpdBranch=>Dis_CdbUpdBranch,
Dis_CdbUpdBranchAddr=>Dis_CdbUpdBranchAddr,
Dis_CdbBranchOutcome=>Dis_CdbBranchOutcome,
Bpb_BranchPrediction=>Bpb_BranchPrediction,
Dis_BpbBranchPCBits=>Dis_BpbBranchPCBits,
Dis_BpbBranch=>Dis_BpbBranch
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of Branch Prediction Buffer only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (Bpb_BranchPrediction_gold /= Bpb_BranchPrediction) then
write (my_outline, string'("ERROR! Bpb_BranchPrediction of TEST does not match Bpb_BranchPrediction_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/Resetb","Resetb",0);
init_signal_spy("/UUT/Dis_CdbUpdBranch","Dis_CdbUpdBranch",1,1);
enable_signal_spy("/UUT/Dis_CdbUpdBranch","Dis_CdbUpdBranch",0);
init_signal_spy("/UUT/Dis_CdbUpdBranchAddr","Dis_CdbUpdBranchAddr",1,1);
enable_signal_spy("/UUT/Dis_CdbUpdBranchAddr","Dis_CdbUpdBranchAddr",0);
init_signal_spy("/UUT/Dis_CdbBranchOutcome","Dis_CdbBranchOutcome",1,1);
enable_signal_spy("/UUT/Dis_CdbBranchOutcome","Dis_CdbBranchOutcome",0);
init_signal_spy("/UUT/Dis_BpbBranchPCBits","Dis_BpbBranchPCBits",1,1);
enable_signal_spy("/UUT/Dis_BpbBranchPCBits","Dis_BpbBranchPCBits",0);
init_signal_spy("/UUT/Dis_BpbBranch","Dis_BpbBranch",1,1);
enable_signal_spy("/UUT/Dis_BpbBranch","Dis_BpbBranch",0);
--outputs--
init_signal_spy("/UUT/Bpb_BranchPrediction","Bpb_BranchPrediction_gold",1,1);
enable_signal_spy("/UUT/Bpb_BranchPrediction","Bpb_BranchPrediction_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_ROB;
|
gpl-2.0
|
9c0ea09bbd9cf533d33692b66d13d2c0
| 0.631587 | 3.376115 | false | false | false | false |
tuura/fantasi
|
dependencies/register.vhdl
| 1 | 987 |
-- Generic size register made with D Flip Flops
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY Generic_register IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N-1 downto 0));
END Generic_register;
ARCHITECTURE structural OF Generic_register IS
COMPONENT ffd IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
BEGIN
REG_GENERATOR : for i in 0 to N-1 generate
FFD_I : ffd PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
D => DIN(i),
Q => DOUT(i));
END GENERATE;
END structural;
|
mit
|
70ab61f5e67a1c93427b5a93e07cb262
| 0.477204 | 3.655556 | false | false | false | false |
csrhau/sandpit
|
VHDL/dual_port_vram/test_ram.vhdl
| 1 | 2,190 |
library ieee;
use ieee.std_logic_1164.all;
entity test_ram is
end test_ram;
architecture behavioural of test_ram is
component RAM is
port (
clock : in std_logic;
-- Port a has read and write
a_addr : in std_logic_vector(9 downto 0);
a_write : in std_logic;
a_din : in std_logic_vector(7 downto 0);
a_dout : out std_logic_vector(7 downto 0);
-- Port b is read only
b_addr : in std_logic_vector(9 downto 0);
b_dout : out std_logic_vector(7 downto 0)
);
end component RAM;
signal clock : std_logic;
signal a_addr : std_logic_vector(9 downto 0);
signal a_write : std_logic;
signal a_din : std_logic_vector(7 downto 0);
signal a_dout : std_logic_vector(7 downto 0);
signal b_addr : std_logic_vector(9 downto 0);
signal b_dout : std_logic_vector(7 downto 0);
begin
ramcell : RAM port map (
clock,
a_addr,
a_write,
a_din,
a_dout,
b_addr,
b_dout
);
process
begin
clock <= '0';
wait for 1 ns;
a_addr <= "0000000000";
b_addr <= "0000000001";
a_write <= '0';
a_din <= "11111111";
clock <= '1';
wait for 1 ns;
assert a_dout = "00000000"
report "PORT A should show initial value of zero" severity error;
assert b_dout = "00000000"
report "PORT B should show initial value of zero" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert a_dout = "00000000"
report "PORT A should still show initial value of zero" severity error;
assert b_dout = "00000000"
report "PORT B should still show initial value of zero" severity error;
clock <= '0';
wait for 1 ns;
a_write <= '1';
clock <= '1';
wait for 1 ns;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert a_dout = "11111111"
report "PORT A should show newly written value" severity error;
assert b_dout = "00000000"
report "PORT B should still show initial value of zero" severity error;
wait;
end process;
end behavioural;
|
mit
|
6f01713b89c6eac391d429bca007eb98
| 0.575799 | 3.5209 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_1/exercise_IU_BPB_SB_SAB_ee560/bpb_NEW.vhd
| 1 | 6,460 |
------------------------------------------------------------------------------
--
-- Design : Branch Predicton Buffer
-- Project : Tomasulo Processor
-- Entity : bpb
-- Author : kapil
-- Company : University of Southern California
-- Last Updated : June 24, 2010
-- Last Updated by : Waleed Dweik
-- Modification : 1. Modify the branch prediction to use the most well-known state machine of the 2-bit saturating counter
-- 2. Update old comments
-------------------------------------------------------------------------------
--
-- Description : 2 - bit wide / 8 deep
-- each 2 bit locn is a state machine
-- 2 bit saturating counter
-- 00 strongly nottaken
-- 01 mildly nottaken
-- 10 mildly taken
-- 11 strongly taken
--
-------------------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------------------------------------
entity bpb is
port (
Clk : in std_logic;
Resetb : in std_logic;
---- Interaction with Cdb -------------------
Dis_CdbUpdBranch : in std_logic; -- indicates that a branch appears on Cdb(wen to bpb)
Dis_CdbUpdBranchAddr : in std_logic_vector(2 downto 0);-- indiactes the last 3 bit addr of the branch on the Cdb
Dis_CdbBranchOutcome : in std_logic; -- indiacates the outocome of the branch to the bpb: 0 means nottaken and 1 means taken
---- Interaction with dispatch --------------
Bpb_BranchPrediction : out std_logic; --This bit tells the dispatch what the prediction actually based on bpb state-mc
Dis_BpbBranchPCBits : in std_logic_vector(2 downto 0) ;--indiaces the 3 least sig bits of the current instr being dispatched
Dis_BpbBranch : in std_logic -- indiactes that there is a branch instr in the dispatch (ren to the bpb)
);
end bpb;
architecture behv of bpb is
subtype sat_counters is std_logic_vector(1 downto 0);
type bpb_array is array (0 to 7) of sat_counters ;
signal bpb_array_r: bpb_array ; -- An array of 8 2-bit saturating counters represents 8 location bpb.
signal Bpb_read_status,Bpb_write_status : std_logic_vector(1 downto 0);
begin
---------------------------------------------------------------------------
-- Task1: Complete the following 2 concurrent statements for Bpb read and write status:
-- Hint: You may want to use CONV_INTEGER function to convert from std_logic_vector to an integer
-- Bpb_read_status represets the 2-bit counter value in the Bpb entry addressed by the branch instruction in dispatch.
-- Bpb_read_status tells whether branch should predicted Taken (11,10) or not Taken (00,01)
Bpb_read_status <= --
-- Bpb_write_status represents the 2-bit counter value in the Bpb entry addressed by the branch instruction on the Cdb.
-- Bpb_write_status is used along with the actual outcome of the branch on Cdb to update the corresponding Bpb entry.
Bpb_write_status <= --
---------------------------------------------------------------------------
-- Update Process
-- This prcoess is used to update the Bpb entry indexed by the PC[4:2] of the branch instruction which appears on Cdb.
-- The update process is based on the State machine for a 2-bit saturating counter which is given in the slide set.
bpb_write: process (Clk,Resetb)
variable write_data_bpb: std_logic_vector(1 downto 0);
variable bpb_waddr_mask ,bpb_index_addr,raw_bpb_addr: std_logic_vector(7 downto 0);
begin
if (Resetb = '0') then
-------------------------------Initialize register file contents(!! weakly taken, weakly not taken alternatvely!!) here----------------------------------
bpb_array_r <= (
"01", -- $0
"10", -- $1
"01", -- $2
"10", -- $3
"01", -- $4
"10", -- $5
"01", -- $6
"10" -- $7
);
elsif(Clk'event and Clk='1') then
if (Dis_CdbUpdBranch = '1')then
bpb_waddr_mask := X"FF";
else
bpb_waddr_mask := X"00";
end if ;
case Dis_CdbUpdBranchAddr is
when "000" => raw_bpb_addr := ("00000001");
when "001" => raw_bpb_addr := ("00000010");
when "010" => raw_bpb_addr := ("00000100");
when "011" => raw_bpb_addr := ("00001000");
when "100" => raw_bpb_addr := ("00010000");
when "101" => raw_bpb_addr := ("00100000");
when "110" => raw_bpb_addr := ("01000000");
when others => raw_bpb_addr := ("10000000");
end case ;
bpb_index_addr := raw_bpb_addr and bpb_waddr_mask ;
---------------------------------------------------------------------------
-- Task2: Add the Code inside the for loop to modify Bpb entries:
-- Hint: According to the current counter value of the corresponding entry and the actual outcome of the branch on Cdb you can
-- decide what is the new prediction value should be based on the state machine given in the slides.
---------------------------------------------------------------------------
for i in 0 to 7 loop
-- Add your Code here
end loop;
end if;
end process bpb_write;
-- Prediction Process
-- This prcoess generates Bpb_BranchPrediction signal which indicates the prediction for branch instruction
-- The signal is always set to '0' except when there is a branch instruction in dispatch and the prediction is either Strongly Taken or Taken.
bpb_predict : process(Bpb_read_status ,Dis_BpbBranch)
begin
Bpb_BranchPrediction<= '0';
if (Bpb_read_status(1) = '0' ) then
Bpb_BranchPrediction<= '0';
else
Bpb_BranchPrediction<= '1' and Dis_BpbBranch;
end if ;
end process;
end behv;
|
gpl-2.0
|
d7dcd771f643df0104b262e6c2f60868
| 0.516718 | 4.66426 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/GC_fifo/simulation/fg_tb_synth.vhd
| 1 | 10,013 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 12,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : GC_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
2b37b71505e1240339fc9bda66b377a6
| 0.458104 | 4.166875 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/controller_command_fifo/simulation/fg_tb_top.vhd
| 3 | 5,679 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
98d8983baf416691cdce009feb5e7abe
| 0.616306 | 4.175735 | false | false | false | false |
csrhau/sandpit
|
VHDL/stencil_buffer/test_stencil_buffer.vhdl
| 1 | 4,585 |
library ieee;
use ieee.std_logic_1164.all;
entity test_stencil_buffer is
end test_stencil_buffer;
architecture behavioural of test_stencil_buffer is
component stencil_buffer is
generic (
addr_bits : natural
);
port (
clock : in std_logic;
advance: in std_logic;
input : in std_logic_vector;
tl : out std_logic_vector;
tc : out std_logic_vector;
tr : out std_logic_vector;
ml : out std_logic_vector;
mc : out std_logic_vector;
mr : out std_logic_vector;
bl : out std_logic_vector;
bc : out std_logic_vector;
br : out std_logic_vector
);
end component stencil_buffer;
signal period: time := 10 ns;
signal clock : std_logic := '0';
signal finished : std_logic := '0';
signal advance : std_logic := '0';
signal input : std_logic_vector(7 downto 0);
signal tl : std_logic_vector(7 downto 0);
signal tc : std_logic_vector(7 downto 0);
signal tr : std_logic_vector(7 downto 0);
signal ml : std_logic_vector(7 downto 0);
signal mc : std_logic_vector(7 downto 0);
signal mr : std_logic_vector(7 downto 0);
signal bl : std_logic_vector(7 downto 0);
signal bc : std_logic_vector(7 downto 0);
signal br : std_logic_vector(7 downto 0);
begin
clock <= not clock after period/2 when finished='0';
BUFF: stencil_buffer generic map (addr_bits => 4) -- 16 places; large enough for a 3x3 stencil
port map (clock, advance, input,
tl, tc, tr,
ml, mc, mr,
bl, bc, br);
process
begin
-- Fill test
advance <= '1';
input <= "11001100";
wait for 9 * period;
assert tl = "11001100" report "tl should be filled" severity error;
assert tc = "11001100" report "tc should be filled" severity error;
assert tr = "11001100" report "tr should be filled" severity error;
assert ml = "11001100" report "ml should be filled" severity error;
assert mc = "11001100" report "mc should be filled" severity error;
assert mr = "11001100" report "mr should be filled" severity error;
assert bl = "11001100" report "bl should be filled" severity error;
assert bc = "11001100" report "bc should be filled" severity error;
assert br = "11001100" report "br should be filled" severity error;
-- Order test
input <= "00000000"; wait for period;
input <= "00000001"; wait for period;
input <= "00000010"; wait for period;
input <= "00000011"; wait for period;
input <= "00000100"; wait for period;
input <= "00000101"; wait for period;
input <= "00000110"; wait for period;
input <= "00000111"; wait for period;
input <= "00001000"; wait for period;
assert tl = "00000000" report "tl should contain the correct value" severity error;
assert tc = "00000001" report "tc should contain the correct value" severity error;
assert tr = "00000010" report "tr should contain the correct value" severity error;
assert ml = "00000011" report "ml should contain the correct value" severity error;
assert mc = "00000100" report "mc should contain the correct value" severity error;
assert mr = "00000101" report "mr should contain the correct value" severity error;
assert bl = "00000110" report "bl should contain the correct value" severity error;
assert bc = "00000111" report "bc should contain the correct value" severity error;
assert br = "00001000" report "br should contain the correct value" severity error;
-- Scroll test
input <= "00001001"; wait for period;
input <= "00001010"; wait for period;
input <= "00001011"; wait for period;
assert tl = "00000011" report "tl should contain the correct value" severity error;
assert tc = "00000100" report "tc should contain the correct value" severity error;
assert tr = "00000101" report "tr should contain the correct value" severity error;
assert ml = "00000110" report "ml should contain the correct value" severity error;
assert mc = "00000111" report "mc should contain the correct value" severity error;
assert mr = "00001000" report "mr should contain the correct value" severity error;
assert bl = "00001001" report "bl should contain the correct value" severity error;
assert bc = "00001010" report "bc should contain the correct value" severity error;
assert br = "00001011" report "br should contain the correct value" severity error;
wait for 30 * period;
finished <= '1';
wait;
end process;
end behavioural;
|
mit
|
e902b59fb3804b43fbcfce769cee0c5f
| 0.660851 | 4.082814 | false | true | false | false |
csrhau/sandpit
|
VHDL/striped_gol/gol_processor.vhdl
| 1 | 1,440 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- 0 1 2 3 4 5 6 7 8 9
-- input | | | | | | | | | | |
-- middle | | | | | | | | | | |
-- bottom | | | | | | | | | | |
-- output x| | | | | | | | |x
--
entity gol_processor is
port (
clock : in std_logic;
input : in std_logic_vector(9 downto 0);
output: out std_logic_vector(8 downto 1)
);
end entity gol_processor;
architecture behavioural of gol_processor is
function popcnt(vector : std_logic_vector) return natural is
variable result : natural range 0 to vector'length := 0;
begin
for i in vector'range loop
if vector(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end function popcnt;
signal middle : std_logic_vector(9 downto 0) := "0000000000";
signal bottom : std_logic_vector(9 downto 0) := "0000000000";
begin
process(clock)
variable count: natural range 0 to 9;
begin
if rising_edge(clock) then
for i in output'range loop
count := popcnt(input(i+1 downto i-1)
& middle(i+1 downto i-1)
& bottom(i+1 downto i-1));
if count = 3 then
output(i) <= '1';
elsif count = 4 then
output(i) <= middle(i);
else
output(i) <= '0';
end if;
end loop;
middle <= input;
bottom <= middle;
end if;
end process;
end behavioural;
|
mit
|
dc8ca06749dc0e50ef2942e38b3d4b7d
| 0.552778 | 3.420428 | false | false | false | false |
BBN-Q/APS2-TDM
|
src/tdm_csr.vhd
| 1 | 6,188 |
-- AXI memory mapped CSR registers
--
-- Original authors: Colm Ryan, Brian Donovan
-- Copyright 2015-2016, Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TDM_CSR is
port (
--CSR control ports
resets : out std_logic_vector(31 downto 0);
control : out std_logic_vector(31 downto 0);
trigger_interval : out std_logic_vector(31 downto 0);
-- CSR status ports
status : in std_logic_vector(31 downto 0);
trigger_word : in std_logic_vector(31 downto 0);
SATA_status : in std_logic_vector(31 downto 0);
uptime_seconds : in std_logic_vector(31 downto 0);
uptime_nanoseconds : in std_logic_vector(31 downto 0);
tdm_version : in std_logic_vector(31 downto 0);
temperature : in std_logic_vector(31 downto 0);
git_sha1 : in std_logic_vector(31 downto 0);
build_timestamp : in std_logic_vector(31 downto 0);
-- slave AXI bus
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(6 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(6 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end entity;
architecture arch of TDM_CSR is
-- array of registers
constant NUM_REGS : natural := 32;
type REG_ARRAY_t is array(natural range <>) of std_logic_vector(31 downto 0) ;
signal regs : REG_ARRAY_t(0 to NUM_REGS-1) := (others => (others => '0'));
signal write_reg_addr : integer range 0 to NUM_REGS-1;
signal read_reg_addr : integer range 0 to NUM_REGS-1;
-- internal AXI signals
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_wdata : std_logic_vector(31 downto 0);
signal axi_wstrb : std_logic_vector(3 downto 0);
signal axi_bvalid : std_logic;
signal axi_arready : std_logic;
signal axi_rvalid : std_logic;
begin
-- wire control/status ports to internal registers
resets <= regs(8);
control <= regs(9);
trigger_interval <= regs(12);
read_regs_register_pro: process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
regs(0) <= status;
regs(11) <= trigger_word;
regs(18) <= SATA_status;
regs(20) <= uptime_seconds;
regs(21) <= uptime_nanoseconds;
regs(22) <= tdm_version;
regs(23) <= temperature;
regs(24) <= git_sha1;
regs(25) <= build_timestamp;
end if;
end process;
-- connect internal AXI signals
s_axi_awready <= axi_awready;
s_axi_wready <= axi_wready;
s_axi_bvalid <= axi_bvalid;
s_axi_arready <= axi_arready;
s_axi_rvalid <= axi_rvalid;
-- simplistic response to write requests that only handles one write at a time
-- 1. hold awready and wready low
-- 2. wait until both awvalid and wvalid are asserted
-- 3. assert awready and wready high; latch write address and data
-- 4. update control register
-- 5. always respond with OK
s_axi_bresp <= "00";
write_ready_pro : process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
if s_axi_aresetn = '0' then
axi_awready <= '0';
axi_wready <= '0';
axi_bvalid <= '0';
else
if (axi_awready = '0' and axi_wready = '0' and s_axi_awvalid = '1' and s_axi_wvalid = '1') then
axi_awready <= '1';
axi_wready <= '1';
else
axi_awready <= '0';
axi_wready <= '0';
end if;
-- once writing set response valid high until accepted
if axi_wready = '1' then
axi_bvalid <= '1';
elsif axi_bvalid = '1' and s_axi_bready = '1' then
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- update control / internal registers
update_write_regs_pro : process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
-- decode register address
write_reg_addr <= to_integer(unsigned(s_axi_awaddr(s_axi_awaddr'high downto 2)));
-- register data and byte enables
axi_wdata <= s_axi_wdata;
axi_wstrb <= s_axi_wstrb;
if s_axi_aresetn = '0' then
regs(8) <= x"00000000"; -- resets
regs(9) <= x"00000000"; -- control
regs(12) <= x"000186a0"; -- trigger_interval
else
for ct in 0 to 3 loop
if axi_wstrb(ct) = '1' and axi_wready = '1' then
-- resets
if write_reg_addr = 8 then
regs(8)(ct*8+7 downto ct*8) <= axi_wdata(ct*8+7 downto ct*8);
end if;
-- control
if write_reg_addr = 9 then
regs(9)(ct*8+7 downto ct*8) <= axi_wdata(ct*8+7 downto ct*8);
end if;
-- trigger_interval
if write_reg_addr = 12 then
regs(12)(ct*8+7 downto ct*8) <= axi_wdata(ct*8+7 downto ct*8);
end if;
end if;
end loop;
end if;
end if;
end process;
-- read response
-- respond with data one clock later
s_axi_rresp <= "00"; -- always OK
read_response_pro : process (s_axi_aclk)
begin
if rising_edge(s_axi_aclk) then
if s_axi_aresetn = '0' then
axi_arready <= '0';
read_reg_addr <= 0;
s_axi_rdata <= (others => '0');
axi_rvalid <= '0';
else
-- acknowledge and latch address when no outstanding read responses
if axi_arready = '0' and s_axi_arvalid = '1' then
axi_arready <= '1';
-- latch register address
read_reg_addr <= to_integer(unsigned(s_axi_araddr(s_axi_araddr'high downto 2)));
else
axi_arready <= '0';
end if;
-- hold data valid high after latching address and until response
if axi_arready = '1' then
axi_rvalid <= '1';
elsif axi_rvalid = '1' and s_axi_rready = '1' then
axi_rvalid <= '0';
end if;
-- register out data
s_axi_rdata <= regs(read_reg_addr);
end if;
end if;
end process;
end architecture;
|
mpl-2.0
|
ee0fa6aaa5d4ea823efbcc7d62cebf90
| 0.631222 | 2.879479 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/i_fetch_fifo_ram_reg_array.vhd
| 1 | 1,645 |
-------------------------------------------------------------------------------
-- Design : Register array for Instruction Fetch Queue i_fetch_q
-- Project : Tomasulo Processor
-- Author : Gandhi Puvvada
-- Company : University of Southern California
-- File: i_fetch_fifo_ram_reg_array.vhd (original file name: ram_n_addr_m_data_dp_clk.vhd)
-- Date: 6/27/2004, 4/13/2008, 7/22/2008
-- Following is the VHDL code for a dual-port RAM with a write clock.
-- There is no read clock. The read port is not a clocked port.
-- This is actually a register array. with no input or output registers.
-- ===================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i_fetch_fifo_ram_reg_array is
generic (N: integer := 2; M: integer := 32);
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(N-1 downto 0);
dia : in std_logic_vector(M-1 downto 0);
addrb : in std_logic_vector(N-1 downto 0);
dob : out std_logic_vector(M-1 downto 0)
);
end entity i_fetch_fifo_ram_reg_array;
architecture syn of i_fetch_fifo_ram_reg_array is
type ram_type is array (2**N-1 downto 0) of std_logic_vector (M-1 downto 0);
signal RAM : ram_type;
-- signal read_addrb : std_logic_vector(1 downto 0) := "00";
begin
process (clka)
begin
if (clka'event and clka = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) <= dia;
end if;
end if;
end process;
dob <= RAM(conv_integer(addrb)); -- not a clocked-port
end architecture syn;
-----------------------------------------------------------------------------
|
gpl-2.0
|
78b445186aa46835ec8545e32a13ed8a
| 0.586626 | 3.316532 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RECV_REQ_QUEUE/example_design/RECV_REQ_QUEUE_top_wrapper.vhd
| 1 | 19,143 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RECV_REQ_QUEUE_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RECV_REQ_QUEUE_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end RECV_REQ_QUEUE_top_wrapper;
architecture xilinx of RECV_REQ_QUEUE_top_wrapper is
SIGNAL clk_i : std_logic;
component RECV_REQ_QUEUE_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : RECV_REQ_QUEUE_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
df5a3ad5558ce7bd13270e249be219ed
| 0.486287 | 3.971577 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_command_send_fifo/example_design/pcie_command_send_fifo_top_wrapper.vhd
| 1 | 19,697 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_command_send_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_command_send_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end pcie_command_send_fifo_top_wrapper;
architecture xilinx of pcie_command_send_fifo_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_command_send_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : pcie_command_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
88c28606606dec27be09bf0d54b98760
| 0.485505 | 3.960788 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/inst_cache_dpram_r2_sim.vhd
| 1 | 9,230 |
-------------------------------------------------------------------------------
--
-- Design : inst_cache_dpram (Dual Port RAM holding cache data)
-- In summer 2008, it was inst_cache_sprom (Single Port ROM holding the cache data)
-- Project : ee560 Tomosulo -- Instruction Cache Emulator
-- Author : Srinivas Vaduvatha , Gandhi Puvvada
-- Company : University of Southern California
-- Date last revised : 7/23/2008, 7/15/2009
-------------------------------------------------------------------------------
--
-- File : inst_cache_dpram_r2.vhd (produced by modifying Summer 2008 inst_cache_sprom_r1.vhd and data_mem_dp.vhd)
--
-------------------------------------------------------------------------------
--
-- Description : This BRAM is instantiated by the instr_cache module.
-- This holds the instructions.
-- In Summer 2008, it was a ROM (BRAM acting like a ROM) with inital
-- content (instruction stream) defined through a package called
-- instr_stream_pkg.
-- In Summer 2009, it is converted to a dual port RAM. The first port (Port a) is of read/write type
-- and it faciliatates downloading a file containing cache contents from a text file holding instructions
-- in hex notation, 4 instruction per line, with Instruction0 on the right-end of the line:
-- Instruction3_ Instruction2_Instruction1_Instruction0
-- Module features:
-- Data width & Address width - Generics
-- Port b: synchronous Read only (for the processor cache read operation)
-- Port a: synchronous Read/Write (for File I/O through Adept 2.0)
-- Infers BRAM resource in Xilinx FPGAs.
-- If the width / depth specified require more bits than in a single
-- BRAM, multiple BRAMs are automatically cascaded to form a larger
-- memory by the Xilinx XST. Memory has to be of (2**n) depth.
--
-------------------------------------------------------------------------------
-- libraries and use clauses
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
use work.instr_stream_pkg.all; -- instruction stream defining package
entity inst_cache_dpram is
generic (
DATA_WIDTH : integer := 128; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
clka : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
wea : in std_logic;
data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
ena : in std_logic;
clkb : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- data_in_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- web : in std_logic;
data_out_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end inst_cache_dpram ;
architecture inferable of inst_cache_dpram is
-- signals declarations.
-- Note: A signal called "mem" of user defined type "mem_type" was declared
-- in a package called "instr_stream_pkg" refered in the use clause above.
-- It has lines similar to the following lines.
-- The initial content defines the stream of instructions.
-- -- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH)-1) of std_logic_vector((DATA_WIDTH-1) downto 0);
--*****************************************************************************************
-- This stream is used to generate the walking led pattern using memory mapped i/0
--*****************************************************************************************
signal mem : mem_type
:= (
X"00000020_AC0200FC_00421020_00000020", -- Loc 0C --nop, 08-- sw $2, 252($0) --[ 252 byte address = 64 word address], 04-- add $2, $2, $2 , 00- nop
X"00000020_00000020_00000020_08000000", -- Loc 1C, 18, 14, 10 --jump Loc 00 --rest all are NOP's
X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
begin
porta_oper : process (clka)
begin
if (clka = '1' and clka'event) then
if (wea = '1' and ena='1') then
mem(CONV_INTEGER(unsigned(addr_a))) <= data_in_a;
end if;
if( ena='1')then
data_out_a <= mem(CONV_INTEGER(unsigned(addr_a)));
end if;
end if;
end process;
portb_oper : process (clkb)
begin
if (clkb = '1' and clkb'event) then
-- if (web = '1') then
-- mem(CONV_INTEGER(addr_b)) := data_in_b;
-- end if;
data_out_b <= mem(CONV_INTEGER(unsigned(addr_b)));
end if;
end process;
end inferable ;
--- ===========================================================
|
gpl-2.0
|
42125a528cb0ec37015dd0b62454ae38
| 0.612243 | 3.315374 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/read_data_fifo_0/example_design/read_data_fifo_0_top.vhd
| 1 | 5,658 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: read_data_fifo_0_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity read_data_fifo_0_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end read_data_fifo_0_top;
architecture xilinx of read_data_fifo_0_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component read_data_fifo_0 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : read_data_fifo_0 PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
6155fbeb356915741ec645e895d45060
| 0.511311 | 4.622549 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/sdramcntl.vhd
| 1 | 18,922 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- sdramcntl.vhd
--
-- Written by D. Vanden Bout, Xess Corp.
--
-- Simplifies the SDRAM on the XSA-100 board to a SRAM like interface. Handles init
-- bank switching and refresh. Instantiated by ram control. Slightly modified
--**********************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.common.all;
entity sdramCntl is
generic(
FREQ: natural := 50_000; -- operating frequency in KHz
DATA_WIDTH: natural := 16; -- host & SDRAM data width
HADDR_WIDTH: natural := 23; -- host-side address width
SADDR_WIDTH: natural := 12 -- SDRAM-side address width
);
port(
clk: in std_logic; -- master clock
-- host side
rst: in std_logic; -- reset
rd: in std_logic; -- read data
wr: in std_logic; -- write data
done: out std_logic; -- read/write op done
hAddr: in unsigned(HADDR_WIDTH-1 downto 0); -- address from host
hDIn: in unsigned(DATA_WIDTH-1 downto 0); -- data from host
hDOut: out unsigned(DATA_WIDTH-1 downto 0); -- data to host
sdramCntl_state: out std_logic_vector(3 downto 0);
-- SDRAM side
cke: out std_logic; -- clock-enable to SDRAM
cs_n: out std_logic; -- chip-select to SDRAM
ras_n: out std_logic; -- command input to SDRAM
cas_n: out std_logic; -- command input to SDRAM
we_n: out std_logic; -- command input to SDRAM
ba: out unsigned(1 downto 0); -- SDRAM bank address bits
sAddr: out unsigned(SADDR_WIDTH-1 downto 0); -- row/column address
sData: inout unsigned(DATA_WIDTH-1 downto 0); -- in/out databus
dqmh: out std_logic; -- high databits I/O mask
dqml: out std_logic -- low databits I/O mask
);
end sdramCntl;
architecture arch of sdramCntl is
-- constants
constant NRows: natural := 4096; -- number of rows in SDRAM
constant NCols: natural := 512; -- number of columns in SDRAM
constant ColCmdPos: natural := 10; -- position of command bit in SDRAM column address
constant Tinit: natural := 200; -- min initialization interval (us)
constant Tras: natural := 45; -- min interval between active to precharge commands (ns)
constant Trc: natural := 67; -- min interval between active to active commands (ns)
constant Trcd: natural := 20; -- min interval between active and R/W commands (ns)
constant Tref: natural := 64_000_000; -- maximum refresh interval (ns)
constant Trfc: natural := 66; -- duration of refresh operation (ns)
constant Trp: natural := 20; -- min precharge command duration (ns)
constant Twr: natural := 15; -- write recovery time (ns)
constant Ccas: natural := 3; -- CAS latency (cycles)
constant Cmrd: natural := 3; -- mode register setup time (cycles)
constant RfshCycles: natural := 8; -- number of refresh cycles needed to init RAM
constant ROW_LEN: natural := log2(NRows); -- number of row address bits
constant COL_LEN: natural := log2(NCols); -- number of column address bits
constant NORM: natural := 1_000_000; -- normalize ns * KHz
constant INIT_CYCLES: natural := 1 + ((Tinit * FREQ) / 1000); -- SDRMA power-on initialization interval
constant RAS_CYCLES: natural := 1 + ((Tras * FREQ) / NORM); -- active-to-precharge interval
constant RC_CYCLES: natural := 1 + ((Trc * FREQ) / NORM); -- active-to-active interval
constant RCD_CYCLES: natural := 1 + ((Trcd * FREQ) / NORM); -- active-to-R/W interval
constant REF_CYCLES: natural := 1 + (((Tref/NROWS) * FREQ) / NORM); -- interval between row refreshes
constant RFC_CYCLES: natural := 1 + ((Trfc * FREQ) / NORM); -- refresh operation interval
constant RP_CYCLES: natural := 1 + ((Trp * FREQ) / NORM); -- precharge operation interval
constant WR_CYCLES: natural := 1 + ((Twr * FREQ) / NORM); -- write recovery time
-- states of the SDRAM controller state machine
type cntlState is (
INITWAIT, -- initialization - waiting for power-on initialization to complete
INITPCHG, -- initialization - doing precharge of banks
INITSETMODE, -- initialization - set SDRAM mode
INITRFSH, -- initialization - do refreshes
REFRESH, -- refresh a row of the SDRAM
RW, -- wait for read/write operations to SDRAM
RDDONE, -- indicate that the SDRAM read is done
WRDONE, -- indicate that the SDRAM write is done
ACTIVATE -- open a row of the SDRAM for reading/writing
);
signal state_r, state_next: cntlState; -- state register and next state
constant AUTO_PCHG_ON: std_logic := '1'; -- set sAddr(10) to this value to auto-precharge the bank
constant AUTO_PCHG_OFF: std_logic := '0'; -- set sAddr(10) to this value to disable auto-precharge
constant ALL_BANKS: std_logic := '1'; -- set sAddr(10) to this value to select all banks
constant ACTIVE_BANK: std_logic := '0'; -- set sAddr(10) to this value to select only the active bank
signal bank: unsigned(ba'range);
signal row: unsigned(ROW_LEN - 1 downto 0);
signal col: unsigned(COL_LEN - 1 downto 0);
signal col_tmp: unsigned(sAddr'high-1 downto sAddr'low);
signal changeRow: std_logic;
signal dirOut: std_logic; -- high when driving data to SDRAM
-- registers
signal activeBank_r, activeBank_next: unsigned(bank'range); -- currently active SDRAM bank
signal activeRow_r, activeRow_next: unsigned(row'range); -- currently active SDRAM row
signal inactiveFlag_r, inactiveFlag_next: std_logic; -- 1 when all SDRAM rows are inactive
signal initFlag_r, initFlag_next: std_logic; -- 1 when initializing SDRAM
signal doRfshFlag_r, doRfshFlag_next: std_logic; -- 1 when a row refresh operation is required
signal wrFlag_r, wrFlag_next: std_logic; -- 1 when writing data to SDRAM
signal rdFlag_r, rdFlag_next: std_logic; -- 1 when reading data from SDRAM
signal rfshCntr_r, rfshCntr_next: unsigned(log2(RfshCycles+1)-1 downto 0); -- counts initialization refreshes
-- timer registers that count down times for various SDRAM operations
signal timer_r, timer_next: unsigned(log2(INIT_CYCLES+1)-1 downto 0); -- current SDRAM op time
signal rasTimer_r, rasTimer_next: unsigned(log2(RAS_CYCLES+1)-1 downto 0); -- active-to-precharge time
signal wrTimer_r, wrTimer_next: unsigned(log2(WR_CYCLES+1)-1 downto 0); -- write-to-precharge time
signal refTimer_r, refTimer_next: unsigned(log2(REF_CYCLES+1)-1 downto 0); -- time between row refreshes
-- SDRAM commands
subtype sdramCmd is unsigned(5 downto 0);
-- cmd = (cs_n,ras_n,cas_n,we_n,dqmh,dqml)
constant NOP_CMD: sdramCmd := "011100";
constant ACTIVE_CMD: sdramCmd := "001100";
constant READ_CMD: sdramCmd := "010100";
constant WRITE_CMD: sdramCmd := "010000";
constant PCHG_CMD: sdramCmd := "001011";
constant MODE_CMD: sdramCmd := "000011";
constant RFSH_CMD: sdramCmd := "000111";
signal cmd: sdramCmd;
-- SDRAM mode register
subtype sdramMode is unsigned(11 downto 0);
constant MODE: sdramMode := "00" & "0" & "00" & "011" & "0" & "000";
signal logic0 : std_logic;
begin
logic0 <= '0';
hDOut <= sData(hDOut'range); -- connect SDRAM data bus to host data bus
sData <= hDIn(sData'range) when dirOut='1' else (others=>'Z'); -- connect host data bus to SDRAM data bus
combinatorial: process(rd,wr,hAddr,hDIn,state_r,bank,row,col,changeRow,
activeBank_r,activeRow_r,initFlag_r,doRfshFlag_r,rdFlag_r,wrFlag_r,
rfshCntr_r,timer_r,rasTimer_r,wrTimer_r,refTimer_r,cmd,col_tmp,inactiveFlag_r)
begin
-- attach bits in command to SDRAM control signals
(cs_n,ras_n,cas_n,we_n,dqmh,dqml) <= cmd;
-- get bank, row, column from host address
bank <= hAddr(bank'length + ROW_LEN + COL_LEN - 1 downto ROW_LEN + COL_LEN);
row <= hAddr(ROW_LEN + COL_LEN - 1 downto COL_LEN);
col <= hAddr(COL_LEN - 1 downto 0);
-- extend column (if needed) until it is as large as the (SDRAM address bus - 1)
col_tmp <= (others=>'0'); -- set it to all zeroes
col_tmp(col'range) <= col; -- write column into the lower bits
-- default operations
cke <= YES; -- enable SDRAM clock input
cmd <= NOP_CMD; -- set SDRAM command to no-operation
if initFlag_r = YES then
cs_n <= HI;
dqml <= HI;
dqmh <= HI;
end if;
done <= NO; -- pending SDRAM operation is not done
ba <= bank; -- set SDRAM bank address bits
-- set SDRAM address to column with interspersed command bit
sAddr(ColCmdPos-1 downto 0) <= col_tmp(ColCmdPos-1 downto 0);
sAddr(sAddr'high downto ColCmdPos+1) <= col_tmp(col_tmp'high downto ColCmdPos);
sAddr(ColCmdPos) <= AUTO_PCHG_OFF; -- set command bit to disable auto-precharge
dirOut <= NO;
-- default register updates
state_next <= state_r;
inactiveFlag_next <= inactiveFlag_r;
activeBank_next <= activeBank_r;
activeRow_next <= activeRow_r;
initFlag_next <= initFlag_r;
doRfshFlag_next <= doRfshFlag_r;
rdFlag_next <= rdFlag_r;
wrFlag_next <= wrFlag_r;
rfshCntr_next <= rfshCntr_r;
-- update timers
if timer_r /= TO_UNSIGNED(0,timer_r'length) then
timer_next <= timer_r - 1;
else
timer_next <= timer_r;
end if;
if rasTimer_r /= TO_UNSIGNED(0,rasTimer_r'length) then
rasTimer_next <= rasTimer_r - 1;
else
rasTimer_next <= rasTimer_r;
end if;
if wrTimer_r /= TO_UNSIGNED(0,wrTimer_r'length) then
wrTimer_next <= wrTimer_r - 1;
else
wrTimer_next <= wrTimer_r;
end if;
if refTimer_r /= TO_UNSIGNED(0,refTimer_r'length) then
refTimer_next <= refTimer_r - 1;
else
-- on timeout, reload the timer with the interval between row refreshes
-- and set the flag that indicates a refresh operation is needed.
refTimer_next <= TO_UNSIGNED(REF_CYCLES,refTimer_next'length);
doRfshFlag_next <= YES;
end if;
-- determine if another row or bank in the SDRAM is being addressed
if row /= activeRow_r or bank /= activeBank_r or inactiveFlag_r = YES then
changeRow <= YES;
else
changeRow <= NO;
end if;
-- ***** compute next state and outputs *****
-- SDRAM initialization
if state_r = INITWAIT then
-- initiate wait for SDRAM power-on initialization
-- timer_next <= TO_UNSIGNED(INIT_CYCLES,timer_next'length); -- set timer for init interval
cs_n <= HI;
dqml <= HI;
dqmh <= HI;
initFlag_next <= YES; -- indicate initialization is in progress
if timer_r = TO_UNSIGNED(0,timer_r'length) then
state_next <= INITPCHG; -- precharge SDRAM after power-on initialization
end if;
sdramCntl_state <= "0001";
-- don't do anything if the previous operation has not completed yet.
-- Place this before anything else so operations in the previous state
-- complete before any operations in the new state are executed.
elsif timer_r /= TO_UNSIGNED(0,timer_r'length) then
sdramCntl_state <= "0000";
elsif state_r = INITPCHG then
cmd <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks
timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation
-- now setup the counter for the number of refresh ops needed during initialization
rfshCntr_next <= TO_UNSIGNED(RfshCycles,rfshCntr_next'length);
state_next <= INITRFSH; -- perform refresh ops after setting the mode
sdramCntl_state <= "0010";
elsif state_r = INITRFSH then
-- refresh the SDRAM a number of times during initialization
if rfshCntr_r /= TO_UNSIGNED(0,rfshCntr_r'length) then
-- do a refresh operation if the counter is not zero yet
cmd <= RFSH_CMD; -- refresh command goes to SDRAM
timer_next <= TO_UNSIGNED(RFC_CYCLES,timer_next'length); -- refresh operation interval
rfshCntr_next <= rfshCntr_r - 1; -- decrement refresh operation counter
state_next <= INITRFSH; -- return to this state while counter is non-zero
else
-- refresh op counter reaches zero, so set the operating mode of the SDRAM
state_next <= INITSETMODE;
end if;
sdramCntl_state <= "0100";
elsif state_r = INITSETMODE then
-- set the mode register in the SDRAM
cmd <= MODE_CMD; -- initiate loading of mode register in the SDRAM
sAddr <= MODE; -- output mode register bits onto the SDRAM address bits
timer_next <= TO_UNSIGNED(Cmrd,timer_next'length); -- set timer for this operation
state_next <= RW; -- process read/write operations after initialization is done
initFlag_next <= NO; -- reset flag since initialization is done
sdramCntl_state <= "0011";
-- refresh a row of the SDRAM when the refresh timer hits zero and sets the flag
-- and the SDRAM is no longer being initialized or read/written.
-- Place this before the RW state so the host can't block refreshes by doing
-- continuous read/write operations.
elsif doRfshFlag_r = YES and initFlag_r = NO and wrFlag_r = NO and rdFlag_r = NO then
if rasTimer_r = TO_UNSIGNED(0,rasTimer_r'length) and wrTimer_r = TO_UNSIGNED(0,wrTimer_r'length) then
doRfshFlag_next <= NO; -- reset the flag that initiates a refresh operation
cmd <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks
timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation
inactiveFlag_next <= YES; -- all rows are inactive after a precharge operation
state_next <= REFRESH; -- refresh the SDRAM after the precharge
end if;
sdramCntl_state <= "0101";
elsif state_r = REFRESH then
cmd <= RFSH_CMD; -- refresh command goes to SDRAM
timer_next <= TO_UNSIGNED(RFC_CYCLES,timer_next'length); -- refresh operation interval
-- after refresh is done, resume writing or reading the SDRAM if in progress
state_next <= RW;
sdramCntl_state <= "0110";
-- do nothing but wait for read or write operations
elsif state_r = RW then
if rd = YES then
-- the host has initiated a read operation
rdFlag_next <= YES; -- set flag to indicate a read operation is in progress
-- if a different row or bank is being read, then precharge the SDRAM and activate the new row
if changeRow = YES then
-- wait for any row activations or writes to finish before doing a precharge
if rasTimer_r = TO_UNSIGNED(0,rasTimer_r'length) and wrTimer_r = TO_UNSIGNED(0,wrTimer_r'length) then
cmd <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks
timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation
inactiveFlag_next <= YES; -- all rows are inactive after a precharge operation
state_next <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- read from the currently active row
else
cmd <= READ_CMD; -- initiate a read of the SDRAM
timer_next <= TO_UNSIGNED(Ccas,timer_next'length); -- setup timer for read access
state_next <= RDDONE; -- read the data from SDRAM after the access time
end if;
sdramCntl_state <= "0111";
elsif wr = YES then
-- the host has initiated a write operation
-- if a different row or bank is being written, then precharge the SDRAM and activate the new row
if changeRow = YES then
wrFlag_next <= YES; -- set flag to indicate a write operation is in progress
-- wait for any row activations or writes to finish before doing a precharge
if rasTimer_r = TO_UNSIGNED(0,rasTimer_r'length) and wrTimer_r = TO_UNSIGNED(0,wrTimer_r'length) then
cmd <= PCHG_CMD; -- initiate precharge of the SDRAM
sAddr(ColCmdPos) <= ALL_BANKS; -- precharge all banks
timer_next <= TO_UNSIGNED(RP_CYCLES,timer_next'length); -- set timer for this operation
inactiveFlag_next <= YES; -- all rows are inactive after a precharge operation
state_next <= ACTIVATE; -- activate the new row after the precharge is done
end if;
-- write to the currently active row
else
cmd <= WRITE_CMD; -- initiate the write operation
dirOut <= YES;
-- set timer so precharge doesn't occur too soon after write operation
wrTimer_next <= TO_UNSIGNED(WR_CYCLES,wrTimer_next'length);
state_next <= WRDONE; -- go back and wait for another read/write operation
end if;
sdramCntl_state <= "1000";
else
null; -- no read or write operation, so do nothing
sdramCntl_state <= "1001";
end if;
-- enter this state when the data read from the SDRAM is available
elsif state_r = RDDONE then
rdFlag_next <= NO; -- set flag to indicate the read operation is over
done <= YES; -- tell the host that the data is ready
state_next <= RW; -- go back and do another read/write operation
sdramCntl_state <= "1010";
-- enter this state when the data is written to the SDRAM
elsif state_r = WRDONE then
dirOut <= YES;
wrFlag_next <= NO; -- set flag to indicate the write operation is over
done <= YES; -- tell the host that the data is ready
state_next <= RW; -- go back and do another read/write operation
sdramCntl_state <= "1011";
-- activate a row of the SDRAM
elsif state_r = ACTIVATE then
cmd <= ACTIVE_CMD; -- initiate the SDRAM activation operation
sAddr <= (others=>'0'); -- output the address for the row that will be activated
sAddr(row'range) <= row;
activeBank_next <= bank; -- remember the active SDRAM row
activeRow_next <= row; -- remember the active SDRAM bank
inactiveFlag_next <= NO; -- the SDRAM is no longer inactive
rasTimer_next <= TO_UNSIGNED(RCD_CYCLES,rasTimer_next'length);
timer_next <= TO_UNSIGNED(RCD_CYCLES,timer_next'length);
state_next <= RW; -- go back and do the read/write operation that caused this activation
sdramCntl_state <= "1100";
-- no operation
else
null;
sdramCntl_state <= "1101";
end if;
end process combinatorial;
-- update registers on the rising clock edge
update: process(clk)
begin
if clk'event and clk='1' then
if rst = NO then
state_r <= INITWAIT;
activeBank_r <= (others=>'0');
activeRow_r <= (others=>'0');
inactiveFlag_r <= YES;
initFlag_r <= YES;
doRfshFlag_r <= NO;
rdFlag_r <= NO;
wrFlag_r <= NO;
rfshCntr_r <= TO_UNSIGNED(0,rfshCntr_r'length);
timer_r <= TO_UNSIGNED(INIT_CYCLES,timer_r'length);
refTimer_r <= TO_UNSIGNED(REF_CYCLES,refTimer_r'length);
rasTimer_r <= TO_UNSIGNED(0,rasTimer_r'length);
wrTimer_r <= TO_UNSIGNED(0,wrTimer_r'length);
else
state_r <= state_next;
activeBank_r <= activeBank_next;
activeRow_r <= activeRow_next;
inactiveFlag_r <= inactiveFlag_next;
initFlag_r <= initFlag_next;
doRfshFlag_r <= doRfshFlag_next;
rdFlag_r <= rdFlag_next;
wrFlag_r <= wrFlag_next;
rfshCntr_r <= rfshCntr_next;
timer_r <= timer_next;
refTimer_r <= refTimer_next;
rasTimer_r <= rasTimer_next;
wrTimer_r <= wrTimer_next;
end if;
end if;
end process update;
end arch;
|
gpl-3.0
|
50dc8c7ea64b2f30905c3ad21b6c61c3
| 0.677677 | 3.330752 | false | false | false | false |
lvoudour/arty-uart
|
src/fifo_srl.vhd
| 1 | 4,597 |
--------------------------------------------------------------------------------
--
-- Shift register (SRL) based synchronous FIFO
--
-- Signals:
-- clk : clock
-- rst : synchronous reset (active high)
-- din : data input
-- wr_en : write enable
-- full : FIFO full flag
-- dout : data output
-- rd_en : read enable
-- empty : FIFO empty flag
--
-- Parameters:
-- G_DATA_WIDTH : Bit width of the data input/output
-- G_DEPTH : FIFO depth
--
-- This design takes advantage of the SRL blocks in Xilinx FPGAs. Optimal
-- G_DEPTH is 16 (SRL16) or 32 (SRL32).
--
-- Read/Write:
-- dout is valid 1 clk cycle after rd_en goes high. din is written into the
-- FIFO 1 clk cycle after wr_en goes high.
-- Simultaneous rd/wr operations do not change the state of the FIFO (ie. FIFO
-- will not go empty or full)
--
-- Empty/Full flags
-- At reset empty flag is set high and full low. Empty flag goes low 1 clk cycle
-- after the first wr_en and high after the last valid rd_en. Full goes high 1
-- clk cycle after the last valid wr_en and low after the first rd_en.
-- Any subsequent rd_en/wr_en when empty/full respecively is ignored and FIFO
-- state doesn't change (ie. it stays empty or full)
--
-- Arty FPGA board specific notes:
-- Vivado infers SRL blocks (SRL16 when using the default G_DEPTH=16). Should
-- work for other Xilinx FPGAs as well. Should be slightly faster than an
-- equivalent distributed RAM impelementation for depths up to 32 words. Same
-- type of FIFO can be generated using the Xilinx FIFO generator (if you don't
-- mind the device specific netlist).
--
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity fifo_srl is
generic(
G_DATA_WIDTH : positive := 8;
G_DEPTH : positive := 16
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
wr_en : in std_logic;
full : out std_logic;
dout : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
rd_en : in std_logic;
empty : out std_logic
);
end entity fifo_srl;
architecture rtl of fifo_srl is
constant C_ADDR_WIDTH : natural := natural(ceil(log2(real(G_DEPTH))));
type srl16_array is array (G_DEPTH-1 downto 0) of std_logic_vector (G_DATA_WIDTH-1 downto 0);
signal fifo : srl16_array := (others=>(others=>'0'));
signal ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal inc_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal dec_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal empty_r : std_logic := '1';
signal full_r : std_logic := '0';
signal wr_rd : std_logic_vector(1 downto 0) := "00";
begin
wr_rd <= wr_en & rd_en;
inc_ptr <= ptr + 1;
dec_ptr <= ptr - 1;
proc_data:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
ptr <= (others=>'0');
full_r <= '0';
empty_r <= '1';
else
case wr_rd is
-- Read operation
-- Read the data and decrement the pointer if not empty.
-- FIFO is empty if the next pointer decrement reaches zero.
when "01" =>
if (empty_r = '0') then
dout <= fifo(to_integer(dec_ptr));
ptr <= dec_ptr;
end if;
full_r <= '0';
if (dec_ptr = 0) then
empty_r <= '1';
end if;
-- Write operation
-- Write the data and increment the pointer if not full.
-- FIFO is full if the next pointer increment reaches zero.
when "10" =>
if (full_r = '0') then
fifo <= fifo(G_DEPTH-2 downto 0) & din;
ptr <= inc_ptr;
end if;
empty_r <= '0';
if (inc_ptr = 0) then
full_r <= '1';
end if;
-- Simultaneous read/write
-- Read and write data without moving the pointer
when "11" =>
fifo <= fifo(G_DEPTH-2 downto 0) & din;
dout <= fifo(to_integer(dec_ptr));
-- No operation
when others =>
null;
end case;
end if;
end if;
end process;
full <= full_r;
empty <= empty_r;
end architecture rtl;
|
mit
|
a8d238c8d9cfb919ae8e9895cf2a7725
| 0.556885 | 3.594214 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/GC_fifo/example_design/GC_fifo_top_wrapper.vhd
| 1 | 19,092 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: GC_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity GC_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end GC_fifo_top_wrapper;
architecture xilinx of GC_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component GC_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : GC_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
aa6deab26fd485ea0d1de6b76622a70c
| 0.485125 | 3.970882 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_FIFO/example_design/WR_FLASH_FIFO_top.vhd
| 1 | 5,230 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: WR_FLASH_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity WR_FLASH_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end WR_FLASH_FIFO_top;
architecture xilinx of WR_FLASH_FIFO_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component WR_FLASH_FIFO is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : WR_FLASH_FIFO PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
a29b225fafd9325b1a2aa510ef3b5cdc
| 0.513384 | 4.754545 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_PRE_FIFO/simulation/fg_tb_synth.vhd
| 1 | 11,217 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 7,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : RD_FLASH_PRE_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
6f64d2d0ea69cf1a2c9377e471804c38
| 0.454845 | 3.965005 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/inst_cache_dpram_r2_sim.vhd
| 4 | 9,310 |
-------------------------------------------------------------------------------
--
-- Design : inst_cache_dpram (Dual Port RAM holding cache data)
-- In summer 2008, it was inst_cache_sprom (Single Port ROM holding the cache data)
-- Project : ee560 Tomosulo -- Instruction Cache Emulator
-- Author : Srinivas Vaduvatha , Gandhi Puvvada
-- Company : University of Southern California
-- Date last revised : 7/23/2008, 7/15/2009
-------------------------------------------------------------------------------
--
-- File : inst_cache_dpram_r2.vhd (produced by modifying Summer 2008 inst_cache_sprom_r1.vhd and data_mem_dp.vhd)
--
-------------------------------------------------------------------------------
--
-- Description : This BRAM is instantiated by the instr_cache module.
-- This holds the instructions.
-- In Summer 2008, it was a ROM (BRAM acting like a ROM) with inital
-- content (instruction stream) defined through a package called
-- instr_stream_pkg.
-- In Summer 2009, it is converted to a dual port RAM. The first port (Port a) is of read/write type
-- and it faciliatates downloading a file containing cache contents from a text file holding instructions
-- in hex notation, 4 instruction per line, with Instruction0 on the right-end of the line:
-- Instruction3_ Instruction2_Instruction1_Instruction0
-- Module features:
-- Data width & Address width - Generics
-- Port b: synchronous Read only (for the processor cache read operation)
-- Port a: synchronous Read/Write (for File I/O through Adept 2.0)
-- Infers BRAM resource in Xilinx FPGAs.
-- If the width / depth specified require more bits than in a single
-- BRAM, multiple BRAMs are automatically cascaded to form a larger
-- memory by the Xilinx XST. Memory has to be of (2**n) depth.
--
-------------------------------------------------------------------------------
-- libraries and use clauses
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
--synopsys translate_off
use work.instr_stream_pkg.all; -- instruction stream defining package
--synopsys translate_on
entity inst_cache_dpram is
generic (
DATA_WIDTH : integer := 128; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
clka : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
wea : in std_logic;
data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
ena : in std_logic;
clkb : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- data_in_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- web : in std_logic;
data_out_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end inst_cache_dpram ;
architecture inferable of inst_cache_dpram is
-- signals declarations.
-- Note: A signal called "mem" of user defined type "mem_type" was declared
-- in a package called "instr_stream_pkg" refered in the use clause above.
-- It has lines similar to the following lines.
-- The initial content defines the stream of instructions.
-- -- type declarations
--type mem_type is array (0 to (2**ADDR_WIDTH)-1) of std_logic_vector((DATA_WIDTH-1) downto 0);
--*****************************************************************************************
-- This stream is used to generate the walking led pattern using memory mapped i/0
--*****************************************************************************************
--signal mem : mem_type
-- := (
-- X"AC180004_000CC01B_004C681B_0050601B", -- Loc 0C, 08, 04, 00
-- X"00000020_AC130004_AC120004_8DA90000", -- Loc 1C, 18, 14, 10 -- corrected
-- X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
-- X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
-- X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
-- X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
-- X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
-- X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
-- X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
-- X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
-- X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
-- X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
-- X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
-- X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
-- X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
-- X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
-- X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
-- X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
-- X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
-- X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
-- X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
-- X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
-- X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
-- X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
-- X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
-- X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
-- X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
-- X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
-- X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
-- X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
-- X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
-- X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
-- X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
-- X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
-- X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
-- X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
-- X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
-- X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
-- X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
-- X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
-- X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
-- X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
-- X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
-- X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
-- X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
-- X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
-- X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
-- X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
-- X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
-- X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
-- X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
-- X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
-- X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
-- X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
-- X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
-- X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
-- X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
-- X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
-- X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
-- X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- -- the last 16 instructions are looping jump instructions
-- X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
-- X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
-- X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
-- X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
-- ) ;
begin
porta_oper : process (clka)
begin
if (clka = '1' and clka'event) then
if (wea = '1' and ena='1') then
mem(CONV_INTEGER(unsigned(addr_a))) <= data_in_a;
end if;
if( ena='1')then
data_out_a <= mem(CONV_INTEGER(unsigned(addr_a)));
end if;
end if;
end process;
portb_oper : process (clkb)
begin
if (clkb = '1' and clkb'event) then
-- if (web = '1') then
-- mem(CONV_INTEGER(addr_b)) := data_in_b;
-- end if;
data_out_b <= mem(CONV_INTEGER(unsigned(addr_b)));
end if;
end process;
end inferable ;
--- ===========================================================
|
gpl-2.0
|
2730b2313fd6709a41b7b6754d09f54e
| 0.604726 | 3.182906 | false | false | false | false |
tuura/fantasi
|
dependencies/sync-latch.vhdl
| 1 | 1,036 |
-- This module make the input visible to the output just for one clock cycle
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic);
END SYNC_LATCH;
ARCHITECTURE structural_description OF SYNC_LATCH IS
COMPONENT ffd IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
SIGNAL d_sync : std_logic;
SIGNAL sync : std_logic;
BEGIN
FFD_OUT : ffd PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
D => d_sync,
Q => DOUT);
FFD_SYNC : ffd PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
D => DIN,
Q => sync);
d_sync <= DIN AND NOT(sync);
END structural_description;
|
mit
|
a2c715ef0de0a9fc99dd339697ff096a
| 0.491313 | 3.419142 | false | false | false | false |
abcsds/RS232
|
RS232Read_DEPRECATED/FsmRead.vhd
| 2 | 3,599 |
library IEEE;
use IEEE.std_logic_1164.all;
entity FsmRead is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOR : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end FsmRead;
architecture simple of FsmRead is
signal Qp, Qn : std_logic_vector(3 downto 0);
begin
combinacional: process(Qp,STR,FBaud)
begin
case Qp is
when "0000" => -- State 0
if (STR='1') then
Qn <= Qp;
else
Qn <= "0001";
end if;
CTRL <= "01";
EOR <= "1";
when "0001" => -- State 1
Qn <= "0010"
CTRL <= "10";
EOR <= "0";
when "0010" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0011"
end if;
CTRL <= "00";
EOR <= "0";
when "0011" => -- State 2
Qn <= "0100"
CTRL <= "10";
EOR <= "0";
when "0100" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0101"
end if;
CTRL <= "00";
EOR <= "0";
when "0101" => -- State 3
Qn <= "0110"
CTRL <= "10";
EOR <= "0";
when "0110" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "0111"
end if;
CTRL <= "00";
EOR <= "0";
when "0111" => -- State 4
Qn <= "1000"
CTRL <= "10";
EOR <= "0";
when "1000" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1001"
end if;
CTRL <= "00";
EOR <= "0";
when "1001" => -- State 5
Qn <= "1010"
CTRL <= "10";
EOR <= "0";
when "1010" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1011"
end if;
CTRL <= "00";
EOR <= "0";
when "1011" => -- State 6
Qn <= "1100"
CTRL <= "10";
EOR <= "0";
when "1100" => -- HOLD State 1
if (FBaud = '0') then
Qn <= Qp;
else
Qn <= "1101"
end if;
CTRL <= "00";
EOR <= "0";
when "1101" => -- State 7
Qn <= "1110"
CTRL <= "10";
EOR <= "0";
when others =>
CTRL<= "0000";
EOR<= '1';
Qn<= "0000";
end case;
end process combinacional;
secuencial: process(RST,CLK)
begin
if(RST='0')then
Qp<= "0000";
elsif(CLK'event and CLK='1')then
Qp<= Qn;
end if;
end process secuencial;
end simple;
|
gpl-3.0
|
58552bb3f71b823da4d9cb2a36049d75
| 0.29147 | 4.661917 | false | false | false | false |
tuura/fantasi
|
dependencies/ffd-inv.vhdl
| 1 | 573 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
LIBRARY work;
entity ffd_en is
port (
CLK : in std_logic;
RST : in std_logic;
EN : in std_logic;
D : in std_logic;
Q : out std_logic
);
end entity ffd_en;
architecture Behavioral of ffd_en is
signal q_tmp : std_logic;
begin
process (CLK) is
begin
if rising_edge(CLK) then
if (RST='1') then
q_tmp <= '1';
elsif (EN='1') then
q_tmp <= D;
end if;
end if;
end process;
Q <= q_tmp;
end architecture Behavioral;
|
mit
|
b512911861396e098896f8f7b32fb2cf
| 0.537522 | 3.080645 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/tx_buf/simulation/fg_tb_synth.vhd
| 1 | 10,789 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 6,
C_RD_PNTR_WIDTH => 6,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : tx_buf_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
2f39def22c2f011264650cba78bdc214
| 0.458615 | 4.124235 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Command_FIFO/example_design/Command_FIFO_top_wrapper.vhd
| 1 | 19,111 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Command_FIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Command_FIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(11-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(11-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(11-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end Command_FIFO_top_wrapper;
architecture xilinx of Command_FIFO_top_wrapper is
SIGNAL clk_i : std_logic;
component Command_FIFO_top is
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : Command_FIFO_top
PORT MAP (
CLK => clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
918d35cba0c762b16c08e1cce17258df
| 0.48548 | 3.986441 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/dsor_vga.vhd
| 1 | 2,838 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: dsor_vga.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity dsor_vga is
Port ( clk_50MHz : in STD_LOGIC;
rst : in STD_LOGIC;
pulso_25MHz : out STD_LOGIC);
end dsor_vga;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture arq of dsor_vga is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal ff_aux: std_logic;
--signal ff_pulso: std_logic;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
--pulso_25MHz <= '1' when clk_50MHz = '1' and ff_aux = '1' else
--'0';
pulso_25MHz <= ff_aux;
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_aux: process(rst, clk_50MHz)
begin
if rst = '1' then
ff_aux <= '0';
elsif rising_edge(clk_50MHz) then
ff_aux <= not ff_aux;
end if;
end process p_aux;
end arq;
|
gpl-3.0
|
317cfce914ab57ea5980bdf9c469c101
| 0.406911 | 5.213235 | false | false | false | false |
tuura/fantasi
|
dependencies/sync-register.vhdl
| 1 | 1,027 |
-- Generic size register made with sync latches
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_sync_register IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N-1 downto 0));
END Generic_sync_register;
ARCHITECTURE structural OF Generic_sync_register IS
COMPONENT SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic);
END COMPONENT;
BEGIN
SYNC_REG_GENERATOR : for i in 0 to N-1 generate
SYNC_LATCH_I : SYNC_LATCH PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
DIN => DIN(i),
DOUT => DOUT(i));
end Generate;
END structural;
|
mit
|
923744cae67a0263add809acc5bca16a
| 0.527751 | 3.481356 | false | false | false | false |
csrhau/sandpit
|
VHDL/vga_imdisplay/test_vga_sequencer.vhdl
| 2 | 2,549 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
use std.textio.all;
entity test_vga_sequencer is
end test_vga_sequencer;
architecture behavioural of test_vga_sequencer is
component vga_sequencer is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
output_enable : out std_logic;
read_address : out natural range vga_memory'range;
hsync : out std_logic;
vsync : out std_logic
);
end component vga_sequencer;
constant min_addr : std_logic_vector(18 downto 0) := (others => '0');
signal clock, output_enable, hsync, vsync : std_logic;
signal read_address: natural range vga_memory'range;
begin
SEQUENCER: vga_sequencer generic map (
display_rows => 4,
display_cols => 4
)
port map (
clock,
output_enable,
read_address,
hsync,
vsync
);
process
variable read_step : natural range vga_memory'range := 0;
variable oline: line;
begin
clock <= '0';
wait for 1 ns;
clock <= '1'; -- Delay1 -> Delay2
wait for 1 ns;
assert output_enable = '0'
report "Delay state should not request a read" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- Delay2 -> Read
wait for 1 ns;
assert output_enable = '0'
report "Delay state should not request a read" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- Read -> Update
wait for 1 ns;
assert output_enable = '1'
report "Read state should requeste a read" severity error;
assert read_address = read_step
report "Read should have specified an address" severity error;
read_step := 1;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- Update -> Delay1
wait for 1 ns;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- Delay1 -> Delay2
wait for 1 ns;
assert output_enable = '1'
report "Read request should remain active" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- Delay2 -> Read
wait for 1 ns;
assert output_enable = '1'
report "Read enable should remain activ" severity error;
wait;
end process;
end behavioural;
|
mit
|
31670cb8a24ba6738e90a5438f3fe68b
| 0.552766 | 4.091493 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/tb_top.vhd
| 1 | 5,006 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:58:46 04/02/2017
-- Design Name:
-- Module Name: D:/VHDL/UART_TEST/tb_top.vhd
-- Project Name: UART_TEST
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_top IS
END tb_top;
ARCHITECTURE behavior OF tb_top IS
constant max_counter: natural := (11538500 / 9600) - 1;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
clk_50mhz : IN std_logic;
rs232_dce_txd : OUT std_logic;
rs232_dce_rxd : IN std_logic;
led : OUT std_logic_vector(7 downto 0);
buttons : IN std_logic_vector(7 downto 0);
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic
);
END COMPONENT;
--Inputs
signal clk_50mhz : std_logic := '0';
signal rs232_dce_rxd : std_logic := '0';
signal buttons : std_logic_vector(7 downto 0) := (others => '0');
signal rot_center : std_logic := '0';
signal rot_a : std_logic := '0';
signal rot_b : std_logic := '1';
--Outputs
signal rs232_dce_txd : std_logic;
signal led : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_50mhz_period : time := 20 ns;
type state_type is (
s_start,
s_data,
s_stop
);
signal state: state_type := s_start;
type bufer_type is array (0 to 2**15) of std_logic_vector(7 downto 0);
signal buff: bufer_type := (
-- (X"AA"),
-- (X"55"),
-- (X"00"),
-- (X"08"),
-- (X"01"),
-- (X"81"),
-- (X"81"),
-- (X"0F"),
-- (X"F0"),
-- (X"3C"),
-- (X"C3"),
-- (X"7E"),
-- (X"E7"),
-- (X"01"),
-- (X"02"),
-- (X"03"),
(X"AA"),
(X"55"),
(X"00"),
(X"05"),
(X"01"),
(X"01"),
(X"02"),
(X"03"),
(X"04"),
(X"05"),
(X"AA"),
(X"55"),
(X"00"),
(X"01"),
(X"06"),
(X"58"),
(X"AA"),
(X"55"),
(X"00"),
(X"02"),
(X"06"),
(X"F0"),
(X"58"),
(X"AA"),
(X"55"),
(X"00"),
(X"01"),
(X"06"),
(X"FA"),
others => (others => '0')
);
signal buff_out: bufer_type := (others => (others => '0'));
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
clk_50mhz => clk_50mhz,
rs232_dce_txd => rs232_dce_txd,
rs232_dce_rxd => rs232_dce_rxd,
led => led,
buttons => buttons,
rot_a => rot_a,
rot_b => rot_b,
rot_center => rot_center
);
-- Clock process definitions
clk_50mhz_process :process
begin
clk_50mhz <= '0';
wait for clk_50mhz_period/2;
clk_50mhz <= '1';
wait for clk_50mhz_period/2;
end process;
-- Stimulus process
stim_proc: process(clk_50mhz)
variable bit_i: integer := 0;
variable i: integer := 0;
variable bit_counter: integer := max_counter;
begin
if rising_edge(clk_50mhz) then
if i < 29 then
case state is
when s_start =>
rs232_dce_rxd <= '0';
state <= s_data;
bit_counter := max_counter-1 + ((max_counter-1) / 2) - 1;
report "bitcounter = "&integer'image(bit_counter);
when s_data =>
if bit_counter = 0 then
bit_counter := max_counter - 2;
if bit_i = 8 then
report "next byte " severity note;
bit_i := 0;
i := i + 1;
state <= s_stop;
rs232_dce_rxd <= '1';
else
rs232_dce_rxd <= buff(i)(bit_i);
bit_i := bit_i + 1;
end if;
else
bit_counter := bit_counter - 1;
end if;
when s_stop =>
if bit_counter = 0 then
state <= s_start;
else
bit_counter := bit_counter - 1;
end if;
end case;
else
rot_center <= '0';
end if;
end if;
end process;
--buttons <= X"F0";
END;
|
mit
|
b720184e972131d4ba55ed1b8b6bf5ba
| 0.479425 | 3.412406 | false | false | false | false |
BBN-Q/APS2-TDM
|
src/InternalTrig.vhd
| 1 | 1,860 |
----
-- Original authors: Blake Johnson and Colm Ryan
-- Copyright 2015, Raytheon BBN Technologies
--
-- InternalTrig module
--
-- Produce trigger signal on a counter or from a command.
----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity InternalTrig is
port (
--Resets
RESET : in std_logic;
--Clocks
CLK : in std_logic;
--trigger params
triggerInterval : in std_logic_vector(31 downto 0);
triggerSource : in std_logic;
softTrigToggle : in std_logic;
--ouput
trigger : out std_logic
);
end entity ; -- InternalTrig
architecture arch of InternalTrig is
signal loadInternalTrigger : std_logic := '0';
signal internalTrig, softwareTrig: std_logic := '0';
signal softTrigToggle_d : std_logic := '0';
begin
-- INTERNAL TRIGGER --
--Downcounter for internal trigger
triggerCounter : process( CLK )
variable c : unsigned(32 downto 0); -- one extra bit to catch underflow
begin
if rising_edge(CLK) then
internalTrig <= '0';
if RESET = '1' then
c := resize(unsigned(triggerInterval), c'length) - 2;
else
if c(c'high) = '1' then
internalTrig <= '1';
c := resize(unsigned(triggerInterval), c'length) - 2;
else
c := c - 1;
end if;
end if ;
end if ;
end process ; -- triggerCounter
-- SOFTWARE TRIGGER --
--The user toggles the trigger line so simple edge detection
catchSoftwareTrigger : process( CLK )
begin
if rising_edge(CLK) then
softTrigToggle_d <= softTrigToggle;
if ((softTrigToggle xor softTrigToggle_d) = '1') then
softwareTrig <= '1';
else
softwareTrig <= '0';
end if;
end if ;
end process ; -- catchSoftwareTrigger
-- Mux INTERNAL / EXTERNAL / SOFTWARE triggers --
with triggerSource select trigger <=
internalTrig when '0',
softwareTrig when '1',
'0' when others;
end architecture ; -- arch
|
mpl-2.0
|
ea8580f0792d4a6274f16332ea5bc89a
| 0.688172 | 3.292035 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/DMA_READ_QUEUE/simulation/fg_tb_pkg.vhd
| 1 | 11,250 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT DMA_READ_QUEUE_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
2319210f4f66f6eac75a227a3744f4e8
| 0.504533 | 3.930818 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_1/spy_tb/top_tb_withSBufComp_r1.vhd
| 1 | 10,732 |
-------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Store Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- synopsys translate_off
--use work.reverseAssemblyFunctionPkg.all;
-- synopsys translate_on
-----------------------------------------------------------------------------
--added by Sabya to use compiled library
library ee560;
use ee560.all;
------------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_Store_Buf of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden BPB)
signal SB_Full_gold : std_logic;
signal SB_Stall_gold : std_logic;
signal SB_FlushSw_gold : std_logic;
signal SB_FlushSwTag_gold : std_logic_vector(1 downto 0);
signal SBTag_counter_gold : std_logic_vector(1 downto 0);
signal SB_DataDmem_gold : std_logic_vector (31 downto 0);
signal SB_AddrDmem_gold : std_logic_vector (31 downto 0);
signal SB_DataValid_gold : std_logic;
-- Signals for the student's DUT (BPB)
signal Resetb : std_logic ;
signal Rob_SwAddr : std_logic_vector (31 downto 0);
signal PhyReg_StoreData : std_logic_vector (31 downto 0);
signal Rob_CommitMemWrite : std_logic;
signal SB_Full : std_logic;
signal SB_Stall : std_logic;
signal Rob_TopPtr : std_logic_vector(4 downto 0);
signal SB_FlushSw : std_logic;
signal SB_FlushSwTag : std_logic_vector(1 downto 0);
signal SBTag_counter : std_logic_vector(1 downto 0);
signal SB_DataDmem : std_logic_vector (31 downto 0);
signal SB_AddrDmem : std_logic_vector (31 downto 0);
signal SB_DataValid : std_logic;
signal DCE_WriteBusy : std_logic;
signal DCE_WriteDone : std_logic;
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
Clk : in std_logic;
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component store_buffer
port (
Clk : in std_logic ;
Resetb : in std_logic ;
Rob_SwAddr : in std_logic_vector (31 downto 0);
PhyReg_StoreData : in std_logic_vector (31 downto 0);
Rob_CommitMemWrite : in std_logic;
SB_Full : out std_logic;
SB_Stall : out std_logic;
Rob_TopPtr : in std_logic_vector(4 downto 0);
SB_FlushSw : out std_logic;
SB_FlushSwTag : out std_logic_vector(1 downto 0);
SBTag_counter : out std_logic_vector(1 downto 0);
SB_DataDmem : out std_logic_vector (31 downto 0);
SB_AddrDmem : out std_logic_vector (31 downto 0);
SB_DataValid : out std_logic;
DCE_WriteBusy : in std_logic;
DCE_WriteDone : in std_logic
);
end component store_buffer;
for Store_Buffer_UUT: store_buffer use entity work.store_buffer(struct);
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
Store_Buffer_UUT: store_buffer
port map (
Clk => Clk,
Resetb => Resetb ,
Rob_SwAddr => Rob_SwAddr,
PhyReg_StoreData => PhyReg_StoreData,
Rob_CommitMemWrite => Rob_CommitMemWrite,
SB_Full => SB_Full,
SB_Stall => SB_Stall,
Rob_TopPtr => Rob_TopPtr,
SB_FlushSw => SB_FlushSw,
SB_FlushSwTag => SB_FlushSwTag,
SBTag_counter => SBTag_counter,
SB_DataDmem => SB_DataDmem,
SB_AddrDmem => SB_AddrDmem,
SB_DataValid => SB_DataValid,
DCE_WriteBusy => DCE_WriteBusy,
DCE_WriteDone => DCE_WriteDone
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of Store Buffer only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (SB_Full_gold /= SB_Full) then
write (my_outline, string'("ERROR! SB_Full of TEST does not match SB_Full_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (SB_Stall_gold /= SB_Stall) then
write (my_outline, string'("ERROR! SB_Stall of TEST does not match SB_Stall_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (SB_FlushSw_gold /= SB_FlushSw) then
write (my_outline, string'("ERROR! SB_FlushSw of TEST does not match SB_FlushSw_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (SB_FlushSwTag_gold /= SB_FlushSwTag) then
write (my_outline, string'("ERROR! SB_FlushSwTag of TEST does not match SB_FlushSwTag_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (SBTag_counter_gold /= SBTag_counter) then
write (my_outline, string'("ERROR! SBTag_counter of TEST does not match SBTag_counter_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (SB_DataDmem_gold /= SB_DataDmem) then
write (my_outline, string'("ERROR! SB_DataDmem of TEST does not match SB_DataDmem_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (SB_AddrDmem_gold /= SB_AddrDmem) then
write (my_outline, string'("ERROR! SB_AddrDmem of TEST does not match SB_AddrDmem_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (SB_DataValid_gold /=SB_DataValid) then
write (my_outline, string'("ERROR! SB_DataValid of TEST does not match SB_DataValid_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/Resetb","Resetb",0);
init_signal_spy("/UUT/Rob_SwAddr","Rob_SwAddr",1,1);
enable_signal_spy("/UUT/Rob_SwAddr","Rob_SwAddr",0);
init_signal_spy("/UUT/PhyReg_StoreData","PhyReg_StoreData",1,1);
enable_signal_spy("/UUT/PhyReg_StoreData","PhyReg_StoreData",0);
init_signal_spy("/UUT/Rob_CommitMemWrite","Rob_CommitMemWrite",1,1);
enable_signal_spy("/UUT/Rob_CommitMemWrite","Rob_CommitMemWrite",0);
init_signal_spy("/UUT/Rob_TopPtr","Rob_TopPtr",1,1);
enable_signal_spy("/UUT/Rob_TopPtr","Rob_TopPtr",0);
init_signal_spy("/UUT/DCE_WriteBusy","DCE_WriteBusy",1,1);
enable_signal_spy("/UUT/DCE_WriteBusy","DCE_WriteBusy",0);
init_signal_spy("/UUT/DCE_WriteDone","DCE_WriteDone",1,1);
enable_signal_spy("/UUT/DCE_WriteDone","DCE_WriteDone",0);
--outputs--
init_signal_spy("/UUT/SB_Full","SB_Full_gold",1,1);
enable_signal_spy("/UUT/SB_Full","SB_Full_gold",0);
init_signal_spy("/UUT/SB_Stall","SB_Stall_gold",1,1);
enable_signal_spy("/UUT/SB_Stall","SB_Stall_gold",0);
init_signal_spy("/UUT/SB_FlushSw","SB_FlushSw_gold",1,1);
enable_signal_spy("/UUT/SB_FlushSw","SB_FlushSw_gold",0);
init_signal_spy("/UUT/SB_FlushSwTag","SB_FlushSwTag_gold",1,1);
enable_signal_spy("/UUT/SB_FlushSwTag","SB_FlushSwTag_gold",0);
init_signal_spy("/UUT/SBTag_counter","SBTag_counter_gold",1,1);
enable_signal_spy("/UUT/SBTag_counter","SBTag_counter_gold",0);
init_signal_spy("/UUT/SB_DataDmem","SB_DataDmem_gold",1,1);
enable_signal_spy("/UUT/SB_DataDmem","SB_DataDmem_gold",0);
init_signal_spy("/UUT/SB_AddrDmem","SB_AddrDmem_gold",1,1);
enable_signal_spy("/UUT/SB_AddrDmem","SB_AddrDmem_gold",0);
init_signal_spy("/UUT/SB_DataValid","SB_DataValid_gold",1,1);
enable_signal_spy("/UUT/SB_DataValid","SB_DataValid_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_Store_Buf;
|
gpl-2.0
|
c612ca5f25ae30b274db69c2525c8156
| 0.627656 | 3.132516 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_command_send_fifo/simulation/fg_tb_synth.vhd
| 1 | 11,717 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(4-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_command_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
1088d9f5a613f13ca6a33dabc1f01e48
| 0.456772 | 3.965144 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
fifo.vhd
| 1 | 5,408 |
-- Greg Stitt
-- University of Florida
-- Description:
-- This file implements a fifo entity. The fifo has a configurable depth
-- and width, and can use bram, distributed ram, or LUTs/FFs to implement
-- the buffer. The fifo also has a configurable output delay of either 0 or 1
-- cycles.
--
-- This entity does not implement the behavior of the fifo and instead
-- instantiates fifo_core architectures depending on the configuration of
-- generics. The fifo and fifo_core could potentially be combined, but having
-- recursive instantiations causes problems with some simulators, which this
-- implementation tries to avoid.
-- Notes:
-- The fifo protects against invalid writes (i.e. when full) and invalid reads
-- (i.e. when empty)
--
-- (use_bram = true and same_cycle_output = true) is not supported by
-- all FPGAs.
--
-- When using BRAM, the FIFO depth is rounded up to the nearest power of two.
--
-- The actual choice of RAM depends on the specific synthesis tool and FPGA.
-- This entity does not guarantee the correct type.
-- Used entities:
-- fifo_core
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- width : the width of the FIFO in bits (required)
-- depth : the depth of the FIFO in words (required)
-- almost_full_count : the count at which almost_full is asserted (default = 0)
-- use_bram : uses bram when true, uses LUTs/FFs when false
-- (default = true)
-- use_distribted_ram : uses distributed ram when true. If use_bram is also
-- true, use_distributed_ram is ignore. If both are false,
-- use LUTS/FFs. (default = false)
-- same_cycle_output : when true, output appears in same cycle as read. when
-- false, output appears one cycle after read.
-- (default = false)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description: (all control inputs are active high)
-- clk : clock
-- rst : reset (asynchronous)
-- rd : read enable
-- wr : write enable
-- empty : asserted when the FIFO is empty
-- full : asserted when the FIFO is full
-- almost_full : asserted when count >= almost_full_count
-- input : Input to write into the FIFO
-- output : Output read from the FIFO
-------------------------------------------------------------------------------
entity fifo is
generic(width : positive;
depth : positive;
almost_full_count : natural := 0;
use_bram : boolean := true;
use_distributed_ram : boolean := false;
same_cycle_output : boolean := false);
port(clk : in std_logic;
rst : in std_logic;
rd : in std_logic;
wr : in std_logic;
empty : out std_logic;
full : out std_logic;
almost_full : out std_logic;
count : out std_logic_vector(bitsNeeded(depth)-1 downto 0);
input : in std_logic_vector(width-1 downto 0);
output : out std_logic_vector(width-1 downto 0));
end fifo;
architecture DEFAULT of fifo is
begin
-- if the user doesn't want any type of ram, use the flip-flop architecture
FF : if use_bram = false and use_distributed_ram = false generate
U_FIFO_FF : entity work.fifo_core(FF)
generic map (width => width,
depth => depth,
almost_full_count => almost_full_count,
use_bram => false,
same_cycle_output => same_cycle_output)
port map (clk => clk,
rst => rst,
rd => rd,
wr => wr,
empty => empty,
full => full,
almost_full => almost_full,
count => count,
input => input,
output => output);
end generate FF;
-- for any type of memory, use the MEMORY architecture where the use_bram
-- option will specify the type of memory
MEMORY : if use_bram = true or use_distributed_ram = true generate
U_FIFO_RAM : entity work.fifo_core(MEMORY)
generic map (width => width,
depth => depth,
almost_full_count => almost_full_count,
use_bram => use_bram,
same_cycle_output => same_cycle_output)
port map (clk => clk,
rst => rst,
rd => rd,
wr => wr,
empty => empty,
full => full,
almost_full => almost_full,
count => count,
input => input,
output => output);
end generate MEMORY;
end DEFAULT;
|
gpl-3.0
|
f086e6081ec6cf7dd5a79155c31bc895
| 0.499075 | 4.74386 | false | false | false | false |
chronos38/DSD-Projekt
|
dezctr/ioctrl/debounce/debounce_struc.vhd
| 1 | 885 |
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture behavioral of debounce is
signal s_keydeb : std_logic_vector(WIDTH-1 downto 0) := (others=>'0');
signal s_debcnt : integer range 0 to DELAY + 1 := 0;
begin
p_debounce: process
begin
wait until rising_edge(clk50);
if (keyin_i = s_keydeb) then
s_debcnt <= 0;
else
s_debcnt <= s_debcnt + 1;
end if;
if (s_debcnt = DELAY) then
s_keydeb <= keyin_i;
end if;
end process;
keyout_o <= s_keydeb;
end behavioral;
|
gpl-3.0
|
db0142c55f023c419c6516c455e2595e
| 0.487006 | 4.135514 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_PRE_FIFO/example_design/WR_FLASH_PRE_FIFO_top.vhd
| 1 | 5,250 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: WR_FLASH_PRE_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity WR_FLASH_PRE_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end WR_FLASH_PRE_FIFO_top;
architecture xilinx of WR_FLASH_PRE_FIFO_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component WR_FLASH_PRE_FIFO is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : WR_FLASH_PRE_FIFO PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
d3048eb5ba310d0ed79f1e312cac9d0b
| 0.512571 | 4.755435 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Command_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,304 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT Command_FIFO_top IS
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
ace44b9753eb4fcfc2c5c2e9c87dcfc4
| 0.503539 | 3.940049 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RESPONSE_QUEUE/simulation/fg_tb_top.vhd
| 2 | 5,679 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 37
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
c66e2be980811c61d5fb7b249886a299
| 0.616306 | 4.175735 | false | false | false | false |
csrhau/sandpit
|
VHDL/vga_imdisplay/vga_rom.vhdl
| 1 | 651 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity VGA_ROM is
generic (
contents : vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in natural range vga_memory'range;
data : out std_logic_vector(7 downto 0)
);
end entity VGA_ROM;
architecture behavioural of VGA_ROM is
constant storage : vga_memory := contents;
begin
process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
data <= storage(address);
else
data <= (others => '0');
end if;
end if;
end process;
end behavioural;
|
mit
|
345bf2211aafc0ad243664d362bf3256
| 0.635945 | 3.481283 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_2/Dispatch_Files/dispatch_xtend_BRAM.vhd
| 1 | 35,948 |
-------------------------------------------------------------------------------
--
-- Design : Dispatch Unit
-- Project : Tomasulo Processor
-- Entity : dispatch_unit
-- Author : Manpreet Billing
-- Company : University of Southern California
-- Last Updated : March 2, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity dispatch_unit is
port(
Clk : in std_logic ;
Resetb : in std_logic ;
-- Interface with Intsruction Fetch Queue
Ifetch_Instruction : in std_logic_vector(31 downto 0); -- instruction from IFQ
Ifetch_PcPlusFour : in std_logic_vector(31 downto 0); -- the PC+4 value carried forward for jumping and branching
Ifetch_EmptyFlag : in std_logic; -- signal showing that the ifq is empty,hence stopping any decoding and dispatch of the current if_inst
Dis_Ren : out std_logic; -- stalling caused due to issue queue being full
Dis_JmpBrAddr : out std_logic_vector(31 downto 0); -- the jump or branch address
Dis_JmpBr : out std_logic; -- validating that address to cause a jump or branch
Dis_JmpBrAddrValid : out std_logic; -- to tell if the jump or branch address is valid or not.. will be invalid for "jr $rs" inst
-------------------------------------------------------------------------
-- Interface with branch prediction buffer
Dis_CdbUpdBranch : out std_logic; -- indicates that a branch is processed by the cdb and gives the pred(wen to bpb)
Dis_CdbUpdBranchAddr : out std_logic_vector(2 downto 0);-- indiactes the least significant 3 bit PC[4:2] of the branch beign processed by cdb
Dis_CdbBranchOutcome : out std_logic; -- indiacates the outocome of the branch to the bpb
Bpb_BranchPrediction : in std_logic; -- this bit tells the dispatch what is the prediction based on bpb state-mc
Dis_BpbBranchPCBits : out std_logic_vector(2 downto 0);-- indiaces the 3 least sig bits of the PC value of the current instr being dis (PC[4:2])
Dis_BpbBranch : out std_logic; -- indiactes a branch instr (ren to the bpb)
--------------------------------------------------------------------------------
-- interface with the cdb
Cdb_Branch : in std_logic;
Cdb_BranchOutcome : in std_logic;
Cdb_BranchAddr : in std_logic_vector(31 downto 0);
Cdb_BrUpdtAddr : in std_logic_vector(2 downto 0);
Cdb_Flush : in std_logic;
Cdb_RobTag : in std_logic_vector(4 downto 0);
------------------------------------------------------------------------------
-- interface with checkpoint module (CFC)
Dis_CfcRsAddr : out std_logic_vector(4 downto 0); -- indicates the Rs Address to be read from Reg file
Dis_CfcRtAddr : out std_logic_vector(4 downto 0); -- indicates the Rt Address to be read from Reg file
Dis_CfcRdAddr : out std_logic_vector(4 downto 0); -- indicates the Rd Address to be written by instruction
-- goes to Dis_CfcRdAddr of ROB too
Cfc_RsPhyAddr : in std_logic_vector(5 downto 0); -- Rs Physical register Tag corresponding to Rs Addr
Cfc_RtPhyAddr : in std_logic_vector(5 downto 0); -- Rt Physical register Tag corresponding to Rt Addr
Cfc_RdPhyAddr : in std_logic_vector(5 downto 0); -- Rd Old Physical register Tag corresponding to Rd Addr
Cfc_Full : in std_logic ; -- indicates that all RATs are used and hence we stall in case of branch or Jr $31
Dis_CfcBranchTag : out std_logic_vector(4 downto 0) ; -- indicats the rob tag of the branch for which checkpoint is to be done
Dis_CfcRegWrite : out std_logic; -- indicates that the instruction in the dispatch is a register writing instruction and hence should update the active RAT with destination register tag.
Dis_CfcNewRdPhyAddr : out std_logic_vector(5 downto 0); -- indicates the new physical register to be assigned to Rd for the instruciton in first stage
Dis_CfcBranch : out std_logic; -- indicates if branch is there in first stage of dispatch... tells cfc to checkpoint
Dis_CfcInstValid : out std_logic;
--------------------------------------------------------------------------------
-- physical register interface
PhyReg_RsDataRdy : in std_logic ; -- indicating if the value of Rs is ready at the physical tag location
PhyReg_RtDataRdy : in std_logic ; -- indicating if the value of Rt is ready at the physical tag location
-- translate_off
Dis_Instruction : out std_logic_vector(31 downto 0);
-- translate_on
--------------------------------------------------------------------------------
-- interface with issue queues
Dis_RegWrite : out std_logic;
Dis_RsDataRdy : out std_logic; -- tells the queues that Rs value is ready in PRF and no need to snoop on CDB for that.
Dis_RtDataRdy : out std_logic; -- tells the queues that Rt value is ready in PRF and no need to snoop on CDB for that.
Dis_RsPhyAddr : out std_logic_vector(5 downto 0); -- tells the physical register mapped to Rs (as given by Cfc)
Dis_RtPhyAddr : out std_logic_vector(5 downto 0); -- tells the physical register mapped to Rt (as given by Cfc)
Dis_RobTag : out std_logic_vector(4 downto 0);
Dis_Opcode : out std_logic_vector(2 downto 0); -- gives the Opcode of the given instruction for ALU operation
Dis_IntIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_LdIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_DivIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_MulIssquenable : out std_logic; -- informs the respective issue queue that the dispatch is going to enter a new entry
Dis_Immediate : out std_logic_vector(15 downto 0); -- 15 bit immediate value for lw/sw address calculation and addi instruction
Issque_IntQueueFull : in std_logic;
Issque_LdStQueueFull : in std_logic;
Issque_DivQueueFull : in std_logic;
Issque_MulQueueFull : in std_logic;
Issque_IntQueTwoOrMoreVacant : in std_logic; -- indicates that 2 or more slots are available in integer queue
Issque_LdStQueTwoOrMoreVacant : in std_logic;
Issque_DivQueTwoOrMoreVacant : in std_logic;
Issque_MulQueTwoOrMoreVacant : in std_logic;
Dis_BranchOtherAddr : out std_logic_vector(31 downto 0); -- indicates 32 pins for carrying branch other address to be used incase of misprediction.
Dis_BranchPredict : out std_logic; -- indicates the prediction given by BPB for branch instruction
Dis_Branch : out std_logic;
Dis_BranchPCBits : out std_logic_vector(2 downto 0);
Dis_JrRsInst : out std_logic;
Dis_JalInst : out std_logic ; -- Indicating whether there is a call instruction
Dis_Jr31Inst : out std_logic;
----------------------------------------------------------------------------------
---- interface with the FRL---- accessed in first sage only so dont need NaerlyEmpty signal from Frl
Frl_RdPhyAddr : in std_logic_vector(5 downto 0); -- Physical tag for the next available free register
Dis_FrlRead : out std_logic ; -- indicating if free register given by FRL is used or not
Frl_Empty : in std_logic; -- indicates that there are no more free physical registers
----------------------------------------------------------------------------------
---- interface with the RAS
Dis_RasJalInst : out std_logic ; -- indicating whether there is a call instruction
Dis_RasJr31Inst : out std_logic;
Dis_PcPlusFour : out std_logic_vector(31 downto 0); -- represents the return address of Jal call instruction
Ras_Addr : in std_logic_vector(31 downto 0); -- popped RAS address from RAS
----------------------------------------------------------------------------------
---- interface with the rob
Dis_PrevPhyAddr : out std_logic_vector(5 downto 0); -- indicates old physical register mapped to Rd of the instruction
Dis_NewRdPhyAddr : out std_logic_vector(5 downto 0); -- indicates new physical register to be assigned to Rd (given by FRL)
Dis_RobRdAddr : out std_logic_vector(4 downto 0); -- indicates the Rd Address to be written by instruction -- send to Physical register file too.. so that he can make data ready bit "0"
Dis_InstValid : out std_logic ;
Dis_InstSw : out std_logic ;
Dis_SwRtPhyAddr : out std_logic_vector(5 downto 0); -- indicates physical register mapped to Rt of the Sw instruction
Rob_BottomPtr : in std_logic_vector(4 downto 0);
Rob_Full : in std_logic;
Rob_TwoOrMoreVacant : in std_logic
);
end dispatch_unit;
architecture behv of dispatch_unit is
signal Ifetch_Instruction_small :std_logic_vector(5 downto 0);
signal dispatch_rsaddr,dispatch_rtaddr,dispatch_rdaddr:std_logic_vector(4 downto 0);
signal sel_que_full ,sel_que_nearly_full: std_logic;
signal DisJal ,DisJr31 ,DisJrRs,RegWrite , jr_stall :std_logic ;
signal jr_rob_tag : std_logic_vector(4 downto 0);
signal StageReg_RdAddr ,Dis_CfcRdAddrTemp : std_logic_vector(4 downto 0);
signal IntIssquenable ,DivIssquenable,LdIssquenable,MulIssquenable , ren_var : std_logic ;
signal InstValid , InstSw ,Branch ,BranchPredict: std_logic ;
signal Opcode , BranchPCBits : std_logic_vector (2 downto 0);
signal ImmLdSt : std_logic_vector(15 downto 0);
signal StageReg_IntIssquenable ,StageReg_DivIssquenable,StageReg_LdIssquenable,StageReg_MulIssquenable : std_logic ;
signal StageReg_InstValid, StageReg_InstSw ,StageReg_Branch ,StageReg_RegWrite ,StageReg_BranchPredict: std_logic ;
signal StageReg_Opcode , StageReg_BranchPCBits : std_logic_vector (2 downto 0);
signal StageReg_ImmLdSt : std_logic_vector(15 downto 0);
signal StageReg_BranchOtherAddr , BranchOtherAddr: std_logic_vector(31 downto 0);
signal StageReg_JrRsInst ,StageReg_Jr31Inst,StageReg_JalInst : std_logic ;
signal StageReg_NewRdPhyAddr : std_logic_vector(5 downto 0);
signal StageReg_Instruction : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
--variable assignments---------------
Ifetch_Instruction_small <= Ifetch_Instruction(31 downto 26);
dispatch_rsaddr <=Ifetch_Instruction(25 downto 21);
dispatch_rtaddr <=Ifetch_Instruction(20 downto 16);
dispatch_rdaddr <=Ifetch_Instruction(15 downto 11);
---- process for interactions with IFETCH
ifetch_comm : process(Ifetch_Instruction,sel_que_full,Rob_Full,Ifetch_Instruction_small,
Cdb_Flush,Ifetch_PcPlusFour,Ifetch_EmptyFlag,Bpb_BranchPrediction,
Cdb_BranchAddr,DisJal,DisJr31,DisJrRs,RegWrite, sel_que_nearly_full,Rob_TwoOrMoreVacant,
StageReg_InstValid,StageReg_RegWrite, Cfc_Full , Branch,InstValid,
jr_stall, Frl_Empty, Cdb_RobTag, jr_rob_tag, Ras_Addr
)
variable branch_addr_sign_extended_var ,branch_target_addr:std_logic_vector(31 downto 0);
variable branch_addr_sign_extended_shifted_var :std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
-- Task1:
-- 1. Correct the sign-extension operation implemented in the if statement below
if (Ifetch_Instruction(15) = '1') then
branch_addr_sign_extended_var := X"0000" & Ifetch_Instruction(15 downto 0) ; -- This line is incorrect and you need to modify it
else
branch_addr_sign_extended_var := X"FFFF" & Ifetch_Instruction(15 downto 0) ; -- This line is incorrect and you need to modify it
end if ;
-- 2. Complete the branch target address calculation
branch_addr_sign_extended_shifted_var := branch_addr_sign_extended_var(29 downto 0)& "00";
branch_target_addr := ; -- Complete this statement
-- End of Task1
----------------------------------------------------------
----------------------------------------------------------
-- Dis_Ren: In this process we generate the read enable signal of IFQ. When the 1st stage dispatch is stalled for one reason
-- or IFQ is empty then read enable should be 0 otherwise it going to be 1.
-- Dis_JmpBr: At the same time we generate the Dis_JmpBr signal. This signal is used to flush the IFQ and start fetching instruction
-- from other direction in any of the following cases: branch instr in dispatch predicted taken, jump instruction in dispatch,
-- Flush signal active due to misprediction, or Jr $rs instruction coming out of stall.
-- Dis_JmpBr has higher priority over Dis_Ren
-- NOTE : The two or more vacant slot condition of rob is checked with StageReg_InstValid to make sure that instruction in 2nd stage dispatch is a valid instruction
-- The same apply for Frl_empty which is checked with RegWrite signal to make sure that instruction in 1st stage dispatch is a register writing instruction
if ((sel_que_full= '1')or (sel_que_nearly_full = '1') or (Rob_Full= '1') or
(Rob_TwoOrMoreVacant = '0' and StageReg_InstValid = '1')or (Ifetch_EmptyFlag = '1') or
(jr_stall = '1') or (Frl_Empty = '1' and RegWrite = '1') or (Cfc_Full = '1' and (Branch = '1' or DisJr31 = '1'))) then
ren_var <= '0' ;
Dis_Ren<= '0';
else
ren_var <= '1' ;
Dis_Ren<= '1';
end if ;
-- Note : Bpb_BranchPrediction is "0" by default . It is "1" only if there is a branch instruction and the prediction is true in the prediction bit table
-- CONDITIONAL INSTRUCTIONS AND CDBFLUSH IS CHECKED HERE...
if ( (((Ifetch_Instruction_small= "000010") or (((DisJal = '1') or (DisJr31 = '1' or DisJrRs = '1')) and InstValid = '1')
or (Bpb_BranchPrediction = '1') )and Ifetch_EmptyFlag = '0') or (Cdb_Flush='1') or (jr_stall = '1' and Cdb_RobTag = jr_rob_tag))then -- confirm
Dis_JmpBr<= '1';
else
Dis_JmpBr<= '0';
end if ;
-- Dis_JmpBrAddrValid: Pin from dispatch to IFetch telling if JR addr is valid...
Dis_JmpBrAddrValid <= not (DisJrRs and InstValid) ; -- in ifetch this pin is checked along with disaptch_jm_br pin..
-- Thus keeping it "1" as default is harmless..But it should be "0" for "jr $rs" inst
----------------------------------------------------------
-- Task2: Complete the following piece of code to generate the next address from which you need to start fetching
-- incase Dis_JmpBr is set to 1.
-- Dis_JmpBrAddrValid
-- Note : Cdb has the responsibility of generating Cdb_Flush at mispredicted branches and mispredicted "jr $31" instructions
-- Have to jump when dispatch is waiting for jr $RS once it comes on Cdb
if (Cdb_Flush= '1' or (jr_stall = '1' and Cdb_RobTag = jr_rob_tag))then -- Cdb_Flush -- can't avoid as have to give priority to CDB flush over any conditional instruction in dispatch
Dis_JmpBrAddr<=Cdb_BranchAddr ;
else
-- have to give the default value to avoid latch
Dis_JmpBrAddr<=Cdb_BranchAddr ;
if ((Ifetch_Instruction_small = "000010") or (DisJal = '1')) then -- jump
Dis_JmpBrAddr <= ; -- Complete this line
elsif (DisJr31 = '1') then -- JR $31 .. use address popped from RAS
Dis_JmpBrAddr <= ; -- Complete this line
elsif (Bpb_BranchPrediction = '1' ) then -- Branch predicted taken
Dis_JmpBrAddr <= ; -- Complete this line
end if ;
end if ;
-- End of Task2
----------------------------------------------------------
end process;
----------------------------------------------------------
-- selective_que_full Process:
-- This process is used to generate the sel_que_full signal which indicates if the desired instruction
-- issue queue is full or not. Basically, what we need to do is to investigate the opcode of the instruction
-- in the dispatch stage and then we check the full bit of the corresponding instr issue queue. If the
-- corresponding issue queue is full then we set the sel_que_full bit to '1' otherwise it is set to '0'.
selective_que_full:process(Ifetch_Instruction_small,Ifetch_Instruction,Issque_IntQueueFull,
Issque_DivQueueFull,Issque_MulQueueFull,Issque_LdStQueueFull )
begin
if ((( (Ifetch_Instruction_small="000000") and((Ifetch_Instruction(5 downto 0) = "100000") -- add
or (Ifetch_Instruction(5 downto 0) = "100010") or -- sub
(Ifetch_Instruction(5 downto 0) = "100100") or -- and
(Ifetch_Instruction(5 downto 0) = "100101") or --or
(Ifetch_Instruction(5 downto 0) = "101010"))) -- slt
or ( Ifetch_Instruction_small="001000" ) -- addi
or ( Ifetch_Instruction_small="000101" ) -- bne
or ( Ifetch_Instruction_small="000100" ) -- beq
or ( Ifetch_Instruction_small="000011" ) -- jal
or ( Ifetch_Instruction_small="000000" and (Ifetch_Instruction(5 downto 0) = "001000"))) -- jr
and Issque_IntQueueFull='1' -- jr
) then
sel_que_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011011") -- div
and (Issque_DivQueueFull='1')) then
sel_que_full<='1';
elsif ((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "011001") -- mul
and (Issque_MulQueueFull = '1' )) then
sel_que_full<='1';
elsif (((Ifetch_Instruction_small="100011") or (Ifetch_Instruction_small="101011")) -- load / store
and (Issque_LdStQueueFull = '1')) then
sel_que_full<='1';
else
sel_que_full<='0';
end if ;
end process;
----------------------------------------------------------
-- Task3: Complete the selective_que_nearly_full Process
-- This process is used to generate the sel_que_nearly_full signal which indicates if the desired instruction
-- issue queue has less than 2 vacancies ( 1 or 0) and the instruction in the 2nd dispatch stage is of the same
-- type.
-- Hint: This process is very similar to the selective_que_full process.
selective_que_nearly_full:process(Ifetch_Instruction_small,Ifetch_Instruction,Issque_IntQueTwoOrMoreVacant,
Issque_DivQueTwoOrMoreVacant,Issque_MulQueTwoOrMoreVacant,Issque_LdStQueTwoOrMoreVacant,
StageReg_IntIssquenable, StageReg_DivIssquenable, StageReg_MulIssquenable, StageReg_LdIssquenable -- Added by Vaibhav
)
begin
-- Add your Code of Task3 here.
-------------------------------
-------------------------------
-------------------------------
end process;
-- End of Task3
----------------------------------------------------------
----------------------------------------------------------
-- make_rob_entry Process:
-- The name of the process may cause some confusion. In this process we generate 3 signals:
-- 1. InstValid signal: This signal indicates if the instruction in the 1st stage dispatch is valid or not. Invalid instructions
-- include the following:
-- if the flush signal is active then the instruction in dispatch is flushed
-- if the instruction is a jump instruction which executes in dispatch and then vanishes.
-- JR $rs: This is a special case, since we stall the pipeline until JR $rs completes and it appears on Cdb. In
-- we need an RobTag to identify when the instruction comes on Cdb but no Rob entry is needed as the instr
-- vanishes after the Cdb and does not enter ROB.
-- For Invalid instructions we don't need to assign an ROB entry for that instruction.
make_rob_entry: process(Cdb_Flush, ren_var,dispatch_rsaddr, dispatch_rtaddr , dispatch_rdaddr , Ifetch_Instruction_Small,Ifetch_Instruction)
begin
if ( (ren_var = '0') or (Cdb_Flush ='1') or (Ifetch_Instruction_small="000010")or
((Ifetch_Instruction_small="000000") and (Ifetch_Instruction(5 downto 0) = "001000") and (dispatch_rsaddr /= "11111")) )then
InstValid<='0';
else
InstValid<='1';
end if;
-- 2. InstSw signal: This signal indicates if the instruction in the 1st stage dispatch is a SW instruction.
if (Ifetch_Instruction_small="101011") then -- store word
InstSw <='1';
else
InstSw <='0';
end if ;
-- 3. Dis_CfcRdAddrTemp: This signal holds the Rd address of the instruction in dispatch
----------------------------------------------------------
-- Task4: Write an if-statement to generate Dis_CfcRdAddrTemp
-- Hint: R-type instructions use $rd field, lw and addi use $rt as destination, jal uses $31 as destination.
-- Add your Code of Task4 here.
-------------------------------
-------------------------------
-------------------------------
-- End of Task4
----------------------------------------------------------
end process ;
----------- Interface with issue queue-------------
-- This process is used to generate the enable signal for the desired issue queue. This signal acts
-- as a wen signal to update the desired issue queue. In addition, we generate the 3-bit ALUOpcode used
-- with r-type, addi, branch and ld/sw instructions.
process (Ifetch_Instruction_small,Ifetch_Instruction , ren_var,Cdb_Flush)
begin
DivIssquenable <= '0';
MulIssquenable <= '0';
IntIssquenable <= '0';
LdIssquenable <= '0' ;
Opcode <= "000";
if ((ren_var = '0') or (Cdb_Flush ='1') or (Ifetch_Instruction_small="000010")) then -- "000010" jump instruction
ImmLdSt <= Ifetch_Instruction(15 downto 0);
-- No entry in any queue is to be made. Queue enables has default value of "0"
else
ImmLdSt <= Ifetch_Instruction(15 downto 0);
case Ifetch_Instruction_small is
when "000000" =>
case Ifetch_Instruction(5 downto 0 ) is
when "011011" => ----div
DivIssquenable <= '1';
when "011001" => ---mul
MulIssquenable <= '1';
when "100000" => ---- add
IntIssquenable <= '1';
when "100010" => ---sub
IntIssquenable <= '1';
Opcode <= "001";
when "100100" => ---and
IntIssquenable <= '1';
Opcode <= "010";
when "100101" => ---or
IntIssquenable <= '1';
Opcode <= "011";
when "101010" => ---slt
IntIssquenable <= '1';
Opcode <= "101";
when "001000" => ---jr
IntIssquenable <= '1';
when others =>
Opcode <= "000";
end case;
when "001000" => -- addi
IntIssquenable <= '1';
Opcode <= "100";
when "000011" => -----jal
IntIssquenable <= '1';
when "000100" => -----beq
IntIssquenable <= '1';
Opcode <= "110";
when "000101" => -- bne
IntIssquenable <= '1';
Opcode <= "111";
when "100011" => -- Load
LdIssquenable <= '1';
Opcode(0)<= '1';
Opcode(2 downto 1)<= "00";
when "101011" => -- store
LdIssquenable <= '1';
Opcode(0)<= '0';
Opcode(2 downto 1)<= "00";
when others =>
Opcode <= "000";
end case ;
end if;
end process;
--- GENERATING RegWrite signal ------------------------------
-- Task5: Your task is to generate the RegWrite signal.
-- Hint1: Why do we need to include the Dis_CfcRdAddrTemp in the sensitivity list !!!
-- Hint2: For R-type instructions you need to check both opcode and the function field. Jr $rs and
-- Jr $31 have the same opcode as R-Type but are not register writing instruction.
process (Ifetch_Instruction_small, Ifetch_Instruction , Dis_CfcRdAddrTemp)
begin
-- Add your Code of Task5 here.
-------------------------------
-------------------------------
-------------------------------
-- End of Task5
----------------------------------------------------------
end process ;
-- Generating Jal , JrRs and Jr31 signals
process (Ifetch_Instruction_small, Ifetch_Instruction , dispatch_rsaddr)
begin
DisJr31 <= '0';
DisJrRs <= '0';
DisJal<= '0';
if ((Ifetch_Instruction_small = "000000") and (Ifetch_Instruction(5 downto 0 ) = "001000")) then-- jr
if (dispatch_rsaddr = "11111") then
DisJr31 <= '1';
else
DisJrRs <= '1';
end if;
elsif ( Ifetch_Instruction_small = "000011") then
DisJal<= '1';
end if;
end process ;
-- Generating Branch PC bits and Branch signal
bpb_comm_read:process(Ifetch_PcPlusFour,Ifetch_Instruction_small)
begin
BranchPCBits <= (Ifetch_PcPlusFour(4 downto 2) - 1); -- to get PC for instruction
if ((Ifetch_Instruction_small="000100") OR (Ifetch_Instruction_small="000101" )) then -- beq or bne
Branch <= '1'; -- queues and bpb
else
Branch <= '0';
end if ;
end process;
-- CLOCK PROCESS FOR GENERATING STALL SIGNAL ON JR $RS INSTRUCTION
-- This is a very important process which takes care of generating the stall signal required in case of Jr $rs
-- instruction. When there is a JR $rs instruction in dispatch, first we set the jr_stall flag which is used to stall
-- the dispatch stage. At the same time we record the Rob Tag mapped to the JR $rs instruction in a special register.
-- We snoop on the Cdb waiting for that Rob Tag in order to get the value of $rs which represents the jump address. At
-- that moment we can come out from the stall.
-- Note that the Jr $rs disappears after coming out on the Cdb and does not enter the ROB and hence no ROB entry is needed.
-- However, we still need to assign an Rob Tag for the Jr $rs instruction in order to use it for snooping on the Cdb.
-- Task6: The process is almost complete you just need to update the condition of two if statements
jr_process: process(Clk,Resetb)
begin
if (Resetb = '0') then
jr_stall <= '0';
jr_rob_tag <= "00000"; -- can be don't care also
elsif (Clk'event and Clk = '1') then
if (Cdb_Flush = '1') then
jr_stall <= '0' ;
else
if (Ifetch_Instruction(5 downto 0 )="001000" and Ifetch_Instruction_small = "000000")then -- if jr
-- Add the condition for the following if statement.
-- Hint: Single Condition
if () then
jr_stall <= '1' ;
if (StageReg_InstValid = '0') then
jr_rob_tag <= Rob_BottomPtr ;
else
jr_rob_tag <= Rob_BottomPtr + 1 ;
end if;
end if ;
end if ; -- end of if jr
-- Complete the condition for the following if statement.
-- Hint: How do you know when to come out of the JR $rs stall!!
if (jr_stall = '1' and ()) then
jr_stall <= '0';
end if ;
end if ;-- if Cdb_Flush
end if ; -- if Resetb
-- End of Task6
----------------------------------------------------------
end process ;
----------------------------------------------------------
-- issue_queue_entry Process:
-- In this process we generate the BranchOtherAddr signal which is used in case of misprediction of branch instruction.
issue_queue_entry :process(Ifetch_Instruction,Ifetch_PcPlusFour,Bpb_BranchPrediction,DisJal, DisJr31,Ras_Addr)
variable branch_addr_sign_extended_var ,branch_target_addr:std_logic_vector(31 downto 0);
variable branch_addr_sign_extended_shifted_var :std_logic_vector(31 downto 0);
begin
if (Ifetch_Instruction(15) = '1') then
branch_addr_sign_extended_var := X"FFFF" & Ifetch_Instruction(15 downto 0) ;
else
branch_addr_sign_extended_var := X"0000" & Ifetch_Instruction(15 downto 0) ;
end if ;
branch_addr_sign_extended_shifted_var := branch_addr_sign_extended_var(29 downto 0)& "00";
branch_target_addr := branch_addr_sign_extended_shifted_var + Ifetch_PcPlusFour;
--------------------------- NOTE--------------------------------------------------
-- Dis_BranchOtherAddr pins carry the following :
-- a) In case of a branch , we sent the "other address" with branch. By "other address " we mean , the address to be taken in case the branch is mis-predicted
-- If the branch was predicted to be "not taken" , then we keep on executing the instructions from PC + 4 location only. In case of mis-prediction,
-- we need to jump to target address calculated , thus we send branch_target_Addr on these pins
-- If the branch was predicted to be "taken" , then we started executing instructions from "target address". In case of mis-prediction,
-- we actually need to execute instructions from PC+4 , thus we send PC+4 on the pins
-- b) In case of jr , the pins carry the address given by RAS (valid or invalid). Sending the invlaid address will be harmless. That address is compared with
-- the correct address from software stack and a flush signal is initiated in case of mis-match.
-- c) In case of jal, the pins carry PC+4 which is stored in register $31.
-----------------------------------------------------------------------------------------
if(Bpb_BranchPrediction = '1' or DisJal = '1') then
BranchOtherAddr <= Ifetch_PcPlusFour;
elsif (DisJr31 = '1') then
BranchOtherAddr <= Ras_Addr;
else
BranchOtherAddr <= branch_target_addr; -- put jr addr from RAS in case of jr
end if ;
end process;
-- PHYSICAL FILE SIGNALS (From second stage)
Dis_RsPhyAddr <= Cfc_RsPhyAddr;
Dis_RtPhyAddr <= Cfc_RtPhyAddr;
-- BPB SIGNALS... INTERFACE WITH BPB IS FROM FIRST STAGE
Dis_CdbUpdBranch <= Cdb_Branch;
Dis_CdbUpdBranchAddr<=Cdb_BrUpdtAddr;
Dis_CdbBranchOutcome<=Cdb_BranchOutcome; ---outcome bit from rob;
Dis_BpbBranchPCBits <= BranchPCBits ;
Dis_BpbBranch <= Branch ;
-- CFC SIGNALS.. INTERFACE WITH CFC IS FROM FIRST STAGE
Dis_CfcBranchTag <= Rob_BottomPtr when (StageReg_InstValid = '0') else Rob_BottomPtr + 1;
Dis_CfcRegWrite <= RegWrite and InstValid ;
Dis_CfcRsAddr <= dispatch_rsaddr ;
Dis_CfcRtAddr <= dispatch_rtaddr ;
Dis_CfcRdAddr <= Dis_CfcRdAddrTemp ;
Dis_CfcBranch <= Branch ;
Dis_CfcNewRdPhyAddr <= Frl_RdPhyAddr ;
Dis_CfcInstValid <= InstValid;
-- FRL SIGNALS.. INTERFACE WITH FRL IS FROM FIRST STAGE
Dis_FrlRead <= RegWrite and InstValid;
-- RAS SIGNALS.. INTERFACE WITH RAS IS FROM FIRST STAGE
Dis_PcPlusFour <= Ifetch_PcPlusFour ;
Dis_RasJalInst <= DisJal and InstValid;
Dis_RasJr31Inst <= DisJr31 and InstValid;
-- ISSUEQUE SIGNALS.. INTERFACE WITH ISSUEQUE IS FROM SECOND STAGE
-- translate_off
Dis_Instruction <= StageReg_Instruction ;
-- translate_on
Dis_RsDataRdy <= PhyReg_RsDataRdy ;
Dis_RtDataRdy <= PhyReg_RtDataRdy ;
Dis_RobTag <= Rob_BottomPtr ;
Dis_Opcode <= StageReg_Opcode;
Dis_IntIssquenable <= StageReg_IntIssquenable when (Cdb_Flush = '0') else '0';
Dis_LdIssquenable <= StageReg_LdIssquenable when (Cdb_Flush = '0') else '0';
Dis_DivIssquenable <= StageReg_DivIssquenable when (Cdb_Flush = '0') else '0';
Dis_MulIssquenable <= StageReg_MulIssquenable when (Cdb_Flush = '0') else '0';
Dis_Immediate <= StageReg_ImmLdSt ;
Dis_BranchOtherAddr <= StageReg_BranchOtherAddr ;
Dis_BranchPredict <= StageReg_BranchPredict;
Dis_Branch <= StageReg_Branch ;
Dis_BranchPCBits <= StageReg_BranchPCBits ;
Dis_JrRsInst <= StageReg_JrRsInst ;
Dis_Jr31Inst <= StageReg_Jr31Inst ;
Dis_JalInst <= StageReg_JalInst ;
-- ROB SIGNALS.. INTERFACE WITH ROB IS FROM SECOND STAGE
Dis_PrevPhyAddr <= Cfc_RdPhyAddr ;
Dis_NewRdPhyAddr <= StageReg_NewRdPhyAddr ;
Dis_RobRdAddr <= StageReg_RdAddr ;
Dis_InstValid <= StageReg_InstValid when (Cdb_Flush = '0') else '0';
Dis_InstSw <= StageReg_InstSw when (Cdb_Flush = '0') else '0';
Dis_RegWrite <= StageReg_RegWrite when (Cdb_Flush = '0') else '0'; -- signal for Queues too
Dis_SwRtPhyAddr <= Cfc_RtPhyAddr;
-- PROCESS FOR STAGE REGISTER of dispatch
process(Clk, Resetb)
begin
if (Resetb = '0') then
StageReg_InstValid <= '0';
StageReg_InstSw <= '0';
StageReg_RegWrite <= '0';
StageReg_IntIssquenable <= '0';
StageReg_LdIssquenable <= '0';
StageReg_DivIssquenable <= '0';
StageReg_MulIssquenable <= '0';
StageReg_Branch <= '0';
StageReg_JrRsInst <= '0';
StageReg_Jr31Inst <= '0';
StageReg_JalInst <= '0';
elsif (Clk'event and Clk = '1' ) then
StageReg_RdAddr <= Dis_CfcRdAddrTemp ;
StageReg_InstValid <= InstValid ;
StageReg_InstSw <= InstSw ;
StageReg_RegWrite <= RegWrite and InstValid; -- RegWrite , DisJrRs, DisJal and DisJr31 are generated in the process without checking the validity of instruciton . Thus needs to be validated with InstValid signal
StageReg_Instruction <= Ifetch_Instruction ;
StageReg_NewRdPhyAddr <= Frl_RdPhyAddr;
StageReg_Opcode <= Opcode;
StageReg_IntIssquenable <= IntIssquenable ;
StageReg_LdIssquenable <= LdIssquenable;
StageReg_DivIssquenable <= DivIssquenable;
StageReg_MulIssquenable <= MulIssquenable;
StageReg_ImmLdSt <= ImmLdSt ;
StageReg_BranchOtherAddr <= BranchOtherAddr ;
StageReg_BranchPredict <= Bpb_BranchPrediction ;
StageReg_Branch <= Branch ;
StageReg_BranchPCBits <= BranchPCBits ;
StageReg_JrRsInst <= DisJrRs and InstValid;
StageReg_Jr31Inst <= DisJr31 and InstValid;
StageReg_JalInst <= DisJal and InstValid;
end if ;
end process;
end behv ;
|
gpl-2.0
|
f0cd5fb2de66b88aa1d438bfe76b6b27
| 0.586458 | 4.531451 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/incrementadorCuenta10bits.vhd
| 1 | 4,209 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: incrementadorCuenta10bits.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity incrementadorCuenta10bits is
Port ( num_in : in STD_LOGIC_VECTOR (9 downto 0);
num_out : out STD_LOGIC_VECTOR (9 downto 0)
);
end incrementadorCuenta10bits;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture arq of incrementadorCuenta10bits is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal aux: std_logic_vector(8 downto 0);
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT adder1bit_comb
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
COMPONENT adder1bit_noCout
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
adder_0: adder1bit_comb port map(
A => num_in(0),
B => '1',
Cin => '0',
Z => num_out(0),
Cout => aux(0)
);
adder_1: adder1bit_comb port map(
A => num_in(1),
B => aux(0),
Cin => '0',
Z => num_out(1),
Cout => aux(1)
);
adder_2: adder1bit_comb port map(
A => num_in(2),
B => aux(1),
Cin => '0',
Z => num_out(2),
Cout => aux(2)
);
adder_3: adder1bit_comb port map(
A => num_in(3),
B => aux(2),
Cin => '0',
Z => num_out(3),
Cout => aux(3)
);
adder_4: adder1bit_comb port map(
A => num_in(4),
B => aux(3),
Cin => '0',
Z => num_out(4),
Cout => aux(4)
);
adder_5: adder1bit_comb port map(
A => num_in(5),
B => aux(4),
Cin => '0',
Z => num_out(5),
Cout => aux(5)
);
adder_6: adder1bit_comb port map(
A => num_in(6),
B => aux(5),
Cin => '0',
Z => num_out(6),
Cout => aux(6)
);
adder_7: adder1bit_comb port map(
A => num_in(7),
B => aux(6),
Cin => '0',
Z => num_out(7),
Cout => aux(7)
);
adder_8: adder1bit_comb port map(
A => num_in(8),
B => aux(7),
Cin => '0',
Z => num_out(8),
Cout => aux(8)
);
adder_9: adder1bit_noCout PORT MAP(
A => num_in(9),
B => aux(8),
Cin => '0',
Z => num_out(9)
);
end arq;
|
gpl-3.0
|
7080fa8a983fd7a57274ce68a44758b8
| 0.436178 | 3.719717 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/TargetCmdFIFO/simulation/fg_tb_top.vhd
| 1 | 5,822 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 21
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
75a7ae074d2b07a92558b7542bf1bea1
| 0.614565 | 4.179469 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_data_send_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,651 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_send_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
507f84d1e8c74ce8542970103f8099d6
| 0.50236 | 3.924217 | false | false | false | false |
csrhau/sandpit
|
VHDL/striped_gol/gol_ram.vhdl
| 1 | 834 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity GOL_RAM is
generic (
rows: natural;
addr_bits: natural
);
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector(addr_bits-1 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end entity GOL_RAM;
architecture behavioural of GOL_RAM is
type memory is array(0 to rows-1) of std_logic_vector(7 downto 0);
signal storage : memory := (others => (others => '0'));
begin
process(clock)
begin
if rising_edge(clock) then
data_out <= storage(to_integer(unsigned(address)));
if write_enable = '1' then
storage(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
end behavioural;
|
mit
|
5a7fd0d7d6bb099f7fbc788fad70816c
| 0.647482 | 3.322709 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/fantasma_v0.vhd
| 1 | 11,725 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: fantasma_v0.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fantasma_v0 is
Port ( -- Señales generales:
clk_50MHz : in std_logic; -- Reloj
rst : in std_logic; -- Reset
p2Hz : in std_logic; -- Pulso para retrasar el movimiento
ini : in std_logic; -- Fantasma tiene permiso para actualizarse.
fin : out std_logic; -- Fantasma ha terminado de actualizarse.
-- Lecutra de la RAM:
ram_addr_rd : out std_logic_vector(5 downto 0);
ram_data_rd : in std_logic_vector(2 downto 0);
-- Escritura en la RAM:
ram_addr_wr : out std_logic_vector(5 downto 0);
ram_data_wr : out std_logic_vector(2 downto 0);
ram_we : out std_logic;
-- Salidas para depurar:
sw_debug : in std_logic_vector(1 downto 0); -- Para seleccionar la pos.contigua
data_db : out std_logic_vector(2 downto 0); -- El dato de la pos.contigua seleccionada.
bt_rand : in std_logic_vector(1 downto 0)
);
end fantasma_v0;
architecture arq of fantasma_v0 is
-- Estados de la FSM:
type t_st is (espera, up_1, up_2, dw_1, dw_2, rg_1, rg_2, lf_1, lf_2, new_pos, wr_pos1, wr_pos2);
signal current_state, next_state : t_st; -- Estados actual y siguiente.
-- Registros con los colores de las posiciones circundantes:
signal ff_up_pos: std_logic_vector(2 downto 0);
signal ff_dw_pos: std_logic_vector(2 downto 0);
signal ff_rg_pos: std_logic_vector(2 downto 0);
signal ff_lf_pos: std_logic_vector(2 downto 0);
-- Senales con las direcciones para acceder a las posiciones circundantes:
signal up_addr: std_logic_vector(5 downto 0);
signal dw_addr: std_logic_vector(5 downto 0);
signal rg_addr: std_logic_vector(5 downto 0);
signal lf_addr: std_logic_vector(5 downto 0);
-- Registros con la posicion del fantasma:
signal my_pos_x: std_logic_vector(2 downto 0);
signal my_pos_y: std_logic_vector(2 downto 0);
signal my_pos_x_in: std_logic_vector(2 downto 0);
signal my_pos_y_in: std_logic_vector(2 downto 0);
-- Señales de carga de registros:
--all_ld <= my_ld & ff_up_ld & ff_dw_ld & ff_rg_ld & ff_lf_ld;
signal all_ld: std_logic_vector(4 downto 0); -- Todas las señales juntas
COMPONENT nueva_pos_rand_async
PORT(
up_pos : IN std_logic_vector(2 downto 0);
dw_pos : IN std_logic_vector(2 downto 0);
rg_pos : IN std_logic_vector(2 downto 0);
lf_pos : IN std_logic_vector(2 downto 0);
my_x : IN std_logic_vector(2 downto 0);
my_y : IN std_logic_vector(2 downto 0);
new_x : OUT std_logic_vector(2 downto 0);
new_y : OUT std_logic_vector(2 downto 0);
bt_rand: in std_logic_vector(1 downto 0)
);
END COMPONENT;
COMPONENT pos_circundantes
PORT(
my_x : IN std_logic_vector(2 downto 0);
my_y : IN std_logic_vector(2 downto 0);
addr_up : OUT std_logic_vector(5 downto 0);
addr_dw : OUT std_logic_vector(5 downto 0);
addr_rg : OUT std_logic_vector(5 downto 0);
addr_lf : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
begin
Inst_nueva_pos_rand: nueva_pos_rand_async PORT MAP(
up_pos => ff_up_pos,
dw_pos => ff_dw_pos,
rg_pos => ff_rg_pos,
lf_pos => ff_lf_pos,
my_x => my_pos_x,
my_y => my_pos_y,
new_x => my_pos_x_in,
new_y => my_pos_y_in,
bt_rand => bt_rand
);
Inst_pos_circundantes: pos_circundantes PORT MAP(
my_x => my_pos_x,
my_y => my_pos_y,
addr_up => up_addr,
addr_dw => dw_addr,
addr_rg => rg_addr,
addr_lf => lf_addr
);
---------------------------------------------------
-- Proceso de calculo del estado siguiente y salidas mealy
---------------------------------------------------
p_next_state : process (current_state, ini, p2Hz) is
begin
case current_state is
when espera =>
if ini = '1' then
next_state <= up_1;
else
next_state <= espera;
end if;
when up_1 =>
next_state <= up_2;
when up_2 =>
next_state <= dw_1;
when dw_1 =>
next_state <= dw_2;
when dw_2 =>
next_state <= rg_1;
when rg_1 =>
next_state <= rg_2;
when rg_2 =>
next_state <= lf_1;
when lf_1 =>
next_state <= lf_2;
when lf_2 =>
-- Comentar para realizar simulaciones.
if p2Hz = '1' then
next_state <= new_pos;
else
next_state <= current_state;
end if;
when new_pos =>
next_state <= wr_pos1;
when wr_pos1 =>
next_state <= wr_pos2;
when wr_pos2 =>
next_state <= espera;
end case;
end process p_next_state;
---------------------------------------------------
-- Proceso de asignación de valores a las salidas
---------------------------------------------------
p_outputs : process (current_state, up_addr, dw_addr, rg_addr, lf_addr, my_pos_y, my_pos_x)
begin
case current_state is
-- Standby
when espera =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '1';
all_ld <= "00000";
-- Leer arriba (1)
when up_1 =>
ram_addr_rd <= up_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer arriba (2)
when up_2 =>
ram_addr_rd <= up_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "01000";
-- Leer abajo (1)
when dw_1 =>
ram_addr_rd <= dw_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer abajo (2)
when dw_2 =>
ram_addr_rd <= dw_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00100";
-- Leer derecha (1)
when rg_1 =>
ram_addr_rd <= rg_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer derecha (2)
when rg_2 =>
ram_addr_rd <= rg_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00010";
-- Leer izquierda (1)
when lf_1 =>
ram_addr_rd <= lf_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer izquierda (2)
when lf_2 =>
ram_addr_rd <= lf_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00001";
-- Calcular nueva posicion 1
when new_pos =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= my_pos_y & my_pos_x;
ram_data_wr <= "000"; -- COLOR NEGRO
ram_we <= '1';
fin <= '0';
all_ld <= "10000"; -- Aqui tengo que escribirla ya
-- Escribir nueva posicion (1)
when wr_pos1 =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= my_pos_y & my_pos_x;
ram_data_wr <= "100"; -- COLOR ROJO
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Escribir nueva posicion (2)
when wr_pos2 =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= my_pos_y & my_pos_x;
ram_data_wr <= "100"; -- COLOR ROJO
ram_we <= '1';
fin <= '0';
all_ld <= "00000";
end case;
end process p_outputs;
---------------------------------------------------
-- Proceso de actualizacion del estado
---------------------------------------------------
p_update_state: process (clk_50MHz, rst) is
begin
if rst = '1' then
current_state <= espera;
elsif rising_edge(clk_50MHz) then
current_state <= next_state;
end if;
end process p_update_state;
--------------------------------------------------
-- Procesos de carga y reset de registros
--------------------------------------------------
p_regs: process(clk_50MHz, rst, all_ld)
begin
if rst = '1' then
ff_up_pos <= (others => '0');
ff_dw_pos <= (others => '0');
ff_rg_pos <= (others => '0');
ff_lf_pos <= (others => '0');
my_pos_x <= "001";
my_pos_y <= "001";
elsif rising_edge(clk_50MHz) then
-- Carga la posicion de arriba
if all_ld = "01000" then
ff_up_pos <= ram_data_rd;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga la posicion de abajo
elsif all_ld = "00100" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ram_data_rd;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga la posicion derecha:
elsif all_ld = "00010" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ram_data_rd;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga la posicion izquierda:
elsif all_ld = "00001" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ram_data_rd;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga mi propia posicion:
elsif all_ld = "10000" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x_in;
my_pos_y <= my_pos_y_in;
-- No carga ninguno
else
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
end if;
end if;
end process p_regs;
------------------------------------------------
-- Salidas para depurar
------------------------------------------------
p_debug: process(sw_debug, ff_up_pos, ff_dw_pos, ff_rg_pos, ff_lf_pos)
begin
-- 00-> pos. de arriba
if sw_debug = "00" then
data_db <= ff_up_pos;
-- 01-> pos. de abajo
elsif sw_debug = "01" then
data_db <= ff_dw_pos;
-- 10-> pos. derecha
elsif sw_debug = "10" then
data_db <= ff_rg_pos;
-- 11-> pos. izquierda
else
data_db <= ff_lf_pos;
end if;
end process p_debug;
end arq;
|
gpl-3.0
|
324ccb9cde7f456b590eaa1550799d2b
| 0.517868 | 2.921754 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/fifo_generator_v9_3/simulation/fifo_generator_v9_3_tb.vhd
| 1 | 6,155 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_generator_v9_3_pkg.ALL;
ENTITY fifo_generator_v9_3_tb IS
END ENTITY;
ARCHITECTURE fifo_generator_v9_3_arch OF fifo_generator_v9_3_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fifo_generator_v9_3_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fifo_generator_v9_3_synth
fifo_generator_v9_3_synth_inst:fifo_generator_v9_3_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 27
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
apache-2.0
|
7daf6ebe7a08600f4eada0c026c0dc84
| 0.617384 | 4.060026 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/gc_command_fifo/example_design/gc_command_fifo_top_wrapper.vhd
| 1 | 19,245 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: gc_command_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity gc_command_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(29-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(29-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end gc_command_fifo_top_wrapper;
architecture xilinx of gc_command_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component gc_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : gc_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
f2a4ba5db496a58fc46e211721e320f5
| 0.485269 | 3.975418 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/gc_command_fifo/example_design/gc_command_fifo_top.vhd
| 1 | 5,160 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: gc_command_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity gc_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end gc_command_fifo_top;
architecture xilinx of gc_command_fifo_top is
SIGNAL clk_i : std_logic;
component gc_command_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : gc_command_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
546b7d60a2ef552406dcfdd2b6c13efe
| 0.518217 | 4.895636 | false | false | false | false |
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