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|---|---|---|---|---|---|---|---|---|---|---|---|---|
chronos38/DSD-Projekt
|
Testbench/tb_dezctr.vhd
| 1 | 1,556 |
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_dezctr is
end tb_dezctr;
-- Beim Testen den Prescaler anpassen
architecture sim of tb_dezctr is
component dezctr
port (
clk50 : in std_logic;
reset_n : in std_logic;
sw_i : in std_logic_vector(9 downto 0);
pb_i : in std_logic_vector(1 downto 0);
ss0_o : out std_logic_vector(7 downto 0);
ss1_o : out std_logic_vector(7 downto 0);
ss2_o : out std_logic_vector(7 downto 0);
ss3_o : out std_logic_vector(7 downto 0));
end component;
signal s_clk50 : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_sw_i : std_logic_vector(9 downto 0) := (others =>'0');
signal s_pb_i : std_logic_vector(1 downto 0) := (others =>'0');
signal s_ss0_o, s_ss1_o,
s_ss2_o, s_ss3_o : std_logic_vector(7 downto 0) := (others =>'0');
begin
i_dezctr : dezctr
port map (
clk50 => s_clk50,
reset_n => s_reset_n,
sw_i => s_sw_i,
pb_i => s_pb_i,
ss0_o => s_ss0_o,
ss1_o => s_ss1_o,
ss2_o => s_ss2_o,
ss3_o => s_ss3_o
);
s_clk50 <= not s_clk50 after 1 ns;
p_test : process
begin
-- Nach Rest hochzählen
s_reset_n <= '0';
wait for 100 ns;
s_reset_n <= '1';
wait for 500 ns;
-- Runterzählen
s_pb_i(1) <= '1';
wait for 100 ns;
s_pb_i(1) <= '0';
wait for 500 ns;
end process;
end sim;
|
gpl-3.0
|
882fd0bb11760b9a9b8dc2c74f637308
| 0.505792 | 2.784946 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/TX_SEND_FIFO/example_design/TX_SEND_FIFO_top.vhd
| 1 | 4,786 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: TX_SEND_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity TX_SEND_FIFO_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end TX_SEND_FIFO_top;
architecture xilinx of TX_SEND_FIFO_top is
SIGNAL clk_i : std_logic;
component TX_SEND_FIFO is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : TX_SEND_FIFO PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
c37050d3f647cbfadd0900a011952907
| 0.526118 | 4.913758 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/TargetCmdFIFO/simulation/fg_tb_pctrl.vhd
| 1 | 16,382 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & af_chk_i & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (EMPTY = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-2.0
|
41556da6e2168b274391b2946ffa6059
| 0.520144 | 3.34668 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Command_FIFO/example_design/Command_FIFO_top.vhd
| 1 | 4,944 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Command_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Command_FIFO_top is
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end Command_FIFO_top;
architecture xilinx of Command_FIFO_top is
SIGNAL clk_i : std_logic;
component Command_FIFO is
PORT (
CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : Command_FIFO PORT MAP (
CLK => clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
bbaed1a96add80161a15b9df1a986404
| 0.519013 | 5.014199 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_rec_fifo/example_design/pcie_data_rec_fifo_top_wrapper.vhd
| 1 | 19,789 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_data_rec_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_data_rec_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(10-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(11-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(11-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(11-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(11-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(256-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(10-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(11-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end pcie_data_rec_fifo_top_wrapper;
architecture xilinx of pcie_data_rec_fifo_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_data_rec_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : pcie_data_rec_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
f597f34ea7aaf43ba909ed140938aaa4
| 0.48436 | 3.962555 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/digital_camera_tb.vhd
| 1 | 7,733 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- digital_camera_tb.vhd
--
-- Test bench for camera top level
-- Exercises image sensor data input and parallel port output
--**********************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.comp_pckgs.all;
entity digital_camera_tb is
end digital_camera_tb;
architecture digital_camera_tb_arch of digital_camera_tb is
constant RST_ACTIVE : STD_LOGIC := '0';
constant CLK_PERIOD : time := 20 nS;
constant PPD_CLK_PERIOD : time := 500 nS; --It's actually alot slower
constant start_addr : unsigned(22 downto 0) := (others=>'0');
constant end_addr : unsigned(22 downto 0) := to_unsigned((128*10)/2, 23);
-- Size of the picture is variable to cut down on simulation time
constant NUM_ROWS : integer := 10; --1024
constant NUM_COLS : integer := 128; --1280;
-- Test Ports
signal init_cycle_complete_test_port : std_logic;
-- XSA-100 interface
signal rst : std_logic;
signal clk : std_logic;
signal ce_n : std_logic;
signal s : std_logic_vector(6 downto 0);
signal dips : std_logic_vector(3 downto 0);
signal pps : std_logic_vector(6 downto 3);
signal ppd : std_logic_vector(6 downto 0);
-- SDRAM interface
signal cke : std_logic; -- SDRAM clock-enable
signal cs_n : std_logic; -- SDRAM chip-select
signal ras_n: std_logic; -- SDRAM RAS
signal cas_n: std_logic; -- SDRAM CAS
signal we_n : std_logic; -- SDRAM write-enable
signal ba : unsigned( 1 downto 0); -- SDRAM bank-address
signal sAddr: unsigned(11 downto 0); -- SDRAM address bus
signal sData: unsigned(15 downto 0); -- data bus to SDRAM
signal dqmh : std_logic; -- SDRAM DQMH
signal dqml : std_logic; -- SDRAM DQML
signal sclk : std_logic;
-- KAC interface
signal mclk_KAC : std_logic;
signal init_KAC : std_logic;
--signal sync_KAC : std_logic;
signal sof_KAC : std_logic; --Start of frame
signal vclk_KAC : std_logic; --Start of line
signal hclk_KAC : std_logic; --valid pixel data
signal pix_KAC : std_logic_vector(9 downto 0);
signal scl : std_logic;
signal sda : std_logic;
-- pullup used for simulation only. Matches pullup.vhd
component PULLUP
port(v101: OUT std_logic);
end component;
begin
DUT: digital_camera
PORT MAP
(
init_cycle_complete_test_port => init_cycle_complete_test_port,
-- XSA-100 MISC
clkin => clk,
rst => rst,
s => s,
ce_n => ce_n,
dips => dips,
pps => pps,
ppd => ppd,
-- XSA-100 SDRAM
sclkfb => sclk, --without the dlls, it's not even used
sclk => sclk,
cke => cke,
cs_n => cs_n,
ras_n => ras_n,
cas_n => cas_n,
we_n => we_n,
ba => ba,
sAddr => sAddr,
sData => sData,
dqmh => dqmh,
dqml => dqml,
--KAC-1310
mclk_KAC => mclk_KAC,
init_KAC => init_KAC,
--sync_KAC => sync_KAC,
sof_KAC => sof_KAC,
vclk_KAC => vclk_KAC,
hclk_KAC => hclk_KAC,
pix_KAC => pix_KAC,
scl => scl,
sda => sda
);
--Pull up the I2C lines for simulation
v109: PULLUP
port map(v101 => scl);
v110: PULLUP
port map(v101 => sda);
CREATE_CLK: process
variable i : integer := 0;
begin
if i <= 2 then
i := i + 1;
rst <= RST_ACTIVE;
else
rst <= not(RST_ACTIVE);
end if;
CLK <= '0';
wait for CLK_PERIOD/2;
CLK <= '1';
wait for CLK_PERIOD/2;
end process;
sData <= "0000" & sAddr when we_n = '1' else (others=>'0');
video_sync_signals: process
variable i : integer := 0;
variable j : integer := 0;
variable k : integer := 0;
begin
sof_KAC <= '0';
vclk_KAC <= '0';
hclk_KAC <= '0';
wait until rst /= RST_ACTIVE;
wait until init_cycle_complete_test_port = '1'; -- 0 active
loop
sof_KAC <= '1';
-- 8 m_clk delay after sof till first vclk
for i in 0 to 7 loop
wait until mclk_KAC'event and mclk_KAC = '1';
end loop;
for i in 0 to NUM_ROWS-1 loop
vclk_KAC <= '1';
for i in 0 to 63 loop --vclk 0 after 64 mclk
wait until mclk_KAC'event and mclk_KAC = '1';
end loop;
vclk_KAC <= '0';
for j in 0 to NUM_COLS-1 loop
wait until mclk_KAC'event and mclk_KAC = '1';
hclk_KAC <= '1';
wait until mclk_KAC'event and mclk_KAC = '0';
hclk_KAC <= '0';
end loop;
sof_KAC <= '0'; --sof 0 after 1 row
end loop;
for k in 0 to 63 loop
wait until mclk_KAC'event and mclk_KAC = '1';
end loop;
end loop;
wait;
end process video_sync_signals;
-- At the same time as the parallel port is uploading, do a transfer from
-- the sensor to memory. Testing the memory arbitrator.
KAC_pixel_generate: process
variable i : integer := 0;
begin
if rst = RST_ACTIVE then
pix_KAC <= (others=>'0');
i := 0;
else
wait until init_cycle_complete_test_port = '1';
pix_KAC <= std_logic_vector(to_unsigned(i, pix_KAC'length));
i := i + 1;
end if;
wait until hclk_KAC'event and hclk_KAC = '1';
end process KAC_pixel_generate;
-- Simulate the pc parallel port connnection. Go through the steps to transfer
-- data from start address to end address.
pport_sdram_access: process
variable i : integer := 0;
begin
dips <= (others=>'0');
ppd <= (others=>'0');
wait until rst = not(RST_ACTIVE); -- INVERSE OF RST_ACTIVE.. but not X or U
wait until init_cycle_complete_test_port = '1';
loop
-- Send upload command and toggle clock pin
ppd <= "000001" & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= "000001" & '1';
wait for PPD_CLK_PERIOD/2;
--Start address pad extra zero at top
ppd <= std_logic_vector(start_addr(5 downto 0)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(start_addr(5 downto 0)) & '1';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(start_addr(11 downto 6)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(start_addr(11 downto 6)) & '1';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(start_addr(17 downto 12)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(start_addr(17 downto 12)) & '1';
wait for PPD_CLK_PERIOD/2;
ppd <= '0' & std_logic_vector(start_addr(22 downto 18)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= '0' & std_logic_vector(start_addr(22 downto 18)) & '1';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(end_addr(5 downto 0)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(end_addr(5 downto 0)) & '1';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(end_addr(11 downto 6)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(end_addr(11 downto 6)) & '1';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(end_addr(17 downto 12)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= std_logic_vector(end_addr(17 downto 12)) & '1';
wait for PPD_CLK_PERIOD/2;
ppd <= '0' & std_logic_vector(end_addr(22 downto 18)) & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= '0' & std_logic_vector(end_addr(22 downto 18)) & '1';
--Generate some clocks on ppd(0) to upload the data
--Go for length of data. figure this, don't hard code it.
for i in 0 to to_integer(end_addr-start_addr)*2 loop
wait for PPD_CLK_PERIOD/2;
ppd <= "000000" & '0';
wait for PPD_CLK_PERIOD/2;
ppd <= "000000" & '1';
end loop;
wait for PPD_CLK_PERIOD;
--ppd <= "000000" & '0';
end loop;
wait; --make sure to end it
end process;
end digital_camera_tb_arch;
|
gpl-3.0
|
e66906991a9b6786cd626c397425033d
| 0.596922 | 2.92142 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/clk_wiz_v3_6/example_design/clk_wiz_v3_6_exdes.vhd
| 1 | 5,418 |
-- file: clk_wiz_v3_6_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_6_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end clk_wiz_v3_6_exdes;
architecture xilinx of clk_wiz_v3_6_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component clk_wiz_v3_6 is
port
(-- Clock in ports
clk : in std_logic;
-- Clock out ports
clk_20MHz : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clk_wiz_v3_6
port map
(-- Clock in ports
clk => CLK_IN1,
-- Clock out ports
clk_20MHz => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
|
apache-2.0
|
2a49babe2a48dc1e0151121786690ad1
| 0.616279 | 3.998524 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_3/top_tb_withCfcComp_r1.vhd
| 1 | 16,721 |
-------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Branch Prediction Buffer
-- Project : Tomasulo Processor
-- Author : Da Cheng
-- Data : June,2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- synopsys translate_off
--use reverseAssemblyFunctionPkg.all; --modified by sabya - not needed in top!
-- synopsys translate_on
-----------------------------------------------------------------------------
--added by Sabya to use compiled library
library ee560;
use ee560.all;
------------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_ROB of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden CFC)
signal Cfc_RdPhyAddr_gold :std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
signal Cfc_RsPhyAddr_gold :std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
signal Cfc_RtPhyAddr_gold :std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
signal Cfc_Full_gold :std_logic; --Flag indicating whether checkpoint table is full or not
--signals from cfc to ROB in case of CDB flush
signal Cfc_RobTag_gold :std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
signal Cfc_FrlHeadPtr_gold :std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
-- Signals for the student's UUT (CFC)
signal Resetb : std_logic; --Global Reset Signal
--interface with dispatch unit
signal Dis_CfcInstValid : std_logic; --Flag indicating if the instruction dispatched is valid or not
signal Dis_CfcBranchTag : std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
signal Dis_CfcRdAddr : std_logic_vector(4 downto 0); --Rd Logical Address
signal Dis_CfcRsAddr : std_logic_vector(4 downto 0); --Rs Logical Address
signal Dis_CfcRtAddr : std_logic_vector(4 downto 0); --Rt Logical Address
signal Dis_CfcNewRdPhyAddr : std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
signal Dis_CfcRegWrite : std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
signal Dis_CfcBranch : std_logic; --Flag indicating whether current instruction being dispatched is branch or not
signal Dis_RasJr31Inst : std_logic; --Flag indicating if the current instruction is Jr 31 or not
signal Cfc_RdPhyAddr :std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
signal Cfc_RsPhyAddr :std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
signal Cfc_RtPhyAddr :std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
signal Cfc_Full :std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
signal Rob_TopPtr :std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
signal Rob_Commit :std_logic; --Flag indicating whether instruction is committing in this cycle or not
signal Rob_CommitRdAddr :std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
signal Rob_CommitRegWrite :std_logic; --Indicates if instruction is writing to register or not
signal Rob_CommitCurrPhyAddr :std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
signal Cfc_RobTag :std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
signal Frl_HeadPtr :std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
signal Cfc_FrlHeadPtr :std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
signal Cdb_Flush :std_logic; --Flag indicating that current instruction is mispredicted or not
signal Cdb_RobTag :std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
signal Cdb_RobDepth :std_logic_vector(4 downto 0); --Depth of mispredicted branch from ROB Top
-- component declaration
component tomasulo_top
port (
Reset : in std_logic;
Clk : in std_logic;
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM: out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic; -- for using the test mode
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component cfc is
port ( --global signals
Clk :in std_logic; --Global Clock Signal
Resetb :in std_logic; --Global Reset Signal
--interface with dispatch unit
Dis_InstValid :in std_logic; --Flag indicating if the instruction dispatched is valid or not
Dis_CfcBranchTag :in std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
Dis_CfcRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address
Dis_CfcRsAddr :in std_logic_vector(4 downto 0); --Rs Logical Address
Dis_CfcRtAddr :in std_logic_vector(4 downto 0); --Rt Logical Address
Dis_CfcNewRdPhyAddr :in std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
Dis_CfcRegWrite :in std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
Dis_CfcBranch :in std_logic; --Flag indicating whether current instruction being dispatched is branch or not
Dis_Jr31Inst :in std_logic; --Flag indicating if the current instruction is Jr 31 or not
Cfc_RdPhyAddr :out std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
Cfc_RsPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
Cfc_RtPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
Cfc_Full :out std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
Rob_TopPtr :in std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
Rob_Commit :in std_logic; --Flag indicating whether instruction is committing in this cycle or not
Rob_CommitRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
Rob_CommitRegWrite :in std_logic; --Indicates if instruction is writing to register or not
Rob_CommitCurrPhyAddr :in std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag :out std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
Frl_HeadPtr :in std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
Cfc_FrlHeadPtr :out std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cdb_RobTag :in std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
Cdb_RobDepth :in std_logic_vector(4 downto 0) --Depth of mispredicted branch from ROB Top
);
end component;
for CFC_UUT: cfc use entity work.cfc(cfc_arch);
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM=> Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start=> Walking_Led
);
CFC_UUT : cfc
port map( --global signals
Clk =>Clk,
Resetb =>Resetb,
--interface with dispatch unit
Dis_CfcBranchTag =>Dis_CfcBranchTag,
Dis_CfcRdAddr =>Dis_CfcRdAddr,
Dis_CfcRsAddr =>Dis_CfcRsAddr,
Dis_CfcRtAddr =>Dis_CfcRtAddr,
Dis_CfcNewRdPhyAddr =>Dis_CfcNewRdPhyAddr,
Dis_CfcRegWrite =>Dis_CfcRegWrite,
Dis_CfcBranch =>Dis_CfcBranch,
Dis_InstValid =>Dis_CfcInstValid,
Dis_Jr31Inst =>Dis_RasJr31Inst,
Cfc_RdPhyAddr =>Cfc_RdPhyAddr,
Cfc_RsPhyAddr =>Cfc_RsPhyAddr,
Cfc_RtPhyAddr =>Cfc_RtPhyAddr,
Cfc_Full =>Cfc_Full,
--interface with ROB
Rob_TopPtr =>Rob_TopPtr,
Rob_Commit =>Rob_Commit,
Rob_CommitRdAddr =>Rob_CommitRdAddr,
Rob_CommitRegWrite =>Rob_CommitRegWrite,
Rob_CommitCurrPhyAddr =>Rob_CommitCurrPhyAddr,
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag =>Cfc_RobTag,
--interface with PHP
Frl_HeadPtr =>Frl_HeadPtr,
Cfc_FrlHeadPtr =>Cfc_FrlHeadPtr,
--interface with CDB
Cdb_Flush =>Cdb_Flush,
Cdb_RobTag =>Cdb_RobTag,
Cdb_RobDepth =>Cdb_RobDepth
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of Branch Prediction Buffer only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open write_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
--if (Bpb_BranchPrediction_gold /= Bpb_BranchPrediction) then
-- write (my_outline, string'("ERROR! Bpb_BranchPrediction of TEST does not match Bpb_BranchPrediction_gold at clock_count = " & integer'image(Clk_Count)));
-- writeline (my_outfile, my_outline);
--end if;
if ( Cfc_RdPhyAddr/= Cfc_RdPhyAddr_gold) then
write (my_outline, string'("ERROR! Cfc_RdPhyAddr of TEST does not match Cfc_RdPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if ( Cfc_RsPhyAddr/= Cfc_RsPhyAddr_gold) then
write (my_outline, string'("ERROR! Cfc_RsPhyAddr of TEST does not match Cfc_RsPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if ( Cfc_RtPhyAddr /= Cfc_RtPhyAddr_gold ) then
write (my_outline, string'("ERROR! Cfc_RtPhyAddr of TEST does not match Cfc_RtPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if ( Cfc_FrlHeadPtr /= Cfc_FrlHeadPtr_gold) then
write (my_outline, string'("ERROR! Cfc_FrlHeadPtr of TEST does not match Cfc_FrlHeadPtr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if ( Cfc_RobTag /= Cfc_RobTag_gold ) then
write (my_outline, string'("ERROR! Cfc_RobTag of TEST does not match Cfc_RobTag_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if ( Cfc_Full /= Cfc_Full_gold) then
write (my_outline, string'("ERROR! Cfc_Full of TEST does not match Cfc_Full_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/Resetb","Resetb",1,1);
-- enable_signal_spy("/UUT/Resetb","Resetb",0);
init_signal_spy("/UUT/Dis_CfcInstValid","Dis_CfcInstValid",1,1);
init_signal_spy("/UUT/Dis_CfcBranchTag","Dis_CfcBranchTag",1,1);
init_signal_spy("/UUT/Dis_CfcRdAddr","Dis_CfcRdAddr",1,1);
init_signal_spy("/UUT/Dis_CfcRsAddr","Dis_CfcRsAddr",1,1);
init_signal_spy("/UUT/Dis_CfcRtAddr","Dis_CfcRtAddr",1,1);
init_signal_spy("/UUT/Dis_CfcNewRdPhyAddr","Dis_CfcNewRdPhyAddr",1,1);
init_signal_spy("/UUT/Dis_CfcRegWrite","Dis_CfcRegWrite",1,1);
init_signal_spy("/UUT/Dis_CfcBranch","Dis_CfcBranch",1,1);
init_signal_spy("/UUT/Dis_RasJr31Inst","Dis_RasJr31Inst",1,1);
init_signal_spy("/UUT/Rob_TopPtr","Rob_TopPtr",1,1);
init_signal_spy("/UUT/Rob_Commit","Rob_Commit",1,1);
init_signal_spy("/UUT/Rob_CommitRdAddr","Rob_CommitRdAddr",1,1);
init_signal_spy("/UUT/Rob_CommitRegWrite","Rob_CommitRegWrite",1,1);
init_signal_spy("/UUT/Rob_CommitCurrPhyAddr","Rob_CommitCurrPhyAddr",1,1);
init_signal_spy("/UUT/Frl_HeadPtr","Frl_HeadPtr",1,1);
init_signal_spy("/UUT/Cdb_Flush","Cdb_Flush",1,1);
init_signal_spy("/UUT/Cdb_RobTag","Cdb_RobTag",1,1);
init_signal_spy("/UUT/Cdb_RobDepth","Cdb_RobDepth",1,1);
--outputs--
init_signal_spy("/UUT/Cfc_RdPhyAddr","Cfc_RdPhyAddr_gold",1,1);
init_signal_spy("/UUT/Cfc_RsPhyAddr","Cfc_RsPhyAddr_gold",1,1);
init_signal_spy("/UUT/Cfc_RtPhyAddr","Cfc_RtPhyAddr_gold",1,1);
init_signal_spy("/UUT/Cfc_FrlHeadPtr","Cfc_FrlHeadPtr_gold",1,1);
init_signal_spy("/UUT/Cfc_RobTag","Cfc_RobTag_gold",1,1);
init_signal_spy("/UUT/Cfc_Full","Cfc_Full_gold",1,1);
-- init_signal_spy("/UUT/Bpb_BranchPrediction","Bpb_BranchPrediction_gold",1,1);
-- enable_signal_spy("/UUT/Bpb_BranchPrediction","Bpb_BranchPrediction_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_ROB;
|
gpl-2.0
|
b90a5eaa86fe3040825d5d0bc4d08876
| 0.6197 | 3.734033 | false | true | false | false |
lenchv/fpga-lab.node.js
|
vhdl/fifo.vhd
| 1 | 2,320 |
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity fifo is
Generic (
constant FIFO_DEPTH : positive := 256;
constant DATA_WIDTH : positive := 8
);
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
WriteEn : in STD_LOGIC;
DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
ReadEn : in STD_LOGIC;
DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
Empty : out STD_LOGIC;
Full : out STD_LOGIC
);
end fifo;
architecture Behavioral of fifo is
begin
-- Memory Pointer Process
fifo_proc : process (CLK)
type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
variable Memory : FIFO_Memory;
variable Head : natural range 0 to FIFO_DEPTH - 1 := 0;
variable Tail : natural range 0 to FIFO_DEPTH - 1 := 0;
variable Looped : boolean;
begin
if rising_edge(CLK) then
if RST = '1' then
Head := 0;
Tail := 0;
Looped := false;
Full <= '0';
Empty <= '1';
else
if (ReadEn = '1') then
if ((Looped = true) or (Head /= Tail)) then
-- Update data output
DataOut <= Memory(Tail);
-- Update Tail pointer as needed
if (Tail = FIFO_DEPTH - 1) then
Tail := 0;
Looped := false;
else
Tail := Tail + 1;
end if;
end if;
end if;
if (WriteEn = '1') then
if ((Looped = false) or (Head /= Tail)) then
-- Write Data to Memory
Memory(Head) := DataIn;
-- Increment Head pointer as needed
if (Head = FIFO_DEPTH - 1) then
Head := 0;
Looped := true;
else
Head := Head + 1;
end if;
end if;
end if;
-- Update Empty and Full flags
if (Head = Tail) then
if Looped then
Full <= '1';
else
Empty <= '1';
end if;
else
Empty <= '0';
Full <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
0f877c89a9db02f45bf3d236fee8da9b
| 0.468103 | 4.195298 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_memory_disambiguation_RAW.vhd
| 3 | 6,218 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"8D0C0000_8D020004_ACE20000_0102381B", -- Loc 0C, 08, 04, 00
X"00000020_00000020_00000020_00000020", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Sukhun Kang
-- Modified: 07-25-2009
--
--
-- 0102381B -- div $7, $8, $2 -- $7 gets q=4, r=0
-- ACE20000 -- SW $2, 0($7) -- mem(1) gets 2
-- 8D020004 -- lw $2, 4($8) -- $2 gets mem(3) = 30H
-- 8D0C0000 -- lw $12, 0($8) -- $12 gets mem(2) = 20H
--
----------------------------------------------
|
gpl-2.0
|
d8babbfd4f56ed88458dc2833c6334d0
| 0.662753 | 2.989423 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/read_data_fifo/simulation/fg_tb_synth.vhd
| 2 | 11,498 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 13,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : read_data_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
050462e8ca0dd9c7e31b9fdfd739f038
| 0.45634 | 3.958003 | false | false | false | false |
chronos38/DSD-Projekt
|
Testbench/tb_ioctrl.vhd
| 1 | 2,499 |
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_ioctrl is
end entity tb_ioctrl;
architecture sim of tb_ioctrl is
component ioctrl
port (
clk50 : in std_logic; -- Takt
reset_n : in std_logic; -- Asynchroner Reset
sw_i : in std_logic_vector(9 downto 0); -- Schalter Eingang
pb_i : in std_logic_vector(1 downto 0); -- Button Eingang
cntr0 : in std_logic_vector(3 downto 0); -- Counter 0
cntr1 : in std_logic_vector(3 downto 0); -- Counter 1
cntr2 : in std_logic_vector(3 downto 0); -- Counter 2
cntr3 : in std_logic_vector(3 downto 0); -- Counter 3
ss0_o : out std_logic_vector(7 downto 0); -- Display 0
ss1_o : out std_logic_vector(7 downto 0); -- Display 1
ss2_o : out std_logic_vector(7 downto 0); -- Display 2
ss3_o : out std_logic_vector(7 downto 0); -- Display 3
swsync_o : out std_logic_vector(9 downto 0); -- Synchronisierter Schalter
pbsync_o : out std_logic_vector(1 downto 0)); -- Synchronisierter Button
end component;
signal s_clk50, s_reset_n : std_logic := '0';
signal s_sw_i, s_swsync_o : std_logic_vector(9 downto 0) := "0000000000";
signal s_pb_i : std_logic_vector(1 downto 0) := "00";
signal s_cntr0, s_cntr1,
s_cntr2, s_cntr3 : std_logic_vector(3 downto 0) := x"0";
signal s_ss0_o, s_ss1_o,
s_ss2_o, s_ss3_o : std_logic_vector(7 downto 0) := x"00";
signal s_pb_sync_o : std_logic_vector(1 downto 0) := "00";
begin
i_ioctrl : ioctrl
port map (
clk50 => s_clk50,
reset_n => s_reset_n,
sw_i => s_sw_i,
pb_i => s_pb_i,
cntr0 => s_cntr0,
cntr1 => s_cntr1,
cntr2 => s_cntr2,
cntr3 => s_cntr3,
ss0_o => s_ss0_o,
ss1_o => s_ss1_o,
ss2_o => s_ss2_o,
ss3_o => s_ss3_o,
swsync_o => s_swsync_o,
pbsync_o => s_pb_sync_o
);
s_clk50 <= not s_clk50 after 20 ps;
p_test : process
begin
s_reset_n <= '0';
wait for 10 ns;
s_reset_n <= '1';
wait for 10 ns;
s_sw_i <= "1111111111";
wait for 100 ns;
s_sw_i <= "0000000000";
wait for 10 ns;
s_pb_i <= "11";
wait for 100 ns;
s_pb_i <= "00";
wait for 100 ns;
end process;
end sim;
|
gpl-3.0
|
1fa55c8ed1fa922926ea027dc06c1302
| 0.509404 | 3.047561 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_send_fifo/simulation/fg_tb_top.vhd
| 6 | 6,307 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
262825f3e99402737dc2550b3677352a
| 0.609006 | 4.10612 | false | false | false | false |
gxliu/ARM-Cortex-M0
|
hdl/shift.vhd
| 1 | 2,435 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity shift is
port ( mode : in std_logic_vector (1 downto 0);--0:LSLS 1:LSRS 2:ASRS 3:RORS
shift : in std_logic_vector (4 downto 0);
input : in std_logic_vector (31 downto 0);
carry : out std_logic;
output : out std_logic_vector (31 downto 0));
end shift;
architecture Behavioral of shift is
signal R1s : std_logic_vector(31 downto 0);
signal R2s : std_logic_vector(31 downto 0);
signal R4s : std_logic_vector(31 downto 0);
signal R8s : std_logic_vector(31 downto 0);
signal R16s : std_logic_vector(31 downto 0);
signal R1 : std_logic_vector(31 downto 0);
signal R2 : std_logic_vector(31 downto 0);
signal R4 : std_logic_vector(31 downto 0);
signal R8 : std_logic_vector(31 downto 0);
signal R16 : std_logic_vector(31 downto 0);
signal input1s : std_logic;
signal input2s : std_logic_vector(1 downto 0);
signal input4s : std_logic_vector(3 downto 0);
signal input8s : std_logic_vector(7 downto 0);
signal input16s : std_logic_vector(15 downto 0);
begin
carry <= '0' when shift = "0000" else '1';
--input(32 - conv_integer(shift)) when mode = "00" else
--input(conv_integer(shift) - 1);
input1s <= input(31) when mode = "10" else
input(0) when mode = "11" else
'0';
R1s <= input(30 downto 0) & input1s when mode = "00" else
input1s & input(31 downto 1);
input2s <= R1(1 downto 0) when mode = "11" else input1s & input1s;
R2s <= R1(29 downto 0) & input2s when mode = "00" else
input2s & R1(31 downto 2);
input4s <= R2(3 downto 0) when mode = "11" else input2s & input2s;
R4s <= R2(27 downto 0) & input4s when mode = "00" else
input4s & R2(31 downto 4);
input8s <= R4(7 downto 0) when mode = "11" else input4s & input4s;
R8s <= R4(23 downto 0) & input8s when mode = "00" else
input8s & R4(31 downto 8);
input16s <= R8(15 downto 0) when mode = "11" else input8s & input8s;
R16s <= R8(15 downto 0) & input16s when mode = "00" else
input16s & R8(31 downto 16);
R1 <= input when shift(0) = '0' else R1s;
R2 <= R1 when shift(1) = '0' else R2s;
R4 <= R2 when shift(2) = '0' else R4s;
R8 <= R4 when shift(3) = '0' else R8s;
output <= R8 when shift(4) = '0' else R16s;
end Behavioral;
|
mit
|
6a32fe0b8dddb7ae232b7198c58036e6
| 0.613963 | 2.857981 | false | false | false | false |
BBN-Q/APS2-TDM
|
testbenches/UDP_tb.vhd
| 1 | 26,736 |
-- Test bench for read/writes via UDP ethernet frames
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.EthernetFrame.all;
use work.IPv4Header.all;
entity UDP_tb is
generic (
SIM_SEQ_FILE : string := "";
APS_REPO_PATH : string := ""
);
end UDP_tb;
architecture Behavioral of UDP_tb is
component Memory is
port (
AXI_resetn : out STD_LOGIC_VECTOR ( 0 to 0 );
clk_axi : in STD_LOGIC;
clk_axi_locked : in STD_LOGIC;
ethernet_mm2s_err : out STD_LOGIC;
ethernet_s2mm_err : out STD_LOGIC;
reset : in STD_LOGIC;
ethernet_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
ethernet_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
ethernet_mm2s_tlast : out STD_LOGIC;
ethernet_mm2s_tready : in STD_LOGIC;
ethernet_mm2s_tvalid : out STD_LOGIC;
ethernet_mm2s_sts_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
ethernet_mm2s_sts_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
ethernet_mm2s_sts_tlast : out STD_LOGIC;
ethernet_mm2s_sts_tready : in STD_LOGIC;
ethernet_mm2s_sts_tvalid : out STD_LOGIC;
ethernet_s2mm_sts_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
ethernet_s2mm_sts_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
ethernet_s2mm_sts_tlast : out STD_LOGIC;
ethernet_s2mm_sts_tready : in STD_LOGIC;
ethernet_s2mm_sts_tvalid : out STD_LOGIC;
ethernet_mm2s_cmd_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
ethernet_mm2s_cmd_tready : out STD_LOGIC;
ethernet_mm2s_cmd_tvalid : in STD_LOGIC;
ethernet_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
ethernet_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
ethernet_s2mm_tlast : in STD_LOGIC;
ethernet_s2mm_tready : out STD_LOGIC;
ethernet_s2mm_tvalid : in STD_LOGIC;
ethernet_s2mm_cmd_tdata : in STD_LOGIC_VECTOR ( 71 downto 0 );
ethernet_s2mm_cmd_tready : out STD_LOGIC;
ethernet_s2mm_cmd_tvalid : in STD_LOGIC;
CSR_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
CSR_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
CSR_awvalid : out STD_LOGIC;
CSR_awready : in STD_LOGIC;
CSR_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
CSR_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
CSR_wvalid : out STD_LOGIC;
CSR_wready : in STD_LOGIC;
CSR_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
CSR_bvalid : in STD_LOGIC;
CSR_bready : out STD_LOGIC;
CSR_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
CSR_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
CSR_arvalid : out STD_LOGIC;
CSR_arready : in STD_LOGIC;
CSR_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
CSR_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
CSR_rvalid : in STD_LOGIC;
CSR_rready : out STD_LOGIC
);
end component Memory;
--Clocks and resets
constant USER_CLK_PERIOD : time := 10 ns;
constant MAC_CLK_PERIOD : time := 8 ns;
constant SYS_CLK_PERIOD : time := 3.33333333333333333 ns;
constant CFG_CLK_PERIOD : time := 10.1 ns;
signal SYS_CLK : std_logic := '0';
signal USER_CLK : std_logic := '0';
signal CFG_CLK : std_logic := '0';
signal MAC_CLK : std_logic := '0';
signal USER_RST : std_logic := '0';
signal RESET : std_logic := '0';
--Interposing MAC signals between the Xilinx trimac and the APSMsgProc
signal MAC_RXD_trimac : std_logic_vector(7 downto 0) := (others => '0');
signal MAC_RX_VALID_trimac : std_logic := '0';
signal MAC_RX_EOP_trimac : std_logic := '0';
signal MAC_BAD_FCS_trimac : std_logic := '0';
signal MAC_TXD_trimac : std_logic_vector(7 downto 0) := (others => '0');
signal MAC_TX_RDY_trimac : std_logic := '0';
signal MAC_TX_VALID_trimac : std_logic := '0';
signal MAC_TX_EOP_trimac : std_logic := '0';
signal MAC_RXD_msgproc : std_logic_vector(7 downto 0) := (others => '0');
signal MAC_RX_VALID_msgproc : std_logic := '0';
signal MAC_RX_EOP_msgproc : std_logic := '0';
signal MAC_BAD_FCS_msgproc : std_logic := '0';
signal MAC_TXD_msgproc : std_logic_vector(7 downto 0) := (others => '0');
signal MAC_TX_RDY_msgproc : std_logic := '0';
signal MAC_TX_VALID_msgproc : std_logic := '0';
signal MAC_TX_EOP_msgproc : std_logic := '0';
--APSMsgProc user signals
signal USER_STATUS : std_logic_vector(31 downto 0) := (others => '0');
signal USER_DIF : std_logic_vector(31 downto 0) := (others => '0');
signal USER_DIF_RD : std_logic := '0';
signal USER_CIF_EMPTY : std_logic := '0';
signal USER_CIF_RD : std_logic := '0';
signal USER_CIF_RW : std_logic := '0';
signal USER_CIF_MODE : std_logic_vector(7 downto 0) := (others => '0');
signal USER_CIF_CNT : std_logic_vector(15 downto 0) := (others => '0');
signal USER_CIF_ADDR : std_logic_vector(31 downto 0) := (others => '0');
signal USER_DOF : std_logic_vector(31 downto 0) := (others => '0');
signal USER_DOF_WR : std_logic := '0';
signal USER_COF_STAT : std_logic_vector(7 downto 0) := (others => '0');
signal USER_COF_CNT : std_logic_vector(15 downto 0) := (others => '0');
signal USER_COF_AFULL : std_logic := '0';
signal USER_COF_WR : std_logic := '0';
signal GoodToggle, BadToggle : std_logic := '0';
--CSR AXI Lite
signal CSR_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal CSR_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal CSR_arready : STD_LOGIC;
signal CSR_arvalid : STD_LOGIC;
signal CSR_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal CSR_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal CSR_awready : STD_LOGIC;
signal CSR_awvalid : STD_LOGIC;
signal CSR_bready : STD_LOGIC;
signal CSR_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal CSR_bvalid : STD_LOGIC;
signal CSR_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal CSR_rready : STD_LOGIC;
signal CSR_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal CSR_rvalid : STD_LOGIC;
signal CSR_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal CSR_wready : STD_LOGIC;
signal CSR_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal CSR_wvalid : STD_LOGIC;
--Ethernet DataMover command and status
signal ethernet_mm2s_tdata : std_logic_vector ( 31 downto 0 ) := (others => '0');
signal ethernet_mm2s_tkeep : std_logic_vector ( 3 downto 0 ) := (others => '0');
signal ethernet_mm2s_tlast : std_logic := '0';
signal ethernet_mm2s_tready : std_logic := '0';
signal ethernet_mm2s_tvalid : std_logic := '0';
signal ethernet_s2mm_tdata : std_logic_vector ( 31 downto 0 ) := (others => '0');
signal ethernet_s2mm_tkeep : std_logic_vector ( 3 downto 0 ) := (others => '1'); -- assuming 32bit words
signal ethernet_s2mm_tlast : std_logic := '0';
signal ethernet_s2mm_tvalid : std_logic := '0';
signal ethernet_s2mm_tready : std_logic := '0';
signal ethernet_s2mm_sts_tdata : std_logic_vector ( 7 downto 0 ) := (others => '0');
signal ethernet_s2mm_sts_tkeep : std_logic_vector ( 0 to 0 );
signal ethernet_s2mm_sts_tlast : std_logic := '0';
signal ethernet_s2mm_sts_tready : std_logic := '0';
signal ethernet_s2mm_sts_tvalid : std_logic := '0';
signal ethernet_mm2s_sts_tdata : std_logic_vector ( 7 downto 0 ) := (others => '0');
signal ethernet_mm2s_sts_tkeep : std_logic_vector ( 0 to 0 );
signal ethernet_mm2s_sts_tlast : std_logic := '0';
signal ethernet_mm2s_sts_tready : std_logic := '0';
signal ethernet_mm2s_sts_tvalid : std_logic := '0';
signal ethernet_s2mm_cmd_tdata : std_logic_vector ( 71 downto 0 ) := (others => '0');
signal ethernet_s2mm_cmd_tready : std_logic := '0';
signal ethernet_s2mm_cmd_tvalid : std_logic := '0';
signal ethernet_mm2s_cmd_tdata : std_logic_vector ( 71 downto 0 ) := (others => '0');
signal ethernet_mm2s_cmd_tready : std_logic := '0';
signal ethernet_mm2s_cmd_tvalid : std_logic := '0';
signal ethernet_s2mm_err : std_logic := '0';
signal ethernet_mm2s_err : std_logic := '0';
--Status register responses
signal HOST_FIRMWARE_VER, USER_FIRMWARE_VER : std_logic_vector(31 downto 0) := (others => '0');
signal CONFIG_SOURCE : std_logic_vector(31 downto 0) := (others => '0');
signal USER_STATUS_RESPONSE, DAC0_STATUS, DAC1_STATUS, PLL_STATUS : std_logic_vector(31 downto 0) := (others => '0');
signal FPGA_TEMPERATURE : std_logic_vector(31 downto 0) := (others => '0');
signal SEND_PKT_COUNT, RECV_PKT_COUNT, SKIP_PKT_COUNT, DUP_PKT_COUNT, FCS_ERR_COUNT, OVERRUN_COUNT : natural := 0;
signal UPTIME_SEC, UPTIME_NSEC : natural := 0;
--CSR inputs/outputs
signal resets, controls : std_logic_vector(31 downto 0) ;
signal AXI_resetn : std_logic;
type TestbenchStates_t is (RESETTING, ARP_QUERY, STATUS_REQUEST, SINGLE_WORD_WRITE, SINGLE_WORD_READ,
WRONG_IP_PACKET, MULTI_WORD_WRITE, MULTI_WORD_READ, BAD_FRAME_TEST,
SEQUENCE_NUMBERING, CSR_WRITE, CSR_READ, WRITE_MULTIPLE_PACKETS, FINISHED);
signal testbenchState : TestbenchStates_t;
begin
--Clock processes
mac_clk_process :process
begin
MAC_CLK <= '0';
wait for MAC_CLK_PERIOD/2;
MAC_CLK <= '1';
wait for MAC_CLK_PERIOD/2;
end process;
user_clk_process :process
begin
USER_CLK <= '0';
wait for USER_CLK_PERIOD/2;
USER_CLK <= '1';
wait for USER_CLK_PERIOD/2;
end process;
cfg_clk_process :process
begin
CFG_CLK <= '0';
wait for CFG_CLK_PERIOD/2;
CFG_CLK <= '1';
wait for CFG_CLK_PERIOD/2;
end process;
sys_clk_process :process
begin
SYS_CLK <= '0';
wait for SYS_CLK_PERIOD/2;
SYS_CLK <= '1';
wait for SYS_CLK_PERIOD/2;
end process;
tx_rdy : process( MAC_CLK )
begin
if rising_edge(MAC_CLK) then
if MAC_TX_VALID_trimac = '1' then
MAC_TX_RDY_trimac <= '1';
else
MAC_TX_RDY_trimac <= '0';
end if;
end if ;
end process ; -- tx_rdy
-- Stimulus process
stim_proc: process
variable srcMAC, destMAC : MACAddr_t := (others => (others => '0'));
variable myCommand : APSCommand_t := (ack => '0', seq => '0', sel => '0', rw => '0', cmd => (others => '0'), mode => (others => '0'), cnt => x"0000");
variable myFrameHeader : APSEthernetFrameHeader_t;
variable myIPHeader : IPv4Header_t;
variable myUDPHeader : UDPHeader_t;
variable emptyPayload : APSPayload_t(0 to -1);
variable testData1 : APSPayload_t(0 to 3);
variable testData2 : APSPayload_t(0 to 255);
variable testData3 : APSPayload_t(0 to 1023);
variable byteCount : natural := 0;
--Procedure to read status registers off of returning MAC byte stream
procedure update_status_registers is
variable tmpWord : std_logic_vector(31 downto 0) ;
procedure byte2word is
begin
for ct in 4 downto 1 loop
wait until rising_edge(MAC_CLK);
tmpWord(ct*8 - 1 downto (ct-1)*8) := MAC_TXD_trimac;
end loop;
end procedure byte2word ;
begin
--Read through the header bytes
byteCount := 0;
while ( byteCount < (14+20+8+16+4)) loop
wait until rising_edge(MAC_CLK);
if MAC_TX_VALID_trimac = '1' and MAC_TX_RDY_trimac = '1' then
byteCount := byteCount+1;
end if;
end loop;
--Now clock through the status words
byte2word; HOST_FIRMWARE_VER <= tmpWord;
byte2word; USER_FIRMWARE_VER <= tmpWord;
byte2word; CONFIG_SOURCE <= tmpWord;
byte2word; USER_STATUS_RESPONSE <= tmpWord;
byte2word; DAC0_STATUS <= tmpWord;
byte2word; DAC1_STATUS <= tmpWord;
byte2word; PLL_STATUS <= tmpWord;
byte2word; FPGA_TEMPERATURE <= tmpWord;
byte2word; SEND_PKT_COUNT <= to_integer(unsigned(tmpWord));
byte2word; RECV_PKT_COUNT <= to_integer(unsigned(tmpWord));
byte2word; SKIP_PKT_COUNT <= to_integer(unsigned(tmpWord));
byte2word; DUP_PKT_COUNT <= to_integer(unsigned(tmpWord));
byte2word; FCS_ERR_COUNT <= to_integer(unsigned(tmpWord));
byte2word; OVERRUN_COUNT <= to_integer(unsigned(tmpWord));
byte2word; UPTIME_SEC <= to_integer(unsigned(tmpWord));
byte2word; UPTIME_NSEC <= to_integer(unsigned(tmpWord));
end procedure update_status_registers;
--Procedure to check read data
procedure check_read_data(testArray : in APSPayload_t) is
variable allGood : boolean := true ;
begin
--Read through the header bytes
byteCount := 0;
while ( byteCount < (14+20+8+16+4)) loop
wait until rising_edge(MAC_CLK);
if MAC_TX_VALID_trimac = '1' and MAC_TX_RDY_trimac = '1' then
byteCount := byteCount+1;
end if;
end loop;
--Now clock through the data and check every byte
for ct in testArray'range loop
wait until rising_edge(MAC_CLK);
assert testArray(ct) = MAC_TXD_trimac report "Read data did not match expected!";
end loop;
end procedure check_read_data;
--Wrapper procedure to clock in a complete Etherent frame using the above variables
procedure write_complete_frame(payLoad : in APSPayload_t; seqNum : in natural := 0; badFCS : in boolean := false) is
begin
MAC_RX_VALID_trimac <= '1';
write_ethernet_frame_header(destMAC, srcMAC, x"0800", MAC_RXD_trimac, MAC_CLK);
write_IPv4Header(myIPHeader, MAC_RXD_trimac, MAC_CLK);
write_UDPHeader(myUDPHeader, MAC_RXD_trimac, MAC_CLK);
write_APSEthernet_frame(myFrameHeader, payLoad, MAC_RXD_trimac, MAC_CLK, MAC_RX_VALID_trimac,
MAC_RX_EOP_trimac, seqNum, badFCS, MAC_BAD_FCS_trimac);
end procedure write_complete_frame;
begin
testbenchState <= RESETTING;
wait for 100ns;
RESET <= '1';
wait for 200ns;
RESET <= '0';
wait for 100ns;
wait until rising_edge(MAC_CLK);
srcMAC := (x"BA", x"AD", x"BA", x"AD", x"BA", x"AD");
destMAC := (x"FF", x"FF", x"FF", x"FF", x"FF", x"FF");
wait until rising_edge(MAC_CLK);
----------------------------------------------------------------------------------------------
testbenchState <= ARP_QUERY;
--ARP request who has 192.168.5.9? Tell 192.168.5.1";
MAC_RX_VALID_trimac <= '1';
write_ethernet_frame_header(destMAC, srcMAC, x"0806", MAC_RXD_trimac, MAC_CLK);
-- HW type
MAC_RXD_trimac <= x"00"; wait until rising_edge(MAC_CLK);
MAC_RXD_trimac <= x"01"; wait until rising_edge(MAC_CLK);
-- Protocol type
MAC_RXD_trimac <= x"08"; wait until rising_edge(MAC_CLK);
MAC_RXD_trimac <= x"00"; wait until rising_edge(MAC_CLK);
-- HW size
MAC_RXD_trimac <= x"06"; wait until rising_edge(MAC_CLK);
-- protocol size
MAC_RXD_trimac <= x"04"; wait until rising_edge(MAC_CLK);
-- Opcode
MAC_RXD_trimac <= x"00"; wait until rising_edge(MAC_CLK);
MAC_RXD_trimac <= x"01"; wait until rising_edge(MAC_CLK);
-- Sender MAC
write_MAC_addr(srcMAC, MAC_RXD_trimac, MAC_CLK);
-- Sender IP
write_IPv4_addr((x"c0", x"a8", x"05", x"01"), MAC_RXD_trimac, MAC_CLK);
-- Target MAC
write_MAC_addr((x"00", x"00", x"00", x"00", x"00", x"00"), MAC_RXD_trimac, MAC_CLK);
-- Target IP
write_IPv4_addr((x"c0", x"a8", x"05", x"09"), MAC_RXD_trimac, MAC_CLK);
--Bonus zeros
MAC_RXD_trimac <= x"00"; wait until rising_edge(MAC_CLK);
MAC_RXD_trimac <= x"00"; wait until rising_edge(MAC_CLK);
MAC_RXD_trimac <= x"00"; wait until rising_edge(MAC_CLK);
MAC_RX_VALID_trimac <= '0';
MAC_RXD_trimac <= x"00"; wait until rising_edge(MAC_CLK);
for ct in 1 to 4 loop
wait until rising_edge(MAC_CLK);
end loop;
MAC_RX_EOP_trimac <= '1';
MAC_RX_VALID_trimac <= '1';
wait until rising_edge(MAC_CLK);
MAC_RX_EOP_trimac <= '0';
MAC_RX_VALID_trimac <= '0';
wait until rising_edge(MAC_CLK);
--Wait for ARP response to come back
--TODO: error check
wait until rising_edge(MAC_TX_EOP_trimac);
wait until rising_edge(MAC_CLK);
------------------------------------------------------------------------------------
-- Clock in a enumerating UDP status request
testbenchState <= STATUS_REQUEST;
--Update MAC address for specific test instrument
destMAC := (x"00", x"11", x"22", x"33", x"44", x"55");
--Setup IPv4 and UDP header entries
myIPHeader.srcIP := (x"c0", x"a8", x"05", x"01");
myIPHeader.destIP := (x"c0", x"a8", x"05", x"09");
--20 bytes ipv4 + 8 bytes UDP + 14 bytes APSEthernet fake Ethernet frame + 10 bytes aps seq. num, command and addr
myIPHeader.totalLength := 20+8+14+10;
myIPHeader.protocol := x"11";
myUDPHeader.srcPort := 47950;
myUDPHeader.destPort := 47950;
myUDPHeader.totalLength := 8+14+10;
-- user data is APSEthernetFrame
myFrameHeader.destMAC := (x"FF", x"FF", x"FF", x"FF", x"FF", x"FF");
myFrameHeader.srcMAC := (x"BA", x"AD", x"BA", x"AD", x"BA", x"AD");
myFrameHeader.command := myCommand;
myFrameHeader.command.rw := '1';
myFrameHeader.command.cmd := x"7";
myFrameHeader.addr := (others => '0');
write_complete_frame(emptyPayload);
--APSMsgProc will send back status registers
update_status_registers;
--Error checking after one clock cycle to catch last register updates
wait until rising_edge(MAC_CLK);
assert (HOST_FIRMWARE_VER = x"00000a01") report "Status registers: HOST_FIRMWARE_VER incorrect";
assert (USER_FIRMWARE_VER = x"00000212") report "Status registers: USER_FIRMWARE_VER incorrect";
assert (CONFIG_SOURCE = x"bbbbbbbb") report "Status registers: CONFIG_SOURCE incorrect";
assert (SEND_PKT_COUNT = 0) report "Status registers: SEND_PKT_COUNT incorrect";
assert (RECV_PKT_COUNT = 1) report "Status registers: RECV_PKT_COUNT incorrect";
assert (FCS_ERR_COUNT = 0) report "Status registers: FCS_ERR_COUNT incorrect";
assert (UPTIME_SEC = 0) report "Status registers: UPTIME_SEC incorrect";
assert (UPTIME_NSEC = 1536) report "Status registers: UPTIME_NSEC incorrect";
---------------------------------------------------------------------------------------------------------
-- Clock in a control word write to controls
testbenchState <= CSR_WRITE;
--Fix-up headers
myFrameHeader.command.rw := '0';
myFrameHeader.command.cmd := x"9";
myFrameHeader.command.cnt := std_logic_vector( to_unsigned(1, 16));
myFrameHeader.addr := x"44A00008";
testData1(0) := x"AB"; testData1(1) := x"CD"; testData1(2) := x"EF"; testData1(3) := x"FE";
myIPHeader.totalLength := 20+8+14+10+testData1'length;
myUDPHeader.totalLength := 8+14+10+testData1'length;
write_complete_frame(testData1);
--Check the data showed up on the register
wait until rising_edge(MAC_TX_EOP_trimac);
assert controls = x"ABCDEFFE" report "CSR control write failed.";
-------------------------------------------------------------------------------------------------
-- Ask for the dummy status
testbenchState <= CSR_READ;
--Fix-up headers
myFrameHeader.command.rw := '1';
myFrameHeader.command.cnt := std_logic_vector( to_unsigned(1, 16));
myFrameHeader.addr := x"44A00004";
myIPHeader.totalLength := 20+8+14+10;
myUDPHeader.totalLength := 8+14+10;
write_complete_frame(emptyPayload);
--Check the data is returned correctly
report "Checking read data for CSR read test.";
check_read_data((x"12", x"34", x"56", x"78"));
testbenchState <= FINISHED;
wait;
end process;
--Instantiate UDP interface
udp: entity work.UDP_Interface
port map (
MAC_CLK => MAC_CLK,
RST => RESET,
--real MAC signals to/from the TRIMAC
MAC_RXD_trimac => MAC_RXD_trimac,
MAC_RX_VALID_trimac => MAC_RX_VALID_trimac,
MAC_RX_EOP_trimac => MAC_RX_EOP_trimac,
MAC_BAD_FCS_trimac => MAC_BAD_FCS_trimac,
MAC_TXD_trimac => MAC_TXD_trimac,
MAC_TX_RDY_trimac => MAC_TX_RDY_trimac,
MAC_TX_VALID_trimac => MAC_TX_VALID_trimac,
MAC_TX_EOP_trimac => MAC_TX_EOP_trimac,
--fake MAC signals to/from the APSMsgProc
MAC_RXD_msgproc => MAC_RXD_msgproc,
MAC_RX_VALID_msgproc => MAC_RX_VALID_msgproc,
MAC_RX_EOP_msgproc => MAC_RX_EOP_msgproc,
MAC_BAD_FCS_msgproc => MAC_BAD_FCS_msgproc,
MAC_TXD_msgproc => MAC_TXD_msgproc,
MAC_TX_RDY_msgproc => MAC_TX_RDY_msgproc,
MAC_TX_VALID_msgproc => MAC_TX_VALID_msgproc,
MAC_TX_EOP_msgproc => MAC_TX_EOP_msgproc,
mac_addr => x"001122334455",
ip_addr => x"c0a80509"
);
--And the ZRL message processor
AMP1 : entity work.ApsMsgProc
port map
(
-- Interface to MAC to get Ethernet packets
MAC_CLK => MAC_CLK,
RESET => RESET,
MAC_RXD => MAC_RXD_msgproc,
MAC_RX_VALID => MAC_RX_VALID_msgproc,
MAC_RX_EOP => MAC_RX_EOP_msgproc,
MAC_BAD_FCS => MAC_BAD_FCS_msgproc,
MAC_TXD => MAC_TXD_msgproc,
MAC_TX_RDY => MAC_TX_RDY_msgproc,
MAC_TX_VALID => MAC_TX_VALID_msgproc,
MAC_TX_EOP => MAC_TX_EOP_msgproc,
-- User Logic Connections
USER_CLK => USER_CLK,
USER_RST => USER_RST,
USER_VERSION => x"12345678",
USER_STATUS => USER_STATUS,
USER_DIF => USER_DIF,
USER_DIF_RD => USER_DIF_RD,
USER_CIF_EMPTY => USER_CIF_EMPTY,
USER_CIF_RD => USER_CIF_RD,
USER_CIF_RW => USER_CIF_RW,
USER_CIF_MODE => USER_CIF_MODE,
USER_CIF_CNT => USER_CIF_CNT,
USER_CIF_ADDR => USER_CIF_ADDR,
USER_DOF => USER_DOF,
USER_DOF_WR => USER_DOF_WR,
USER_COF_STAT => USER_COF_STAT,
USER_COF_CNT => USER_COF_CNT,
USER_COF_AFULL => USER_COF_AFULL,
USER_COF_WR => USER_COF_WR,
-- Interface to Config CPLD
CFG_CLK => CFG_CLK,
CFGD_IN => x"AAAA", -- Temporary for Status command testing
CFGD_OUT => open , -- Eventually connected to CPLD
CFGD_OE => open , -- Eventually connected to CPLD
STAT_OE => open , -- Eventually connected to CPLD
-- Status to top level
GOOD_TOGGLE => GoodToggle,
BAD_TOGGLE => BadToggle
);
-- Instantiate the APSMsgProc - AXI bridge
AXIbridge : entity work.AXIBridge
port map (
RST => RESET,
-- User Logic Connections
USER_CLK => USER_CLK, -- Clock for User side of FIFO interface
USER_RST => USER_RST,
USER_DIF => USER_DIF, -- User Data Input FIFO output
USER_DIF_RD => USER_DIF_RD, -- User Data Onput FIFO Read Enable
USER_CIF_EMPTY => USER_CIF_EMPTY, -- Low when there is data available
USER_CIF_RD => USER_CIF_RD, -- Command Input FIFO Read Enable
USER_CIF_RW => USER_CIF_RW, -- High for read, low for write
USER_CIF_MODE => USER_CIF_MODE, -- MODE field from current User I/O command
USER_CIF_CNT => USER_CIF_CNT, -- CNT field from current User I/O command
USER_CIF_ADDR => USER_CIF_ADDR, -- Address for the current command
USER_DOF => USER_DOF, -- User Data Onput FIFO input
USER_DOF_WR => USER_DOF_WR, -- User Data Onput FIFO Write Enable
USER_COF_STAT => USER_COF_STAT, -- STAT value to return for current User I/O command
USER_COF_CNT => USER_COF_CNT, -- Number of words written to DOF for current User I/O command
USER_COF_AFULL => USER_COF_AFULL, -- User Control Output FIFO Almost Full
USER_COF_WR => USER_COF_WR, -- User Control Onput FIFO Write Enable
MM2S_STS_tdata => ethernet_mm2s_sts_tdata,
MM2S_STS_tkeep => ethernet_mm2s_sts_tkeep,
MM2S_STS_tlast => ethernet_mm2s_sts_tlast,
MM2S_STS_tready => ethernet_mm2s_sts_tready,
MM2S_STS_tvalid => ethernet_mm2s_sts_tvalid,
MM2S_tdata => ethernet_mm2s_tdata,
MM2S_tkeep => ethernet_mm2s_tkeep,
MM2S_tlast => ethernet_mm2s_tlast,
MM2S_tready => ethernet_mm2s_tready,
MM2S_tvalid => ethernet_mm2s_tvalid,
S2MM_STS_tdata => ethernet_s2mm_sts_tdata,
S2MM_STS_tkeep => ethernet_s2mm_sts_tkeep,
S2MM_STS_tlast => ethernet_s2mm_sts_tlast,
S2MM_STS_tready => ethernet_s2mm_sts_tready,
S2MM_STS_tvalid => ethernet_s2mm_sts_tvalid,
MM2S_CMD_tdata => ethernet_mm2s_cmd_tdata,
MM2S_CMD_tready => ethernet_mm2s_cmd_tready,
MM2S_CMD_tvalid => ethernet_mm2s_cmd_tvalid,
S2MM_CMD_tdata => ethernet_s2mm_cmd_tdata,
S2MM_CMD_tready => ethernet_s2mm_cmd_tready,
S2MM_CMD_tvalid => ethernet_s2mm_cmd_tvalid,
S2MM_tdata => ethernet_s2mm_tdata,
S2MM_tkeep => ethernet_s2mm_tkeep,
S2MM_tlast => ethernet_s2mm_tlast,
S2MM_tready => ethernet_s2mm_tready,
S2MM_tvalid => ethernet_s2mm_tvalid);
--Instantiate the memory BD
myMemory : Memory
port map (
reset => RESET,
clk_axi => USER_CLK,
clk_axi_locked => "not"(RESET),
AXI_resetn(0) => AXI_resetn,
------------------------------------------------------------------
-- CSR AXI
CSR_araddr => CSR_araddr,
CSR_arprot => CSR_arprot,
CSR_arready => CSR_arready,
CSR_arvalid => CSR_arvalid,
CSR_awaddr => CSR_awaddr,
CSR_awprot => CSR_awprot,
CSR_awready => CSR_awready,
CSR_awvalid => CSR_awvalid,
CSR_bready => CSR_bready,
CSR_bresp => CSR_bresp,
CSR_bvalid => CSR_bvalid,
CSR_rdata => CSR_rdata,
CSR_rready => CSR_rready,
CSR_rresp => CSR_rresp,
CSR_rvalid => CSR_rvalid,
CSR_wdata => CSR_wdata,
CSR_wready => CSR_wready,
CSR_wstrb => CSR_wstrb,
CSR_wvalid => CSR_wvalid,
------------------------------------------------------------------
--Ethernet DMA
ethernet_mm2s_tdata => ethernet_mm2s_tdata,
ethernet_mm2s_tkeep => ethernet_mm2s_tkeep,
ethernet_mm2s_tlast => ethernet_mm2s_tlast,
ethernet_mm2s_tready => ethernet_mm2s_tready,
ethernet_mm2s_tvalid => ethernet_mm2s_tvalid,
ethernet_s2mm_tdata => ethernet_s2mm_tdata,
ethernet_s2mm_tkeep => ethernet_s2mm_tkeep,
ethernet_s2mm_tlast => ethernet_s2mm_tlast,
ethernet_s2mm_tvalid => ethernet_s2mm_tvalid,
ethernet_s2mm_tready => ethernet_s2mm_tready,
ethernet_mm2s_sts_tdata => ethernet_mm2s_sts_tdata,
ethernet_mm2s_sts_tkeep => ethernet_mm2s_sts_tkeep,
ethernet_mm2s_sts_tlast => ethernet_mm2s_sts_tlast,
ethernet_mm2s_sts_tready => ethernet_mm2s_sts_tready,
ethernet_mm2s_sts_tvalid => ethernet_mm2s_sts_tvalid,
ethernet_s2mm_sts_tdata => ethernet_s2mm_sts_tdata,
ethernet_s2mm_sts_tkeep => ethernet_s2mm_sts_tkeep,
ethernet_s2mm_sts_tlast => ethernet_s2mm_sts_tlast,
ethernet_s2mm_sts_tready => ethernet_s2mm_sts_tready,
ethernet_s2mm_sts_tvalid => ethernet_s2mm_sts_tvalid,
ethernet_mm2s_cmd_tdata => ethernet_mm2s_cmd_tdata,
ethernet_mm2s_cmd_tready => ethernet_mm2s_cmd_tready,
ethernet_mm2s_cmd_tvalid => ethernet_mm2s_cmd_tvalid,
ethernet_s2mm_cmd_tdata => ethernet_s2mm_cmd_tdata,
ethernet_s2mm_cmd_tready => ethernet_s2mm_cmd_tready,
ethernet_s2mm_cmd_tvalid => ethernet_s2mm_cmd_tvalid,
ethernet_s2mm_err => ethernet_s2mm_err,
ethernet_mm2s_err => ethernet_mm2s_err
);
-- CSR
CSR : entity work.APS2_CSR
port map (
sys_clk => USER_CLK,
resets => resets,
controls => controls,
dummyStatus => x"12345678",
dummyStatus2 => x"87654321",
S_AXI_ACLK => USER_CLK,
S_AXI_ARESETN => AXI_resetn,
S_AXI_AWADDR => CSR_awaddr(7 downto 0),
S_AXI_AWPROT => CSR_awprot,
S_AXI_AWVALID => CSR_awvalid,
S_AXI_AWREADY => CSR_awready,
S_AXI_WDATA => CSR_wdata,
S_AXI_WSTRB => CSR_wstrb,
S_AXI_WVALID => CSR_wvalid,
S_AXI_WREADY => CSR_wready,
S_AXI_BRESP => CSR_bresp,
S_AXI_BVALID => CSR_bvalid,
S_AXI_BREADY => CSR_bready,
S_AXI_ARADDR => CSR_araddr(7 downto 0),
S_AXI_ARPROT => CSR_arprot,
S_AXI_ARVALID => CSR_arvalid,
S_AXI_ARREADY => CSR_arready,
S_AXI_RDATA => CSR_rdata,
S_AXI_RRESP => CSR_rresp,
S_AXI_RVALID => CSR_rvalid,
S_AXI_RREADY => CSR_rready
);
end Behavioral;
|
mpl-2.0
|
df7927e05d6d1e6e8967b8e2d9bb9226
| 0.648826 | 2.9319 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_command_send_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,598 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_command_send_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(4-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(4-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
0d6176245c53ad3f3cf04e9d54d7cec3
| 0.503104 | 3.920892 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/alu_r1.vhd
| 1 | 4,578 |
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;-- for slt and not sltu
------------------------------------------------------------------------------
-- New instructions introduced in the Design
-- JR $Rs, JR $31, Bne $rt, $rs, offset, Addi $rd, $rs, Immediate
-- Other instructions same as previous design
------------------------------------------------------------------------------
entity ALU is
generic (
tag_width : integer := 6
);
port (
PhyReg_AluRsData : in std_logic_vector(31 downto 0);
PhyReg_AluRtData : in std_logic_vector(31 downto 0);
Iss_OpcodeAlu : in std_logic_vector(2 downto 0);
Iss_RobTagAlu : in std_logic_vector(4 downto 0);
Iss_RdPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_BranchAddrAlu : in std_logic_vector(31 downto 0);
Iss_BranchAlu : in std_logic;
Iss_RegWriteAlu : in std_logic;
Iss_BranchUptAddrAlu : in std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : in std_logic;
Iss_JalInstAlu : in std_logic;
Iss_JrInstAlu : in std_logic;
Iss_JrRsInstAlu : in std_logic;
Iss_ImmediateAlu : in std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : in std_logic_vector(31 downto 0);
-- translate_on
Alu_RdData : out std_logic_vector(31 downto 0);
Alu_RdPhyAddr : out std_logic_vector(5 downto 0);
Alu_BranchAddr : out std_logic_vector(31 downto 0);
Alu_Branch : out std_logic;
Alu_BranchOutcome : out std_logic;
-- translate_off
Alu_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Alu_RobTag : out std_logic_vector(4 downto 0);
Alu_BranchUptAddr : out std_logic_vector( 2 downto 0 );
Alu_BranchPredict : out std_logic;
Alu_RdWrite : out std_logic;
Alu_JrFlush : out std_logic
);
end ALU;
architecture comput of ALU is
begin
Alu_RdPhyAddr <= Iss_RdPhyAddrAlu;
Alu_BranchPredict <= Iss_BranchPredictAlu;
Alu_BranchUptAddr <= Iss_BranchUptAddrAlu;
Alu_Branch <= Iss_BranchAlu;
Alu_RobTag <= Iss_RobTagAlu;
Alu_RdWrite <= Iss_RegWriteAlu;
-- translate_off
Alu_instruction <= Iss_instructionAlu;
-- translate_on
ALU_COMPUT: process (PhyReg_AluRtData, PhyReg_AluRsData, Iss_OpcodeAlu, Iss_BranchAddrAlu , Iss_JalInstAlu, Iss_JrRsInstAlu, Iss_JrInstAlu, Iss_ImmediateAlu)
begin
Alu_BranchOutcome <= '0';
Alu_BranchAddr <= Iss_BranchAddrAlu;
Alu_JrFlush <= '0';
case Iss_OpcodeAlu is
when "000" => -- Addition
Alu_RdData <= PhyReg_AluRsData + PhyReg_AluRtData;
when "001" => -- Subtraction
Alu_RdData <= PhyReg_AluRsData - PhyReg_AluRtData;
when "010" => -- And operation
Alu_RdData <= PhyReg_AluRsData and PhyReg_AluRtData;
when "011" => -- Or operation
Alu_RdData <= PhyReg_AluRsData or PhyReg_AluRtData;
when "100" => -- Add immediate
if (Iss_ImmediateAlu(15) = '1') then
Alu_RdData <= PhyReg_AluRsData + ("1111111111111111" & Iss_ImmediateAlu); --do sign extend
else
Alu_RdData <= PhyReg_AluRsData + ("0000000000000000" & Iss_ImmediateAlu);
end if;
when "101" => -- slt
Alu_RdData(31 downto 1) <= (others => '0');
if ( PhyReg_AluRsData < PhyReg_AluRtData ) then
Alu_RdData(0) <= '1';
else
Alu_RdData(0) <= '0';
end if;
when "110" => -- beq
if(PhyReg_AluRsData = PhyReg_AluRtData) then
Alu_BranchOutcome <= '1';
else
Alu_BranchOutcome <= '0';
end if;
Alu_RdData <= (others => '0');
when "111" => -- bne
if(PhyReg_AluRsData = PhyReg_AluRtData) then
Alu_BranchOutcome <= '0';
else
Alu_BranchOutcome <= '1';
end if;
Alu_RdData <= (others => '0');
when others =>
Alu_RdData <= (others => '0');
end case;
if(Iss_JalInstAlu = '1') then -- jal instruction
Alu_RdData <= Iss_BranchAddrAlu;
end if;
if(Iss_JrInstAlu = '1') then -- Jr $31
if(Iss_BranchAddrAlu = PhyReg_AluRsData) then
Alu_JrFlush <= '0';
else
Alu_BranchAddr <= PhyReg_AluRsData;
Alu_JrFlush <= '1';
end if;
end if;
if(Iss_JrRsInstAlu = '1') then -- Jr Rs
Alu_JrFlush <= '0';
Alu_BranchAddr <= PhyReg_AluRsData;
end if;
end process ALU_COMPUT;
end architecture comput;
|
gpl-2.0
|
8e2a70f056a6ec6136d1c8e100182ebf
| 0.577108 | 3.57377 | false | false | false | false |
corneydavid/HT_FPGA
|
Exercises/Exercises/Exercise 5-1 Implement Custom IP/NI 5734 FIR Filter [FPGA]/FIR Compiler/FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C.vhd
| 1 | 6,877 |
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C.vhd when simulating
-- the core, FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C IS
port (
sclr: in std_logic;
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(31 downto 0));
END FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C;
ARCHITECTURE FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C_a OF FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C IS
-- synthesis translate_off
component wrapped_FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C
port (
sclr: in std_logic;
clk: in std_logic;
ce: in std_logic;
nd: in std_logic;
rfd: out std_logic;
rdy: out std_logic;
din: in std_logic_vector(15 downto 0);
dout: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C use entity XilinxCoreLib.fir_compiler_v5_0(behavioral)
generic map(
coef_width => 18,
c_has_sclr => 1,
datapath_memtype => 0,
c_component_name => "FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C",
c_family => "virtex5",
round_mode => 1,
output_width => 32,
sclr_deterministic => 0,
col_config => "17",
coef_memtype => 0,
clock_freq => 300000000,
symmetry => 1,
col_pipe_len => 4,
c_latency => 23,
chan_sel_width => 1,
c_xdevicefamily => "virtex5",
c_has_nd => 1,
allow_approx => 0,
num_channels => 1,
data_width => 16,
filter_sel_width => 1,
sample_freq => 300000000,
coef_reload => 0,
neg_symmetry => 0,
filter_type => 0,
data_type => 0,
accum_width => 37,
rate_change_type => 0,
ipbuff_memtype => 0,
c_optimization => 1,
output_reg => 1,
data_memtype => 0,
c_has_data_valid => 0,
decim_rate => 1,
coef_type => 0,
filter_arch => 1,
interp_rate => 1,
num_taps => 33,
c_mem_init_file => "FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C.mif",
zero_packing_factor => 1,
num_paths => 1,
num_filts => 1,
col_mode => 0,
c_has_ce => 1,
chan_in_adv => 0,
opbuff_memtype => 0,
odd_symmetry => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C
port map (
sclr => sclr,
clk => clk,
ce => ce,
nd => nd,
rfd => rfd,
rdy => rdy,
din => din,
dout => dout);
-- synthesis translate_on
END FIR_Compiler_4CD2A32C408F15EFB482219563CAD03C_a;
|
apache-2.0
|
8526aa7b56fdacbdebaa41184aea7ebd
| 0.554311 | 4.059622 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/web_button.vhd
| 1 | 2,201 |
----------------------------------------------------------------------------------
-- Óñòðîéñòâî: êíîïêè
-- Êîä: 0x03
-- --------- ---------- ---------- --------- ------- ------- ------- -------
-- | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
-- |-------------------------------------------------------------------------|
-- | PB_WEST | PB_SOUTH | PB_NORTH | PB_EAST | SW[3] | SW[2] | SW[1] | SW[0] |
-- --------- ---------- ---------- --------- ------- ------- ------- -------
-- PB - push button; SW - switch button
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity web_button is
port (
data_o: out std_logic_vector(7 downto 0); -- âûâîäèò ñîñòîÿíèÿ êíîïîê
rs232_data_i: in std_logic_vector(7 downto 0); -- äàííûå, îò êíîïîê ñ êîì ïîðòà
physical_data_i: in std_logic_vector(7 downto 0); -- äàííûå ñ ôèçè÷åñêèõ êíîïîê
rst_i: in std_logic;
clk: in std_logic
);
end web_button;
architecture BtnArch of web_button is
signal physical_data_r0, physical_data_r1: std_logic_vector(7 downto 0);
begin
proc: process(clk, rst_i)
variable store_rs232_data_i: integer := 0;
variable store_physical_data_i: integer := 0;
--variable init_flag: boolean := true;
begin
if rst_i = '1' then
--init_flag := false;
store_rs232_data_i := to_integer(unsigned(rs232_data_i));
store_physical_data_i := to_integer(unsigned(physical_data_r1));
physical_data_r0 <= (others =>'0');
physical_data_r1 <= (others =>'0');
elsif rising_edge(clk) then
physical_data_r0 <= physical_data_i;
physical_data_r1<=physical_data_r0;
-- åñëè äàííûå äëÿ êíîïîê ïðèøëè ñ êîì ïîðòà
if store_rs232_data_i /= to_integer(unsigned(rs232_data_i)) then
store_rs232_data_i := to_integer(unsigned(rs232_data_i));
data_o <= rs232_data_i;
-- èíà÷å åñëè äàííûå ïðèøëè îò ôèçè÷åñêèõ êíîïîê
elsif store_physical_data_i /= to_integer(unsigned(physical_data_r1)) then
store_physical_data_i := to_integer(unsigned(physical_data_r1));
data_o <= physical_data_r1;
end if;
end if;
end process;
end BtnArch;
|
mit
|
1cb9b495b68643379f2ff34922307a6e
| 0.534303 | 3.091292 | false | false | false | false |
csrhau/sandpit
|
VHDL/vga_imdisplay/test_vga_system.vhdl
| 2 | 2,495 |
library ieee;
use ieee.std_logic_1164.all;
use work.init_funcs.all;
use std.textio.all;
entity test_vga_system is
end test_vga_system;
architecture behavioural of test_vga_system is
component VGA_system is
generic (
display_rows : natural := 480;
display_cols : natural := 640
);
port (
clock : in std_logic; -- 100 MHz Clock
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end component VGA_system;
signal clock : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal red : std_logic_vector(2 downto 0);
signal green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(2 downto 1);
begin
SYSTEM: VGA_system port map (
clock,
hsync,
vsync,
red,
green,
blue
);
process
variable vsync_holder : std_logic;
variable hsync_holder : std_logic;
variable log_line, data_line : line;
file file_pointer: text is out "vga_log.txt";
begin
for i in 1 to 2000000 loop
vsync_holder := vsync;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay2 -> Read
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Read -> Update
wait for 5 ns;
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Update -> Delay1
wait for 5 ns;
write(data_line, now); -- write the line.
write(data_line, ':'); -- write the line.
-- Write the hsync
write(data_line, ' ');
write(data_line, chr(hsync)); -- write the line.
-- Write the vsync
write(data_line, ' ');
write(data_line, chr(vsync)); -- write the line.
-- Write the red
write(data_line, ' ');
write(data_line, str(red)); -- write the line.
-- Write the green
write(data_line, ' ');
write(data_line, str(green)); -- write the line.
-- Write the blue
write(data_line, ' ');
write(data_line, str(blue)); -- write the line.
writeline(file_pointer, data_line); -- write the contents into the file.
clock <= '0';
wait for 5 ns;
clock <= '1'; -- Delay1 -> Delay2
wait for 5 ns;
end loop;
wait;
end process;
end behavioural;
|
mit
|
775d2bc5943104ba0ba24fb1a6e11b8c
| 0.543487 | 3.75188 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/multiplier_core.vhd
| 1 | 8,536 |
------------------------------------------------------------------------------
-- Create/rivision Date: on 07/21/09
-- Design Name: multiplier_core for Tomasulo execution units
-- Module Name: multiplier_core
-- Author: Ketan Sharma, Ashutosh Moghe, Gandhi Puvvada
------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------------
-- This is a pipelined multiplier. It has 4 stages.
-- The four parts of the combinational logic are separated by three (3, not 4) stage registers.
-- The end registers (one at entry and one at exit) are not coded here.
-- The entry register is the register in multiplier issue queue.
-- The exit register is the CDB register.
-- Comb_logic_1 -> Stage_Reg1 -> Comb_logic_2 -> Stage_Reg2 -> Comb_logic_3 -> Stage_Reg3 -> Comb_logic_4
-- _suffix_A _suffix_B _suffix_C _suffix_D
-- The suffixes _A, _B, _C, _D are used with signals and variables.
------------------------------------------------------------------------------
-- This design is the "core" design. There is wrapper called "multiplier,
-- which instantiates this core. The wrapper design is responsible to carry
-- the tags of
------------------------------------------------------------------------------
entity multiplier_core is
Port ( m: in std_logic_vector (15 downto 0 ); -- multiplicand (input 1)
q: in std_logic_vector ( 15 downto 0); -- multiplier (input 2)
P: out std_logic_vector ( 31 downto 0); -- the output product
clk: in std_logic
);
end multiplier_core;
------------------------------------------------------------------------------
architecture behv of multiplier_core is
-- Signals with suffixes (signals with suffixes _B, _C, and _D are actually Pipeline registers
signal m_A, m_B, q_A, m_C, q_B, q_C: std_logic_vector (15 downto 0); -- Pipeline registers
-- Note: The product bits are progressively generated and further carried through the pipe. Hence they were 6 bits to start
-- with and eventually became 32 bits.
signal P_A_5_to_0, P_B_5_to_0: std_logic_vector (5 downto 0);
signal P_B_10_to_6 : std_logic_vector (10 downto 6);
-- P_B_5_to_0 are FFs in Stage_Reg1, where as P_B_10_to_6 are produced combinationally by CSAs
signal P_C_10_to_0: std_logic_vector (10 downto 0);
signal P_C_15_to_11: std_logic_vector (15 downto 11);
-- P_C_10_to_0 are FFs in Stage_Reg2, where as P_C_15_to_11 are produced combinationally by CSAs
signal P_D_15_to_0: std_logic_vector (15 downto 0);
signal P_D_31_to_16: std_logic_vector (31 downto 16);
-- P_D_15_to_0 are FFs in Stage_Reg3, where as P_D_31_to_16 are produced combinationally by Comb_logic_4 (CPA/CLA)
signal s_A_out, c_A_out, s_B_in, c_B_in, s_B_out, c_B_out,s_C_in, c_C_in, s_C_out, c_C_out, s_D_in, c_D_in : std_logic_vector (15 downto 1); -- _B, _C, _D are Pipeline registers
begin
-----------------------------------------------------------
m_A <= m; q_A <= q;
mult_stage1_comb: process (m_A, q_A)
variable s_v_A : std_logic_vector (15 downto 0); -- sum input. -- note s_v_A is 16 bits where as s_A signal is 15 bits
variable pp_v_A : std_logic_vector (15 downto 1); -- partial product for stage 1.
variable c_v_A : std_logic_vector (15 downto 1); -- carry input.
begin
c_v_A(15 downto 1) := "000000000000000"; -- carry input for stage 1 is 0.
s_v_A(15 downto 0) := (m_A(15) and q_A(0)) & (m_A(14) and q_A(0)) & (m_A(13) and q_A(0)) &
(m_A(12) and q_A(0)) & (m_A(11) and q_A(0)) & (m_A(10) and q_A(0)) &
(m_A(9) and q_A(0)) & (m_A(8) and q_A(0)) & (m_A(7) and q_A(0)) &
(m_A(6) and q_A(0)) & (m_A(5) and q_A(0)) & (m_A(4) and q_A(0)) &
(m_A(3) and q_A(0)) & (m_A(2) and q_A(0)) & (m_A(1) and q_A(0)) & (m_A(0) and q_A(0)); -- sum input for stage 1 is partial product of stage 0.
P_A_5_to_0(0) <= s_v_A(0); -- the lowest partial product retires as product outputs 0th bit.
for i in 1 to 5 loop -- this loop instantiates 5 stages of the 15 CSA stages in a 16x16 multiplication. using linear cascading of CSAs (and not a Walace Tree)
for j in 1 to 15 loop -- one iteration of this loop makes one 15 bit CSA (one row of Full-Adder boxes)
pp_v_A(j) := q_A(i) and m_A(j-1);
s_v_A(j -1) := s_v_A(j) xor c_v_A(j) xor pp_v_A(j);
c_v_A(j) := (s_v_A(j) and c_v_A(j)) or (c_v_A(j) and pp_v_A(j)) or (s_v_A(j) and pp_v_A(j));
end loop;
P_A_5_to_0(i) <= s_v_A(0);
s_v_A(15) := m_A(15) and q_A(i);
end loop;
s_A_out <= s_v_A(15 downto 1); -- note s_v_A is 16 bits where as s_A signal is 15 bits
c_A_out <= c_v_A;
end process mult_stage1_comb;
mult_stage1_clocked: process (clk)
begin
if (clk'event and clk = '1') then
m_B <= m_A; q_B <= q_A; -- some bits of q are not needed bu they will be removed during oprimization by the syntehsis tool
s_B_in <= s_A_out;
c_B_in <= c_A_out;
P_B_5_to_0 <= P_A_5_to_0;
end if;
end process mult_stage1_clocked;
-----------------------------------------------------------
mult_stage2_comb: process (m_B, q_B, S_B_in, c_B_in)
variable s_v_B : std_logic_vector (15 downto 0); -- sum input. -- note s_v_B is 16 bits where as s_B signal is 15 bits
variable pp_v_B : std_logic_vector (15 downto 1); -- partial product for stage 1.
variable c_v_B : std_logic_vector (15 downto 1); -- carry input.
begin
s_v_B := S_B_in & '0';
c_v_B := c_B_in;
for i in 6 to 10 loop -- this loop instantiates 5 stages of the 15 CSA stages in a 16x16 multiplication. using linear cascading of CSAs (and not a Walace Tree)
for j in 1 to 15 loop -- one iteration of this loop makes one 15 bit CSA (one row of Full-Adder boxes)
pp_v_B(j) := q_B(i) and m_B(j-1);
s_v_B(j -1) := s_v_B(j) xor c_v_B(j) xor pp_v_B(j);
c_v_B(j) := (s_v_B(j) and c_v_B(j)) or (c_v_B(j) and pp_v_B(j)) or (s_v_B(j) and pp_v_B(j));
end loop;
P_B_10_to_6(i) <= s_v_B(0);
s_v_B(15) := m_B(15) and q_B(i);
end loop;
s_B_out <= s_v_B(15 downto 1); -- note s_v_B is 16 bits where as s_B signal is 15 bits
c_B_out <= c_v_B;
end process mult_stage2_comb;
mult_stage2_clocked: process (clk)
begin
if (clk'event and clk = '1') then
m_C <= m_B; q_C <= q_B; -- some bits of q are not needed bu they will be removed during oprimization by the syntehsis tool
s_C_in <= s_B_out;
c_C_in <= c_B_out;
P_C_10_to_0 <= P_B_10_to_6 & P_B_5_to_0;
end if;
end process mult_stage2_clocked;
-----------------------------------------------------------
mult_stage3_comb: process (m_C, q_C, S_C_in, c_C_in)
variable s_v_C : std_logic_vector (15 downto 0); -- sum input. -- note s_v_C is 16 bits where as s_C signal is 15 bits
variable pp_v_C : std_logic_vector (15 downto 1); -- partial product for stage 1.
variable c_v_C : std_logic_vector (15 downto 1); -- carry input.
begin
s_v_C := S_C_in & '0';
c_v_C := c_C_in;
for i in 11 to 15 loop -- this loop instantiates 5 stages of the 15 CSA stages in a 16x16 multiplication. using linear cascading of CSAs (and not a Walace Tree)
for j in 1 to 15 loop -- one iteration of this loop makes one 15 bit CSA (one row of Full-Adder boxes)
pp_v_C(j) := q_C(i) and m_C(j-1);
s_v_C(j -1) := s_v_C(j) xor c_v_C(j) xor pp_v_C(j);
c_v_C(j) := (s_v_C(j) and c_v_C(j)) or (c_v_C(j) and pp_v_C(j)) or (s_v_C(j) and pp_v_C(j));
end loop;
P_C_15_to_11(i) <= s_v_C(0);
s_v_C(15) := m_C(15) and q_C(i);
end loop;
s_C_out <= s_v_C(15 downto 1); -- note s_v_C is 16 bits where as s_C signal is 15 bits
c_C_out <= c_v_C;
end process mult_stage3_comb;
mult_stage3_clocked: process (clk)
begin
if (clk'event and clk = '1') then
-- m_D <= m_C; q_D <= q_C; -- the multiplicand and the multiplier are no more needed for the last stage.
s_D_in <= s_C_out;
c_D_in <= c_C_out;
P_D_15_to_0 <= P_C_15_to_11 & P_C_10_to_0;
end if;
end process mult_stage3_clocked;
-----------------------------------------------------------
-- Comb_logic_4 (CPA/CLA)
P_D_31_to_16 <= unsigned('0' & c_D_in) + unsigned('0' & s_D_in);
-----------------------------------------------------------
P <= P_D_31_to_16 & P_D_15_to_0 ;
end behv;
|
gpl-2.0
|
e63c8075d046f5f38ece75a174ee2261
| 0.547446 | 2.802364 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/cont50.vhd
| 1 | 3,729 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont50.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity cont50 is
Port ( clk : in STD_LOGIC;
ena : in STD_LOGIC;
rst: in std_logic;
fin : out STD_LOGIC
);
end cont50;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of cont50 is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal reg_cuenta: std_logic_vector(7 downto 0);
signal reg_cuenta_in: std_logic_vector(7 downto 0);
signal fin_aux: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT incrementadorCuenta8bits
PORT(
num_in : IN std_logic_vector(7 downto 0);
num_out : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
fin <= fin_aux;
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
incr_0: incrementadorCuenta8bits PORT MAP(
num_in => reg_cuenta,
num_out => reg_cuenta_in
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_cuenta: process(clk, ena, rst)
begin
if rst = '1' then
reg_cuenta <= (others => '0');
fin_aux <= '0';
elsif rising_edge(clk) then
if fin_aux = '1' then
fin_aux <= '0';
reg_cuenta <= (others => '0');
elsif reg_cuenta = "00110010" then
fin_aux <= '1';
reg_cuenta <= (others => '0');
elsif ena = '1' then
reg_cuenta <= reg_cuenta_in;
fin_aux <= '0';
end if;
end if;
end process p_cuenta;
end rtl;
|
gpl-3.0
|
dc4815b567aeb139b2bf399c33381fd3
| 0.403542 | 5.084584 | false | false | false | false |
gxliu/ARM-Cortex-M0
|
hdl/alu.vhd
| 1 | 5,522 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
port ( input_1 : in std_logic_vector (31 downto 0);
input_2 : in std_logic_vector (31 downto 0);
funct : in std_logic_vector (4 downto 0);
flags_current : in std_logic_vector(3 downto 0);
output : out std_logic_vector (31 downto 0);
flags_next : out std_logic_vector (3 downto 0);
flags_update : out std_logic_vector (1 downto 0)); -- 0:none 1:NZ 2:NZC 3:NZCV
end alu;
architecture Behavioral of alu is
component mul32 is
port ( a : in std_logic_vector (31 downto 0);
b : in std_logic_vector (31 downto 0);
p : out std_logic_vector (31 downto 0));
end component mul32;
component shift is
port ( mode : in std_logic_vector (1 downto 0);--0:LSLS 1:LSRS 2:ASRS 3:RORS
shift : in std_logic_vector (4 downto 0);
input : in std_logic_vector (31 downto 0);
carry : out std_logic;
output : out std_logic_vector (31 downto 0));
end component shift;
component add32 is
port ( a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in std_logic;
sum : out std_logic_vector(31 downto 0);
cout : out std_logic);
end component add32;
signal zero, carry_out, overflow : std_logic;
signal output_mux, output_mul, output_shift, output_add, output_mvn : std_logic_vector(31 downto 0);
signal carry_mux, carry_shift, carry_in_add, carry_add : std_logic;
signal shift_mode : std_logic_vector(1 downto 0);
signal input_add_2 : std_logic_vector(31 downto 0);
begin
--FIX OP CODE
--00000 AND ok
--00001 EOR ok
--00010 LSL ok
--00011 LSR ok
--00100 ASR ok
--00101 ADC ok, V not implemented
--00110 SBC ok, V not implemented
--00111 ROR ok
--01000 TST
--01001 NEG
--01010 CMP ok, V not implemented, same as sub, not implemented not outputting result
--01011 CMN ok, V not implemented, same as add, not implemented not outputting result
--01100 ORR ok
--01101 MUL ok
--01110 BIC ok
--01111 MVN ok
--10000 MOV ok
--10001 ADD ok, V not implemented
--10010 SUB ok, V not implemented
mul_block : mul32 port map (
a => input_1 ,
b => input_2 ,
p => output_mul
);
shift_mode <= "00" when funct = "00010" else
"01" when funct = "00011" else
"10" when funct = "00100" else
"11";
shift_block : shift port map (
mode => shift_mode ,
shift => input_2( 4 downto 0) ,
input => input_1 ,
carry => carry_shift ,
output => output_shift
);
input_add_2 <= input_2 when funct = "00101" or funct = "10001" or funct = "01011" else
std_logic_vector(unsigned(not(input_2)) + 1);
carry_in_add <= flags_current(1) when funct = "00101" or funct = "00110" else
'0';
add_block : add32 port map (
a => input_1 ,
b => input_add_2 ,
cin => carry_in_add ,
sum => output_add ,
cout => carry_add
);
output_mvn <= not( input_1 );
output_mux <= input_1 and input_2 when funct = "00000" else
input_1 xor input_2 when funct = "00001" else
input_1 or input_2 when funct = "01100" else
input_1 and not(input_2) when funct = "01110" else
output_mul when funct = "01101" else
output_shift when funct = "00010" or funct = "00011" or funct = "00100" or funct = "00111" else
output_add when funct = "00101" or funct = "10001" or funct = "00110" or funct = "10010" or funct = "01011" or funct = "01010" else -- wrong "01011" , wrong "01010"
output_mvn when funct = "01111" else
input_1 when funct = "10000" else
(others=> '0');
output <= output_mux;
zero <= not ( output_mux(31) or output_mux(30) or output_mux(29) or output_mux(28) or output_mux(27) or output_mux(26) or output_mux(25) or output_mux(24) or
output_mux(23) or output_mux(22) or output_mux(21) or output_mux(20) or output_mux(19) or output_mux(18) or output_mux(17) or output_mux(16) or
output_mux(15) or output_mux(14) or output_mux(13) or output_mux(12) or output_mux(11) or output_mux(10) or output_mux( 9) or output_mux( 8) or
output_mux( 7) or output_mux( 6) or output_mux( 5) or output_mux( 4) or output_mux( 3) or output_mux( 2) or output_mux( 1) or output_mux( 0) );
carry_mux <= carry_shift when funct = "00010" or funct = "00011" or funct = "00100" or funct = "00111" else
carry_add when funct = "00101" or funct = "10001" or funct = "00110" or funct = "10010" or funct = "01011" or funct = "01010" else
'0';
overflow <= '1' when funct = "" else
'0';
flags_next <= output_mux(31) & zero & carry_mux & overflow;
flags_update <= "01" when funct = "01101" or funct = "00000" or funct = "00001" or funct = "01100" or funct = "01110" or funct = "01000" or funct = "01111" or funct = "10000" else
"10" when funct = "00010" or funct = "00011" or funct = "00100" or funct = "00111" else
"11" when funct = "00101" or funct = "00110" or funct = "01001" or funct = "01010" or funct = "01011" or funct = "10001" or funct = "10010" else
"00";
end Behavioral;
|
mit
|
c0d3093e8b36e6eae243637ac4a75b9a
| 0.576784 | 3.43408 | false | false | false | false |
BBN-Q/APS2-TDM
|
src/TDM_top.vhd
| 1 | 20,095 |
-- TDM_top.vhd
--
-- This is the top level module of the ATM firmware.
-- It instantiates the main BD with the comms., 9 SATA outputs, and one SATA input.
-- Original authors: Colm Ryan and Blake Johnson
-- Copyright 2015,2016 Raytheon BBN Technologies
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
entity TDM_top is
generic (
TDM_VERSION : std_logic_vector(31 downto 0) := x"0000_0000"; -- bits 31-28 = d for dirty; bits 27-16 commits since; bits 15-8 version major; bits 7-0 version minor;
GIT_SHA1 : std_logic_vector(31 downto 0) := x"0000_0000"; -- git SHA1 of HEAD;
BUILD_TIMESTAMP : std_logic_vector(31 downto 0) := x"0000_0000" -- 32h'YYMMDDHH as hex string e.g. 16032108 for 2016-March-21 8am
);
port
(
ref_fpga : in std_logic; -- Global 10MHz reference
fpga_resetl : in std_logic; -- Global reset from config FPGA
-- Temp Diode Pins
vp : in std_logic;
vn : in std_logic;
-- Config Bus Connections
cfg_clk : in std_logic; -- 100 MHZ clock from the Config CPLD
cfgd : inout std_logic_vector(15 downto 0); -- Config Data bus from CPLD
fpga_cmdl : out std_logic; -- Command strobe from FPGA
fpga_rdyl : out std_logic; -- Ready Strobe from FPGA
cfg_rdy : in std_logic; -- Ready to complete current transfer. Connected to CFG_RDWR_B
cfg_err : in std_logic; -- Error during current command. Connecte to CFG_CSI_B
cfg_act : in std_logic; -- Current transaction is complete
stat_oel : out std_logic; -- Enable CPLD to drive status onto CFGD
-- SFP Tranceiver Interface
sfp_mgt_clkp : in std_logic; -- 125 MHz reference
sfp_mgt_clkn : in std_logic;
sfp_txp : out std_logic; -- TX out to SFP
sfp_txn : out std_logic;
sfp_rxp : in std_logic; -- RX in from SPF
sfp_rxn : in std_logic;
-- SFP control signals
sfp_enh : buffer std_logic; -- sfp enable high
sfp_scl : out std_logic; -- sfp serial clock - unused
sfp_txdis : buffer std_logic; -- sfp disable laser
sfp_sda : in std_logic; -- sfp serial data - unused
sfp_fault : in std_logic; -- sfp tx fault -unused
sfp_los : in std_logic; -- sfp loss of signal input laser power too low; also goes high when ethernet jack disconnected; low when plugged in -unused
sfp_presl : in std_logic; -- sfp present low ??? doesn't seem to be in spec.
-- External trigger comparator related signals
trg_cmpn : in std_logic_vector(7 downto 0);
trg_cmpp : in std_logic_vector(7 downto 0);
thr : out std_logic_vector(7 downto 0);
-- Trigger Outputs
trgclk_outn : out std_logic_vector(8 downto 0);
trgclk_outp : out std_logic_vector(8 downto 0);
trgdat_outn : out std_logic_vector(8 downto 0);
trgdat_outp : out std_logic_vector(8 downto 0);
-- Trigger input
trig_ctrln : in std_logic_vector(1 downto 0);
trig_ctrlp : in std_logic_vector(1 downto 0);
-- Internal Status LEDs
led : out std_logic_vector(9 downto 0);
-- Debug LEDs / configuration jumpers
dbg : inout std_logic_vector(8 downto 0)
);
end TDM_top;
architecture behavior of TDM_top is
--- Constants ---
constant SUBNET_MASK : std_logic_vector(31 downto 0) := x"ffffff00"; -- 255.255.255.0
constant TCP_PORT : std_logic_vector(15 downto 0) := x"bb4e"; -- BBN
constant UDP_PORT : std_logic_vector(15 downto 0) := x"bb4f"; -- BBN + 1
constant GATEWAY_IP_ADDR : std_logic_vector(31 downto 0) := x"c0a80201"; -- TODO: what this should be?
constant PCS_PMA_AN_ADV_CONFIG_VECTOR : std_logic_vector(15 downto 0) := x"0020"; --full-duplex see Table 2-55 (pg. 74) of PG047 November 18, 2015
constant PCS_PMA_CONFIGURATION_VECTOR : std_logic_vector(4 downto 0) := b"10000"; --auto-negotiation enabled see Table 2-54 (pg. 73) of PG047 November 18, 2015
--- clocks
signal clk_100, clk_100_skewed, clk_100_axi, clk_125, clk_200, clk_400,
ref_125 : std_logic;
signal cfg_clk_mmcm_locked : std_logic;
signal ref_locked : std_logic;
signal ref_locked_s : std_logic;
signal ref_locked_d : std_logic;
signal sys_clk_mmcm_locked : std_logic;
-- Resets
signal rst_comm_stack, rst_cfg_reader, rst_comblock,
rst_cpld_bridge, rst_eth_mac, rst_pcs_pma, rst_tcp_bridge,
rst_udp_responder, rstn_axi,
rst_sync_clk125, rst_sync_clk100, rst_sync_clk_100_axi,
rst_sata : std_logic := '0';
signal cfg_reader_done : std_logic;
--SFP
signal mgt_clk_locked : std_logic;
signal pcs_pma_status_vector : std_logic_vector(15 downto 0);
alias link_established : std_logic is pcs_pma_status_vector(0);
signal pcs_pma_an_restart_config : std_logic;
signal ExtTrig : std_logic_vector(7 downto 0);
signal sys_clk_mmcm_reset : std_logic := '0';
-- Trigger signals
type BYTE_ARRAY is array (0 to 8) of std_logic_vector(7 downto 0);
signal TrigOutDat : BYTE_ARRAY;
signal TrigWr : std_logic_vector(8 downto 0);
signal TrigInDat : std_logic_vector(7 downto 0);
signal TrigClkErr : std_logic;
signal TrigOvflErr : std_logic;
signal TrigLocked : std_logic;
signal TrigInReady : std_logic;
signal TrigInRd : std_logic;
signal TrigFull : std_logic;
signal ext_valid : std_logic;
signal ext_valid_d : std_logic;
signal ext_valid_re : std_logic;
signal CMP : std_logic_vector(7 downto 0);
-- etherenet comms status
signal comms_active : std_logic;
signal ethernet_mm2s_err, ethernet_s2mm_err : std_logic;
-- CSR registers
signal status, control, resets, SATA_status, uptime_seconds, uptime_nanoseconds,
trigger_interval, latched_trig_word : std_logic_vector(31 downto 0) := (others => '0');
alias trigger_enabled : std_logic is control(4);
alias soft_trig_toggle : std_logic is control(3);
alias trigger_source : std_logic_vector(1 downto 0) is control(2 downto 1);
signal trigger : std_logic;
begin
------------------------- clocking ------------------------------------------
sync_reflocked : entity work.synchronizer
port map ( rst => not(fpga_resetl), clk => clk_125, data_in => ref_locked, data_out => ref_locked_s );
-- need to reset SYS_MMCM on rising or falling edge of RefLocked
sys_mmcm_reset : process( mgt_clk_locked, clk_125 )
begin
if mgt_clk_locked = '0' then
sys_clk_mmcm_reset <= '1';
elsif rising_edge(clk_125) then
ref_locked_d <= ref_locked_s;
if (ref_locked_d xor ref_locked_s) = '1' then
sys_clk_mmcm_reset <= '1';
else
sys_clk_mmcm_reset <= '0';
end if;
end if;
end process ; -- sys_mmcm_reset
-- multiply reference clock up to 125 MHz
ref_mmmc_inst : entity work.REF_MMCM
port map (
CLK_REF => ref_fpga,
-- clock out ports
CLK_100MHZ => ref_125,
-- status and control signals
RESET => not fpga_resetl,
LOCKED => ref_locked
);
-- Create aligned 100 and 400 MHz clocks for SATA in/out logic
-- from either the 10 MHz reference or the 125 MHz sfp clock
sys_mmcm_inst : entity work.SYS_MMCM
port map
(
-- Clock in ports
REF_125MHZ_IN => ref_125,
CLK_125MHZ_IN => clk_125,
CLK_IN_SEL => ref_locked, -- choose ref_125 when HIGH
-- Clock out ports
CLK_100MHZ => clk_100,
CLK_400MHZ => clk_400,
-- Status and control signals
RESET => sys_clk_mmcm_reset,
LOCKED => sys_clk_mmcm_locked
);
-- create a skewed copy of the cfg_clk to meet bus timing
-- create a 100MHz clock for AXI
-- create a 200 MHz IODELAY reference calibration
cfg_clk_mmcm_inst : entity work.CCLK_MMCM
port map (
clk_100MHZ_in => cfg_clk,
clk_100MHZ_skewed => clk_100_skewed,
clk_100MHZ => clk_100_axi,
clk_200MHZ => clk_200,
reset => not fpga_resetl,
locked => cfg_clk_mmcm_locked
);
-- wire out status register bits
status(0) <= mgt_clk_locked; --if low we probably won't be able to read anyways
status(1) <= cfg_clk_mmcm_locked; --if low we probably won't be able to read anyways
status(2) <= ref_locked;
status(3) <= sys_clk_mmcm_locked;
status(4) <= sys_clk_mmcm_reset;
-------------------- SFP -------------------------------------------------------
-- force use of usused pins
sfp_scl <= '1' when
(fpga_resetl = '0' and (sfp_sda and sfp_fault and sfp_los and sfp_presl) = '1')
else '0';
-- reset SFP module for at least 100 ms when FPGA is reprogrammed or fpga_resetl is asserted
sfp_reset_pro : process(clk_125, mgt_clk_locked, sfp_presl)
variable reset_ct : unsigned(24 downto 0) := (others => '0');
begin
if mgt_clk_locked = '0' or sfp_presl = '1' then
reset_ct := to_unsigned(12_500_000, reset_ct'length); --100ms at 125MHz ignoring off-by-one issues
sfp_enh <= '0';
sfp_txdis <= '1';
elsif rising_edge(clk_125) then
if reset_ct(reset_ct'high) = '1' then
sfp_enh <= '1';
sfp_txdis <= '0';
else
reset_ct := reset_ct - 1;
end if;
end if;
end process;
---------------------------- resets -----------------------------------------
-- Reset sequencing:
-- 1. CFG clock is reset by FPGA_RESETL and everything waits on CFG clock to lock
-- 2. Once CFG clock is up release CPLD bridge to let APS Msg processor come up and PCS/PMA layer
-- 3. Wait ???? after ApsMsgProc released from reset to issue configuration read command
-- 3. Wait 100 ms after boot for SFP to come up (see above)
-- 4. Wait for cfg_reader_done with timeout of ??? to release rest of comms stack
-- 5. Release everything else
--Wait until cfg_clk_mmcm_locked so that we have 200MHz reference before deasserting pcs/pma and MIG reset
rst_pcs_pma <= not cfg_clk_mmcm_locked;
-- once we have CFG clock MMCM locked we have CPLD and AXI and we can talk to CPLD
reset_synchronizer_clk_100_axi : entity work.synchronizer
generic map(RESET_VALUE => '1')
port map(rst => not cfg_clk_mmcm_locked, clk => clk_100_axi, data_in => '0', data_out => rst_sync_clk_100_axi);
rst_cpld_bridge <= rst_sync_clk_100_axi;
rst_tcp_bridge <= rst_sync_clk_100_axi;
rstn_axi <= not rst_sync_clk_100_axi;
-- hold config reader in reset until after CPLD and AXI are ready and give another 100ms
-- for ApsMsgProc to startup and do it's reading of the MAC address
-- then wait for done with timeout of 100ms so we have IP and MAC before releasing comm statck
cfg_reader_wait : process(clk_100_axi)
variable reset_ct : unsigned(24 downto 0) := (others => '0');
variable wait_ct : unsigned(24 downto 0) := (others => '0');
type state_t is (WAIT_FOR_RESET, WAIT_FOR_DONE, FINISHED);
variable state : state_t;
begin
if rising_edge(clk_100_axi) then
if rst_sync_clk_100_axi = '1' then
state := WAIT_FOR_RESET;
reset_ct := to_unsigned(10_000_000, reset_ct'length); --100ms at 100 MHz ignoring off-by-one issues
wait_ct := to_unsigned(10_000_000, wait_ct'length); --100ms at 100 MHz ignoring off-by-one issues
rst_cfg_reader <= '1';
rst_comm_stack <= '1';
else
case( state ) is
when WAIT_FOR_RESET =>
if reset_ct(reset_ct'high) = '1' then
state := WAIT_FOR_DONE;
else
reset_ct := reset_ct - 1;
end if;
when WAIT_FOR_DONE =>
rst_cfg_reader <= '0';
if cfg_reader_done = '1' or wait_ct(wait_ct'high) = '1' then
state := FINISHED;
else
wait_ct := wait_ct - 1;
end if;
when FINISHED =>
rst_comm_stack <= '0';
end case;
end if;
end if;
end process;
-- synchronize comm stack reset to 125 MHz ethernet clock domain
reset_synchronizer_clk_125Mhz : entity work.synchronizer
generic map(RESET_VALUE => '1')
port map(rst => rst_comm_stack, clk => clk_125, data_in => '0', data_out => rst_sync_clk125);
rst_udp_responder <= rst_sync_clk125;
rst_comblock <= rst_sync_clk125;
rst_eth_mac <= rst_sync_clk125;
-- hold SATA in reset until we have system clock and cfg_clk for 200MHz reference
reset_synchronizer_clk_100 : entity work.synchronizer
generic map(RESET_VALUE => '1')
port map(rst => not (sys_clk_mmcm_locked and cfg_clk_mmcm_locked), clk => clk_100, data_in => '0', data_out => rst_sync_clk100);
rst_sata <= rst_sync_clk100;
------------------ front panel LEDs ------------------------
status_leds_inst : entity work.status_leds
port map (
clk => clk_100_axi,
rst => rst_comm_stack,
link_established => link_established,
comms_active => comms_active,
comms_error => ethernet_mm2s_err or ethernet_s2mm_err,
inputs_latched => ext_valid_re,
trigger_enabled => trigger_enabled,
leds => dbg(7 downto 4)
);
dbg(3 downto 0) <= (others => '0');
-- Send output status to LEDs for checking
-- TODO
led <= (others => '0');
--------------------------- comparator inputs ----------------------------------
CBF1 : for i in 0 to 7 generate
-- External trigger input from LVDS comparator. Must be differentially termianted
IBX : IBUFDS
generic map
(
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE -- Low power (TRUE) vs. performance (FALSE) setting for refernced I/O standards
)
port map
(
O => CMP(i), -- Drive the LED output
I => TRG_CMPP(i), -- Diff_p buffer input (connect directly to top-level port)
IB => TRG_CMPN(i) -- Diff_n buffer input (connect directly to top-level port)
);
PWMX : entity work.PWMA8
port map
(
CLK => clk_100,
RESET => rst_sata,
DIN => x"52", -- Fix at 0.8V for now. Eventually drive from a status register
PWM_OUT => THR(i)
);
end generate;
------------------------- SATA connections ------------------------------------
-- basic logic to broadcast input triggers to all output triggers
-- VALID on rising edge of CMP(7) or internal trigger
-- sync external valid on CLK_100MHZ
sync_valid : entity work.synchronizer
port map ( rst => rst_sata, clk => clk_100, data_in => CMP(7), data_out => ext_valid );
-- DATA is CMP(6 downto 0) except when internal trigger fires, in which case we send 0xFE
ext_valid_re <= ext_valid and not ext_valid_d;
process(clk_100)
begin
if rising_edge(clk_100) then
ext_valid_d <= ext_valid;
if trigger = '1' then
-- magic symbol of 0xFE indicates a system trigger to slave modules
TrigOutDat <= (others => x"fe");
else
TrigOutDat <= (others => '0' & CMP(6 downto 0));
end if;
if rst_sata = '1' then
TrigWr <= (others => '0');
else
TrigWr <= (others => ext_valid_re or trigger);
end if;
end if;
end process;
TO1 : for i in 0 to 8 generate
-- Externally, cable routing requires a non sequential JTx to TOx routing.
-- The cables are routed from the PCB connectors to the front panel as shown below.
-- The mapping is performed by changing the pin definitions in the XDC file.
--
-- TO1 = JT0
-- TO2 = JT2
-- TO3 = JT4
-- TO4 = JT6
-- TO5 = JC01
-- TO6 = JT3
-- TO7 = JT1
-- TO8 = JT5
-- TO9 = JT7
-- TAUX = JT8
TOLX : entity work.TriggerOutLogic
port map
(
-- These clocks are driven by SYS_MMCM, and thus are locked to the 10 MHz
-- reference (if present), or the SFP clock.
CLK_100MHZ => clk_100,
CLK_400MHZ => CLK_400,
RESET => rst_sata,
TRIG_TX => TrigOutDat(i),
TRIG_VALID => TrigWr(i),
TRIG_CLKP => trgclk_outp(i),
TRIG_CLKN => trgclk_outn(i),
TRIG_DATP => trgdat_outp(i),
TRIG_DATN => trgdat_outn(i)
);
end generate;
-- Instantiate LVDS 8:1 logic on auxiliary SATA port
TIL1 : entity work.TriggerInLogic
port map
(
USER_CLK => clk_100,
CLK_200MHZ => clk_200,
RESET => rst_sata,
TRIG_CLKP => trig_ctrlp(0),
TRIG_CLKN => trig_ctrln(0),
TRIG_DATP => trig_ctrlp(1),
TRIG_DATN => trig_ctrln(1),
TRIG_NEXT => TrigInRd, -- Always read data when it is available
TRIG_LOCKED => TrigLocked,
TRIG_ERR => TrigClkErr,
TRIG_RX => TrigInDat,
TRIG_OVFL => TrigOvflErr,
TRIG_READY => TrigInReady
);
-- Continually drain the input FIFO
TrigInRd <= TrigInReady;
-- internal trigger generator
IntTrig : entity work.InternalTrig
port map (
RESET => not trigger_enabled,
CLK => clk_100,
triggerInterval => trigger_interval,
triggerSource => trigger_source(1),
softTrigToggle => soft_trig_toggle,
trigger => trigger
);
-- wire out status registers
SATA_status(8 downto 0) <= TrigWr;
SATA_status(17 downto 9) <= (others => '0');
SATA_status(20) <= ext_valid;
SATA_status(24) <= TrigLocked;
SATA_status(25) <= TrigClkErr;
SATA_status(26) <= TrigOvflErr;
-- store latched trigger words in a shift register that we report in a status register
process (clk_100)
begin
if rising_edge(clk_100) then
if rst_sync_clk100 = '1' then
latched_trig_word <= (others => '0');
elsif TrigWr(0) = '1' then
latched_trig_word <= latched_trig_word(23 downto 0) & TrigOutDat(0);
end if;
end if;
end process;
------------------------ wrap the main block design ----------------------------
main_bd_inst : entity work.main_bd
port map (
--configuration constants
gateway_ip_addr => GATEWAY_IP_ADDR,
subnet_mask => SUBNET_MASK,
tcp_port => TCP_PORT,
udp_port => UDP_PORT,
pcs_pma_an_adv_config_vector => PCS_PMA_AN_ADV_CONFIG_VECTOR,
pcs_pma_configuration_vector => PCS_PMA_CONFIGURATION_VECTOR,
--clocks
clk_125 => clk_125,
clk_axi => clk_100_axi,
clk_ref_200 => clk_200,
sfp_mgt_clk_clk_n => sfp_mgt_clkn,
sfp_mgt_clk_clk_p => sfp_mgt_clkp,
--resets
rst_pcs_pma => rst_pcs_pma,
rst_eth_mac => rst_eth_mac,
rst_cpld_bridge => rst_cpld_bridge,
rst_cfg_reader => rst_cfg_reader,
rst_comblock => rst_comblock,
rst_tcp_bridge => rst_tcp_bridge,
rst_udp_responder => rst_udp_responder,
rstn_axi => rstn_axi,
cfg_reader_done => cfg_reader_done,
--SFP
pcs_pma_mmcm_locked => mgt_clk_locked,
pcs_pma_status_vector => pcs_pma_status_vector,
sfp_rxn => sfp_rxn,
sfp_rxp => sfp_rxp,
sfp_txn => sfp_txn,
sfp_txp => sfp_txp,
comms_active => comms_active,
ethernet_mm2s_err => ethernet_mm2s_err,
ethernet_s2mm_err => ethernet_s2mm_err,
--CPLD interface
cfg_act => cfg_act,
cfg_clk => clk_100_skewed,
cfg_err => cfg_err,
cfg_rdy => cfg_rdy,
cfgd => cfgd(15 downto 0),
fpga_cmdl => fpga_cmdl,
fpga_rdyl => fpga_rdyl,
stat_oel => stat_oel,
-- XADC Pins
XADC_Vp_Vn_v_n => vn,
XADC_Vp_Vn_v_p => vp,
-- CSR registers
status => status,
control => control,
resets => resets,
trigger_interval => trigger_interval,
SATA_status => SATA_status,
build_timestamp => BUILD_TIMESTAMP,
git_sha1 => GIT_SHA1,
tdm_version => TDM_VERSION,
trigger_word => latched_trig_word,
uptime_nanoseconds => uptime_nanoseconds,
uptime_seconds => uptime_seconds
);
--up time registers
up_time_counters : process(clk_100_axi)
constant CLKS_PER_SEC : natural := 100_000_000;
constant NS_PER_CLK : natural := 10;
variable roll_over_ct : unsigned(31 downto 0);
variable seconds_ct : unsigned(31 downto 0);
variable nanoseconds_ct : unsigned(31 downto 0);
begin
if rising_edge(clk_100_axi) then
if rst_sync_clk_100_axi = '1' then
roll_over_ct := to_unsigned(CLKS_PER_SEC-2, 32);
seconds_ct := (others => '0');
nanoseconds_ct := (others => '0');
uptime_seconds <= (others => '0');
uptime_nanoseconds <= (others => '0');
else
--Output registers
uptime_seconds <= std_logic_vector(seconds_ct);
uptime_nanoseconds <= std_logic_vector(nanoseconds_ct);
--Check for roll-over
if roll_over_ct(roll_over_ct'high) = '1' then
roll_over_ct := to_unsigned(CLKS_PER_SEC-2, 32);
seconds_ct := seconds_ct + 1;
nanoseconds_ct := (others => '0');
else
nanoseconds_ct := nanoseconds_ct + NS_PER_CLK;
--Count down
roll_over_ct := roll_over_ct - 1;
end if;
end if;
end if;
end process;
end behavior;
|
mpl-2.0
|
777797ce396c28777ab00b3f83726d9f
| 0.629808 | 3.044236 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
fifo_vw_tb.vhd
| 1 | 7,609 |
-- fifo_vw testbench
-- Greg Stitt
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.tb_pkg.all;
entity fifo_vw_tb is
generic(
parallel_io : positive := 4;
data_width : positive := 8;
test_size : positive := 400;
input_delay_prob : real range 0.0 to 1.0 := 0.1;
min_input_delay : natural := 1;
max_input_delay : natural := 10;
output_delay_prob : real range 0.0 to 1.0 := 0.0;
min_output_delay : natural := 1;
max_output_delay : natural := 10
);
end fifo_vw_tb;
architecture TB of fifo_vw_tb is
-- ensure that that input size is a multiple of parallel_io. This will
-- round up test_size to the next multiple
constant adjusted_input_size : integer := integer(ceil(real(test_size) / real(parallel_io)))*parallel_io;
type data_array is array (0 to adjusted_input_size-1) of std_logic_vector(data_width-1 downto 0);
signal input_array : data_array;
signal output_array : data_array;
signal clk_en : std_logic := '1';
signal clk, rst, rd, wr : std_logic := '0';
signal empty, full : std_logic;
signal wr_amount : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0) := (others => '0');
signal valid_count : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0) := (others => '0');
signal input : std_logic_vector(parallel_io*data_width-1 downto 0) := (others => '0');
signal output : std_logic_vector(parallel_io*data_width-1 downto 0);
signal input_ready : std_logic := '0';
signal output_ready : std_logic := '0';
signal input_done : std_logic := '0';
signal all_outputs : boolean := false;
type count_array is array (0 to adjusted_input_size-1) of integer;
signal counts : count_array;
signal stall : std_logic := '0';
begin
U_FIFO_VW : entity work.fifo_vw
generic map(
data_width => data_width,
parallel_io => parallel_io)
port map(
clk => clk,
rst => rst,
rd => rd,
wr => wr,
valid_count => valid_count,
empty => empty,
full => full,
input => input,
output => output
);
clk <= not clk after 10 ns when clk_en = '1' else '0';
-- determine when to write
process(full, input_ready, rst, input_done)
begin
-- input_ready includes random delays
wr <= input_ready and not full and not rst and not input_done;
end process;
-- set the inputs during a write
process(clk, wr, rst)
variable input_count : integer := 0;
begin
if (rst = '1') then
input_count := 0;
for j in 0 to parallel_io-1 loop
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(j);
end loop;
-- set the inputs for each write
elsif (rising_edge(clk) and wr = '1' and rst = '0') then
input_count := input_count + to_integer(unsigned(valid_count));
-- write valid_count elements into the fifo
for j in 0 to parallel_io-1 loop
if (input_count + j < adjusted_input_size) then
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(input_count + j);
end if;
end loop;
if (input_count = adjusted_input_size) then
input_done <= '1';
end if;
end if;
end process;
-- randomly vary write timings
process
variable s1, s2 : positive; -- seeds for rand function
begin
input_ready <= '0';
wait until rst = '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
while (input_done = '0') loop
input_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, input_delay_prob, min_input_delay, max_input_delay);
input_ready <= '1';
wait until rising_edge(clk);
end loop;
input_ready <= '0';
wait;
end process;
-- initialize the simulation
process
variable rand : integer; -- random inputs to be written to fifo
variable s1, s2 : positive; -- seeds for rand function
variable input_count : integer;
begin
-- initialize inputs
for i in 0 to adjusted_input_size-1 loop
-- randomInt(s1, s2, 0, 2**data_width-1, rand);
-- input_array(i) <= std_logic_vector(to_unsigned(rand, data_width));
input_array(i) <= std_logic_vector(to_unsigned(i, data_width));
end loop;
--Reset the entity and initialize the wr and input to zero
rst <= '1';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
rst <= '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
wait;
end process;
-- randomly vary read timings
vary_read_timing : process
variable s1, s2 : positive; -- seeds for rand function
begin
while (not all_outputs) loop
output_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, output_delay_prob, min_output_delay, max_output_delay);
output_ready <= '1';
wait until rising_edge(clk);
end loop;
wait;
end process;
-- determine when reads occur
process(empty, output_ready)
begin
rd <= not empty and output_ready;
end process;
-- set write amounts
write_amounts : process(clk, rst)
variable s1, s2 : positive;
variable wr_amount_v : integer;
begin
if (rst = '1') then
randomInt(s1, s2, 0, parallel_io+1, wr_amount_v);
valid_count <= std_logic_vector(to_unsigned(wr_amount_v, valid_count'length));
elsif (rising_edge(clk) and wr = '1') then
randomInt(s1, s2, 0, parallel_io+1, wr_amount_v);
valid_count <= std_logic_vector(to_unsigned(wr_amount_v, valid_count'length));
end if;
end process;
check_outputs : process(clk)
variable out_ind_count : integer := 0;
variable output_temp : std_logic_vector(data_width-1 downto 0) := (others => '0');
begin
-- if there is a valid output, verify it
if (rising_edge(clk) and rd = '1') then
-- check the outputs
for i in 0 to parallel_io-1 loop
output_temp := output((parallel_io-i)*data_width-1 downto (parallel_io-i-1)*data_width);
assert(output_temp = input_array(out_ind_count)) report "Output incorrect.";
out_ind_count := out_ind_count + 1;
end loop;
end if;
if (out_ind_count = adjusted_input_size) then
report "SIMULATION COMPLETE!!!";
clk_en <= '0';
end if;
end process;
end TB;
|
gpl-3.0
|
dcd77b11163c1a2e6897cba985aa7d7c
| 0.540281 | 3.85461 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/GC_fifo/example_design/GC_fifo_top_wrapper.vhd
| 1 | 19,102 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: GC_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity GC_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(13-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end GC_fifo_top_wrapper;
architecture xilinx of GC_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component GC_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : GC_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
f746ed4db5bda956475752254626eb31
| 0.485394 | 3.972962 | false | false | false | false |
PiJoules/Zybo-Vision-Processing
|
hdmi_passthrough_720p.srcs/sources_1/ipshared/digilentinc.com/dvi2rgb_v1_4/4f0fd262/src/dvi2rgb.vhd
| 1 | 9,921 |
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
vid_pData(23 downto 16) <= pDataIn(2); -- red is channel 2
vid_pData(7 downto 0) <= pDataIn(1); -- green is channel 1
vid_pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
vid_pHSync <= pC0(0); -- channel 0 carries control signals too
vid_pVSync <= pC1(0); -- channel 0 carries control signals too
vid_pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
PixelClk <= PixelClk_int; -- pixel clock sourced from DVI link
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => "dgl_dvi_edid.txt") -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
unlicense
|
0d8d59e11d31cefccb66627c4c48c997
| 0.615765 | 4.479007 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/inst_cache_r2.vhd
| 1 | 9,161 |
------------------------------------------------------------------------------
-- Create/rivision Date: 7/13/2008, 7/15/2009, 6/28/2010
-- Design Name: Instruction Cache Emulator Unit
-- Module Name: inst_cache
-- Authors: Rahul P. Tekawade, Gandhi Puvvada
-- File: inst_cache_r2.vhd
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.std_logic_unsigned.all;
--synopsys translate_off
use work.instr_stream_pkg.all; -- instruction stream defining package
--synopsys translate_on
------------------------------------------------------------------------------
entity inst_cache is
generic (
DATA_WIDTH : integer := 128; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
Clk : in std_logic;
Resetb : in std_logic;
read_cache : in std_logic;
abort_prev_read : in std_logic; -- will be used under jump or successful branch
addr : in std_logic_vector (31 downto 0);
cd0 : out std_logic_vector (31 downto 0);
cd1 : out std_logic_vector (31 downto 0);
cd2 : out std_logic_vector (31 downto 0);
cd3 : out std_logic_vector (31 downto 0);
-- synopsys translate_off
registered_addr : out std_logic_vector(31 downto 0);
-- synopsys translate_on
read_hit : out std_logic;
fio_icache_addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
fio_icache_data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
fio_icache_wea : in std_logic;
fio_icache_data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
fio_icache_ena : in std_logic
);
end inst_cache;
------------------------------------------------------------------------------
architecture behv of inst_cache is
--constant DATA_WIDTH : integer := 128;
--constant ADDR_WIDTH : integer := 6;
signal count : std_logic_vector( 3 downto 0); -- count for latency
-- signal indx : std_logic_vector ( 3 downto 0); -- index to the register array contaning latencies
signal latency : std_logic_vector ( 3 downto 0); -- latency read from the latency register array
signal data_out : std_logic_vector(127 downto 0);
signal pending_req : std_logic; -- basically a new read_cache request is recorded as a pending request
signal read_hit_int : std_logic; -- internal signal for the output port read_hit
-- Type definition for latencies
-- Type definition for a 4-bit individual register for the register array.
subtype reg is std_logic_vector (3 downto 0);
-- Type definition of 16-latencies register array
type reg_array is array (0 to 15) of reg;
constant latency_array : reg_array := -- minimum latency = 0 after registering the request
-- ( X"7", --0 -- which guarantees the 1 clock delay due to BRAM
-- X"1", --1
-- X"2", --2
-- X"3", --3 -- however, the BRAM works like a pipeline
-- X"6", --4 -- if the latency is continuously 0 and if
-- X"6", --5 -- read_cache request is true continuously.
-- X"6", --6
-- X"7", --7
-- X"3", --8
-- x"1", --9
-- x"2", --10
-- X"6", --11
-- X"4", --12
-- X"5", --13
-- X"8", --14
-- X"7" --15
-- );
( X"3", --0 -- which guarantees the 1 clock delay due to BRAM
X"5", --1
X"0", --2
X"0", --3 -- however, the BRAM works like a pipeline
X"0", --4 -- if the latency is continuously 0 and if
X"0", --5 -- read_cache request is true continuously.
X"0", --6
X"5", --7
X"4", --8
x"9", --9
x"2", --10
X"7", --11
X"0", --12
X"0", --13
X"A", --14
X"7" --15
);
------
-- component declarations [ instruction memory]
component inst_cache_dpram is
generic (
DATA_WIDTH : integer := 128; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 -- defined as 6 in the instr_stream_pkg;
);
port (
Clka : in std_logic;
addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
wea : in std_logic;
data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
ena : in std_logic;
Clkb : in std_logic;
addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- data_in_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- web : in std_logic;
data_out_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component inst_cache_dpram;
begin -- begin of architecture
-- component port map
memory: inst_cache_dpram
generic map(DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH)
port map(Clka => Clk, addr_a => fio_icache_addr_a, data_in_a => fio_icache_data_in_a,
wea => fio_icache_wea, data_out_a => fio_icache_data_out_a, ena => fio_icache_ena,
Clkb=>Clk, addr_b=>addr(9 downto 4), data_out_b=>data_out);
-- note that we shall not be sending the registered address as we
-- do not want to create an additional pipeline stage!
read_hit <= read_hit_int ; -- read_hit port is assigned with internal read_hit_int
-------------------------------------------------------------------------------
pending_req_two_state_state_machine: process ( Clk, Resetb )
begin
if (Resetb = '0') then
pending_req <= '0';
elsif Clk'event and Clk = '1' then
case pending_req is
when '0' =>
if read_cache = '1' then
pending_req <= '1';
end if;
when others => -- i.e. when '1' =>
-- if ( ( (read_hit_int = '1') or (abort_prev_read = '1') ) and (read_cache = '0') ) then
if (read_cache = '0' ) then
pending_req <= '0';
end if;
end case;
end if;
end process pending_req_two_state_state_machine;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
register_addr_and_latecy: process ( Clk, Resetb )
begin
if (Resetb = '0') then
-- synopsys translate_off
registered_addr <= x"08080808"; -- actually does not need any initalization
-- synopsys translate_on
latency <= X"0"; -- actually does not need any initalization
count <= X"0";
-- indx <= X"0"; --
elsif ( Clk'event and Clk='1') then
if ( ( read_cache = '1') and
( (pending_req = '0') or (read_hit_int = '1') or (abort_prev_read = '1') )
) then -- i.e. a new request has been initiated;
-- we need to record the address of memory location to be read,
-- the latency pointed to by the index,
-- initiate count to zero, and
-- increment the index
-- synopsys translate_off
registered_addr <= addr(31 downto 0); -- need to change according to the width
-- synopsys translate_on
latency <= latency_array (CONV_INTEGER(unsigned(addr(9 downto 6))));
count <= X"0";
-- indx <= unsigned(indx) + 1; -- index will naturally roll over
elsif (pending_req = '1') then
count <= unsigned(count) + 1;
else
count <= X"0";
end if;
end if;
end process register_addr_and_latecy;
-------------------------------------------------------------------------------
read_hit_comb_process:
process (pending_req, latency, count, data_out)
begin
if ((pending_req = '1') and (latency = count)) then
read_hit_int <= '1';
cd0 <= data_out( 31 downto 0);
cd1 <= data_out( 63 downto 32);
cd2 <= data_out( 95 downto 64);
cd3 <= data_out( 127 downto 96);
else
read_hit_int <= '0';
cd0 <= (others => 'X'); -- don't care
cd1 <= (others => 'X'); -- don't care
cd2 <= (others => 'X'); -- don't care
cd3 <= (others => 'X'); -- don't care
end if;
end process read_hit_comb_process;
-------------------------------------------------------------------------------
end behv;
|
gpl-2.0
|
7abd4be2f57cb1599d1a8d881a251f89
| 0.477131 | 3.967518 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/ram_dp_sr_sw.vhd
| 1 | 4,716 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: ram_dp_sr_sw.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity ram_dp_sr_sw is
generic (
DATA_WIDTH :integer := 3;
ADDR_WIDTH :integer := 6
);
port (
-- Señales comunes:
rst : in std_logic; -- Reset
clk : in std_logic; -- Clock Input
-- Puerto 0 (solo escritura)
address_0 : in std_logic_vector (ADDR_WIDTH-1 downto 0); -- Dir. escritura (port 0)
data_0 : in std_logic_vector (DATA_WIDTH-1 downto 0); -- Dato escribir (port 0)
wr_0 : in std_logic; -- Write Enable (port 0)
-- Puerto 1 (solo lectura)
address_1 : in std_logic_vector (ADDR_WIDTH-1 downto 0); -- Dir. lectura (port 1)
data_1 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- Dato leído (port 1)
-- Puerto 2 (solo lectura)
address_2 : in std_logic_vector (ADDR_WIDTH-1 downto 0); -- Dir. lectura (port 2)
data_2 : out std_logic_vector (DATA_WIDTH-1 downto 0); -- Dato leído (port 2)
-- NOTA: metemos la direccion y da el dato en el siguiente ciclo(?)
-- Senales de depuracion:
bt_ld: in std_logic;
addr_db: out std_logic_vector(5 downto 0);
data_db: out std_logic_vector(2 downto 0)
);
end entity;
architecture rtl of ram_dp_sr_sw is
constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
signal data_1_out : std_logic_vector (DATA_WIDTH-1 downto 0);
signal data_2_out : std_logic_vector (DATA_WIDTH-1 downto 0);
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0); -- ORIGINAL
signal mem : RAM (0 to RAM_DEPTH-1); -- original
--Senales debug
signal cntr_db: std_logic_vector( 5 downto 0);
begin
-- Conexion de senales de depuracion
----------------------------------------------------------
addr_db <= cntr_db;
data_db <= mem(conv_integer(cntr_db));
-- Puerto_0: solo escritura
-------------------------------------------------------
MEM_WRITE_0: process (rst,clk) begin
if rst = '1' then
mem(0) <= "100";
mem(7) <= "010";
mem(63) <= "001";
elsif rising_edge(clk) then
if wr_0 = '1' then
mem(conv_integer(address_0)) <= data_0;
end if;
end if;
end process;
-- Puerto_1: solo lectura
-------------------------------------------------------
data_1 <= data_1_out;
MEM_READ_1: process (rst,clk) begin
if rising_edge(clk) then
data_1_out <= mem(conv_integer(address_1));
end if;
end process;
-- Puerto_2: solo lectura
-------------------------------------------------------
data_2 <= data_2_out;
MEM_READ_2: process (rst,clk) begin
if rising_edge(clk) then
data_2_out <= mem(conv_integer(address_2));
end if;
end process;
-- Contador de depuración
---------------------------------------------------------------
p_cntr_db: process(clk, rst, bt_ld)
begin
if rst = '1' then
cntr_db <= (others => '0');
elsif rising_edge(clk) then
if bt_ld = '1' then
cntr_db <= std_logic_vector(unsigned(cntr_db) + 1);
else
cntr_db <= cntr_db;
end if;
end if;
end process p_cntr_db;
-----------------------------------------------------------------
end architecture;
|
gpl-3.0
|
b9b0c25a8e98bf0fbda10d8998c6d26a
| 0.525445 | 3.790997 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_PRE_FIFO/example_design/RD_FLASH_PRE_FIFO_top.vhd
| 1 | 5,246 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RD_FLASH_PRE_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RD_FLASH_PRE_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RD_FLASH_PRE_FIFO_top;
architecture xilinx of RD_FLASH_PRE_FIFO_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component RD_FLASH_PRE_FIFO is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : RD_FLASH_PRE_FIFO PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
bf06790e97af91e560283315d4b1cc8d
| 0.5122 | 4.751812 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_FLASH_PRE_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,388 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RD_FLASH_PRE_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(8-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
5911e936a161c3590902869c30369568
| 0.50281 | 3.922838 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/rob_exercise.vhd
| 2 | 10,996 |
-- Modified by Da Cheng in Summer 2010
-------------------------------------------------------------------------------
-- Description:
-- Reorder buffer is to make sure that the instructions commit in order.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rob is
port( --inputs--
clk :in std_logic;
Resetb :in std_logic;
-- Interface with CDB
Cdb_Valid : in std_logic; -- signal to tell that the values coming on CDB is valid
Cdb_RobTag : in std_logic_vector(4 downto 0); -- Tag of the instruction which the the CDB is broadcasting
Cdb_SwAddr : in std_logic_vector (31 downto 0); -- to give the store wordaddr
--Interface with Dispatch unit
Dis_InstSw : in std_logic; -- signal that tells that the signal being dispatched is a store word
Dis_RegWrite : in std_logic; -- signal telling that the instruction is register writing instruction
Dis_InstValid : in std_logic; -- Signal telling that Dispatch unit is giving valid information
Dis_RobRdAddr : in std_logic_vector(4 downto 0); -- Actual Desitnation register number of the instruction being dispatched
Dis_NewRdPhyAddr : in std_logic_vector (5 downto 0); -- Current Physical Register number of dispatching instruction taken by the dispatch unit from the FRL
Dis_PrevPhyAddr : in std_logic_vector (5 downto 0); -- Previous Physical Register number of dispatch unit taken from CFC
Dis_SwRtPhyAddr : in std_logic_vector (5 downto 0); -- Physical Address number from where store word has to take the data
Rob_Full : out std_logic; -- Whether the ROB is Full or not
Rob_TwoOrMoreVacant : out std_logic; -- Whether there are two or more vacant spot in ROB. Useful because Dispatch is 2 stage and if there is
-- only 1 vacant spot and second stage is dispatching the insturction first stage should not
-- dispatch any new Instruction
--translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
Rob_Instruction : out std_logic_vector(31 downto 0);
--translate_on
-- Interface with store buffer
SB_Full : in std_logic; -- Tells the ROB that the store buffer is full
Rob_SwAddr : out std_logic_vector (31 downto 0); -- The address in case of sw instruction
Rob_CommitMemWrite : out std_logic; -- Signal to enable the memory for writing purpose
-- Interface with FRL and CFC
Rob_TopPtr : out std_logic_vector (4 downto 0); -- Gives the value of TopPtr pointer of ROB
Rob_BottomPtr : out std_logic_vector (4 downto 0); -- Gives the Bottom Pointer of ROB
Rob_Commit : out std_logic; -- FRL needs it to to add pre phy to free list cfc needs it to remove the latest cheackpointed copy
Rob_CommitRdAddr : out std_logic_vector(4 downto 0); -- Architectural register number of committing instruction
Rob_CommitRegWrite : out std_logic; -- Indicates that the instruction that is being committed is a register wrtiting instruction
Rob_CommitPrePhyAddr : out std_logic_vector(5 downto 0); -- pre physical addr of committing inst to be added to FRL
Rob_CommitCurrPhyAddr : out std_logic_vector (5 downto 0); -- Current Register Address of committing instruction to update retirment rat
Cdb_Flush : in std_logic; -- Flag indicating that current instruction is mispredicted or not
Cfc_RobTag : in std_logic_vector (4 downto 0) -- Tag of the instruction that has the checkpoint
);
end rob;
architecture rob_arch of rob is
subtype bit6 is std_logic_vector(5 downto 0);
type phy_reg is array(0 to 31) of bit6;
signal CurrPhyArray,PrePhyArray: phy_reg;
subtype bit5 is std_logic_vector(4 downto 0);
type rd_addr is array(0 to 31) of bit5;
signal RdAddrArray: rd_addr;
type bit1 is array (0 to 31) of std_logic;
signal RegWriteArray,CompleteArray,MemwriteArray: bit1;
type bit21 is array (0 to 31) of std_logic_vector (20 downto 0);
signal SwAddrArray: bit21; -- Used to store additional bits of store word address
type bit32 is array (0 to 31) of std_logic_vector (31 downto 0);
-- translate_off
signal Rob_Inst :bit32;
-- translate_on
signal Internal_Depth : std_logic_vector(4 downto 0);
signal TopPtr_temp, BottomPtr_temp : std_logic_vector(5 downto 0);
signal full,commit_s : std_logic;
begin
Rob_TopPtr <= TopPtr_temp(4 downto 0);
Rob_BottomPtr<=BottomPtr_temp(4 downto 0);
-- when an Instruction gets commited from the ROB all the Information related to thatInstrcution is Broadcasted to that it can be used by others
Rob_CommitRdAddr <= RdAddrArray(conv_integer(TopPtr_temp(4 downto 0)));
Rob_CommitRegWrite <= RegWriteArray(conv_integer(TopPtr_temp(4 downto 0)));
Rob_CommitCurrPhyAddr <= CurrPhyArray (conv_integer(TopPtr_temp(4 downto 0)));
Rob_CommitPrePhyAddr <= PrePhyArray (conv_integer(TopPtr_temp(4 downto 0)));
Rob_CommitMemWrite <= MemwriteArray (conv_integer(TopPtr_temp(4 downto 0))) and commit_s ;
-- translate_off
Rob_Instruction<=Rob_Inst(conv_integer(TopPtr_temp(4 downto 0)));
-- translate_on
Rob_SwAddr(31 downto 27)<= RdAddrArray(CONV_INTEGER(UNSIGNED(TopPtr_temp(4 downto 0))));
Rob_SwAddr (26 downto 21) <= PrePhyArray(CONV_INTEGER(UNSIGNED(TopPtr_temp(4 downto 0))));
Rob_SwAddr (20 downto 0) <= SwAddrArray(CONV_INTEGER(UNSIGNED(TopPtr_temp(4 downto 0))));
-- To determine whether the ROB is full or empty we use an additional bit. ROB becomes full if the MSB of the TopPtr and BottomPtr pointer differ
-- and all other bits are same
full <= '1' when ((TopPtr_temp xor BottomPtr_temp) = "100000") else
'0';
--Condition to Check whether there is more than 1 vacant spot in the ROB
Rob_TwoOrMoreVacant <= '0' when (BottomPtr_temp(4 downto 0)-TopPtr_temp(4 downto 0)>=30) else
'1';
Rob_Full <= full when commit_s = '0' else '0';
-- Task 1: commit_s signal need to be generated here.
-- Hint: think of all possibilities and conditions to commit one instruction.
commit_s <= CompleteArray(CONV_INTEGER(UNSIGNED(TopPtr_temp(4 downto 0))));
Rob_Commit <= commit_s;
-- Task 2.1: Internal_Depth signal need to be generated here.
-- Hint: Internal_Depth is used to update the bottom pointer when flush (in Task 2.2).
-- In phase 1, Cfc_RobTag is same as Cdb_RobTag. They differ in phase 2.
-- Make sure you understand why you generate internal_depth here, that is why you need it in task 2.2
Internal_Depth <= unsigned(BottomPtr_temp(4 downto 0)) - unsigned(Cdb_RobTag) ;
-- Handling the entry and exit of each instruction, and update TopPtr_temp/BottomPtr_temp signals
rob_entry_exit: process(clk,Resetb)
begin
if(Resetb = '0') then
BottomPtr_temp <= (others=>'0');
TopPtr_temp <= (others=>'0');
for I in 0 to 31 loop
RegWriteArray(I) <= '0';
CompleteArray(I) <= '0';
MemwriteArray(I) <= '0';
CurrPhyArray(I) <= (others => '-');
PrePhyArray(I) <= (others => '-');
RdAddrArray(I) <= (others => '-');
SwAddrArray(I) <= (others => '-');
-- translate_off
Rob_Inst(I) <= (others=>'0');
-- translate_on
end loop;
elsif(clk'event and clk = '1') then
-- Once the instruction has been commited, the complete bit of that instruction is set to 0 and TopPtr pointer is incremented by 1
if( commit_s = '1') then
CompleteArray(conv_integer(TopPtr_temp(4 downto 0))) <= '0';
TopPtr_temp <= TopPtr_temp + '1';
end if;
-- Whenever the dispatch unit dispatches one instruction, we take all the information from the dispatch unit and store it at the location
-- pointed by our BottomPtr pointer. Then we increment the BottomPtr pointer by 1
if(Dis_InstValid = '1' and (full='0' or (full = '1' and commit_s = '1'))) then
RegWriteArray(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0)))) <= Dis_RegWrite; -- make all TopPtr and BottomPtr 4 downto 0
MemwriteArray(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0)))) <= Dis_InstSw;
CompleteArray(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0)))) <= '0';
BottomPtr_temp <= BottomPtr_temp+1;
-- translate_off
Rob_Inst(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0)))) <= Dis_instruction ;
-- translate_on
if (Dis_InstSw = '0') then
CurrPhyArray(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0))))<= Dis_NewRdPhyAddr;
PrePhyArray(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0))))<= Dis_PrevPhyAddr;
RdAddrArray(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0)))) <= Dis_RobRdAddr;
else
CurrPhyArray(CONV_INTEGER(UNSIGNED(BottomPtr_temp(4 downto 0))))<= Dis_SwRtPhyAddr;
end if;
end if;
-- Whenever an insturction finishes execution it announced it on the CDB. We will go that that loction and mark it as complete. If it is a
-- store word instruction, we also need to store the store word address inside the ROB
if (Cdb_Valid = '1') then -- there is no harm doing it even when cfc jump is true
CompleteArray(CONV_INTEGER(UNSIGNED(Cdb_RobTag))) <= '1';
if (MemwriteArray(CONV_INTEGER(UNSIGNED(Cdb_RobTag))) = '1') then
RdAddrArray(CONV_INTEGER(UNSIGNED(Cdb_RobTag))) <= Cdb_SwAddr ( 31 downto 27);
PrePhyArray(CONV_INTEGER(UNSIGNED(Cdb_RobTag))) <= Cdb_SwAddr (26 downto 21);
SwAddrArray(CONV_INTEGER(UNSIGNED(Cdb_RobTag))) <= Cdb_SwAddr (20 downto 0);
end if;
end if;
-- Task 2.2: update bottom pointer using Internal_Depth from Task 2.1.
-- In case of CDB Flush, we move the bottom Pointer to the instruction that claims flush at CDB, by which we invalidate all the younger Instructions. Think about where you can find this instruction's tag in order to flush all its younger instructions.
if (Cdb_Flush = '1') then
BottomPtr_temp <= unsigned(BottomPtr_temp) - unsigned(Internal_Depth) ;
for i in 0 to 31 loop --conv_integer(Internal_Depth) loop
if (i <= conv_integer(Internal_Depth)) then
CompleteArray(conv_integer(BottomPtr_temp(4 downto 0) - i)) <= '0';
end if;
end loop;
-- CompleteArray(conv_integer(BottomPtr_temp(4 downto 0) - i)) <= '0';
-- RegWriteArray(conv_integer(BottomPtr_temp(4 downto 0) - i)) <= '0';
-- MemwriteArray(conv_integer(BottomPtr_temp(4 downto 0) - i)) <= '0';
-- Rob_Inst(conv_integer(BottomPtr_temp(4 downto 0) - i)) <= (others=>'0');
-- end loop;
end if;
end if;
end process;
end rob_arch;
|
gpl-2.0
|
41b769c0ca0b5409f5108c7611157337
| 0.655602 | 3.834031 | false | false | false | false |
csrhau/sandpit
|
VHDL/vga_bindisplay/init_funcs.vhdl
| 1 | 1,779 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
use std.textio.all;
package init_funcs is
function read_file(data_file_name: string) return vga_memory_ptr;
function chr(sl: std_logic) return character;
function str(slv: std_logic_vector) return string;
end package init_funcs;
package body init_funcs is
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function read_file(data_file_name: string) return vga_memory_ptr is
variable state_ptr : vga_memory_ptr;
variable data_line : line;
variable text_line : line;
variable pixel_value: natural range 255 downto 0;
file data_file : text open read_mode is data_file_name;
begin
state_ptr := new vga_memory;
for i in vga_memory'reverse_range loop -- range would operate downto, and reverse the image! (this took 3 hours)
readline(data_file, data_line);
read(data_line, pixel_value);
if pixel_value < 128 then
state_ptr(i) := '0';
else
state_ptr(i) := '1';
end if;
end loop;
return state_ptr;
end function read_file;
end package body init_funcs;
|
mit
|
118774a96c73f21516ae15e7ad15848b
| 0.59303 | 3.356604 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/mega_tb.vhd
| 2 | 5,259 |
-------------------------------------------------------------------------------
--
-- Design : Test Bench test_all_streams
-- Project : Tomasulo Processor
-- Company : University of Southern California
-- Module: mega_tb
-- File: mega_tb.vhd
-- Date: 7/26/08
-- BY: Prasanjeet Das
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- This testbench creates clk and Reset for the the Tomasulo top
--
library std,ieee, modelsim_lib;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
library ee560;
use ee560.all;
-----------------------------------------------------------------------------
entity mega_tb is
generic (ADDR_WIDTH: integer := 6; DATA_WIDTH: integer := 32);--added by Sabya: data cache width
end entity mega_tb;
--use work.instr_stream_pkg.all; -- added by Sabya: we have the mem signal here, which is the instruction memory. see if we can just use this signal or do we need to use signal spy?
architecture mega_tb_a of mega_tb is
-- local signals
signal clk, Reset : std_logic;
-- clock period
constant clk_period: time := 20 ns;
-- clock count signal to make it easy for debugging
signal clk_count: integer range 0 to 9999;
-- a 10% delayed clock for clock counting
signal clk_delayed10 : std_logic;
signal walking_led : std_logic;
signal fio_icache_addr_IM : std_logic_vector(5 downto 0); --changed by PRASANJEET
signal fio_icache_data_in_IM : std_logic_vector(127 downto 0); --changed by PRASANJEET
signal fio_icache_wea_IM : std_logic; --changed by PRASANJEET
signal fio_icache_data_out_IM : std_logic_vector(127 downto 0); --changed by PRASANJEET
signal fio_icache_ena_IM : std_logic; -- changed by PRASANJEET
signal fio_dmem_addr_DM : std_logic_vector(5 downto 0); --changed by PRASANJEET
signal fio_dmem_data_out_DM : std_logic_vector(31 downto 0); --changed by PRASANJEET
signal fio_dmem_data_in_DM : std_logic_vector(31 downto 0); --changed by PRASANJEET
signal fio_dmem_wea_DM : std_logic; --changed by PRASANJEET
--data types and signals for data and instruction memory
-- type ram_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
-- signal dram_array : ram_type;
signal dram_array : std_logic_vector (DATA_WIDTH*(2**ADDR_WIDTH)-1 downto 0);
-- component declarations
component tomasulo_top
port (
Reset : in std_logic;
--digi_address : in std_logic_vector(5 downto 0); -- input ID for the register we want to see
--digi_data : out std_logic_vector(31 downto 0); -- output data given by the register
clk : in std_logic;
--modified by Prasanjeet
-- signals corresponding to Instruction memory
fio_icache_addr_IM : in std_logic_vector(5 downto 0); --changed by PRASANJEET
fio_icache_data_in_IM : in std_logic_vector(127 downto 0); --changed by PRASANJEET
fio_icache_wea_IM : in std_logic; --changed by PRASANJEET
fio_icache_data_out_IM : out std_logic_vector(127 downto 0); --changed by PRASANJEET
fio_icache_ena_IM : in std_logic; -- changed by PRASANJEET
fio_dmem_addr_DM : in std_logic_vector(5 downto 0); --changed by PRASANJEET
fio_dmem_data_out_DM : out std_logic_vector(31 downto 0); --changed by PRASANJEET
fio_dmem_data_in_DM : in std_logic_vector(31 downto 0); --changed by PRASANJEET
fio_dmem_wea_DM : in std_logic; --changed by PRASANJEET
Test_mode : in std_logic; -- for using the test mode
walking_led_start : out std_logic
-- end modified by Prasanjeet
);
end component ;
begin
UUT: tomasulo_top port map (
Reset => Reset,
clk => clk,
fio_icache_addr_IM => fio_icache_addr_IM,
fio_icache_data_in_IM => fio_icache_data_in_IM,
fio_icache_wea_IM => fio_icache_wea_IM ,
fio_icache_data_out_IM => fio_icache_data_out_IM,
fio_icache_ena_IM => fio_icache_ena_IM,
fio_dmem_addr_DM => fio_dmem_addr_DM,
fio_dmem_data_out_DM => fio_dmem_data_out_DM,
fio_dmem_data_in_DM => fio_dmem_data_in_DM,
fio_dmem_wea_DM => fio_dmem_wea_DM,
Test_mode => '0',
walking_led_start => walking_led
-- end modified by Prasanjeet
);
clock_generate: process
begin
clk <= '0', '1' after (clk_period/2);
wait for clk_period;
end process clock_generate;
-- Reset activation and inactivation
reset_process : process
begin
Reset <= '1' ;
wait for 80.1 ns ;
Reset <= '0';
wait;
end process;
clk_delayed10 <= clk after (clk_period/10);
-- clock count processes
clk_count_process: process (clk_delayed10, Reset)
begin
if Reset = '1' then
clk_count <= 0;
elsif clk_delayed10'event and clk_delayed10 = '1' then
clk_count <= clk_count + 1;
end if;
end process clk_count_process;
end architecture mega_tb_a;
|
gpl-2.0
|
5007100d02e02feb44b9f89c3c0a4ed8
| 0.592508 | 3.672486 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/TX_SEND_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,248 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT TX_SEND_FIFO_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
739cb7b2d977a05d8a0746b9b92a175b
| 0.504445 | 3.930119 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_rec_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,650 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_rec_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
5676c015b36800951067fbff2e4a676e
| 0.502318 | 3.92388 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
left_shift.vhd
| 1 | 3,836 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity left_shift is
generic (
SHIFT_BITS : positive := 1;
WORD_WIDTH : positive := 8;
NUM_WORDS : positive := 2);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic := '1';
input : in std_logic_vector(WORD_WIDTH*NUM_WORDS-1 downto 0);
shift_amount : in std_logic_vector(SHIFT_BITS-1 downto 0);
output : out std_logic_vector(WORD_WIDTH*NUM_WORDS-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic);
end left_shift;
architecture DEFAULT of left_shift is
constant LEVELS : positive := SHIFT_BITS;
type word_array is array (0 to LEVELS-1, 0 to NUM_WORDS-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
signal words : word_array;
type input_array is array (0 to NUM_WORDS-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
signal inputs : input_array;
type shift_array is array (0 to LEVELS-1) of std_logic_vector(SHIFT_BITS-1 downto 0);
signal shift : shift_array;
begin
-- convert input vector into 2d array
process(input)
begin
for i in 0 to NUM_WORDS-1 loop
inputs(i) <= input(input'length-i*WORD_WIDTH-1 downto input'length-(i+1)*WORD_WIDTH);
end loop;
end process;
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to LEVELS-1 loop
for j in 0 to NUM_WORDS-1 loop
words(i, j) <= (others => '0');
end loop;
shift(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
-- level 0
for j in 0 to NUM_WORDS-1 loop
if (en = '1') then
if (shift_amount(LEVELS-1) = '1') then
if (j+2**(LEVELS-1) >= NUM_WORDS) then
words(0, j) <= (others => '0');
else
words(0, j) <= inputs(j+2**(LEVELS-1));
end if;
else
words(0, j) <= inputs(j);
end if;
shift(0) <= shift_amount;
end if;
end loop;
for i in 1 to LEVELS-1 loop
shift(i) <= shift(i-1);
for j in 0 to NUM_WORDS-1 loop
if (en = '1') then
if (shift(i-1)(LEVELS-i-1) = '1') then
-- if word to shift from doesn't exist, shift in 0
-- else, shift in words based on the level
if (j+2**(LEVELS-i-1) >= NUM_WORDS) then
words(i, j) <= (others => '0');
else
words(i, j) <= words(i-1, j+2**(LEVELS-i-1));
end if;
else
words(i, j) <= words(i-1, j);
end if;
end if;
end loop;
end loop;
end if;
end process;
process(words)
begin
for i in 0 to NUM_WORDS-1 loop
output((NUM_WORDS-i)*WORD_WIDTH-1 downto (NUM_WORDS-i-1)*WORD_WIDTH) <= words(LEVELS-1, i);
end loop;
end process;
U_DELAY : entity work.delay
generic map (
width => 1,
cycles => LEVELS,
init => "0")
port map (
clk => clk,
rst => rst,
en => en,
input(0) => valid_in,
output(0) => valid_out);
end DEFAULT;
|
gpl-3.0
|
fe93f3cf4cd14fb378ed50496ca0b021
| 0.436131 | 3.987526 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_3/CFC_exerceise/Cfc_withBRAM.vhd
| 1 | 16,602 |
-------------------------------------------------------------------------------
--
-- Design : CFC Unit
-- Project : Tomasulo Processor
-- Entity : CFC
-- Author : Rajat Shah
-- Company : University of Southern California
-- Last Updated : April 15th, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cfc is
port ( --global signals
Clk :in std_logic; --Global Clock Signal
Resetb :in std_logic; --Global Reset Signal
--interface with dispatch unit
Dis_InstValid :in std_logic; --Flag indicating if the instruction dispatched is valid or not
Dis_CfcBranchTag :in std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
Dis_CfcRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address
Dis_CfcRsAddr :in std_logic_vector(4 downto 0); --Rs Logical Address
Dis_CfcRtAddr :in std_logic_vector(4 downto 0); --Rt Logical Address
Dis_CfcNewRdPhyAddr :in std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
Dis_CfcRegWrite :in std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
Dis_CfcBranch :in std_logic; --Flag indicating whether current instruction being dispatched is branch or not
Dis_Jr31Inst :in std_logic; --Flag indicating if the current instruction is Jr 31 or not
Cfc_RdPhyAddr :out std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
Cfc_RsPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
Cfc_RtPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
Cfc_Full :out std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
Rob_TopPtr :in std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
Rob_Commit :in std_logic; --Flag indicating whether instruction is committing in this cycle or not
Rob_CommitRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
Rob_CommitRegWrite :in std_logic; --Indicates if instruction is writing to register or not
Rob_CommitCurrPhyAddr :in std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag :out std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
Frl_HeadPtr :in std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
Cfc_FrlHeadPtr :out std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cdb_RobTag :in std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
Cdb_RobDepth :in std_logic_vector(4 downto 0) --Depth of mispredicted branch from ROB Top
);
end cfc;
architecture cfc_arch of cfc is
--Signal declaration for 8 copies of checkpoints - Each 32 deep and 6 bit wide
type cfc_checkpoint_type is array(0 to 255) of std_logic_vector(5 downto 0);
signal Cfc_RsList, Cfc_RtList, Cfc_RdList : cfc_checkpoint_type; --3 BRAM, each containing flattened 8 tables
--Signal declaration for committed checkpoint (Retirement RAT) - 32 deep and 6 bit wide
type committed_type is array(0 to 31) of std_logic_vector(5 downto 0);
signal Committed_RsList, Committed_RtList, Committed_RdList : committed_type :=(
"000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111"); -- 3 copies of committed list initialize to 0 to 31
--Signal declaration for 8 copies of Dirty Flag Array(DFA) validating each checkpoints - Each 32 deep and 1 bit wide
type dfa_checkpoint_type is array(0 to 31) of std_logic;
type dfa_array_type is array (0 to 7) of dfa_checkpoint_type;
signal Dfa_List : dfa_array_type;
type checkpoint_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Checkpoint_TagArray: checkpoint_tag_type; --8 deep and 5 bit wide array for storing ROB tag of checkpointed branch instructions
type Frl_HeadPtrArray_type is array (0 to 7) of std_logic_vector (4 downto 0);
signal Frl_HeadPtrArray: Frl_HeadPtrArray_type;
type depth_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Depth_Array: depth_tag_type;
type Cfc_Valid_Array_type is array (0 to 7) of std_logic;
signal Cfc_ValidArray: Cfc_Valid_Array_type;
signal Full, Empty : std_logic; --flag indicating if all 8 checkpoints are used or empty
signal Head_Pointer, Tail_Pointer: std_logic_vector(2 downto 0); --Head Pointer indicates active checkpoint while tail pointer indicates oldest uncommitted branch
signal Checkpoint_MatchArray: std_logic_vector (7 downto 0); --Array indicating if the instruction on CDB matches any checkpointed branch
signal DFA_RsValid, DFA_RtValid, DFA_RdValid: std_logic;
signal Cfc_RsList_temp, Cfc_RtList_temp, Cfc_RdList_temp: std_logic_vector (5 downto 0);
signal Committed_RsList_temp, Committed_RtList_temp, Committed_RdList_temp: std_logic_vector (5 downto 0);
signal Next_Head_Pointer: std_logic_vector (2 downto 0); --Temporary Head_pointer generated during CDB Flush
begin
Depth_Array(0) <= Checkpoint_TagArray(0) - Rob_TopPtr; -- std_logic_vector is treated as unsigned because of library declaration IEEE_STD_LOGIC_UNSIGNED
Depth_Array(1) <= Checkpoint_TagArray(1) - Rob_TopPtr;
Depth_Array(2) <= Checkpoint_TagArray(2) - Rob_TopPtr;
Depth_Array(3) <= Checkpoint_TagArray(3) - Rob_TopPtr;
Depth_Array(4) <= Checkpoint_TagArray(4) - Rob_TopPtr;
Depth_Array(5) <= Checkpoint_TagArray(5) - Rob_TopPtr;
Depth_Array(6) <= Checkpoint_TagArray(6) - Rob_TopPtr;
Depth_Array(7) <= Checkpoint_TagArray(7) - Rob_TopPtr;
--Combinational assignment determining if the instruction on CDB is a frozen branch or not
Checkpoint_MatchArray(0) <= '1' when ((Checkpoint_TagArray(0) = Cdb_RobTag) and (Cfc_ValidArray(0) = '1')) else
'0';
Checkpoint_MatchArray(1) <= '1' when ((Checkpoint_TagArray(1) = Cdb_RobTag) and (Cfc_ValidArray(1) = '1')) else
'0';
Checkpoint_MatchArray(2) <= '1' when ((Checkpoint_TagArray(2) = Cdb_RobTag) and (Cfc_ValidArray(2) = '1')) else
'0';
Checkpoint_MatchArray(3) <= '1' when ((Checkpoint_TagArray(3) = Cdb_RobTag) and (Cfc_ValidArray(3) = '1')) else
'0';
Checkpoint_MatchArray(4) <= '1' when ((Checkpoint_TagArray(4) = Cdb_RobTag) and (Cfc_ValidArray(4) = '1')) else
'0';
Checkpoint_MatchArray(5) <= '1' when ((Checkpoint_TagArray(5) = Cdb_RobTag) and (Cfc_ValidArray(5) = '1')) else
'0';
Checkpoint_MatchArray(6) <= '1' when ((Checkpoint_TagArray(6) = Cdb_RobTag) and (Cfc_ValidArray(6) = '1')) else
'0';
Checkpoint_MatchArray(7) <= '1' when ((Checkpoint_TagArray(7) = Cdb_RobTag) and (Cfc_ValidArray(7) = '1')) else
'0';
Cfc_Full <= Full;
--Task 0: Complete the Full and empty conditions depending on the Head_Pointer and Tail_pointer values
Full <= ; --Flag indicating that all 8 checkpoints (7 frozen + 1 Active) are being used //if HP - TP =
Empty <= ; --Flag indicating that there is no frozen checkpoint //if HP - TP = 0
Cfc_FrlHeadPtr <= Frl_HeadPtrArray(conv_integer(Next_Head_Pointer));
Cfc_RobTag <= Checkpoint_Tagarray(conv_integer(Next_Head_Pointer));
CfcUpdate: process (Clk, Resetb)
begin
if(Resetb = '0') then
Head_Pointer <= "000"; --Here the Head_Pointer points to the active checkpoint and not to the empty location
Tail_Pointer <= "000";
for I in 0 to 7 loop
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
Cfc_ValidArray(I) <= '0';
end loop;
elsif (Clk'event and Clk = '1') then
--Releasing the oldest checkpoint if the branch reaches top of ROB
if ((Rob_Commit = '1') and (Rob_TopPtr = Checkpoint_TagArray(conv_integer(Tail_Pointer))) and ((Tail_Pointer - Next_Head_Pointer) /= "00")) then
Tail_Pointer <= Tail_Pointer + '1';
Cfc_ValidArray(conv_integer(Tail_Pointer)) <= '0';
for I in 0 to 31 loop
Dfa_List(conv_integer(Tail_Pointer))(I) <= '0';
end loop;
end if;
if (Cdb_Flush = '1') then
---- ADDED BY MANPREET--- need to invalidate the active rat dfa bits
for J in 0 to 31 loop
Dfa_List(conv_integer(Head_Pointer))(J) <= '0';
end loop;
-----------------------------
for I in 0 to 7 loop
-- changed by Manpreet.. shouldnt invalidate the rat corresponding to branch_tag = cdb_robtag as
-- it contains instructions before the flushed branch and will become the active rat
if (Cdb_RobDepth < Depth_Array(I)) then --Invalidating all the younger checkpoints and clearing the Dfa_List
Cfc_ValidArray(I)<='0';
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
end if;
if (Cdb_RobDepth = Depth_Array(I)) then
Cfc_ValidArray(I)<='0';
end if ;
end loop;
Head_Pointer <= Next_Head_Pointer;
else
-- Task 1: Update the DFA bit of the Active Checkpoint on dispatch of Register Writing Instruction
-- Task 2: Create a new checkpoint for dispatched branch (i.e. freeze the active checkpoint)
if ((Dis_CfcBranch = '1' or Dis_Jr31Inst = '1')and Dis_InstValid = '1' and ((Full /= '1') or ((Rob_Commit = '1') and --not full, TP? ))) then -- Task 2.1 - some conditions missing - think structural hazard - can't dispatch branch if all checkpoints are in use. But what if a branch is committing as well?
-- Task 2.2 - what things need to be done for a new checkpoint? Tagarray, validarray, FRL headpointer and the headpointer should be updated.
--//store ROBtag, make things valid/invalid, move HP
end if;
end if;
end if;
end process;
--Combinational Process to determine new head pointer during branch misprediction
CDB_Flush_Process: process (Cdb_Flush, Checkpoint_MatchArray, Frl_HeadPtrArray, Checkpoint_TagArray, Head_Pointer)
begin
Next_Head_Pointer <= Head_Pointer;
if (Cdb_Flush = '1') then
Case Checkpoint_MatchArray is --Case statement to move the head pointer on branch misprediction to corresponding frozen checkpoint
when "00000001" =>
Next_Head_Pointer <= "000";
when "00000010" =>
Next_Head_Pointer <= "001";
when "00000100" =>
Next_Head_Pointer <= "010";
when "00001000" =>
Next_Head_Pointer <= "011";
when "00010000" =>
Next_Head_Pointer <= "100";
when "00100000" =>
Next_Head_Pointer <= "101";
when "01000000" =>
Next_Head_Pointer <= "110";
when "10000000" =>
Next_Head_Pointer <= "111";
when others =>
Next_Head_Pointer <= "XXX";
end case;
end if;
end process;
--Process to find the latest value of Rs to be given to Dispatch
Dispatch_RsRead_Process: process (Clk,Resetb)
variable found_Rs1, found_Rs2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RsPointer: std_logic_vector(2 downto 0);
begin
if (Resetb = '0') then
Committed_RsList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rs1 := '1';
exit;
else
found_Rs1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rs2 := '1';
exit;
else
found_Rs2 := '0';
end if;
end if;
end loop;
-- Task 3: Use found_Rs1, found_Rs2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rspointer and Dfa_RsValid
-- Dfa_RsValid tells if the Rs register is present in any of the 8 checkpoints or not
-- BRAM_Rspointer gives which checkpoint it is present in. Set it to "000" by default.
--//combinational for loop for HP and 7downto0, compare each dirty flag to extract info from where to to read value
--//Rs1 high, don't need to look at Rs2 (shown above?)
--//two indexes for which copy and which register
--//found_Rs1/2, BRAM_pointer1/2 (use conv_std_logic_vector to find index from variables BRAM_pointers)
--//if found_Rd1 = 1, don't neeed to go to Rd2 (if else loop)
-- Task 4: Update Committed_Rslist when a register-writing instruction is committed
--//
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RsList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RsList_temp <= Cfc_RsList(conv_integer(BRAM_RsPointer & Dis_CfcRsAddr)); --concatenating the pointer & logical Rs address value to read BRAM
Committed_RsList_temp <= Committed_RsList(conv_integer(Dis_CfcRsAddr));
end if;
end if;
end process;
process (Dfa_RsValid, Cfc_RsList_temp, Committed_RsList_temp)--mux to select between the checkpoint value or committed value
begin
if (Dfa_RsValid = '1') then
Cfc_RsPhyAddr <= Cfc_RsList_temp;
else
Cfc_RsPhyAddr <= Committed_RsList_temp;
end if;
end process;
-- Task 5: same process as above for finding the latest value of Rt
Dispatch_RtRead_Process: process(Clk,Resetb)
variable found_Rt1, found_Rt2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RtPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RtList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
end if;
end process;
process (Dfa_RtValid, Cfc_RtList_temp, Committed_RtList_temp)
begin
if (Dfa_RtValid = '1') then
Cfc_RtPhyAddr <= Cfc_RtList_temp;
else
Cfc_RtPhyAddr <= Committed_RtList_temp;
end if;
end process;
-- Task 6: same process as above for finding the latest value of Rd
Dispatch_RdRead_Process: process(Clk,Resetb)
variable found_Rd1, found_Rd2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RdPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RdList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
end if;
end process;
process (Dfa_RdValid, Cfc_RdList_temp, Committed_RdList_temp)
begin
if (Dfa_RdValid = '1') then
Cfc_RdPhyAddr <= Cfc_RdList_temp;
else
Cfc_RdPhyAddr <= Committed_RdList_temp;
end if;
end process;
end cfc_arch;
|
gpl-2.0
|
e15422f60afcdc93fbb00e6f9a029cbf
| 0.658836 | 3.643186 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RX_RECV_FIFO/example_design/RX_RECV_FIFO_top.vhd
| 1 | 4,786 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RX_RECV_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RX_RECV_FIFO_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end RX_RECV_FIFO_top;
architecture xilinx of RX_RECV_FIFO_top is
SIGNAL clk_i : std_logic;
component RX_RECV_FIFO is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : RX_RECV_FIFO PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
790f62e17602bb146a5708184136ee45
| 0.526118 | 4.913758 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/simulation/fg_tb_top.vhd
| 1 | 6,020 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
CONSTANT rd_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
310f502690c37770679611c64aa3cd9d
| 0.61196 | 4.095238 | false | false | false | false |
gxliu/ARM-Cortex-M0
|
hdl/mcu.vhd
| 1 | 19,507 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mcu is
port ( clk : in std_logic;
rst : in std_logic;
instr : out std_logic_vector(31 downto 0));
end mcu;
architecture Behavioral of mcu is
component memory_no_clk is
generic ( N : integer);
port ( clk : in std_logic;
write_en: in std_logic;
addr_1 : in std_logic_vector (31 downto 0);
addr_2 : in std_logic_vector (31 downto 0);
data_w2 : in std_logic_vector (31 downto 0);
data_r1 : out std_logic_vector (31 downto 0);
data_r2 : out std_logic_vector (31 downto 0));
end component memory_no_clk;
component regfile_no_clk is
port ( clk : in std_logic;
write_en: in std_logic;
addr_r1 : in std_logic_vector (3 downto 0);
addr_r2 : in std_logic_vector (3 downto 0);
addr_w1 : in std_logic_vector (3 downto 0);
data_w1 : in std_logic_vector (31 downto 0);
pc_next : in std_logic_vector (31 downto 0);
data_r1 : out std_logic_vector (31 downto 0);
data_r2 : out std_logic_vector (31 downto 0);
data_pc : out std_logic_vector (31 downto 0));
end component regfile_no_clk;
component alu is
port ( input_1 : in std_logic_vector (31 downto 0);
input_2 : in std_logic_vector (31 downto 0);
funct : in std_logic_vector (4 downto 0);
flags_current : in std_logic_vector(3 downto 0);
output : out std_logic_vector (31 downto 0);
flags_next : out std_logic_vector (3 downto 0);
flags_update : out std_logic_vector (1 downto 0));
end component alu;
signal instruction_fetched : std_logic_vector (31 downto 0) := (others=>'0');
signal pc_current, pc_next, pc_shifted, pc_plus4 : std_logic_vector (31 downto 0) := (others=>'0');
signal cond_branch : std_logic;
signal reg_read_addr_1, reg_read_addr_2, reg_write_addr : std_logic_vector (3 downto 0) := (others=>'0');
signal reg_read_data_1, reg_read_data_2, reg_write_data, reg_write_data_pre : std_logic_vector (31 downto 0) := (others=>'0');
signal reg_write_enable : std_logic := '1';
signal mem_output : std_logic_vector (31 downto 0) := (others=>'0');
signal mem_write_data : std_logic_vector (31 downto 0) := (others=>'0');
signal mem_write_enable : std_logic := '1';
signal flags_current, flags_next : std_logic_vector (3 downto 0) := (others=>'0');
signal flags_update : std_logic_vector (1 downto 0) := (others=>'0');
signal alu_function : std_logic_vector (4 downto 0) := (others=>'0');
signal alu_input_1, alu_input_2, alu_output, alu_output_shifted : std_logic_vector (31 downto 0) := (others=>'0');
signal instr_ok, instr_0, instr_1, instr_2, instr_3, instr_4, instr_5, instr_6, instr_7, instr_8, instr_9 : std_logic;
signal instr_10, instr_11, instr_12, instr_13, instr_14, instr_15, instr_16, instr_17, instr_18, instr_19 : std_logic;
signal stack_finished : std_logic := '0';
signal stack_started : std_logic := '0';
signal listofreg : std_logic_vector (8 downto 0) := (others=>'0');
signal increasedpointer : std_logic_vector (3 downto 0);
begin
--USELESS
instr <= instruction_fetched;
--END
pc_shifted <= "00" & pc_current(31 downto 2);
alu_output_shifted <= "00" & alu_output(31 downto 2);
memory_block : memory_no_clk
generic map (
N => 29
)
port map (
clk => clk ,
write_en=> mem_write_enable ,
addr_1 => pc_shifted ,
addr_2 => alu_output_shifted ,
data_w2 => mem_write_data ,
data_r1 => instruction_fetched ,
data_r2 => mem_output
);
register_block : regfile_no_clk port map (
clk => clk ,
write_en=> reg_write_enable ,
addr_r1 => reg_read_addr_1 ,
addr_r2 => reg_read_addr_2 ,
addr_w1 => reg_write_addr ,
data_w1 => reg_write_data ,
pc_next => pc_next ,
data_r1 => reg_read_data_1 ,
data_r2 => reg_read_data_2 ,
data_pc => pc_current
);
alu_block : alu port map (
input_1 => alu_input_1 ,
input_2 => alu_input_2 ,
funct => alu_function ,
flags_current => flags_current ,
output => alu_output ,
flags_next => flags_next ,
flags_update => flags_update
);
--PC updating block
pc_plus4 <= std_logic_vector( unsigned(pc_current) + 4 );
pc_next <= "00000000000000000000000000000000" when rst = '1' else --reset
"00000000000000000000000000001000" when instr_17 = '1' else --SWI int
pc_current when instr_14 = '1' and stack_finished = '0' else
reg_read_data_2 when instr_5 = '1' and instruction_fetched(9 downto 8) = "11" else
alu_output when (instr_16 = '1' and cond_branch = '1') or instr_18 = '1' else
pc_plus4;
cond_branch <= '1' when (instruction_fetched(11 downto 8) = "0000" and flags_current(2) = '1') or
(instruction_fetched(11 downto 8) = "0001" and flags_current(2) = '0') or
(instruction_fetched(11 downto 8) = "0010" and flags_current(1) = '1') or
(instruction_fetched(11 downto 8) = "0011" and flags_current(1) = '0') or
(instruction_fetched(11 downto 8) = "0100" and flags_current(3) = '1') or
(instruction_fetched(11 downto 8) = "0101" and flags_current(3) = '0') or
(instruction_fetched(11 downto 8) = "0110" and flags_current(0) = '1') or
(instruction_fetched(11 downto 8) = "0111" and flags_current(0) = '0') or
(instruction_fetched(11 downto 8) = "1000" and flags_current(1) = '1' and flags_current(2) = '0') or
(instruction_fetched(11 downto 8) = "1001" and (flags_current(1) = '0' or flags_current(2) = '1')) or
(instruction_fetched(11 downto 8) = "1010" and flags_current(3) = flags_current(0)) or
(instruction_fetched(11 downto 8) = "1011" and flags_current(3) /= flags_current(0)) or
(instruction_fetched(11 downto 8) = "1100" and flags_current(2) = '0' and flags_current(3) = flags_current(0)) or
(instruction_fetched(11 downto 8) = "1101" and flags_current(2) = '1' and flags_current(3) /= flags_current(0))
else '0';
--Flags updating block
--flag_current(3) == N , flag_current(2) == Z , flag_current(1) == C , flag_current(0) == V
process(clk)
begin
if rising_edge(clk) then
case flags_update is --Update mode for flags 0:none 1:NZ 2:NZC 3:NZCV
when "01" => flags_current <= flags_next(3 downto 2) & flags_current(1 downto 0);
when "10" => flags_current <= flags_next(3 downto 1) & flags_current(0);
when "11" => flags_current <= flags_next;
when others => flags_current <= flags_current;
end case;
end if;
end process;
--Multiple push/pop
process(clk)
begin
if rising_edge(clk) then
if instr_14 = '1' then
if stack_started = '0' then
listofreg <= instruction_fetched(8 downto 0);
stack_started <= '1';
else
if listofreg(8) = '1' then
listofreg(8) <= '0';
if listofreg(7) = '0' and listofreg(6) = '0' and listofreg(5) = '0' and listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then
stack_finished <= '1';
end if;
elsif listofreg(7) = '1' then
listofreg(7) <= '0';
if listofreg(6) = '0' and listofreg(5) = '0' and listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then
stack_finished <= '1';
end if;
elsif listofreg(6) = '1' then
listofreg(6) <= '0';
if listofreg(5) = '0' and listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then
stack_finished <= '1';
end if;
elsif listofreg(5) = '1' then
listofreg(5) <= '0';
if listofreg(4) = '0' and listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then
stack_finished <= '1';
end if;
elsif listofreg(4) = '1' then
listofreg(4) <= '0';
if listofreg(3) = '0' and listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then
stack_finished <= '1';
end if;
elsif listofreg(3) = '1' then
listofreg(3) <= '0';
if listofreg(2) = '0' and listofreg(1) = '0' and listofreg(0) = '0' then
stack_finished <= '1';
end if;
elsif listofreg(2) = '1' then
listofreg(2) <= '0';
if listofreg(1) = '0' and listofreg(0) = '0' then
stack_finished <= '1';
end if;
elsif listofreg(1) = '1' then
listofreg(1) <= '0';
if listofreg(0) = '0' then
stack_finished <= '1';
end if;
else
listofreg(0) <= '0';
stack_finished <= '1';
end if;
end if;
else
stack_started <= '0';
stack_finished <= '0';
end if;
end if;
end process;
increasedpointer <= "1111" when listofreg(8) = '1' and instruction_fetched(11) = '0' else
"1110" when listofreg(8) = '1' and instruction_fetched(11) = '1' else
"0111" when listofreg(7) = '1' else
"0110" when listofreg(6) = '1' else
"0101" when listofreg(5) = '1' else
"0100" when listofreg(4) = '1' else
"0011" when listofreg(3) = '1' else
"0010" when listofreg(2) = '1' else
"0001" when listofreg(1) = '1' else
"0000";
--Register address decoding
reg_read_addr_1 <= '0' & instruction_fetched(5 downto 3) when instr_1 = '1' or instr_2 = '1' or instr_7 = '1' else
'0' & instruction_fetched(10 downto 8) when instr_3 = '1' else
'0' & instruction_fetched(2 downto 0) when instr_4 = '1' or instr_9 = '1' or instr_10 = '1' else
instruction_fetched(7) & instruction_fetched(2 downto 0) when instr_5 = '1' else --high reg
"1101" when instr_11 = '1' or (instr_12 = '1' and instruction_fetched(11) ='1') or instr_13 = '1' or instr_14 = '1' else --SP
"1111" when instr_16 = '1' or instr_18 = '1' else --PC
(others=>'0');
reg_read_addr_2 <= '0' & instruction_fetched(8 downto 6) when (instr_2 ='1' and instruction_fetched(10) ='0') or instr_7 = '1' else
'0' & instruction_fetched(5 downto 3) when instr_4 ='1' or instr_9 = '1' or instr_10 = '1' else
instruction_fetched(6 downto 3) when instr_5 = '1' else --high reg
increasedpointer when instr_14 = '1' and instruction_fetched(11) = '0' else
(others=>'0');
--ALU input
alu_input_1 <= pc_plus4 when instr_6 = '1' or (instr_12 = '1' and instruction_fetched(11) ='0') else
"000000000000000000000000000" & instruction_fetched(10 downto 6) when (instr_9 = '1' and instruction_fetched(12) ='1') else
"0000000000000000000000000" & instruction_fetched(10 downto 6) & "00" when (instr_9 = '1' and instruction_fetched(12) ='0') else
"00000000000000000000000000" & instruction_fetched(10 downto 6) & "0" when instr_10 = '1' else
reg_read_data_1;
alu_input_2 <= "000000000000000000000000000" & instruction_fetched(10 downto 6) when instr_1 = '1' else
"00000000000000000000000000000" & instruction_fetched(8 downto 6) when (instr_2 = '1' and instruction_fetched(10) ='1') else
X"000000" & instruction_fetched(7 downto 0) when instr_3 = '1' else
"0000000000000000000000" & instruction_fetched(7 downto 0) & "00" when instr_6 = '1' or instr_11 = '1' or instr_12 = '1' else
(31 downto 9 => instruction_fetched(7)) & instruction_fetched(6 downto 0) & "00" when instr_13 = '1' else
"00000000000000000000000" & instruction_fetched(7 downto 0) & '0' when instr_16 = '1' else
(31 downto 12 => instruction_fetched(10)) & instruction_fetched(10 downto 0) & '0' when instr_18 = '1' else
(31 downto 3 => '0') & "100" when instr_14 = '1' else --SP +- 4
reg_read_data_2;
--FIX OP CODE
--0000 AND,0001 EOR,0010 LSL,0011 LSR,0100 ASR,0101 ADC,0110 SBC,0111 ROR,
--1000 TST,1001 NEG,1010 CMP,1011 CMN,1100 ORR,1101 MUL,1110 BIC,1111 MVN
alu_function <= "0" & instruction_fetched(9 downto 6) when instr_4 = '1' else
"00010" when (instr_1 = '1' and instruction_fetched(12 downto 11) = "00") else --LSL
"00011" when (instr_1 = '1' and instruction_fetched(12 downto 11) = "01") else --LSR
"00100" when (instr_1 = '1' and instruction_fetched(12 downto 11) = "10") else --ASR
"10000" when (instr_3 = '1' and instruction_fetched(12 downto 11) = "00") or (instr_5 = '1' and instruction_fetched(12 downto 11) = "10") else --MOV
"01010" when (instr_3 = '1' and instruction_fetched(12 downto 11) = "01") or (instr_5 = '1' and instruction_fetched(12 downto 11) = "01") else --CMP
"10001" when (instr_2 = '1' and instruction_fetched(9) = '0') or (instr_3 = '1' and instruction_fetched(12 downto 11) = "10") or (instr_13 = '1' and instruction_fetched(7) ='0') or (instr_5 = '1' and instruction_fetched(12 downto 11) = "00") or instr_6 = '1' or instr_7 = '1' or instr_9 = '1' or instr_10 = '1' or instr_11 = '1' or instr_12 = '1' or instr_16 = '1' or instr_18 = '1' or (instr_14 = '1' and instruction_fetched(11) = '1') else --ADD
"10010" when (instr_2 = '1' and instruction_fetched(9) = '1') or (instr_3 = '1' and instruction_fetched(12 downto 11) = "11") or (instr_13 = '1' and instruction_fetched(7) ='1') or (instr_14 = '1' and instruction_fetched(11) = '0') else --SUB
(others=>'1');
--Memory write port
mem_write_enable <= '1' when (instr_9 = '1' and instruction_fetched(11) = '0') or (instr_10 = '1' and instruction_fetched(11) = '0') or (instr_11 = '1' and instruction_fetched(11) = '0') or (instr_14 = '1' and instruction_fetched(11) = '0' and stack_started = '1') else
'0';
mem_write_data <= X"000000" & reg_read_data_1(7 downto 0) when (instr_9 = '1' and instruction_fetched(12) = '1') else
X"0000" & reg_read_data_1(15 downto 0) when instr_10 = '1' else
reg_read_data_2 when instr_14 = '1' and instruction_fetched(11) = '0' else
reg_read_data_1;
--Register write port
reg_write_enable <= '0' when (instr_9 = '1' and instruction_fetched(11) = '0') or (instr_5 = '1' and instruction_fetched(9 downto 8) = "11") or (instr_10 = '1' and instruction_fetched(11) = '0') or (instr_11 = '1' and instruction_fetched(11) = '0') or instr_16 = '1' or instr_18 = '1' or instr_0 = '1' or (instr_14 = '1' and instruction_fetched(11) = '0' and stack_started = '0') else
'1';
reg_write_addr <= '0' & instruction_fetched(2 downto 0) when instr_1 = '1' or instr_2 = '1' or instr_4 = '1' or instr_7 = '1' or instr_9 = '1' or instr_10 = '1' else
'0' & instruction_fetched(10 downto 8) when instr_3 = '1' or instr_6 = '1' or instr_11 = '1' or instr_12 = '1' else
instruction_fetched(7) & instruction_fetched(2 downto 0) when instr_5 = '1' else
"1101" when instr_13 = '1' or (instr_14 = '1' and instruction_fetched(11) = '0' and stack_started = '1') else
"1110" when instr_17 = '1' else
(others=>'0');
reg_write_data_pre <= mem_output when instr_6 = '1' or instr_7 = '1' or instr_9 = '1' or instr_10 = '1' or instr_11 = '1' else
pc_plus4 when instr_17 = '1' else
alu_output;
reg_write_data <= X"000000" & reg_write_data_pre(7 downto 0) when (instr_7 = '1' and instruction_fetched(10) = '1') or (instr_9 = '1' and instruction_fetched(12) = '1') else
X"0000" & reg_write_data_pre(15 downto 0) when instr_10 = '1' else
reg_write_data_pre;
--Instruction basic decoding into 19 groups, depending on the format of instructions
instr_ok <= '1' when instruction_fetched(31 downto 16) = (31 downto 16 => '0') else '0';
instr_0 <= '1' when instruction_fetched(31 downto 0) = (31 downto 0 => '0') else '0'; --nop
instr_1 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "000" and instruction_fetched(12 downto 11) /= "11" else '0';
instr_2 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "000" and instruction_fetched(12 downto 11) = "11" else '0';
instr_3 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "001" else '0';
instr_4 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 10) = "010000" else '0';
instr_5 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 10) = "010001" else '0';
instr_6 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 11) = "01001" else '0';
instr_7 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "0101" and instruction_fetched(9) = '0' else '0'; --only implemented LDR, STR not working
instr_8 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "0101" and instruction_fetched(9) = '1' else '0'; --not implemented
instr_9 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 13) = "011" else '0';
instr_10 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1000" else '0';
instr_11 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1001" else '0';
instr_12 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1010" else '0';
instr_13 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 8 ) = "10110000" else '0'; --only implemented +offset, ignoring sign
instr_14 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1011" and instruction_fetched(10 downto 9) = "10" else '0'; --multiple push implemented, multiple pop not
instr_15 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1100" else '0'; --TODO
instr_16 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1101" and instruction_fetched(11 downto 8) /= "1111" else '0';
instr_17 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 8 ) = "11011111" else '0'; --CPSR->SPSR not implemented, only thumb mode enable
instr_18 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 11) = "11100" else '0';
instr_19 <= '1' when instr_ok = '1' and instruction_fetched(15 downto 12) = "1111" else '0'; --TODO
end Behavioral;
|
mit
|
f0d868274caf5a53dc2448cac74724dd
| 0.560978 | 3.316953 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_command_send_fifo/simulation/fg_tb_top.vhd
| 1 | 6,308 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
6a56ba663a47bb7048eee0b9bc369f3c
| 0.609068 | 4.106771 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/controller_command_fifo/example_design/controller_command_fifo_top_wrapper.vhd
| 1 | 19,192 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: controller_command_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity controller_command_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end controller_command_fifo_top_wrapper;
architecture xilinx of controller_command_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component controller_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : controller_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
6fb522081f77e99600c1cd17d9749b09
| 0.487495 | 3.981743 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/sincronismo.vhd
| 1 | 5,659 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: sincronismo.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity sincronismo is
port(
clk_50MHz: in std_logic;
rst: in std_logic;
hsync: out std_logic;
vsync: out std_logic;
pos_h: out std_logic_vector(9 downto 0);
pos_v: out std_logic_vector(9 downto 0)
);
end sincronismo;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture arq of sincronismo is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
-- Contadores
signal v_cntr : std_logic_vector(9 downto 0);
signal v_cntr_add1: std_logic_vector(9 downto 0);
signal h_cntr : std_logic_vector(9 downto 0);
signal h_cntr_add1: std_logic_vector(9 downto 0);
-- Senales de sincronismo:
signal ff_hsync: std_logic;
signal ff_vsync: std_logic;
signal hsync_in: std_logic;
signal vsync_in: std_logic;
-- Pulso 25MHz:
signal p25MHz: std_logic;
-----------------------------------------------------------------------------
-- Declaracion de componentes
-----------------------------------------------------------------------------
COMPONENT dsor_vga
PORT(
clk_50MHz : IN std_logic;
rst : IN std_logic;
pulso_25MHz : OUT std_logic
);
END COMPONENT;
COMPONENT incrementadorCuenta10bits
PORT(
num_in : IN std_logic_vector(9 downto 0);
num_out : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
dsor_vga_0: dsor_vga PORT MAP(
clk_50MHz => clk_50MHz,
rst => rst,
pulso_25MHz => p25MHz
);
incr_cont_h: incrementadorCuenta10bits PORT MAP(
num_in => h_cntr,
num_out => h_cntr_add1
);
incr_cont_v: incrementadorCuenta10bits PORT MAP(
num_in => v_cntr,
num_out => v_cntr_add1
);
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
-- Senales de sincronismo:
hsync_in <= '1' when h_cntr >= "1010010000" and h_cntr <= "1011101111" else -- Entre 656 y 751
'0';
vsync_in <= '1' when v_cntr >= "0111101010" and v_cntr <= "0111101011" else -- Enre 490 y 491
'0';
-- Conexion a la salida:
hsync <= ff_hsync;
vsync <= ff_vsync;
pos_h <= h_cntr;
pos_v <= v_cntr;
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
-- Registros de las senales de sincronismo:
-------------------------------------------------------------
p_ff_sync: process(clk_50MHz, rst)
begin
if rst = '1' then
ff_hsync <= '0';
ff_vsync <= '0';
elsif rising_edge(clk_50MHz) then
ff_hsync <= hsync_in;
ff_vsync <= vsync_in;
end if;
end process p_ff_sync;
-- Contador hasta 800
-------------------------------------------------------------
p_h_cntr: process (h_cntr, p25MHz, clk_50MHz, rst)
begin
if rst = '1' then
h_cntr <= (others => '0');
elsif rising_edge(clk_50MHz) then
if p25MHz = '1' then
if h_cntr = "1100011111" then -- Si ha llegado a 799
h_cntr <= (others => '0');
else
h_cntr <= h_cntr_add1;
end if;
end if;
end if;
end process p_h_cntr;
-- Contador hasta 525
-------------------------------------------------------------
p_v_cntr: process (v_cntr, h_cntr, p25MHz, clk_50MHz, rst)
begin
if rst = '1' then
v_cntr <= (others => '0');
elsif rising_edge(clk_50MHz) then
if p25MHz = '1' and h_cntr = "1100011111" then -- h_cntr = 799
if v_cntr = "1000001100" then -- Si ha llegado a 524
v_cntr <= (others => '0');
else
v_cntr <= v_cntr_add1;
end if;
end if;
end if;
end process p_v_cntr;
end arq;
|
gpl-3.0
|
e7fd9f26780ed698120361d68eff12b3
| 0.457663 | 4.111192 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/GC_fifo/example_design/GC_fifo_top.vhd
| 1 | 4,955 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: GC_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity GC_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end GC_fifo_top;
architecture xilinx of GC_fifo_top is
SIGNAL clk_i : std_logic;
component GC_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : GC_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
24558a81d9054bbe82409aacb548beb4
| 0.520686 | 4.905941 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/DMA_READ_QUEUE/example_design/DMA_READ_QUEUE_top_wrapper.vhd
| 1 | 19,010 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: DMA_READ_QUEUE_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity DMA_READ_QUEUE_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end DMA_READ_QUEUE_top_wrapper;
architecture xilinx of DMA_READ_QUEUE_top_wrapper is
SIGNAL clk_i : std_logic;
component DMA_READ_QUEUE_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : DMA_READ_QUEUE_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
33e74d0bd1f85d76ae2deddbfee2ec34
| 0.486481 | 3.967856 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_rec_fifo/example_design/pcie_data_rec_fifo_top.vhd
| 1 | 5,995 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_data_rec_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_data_rec_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_data_rec_fifo_top;
architecture xilinx of pcie_data_rec_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_data_rec_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_data_rec_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
caa557e2ced5d04002e6e3737b195382
| 0.506255 | 4.654503 | false | false | false | false |
mdavid626/fit
|
src/IMP_crossroads/fpga/top_level.vhd
| 1 | 5,745 |
-- top_level.vhd : keyboard
-- Copyright (C) 2009 Brno University of Technology,
-- Faculty of Information Technology
-- Author(s): Zdenek Vasicek vasicek AT fit.vutbr.cz
--
-- LICENSE TERMS
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. All advertising materials mentioning features or use of this software
-- or firmware must display the following acknowledgement:
--
-- This product includes software developed by the University of
-- Technology, Faculty of Information Technology, Brno and its
-- contributors.
--
-- 4. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software or firmware is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id$
--
--
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_ARITH.ALL;
use ieee.std_logic_UNSIGNED.ALL;
architecture main of tlv_bare_ifc is
-----------------------------------------------------------------------------
-- Signaly
signal adc_addr : std_logic_vector(1 downto 0);
signal adc_data_out : std_logic_vector(15 downto 0);
signal adc_data_in : std_logic_vector(15 downto 0);
signal adc_we : std_logic;
-- Keyboard 4x4
signal key_data_in : std_logic_vector (15 downto 0);
-- LCD Display
signal lcd_we : std_logic;
-----------------------------------------------------------------------------
-- POUZITE KOMPONENTY
component SPI_adc
generic (
ADDR_WIDTH : integer;
DATA_WIDTH : integer;
ADDR_OUT_WIDTH : integer;
BASE_ADDR : integer
);
port (
CLK : in std_logic;
CS : in std_logic;
DO : in std_logic;
DO_VLD : in std_logic;
DI : out std_logic;
DI_REQ : in std_logic;
ADDR : out std_logic_vector (ADDR_OUT_WIDTH-1 downto 0);
DATA_OUT : out std_logic_vector (DATA_WIDTH-1 downto 0);
DATA_IN : in std_logic_vector (DATA_WIDTH-1 downto 0);
WRITE_EN : out std_logic;
READ_EN : out std_logic
);
end component;
-- Keyboard 4x4
component keyboard_controller
port(
CLK : in std_logic;
RST : in std_logic;
DATA_OUT : out std_logic_vector(15 downto 0);
DATA_VLD : out std_logic;
KB_KIN : out std_logic_vector(3 downto 0);
KB_KOUT : in std_logic_vector(3 downto 0)
);
end component;
component lcd_raw_controller
port (
RST : in std_logic;
CLK : in std_logic;
DATA_IN : in std_logic_vector (15 downto 0);
WRITE_EN : in std_logic;
DISPLAY_RS : out std_logic;
DISPLAY_DATA : inout std_logic_vector(7 downto 0);
DISPLAY_RW : out std_logic;
DISPLAY_EN : out std_logic
);
end component;
begin
LEDF <= '0';
-- Adresovy dekoder pro KB
SPI_adc_keybrd: SPI_adc
generic map(
ADDR_WIDTH => 8, -- sirka adresy 8 bitu
DATA_WIDTH => 16, -- sirka dat 16 bitu
ADDR_OUT_WIDTH => 2, -- sirka adresy na vystupu 2 bity
BASE_ADDR => 16#0000# -- adresovy prostor od 0x00 = LCD, 0x02 = KB
)
port map(
CLK => CLK,
CS => SPI_CS,
DO => SPI_DO,
DO_VLD => SPI_DO_VLD,
DI => SPI_DI,
DI_REQ => SPI_DI_REQ,
ADDR => adc_addr,
DATA_OUT => adc_data_out,
DATA_IN => adc_data_in,
WRITE_EN => adc_we,
READ_EN => open
);
adc_data_in <= key_data_in when adc_addr(1) = '1' else (others => '0');
lcd_we <= (not adc_addr(1)) and adc_we;
-- Radic klavesnice
keybrd: keyboard_controller
port map(
CLK => CLK,
RST => RESET, -- reset
DATA_OUT => key_data_in,
DATA_VLD => open,
-- Keyboart
KB_KIN => KIN,
KB_KOUT => KOUT
);
-- Radic LCD displeje
lcdctrl: lcd_raw_controller
port map (
RST => RESET,
CLK => CLK,
-- ridici signaly
DATA_IN => adc_data_out,
WRITE_EN => lcd_we,
--- signaly displeje
DISPLAY_RS => LRS,
DISPLAY_DATA => LD,
DISPLAY_RW => LRW,
DISPLAY_EN => LE
);
end main;
|
mit
|
1fdde6f08af9a2820ac2b68d11bae104
| 0.566406 | 3.929549 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/block_ram_2kx16.vhd
| 1 | 2,832 |
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file block_ram_2kx16.vhd when simulating
-- the core, block_ram_2kx16. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Express, Exemplar and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;
ENTITY block_ram_2kx16 IS
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
sinit: IN std_logic;
we: IN std_logic);
END block_ram_2kx16;
ARCHITECTURE block_ram_2kx16_a OF block_ram_2kx16 IS
component wrapped_block_ram_2kx16
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
sinit: IN std_logic;
we: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_block_ram_2kx16 use entity XilinxCoreLib.blkmemsp_v3_1(behavioral)
generic map(
c_reg_inputs => 0,
c_addr_width => 11,
c_has_sinit => 1,
c_has_rdy => 0,
c_width => 16,
c_has_en => 0,
c_mem_init_file => "mif_file_16_1",
c_depth => 2047,
c_has_nd => 0,
c_has_default_data => 1,
c_default_data => "0",
c_limit_data_pitch => 8,
c_pipe_stages => 0,
c_has_rfd => 0,
c_has_we => 1,
c_sinit_value => "0",
c_has_limit_data_pitch => 0,
c_enable_rlocs => 0,
c_has_din => 1,
c_write_mode => 0);
BEGIN
U0 : wrapped_block_ram_2kx16
port map (
addr => addr,
clk => clk,
din => din,
dout => dout,
sinit => sinit,
we => we);
END block_ram_2kx16_a;
-- synopsys translate_on
|
gpl-3.0
|
16ee8851f77361856fe07a238110d9c5
| 0.592161 | 3.46634 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/top_synth_r1.vhd
| 1 | 99,598 |
-------------------------------------------------------------------------------
--
-- Design : Tomasulo Top
-- Project : Tomasulo Processor
-- Author : Manpreet Billing
-- Company : University of Southern California
-------------------------------------------------------------------------------
--
-- File : top.vhd
-- Version : 1.1
--
-------------------------------------------------------------------------------
-- minor revision by Ammar Sheik and Gandhi Puvvada on 7/11/2011 and 7/15/2011
-- File name: top_synth_r1.vhd
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- synopsys translate_off
use work.reverseAssemblyFunctionPkg.all;
-- synopsys translate_on
entity tomasulo_top is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic ;
Reset : in std_logic ;
--modified by Prasanjeet
-- signals corresponding to Instruction memory
fio_icache_addr_IM : in std_logic_vector(5 downto 0);
fio_icache_data_in_IM : in std_logic_vector(127 downto 0);
fio_icache_wea_IM : in std_logic;
fio_icache_data_out_IM : out std_logic_vector(127 downto 0);
fio_icache_ena_IM : in std_logic;
--signals corresponding to Data memory
fio_dmem_addr_DM : in std_logic_vector(5 downto 0);
fio_dmem_data_out_DM : out std_logic_vector(31 downto 0);
fio_dmem_data_in_DM : in std_logic_vector(31 downto 0); --changed by PRASANJEET
fio_dmem_wea_DM : in std_logic; --changed by PRASANJEET
Test_mode : in std_logic;-- for using the test mode
walking_led_start : out std_logic -- ADDED BY PRASANEJEET to enable the walking led counter
-- end modified by Prasanjeet
-- COMMENTED BY PRASANJEET
-- modified by kapil
--digi_address : in std_logic_vector(5 downto 0); -- data mem address
--digi_data : out std_logic_vector(31 downto 0) -- data mem data
-- end modified by kapil
) ;
end tomasulo_top;
-- Architecture begins here
architecture behave of tomasulo_top is
-- Component declarations
component physicalregister_file is
generic(
tag_width : integer:= 6
);
port(
Clk : in std_logic;
Resetb : in std_logic;
---Interface with Integer Issue queue---
Iss_RsPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_RtPhyAddrAlu : in std_logic_vector(5 downto 0);
---Interface with Load Store Issue queue---
Iss_RsPhyAddrLsq : in std_logic_vector(5 downto 0);
---Interface with Multiply Issue queue---
Iss_RsPhyAddrMul : in std_logic_vector(5 downto 0);
Iss_RtPhyAddrMul : in std_logic_vector(5 downto 0);
---Interface with Divide Issue queue---
Iss_RsPhyAddrDiv : in std_logic_vector(5 downto 0);
Iss_RtPhyAddrDiv : in std_logic_vector(5 downto 0);
---Interface with Dispatch---
Dis_RsAddr : in std_logic_vector(5 downto 0);
PhyReg_RsDataRdy : out std_logic; -- for dispatch unit
Dis_RtAddr : in std_logic_vector(5 downto 0);
PhyReg_RtDataRdy : out std_logic; -- for dispatch unit
Dis_NewRdPhyAddr : in std_logic_vector(5 downto 0);
Dis_RegWrite : in std_logic;
---Interface with Integer Execution Unit---
PhyReg_AluRsData : out std_logic_vector(31 downto 0);
PhyReg_AluRtData : out std_logic_vector(31 downto 0);
---Interface with Load Store Execution Unit---
PhyReg_LsqRsData : out std_logic_vector(31 downto 0);
---Interface with Multiply Execution Unit---
PhyReg_MultRsData : out std_logic_vector(31 downto 0);
PhyReg_MultRtData : out std_logic_vector(31 downto 0);
---Interface with Divide Execution Unit---
PhyReg_DivRsData : out std_logic_vector(31 downto 0);
PhyReg_DivRtData : out std_logic_vector(31 downto 0);
---Interface with CDB ---
Cdb_RdData : in std_logic_vector(31 downto 0);
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0);
Cdb_Valid : in std_logic;
Cdb_PhyRegWrite : in std_logic;
---Interface with Store Buffer ---
Rob_CommitCurrPhyAddr : in std_logic_vector(5 downto 0);
PhyReg_StoreData : out std_logic_vector(31 downto 0)
);
end component ;
-------------------------
component issue_unit is
generic(
Resetb_ACTIVE_VALUE : std_logic := '0' -- ACTIVE LOW Resetb
);
port(
Clk : in std_logic;
Resetb : in std_logic;
-- ready signals from each of the queues
IssInt_Rdy : in std_logic;
IssMul_Rdy : in std_logic;
IssDiv_Rdy : in std_logic;
IssLsb_Rdy : in std_logic;
-- signal from the division execution unit to indicate that it is currently available
Div_ExeRdy : in std_logic;
--issue signals as acknowledgement from issue unit to each of the queues
Iss_Int : out std_logic;
Iss_Mult : out std_logic;
Iss_Div : out std_logic;
Iss_Lsb : out std_logic
);
end component;
-----------------------------------------------------------------
component cdb is
generic(
Resetb_ACTIVE_VALUE : std_logic := '0'
);
port(
Clk : in std_logic;
Resetb : in std_logic;
-- from ROB
Rob_TopPtr : in std_logic_vector (4 downto 0 ) ;
-- from integer execution unit
Alu_RdData : in std_logic_vector(31 downto 0);
Alu_RdPhyAddr : in std_logic_vector(5 downto 0);
Alu_BranchAddr : in std_logic_vector(31 downto 0);
Alu_Branch : in std_logic;
Alu_BranchOutcome : in std_logic;
Alu_BranchUptAddr : in std_logic_vector( 2 downto 0 );
Iss_Int : in std_logic;
Alu_BranchPredict : in std_logic;
Alu_JrFlush : in std_logic;
Alu_RobTag : in std_logic_vector( 4 downto 0);
Alu_RdWrite : in std_logic;
-- translate_off
Alu_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- from mult execution unit
Mul_RdData : in std_logic_vector(31 downto 0); -- mult_data coming from the multiplier
Mul_RdPhyAddr : in std_logic_vector(5 downto 0); -- mult_prfaddr coming from the multiplier
Mul_Done : in std_logic ; -- this is the valid bit coming from the bottom most pipeline register in the multiplier wrapper
Mul_RobTag : in std_logic_vector( 4 downto 0);
Mul_RdWrite : in std_logic;
-- translate_off
Mul_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- from div execution unit
Div_Rddata : in std_logic_vector(31 downto 0); -- div_data coming from the divider
Div_RdPhyAddr : in std_logic_vector(5 downto 0); -- div_prfaddr coming from the divider
Div_Done : in std_logic ; -- this is the valid bit coming from the bottom most pipeline register in the multiplier wrapper
Div_RobTag : in std_logic_vector( 4 downto 0);
Div_RdWrite : in std_logic;
-- translate_off
Div_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- from load buffer and store word
Lsbuf_Data : in std_logic_vector(31 downto 0);
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0);
Iss_Lsb : in std_logic;
Lsbuf_RobTag : in std_logic_vector( 4 downto 0);
Lsbuf_SwAddr : in std_logic_vector(31 downto 0);
Lsbuf_RdWrite : in std_logic;
-- translate_off
Lsbuf_instruction : in std_logic_vector(31 downto 0);
-- translate_on
--outputs of cdb
-- translate_off
Cdb_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Cdb_Valid : out std_logic;
Cdb_PhyRegWrite : out std_logic;--Cdb_PhyRegWrite
Cdb_Data : out std_logic_vector(31 downto 0);
Cdb_RobTag : out std_logic_vector(4 downto 0);--Cdb_RobTag
Cdb_BranchAddr : out std_logic_vector(31 downto 0);
Cdb_BranchOutcome : out std_logic;
Cdb_BranchUpdtAddr : out std_logic_vector( 2 downto 0 );
Cdb_Branch : out std_logic;
Cdb_Flush : out std_logic;
Cdb_RobDepth : out std_logic_vector (4 downto 0 );
Cdb_RdPhyAddr : out std_logic_vector (5 downto 0 );
Cdb_SwAddr : out std_logic_vector (31 downto 0)
);
end component;
-------------------------------------------------------------------
component issueque is
port (
-- Global Clk and dispat Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Ls Buffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Dis_Immediate : in std_logic_vector ( 15 downto 0 );
Dis_Branch : in std_logic;
Dis_BranchPredict : in std_logic;
Dis_BranchOtherAddr : in std_logic_vector ( 31 downto 0 );
Dis_BranchPCBits : in std_logic_vector ( 2 downto 0 ) ;
Issque_IntQueueFull : out std_logic ;
Issque_IntQueueTwoOrMoreVacant : out std_logic;
Dis_Jr31Inst : in std_logic;
Dis_JalInst : in std_logic;
Dis_JrRsInst : in std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy : out std_logic ;
Iss_Int : in std_logic ;
Iss_Lsb : in std_logic;
-- Interface with the Multiply execution unit
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrAlu : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit
Iss_RdPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RobTagAlu : out std_logic_vector(4 downto 0);
Iss_OpcodeAlu : out std_logic_vector(2 downto 0) ; --add branch information
Iss_BranchAddrAlu : out std_logic_vector(31 downto 0);
Iss_BranchAlu : out std_logic;
Iss_RegWriteAlu : out std_logic;
Iss_BranchUptAddrAlu : out std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : out std_logic;
Iss_JalInstAlu : out std_logic;
Iss_JrInstAlu : out std_logic;
Iss_JrRsInstAlu : out std_logic;
Iss_ImmediateAlu : out std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end component ;
------------------------------------------------------------------
component issueque_div is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Ls Buffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Issque_DivQueueFull : out std_logic ;
Issque_DivQueueTwoOrMoreVacant : out std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssDiv_Rdy : out std_logic ;
Iss_Div : in std_logic ;
Iss_Int : in std_logic;
Iss_Lsb : in std_logic;
-- Interface with the Multiply execution unit
Iss_RdPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_PhyRegValidAlu : in std_logic;
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrDiv : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrDiv : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit
Iss_RdPhyAddrDiv : out std_logic_vector(5 downto 0) ;
Iss_RobTagDiv : out std_logic_vector(4 downto 0);
Iss_OpcodeDiv : out std_logic_vector(2 downto 0) ; --add branch information
Iss_RegWriteDiv : out std_logic;
-- translate_off
Iss_instructionDiv : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end component;
----------------------------------------------------------------------------------------------
component issueque_mult is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Ls Buffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Issque_MulQueueFull : out std_logic ;
Issque_MulQueueTwoOrMoreVacant : out std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssMul_Rdy : out std_logic ;
Iss_Mult : in std_logic ;
Iss_Int : in std_logic;
Iss_Lsb : in std_logic;
-- Interface with the Multiply execution unit
Iss_RdPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_PhyRegValidAlu : in std_logic;
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- translate_off
Iss_instructionMul : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Physical Register File
Iss_RsPhyAddrMul : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrMul : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit
Iss_RdPhyAddrMul : out std_logic_vector(5 downto 0) ;
Iss_RobTagMul : out std_logic_vector(4 downto 0);
Iss_OpcodeMul : out std_logic_vector(2 downto 0) ; --add branch information
Iss_RegWriteMul : out std_logic;
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;-- Information to be captured from the Write port of Physical Register file
end component;
------------------------------------------------------------------------------------------------
component lsq is
port (
-- Global Clk and Resetb Signals
Clk : in std_logic;
Resetb : in std_logic;
-- Information to be captured from the CDB (Common Data Bus)
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0);
Cdb_PhyRegWrite : in std_logic;
Cdb_Valid : in std_logic ;
-- Information from the Dispatch Unit
Dis_Opcode : in std_logic;
Dis_Immediate : in std_logic_vector(15 downto 0 );
Dis_RsDataRdy : in std_logic;
Dis_RsPhyAddr : in std_logic_vector(5 downto 0 );
Dis_RobTag : in std_logic_vector(4 downto 0);
Dis_NewRdPhyAddr : in std_logic_vector(5 downto 0);--Dis_NewPhyAddr previous signal changed
Dis_LdIssquenable : in std_logic;
Issque_LdStQueueFull : out std_logic;
Issque_LdStQueueTwoOrMoreVacant: out std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Iss_instructionLsq : out std_logic_vector(31 downto 0);
-- translate_on
-- interface with PRF
Iss_RsPhyAddrLsq : out std_logic_vector(5 downto 0);
PhyReg_LsqRsData : in std_logic_vector(31 downto 0);
-- Interface with the Issue Unit
Iss_LdStReady : out std_logic ;
Iss_LdStOpcode : out std_logic ;
Iss_LdStRobTag : out std_logic_vector(4 downto 0); --Iss_LdStRobTag previous changed
Iss_LdStAddr : out std_logic_vector(31 downto 0);
Iss_LdStIssued : in std_logic;
---------------------- add appropriate value to the pin.. needed at CDB ( added by manpreet)
Iss_LdStPhyAddr : out std_logic_vector(5 downto 0); -- Physical address at which data is to be written in case of lw
-------------------------------------------------------------------
DCE_ReadBusy : in std_logic;
Lsbuf_Done : in std_logic;
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector (4 downto 0);
Cdb_RobDepth : in std_logic_vector (4 downto 0);
SB_FlushSw : in std_logic;
--SB_FlushSwTag : in std_logic_vector (4 downto 0) --Modified by Waleed 06/04/10
SB_FlushSwTag : in std_logic_vector (1 downto 0);
SBTag_counter : in std_logic_vector (1 downto 0); --Added by Waleed 06/04/10
--Interface with ROB , Added by Waleed 06/04/10
Rob_CommitMemWrite : in std_logic
);
end component;
----------------------------------------------
component dispatch_unit is
port(
Clk : in std_logic ;
Resetb : in std_logic ;
-- Interface with Intsruction Fetch Queue
Ifetch_Instruction : in std_logic_vector(31 downto 0); -- instruction from IFQ
Ifetch_PcPlusFour : in std_logic_vector(31 downto 0); -- the IC+4 value carried forward for jumping and branching
Ifetch_EmptyFlag : in std_logic; -- signal showing that the ifq is empty,hence stopping any decoding and dispatch of the current if_inst
Dis_Ren : out std_logic; -- stalling caused due to issue queue being full
Dis_JmpBrAddr : out std_logic_vector(31 downto 0); -- the jump or branch address
Dis_JmpBr : out std_logic; -- validating that address to cause a jump or branch
Dis_JmpBrAddrValid : out std_logic; -- to tell if the jump pr branch address is valid or not.. ll be invalid for "jr $rs" inst
-------------------------------------------------------------------------
-- Interface with branch prediction buffer
Dis_CdbUpdBranch : out std_logic; -- indicates that a branch is processed by the top of the rob and gives the pred(wen to bpb)
Dis_CdbUpdBranchAddr : out std_logic_vector(2 downto 0);-- indiactes the last 3 bit addr of the branch beign processed by top
Dis_CdbBranchOutcome : out std_logic; -- indiacates the outocome of the branch to the bpb
Bpb_BranchPrediction : in std_logic; --This bit tells the dispatch what the prediction actually based on bpb state-mc
Dis_BpbBranchPCBits : out std_logic_vector(2 downto 0);--indiaces the 3 least sig bits of the current instr being dis
Dis_BpbBranch : out std_logic; -- indiactes a branch instr (ren to the bpb)
--------------------------------------------------------------------------------
-- interface with the cdb
Cdb_Branch : in std_logic;
Cdb_BranchOutcome : in std_logic;
Cdb_BranchAddr : in std_logic_vector(31 downto 0);
Cdb_BrUpdtAddr : in std_logic_vector(2 downto 0);
Cdb_Flush : in std_logic;
Cdb_RobTag : in std_logic_vector(4 downto 0);
------------------------------------------------------------------------------
-- interface with checkpoint module
Dis_CfcRsAddr : out std_logic_vector(4 downto 0);-- Indicates the Rs Address to be read from Reg file
Dis_CfcRtAddr : out std_logic_vector(4 downto 0); -- Indicates the Rt Address to be read from Reg file
Dis_CfcRdAddr : out std_logic_vector(4 downto 0); -- Indicates the Rd Address to be written by instruction
-- goes to Dis_CfcRdAddr of ROB too
Cfc_RsPhyAddr : in std_logic_vector(5 downto 0); -- Rs Physical register Tag corresponding to Rs Addr
Cfc_RtPhyAddr : in std_logic_vector(5 downto 0); -- Rt Physical register Tag corresponding to Rt Addr
Cfc_RdPhyAddr : in std_logic_vector(5 downto 0); -- Rd Old Physical register Tag corresponding to Rd Addr
Cfc_Full : in std_logic ;
Dis_CfcBranchTag : out std_logic_vector(4 downto 0) ; -- Indicats the rob tag of the branch for which checkpoint is to be done
Dis_CfcRegWrite : out std_logic; -- cfc and ROB
Dis_CfcNewRdPhyAddr : out std_logic_vector(5 downto 0);
Dis_CfcBranch : out std_logic;
Dis_CfcInstValid : out std_logic;
--------------------------------------------------------------------------------
-- physical register interface
PhyReg_RsDataRdy : in std_logic ; -- Indicating if the value of Rs is ready at the physical tag location
PhyReg_RtDataRdy : in std_logic ; -- Indicating if the value of Rt is ready at the physical tag location
-- interface with issue queues
-- translate_off
Dis_Instruction : out std_logic_vector(31 downto 0);
-- translate_on
Dis_RegWrite : out std_logic;
Dis_RsDataRdy : out std_logic;-- Tells the queues the validity of the data given by the dispatch itself
Dis_RtDataRdy : out std_logic;--Tells the queues the validity of the data given by the dispatch itself
Dis_RsPhyAddr : out std_logic_vector(5 downto 0);--This tells the tag of the operands if the data is not in the complete or commit phase
Dis_RtPhyAddr : out std_logic_vector(5 downto 0);--This tells the tag of the operands if the data is not in the complete or commit phase
Dis_RobTag : out std_logic_vector(4 downto 0);
Dis_Opcode : out std_logic_vector(2 downto 0);--Gives the Opcode of the given instruction
Dis_IntIssquenable : out std_logic;--Informs the respective issue queue that the dispatch is going to enter a new entry
Dis_LdIssquenable : out std_logic;--Informs the respective issue queue that the dispatch is going to enter a new entry
Dis_DivIssquenable : out std_logic;--Informs the respective issue queue that the dispatch is going to enter a new entry
Dis_MulIssquenable : out std_logic;--Informs the respective issue queue that the dispatch is going to enter a new entry
Dis_Immediate : out std_logic_vector(15 downto 0);
Issque_IntQueueFull : in std_logic;
Issque_LdStQueueFull : in std_logic;
Issque_DivQueueFull : in std_logic;
Issque_MulQueueFull : in std_logic;
Issque_IntQueTwoOrMoreVacant : in std_logic;
Issque_LdStQueTwoOrMoreVacant : in std_logic;
Issque_DivQueTwoOrMoreVacant : in std_logic;
Issque_MulQueTwoOrMoreVacant : in std_logic;
Dis_BranchOtherAddr : out std_logic_vector(31 downto 0);
Dis_BranchPredict : out std_logic;
Dis_Branch : out std_logic;
Dis_BranchPCBits : out std_logic_vector(2 downto 0);
Dis_JrRsInst : out std_logic;
Dis_JalInst : out std_logic ; -- Indicating whether there is a call instruction
Dis_Jr31Inst : out std_logic;
----------------------------------------------------------------------------------
---- interface with the FRL---- accessed in first sage only so dont need NaerlyEmpty signal from Frl
Frl_RdPhyAddr : in std_logic_vector(5 downto 0); -- Physical tag for the next available free register
Dis_FrlRead : out std_logic ; -- Indicating if free register given by FRL is used or not
Frl_Empty : in std_logic;
----------------------------------------------------------------------------------
---- interface with the RAS----
Dis_RasJalInst : out std_logic ; -- Indicating whether there is a call instruction
Dis_RasJr31Inst : out std_logic;
Dis_PcPlusFour : out std_logic_vector(31 downto 0);
Ras_Addr : in std_logic_vector(31 downto 0);
----------------------------------------------------------------------------------
---- interface with the rob----
Dis_PrevPhyAddr : out std_logic_vector(5 downto 0);
Dis_NewRdPhyAddr : out std_logic_vector(5 downto 0); -- send to integer queue , cfc and
Dis_RobRdAddr : out std_logic_vector(4 downto 0); -- Indicates the Rd Address to be written by instruction -- send to Physical register file too.. so that he can make data ready bit "0"
Dis_InstValid : out std_logic ;
Dis_InstSw : out std_logic ;
Dis_SwRtPhyAddr : out std_logic_vector(5 downto 0);
Rob_BottomPtr : in std_logic_vector(4 downto 0);
Rob_Full : in std_logic;
Rob_TwoOrMoreVacant : in std_logic
);
end component;
------------------------------------------------------------------
component multiplier is
generic (
tag_width : integer := 6
);
port (
clk : in std_logic;
Resetb : in std_logic;
Iss_Mult : in std_logic ; -- from issue unit
PhyReg_MultRsData : in std_logic_VECTOR(31 downto 0); -- from issue queue mult
PhyReg_MultRtData : in std_logic_VECTOR(31 downto 0); -- from issue queue mult
Iss_RobTag : in std_logic_vector(4 downto 0); -- from issue queue mult
-------------------------------- Logic for the pins ( added by Atif) --------------------------------
Mul_RdPhyAddr : out std_logic_vector(5 downto 0); -- output to CDB required
Mul_RdWrite : out std_logic;
Iss_RdPhyAddr : in std_logic_vector(5 downto 0); -- incoming form issue queue, need to be carried as Iss_RobTag
Iss_RdWrite : in std_logic;
----------------------------------------------------------------------
-- translate_off
Iss_instructionMul : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Mul_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Mul_RdData : out std_logic_VECTOR(31 downto 0); -- output to CDB unit (to CDB Mux)
Mul_RobTag : out std_logic_vector(4 downto 0); -- output to CDB unit (to CDB Mux)
Mul_Done : out std_logic ; -- output to CDB unit ( to control Mux selection)
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
);
end component;
-----------------------------------------------------------------
component ALU is
generic (
tag_width : integer := 6
);
port (
PhyReg_AluRsData : in std_logic_vector(31 downto 0);
PhyReg_AluRtData : in std_logic_vector(31 downto 0);
Iss_OpcodeAlu : in std_logic_vector(2 downto 0);
Iss_RobTagAlu : in std_logic_vector(4 downto 0);
Iss_RdPhyAddrAlu : in std_logic_vector(5 downto 0);
Iss_BranchAddrAlu : in std_logic_vector(31 downto 0);
Iss_BranchAlu : in std_logic;
Iss_RegWriteAlu : in std_logic;
Iss_BranchUptAddrAlu : in std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : in std_logic;
Iss_JalInstAlu : in std_logic;
Iss_JrInstAlu : in std_logic;
Iss_JrRsInstAlu : in std_logic;
Iss_ImmediateAlu : in std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : in std_logic_vector(31 downto 0);
-- translate_on
Alu_RdData : out std_logic_vector(31 downto 0);
Alu_RdPhyAddr : out std_logic_vector(5 downto 0);
Alu_BranchAddr : out std_logic_vector(31 downto 0);
Alu_Branch : out std_logic;
Alu_BranchOutcome : out std_logic;
-- translate_off
Alu_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Alu_RobTag : out std_logic_vector(4 downto 0);
Alu_BranchUptAddr : out std_logic_vector( 2 downto 0 );
Alu_BranchPredict : out std_logic;
Alu_RdWrite : out std_logic;
Alu_JrFlush : out std_logic
);
end component;
-------------------------------------------------------------------
component divider is
generic (
tag_width : integer := 6
);
port (
clk : IN std_logic;
Resetb : IN std_logic;
PhyReg_DivRsData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit
PhyReg_DivRtData : IN std_logic_VECTOR(31 downto 0); -- from divider issue queue unit --
Iss_RobTag : IN std_logic_vector( 4 downto 0); -- from divider issue queue unit
Iss_Div : IN std_logic; -- from issue unit
-------------------------------- Logic for the pics ( added by Atif) --------------------------------
Div_RdPhyAddr : out std_logic_vector(5 downto 0); -- output to CDB required
Div_RdWrite : out std_logic;
Iss_RdPhyAddr : in std_logic_vector(5 downto 0); -- incoming form issue queue, need to be carried as Iss_RobTag
Iss_RdWrite : in std_logic;
----------------------------------------------------------------------
-- translate_off
Iss_instructionDiv : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Div_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 ) ;
Div_Done : out std_logic ;
Div_RobTag : OUT std_logic_vector(4 downto 0);
Div_Rddata : OUT std_logic_vector(31 downto 0);
Div_ExeRdy : OUT std_logic -- divider is read for division ==> drives "div_exec_ready" in the TOP
);
end component;
--------------------------------------------------------------------
component inst_cache
generic (
DATA_WIDTH : integer := 128; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
Clk : in std_logic;
Resetb : in std_logic;
read_cache : in std_logic;
abort_prev_read : in std_logic; -- will be used under jump or successful branch
addr : in std_logic_vector (31 downto 0);
cd0 : out std_logic_vector (31 downto 0);
cd1 : out std_logic_vector (31 downto 0);
cd2 : out std_logic_vector (31 downto 0);
cd3 : out std_logic_vector (31 downto 0);
-- synopsys translate_off
registered_addr : out std_logic_vector(31 downto 0);
-- synopsys translate_on
read_hit : out std_logic;
fio_icache_addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
fio_icache_data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
fio_icache_wea : in std_logic;
fio_icache_data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
fio_icache_ena : in std_logic
);
end component;
-----------------------------------------------------------------------
component i_fetch_q is
port (
Clk : in std_logic;
Resetb : in std_logic;
-- interface with the dispatch unit
Ifetch_Instruction : out std_logic_vector(31 downto 0);
Ifetch_PcPlusFour : out std_logic_vector(31 downto 0);
Ifetch_EmptyFlag : out std_logic;
Dis_Ren : in std_logic; -- may be active even if ifq is empty.
Dis_JmpBrAddr : in std_logic_vector(31 downto 0);
Dis_JmpBr : in std_logic;
Dis_JmpBrAddrValid : in std_logic;
-- interface with the cache unit
Ifetch_WpPcIn : out std_logic_vector(31 downto 0);
Ifetch_ReadCache : out std_logic;
-- synopsys translate_off
wp_report, rp_report, depth_report : out std_logic_vector(4 downto 0);
-- synopsys translate_on
Ifetch_AbortPrevRead : out std_logic;
Cache_Cd0 : in std_logic_vector (31 downto 0);
Cache_Cd1 : in std_logic_vector (31 downto 0);
Cache_Cd2 : in std_logic_vector (31 downto 0);
Cache_Cd3 : in std_logic_vector (31 downto 0);
Cache_ReadHit : in std_logic
);
end component ;
---------------------------------------------------
component bpb is
port (
Clk : in std_logic;
Resetb : in std_logic;
---- rob -------
Dis_CdbUpdBranch : in std_logic; -- indicates that a branch is processed by the top of the rob and gives the pred(wen to bpb)
Dis_CdbUpdBranchAddr : in std_logic_vector(2 downto 0);-- indiactes the last 3 bit addr of the branch beign processed by top
Dis_CdbBranchOutcome : in std_logic; -- indiacates the outocome of the branch to the bpb 0 nottaken 1 taken
------------------
---- dispatch --------------
Bpb_BranchPrediction : out std_logic; --This bit tells the dispatch what the prediction actually based on bpb state-mc
Dis_BpbBranchPCBits : in std_logic_vector(2 downto 0) ;--indiaces the 3 least sig bits of the current instr being dis
Dis_BpbBranch : in std_logic -- indiactes a branch instr (ren to the bpb)
---------------------------
);
end component;
-------------------
component ls_buffer is
port (
Clk : in std_logic;
Resetb : in std_logic;
-- from ROB -- for fulsing the instruction in this buffer if appropriate.
Cdb_Flush : in std_logic ;
Rob_TopPtr : in std_logic_vector (4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector (4 downto 0 ) ;
-- interface with lsq
Iss_LdStReady : in std_logic ;
Iss_LdStOpcode : in std_logic ; -- 1 = lw , 0 = sw
Iss_LdStRobTag : in std_logic_vector(4 downto 0);
Iss_LdStAddr : in std_logic_vector(31 downto 0);
Iss_LdStData : in std_logic_vector(31 downto 0);-- data to be written to memory in the case of sw
Iss_LdStPhyAddr : in std_logic_vector(5 downto 0);
-- translate_off
DCE_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Iss_instructionLsq : in std_logic_vector(31 downto 0);
-- translate_on
---- interface with data cache emulator ----------------
DCE_PhyAddr : in std_logic_vector(5 downto 0);
DCE_Opcode : in std_logic ;
DCE_RobTag : in std_logic_vector(4 downto 0);
DCE_Addr : in std_logic_vector(31 downto 0);
DCE_MemData: in std_logic_vector (31 downto 0 ) ; -- data from data memory in the case of lw
DCE_ReadDone : in std_logic ; -- data memory (data cache) reporting that read finished -- from ls_buffer_ram_reg_array -- instance name DataMem
Lsbuf_LsqTaken : out std_logic; -- handshake signal to ls_queue
Lsbuf_DCETaken : out std_logic; -- handshake signal to ls_queue
Lsbuf_Full : out std_logic; -- handshake signal to ls_queue
-- interface with issue unit
-- from load buffer and store word
-- translate_off
Lsbuf_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Lsbuf_Ready : out std_logic ;
------------- changed as per CDB -------------
Lsbuf_Data : out std_logic_vector(31 downto 0);
Lsbuf_PhyAddr : out std_logic_vector(5 downto 0);
Lsbuf_RobTag : out std_logic_vector(4 downto 0) ;
Lsbuf_SwAddr : out std_logic_vector(31 downto 0);
Lsbuf_RdWrite : out std_logic;
------------------------------------------------------------
Iss_Lsb : in std_logic -- return signal from the issue unit
);
end component ;
-------------------------------------------------------------
component ls_buffer_ram_reg_array is
generic (ADDR_WIDTH: integer := 6; DATA_WIDTH: integer := 32);
port (
Clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dia : in std_logic_vector (DATA_WIDTH-1 downto 0);
addrb : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dob : out std_logic_vector (DATA_WIDTH-1 downto 0);
rea : in std_logic ;
mem_wri : out std_logic ;
mem_exc : out std_logic ;
mem_read : out std_logic
-- modified by kapil
--addrc : in std_logic_vector(ADDR_WIDTH-1 downto 0);
--doc : out std_logic_vector(DATA_WIDTH-1 downto 0)
-- end modified by kapil
);
end component ;
----------------------------------------------------------------------------------------------------------------------------------
component rob is
port(--inputs--
Clk :in std_logic;
Resetb :in std_logic;
-- Interface with CDB
Cdb_Valid : in std_logic; -- signal to tell that the values coming on CDB is valid
Cdb_RobTag : in std_logic_vector(4 downto 0); -- Tag of the instruction which the the CDB is broadcasting
Cdb_SwAddr : in std_logic_vector (31 downto 0); -- to give the store wordaddr
-- Interface with Dispatch unit
Dis_InstSw : in std_logic; -- signal that tells that the signal being dispatched is a store word
Dis_RegWrite : in std_logic; -- signal telling that the instruction is register writing instruction
Dis_InstValid : in std_logic; -- Signal telling that Dispatch unit is giving valid information
Dis_RobRdAddr : in std_logic_vector(4 downto 0); -- Actual Desitnation register number of the instruction being dispatched
Dis_NewRdPhyAddr : in std_logic_vector (5 downto 0); -- Current Physical Register number of dispatching instruction taken by the dispatch unit from the FRL
Dis_PrevPhyAddr : in std_logic_vector (5 downto 0); -- Previous Physical Register number of dispatch unit taken from CFC
Dis_SwRtPhyAddr : in std_logic_vector (5 downto 0); -- Physical Address number from where store word has to take the data
Rob_Full : out std_logic;
Rob_TwoOrMoreVacant : out std_logic;
-- Interface with store buffer
SB_Full : in std_logic; -- Tells the ROB that the store buffer is full
Rob_SwAddr : out std_logic_vector (31 downto 0); -- The address in case of sw instruction
Rob_CommitMemWrite : out std_logic; -- Signal to enable the memory for writing purpose
-- Rob_FlushSw : out std_logic; -- for address buffer of lsq
-- Rob_FlushSwTag : out std_logic_vector (5 downto 0);
-- Takes care of flushing the address buffer
-- Interface with FRL and CFC
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
Rob_Instruction : out std_logic_vector(31 downto 0);
-- translate_on
Rob_TopPtr : out std_logic_vector (4 downto 0); -- Gives the value of TopPtr pointer of ROB
Rob_BottomPtr : out std_logic_vector (4 downto 0);
Rob_Commit : out std_logic; -- FRL needs it to to add pre phy to free list cfc needs it to remove the latest cheackpointed copy
Rob_CommitRdAddr : out std_logic_vector(4 downto 0); -- Architectural register number of committing instruction
Rob_CommitRegWrite : out std_logic; --Indicates that the instruction that is being committed is a register wrtiting instruction
Rob_CommitPrePhyAddr : out std_logic_vector(5 downto 0); --pre physical addr of committing inst to be added to FRL
Rob_CommitCurrPhyAddr : out std_logic_vector (5 downto 0); -- Current Register Address of committing instruction to update retirment rat
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cfc_RobTag : in std_logic_vector (4 downto 0) -- Tag of the instruction that has the checkpoint
);
end component;
----------------------------------------------------------------------------------------------------------------------------------
component cfc is
port ( --global signals
Clk :in std_logic; --Global Clock Signal
Resetb :in std_logic; --Global Reset Signal
--interface with dispatch unit
Dis_InstValid :in std_logic; --Flag indicating if the instruction dispatched is valid or not
Dis_CfcBranchTag :in std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
Dis_CfcRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address
Dis_CfcRsAddr :in std_logic_vector(4 downto 0); --Rs Logical Address
Dis_CfcRtAddr :in std_logic_vector(4 downto 0); --Rt Logical Address
Dis_CfcNewRdPhyAddr :in std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
Dis_CfcRegWrite :in std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
Dis_CfcBranch :in std_logic; --Flag indicating whether current instruction being dispatched is branch or not
Dis_Jr31Inst :in std_logic; --Flag indicating if the current instruction is Jr 31 or not
Cfc_RdPhyAddr :out std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
Cfc_RsPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
Cfc_RtPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
Cfc_Full :out std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
Rob_TopPtr :in std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
Rob_Commit :in std_logic; --Flag indicating whether instruction is committing in this cycle or not
Rob_CommitRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
Rob_CommitRegWrite :in std_logic; --Indicates if instruction is writing to register or not
Rob_CommitCurrPhyAddr :in std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag :out std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
Frl_HeadPtr :in std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
Cfc_FrlHeadPtr :out std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cdb_RobTag :in std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
Cdb_RobDepth :in std_logic_vector(4 downto 0) --Depth of mispredicted branch from ROB Top
);
end component;
---------------------------------------------------------------------------------
component Frl is
generic (WIDE : integer := 6;DEEP : integer:=16;PTRWIDTH:integer:=5);
port (
--Inputs
Clk : in std_logic ;
Resetb : in std_logic ;
Cdb_Flush : in std_logic ;
--Interface with Rob
Rob_CommitPrePhyAddr : in std_logic_vector(WIDE-1 downto 0) ;
Rob_Commit : in std_logic ;
Rob_CommitRegWrite : in std_logic;
Cfc_FrlHeadPtr: in std_logic_vector(PTRWIDTH-1 downto 0) ;
--Intreface with Dis_FrlRead unit
Frl_RdPhyAddr : out std_logic_vector(WIDE-1 downto 0) ;
Dis_FrlRead : in std_logic ;
Frl_Empty : out std_logic ;
--Frl_NearEmpty : out std_logic;
--Interface with Previous Head Pointer Stack
Frl_HeadPtr : out std_logic_vector(PTRWIDTH-1 downto 0)
);
end component;
---------------------------------------------------------------------------------
component ras is
generic (size : integer :=4);
port(
--global signals
Resetb : in std_logic;
Clk : in std_logic;
-- Interface with Dispatch
--inputs
Dis_PcPlusFour : in std_logic_vector(31 downto 0); -- the PC+4 value carried forward for storing in RAS
Dis_RasJalInst : in std_logic; -- set to 1 if instruction is JAL
Dis_RasJr31Inst : in std_logic; -- set to 1 if instruction is JR
--outputs
Ras_Addr : out std_logic_vector(31 downto 0) -- The address given by RAS for JR
);
end component;
---------------------------------------------------------------------------------
component store_buffer is
port (
-- Global Signals
Clk : in std_logic ;
Resetb : in std_logic ;
--interface with ROB
Rob_SwAddr : in std_logic_vector (31 downto 0);
PhyReg_StoreData : in std_logic_vector (31 downto 0);
Rob_CommitMemWrite : in std_logic;
SB_Full : out std_logic;
SB_Stall : out std_logic;
Rob_TopPtr :in std_logic_vector(4 downto 0);
-- interface with lsq
SB_FlushSw : out std_logic;
--SB_FlushSwTag : out std_logic_vector(4 downto 0); Modified by Waleed 06/04/10
SB_FlushSwTag : out std_logic_vector(1 downto 0);
SBTag_counter : out std_logic_vector (1 downto 0); --Added by Waleed 06/04/10
--interface with Data Cache Emulator
SB_DataDmem : out std_logic_vector (31 downto 0);
SB_AddrDmem : out std_logic_vector (31 downto 0);
SB_DataValid : out std_logic;
DCE_WriteBusy : in std_logic;
DCE_WriteDone :in std_logic
--interface with Load Store Buffer ( no forwarding now)
-- lsq_addr_dmem : in std_logic_vector (5 downto 0);
-- Lsbuf_Data_dmem : out std_logic_vector (31 downto 0);
-- Lsbuf_Data_valid : out std_logic
);
end component;
---------------------------------------------------------------------------------
component data_cache is
generic (
DATA_WIDTH : integer := 32; --DATA_WIDTH_CONSTANT; -- defined as 128 in the instr_stream_pkg;
ADDR_WIDTH : integer := 6 --ADDR_WIDTH_CONSTANT -- defined as 6 in the instr_stream_pkg;
);
port (
Clk : in std_logic;
Resetb : in std_logic;
DCE_ReadCache : in std_logic;
-- Abort_PrevRead : in std_logic; -- will be used under jump or successful branch -- commented out on July 15, 2011
--addr : in std_logic_vector (5 downto 0);
Iss_LdStOpcode : in std_logic ;
Iss_LdStRobTag : in std_logic_vector(4 downto 0);
Iss_LdStAddr : in std_logic_vector(31 downto 0);
--- added --------
Iss_LdStPhyAddr : in std_logic_vector(5 downto 0);
------------------
Lsbuf_DCETaken : in std_logic;
Cdb_Flush : in std_logic ; -- Cdb_Flush signal
Rob_TopPtr : in std_logic_vector(4 downto 0);
Cdb_RobDepth : in std_logic_vector(4 downto 0);
SB_WriteCache : in std_logic ;
SB_AddrDmem : in std_logic_vector (31 downto 0);
SB_DataDmem : in std_logic_vector (31 downto 0);
-- translate_off
DCE_instruction : out std_logic_vector(31 downto 0);
-- translate_on
-- translate_off
Iss_instructionLsq : in std_logic_vector(31 downto 0);
-- translate_on
--data_out : out std_logic_vector (31 downto 0);
DCE_Opcode : out std_logic ;
DCE_RobTag : out std_logic_vector(4 downto 0);
DCE_Addr : out std_logic_vector(31 downto 0);
DCE_MemData : out std_logic_vector (31 downto 0 ) ; -- data from data memory in the case of lw
------------------new pin added for CDB-----------
DCE_PhyAddr : out std_logic_vector(5 downto 0);
------------------------------------------------------------
-- synopsys translate_off
registered_addr : out std_logic_vector(5 downto 0);
registered_SB_AddrDmem : out std_logic_vector(5 downto 0);
-- synopsys translate_on
DCE_ReadDone : out std_logic;
DCE_WriteDone : out std_logic;
DCE_ReadBusy : out std_logic;
DCE_WriteBusy : out std_logic
-- fio_icache_addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- fio_icache_data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- fio_icache_wea : in std_logic;
-- fio_icache_data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- fio_icache_ena : in std_logic
);
end component;
---------------------------------------------------------------------------------
-- change the lsbuf instance and DCE instance .. component declaration is fine
-----------------------------------------------------------------------
signal Alu_RdData,Alu_BranchAddr : std_logic_vector(31 downto 0);
signal Alu_RdPhyAddr : std_logic_vector(5 downto 0);
signal Alu_Branch ,Alu_BranchOutcome,Alu_BranchPredict,Alu_RdWrite,Alu_JrFlush : std_logic;
signal Alu_RobTag :std_logic_vector(4 downto 0);
signal Alu_BranchUptAddr :std_logic_vector(2 downto 0);
signal Bpb_BranchPrediction :std_logic;
signal Cdb_Valid,Cdb_PhyRegWrite,Cdb_BranchOutcome,Cdb_Branch,Cdb_Flush :std_logic;
signal Cdb_Data,Cdb_BranchAddr,Cdb_SwAddr :std_logic_vector(31 downto 0);
signal Cdb_RobTag,Cdb_RobDepth :std_logic_vector(4 downto 0);
signal Cdb_RdPhyAddr : std_logic_vector(5 downto 0);
signal Cdb_BranchUpdtAddr :std_logic_vector(2 downto 0);
signal Cfc_RdPhyAddr,Cfc_RsPhyAddr,Cfc_RtPhyAddr : std_logic_vector(5 downto 0);
signal Cfc_WalkBkwd,Cfc_WalkFwd,Cfc_Checkpoint,Cfc_Commit :std_logic;
signal Cfc_RobTag,Cfc_BranchTag : std_logic_vector(4 downto 0);
signal DCE_Opcode,DCE_ReadDone,DCE_WriteDone,DCE_ReadBusy,DCE_WriteBusy :std_logic;
signal DCE_RobTag :std_logic_vector(4 downto 0);
signal DCE_Addr,DCE_MemData :std_logic_vector(31 downto 0);
signal DCE_PhyAddr : std_logic_vector(5 downto 0);
signal Dis_Ren,Dis_JmpBr,Dis_JmpBrAddrValid,Dis_CdbUpdBranch,Dis_CdbBranchOutcome :std_logic;
signal Dis_JmpBrAddr,Dis_BranchOtherAddr,Dis_PcPlusFour :std_logic_vector(31 downto 0);
signal Dis_CdbUpdBranchAddr,Dis_BranchPCBits,Dis_BpbBranchPCBits,Dis_Opcode :std_logic_vector(2 downto 0);
signal Dis_CfcBranch,Dis_CfcRegWrite,Dis_Branch,Dis_BpbBranch,Dis_RegWrite,Dis_RsDataRdy,Dis_RtDataRdy,Dis_BranchPredict,Dis_JrRsInst :std_logic;
signal Dis_CfcRsAddr,Dis_CfcRtAddr,Dis_CfcRdAddr,Dis_RobRdAddr,Dis_CfcBranchTag ,Dis_RobTag:std_logic_vector(4 downto 0);
signal Dis_RsPhyAddr,Dis_RtPhyAddr,Dis_PrevPhyAddr,Dis_CfcNewRdPhyAddr, Dis_NewRdPhyAddr,Dis_SwRtPhyAddr:std_logic_vector(5 downto 0);
signal Dis_IntIssquenable,Dis_LdIssquenable,Dis_DivIssquenable,Dis_MulIssquenable ,Dis_FrlRead:std_logic;
signal Dis_Immediate :std_logic_vector(15 downto 0);
signal Dis_JalInst,Dis_RasJalInst,Dis_RasJr31Inst,Dis_Jr31Inst,Dis_CfcInstValid,Dis_InstValid,Dis_InstSw:std_logic;
signal Dis_instruction,Alu_instruction,Mul_instruction ,Div_instruction,Lsbuf_instruction, Cdb_instruction :std_logic_vector(31 downto 0);
signal Iss_instructionAlu,Iss_instructionMul,Iss_instructionDiv,Iss_instructionLsq,DCE_instruction : std_logic_vector(31 downto 0);
signal Div_RdPhyAddr :std_logic_vector(5 downto 0);
signal Div_RdWrite,Div_Done,Div_ExeRdy :std_logic;
signal Div_RobTag :std_logic_vector(4 downto 0);
signal Div_Rddata :std_logic_vector(31 downto 0);
signal Frl_RdPhyAddr:std_logic_vector(5 downto 0);
signal Frl_HeadPtr :std_logic_vector(4 downto 0);
signal Frl_Empty :std_logic;
signal Ifetch_Instruction,Ifetch_PcPlusFour,Ifetch_WpPcIn:std_logic_vector(31 downto 0);
signal Ifetch_EmptyFlag,Ifetch_ReadCache,Ifetch_AbortPrevRead :std_logic;
signal wp_report,rp_report,depth_report :std_logic_vector(4 downto 0);
signal Cache_Cd0,Cache_Cd1,Cache_Cd2,Cache_Cd3 :std_logic_vector(31 downto 0);
signal Cache_ReadHit :std_logic;
-- signal fio_icache_data_out_IM :std_logic_vector(127 downto 0);
signal Iss_Int,Iss_Mult,Iss_Div,Iss_Lsb :std_logic;
signal Issque_IntQueueFull,IssInt_Rdy,Iss_BranchAlu, Iss_RegWriteAlu:std_logic;
signal Iss_RsPhyAddrAlu,Iss_RtPhyAddrAlu,Iss_RdPhyAddrAlu :std_logic_vector(5 downto 0);
signal Iss_RobTagAlu :std_logic_vector(4 downto 0);
signal Iss_OpcodeAlu ,Iss_BranchUptAddrAlu:std_logic_vector(2 downto 0);
signal Iss_BranchAddrAlu :std_logic_vector(31 downto 0);
signal Iss_BranchPredictAlu,Iss_JalInstAlu,Iss_JrInstAlu,Iss_JrRsInstAlu:std_logic;
signal Iss_ImmediateAlu : std_logic_vector(15 downto 0);
signal Issque_DivQueueFull,IssDiv_Rdy,Iss_RegWriteDiv :std_logic;
signal Iss_RsPhyAddrDiv,Iss_RtPhyAddrDiv,Iss_RdPhyAddrDiv :std_logic_vector(5 downto 0);
signal Iss_RobTagDiv ,Iss_RobTagMul:std_logic_vector(4 downto 0);
signal Iss_OpcodeDiv,Iss_OpcodeMul :std_logic_vector(2 downto 0);
signal Issque_IntQueueTwoOrMoreVacant,Issque_MulQueueTwoOrMoreVacant,Issque_DivQueueTwoOrMoreVacant,Issque_LdStQueueTwoOrMoreVacant :std_logic;
signal Issque_MulQueueFull,IssMul_Rdy,Iss_RegWriteMul:std_logic;
signal Iss_RsPhyAddrMul,Iss_RtPhyAddrMul,Iss_RdPhyAddrMul :std_logic_vector(5 downto 0);
signal Lsbuf_LsqTaken,Lsbuf_DCETaken,Lsbuf_Full,IssLsb_Rdy,Lsbuf_RdWrite:std_logic;
signal Lsbuf_Data,Lsbuf_SwAddr,Iss_LdStAddr,Iss_LdStData:std_logic_vector(31 downto 0);
signal Lsbuf_PhyAddr :std_logic_vector(5 downto 0);
signal Lsbuf_RobTag:std_logic_vector(4 downto 0);
signal Iss_LdStQueueFull,Iss_LdStReady,Iss_LdStOpcode :std_logic;
signal Iss_RsPhyAddrLsq,Iss_RtPhyAddrLsq,Iss_LdStPhyAddr :std_logic_vector(5 downto 0);
signal Iss_LdStRobTag ,Mul_RobTag:std_logic_vector(4 downto 0);
signal Mul_RdPhyAddr ,Phs_PrevHeadPtr:std_logic_vector(5 downto 0);
signal Mul_RdWrite,Mul_Done :std_logic ;
signal Mul_RdData : std_logic_vector(31 downto 0);
signal PhyReg_RsDataRdy,PhyReg_RtDataRdy :std_logic ;
signal PhyReg_AluRsData,PhyReg_AluRtData,PhyReg_LsqRsData,PhyReg_LsqRtData:std_logic_vector(31 downto 0);
signal PhyReg_MultRsData,PhyReg_MultRtData,PhyReg_DivRsData,PhyReg_DivRtData,PhyReg_StoreData,Ras_Addr:std_logic_vector(31 downto 0);
signal Rob_Full,Rob_CommitMemWrite ,Rob_Commit,Rob_CommitRegWrite,Rob_WalkingRegWrite:std_logic;
signal Rob_SwAddr, Rob_Instruction :std_logic_vector(31 downto 0);
signal Rob_TopPtr,Rob_BottomPtr ,Rob_CommitRdAddr,Rob_WalkingRdAddr:std_logic_vector(4 downto 0);
signal Rob_CommitPrePhyAddr,Rob_CommitCurrPhyAddr,Rob_WalkingPrePhyAddr,Rob_WalkingCurrPhyAddr:std_logic_vector(5 downto 0);
signal Rob_Walking,Rob_WalkBkd,Rob_WalkFwd,Rob_TwoOrMoreVacant :std_logic;
signal SB_Full,SB_Stall,SB_FlushSw,SB_DataValid :std_logic ;
--signal SB_FlushSwTag :std_logic_vector(4 downto 0); Modified by Waleed 06/04/10
signal SB_FlushSwTag :std_logic_vector(1 downto 0);
signal SBTag_counter :std_logic_vector(1 downto 0); --Added by Waleed 06/04/10
signal SB_DataDmem,SB_AddrDmem :std_logic_vector(31 downto 0);
signal Iss_LdStIssued,Lsbuf_Done,DCE_ReadCache,SB_InputValid,Cfc_Full:std_logic; -- July 15, 2011 Gandhi: Removed Abort_PrevRead
-- signal Iss_LdStIssued,Lsbuf_Done,DCE_ReadCache,Abort_PrevRead ,SB_InputValid,Cfc_Full:std_logic;
signal Cfc_FrlHeadPtr : std_logic_vector(4 downto 0);
-- signal ifetch_instruction_sig : std_logic_vector(31 downto 0);
-- signal ifetch_instruction_string_sig : string(1 to 24) := "Empty_Empty_Empty_Empty";
-- translate_off
signal IfetchInst_string : string(1 to 24) := (others => ' ');
signal DisInst_string : string(1 to 24) := (others => ' ');
signal IntQueueInst_string : string(1 to 24) := (others => ' ');
signal MulQueueInst_string : string(1 to 24) := (others => ' ');
signal DivQueueInst_string : string(1 to 24) := (others => ' ');
signal LdStQueueInst_string : string(1 to 24) := (others => ' ');
signal CdbInst_string : string(1 to 24) := (others => ' ');
signal RobInst_string : string(1 to 24) := (others => ' ');
-- translate_on
signal Resetb : std_logic ;
signal Dmem_ReadAddr : std_logic_vector(31 downto 0);
signal Dmem_WriteAddr : std_logic_vector(31 downto 0);
signal SB_WriteCache: std_logic;
signal Dmem_WriteData : std_logic_vector(31 downto 0);
signal walking_led_counter : std_logic_vector(24 downto 0);
begin
-----------------------------------------------------------------------------------------------
----- Components Interface -------------------
-----------------------------------------------------------------------------------------------
-- synopsys translate_off
--ifetch_instruction_string_sig <= reverse_Assembly(ifetch_instruction_sig);
-- synopsys translate_on
Resetb <= not(reset) ;
Dmem_ReadAddr(31 downto 8) <= (others => '0');
Dmem_ReadAddr(1 downto 0) <= (others => '0');
Dmem_ReadAddr ( 7 downto 2 ) <= fio_dmem_addr_DM when Test_mode = '1' else
Iss_LdStAddr ( 7 downto 2 );
fio_dmem_data_out_DM <= DCE_MemData;
Dmem_WriteAddr(7 downto 2 ) <= fio_dmem_addr_DM when Test_mode = '1' else
SB_AddrDmem(7 downto 2);
Dmem_WriteData <= fio_dmem_data_in_DM when Test_mode = '1' else
SB_DataDmem;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- to support memory mapped I/O from location 64 onwards
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
SB_WriteCache <= fio_dmem_wea_DM when Test_mode = '1' else
--'0' when mem_addr(8)='1' else
SB_DataValid; --don't write to the memory if it is memory mapped i/o
walking_led_start <= '0' when (walking_led_counter = "0000000000000000000000000") else '1'; -- enable the walking LED based on counter
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
process(Resetb, Clk )
begin
if(Resetb = '0') then
walking_led_counter <= "0000000000000000000000000";
elsif( Clk'event and Clk = '1' ) then
-- if (SB_DataValid = '1' and SB_AddrDmem(7 downto 2) = "111111") then
if (Dis_JmpBr = '1') then -- July 15, 2011 Instead of store word, we are using JUMP as trigger to walking LED
walking_led_counter <= "1011111010111100001000000"; -- This value is chosen so that downcount to zero takes 10 seconds for 25 MHz Clock.
-- walking_led_counter <= "1111111010111100001000000"; -- This value is chosen so that downcount to zero takes 10 seconds for 25 MHz Clock.
elsif (walking_led_counter /= "0000000000000000000000000") then
walking_led_counter <= walking_led_counter - 1;
end if;
end if;
end process;
---- USING REVERSE ASSEMBLY FUNCTION FOR AIDING DEBUGGING
-- translate_off
IfetchInst_string <= reverse_Assembly(Ifetch_Instruction);
DisInst_String <= reverse_Assembly(Dis_Instruction);
IntQueueInst_String <= reverse_Assembly(Iss_instructionAlu); -- output of Int queue.. Instruciton which is ready in integer queue to be sent to ALu
MulQueueInst_String <= reverse_Assembly(Iss_instructionMul); -- output of Mul queue.. Instruciton which is ready in integer queue to be sent to Mul
DivQueueInst_String <= reverse_Assembly(Iss_instructionDiv); -- output of Div queue.. Instruciton which is ready in integer queue to be sent to Div
LdStQueueInst_String <= reverse_Assembly(Iss_instructionLsq); -- output of LdSt queue.. Instruciton which is ready in integer queue to be sent to LsBuf/DCE
CdbInst_String <= reverse_Assembly(Cdb_Instruction); -- instruction on Cdb
RobInst_String <= reverse_Assembly(Rob_Instruction); -- instruction at Rob Top
-- translate_on
PhyRegFile : PhysicalRegister_File
generic map(
tag_width => 6
)
port map(
Clk => Clk ,
Resetb => Resetb ,
---Interface with Integer Issue queue---
Iss_RsPhyAddrAlu => Iss_RsPhyAddrAlu,
Iss_RtPhyAddrAlu => Iss_RtPhyAddrAlu,
---Interface with Load Store Issue queue---
Iss_RsPhyAddrLsq => Iss_RsPhyAddrLsq,
---Interface with Multiply Issue queue---
Iss_RsPhyAddrMul => Iss_RsPhyAddrMul,
Iss_RtPhyAddrMul => Iss_RtPhyAddrMul,
---Interface with Divide Issue queue---
Iss_RsPhyAddrDiv => Iss_RsPhyAddrDiv,
Iss_RtPhyAddrDiv => Iss_RtPhyAddrDiv,
---Interface with Dispatch---
Dis_RsAddr => Cfc_RsPhyAddr,
PhyReg_RsDataRdy => PhyReg_RsDataRdy,
Dis_RtAddr => Cfc_RtPhyAddr,
PhyReg_RtDataRdy => PhyReg_RtDataRdy,
Dis_NewRdPhyAddr => Dis_NewRdPhyAddr,
Dis_RegWrite => Dis_RegWrite,
---Interface with Integer Execution Unit---
PhyReg_AluRsData => PhyReg_AluRsData,
PhyReg_AluRtData => PhyReg_AluRtData,
---Interface with Load Store Execution Unit---
PhyReg_LsqRsData => PhyReg_LsqRsData,
---Interface with Multiply Execution Unit---
PhyReg_MultRsData => PhyReg_MultRsData,
PhyReg_MultRtData => PhyReg_MultRtData,
---Interface with Divide Execution Unit---
PhyReg_DivRsData => PhyReg_DivRsData,
PhyReg_DivRtData => PhyReg_DivRtData,
---Interface with CDB ---
Cdb_RdData => Cdb_Data,
Cdb_RdPhyAddr => Cdb_RdPhyAddr,
Cdb_Valid => Cdb_Valid,
Cdb_PhyRegWrite => Cdb_PhyRegWrite,
---Interface with Store Buffer ---
Rob_CommitCurrPhyAddr => Rob_CommitCurrPhyAddr,
PhyReg_StoreData => PhyReg_StoreData
);
-----------------------------------------------------------------------------------------------
inst_cache_inst: inst_cache
generic map ( DATA_WIDTH => 128,
ADDR_WIDTH => 6 )
port map (
Clk => Clk,
Resetb => Resetb,
read_cache => Ifetch_ReadCache,
abort_prev_read => Ifetch_AbortPrevRead,
addr => Ifetch_WpPcIn,
cd0 => Cache_Cd0 ,
cd1 => Cache_Cd1 ,
cd2 => Cache_Cd2,
cd3 => Cache_Cd3 ,
-- synopsys translate_off
registered_addr => open,
-- synopsys translate_on
read_hit => Cache_ReadHit,
fio_icache_addr_a => fio_icache_addr_IM,
fio_icache_data_in_a => fio_icache_data_in_IM,
fio_icache_wea => fio_icache_wea_IM,
fio_icache_data_out_a => fio_icache_data_out_IM,
fio_icache_ena => fio_icache_ena_IM
);
----------------------------------------------------------------------------------------------
ifetch_queue : i_fetch_q
port map(
Clk => Clk,
Resetb => Resetb,
-- interface with the dispatch unit
Ifetch_Instruction => Ifetch_Instruction,
Ifetch_PcPlusFour => Ifetch_PcPlusFour ,
Ifetch_EmptyFlag => Ifetch_EmptyFlag,
Dis_Ren => Dis_Ren,
Dis_JmpBrAddr => Dis_JmpBrAddr,
Dis_JmpBr => Dis_JmpBr,
Dis_JmpBrAddrValid => Dis_JmpBrAddrValid,
-- interface with the cache unit
Ifetch_WpPcIn =>Ifetch_WpPcIn,
Ifetch_ReadCache => Ifetch_ReadCache,
-- synopsys translate_off
wp_report => wp_report,
rp_report => rp_report,
depth_report => depth_report,
-- synopsys translate_on
Ifetch_AbortPrevRead => Ifetch_AbortPrevRead,
Cache_Cd0 => Cache_Cd0,
Cache_Cd1 => Cache_Cd1,
Cache_Cd2 => Cache_Cd2,
Cache_Cd3 => Cache_Cd3,
Cache_ReadHit => Cache_ReadHit
);
-----------------------------------------------------------------------------------------------
branch_predictor : bpb
port map(
Clk => Clk,
Resetb => Resetb,
---- rob -------
Dis_CdbUpdBranch => Dis_CdbUpdBranch,
Dis_CdbUpdBranchAddr =>Dis_CdbUpdBranchAddr,
Dis_CdbBranchOutcome =>Dis_CdbBranchOutcome,
------------------
---- dispatch --------------
Bpb_BranchPrediction =>Bpb_BranchPrediction,
Dis_BpbBranchPCBits =>Dis_BpbBranchPCBits,
Dis_BpbBranch =>Dis_BpbBranch
---------------------------
);
-----------------------------------------------------------------------------------------------
ras_unit : ras
port map(
--global signals
Resetb => Resetb,
Clk => Clk,
-- Interface with Dispatch
--inputs
Dis_PcPlusFour =>Dis_PcPlusFour,
Dis_RasJalInst =>Dis_RasJalInst,
Dis_RasJr31Inst =>Dis_RasJr31Inst,
--outputs
Ras_Addr =>Ras_Addr
);
-----------------------------------------------------------------------------------------------
dispatch_inst : dispatch_unit
port map(
Clk =>Clk,
Resetb =>Resetb,
-- Interface with Intsruction Fetch Queue
Ifetch_Instruction =>Ifetch_Instruction,
Ifetch_PcPlusFour =>Ifetch_PcPlusFour,
Ifetch_EmptyFlag =>Ifetch_EmptyFlag,
Dis_Ren =>Dis_Ren,
Dis_JmpBrAddr =>Dis_JmpBrAddr,
Dis_JmpBr =>Dis_JmpBr,
Dis_JmpBrAddrValid =>Dis_JmpBrAddrValid,
-- Interface with branch prediction buffer
Dis_CdbUpdBranch =>Dis_CdbUpdBranch,
Dis_CdbUpdBranchAddr =>Dis_CdbUpdBranchAddr,
Dis_CdbBranchOutcome => Dis_CdbBranchOutcome,
Bpb_BranchPrediction =>Bpb_BranchPrediction,
Dis_BpbBranchPCBits =>Dis_BpbBranchPCBits,
Dis_BpbBranch =>Dis_BpbBranch,
-- interface with the cdb
Cdb_Branch =>Cdb_Branch,
Cdb_BranchOutcome =>Cdb_BranchOutcome,
Cdb_BranchAddr =>Cdb_BranchAddr,
Cdb_BrUpdtAddr =>Cdb_BranchUpdtAddr,
Cdb_Flush =>Cdb_Flush,
Cdb_RobTag =>Cdb_RobTag,
------------------------------------------------------------------------------
-- interface with checkpoint module
Dis_CfcRsAddr =>Dis_CfcRsAddr,
Dis_CfcRtAddr =>Dis_CfcRtAddr,
Dis_CfcRdAddr =>Dis_CfcRdAddr,
-- goes to Dis_RobRdAddr of ROB too
Cfc_RsPhyAddr =>Cfc_RsPhyAddr,
Cfc_RtPhyAddr =>Cfc_RtPhyAddr,
Cfc_RdPhyAddr =>Cfc_RdPhyAddr,
Cfc_Full =>Cfc_Full,
Dis_CfcBranchTag =>Dis_CfcBranchTag,
Dis_CfcRegWrite =>Dis_CfcRegWrite,
Dis_CfcNewRdPhyAddr =>Dis_CfcNewRdPhyAddr,
Dis_CfcBranch =>Dis_CfcBranch,
Dis_CfcInstValid =>Dis_CfcInstValid,
--------------------------------------------------------------------------------
-- physical register interface
PhyReg_RsDataRdy =>PhyReg_RsDataRdy,
PhyReg_RtDataRdy =>PhyReg_RtDataRdy,
-- interface with issue queues
-- translate_off
Dis_Instruction =>Dis_instruction,
-- translate_on
Dis_RegWrite =>Dis_RegWrite,
Dis_RsDataRdy =>Dis_RsDataRdy,
Dis_RtDataRdy => Dis_RtDataRdy,
Dis_RsPhyAddr =>Dis_RsPhyAddr,
Dis_RtPhyAddr => Dis_RtPhyAddr,
Dis_RobTag =>Dis_RobTag,
Dis_Opcode =>Dis_Opcode,
Dis_IntIssquenable =>Dis_IntIssquenable,
Dis_LdIssquenable =>Dis_LdIssquenable,
Dis_DivIssquenable =>Dis_DivIssquenable,
Dis_MulIssquenable =>Dis_MulIssquenable,
Dis_Immediate =>Dis_Immediate,
Issque_IntQueueFull =>Issque_IntQueueFull,
Issque_LdStQueueFull =>Iss_LdStQueueFull,
Issque_DivQueueFull =>Issque_DivQueueFull,
Issque_MulQueueFull =>Issque_MulQueueFull,
Issque_IntQueTwoOrMoreVacant =>Issque_IntQueueTwoOrMoreVacant,
Issque_LdStQueTwoOrMoreVacant =>Issque_LdStQueueTwoOrMoreVacant,
Issque_DivQueTwoOrMoreVacant =>Issque_DivQueueTwoOrMoreVacant,
Issque_MulQueTwoOrMoreVacant =>Issque_MulQueueTwoOrMoreVacant,
Dis_BranchOtherAddr =>Dis_BranchOtherAddr,
Dis_BranchPredict =>Dis_BranchPredict,
Dis_BranchPCBits =>Dis_BranchPCBits,
Dis_Branch =>Dis_Branch,
Dis_JrRsInst =>Dis_JrRsInst,
Dis_JalInst =>Dis_JalInst,
Dis_Jr31Inst =>Dis_Jr31Inst,
----------------------------------------------------------------------------------
---- interface with the FRL----
Frl_RdPhyAddr =>Frl_RdPhyAddr,
Dis_FrlRead =>Dis_FrlRead,
Frl_Empty =>Frl_Empty,
----------------------------------------------------------------------------------
---- interface with the RAS----
Dis_RasJalInst =>Dis_RasJalInst,
Dis_RasJr31Inst =>Dis_RasJr31Inst,
Dis_PcPlusFour =>Dis_PcPlusFour,
Ras_Addr =>Ras_Addr,
Dis_PrevPhyAddr =>Dis_PrevPhyAddr,
Dis_NewRdPhyAddr =>Dis_NewRdPhyAddr,
Dis_RobRdAddr =>Dis_RobRdAddr, -- send to Physical register file too.. so that he can make data ready bit "0"
Dis_InstValid =>Dis_InstValid,
Dis_InstSw => Dis_InstSw,
Dis_SwRtPhyAddr =>Dis_SwRtPhyAddr,
Rob_BottomPtr =>Rob_BottomPtr,
Rob_Full =>Rob_Full,
Rob_TwoOrMoreVacant =>Rob_TwoOrMoreVacant
);
-----------------------------------------------------------------------------------------------
cfc_inst : cfc
port map( --global signals
Clk =>Clk,
Resetb =>Resetb,
--interface with dispatch unit
Dis_CfcBranchTag =>Dis_CfcBranchTag,
Dis_CfcRdAddr =>Dis_CfcRdAddr,
Dis_CfcRsAddr =>Dis_CfcRsAddr,
Dis_CfcRtAddr =>Dis_CfcRtAddr,
Dis_CfcNewRdPhyAddr =>Dis_CfcNewRdPhyAddr,
Dis_CfcRegWrite =>Dis_CfcRegWrite,
Dis_CfcBranch =>Dis_CfcBranch,
Dis_InstValid =>Dis_CfcInstValid,
Dis_Jr31Inst =>Dis_RasJr31Inst,
Cfc_RdPhyAddr =>Cfc_RdPhyAddr,
Cfc_RsPhyAddr =>Cfc_RsPhyAddr,
Cfc_RtPhyAddr =>Cfc_RtPhyAddr,
Cfc_Full =>Cfc_Full,
--interface with ROB
Rob_TopPtr =>Rob_TopPtr,
Rob_Commit =>Rob_Commit,
Rob_CommitRdAddr =>Rob_CommitRdAddr,
Rob_CommitRegWrite =>Rob_CommitRegWrite,
Rob_CommitCurrPhyAddr =>Rob_CommitCurrPhyAddr,
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag =>Cfc_RobTag,
--interface with PHP
Frl_HeadPtr =>Frl_HeadPtr,
Cfc_FrlHeadPtr =>Cfc_FrlHeadPtr,
--interface with CDB
Cdb_Flush =>Cdb_Flush,
Cdb_RobTag =>Cdb_RobTag,
Cdb_RobDepth =>Cdb_RobDepth
);
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
frl_inst : Frl
generic map(WIDE => 6 ,
DEEP => 16,
PTRWIDTH => 5)
port map(
--Inputs
Clk =>Clk,
Resetb =>Resetb,
Cdb_Flush =>Cdb_Flush,
--Interface with Rob
Rob_CommitPrePhyAddr =>Rob_CommitPrePhyAddr,
Rob_Commit =>Rob_Commit,
Rob_CommitRegWrite =>Rob_CommitRegWrite,
Cfc_FrlHeadPtr =>Cfc_FrlHeadPtr,
--Intreface with Dis_FrlRead unit
Frl_RdPhyAddr =>Frl_RdPhyAddr,
Dis_FrlRead =>Dis_FrlRead,
Frl_Empty =>Frl_Empty,
--Interface with Previous Head Pointer Stack
Frl_HeadPtr =>Frl_HeadPtr
);
-----------------------------------------------------------------------------------------------
alu_inst : ALU
generic map(
tag_width =>6
)
port map(
PhyReg_AluRsData =>PhyReg_AluRsData,
PhyReg_AluRtData =>PhyReg_AluRtData,
Iss_OpcodeAlu =>Iss_OpcodeAlu,
Iss_RobTagAlu =>Iss_RobTagAlu,
Iss_RdPhyAddrAlu =>Iss_RdPhyAddrAlu,
Iss_BranchAddrAlu =>Iss_BranchAddrAlu,
Iss_BranchAlu =>Iss_BranchAlu,
Iss_RegWriteAlu =>Iss_RegWriteAlu,
Iss_BranchUptAddrAlu =>Iss_BranchUptAddrAlu,
Iss_BranchPredictAlu =>Iss_BranchPredictAlu,
Iss_JalInstAlu =>Iss_JalInstAlu,
Iss_JrInstAlu =>Iss_JrInstAlu,
Iss_JrRsInstAlu =>Iss_JrRsInstAlu,
Iss_ImmediateAlu =>Iss_ImmediateAlu,
-- translate_off
Iss_instructionAlu =>Iss_instructionAlu ,
-- translate_on
Alu_RdData =>Alu_RdData,
Alu_RdPhyAddr =>Alu_RdPhyAddr,
Alu_BranchAddr =>Alu_BranchAddr,
Alu_Branch =>Alu_Branch,
Alu_BranchOutcome =>Alu_BranchOutcome,
-- translate_off
Alu_instruction =>Alu_instruction,
-- translate_on
Alu_RobTag =>Alu_RobTag,
Alu_BranchUptAddr =>Alu_BranchUptAddr,
Alu_BranchPredict =>Alu_BranchPredict,
Alu_RdWrite =>Alu_RdWrite,
Alu_JrFlush =>Alu_JrFlush
);
-----------------------------------------------------------------------------------------------
integer_queue_inst : issueque
port map(
-- Global Clk and Resetb Signals
Clk =>Clk,
Resetb =>Resetb,
-- Information to be captured from the Lsb Buffer
Lsbuf_PhyAddr =>Lsbuf_PhyAddr,
Lsbuf_RdWrite =>Lsbuf_RdWrite,
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr =>Cdb_RdPhyAddr,
Cdb_PhyRegWrite =>Cdb_PhyRegWrite,
-- Information from the Dispatch Unit
Dis_Issquenable =>Dis_IntIssquenable,
Dis_RsDataRdy =>Dis_RsDataRdy,
Dis_RtDataRdy =>Dis_RtDataRdy,
Dis_RegWrite =>Dis_RegWrite,
Dis_RsPhyAddr =>Dis_RsPhyAddr,
Dis_RtPhyAddr =>Dis_RtPhyAddr,
Dis_NewRdPhyAddr =>Dis_NewRdPhyAddr,
Dis_RobTag =>Dis_RobTag,
Dis_Opcode =>Dis_Opcode,
Dis_Immediate =>Dis_Immediate,
Dis_Branch =>Dis_Branch,
Dis_BranchPredict =>Dis_BranchPredict,
Dis_BranchOtherAddr =>Dis_BranchOtherAddr,
Dis_BranchPCBits =>Dis_BranchPCBits,
Issque_IntQueueFull =>Issque_IntQueueFull,
Issque_IntQueueTwoOrMoreVacant =>Issque_IntQueueTwoOrMoreVacant,
Dis_Jr31Inst =>Dis_Jr31Inst,
Dis_JalInst =>Dis_JalInst,
Dis_JrRsInst =>Dis_JrRsInst,
-- translate_off
Dis_instruction => Dis_instruction,
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy =>IssInt_Rdy,
Iss_Int =>Iss_Int ,
Iss_Lsb => Iss_Lsb,
-- Interface with the Multiply execution unit
Mul_RdPhyAddr => Mul_RdPhyAddr,
Mul_ExeRdy => Mul_Done,
Div_RdPhyAddr => Div_RdPhyAddr,
Div_ExeRdy => Div_ExeRdy,
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu =>Iss_RsPhyAddrAlu,
Iss_RtPhyAddrAlu =>Iss_RtPhyAddrAlu,
-- Interface with the Execution unit
Iss_RdPhyAddrAlu =>Iss_RdPhyAddrAlu,
Iss_RobTagAlu =>Iss_RobTagAlu,
Iss_OpcodeAlu =>Iss_OpcodeAlu,
Iss_BranchAddrAlu =>Iss_BranchAddrAlu,
Iss_BranchAlu =>Iss_BranchAlu,
Iss_RegWriteAlu =>Iss_RegWriteAlu,
Iss_BranchUptAddrAlu =>Iss_BranchUptAddrAlu,
Iss_BranchPredictAlu =>Iss_BranchPredictAlu,
Iss_JalInstAlu =>Iss_JalInstAlu,
Iss_JrInstAlu =>Iss_JrInstAlu,
Iss_JrRsInstAlu =>Iss_JrRsInstAlu,
Iss_ImmediateAlu =>Iss_ImmediateAlu,
-- translate_off
Iss_instructionAlu =>Iss_instructionAlu,
-- translate_on
-- Interface with ROB
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth
) ;
-----------------------------------------------------------------------------------------------
mult_inst : multiplier
generic map(
tag_width => 6
)
port map(
Clk =>Clk,
Resetb =>Resetb,
Iss_Mult =>Iss_Mult,
PhyReg_MultRsData =>PhyReg_MultRsData,
PhyReg_MultRtData =>PhyReg_MultRtData,
Iss_RobTag =>Iss_RobTagMul,
--
Mul_RdPhyAddr =>Mul_RdPhyAddr,
Mul_RdWrite =>Mul_RdWrite,
Iss_RdPhyAddr =>Iss_RdPhyAddrMul,
Iss_RdWrite => Iss_RegWriteMul,
--
-- translate_off
Iss_instructionMul =>Iss_instructionMul,
-- translate_on
-- translate_off
Mul_instruction =>Mul_instruction,
-- translate_on
Mul_RdData =>Mul_RdData,
Mul_RobTag =>Mul_RobTag,
Mul_Done =>Mul_Done,
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth
);
-----------------------------------------------------------------------------------------------
MultIssueQue_inst : issueque_mult
port map(
-- Global Clk and Resetb Signals
Clk =>Clk,
Resetb =>Resetb,
-- Information to be captured from the Lsb Buffer
Lsbuf_PhyAddr =>Lsbuf_PhyAddr,
Lsbuf_RdWrite =>Lsbuf_RdWrite,
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr =>Cdb_RdPhyAddr,
Cdb_PhyRegWrite =>Cdb_PhyRegWrite,
-- Information from the Dispatch Unit
Dis_Issquenable =>Dis_MulIssquenable,
Dis_RsDataRdy =>Dis_RsDataRdy,
Dis_RtDataRdy =>Dis_RtDataRdy,
Dis_RegWrite =>Dis_RegWrite,
Dis_RsPhyAddr =>Dis_RsPhyAddr,
Dis_RtPhyAddr =>Dis_RtPhyAddr,
Dis_NewRdPhyAddr =>Dis_NewRdPhyAddr,
Dis_RobTag =>Dis_RobTag,
Dis_Opcode =>Dis_Opcode,
Issque_MulQueueFull =>Issque_MulQueueFull,
Issque_MulQueueTwoOrMoreVacant =>Issque_MulQueueTwoOrMoreVacant,
-- translate_off
Dis_instruction =>Dis_instruction,
-- translate_on
-- Interface with the Issue Unit
IssMul_Rdy =>IssMul_Rdy,
Iss_Mult =>Iss_Mult,
Iss_Int => Iss_Int,
Iss_Lsb => Iss_Lsb,
-- Interface with the Multiply execution unit
Iss_RdPhyAddrAlu =>Iss_RdPhyAddrAlu,
Iss_PhyRegValidAlu =>Iss_RegWriteAlu,
Mul_RdPhyAddr =>Mul_RdPhyAddr,
Mul_ExeRdy =>Mul_Done,
Div_RdPhyAddr =>Div_RdPhyAddr,
Div_ExeRdy =>Div_ExeRdy,
-- translate_off
Iss_instructionMul =>Iss_instructionMul,
-- translate_on
-- Interface with the Physical Register File
Iss_RsPhyAddrMul =>Iss_RsPhyAddrMul,
Iss_RtPhyAddrMul =>Iss_RtPhyAddrMul,
-- Interface with the Execution unit
Iss_RdPhyAddrMul =>Iss_RdPhyAddrMul,
Iss_RobTagMul =>Iss_RobTagMul,
Iss_OpcodeMul =>Iss_OpcodeMul,
Iss_RegWriteMul =>Iss_RegWriteMul,
-- Interface with ROB
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth
) ;
-----------------------------------------------------------------------------------------------
divider_inst : divider
generic map(
tag_width => 6
)
port map(
Clk =>Clk,
Resetb =>Resetb,
PhyReg_DivRsData =>PhyReg_DivRsData,
PhyReg_DivRtData =>PhyReg_DivRtData,
Iss_RobTag =>Iss_RobTagDiv,
Iss_Div =>Iss_Div,
--
Div_RdPhyAddr =>Div_RdPhyAddr,
Div_RdWrite =>Div_RdWrite,
Iss_RdPhyAddr =>Iss_RdPhyAddrDiv,
Iss_RdWrite => Iss_RegWriteDiv,
--
-- translate_off
Iss_instructionDiv =>Iss_instructionDiv,
-- translate_on
-- translate_off
Div_instruction =>Div_instruction,
-- translate_on
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth,
Div_Done =>Div_Done,
Div_RobTag =>Div_RobTag,
Div_Rddata =>Div_Rddata,
Div_ExeRdy =>Div_ExeRdy
);
-----------------------------------------------------------------------------------------------
DivIssQue_inst : issueque_div
port map(
-- Global Clk and Resetb Signals
Clk =>Clk,
Resetb =>Resetb,
-- Information to be captured from the Lsb Buffer
Lsbuf_PhyAddr =>Lsbuf_PhyAddr,
Lsbuf_RdWrite =>Lsbuf_RdWrite,
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr =>Cdb_RdPhyAddr,
Cdb_PhyRegWrite =>Cdb_PhyRegWrite,
-- Information from the Dispatch Unit
Dis_Issquenable =>Dis_DivIssquenable,
Dis_RsDataRdy =>Dis_RsDataRdy,
Dis_RtDataRdy =>Dis_RtDataRdy,
Dis_RegWrite =>Dis_RegWrite,
Dis_RsPhyAddr =>Dis_RsPhyAddr,
Dis_RtPhyAddr =>Dis_RtPhyAddr,
Dis_NewRdPhyAddr =>Dis_NewRdPhyAddr,
Dis_RobTag =>Dis_RobTag,
Dis_Opcode =>Dis_Opcode,
Issque_DivQueueFull =>Issque_DivQueueFull,
Issque_DivQueueTwoOrMoreVacant =>Issque_DivQueueTwoOrMoreVacant,
-- translate_off
Dis_instruction =>Dis_instruction,
-- translate_on
-- Interface with the Issue Unit
IssDiv_Rdy =>IssDiv_Rdy,
Iss_Div =>Iss_Div,
Iss_Int => Iss_Int,
Iss_Lsb => Iss_Lsb,
-- Interface with the Multiply execution unit
Iss_RdPhyAddrAlu =>Iss_RdPhyAddrAlu,
Iss_PhyRegValidAlu =>Iss_RegWriteAlu,
Mul_RdPhyAddr =>Mul_RdPhyAddr,
Mul_ExeRdy =>Mul_Done,
Div_RdPhyAddr =>Div_RdPhyAddr,
Div_ExeRdy =>Div_ExeRdy,
-- Interface with the Physical Register File
Iss_RsPhyAddrDiv =>Iss_RsPhyAddrDiv,
Iss_RtPhyAddrDiv =>Iss_RtPhyAddrDiv,
-- Interface with the Execution unit
Iss_RdPhyAddrDiv =>Iss_RdPhyAddrDiv,
Iss_RobTagDiv =>Iss_RobTagDiv,
Iss_OpcodeDiv =>Iss_OpcodeDiv,
Iss_RegWriteDiv =>Iss_RegWriteDiv,
-- translate_off
Iss_instructionDiv =>Iss_instructionDiv,
-- translate_on
-- Interface with ROB
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth
) ;
-----------------------------------------------------------------------------------------------
LoadStoreQue_inst : lsq
port map(
-- Global Clk and Resetb Signals
Clk =>Clk,
Resetb =>Resetb,
-- Information to be captured from the CDB (Common Data Bus)
Cdb_RdPhyAddr =>Cdb_RdPhyAddr,
Cdb_PhyRegWrite => Cdb_PhyRegWrite,
Cdb_Valid =>Cdb_Valid,
-- Information from the Dispatch Unit
Dis_Opcode =>Dis_Opcode(0),
Dis_Immediate =>Dis_Immediate,
Dis_RsDataRdy =>Dis_RsDataRdy,
Dis_RsPhyAddr =>Dis_RsPhyAddr,
Dis_RobTag =>Dis_RobTag,
Dis_NewRdPhyAddr =>Dis_NewRdPhyAddr,
Dis_LdIssquenable =>Dis_LdIssquenable,
Issque_LdStQueueFull =>Iss_LdStQueueFull,
Issque_LdStQueueTwoOrMoreVacant =>Issque_LdStQueueTwoOrMoreVacant,
-- translate_off
Dis_instruction =>Dis_instruction,
-- translate_on
-- translate_off
Iss_instructionLsq =>Iss_instructionLsq,
-- translate_on
-- interface with PRF
Iss_RsPhyAddrLsq =>Iss_RsPhyAddrLsq,
PhyReg_LsqRsData =>PhyReg_LsqRsData,
-- Interface with the Issue Unit
Iss_LdStReady =>Iss_LdStReady,
Iss_LdStOpcode =>Iss_LdStOpcode,
Iss_LdStRobTag =>Iss_LdStRobTag,
Iss_LdStAddr =>Iss_LdStAddr,
Iss_LdStIssued =>Iss_LdStIssued,
Iss_LdStPhyAddr => Iss_LdStPhyAddr,
DCE_ReadBusy =>DCE_ReadBusy,
Lsbuf_Done =>Lsbuf_Done,
-- Interface with ROB
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth,
SB_FlushSw =>SB_FlushSw,
SB_FlushSwTag =>SB_FlushSwTag,
SBTag_counter => SBTag_counter, --Added by Waleed 06/04/10
Rob_CommitMemWrite => Rob_CommitMemWrite--Added by Waleed 06/04/10
);
Iss_LdStIssued <= (((not(Lsbuf_Full) and not(Iss_LdStOpcode)) or (Iss_LdStOpcode and (not DCE_ReadBusy))) and Iss_LdStReady); -- lw /sw is ready to leave LSQ
Lsbuf_Done <= (not Lsbuf_Full);
DCE_ReadCache <= '1' when Test_mode = '1' else Iss_LdStReady and Iss_LdStOpcode and (not DCE_ReadBusy); -- changed by vaibhav
-----------------------------------------------------------------------------------------------
datacache_inst : data_cache
generic map(
DATA_WIDTH => 32 ,
ADDR_WIDTH =>6
)
port map(
Clk => Clk,
Resetb => Resetb,
DCE_ReadCache => DCE_ReadCache,
-- Abort_PrevRead => Abort_PrevRead, -- July 15, 2011 Gandhi: Commented out this line
--addr : in std_logic_vector (5 downto 0);
Iss_LdStOpcode => Iss_LdStOpcode,
Iss_LdStRobTag =>Iss_LdStRobTag,
Iss_LdStAddr =>Dmem_ReadAddr,
Iss_LdStPhyAddr =>Iss_LdStPhyAddr,
Lsbuf_DCETaken =>Lsbuf_DCETaken,
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth,
SB_WriteCache =>SB_WriteCache,
SB_AddrDmem =>Dmem_WriteAddr,
SB_DataDmem =>Dmem_WriteData,
-- translate_off
DCE_instruction =>DCE_instruction,
Iss_instructionLsq =>Iss_instructionLsq,
-- translate_on
--data_out : out std_logic_vector (31 downto 0);
DCE_Opcode =>DCE_Opcode,
DCE_RobTag =>DCE_RobTag,
DCE_Addr =>DCE_Addr,
DCE_MemData =>DCE_MemData,
DCE_PhyAddr => DCE_PhyAddr,
-- synopsys translate_off
registered_addr =>open ,
registered_SB_AddrDmem => open,
-- synopsys translate_on
DCE_ReadDone =>DCE_ReadDone,
DCE_WriteDone =>DCE_WriteDone,
DCE_ReadBusy =>DCE_ReadBusy,
DCE_WriteBusy =>DCE_WriteBusy
-- fio_icache_addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- fio_icache_data_in_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- fio_icache_wea : in std_logic;
-- fio_icache_data_out_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- fio_icache_ena : in std_logic
);
-----------------------------------------------------------------------------------------------
lsBuf_inst : ls_buffer
port map(
Clk =>Clk,
Resetb =>Resetb,
-- from ROB -- for fulsing the instruction in this buffer if appropriate.
Cdb_Flush =>Cdb_Flush,
Rob_TopPtr =>Rob_TopPtr,
Cdb_RobDepth =>Cdb_RobDepth,
-- interface with lsq
Iss_LdStReady =>Iss_LdStReady,
Iss_LdStOpcode =>Iss_LdStOpcode,
Iss_LdStRobTag =>Iss_LdStRobTag,
Iss_LdStAddr =>Iss_LdStAddr,
Iss_LdStData =>Iss_LdStData,
Iss_LdStPhyAddr =>Iss_LdStPhyAddr,
-- translate_off
DCE_instruction =>DCE_instruction,
Iss_instructionLsq =>Iss_instructionLsq,
-- translate_on
---- interface with data cache emulator ----------------
DCE_PhyAddr =>DCE_PhyAddr,
DCE_Opcode =>DCE_Opcode,
DCE_RobTag =>DCE_RobTag,
DCE_Addr =>DCE_Addr,
DCE_MemData =>DCE_MemData,
DCE_ReadDone =>DCE_ReadDone,
Lsbuf_LsqTaken =>Lsbuf_LsqTaken,
Lsbuf_DCETaken =>Lsbuf_DCETaken,
Lsbuf_Full =>Lsbuf_Full,
-- interface with issue unit
-- translate_off
Lsbuf_instruction =>Lsbuf_instruction,
-- translate_on
Lsbuf_Ready => IssLsb_Rdy,
Lsbuf_Data =>Lsbuf_Data,
Lsbuf_PhyAddr =>Lsbuf_PhyAddr,
Lsbuf_RobTag =>Lsbuf_RobTag,
Lsbuf_SwAddr =>Lsbuf_SwAddr,
Lsbuf_RdWrite =>Lsbuf_RdWrite,
Iss_Lsb =>Iss_Lsb
);
-----------------------------------------------------------------------------------------------
issueUnit_inst : issue_unit
generic map(
Resetb_ACTIVE_VALUE => '0'
)
port map(
Clk =>Clk,
Resetb =>Resetb,
-- ready signals from each of the queues
IssInt_Rdy =>IssInt_Rdy,
IssMul_Rdy =>IssMul_Rdy,
IssDiv_Rdy =>IssDiv_Rdy,
IssLsb_Rdy =>IssLsb_Rdy,
-- signal from the division execution unit to indicate that it is currently available
Div_ExeRdy =>Div_ExeRdy,
--issue signals as acknowledgement from issue unit to each of the queues
Iss_Int =>Iss_Int,
Iss_Mult =>Iss_Mult,
Iss_Div =>Iss_Div,
Iss_Lsb =>Iss_Lsb
);
-----------------------------------------------------------------------------------------------
cdb_inst : cdb
generic map(
Resetb_ACTIVE_VALUE => '0'
)
port map(
Clk =>Clk,
Resetb =>Resetb,
-- from ROB
Rob_TopPtr =>Rob_TopPtr,
-- from integer execution unit
Alu_RdData =>Alu_RdData,
Alu_RdPhyAddr =>Alu_RdPhyAddr,
Alu_BranchAddr =>Alu_BranchAddr,
Alu_Branch =>Alu_Branch,
Alu_BranchOutcome =>Alu_BranchOutcome,
Alu_BranchUptAddr =>Alu_BranchUptAddr,
Iss_Int =>Iss_Int,
Alu_BranchPredict =>Alu_BranchPredict,
Alu_JrFlush =>Alu_JrFlush,
Alu_RobTag =>Alu_RobTag,
Alu_RdWrite =>Alu_RdWrite,
-- translate_off
Alu_instruction =>Alu_instruction,
-- translate_on
-- from mult execution unit
Mul_RdData =>Mul_RdData,
Mul_RdPhyAddr =>Mul_RdPhyAddr,
Mul_Done =>Mul_Done,
Mul_RobTag =>Mul_RobTag,
Mul_RdWrite =>Mul_RdWrite,
-- translate_off
Mul_instruction =>Mul_instruction,
-- translate_on
-- from div execution unit
Div_Rddata =>Div_Rddata,
Div_RdPhyAddr =>Div_RdPhyAddr,
Div_Done =>Div_Done,
Div_RobTag =>Div_RobTag,
Div_RdWrite =>Div_RdWrite,
-- translate_off
Div_instruction =>Div_instruction,
-- translate_on
-- from load buffer and store word
Lsbuf_Data =>Lsbuf_Data,
Lsbuf_PhyAddr =>Lsbuf_PhyAddr,
Iss_Lsb =>Iss_Lsb,
Lsbuf_RobTag =>Lsbuf_RobTag,
Lsbuf_SwAddr =>Lsbuf_SwAddr,
Lsbuf_RdWrite =>Lsbuf_RdWrite,
-- translate_off
Lsbuf_instruction =>Lsbuf_instruction,
Cdb_instruction =>Cdb_instruction,
-- translate_on
--outputs of cdb
Cdb_Valid =>Cdb_Valid,
Cdb_PhyRegWrite =>Cdb_PhyRegWrite,
Cdb_Data =>Cdb_Data,
Cdb_RobTag =>Cdb_RobTag,
Cdb_BranchAddr =>Cdb_BranchAddr,
Cdb_BranchOutcome =>Cdb_BranchOutcome,
Cdb_BranchUpdtAddr =>Cdb_BranchUpdtAddr,
Cdb_Branch =>Cdb_Branch,
Cdb_Flush =>Cdb_Flush,
Cdb_RobDepth =>Cdb_RobDepth,
Cdb_RdPhyAddr =>Cdb_RdPhyAddr,
Cdb_SwAddr =>Cdb_SwAddr
);
-----------------------------------------------------------------------------------------------
rob_inst : rob
port map(--inputs--
Clk =>Clk,
Resetb =>Resetb,
-- Interface with CDB
Cdb_Valid =>Cdb_Valid,
Cdb_RobTag =>Cdb_RobTag,
Cdb_SwAddr =>Cdb_SwAddr,
-- Interface with Dispatch unit
Dis_InstSw =>Dis_InstSw,
Dis_RegWrite =>Dis_RegWrite,
Dis_InstValid =>Dis_InstValid,
Dis_RobRdAddr =>Dis_RobRdAddr,
Dis_NewRdPhyAddr =>Dis_NewRdPhyAddr,
Dis_PrevPhyAddr =>Dis_PrevPhyAddr,
Dis_SwRtPhyAddr =>Dis_SwRtPhyAddr,
Rob_Full =>Rob_Full,
Rob_TwoOrMoreVacant =>Rob_TwoOrMoreVacant,
--translate_off
Dis_instruction =>Dis_instruction,
--translate_on
-- Interface with store buffer
SB_Full =>SB_Full,
Rob_SwAddr =>Rob_SwAddr,
Rob_CommitMemWrite =>Rob_CommitMemWrite,
-- Takes care of flushing the address buffer
-- Interface with FRL and CFC
--translate_off
Rob_Instruction =>Rob_Instruction,
--translate_on
Rob_TopPtr =>Rob_TopPtr,
Rob_BottomPtr => Rob_BottomPtr,
Rob_Commit =>Rob_Commit,
Rob_CommitRdAddr =>Rob_CommitRdAddr,
Rob_CommitRegWrite =>Rob_CommitRegWrite,
Rob_CommitPrePhyAddr =>Rob_CommitPrePhyAddr,
Rob_CommitCurrPhyAddr =>Rob_CommitCurrPhyAddr,
Cfc_RobTag =>Cfc_RobTag,
Cdb_Flush =>Cdb_Flush
);
-----------------------------------------------------------------------------------------------
storeBuffer_inst : store_buffer
port map(
-- Global Signals
Clk => Clk,
Resetb => Resetb ,
--interface with ROB
Rob_SwAddr => Rob_SwAddr,
PhyReg_StoreData => PhyReg_StoreData,
Rob_CommitMemWrite => Rob_CommitMemWrite,
SB_Full => SB_Full,
SB_Stall => SB_Stall,
Rob_TopPtr => Rob_TopPtr,
-- interface with lsq
SB_FlushSw =>SB_FlushSw,
SB_FlushSwTag =>SB_FlushSwTag,
SBTag_counter =>SBTag_counter, --Added by Waleed 06/04/10
--interface with Data Cache Emulator
SB_DataDmem => SB_DataDmem,
SB_AddrDmem => SB_AddrDmem,
SB_DataValid => SB_DataValid,
DCE_WriteBusy => DCE_WriteBusy,
DCE_WriteDone => DCE_WriteDone
);
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
end behave ;
|
gpl-2.0
|
e00cf257353f90fc526ba5dd596587bf
| 0.561568 | 4.176017 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/write_data_fifo/simulation/fg_tb_top.vhd
| 3 | 6,021 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
c7c655e1c13a539839ec685fc730cd2a
| 0.612025 | 4.095918 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/simulation/bmg_stim_gen.vhd
| 1 | 15,576 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(256,256);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(255 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(32768,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(9 DOWNTO 0) <= WRITE_ADDR_A(9 DOWNTO 0);
READ_ADDR_INT_A(9 DOWNTO 0) <= READ_ADDR_A(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) AFTER 50 ns;
WRITE_ADDR_INT_B(14 DOWNTO 0) <= WRITE_ADDR_B(14 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr
READ_ADDR_INT_B(14 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),NOT(READ_ADDR_B(14 DOWNTO 0)),READ_ADDR_B(14 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) AFTER 50 ns;
DINA <= DINA_INT AFTER 50 ns;
DINB <= DINB_INT AFTER 50 ns;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_REG_B(0);
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024)
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 32768 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 32768 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>256,
DOUT_WIDTH => 256,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>8,
DOUT_WIDTH =>8 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') AFTER 50 ns;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') AFTER 50 ns;
END ARCHITECTURE;
|
gpl-2.0
|
ccaae08211490246b89a6caa06a4ef82
| 0.579032 | 3.20362 | false | false | false | false |
ultraembedded/altor32
|
fpga/papilio_xc3s250e/program.vhd
| 1 | 191,915 |
-------------------------------------------------------------------
-- This file was derived from the Plasma project by Steve Rhoads.
-- It has been modified to support dual port block RAM and contains
-- the FPGA Bootloader image.
--
-- Original copyright notice:
--
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic
(
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1
);
port
(
-- Port A
clka_i : in std_logic;
ena_i : in std_logic;
wea_i : in std_logic_vector(3 downto 0);
addra_i : in std_logic_vector(31 downto 2);
dataa_i : in std_logic_vector(31 downto 0);
dataa_o : out std_logic_vector(31 downto 0);
-- Port B
clkb_i : in std_logic;
enb_i : in std_logic;
web_i : in std_logic_vector(3 downto 0);
addrb_i : in std_logic_vector(31 downto 2);
datab_i : in std_logic_vector(31 downto 0);
datab_o : out std_logic_vector(31 downto 0)
);
end;
architecture logic of ram is
-----------------------------------------------
-- Signals
-----------------------------------------------
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
-- Which 8KB block
alias block_a_sel: std_logic_vector(2 downto 0) is addra_i(15 downto 13);
alias block_b_sel: std_logic_vector(2 downto 0) is addrb_i(15 downto 13);
-- Address within a 8KB block (without lower two bits)
alias block_a_addr : std_logic_vector(10 downto 0) is addra_i(12 downto 2);
alias block_b_addr : std_logic_vector(10 downto 0) is addrb_i(12 downto 2);
-- Block ena_i with 1 bit per memory block
signal block_a_enable: std_logic_vector(7 downto 0);
signal block_b_enable: std_logic_vector(7 downto 0);
-- Block Data Out
signal block_a_do: mem32_vector(7 downto 0);
signal block_b_do: mem32_vector(7 downto 0);
-- Remember which block was selected
signal block_a_sel_buf: std_logic_vector(2 downto 0);
signal block_b_sel_buf: std_logic_vector(2 downto 0);
constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
-----------------------------------------------
-- Port A
-----------------------------------------------
block_a_enable <= "00000001" when (ena_i='1') and (block_a_sel="000") else
"00000010" when (ena_i='1') and (block_a_sel="001") else
"00000100" when (ena_i='1') and (block_a_sel="010") else
"00001000" when (ena_i='1') and (block_a_sel="011") else
"00010000" when (ena_i='1') and (block_a_sel="100") else
"00100000" when (ena_i='1') and (block_a_sel="101") else
"01000000" when (ena_i='1') and (block_a_sel="110") else
"10000000" when (ena_i='1') and (block_a_sel="111") else
"00000000";
process (clka_i, block_a_sel) is
begin
if rising_edge(clka_i) then
block_a_sel_buf <= block_a_sel;
end if;
end process;
process (block_a_do, block_a_sel_buf) is
begin
dataa_o <= block_a_do(conv_integer(block_a_sel_buf));
end process;
-----------------------------------------------
-- Port B
-----------------------------------------------
block_b_enable <= "00000001" when (enb_i='1') and (block_b_sel="000") else
"00000010" when (enb_i='1') and (block_b_sel="001") else
"00000100" when (enb_i='1') and (block_b_sel="010") else
"00001000" when (enb_i='1') and (block_b_sel="011") else
"00010000" when (enb_i='1') and (block_b_sel="100") else
"00100000" when (enb_i='1') and (block_b_sel="101") else
"01000000" when (enb_i='1') and (block_b_sel="110") else
"10000000" when (enb_i='1') and (block_b_sel="111") else
"00000000";
process (clkb_i, block_b_sel) is
begin
if rising_edge(clkb_i) then
block_b_sel_buf <= block_b_sel;
end if;
end process;
process (block_b_do, block_b_sel_buf) is
begin
datab_o <= block_b_do(conv_integer(block_b_sel_buf));
end process;
-----------------------------------------------
-- BRAM
-----------------------------------------------
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00000000000000000000000000000000000000150415139ce4d4a818a818a818",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000001500",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000001500",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000001500",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000001500",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"d7d7d7d7d7d7d718009cd70048d49c84d4841815151515c09c18159cd7d71524",
INIT_0F => X"0cbc0cbc040cbc10bde084860cbc04a81804a818aaa89e18180ce404049d9ca8",
INIT_10 => X"180304a81804a8180304a81804a89e180304a8a804a89e1813bc0cbc13bc0cbc",
INIT_11 => X"a89d1807a81804a8180fbc0404a81807a818049c1804a81807a8049ca804a818",
INIT_12 => X"d7a8d718d707a81804a8180304a89e180cbc04a80304a81804a89e180cbc0304",
INIT_13 => X"a8a9a81944858484859d9cd40fdbe48c9ce0e0e0a80c84a9bd190ca89cbcd784",
INIT_14 => X"04a9a8a81818d49ca81918d4d7d7a8d718d703e04485849dd48485e09c840484",
INIT_15 => X"9c0ce49d84a8a818180418a8a89c9cd7d7d71844858484859c0fbd04d4a88418",
INIT_16 => X"18d7d744b984ad84e09ce19ce0d7a88418d7448484859d9c048418a844848485",
INIT_17 => X"9cd4a818d49ca8d7184486858484859c0fbce0840fbd488585a89caad7d7d71a",
INIT_18 => X"d49e9cabd49e9c10bc84a91910d4bc9c85d7d7d7d7d7d7d7d7d7abd71bd74484",
INIT_19 => X"10bc0cbc13bd488510bce08400860cbc10bc13bd488510bce084008648a8a818",
INIT_1A => X"ba9e9e0ce4a48dac8c0fd8e0e5a89e1813bd488510bce08400869ed89fabd41b",
INIT_1B => X"ac8c13ba9ee5ba079e009d48859c48859c48859c0713bdbaba9e03850cbd07ba",
INIT_1C => X"d89fab9f1b4487878787868686858484859c8548a8849c48859c070013e4a48d",
INIT_1D => X"a4bcac9c13a4bde0b810bc9c00e09cb88ca5e19cb88d8ca89c1810bc84039ed4",
INIT_1E => X"13e48c0fe4a4a89c18e08ca88418039e0fe4a49c8410e4840fe40fe4a89c180f",
INIT_1F => X"9cd7039d03d4a4859c9e84489e84d4a8e018849c039d48859c070307baba9e9e",
INIT_20 => X"a8d71803079c448484859c0fbca585d4a8a81815a80cbc9cd7b8d7d7b844849c",
INIT_21 => X"90079c0c9cbc90a8d7d7d74484a59c859ca8d718039d44849c85a810bca4849c",
INIT_22 => X"a80cd89cd4a818d4a818d4a818d4bd9cd7d7d7d7d7a8d718d7448484859c0fbc",
INIT_23 => X"9c909d0cd8e49c9cd89e9c10bc0fa8bc04d88da8e19c9c049e9ca8a900a99e9e",
INIT_24 => X"44849c0fe5e084849ca8d71844849c9cd7039ee044868686858484859c0fe407",
INIT_25 => X"a80fbca41884d4a4a8a8b80fbca41884d4a4a8a8b80fbca41884a8d49ca8d718",
INIT_26 => X"a484d4a9a8a89d180fbca484d49cd49ca8d79ca8d71844849c0fbca484d4a8a4",
INIT_27 => X"84d4a89c180fbca484d49cd49ca8d79ca8d7184484849cd4a59c0fe4859c0fbc",
INIT_28 => X"bca4d4840fbca484d40fbca484d4d49c9da8a9a89d184484849c10e418e08418",
INIT_29 => X"180fbca484d4a89ca80fbca41884d49c9ca8d4d7d7d7d7a89c18d74484849c0f",
INIT_2A => X"448685848485a99c0c9cbc10aabc0cbc0cd4a8bc1807aaa807a807d484a8a89d",
INIT_2B => X"1884d4d4a8a8071813bcd485e0a8b818e09ee00fbc44868584a98485aa9c10bc",
INIT_2C => X"d7d7d7d7d7d7d7d7d7d703a8448685848485a99cd49e0fbca484d4a8a80fbca4",
INIT_2D => X"e0a8bd079cd4a89cabaa10e4ab84e284aaa8d49e84a9a818180cababab9cbdd7",
INIT_2E => X"87878787868686858484859d9c13e3e3d4e59ce20fdbe4849c0fbca484d40c9c",
INIT_2F => X"a484d4d49c9da8a99dd4a8a89c078c84a818d4a89ca807aa199cd7d7d7d7d744",
INIT_30 => X"d7d7d7d7d7d784d7d7a8d718d74486858484859c0fbca5d4850fbca484d40fbc",
INIT_31 => X"bc9c07d4a89c9c07ab10e486e384a9a89e180c9fbd0cbce0ab9caa84d4ab9cd7",
INIT_32 => X"840fbca484d40fbca484d4d49c9ca8d4a8189c0fa8e49c0fbca484d48ce00ca8",
INIT_33 => X"9c9cd7d7d7030703aa4487878787868686858484859d9c0fe2e5e3e30fbca4d4",
INIT_34 => X"0fbca484d40fbca484d4d49c9da8a99dd4a8a89c180fbca484d4d4a8a89c1807",
INIT_35 => X"109ce4d74484859c049c9cd7d74484859c049c9cd7d7448484859c0fbca5d485",
INIT_36 => X"bc0fbcb8b8e1e010e49d0ca9bc0fbca49c10e19ce4e1e0e010bd0cbd00109cbd",
INIT_37 => X"64616e6b0a740a0020000000bf00200000001f00d800000020039c44849ca910",
INIT_38 => X"63207073002e626e782e6f294261740a504d2000704d20006e78456c65200063",
INIT_39 => X"000000000052696261656961002e414f6d20422e6129464f0a6866704d002e69",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(0)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00000000000000000000000000000000000000000000ff84a404a5a084802480",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"e1e1e1e1e1e1e1600021e10000018481018480000000000480a00021e1e10000",
INIT_0F => X"002b002b00001400a4848242002e006360006360c342806040002b0000c02163",
INIT_10 => X"60ff006360006360ff00946000638060ff00946e00638060ff2b002bff2e002b",
INIT_11 => X"63c060ff6360006360ff0b00006360ff6360008060006360ff62008062006340",
INIT_12 => X"e142e140e1ff6360006360ff00638060000b0076ff00636000638060002eff00",
INIT_13 => X"a2ce83c000c1412121602108ffe606a5c6a363e4c700e808440000442105e1a2",
INIT_14 => X"00ce84638060032163c06002e1e142e140e1ffe400c141600e212142216e006e",
INIT_15 => X"21002660c563a560a00060844321a0e1e1e18000c141212121ff6b000e638260",
INIT_16 => X"40e1e1006b4163216b21602163e1426340e100412121602100a5608200412121",
INIT_17 => X"210363600521a5e1a00041c141212121ff436362ff8b0072c2422152e1e1e140",
INIT_18 => X"0140408201c04000024ecec000010b217ae1e1e1e1e1e1e1e1e15ae140e10021",
INIT_19 => X"0012002bff8b006e004363620082000b000bff8b006e00436362008200724240",
INIT_1A => X"d640d60023631e637eff037454849480ff8b006e004363620042801e1cde01c0",
INIT_1B => X"637effd64078d6ffd60060007a60007a60007a60ffff56d6d6d6ff7a0056ffd6",
INIT_1C => X"1e00de80c000c1814101c18141c1412121216100834160007a60ff00ff23631e",
INIT_1D => X"63046684ff6665c3a3000484006580a5a76b6be5846585a560a0000361ff8001",
INIT_1E => X"ff037eff0384a563a084a3638160ff40ff086365a10005a1ff0bff0784e780ff",
INIT_1F => X"21e1ff60ff01637a64408100c0a10163a560a180ff60007a60ffffffd6d640d6",
INIT_20 => X"83e160ffff600041212121ff0b6b63046383600062002221e143e1e163002121",
INIT_21 => X"62ff420021236343e1e1e100216b21632163e160ff6000212163630004848421",
INIT_22 => X"43000140014240014240014240016321e1e1e1e1e142e140e10041212121ff03",
INIT_23 => X"4262d400126260520e4e400016ff4b0b000e6b62638061004e8062d200d481c0",
INIT_24 => X"002121ffa38485c521a5e1a000212121e1ffc04000c18141c141212121ff02ff",
INIT_25 => X"65ff0363a06603a7c565e4ff0363a06603a7c565e4ff0363a066c60521a6e1c0",
INIT_26 => X"84850707a5e580a0ff06c6c4052104c0a5e14085e1a0002121ff03636503a584",
INIT_27 => X"840384e080ff048483042103a084e14064e18000412121056b60ff8368c6ff04",
INIT_28 => X"24840b85ff04848305ff04848306034000a663c680c000412121000440848440",
INIT_29 => X"a0ff02424402846044ff024280430221804203e1e1e1e1628040e100412121ff",
INIT_2A => X"0041c1412121722100402b00423200320003633260ff4b6eff62ff04a56ea5c0",
INIT_2B => X"604402044282ff40ff2e03c242844280444082ff0b0041c1417221214221000b",
INIT_2C => X"e1e1e1e1e1e1e1e1e1e1ff4e0041c141212172210340ff024243046383ff0242",
INIT_2D => X"d49854ff60029ca0438300b454649e814e4201c063c2634060000483c52145e1",
INIT_2E => X"c1814101c18141c14121216021ff189c025e60d6ffe4047284ff0363620e00a0",
INIT_2F => X"848306034000a682a00262cee0ff636363600292604eff43c021e1e1e1e1e100",
INIT_30 => X"e1e1e1e1e1e142e1e142e140e10041c141212121ff0b6b0c65ff04848305ff04",
INIT_31 => X"3280ff029c60a0ff5200ba445e81c343c06000005e002243c5428442018321e1",
INIT_32 => X"64ff03636204ff0363620e0260c08302e260a0ff640484ff0363620e63740064",
INIT_33 => X"4021e1e1e1ffffff5a00c1814101c18141c14121216021ff94be9c18ff036307",
INIT_34 => X"ff04848305ff04848306034000a684a00464c6e0c0ff03636403046383a060ff",
INIT_35 => X"002164e1002121210021a0e1e1002121210021a0e1e10041212121ff0b6b0c65",
INIT_36 => X"05ff0684c66b63008360006626ff07e7e00008e0430084c6008400880000c064",
INIT_37 => X"6573206e005242000000000025000000000044000001000020ffc00021216300",
INIT_38 => X"6f746173502e6f61740a7420526c65004720503c7020503c61743e0a72493c65",
INIT_39 => X"00000000004f6e6c69206d704e2e704d20666f2e7320504d002e6c7020502e6e",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(0)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00000000000000000000000000000000000000000100ff0028001f101c101f10",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000001",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000008",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000008",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"b7a797170f774f1000ff0f00182000002000100000000028000000ff0f4f0000",
INIT_0F => X"0000000002000000279000000000021c10021c1020010010120070030200ff1b",
INIT_10 => X"10ff021c10021c10ff000000021c0010ff000000021c0010ff000000ff000000",
INIT_11 => X"1b0010ff0111011c10ff0001021c10ff0111000011021c10ff21000020021c10",
INIT_12 => X"0f1c4f1017ff2110011c10ff011c001000000000ff011c10011c00100000ff01",
INIT_13 => X"001c001048ffffffff000038ff2f3800003030380000001c00100000ff007700",
INIT_14 => X"001c1010101020ff1c1010180f4f1c771017ff3848ffff0010ffff1800000300",
INIT_15 => X"0000180000101cb01002001c00ff000f4f171048ffffffff00ff000020090010",
INIT_16 => X"1297174800ffffff180018ff100f1000b01748ffffff00000200000048ffffff",
INIT_17 => X"00201d1018ff1d0f1048ffffffffff00ff037000ff0058000001ff1d770f4f10",
INIT_18 => X"100000001000000000001d10001800ff00f7e7c7b7a79777170f1d4f10d748ff",
INIT_19 => X"00000000ff0058000003a000000000000000ff0058000003a000000058000112",
INIT_1A => X"0000ff004000000000ff5820c01d0010ff0058000003900000000058001de010",
INIT_1B => X"0000ff0000a000ffff00ff580000580000580000ffff000000ffff000000ff00",
INIT_1C => X"58001d001048ffffffffffffffffffffff000010000000580000ff00ff400000",
INIT_1D => X"ff0010ffffff0018000000ff0018000000ff20000000001d0010000000ff00e0",
INIT_1E => X"ff2000ff28001d001028001d0010ff00ff1800ff00004000ff18ff201d0010ff",
INIT_1F => X"ff0fffffff180000000000280000281d20100000ffff580000fefffe000000ff",
INIT_20 => X"000f12ffff0048ffffff00ff0000001000001200000000ff0f004f170048ff00",
INIT_21 => X"00ff0000ff0000000f4f1748ff000000ff000f12ffff48ff00000000000000ff",
INIT_22 => X"000010001045431041381036341000ffb7a797770f324f301748ffffff00ff00",
INIT_23 => X"ff00ff0018a000ff1000000000ff000002580000580000020000000000000000",
INIT_24 => X"48ff00ff20300000ff010f1248ff00ff0fff001848ffffffffffffff00ff70ff",
INIT_25 => X"03ff000012002800030300ff000012002800030300ff000012000318ff030f12",
INIT_26 => X"0000600003030012ff00000030ff1000030f0003171248ff00ff000000200300",
INIT_27 => X"00381d0010ff00000028ff1000030f0003171248ffff00180000ff300000ff00",
INIT_28 => X"00003800ff00000040ff00000060100000000003001248ffff000010201000ff",
INIT_29 => X"12ff00000018030003ff0000120020ff00032097770f4f0300121748ffff00ff",
INIT_2A => X"48ffffffffff0000000000000000000000101d0010ff0000ff00ff7000000300",
INIT_2B => X"120090700303ff12ff001000201b0010100010ff0048ffffff00ffff00000000",
INIT_2C => X"b7a79777170f4ff7e7c7ff0048ffffffffff00009000ff000000100303ff0000",
INIT_2D => X"c00000fe00280000000000180000b0000003180000031d121000000000ff00d7",
INIT_2E => X"ffffffffffffffffffffff0000ffd0d018b000a0ff1f300000ff000000280000",
INIT_2F => X"00006810000000000038000300fe00001d1018000003ff0012ff0f9777174f48",
INIT_30 => X"c7b797770f4f00f7e71da7101748ffffffffff00ff00003800ff00000040ff00",
INIT_31 => X"0000fe28000000fe00009000c0000303001200000000001000ff00001000ffd7",
INIT_32 => X"00ff00000030ff000000b01800000328001200ff009000ff0000001800180000",
INIT_33 => X"00ff0f4f17ffffff0048ffffffffffffffffffffff0000ff90c090d0ff000028",
INIT_34 => X"ff00000040ff000000681000000000003800030012ff000000281003030012fe",
INIT_35 => X"00ff180f48ffff0000ff000f4f48ffff0000ff000f4f48ffffff00ff00003800",
INIT_36 => X"00ff0000003020002000000000ff000000003000203020300000000000000000",
INIT_37 => X"7668666f554f6f000010010000000010010100000000010100ff0048ff000000",
INIT_38 => X"6e6f6320722e6f6c65002e624120724941285246292852416c6520006e6e4921",
INIT_39 => X"00000000004d20656c6161706f2e702050726f0a68664720502e612928522e75",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(0)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00000000000000000000000000000000000000008d00fd040000a000f0009000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000040",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000040",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"f8f4f0e8e4ecfc0000fcfc00000001000000000000000000110600f4f8fc0000",
INIT_0F => X"29452249224801030f020000250044130047050000000000005700415200e4e4",
INIT_10 => X"00d61831001b2100de78000622890100e68000002a9e0100ee460b41f2003058",
INIT_11 => X"ee0100860000fc5b00fe20e9026d009200006100000b5b009b00690000134200",
INIT_12 => X"f0f0fc00f4680000deb40098e2cd010006006000a9eb1300ee0501000900a6f5",
INIT_13 => X"00f8000000f8f4f0fc001000fbff000001000200002200f800001700f000f800",
INIT_14 => X"58f8740c000000f0f0000000f0fcf4f800f4e70000f8f40000f0fc0010009200",
INIT_15 => X"0c06000008adfc0700e006fc00f410f4fcf80000f8f4f0fc10fa005e006c0000",
INIT_16 => X"00f8f0005ffcfff8040802f805f8ae0807fc00f8f4fc010ccf0c060000f8f4fc",
INIT_17 => X"0400940000fc98fc0000f8f4f0ecfc14f9e70200fc0000000000ec94f4ecfc00",
INIT_18 => X"0c430100001000e400009400e90800c400f8f4ece8e4e0dcd8d498fc00f000fc",
INIT_19 => X"5c43a918f900000007e7020005000d185604f90000003de70200050000000000",
INIT_1A => X"1815ff4700ff01ff02f00000000c0100f90000002ce7020005000000820c0400",
INIT_1B => X"ff02ec9815001865ff18ff00001800001800001872fa009818ffbd0008007c98",
INIT_1C => X"00830c010000f8f4f0ece8e4e0dcd8d4fc3c0000000800000006581fda00ff01",
INIT_1D => X"ff0021fff9ff0000100b00ff0405080800ff00030884830c00002d0004a40004",
INIT_1E => X"e90083f900ff8f010000000f040098069c00ffff0c22000c9600ea008f0100f7",
INIT_1F => X"fcfc91ff270cff0001060c001008000f00000080a3ff000006f77df9981815ff",
INIT_20 => X"04fc00efe80d00f8f4fc0cfd000800000408000400100af4f498fcf81800fc04",
INIT_21 => X"00c50106f4000000f4fcf800fc010400fc04fc00fcff00fc04000806000100fc",
INIT_22 => X"002e10000c46440842390437350000b0f8f4f0ece433fc31e800f8f4fc0cfc00",
INIT_23 => X"ff00ff07000000ff01022d0400f200003b000000000a004b010a000002001400",
INIT_24 => X"00fc04fd00020000fc00fc0000fc04fcfcd3010200f8f4f0ece8e4fc50fc0083",
INIT_25 => X"04fc0001000000ff000448fc0001000000ff000450fc000100000000fc04fc00",
INIT_26 => X"010000000004ff00fd00010000f8009f04f80000fc0000fc04fd0001000000ff",
INIT_27 => X"00009c0100fd00010000f8000604f80000fc0000fcf80800ff01f8000001fd00",
INIT_28 => X"00020000fd00010000fd000100000000ff000004050000fcf8080500200300ff",
INIT_29 => X"00fd0001000000ff04fc0001000000ec050400f8f4ecfc000000f000fcf808f0",
INIT_2A => X"00f8f4f0ecfc00141602250400bf0f1f1c009c20008000008300850000000401",
INIT_2B => X"0000000004007400e1000014009c0300000100f62000f8f4f000ecfc00143344",
INIT_2C => X"e8e4e0dcd8d4fcf8f4ecd80000f8f4f0ecfc00140001fd000100000004fc0001",
INIT_2D => X"000000e40300000000000300000802000000000000049c00002d000000d000f0",
INIT_2E => X"f8f4f0ece8e4e0dcd8d4fc0030de000000000100f7ff000001fd000100000bff",
INIT_2F => X"0100000000ff00000500000401ae10009c0000000000040000ececf8f4f0fc00",
INIT_30 => X"ece8e0dcd4fc00f8f49ce400d800f8f4f0ecfc14f000010000fd00010000fd00",
INIT_31 => X"00006300000200b5004100040200040005003c00004f000300ff000c0000d0f0",
INIT_32 => X"00fd00010000fd000100000000ff0400000001f6000001fd0001000000000c00",
INIT_33 => X"00f4f4fcf8b168c00000f8f4f0ece8e4e0dcd8d4fc0030ca00000000f0000100",
INIT_34 => X"fd00010000fd000100000000ff0000050000040100fd0001000000040060006d",
INIT_35 => X"26fc00fc00f8fc0805f801f8fc00f8fc080ef800f8fc00f8f4fc0cf000010000",
INIT_36 => X"00f900414104020300000a0000f200ff00020401000200000f000e0013060100",
INIT_37 => X"69206c776e4d6f000000000100000000000000010000000000f00100fc040002",
INIT_38 => X"74206573650a742072452e6f4d286e6e29464f3e0a414f3e0a72453c61743e0a",
INIT_39 => X"00000000000a502061766720200a2928526f74002e6c4128522e7320414f0a65",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(0)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(1)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(1)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(1)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(1)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(2)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(2)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(2)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(2)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(3)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(3)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(3)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(3)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(4)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(4)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(4)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(4)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(5)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(5)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(5)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(5)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(6)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(6)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(6)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(6)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(7)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(7)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(7)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(7)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block7
end; --architecture logic
|
lgpl-3.0
|
ddf5c3d9f789cc3b7833b133cb82cfd3
| 0.819597 | 5.610565 | false | false | false | false |
tuura/fantasi
|
dependencies/Altera_DE4/TOP.vhd
| 1 | 7,214 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY TOP IS
GENERIC (
RESULT_WIDTH : integer := 9;
NODES : integer := 15;
ADDR_SHIFT : integer := 4);
PORT (
--//////////// CLOCK //////////
GCLKIN : IN std_logic;
GCLKOUT_FPGA : OUT std_logic;
OSC_50_BANK2 : IN std_logic;
OSC_50_BANK3 : IN std_logic;
OSC_50_BANK4 : IN std_logic;
OSC_50_BANK5 : IN std_logic;
OSC_50_BANK6 : IN std_logic;
OSC_50_BANK7 : IN std_logic;
PLL_CLKIN_p : IN std_logic;
--//////////// LED x 8 //////////
LED : OUT std_logic_vector(7 downto 0);
--//////////// BUTTON x 4, EXT_IO and CPU_RESET_n //////////
BUTTON : IN std_logic_vector(3 downto 0);
CPU_RESET_n : IN std_logic;
EXT_IO : IN std_logic;
--//////////// SLIDE SWITCH x 4 //////////
SLIDE_SW : IN std_logic_vector(3 downto 0);
--//////////// SEG7 //////////
SEG0_D : OUT std_logic_vector(7 downto 0);
SEG0_DP : OUT std_logic;
SEG1_D : OUT std_logic_vector(7 downto 0);
SEG1_DP : OUT std_logic;
--//////////// Temperature //////////
TEMP_INT_n : IN std_logic;
TEMP_SMCLK : OUT std_logic;
TEMP_SMDAT : IN std_logic;
--//////////// Current //////////
CSENSE_ADC_FO : OUT std_logic;
CSENSE_CS_n : OUT std_logic_vector(1 downto 0);
CSENSE_SCK : OUT std_logic;
CSENSE_SDI : OUT std_logic;
CSENSE_SDO : IN std_logic;
--//////////// Fan //////////
FAN_CTRL : OUT std_logic;
--//////////// Flash and SRAM Address/Data Share Bus //////////
FSM_A : OUT std_logic_vector(20 downto 1);
FSM_D : INOUT std_logic_vector(15 downto 0);
--//////////// SSRAM Control //////////
SSRAM_ADV : OUT std_logic;
SSRAM_BWA_n : OUT std_logic;
SSRAM_BWB_n : OUT std_logic;
SSRAM_CE_n : OUT std_logic;
SSRAM_CKE_n : OUT std_logic;
SSRAM_CLK : OUT std_logic;
SSRAM_OE_n : OUT std_logic;
SSRAM_WE_n : OUT std_logic;
--//////////// 3-Ports High-Speed USB OTG //////////
OTG_A : OUT std_logic_vector(17 downto 1);
OTG_CS_n : OUT std_logic;
OTG_D : INOUT std_logic_vector(31 downto 0);
OTG_DC_DACK : OUT std_logic;
OTG_DC_DREQ : IN std_logic;
OTG_DC_IRQ : IN std_logic;
OTG_HC_DACK : OUT std_logic;
OTG_HC_DREQ : IN std_logic;
OTG_HC_IRQ : IN std_logic;
OTG_OE_n : OUT std_logic;
OTG_RESET_n : OUT std_logic;
OTG_WE_n : OUT std_logic);
END TOP;
ARCHITECTURE Behavioural OF TOP IS
COMPONENT system1 IS
PORT (
clk_clk : IN std_logic;
reset_reset_n : IN std_logic;
input0_extern_con_export : IN std_logic_vector(31 downto 0);
input1_extern_con_export : IN std_logic_vector(31 downto 0);
input2_extern_con_export : IN std_logic_vector(31 downto 0);
input3_extern_con_export : IN std_logic_vector(31 downto 0);
output0_extern_con_export : OUT std_logic_vector(31 downto 0);
output1_extern_con_export : OUT std_logic_vector(31 downto 0);
output2_extern_con_export : OUT std_logic_vector(31 downto 0);
output3_extern_con_export : OUT std_logic_vector(31 downto 0));
END COMPONENT;
COMPONENT pll_100mhz IS
PORT (
inclk0 : IN std_logic;
c0 : OUT std_logic);
END COMPONENT;
-- FANTASI
COMPONENT FSM IS
GENERIC (DATA_WIDTH : integer;
NODES : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
GO : IN std_logic;
COMPL : OUT std_logic;
EN_NODES : in std_logic_vector(NODES-1 downto 0);
RESULT : OUT std_logic_vector(DATA_WIDTH downto 0));
END COMPONENT;
COMPONENT FSM_ENABLE_NODES IS
GENERIC (NODES : integer;
ADDR : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
M_SET : IN std_logic;
ZERO : IN std_logic;
ONE : IN std_logic;
DIN : IN std_logic_vector(ADDR-1 downto 0);
SH_DONE: OUT std_logic;
DOUT : OUT std_logic_vector(NODES-1 downto 0));
END COMPONENT;
component rgen1 is
port (
clock : in std_logic := 'X'; -- clk
resetn : in std_logic := 'X'; -- reset_n
rand_num_data : out std_logic_vector(31 downto 0); -- data
rand_num_ready : in std_logic := 'X'; -- ready
rand_num_valid : out std_logic; -- valid
start : in std_logic := 'X' -- enable
);
end component rgen1;
signal clk : std_logic;
signal reset, reset_n : std_logic;
-- Nios
signal in_port_to_the_input0 : std_logic_vector(31 downto 0);
signal in_port_to_the_input1 : std_logic_vector(31 downto 0);
signal in_port_to_the_input2 : std_logic_vector(31 downto 0);
signal in_port_to_the_input3 : std_logic_vector(31 downto 0);
signal out_port_from_the_output0 : std_logic_vector(31 downto 0);
signal out_port_from_the_output1 : std_logic_vector(31 downto 0);
signal out_port_from_the_output2 : std_logic_vector(31 downto 0);
signal out_port_from_the_output3 : std_logic_vector(31 downto 0);
-- Wires for FSMs connection
signal enables : std_logic_vector(NODES-1 downto 0);
signal en_tmp : std_logic_vector(NODES-1 downto 0);
BEGIN
-- SRAM
SSRAM_BWA_n <= '0'; -- sync byte lane A write input = 1
SSRAM_BWB_n <= '0'; -- sync byte lane B write input = 1
SSRAM_WE_n <= '1'; -- write ena = ?
SSRAM_CE_n <= '0'; -- synchronous chip ena = 1
SSRAM_ADV <= '1'; -- address valid = 1
SSRAM_CKE_n <= '0'; -- clock ena = 1
SSRAM_CLK <= '0'; -- dont care
SSRAM_OE_n <= '1'; -- output ena = 1
FAN_CTRL <= '1';
process (clk)
begin
if (clk'event and clk='1') then
reset_n <= CPU_RESET_n;
reset <= NOT(CPU_RESET_n);
end if;
end process;
process(clk,reset)
begin
if(reset = '1') then --change in reset get immediately reflected on signal 'o'.
LED <= (others => '0');
in_port_to_the_input0 <= (others => '0');
elsif(rising_edge(clk)) then
LED <= out_port_from_the_output0(7 downto 0);
in_port_to_the_input0(3 downto 0) <= SLIDE_SW;
end if;
end process;
NIOS : system1
PORT MAP(
clk_clk => clk,
reset_reset_n => reset_n,
input0_extern_con_export => in_port_to_the_input0,
input1_extern_con_export => in_port_to_the_input1,
input2_extern_con_export => in_port_to_the_input2,
input3_extern_con_export => in_port_to_the_input3,
output0_extern_con_export => out_port_from_the_output0,
output1_extern_con_export => out_port_from_the_output1,
output2_extern_con_export => out_port_from_the_output2,
output3_extern_con_export => out_port_from_the_output3);
PLL : pll_100mhz PORT MAP(OSC_50_BANK2, clk);
FANTASI_TEST : FSM
GENERIC MAP(RESULT_WIDTH, NODES)
PORT MAP(
CLK => clk,
RST => out_port_from_the_output1(0),
GO => out_port_from_the_output1(1),
EN_NODES => enables,
COMPL => in_port_to_the_input2(0),
RESULT => in_port_to_the_input1(RESULT_WIDTH downto 0));
ENABLE_NODES_CONTROL : FSM_ENABLE_NODES
GENERIC MAP(NODES, ADDR_SHIFT)
PORT MAP(
CLK => clk,
RST => out_port_from_the_output1(0),
EN => '1',
M_SET => out_port_from_the_output1(2),
ZERO => out_port_from_the_output1(3),
ONE => out_port_from_the_output1(4),
SH_DONE => in_port_to_the_input2(1),
DIN => out_port_from_the_output2(ADDR_SHIFT-1 downto 0),
DOUT => enables);
END Behavioural;
|
mit
|
5a967dbfe79f8eb04a0494d1cde5f6f3
| 0.603826 | 2.720211 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_3/complete/issueque.vhd
| 1 | 52,631 |
-------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre,Prasanjeet Das
-- Company : University of Southern California
-- Updated : 03/15/2010, 07/13/2010
-- TASK : Complete the seven TODO sections
-------------------------------------------------------------------------------
--
-- File : issueque.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The issue queue stores instructions and dispatches instructions
-- to the issue block as and when they are ready to be executed
-- Higher priority is given to instructions which has been in the
-- queue for the longest time
-- This is the code for the integer issue queue, the codes for
-- Multiplier queue and divider queue are provided separately
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity issueque is
port (
-- Global Clk and dispatch Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Output of LsBuffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
Iss_Lsb : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Dis_Immediate : in std_logic_vector ( 15 downto 0 );
Dis_Branch : in std_logic;
Dis_BranchPredict : in std_logic;
Dis_BranchOtherAddr : in std_logic_vector ( 31 downto 0 );
Dis_BranchPCBits : in std_logic_vector ( 2 downto 0 ) ;
Issque_IntQueueFull : out std_logic ;
Issque_IntQueueTwoOrMoreVacant : out std_logic;
Dis_Jr31Inst : in std_logic;
Dis_JalInst : in std_logic;
Dis_JrRsInst : in std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy : out std_logic ;
Iss_Int : in std_logic ;
-- Interface with the Multiply execution unit
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrAlu : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit (ALU)
Iss_RdPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RobTagAlu : out std_logic_vector(4 downto 0);
Iss_OpcodeAlu : out std_logic_vector(2 downto 0) ; --add branch information
Iss_BranchAddrAlu : out std_logic_vector(31 downto 0);
Iss_BranchAlu : out std_logic;
Iss_RegWriteAlu : out std_logic;
Iss_BranchUptAddrAlu : out std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : out std_logic;
Iss_JalInstAlu : out std_logic;
Iss_JrInstAlu : out std_logic;
Iss_JrRsInstAlu : out std_logic;
Iss_ImmediateAlu : out std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end issueque;
-- Architecture
architecture behav of issueque is
-- Type declarations
-- Declarations of Register Array for the Issue Queue and Issue Priority Register
type array_8_5 is array (0 to 7) of std_logic_vector(4 downto 0) ; --TAG
type array_8_6 is array (0 to 7) of std_logic_vector(5 downto 0) ; --REG
type array_8_3 is array (0 to 7) of std_logic_vector(2 downto 0) ; --OPCODE
type array_8_32 is array(0 to 7) of std_logic_vector(31 downto 0) ; --BRANCHADDR
type array_8_16 is array(0 to 7) of std_logic_vector(15 downto 0) ; --IMMEDIATEADDR
type array_8_1 is array(0 to 7) of std_logic; --BRANCHPredict
-- Signals declarations.
signal Flush : std_logic_vector(7 downto 0);
signal En : std_logic_vector(7 downto 0);
signal OutSelect : std_logic_vector(2 downto 0);
signal OutSelecttemp : std_logic_vector(7 downto 0);
signal OutSelectEmpty : std_logic_vector(7 downto 0);
signal OutSelectJRrstemp : std_logic_vector(7 downto 0);
signal OutSelectJRrs : std_logic_vector(2 downto 0);
signal OutSelect_result : std_logic_vector(2 downto 0);
signal RtReadyTemp : std_logic_vector(7 downto 0);
signal RsReadyTemp : std_logic_vector(7 downto 0);
signal IssuedRdPhyAddr : std_logic_vector(5 downto 0);
SIGNAL IssuequeBranchPredict : array_8_1;
SIGNAL IssuequeJR : array_8_1;
SIGNAL IssuequeJRrs : array_8_1;
SIGNAL IssuequeJAL : array_8_1;
SIGNAL IssuequeBranch : array_8_1;
SIGNAL IssuequeRegWrite : array_8_1;
SIGNAL IssuequeBranchAddr : array_8_32;
-- translate_off
SIGNAL Issuequeinstruction : array_8_32;
-- translate_on
SIGNAL IssuequeBranchPCBits : array_8_3;
SIGNAL IssuequeRsPhyAddrReg : array_8_6;
SIGNAL IssuequeRtPhyAddrReg : array_8_6;
SIGNAL IssuequeRdPhyAddrReg : array_8_6;
SIGNAL IssuequeOpcodeReg : array_8_3;
SIGNAL IssuequeRobTag : array_8_5;
SIGNAL IssuequeImmediate : array_8_16;
SIGNAL IssuequeRtReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeRsReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeInstrValReg : std_logic_vector (7 DOWNTO 0);
SIGNAL Entemp : std_logic_vector (7 DOWNTO 0);
SIGNAL EnJRrstemp : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeReadyTemp , IssuequefullTemp_Upper, IssuequefullTemp_Lower, UpperHalf_Has_Two_or_More_vacant, LowerHalf_Has_Two_or_More_vacant : std_logic ;
SIGNAL Buffer0Depth , Buffer1Depth ,Buffer2Depth ,Buffer3Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL Buffer4Depth , Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL IssuedRegWrite : std_logic;
begin
----------------------Generating Issuque ready -------------------------------------
---DisJAL only Instruction valid.
--###############################################################################################
-- TODO 1: Generate the IssuequeReadyTemp signal which is asserted when
--################################################################################################
-- For anyone of the 8 entries in the issue queue
-- NOTE: where [i] is from 0 to 7
-- The instruction [i] is valid and
-- instruction [i] is JAL or (JR with Rs register ready) or (JRrs with Rs register ready) or other int type instructions with both Rs register and Rt register ready
IssuequeReadyTemp <= OutSelecttemp(0) or OutSelecttemp(1) or OutSelecttemp (2) or OutSelecttemp(3) or
OutSelecttemp(4) or OutSelecttemp(5) or OutSelecttemp (6) or OutSelecttemp(7);
IssInt_Rdy <= IssuequeReadyTemp ;
---------- ----------Done Generating issuque Ready --------------------------------
--##################################################################################################
--------------------- Generating Full Condition-------------------------------------
--**********************************************************************************
-- This process generates the issueque full signal :
-- If you are issuing an instruction then the issueque is not full otherwise
-- issueque is full if all the eight entries are valid
--***********************************************************************************
--###############################################################################################
-- TODO 2: Generate the Full control signal
--################################################################################################
process ( IssuequeInstrValReg ,Iss_Int ) --ISSUEBLKDONE FROM ISSUE UNIT telling you that a instruction is issued
begin
if ( Iss_Int = '1' ) then
IssuequefullTemp_Upper <= '0' ; --Fill in the initial values of these two signals.
IssuequefullTemp_Lower <= IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
else
IssuequefullTemp_Upper <=IssuequeInstrValReg(7) and IssuequeInstrValReg(6) and
IssuequeInstrValReg(5) and IssuequeInstrValReg(4);
IssuequefullTemp_Lower <=IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
end if ;
end process ;
Issque_IntQueueFull <= IssuequefullTemp_Upper and IssuequefullTemp_Lower; --Complete the right hand side of the expression
--##################################################################################################
--------------- Nearly Full Signal ------------------------------
--**********************************************************************************
-- This process generates the issueque Nearly full signal :
-- The nearly full signal is generated for the first stage of dispatch unit for the following case
-- where both the stages have instructions to be issued in the same queue.
-- 1. Only one slot vacant in issueque: The instruction in first stage cannot be issued by dispatch.
-- 2. Two or more slots vacant in issueque: The instruction in first stage of dispatch finds a slot in issueque.
--***********************************************************************************
--###############################################################################################
-- TODO 3: Generate the Nearly Full control signal
--################################################################################################
UpperHalf_Has_Two_or_More_vacant <=(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(6))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(5)) and not(IssuequeInstrValReg(4))) ;
LowerHalf_Has_Two_or_More_vacant <= (not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(2))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(1)) and not(IssuequeInstrValReg(0))) ;
Issque_IntQueueTwoOrMoreVacant <= UpperHalf_Has_Two_or_More_vacant or LowerHalf_Has_Two_or_More_vacant or
(not (IssuequefullTemp_Upper) and not (IssuequefullTemp_Lower)) ;
-- NOTE : Two or more vacant only if
-- (a) UpperHalf Has Two or More vacant
-- (b) LowerHalf Has Two or More vacant
-- (c) Identify the third case when you need to deal with both the halfs simultaneoulsy
-- i.e) atleast one slot vacant in lower half and atleast one slot vacant in upper half
------------------ Done Generating Full and Nearly Full Condition -------------------------------
--##################################################################################################
------------------- Generating OutSelect and En-----------------------------------------
-- issue the instruction if instruction and data are valid
OUT_SELECT:
for I in 0 to 7 generate
OutSelecttemp(I) <= (IssuequeInstrValReg(I) and (IssuequeJAL(I) or(IssuequeRsReadyReg(I) and (IssuequeRtReadyReg(I) or IssuequeJR(I) or IssuequeJRrs(I))))) ; -- this has the priority in being issued
OutSelectJRrstemp(I) <= (IssuequeInstrValReg(I) and IssuequeRsReadyReg(I) and IssuequeJRrs(I)) ;
end generate OUT_SELECT;
--***************************************************************************************
-- This process generates the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelecttemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelecttemp(0) = '1' ) then
OutSelect <= "000";
else
if ( OutSelecttemp(1) = '1' ) then
OutSelect <= "001";
else
if ( OutSelecttemp(2) = '1') then
OutSelect <= "010";
else
if ( OutSelecttemp(3) = '1') then
OutSelect <= "011";
else
if ( OutSelecttemp(4) = '1') then
OutSelect <= "100";
else
if ( OutSelecttemp(5) = '1') then
OutSelect <= "101";
else
if ( OutSelecttemp(6) = '1') then
OutSelect <= "110";
else
OutSelect <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
--***************************************************************************************
-- This process generates to give priority to JRrs instruction in the issue queue.
-- the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelectJRrstemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelectJRrstemp(0) = '1' ) then
OutSelectJRrs <= "000";
else
if ( OutSelectJRrstemp(1) = '1' ) then
OutSelectJRrs <= "001";
else
if ( OutSelectJRrstemp(2) = '1') then
OutSelectJRrs <= "010";
else
if ( OutSelectJRrstemp(3) = '1') then
OutSelectJRrs <= "011";
else
if ( OutSelectJRrstemp(4) = '1') then
OutSelectJRrs <= "100";
else
if ( OutSelectJRrstemp(5) = '1') then
OutSelectJRrs <= "101";
else
if ( OutSelectJRrstemp(6) = '1') then
OutSelectJRrs <= "110";
else
OutSelectJRrs <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
process ( OutSelect , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelect) is
when "000" => Entemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => Entemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
Entemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
Entemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
Entemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
Entemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
Entemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
process ( OutSelectJRrs , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelectJRrs) is
when "000" => EnJRrstemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => EnJRrstemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => EnJRrstemp <= "11111100" ;
when "011" => EnJRrstemp <= "11111000" ;
when "100" => EnJRrstemp <= "11110000" ;
when "101" => EnJRrstemp <= "11100000" ;
when "110" => EnJRrstemp <= "11000000" ;
when others => EnJRrstemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
EnJRrstemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
EnJRrstemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
EnJRrstemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
EnJRrstemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
EnJRrstemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
En <= EnJRrstemp when (OutSelectJRrstemp /= "00000000") else Entemp; -- To given JRrs priority
OutSelect_result <= OutSelectJRrs when (OutSelectJRrstemp /= "00000000") else OutSelect; -- To given JRrs priority
------------------------------------Done Generating Enable ------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 4: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= unsigned(IssuequeRobTag(0)) - unsigned(Rob_TopPtr);
Buffer1Depth <= unsigned(IssuequeRobTag(1)) - unsigned(Rob_TopPtr);
Buffer2Depth <= unsigned(IssuequeRobTag(2)) - unsigned(Rob_TopPtr);
Buffer3Depth <= unsigned(IssuequeRobTag(3)) - unsigned(Rob_TopPtr);
Buffer4Depth <= unsigned(IssuequeRobTag(4)) - unsigned(Rob_TopPtr);
Buffer5Depth <= unsigned(IssuequeRobTag(5)) - unsigned(Rob_TopPtr);
Buffer6Depth <= unsigned(IssuequeRobTag(6)) - unsigned(Rob_TopPtr);
Buffer7Depth <= unsigned(IssuequeRobTag(7)) - unsigned(Rob_TopPtr);
--################################################################################################
--***************************************************************************************************************
-- This process does the selective flushing, if the instruction is younger to branch and there is an intent to flush
-- Flush the instruction if it is a valid instruction, this is an additional qualification which is unnecessary
-- We are just flushing the valid instructions and not caring about invalid instructions
--*****************************************************************************************************************
--###############################################################################################
-- TODO 5: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth , Buffer4Depth , Buffer5Depth ,
Buffer6Depth , Buffer7Depth , En ,IssuequeInstrValReg)
begin
Flush <= (others => '0') ;
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then -- WHY THIS CONDITION?? CHECK WETHER THE INSTRUCTION IS AFTER BRANCH OR NOT(i.e, instruction is younger to branch)
if ( En(0) = '0' ) then -- NOT UPDATING HENCE FLUSH IF INSTRUCTION IS VALID
Flush(0) <= IssuequeInstrValReg(0) ; --just to make sure that flush only valid instruction
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then -- check for younger instructions
if ( En(0) = '1' ) then
Flush(0) <= Flush(1); --Hint: Take into account the shift mechanism so is it i or i+1 or i - 1?
else
Flush(1) <= IssuequeInstrValReg(1) ;-- NO UPDATION SO FLUSH(1) IS THE STATUS OF INSTRUCTION (1)
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( En(1) = '1' ) then
Flush(1) <= Flush(2);
else
Flush(2) <= IssuequeInstrValReg(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( En(2) = '1' ) then
Flush(2) <= Flush(3);
else
Flush(3) <= IssuequeInstrValReg(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( En(3) = '1' ) then
Flush(3) <= Flush(4);
else
Flush(4) <= IssuequeInstrValReg(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( En(4) = '1' ) then
Flush(4) <= Flush(5);
else
Flush(5) <= IssuequeInstrValReg(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( En(5) = '1' ) then
Flush(5) <= Flush(6);
else
Flush(6) <= IssuequeInstrValReg(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( En(6) = '1' ) then
Flush(6) <= Flush(7);
else
Flush(7) <= IssuequeInstrValReg(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--###############################################################################################
-- TODO 6: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RtReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction being issued for ALU Queue, load - store queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit and do the forwarding if necessary.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process ( IssuequeRtPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Lsbuf_RdWrite, Iss_Lsb, IssuequeRegWrite , IssuequeInstrValReg, IssuequeRtReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RtReadyTemp <= (others => '0') ;
if (( (IssuequeRtPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(0) ='0' and IssuequeInstrValReg(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RtReadyTemp(0) <= IssuequeRtReadyReg(0);
end if ;
if (( (IssuequeRtPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(1) ='0' and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RtReadyTemp(0) <= IssuequeRtReadyReg(1);
else
RtReadyTemp(1) <= IssuequeRtReadyReg(1);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(2) ='0' and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RtReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RtReadyTemp(1) <= IssuequeRtReadyReg(2);
else
RtReadyTemp(2) <= IssuequeRtReadyReg(2);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(3) ='0' and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RtReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RtReadyTemp(2) <= IssuequeRtReadyReg(3);
else
RtReadyTemp(3) <= IssuequeRtReadyReg(3);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(4) ='0' and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RtReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RtReadyTemp(3) <= IssuequeRtReadyReg(4);
else
RtReadyTemp(4) <= IssuequeRtReadyReg(4);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(5) ='0' and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RtReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RtReadyTemp(4) <= IssuequeRtReadyReg(5);
else
RtReadyTemp(5) <= IssuequeRtReadyReg(5);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(6) ='0' and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RtReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RtReadyTemp(5) <= IssuequeRtReadyReg(6);
else
RtReadyTemp(6) <= IssuequeRtReadyReg(6);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRtPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRtReadyReg(7) ='0' and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RtReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RtReadyTemp(6) <= IssuequeRtReadyReg(7);
else
RtReadyTemp(7) <= IssuequeRtReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
--###############################################################################################
-- TODO 7: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RsReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for load - store queue, ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process (IssuequeRsPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Iss_Lsb, Lsbuf_RdWrite,IssuequeInstrValReg, IssuequeRsReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RsReadyTemp <= (others => '0');
if (( (IssuequeRsPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(0) ='0'and IssuequeInstrValReg(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RsReadyTemp(0) <= IssuequeRsReadyReg(0);
end if ;
if (( (IssuequeRsPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(1) ='0'and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RsReadyTemp(0) <= IssuequeRsReadyReg(1);
else
RsReadyTemp(1) <= IssuequeRsReadyReg(1);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(2) ='0'and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RsReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RsReadyTemp(1) <= IssuequeRsReadyReg(2);
else
RsReadyTemp(2) <= IssuequeRsReadyReg(2);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(3) ='0'and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RsReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RsReadyTemp(2) <= IssuequeRsReadyReg(3);
else
RsReadyTemp(3) <= IssuequeRsReadyReg(3);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or(IssuequeRsPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(4) ='0'and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RsReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RsReadyTemp(3) <= IssuequeRsReadyReg(4);
else
RsReadyTemp(4) <= IssuequeRsReadyReg(4);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(5) ='0'and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RsReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RsReadyTemp(4) <= IssuequeRsReadyReg(5);
else
RsReadyTemp(5) <= IssuequeRsReadyReg(5);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(6) ='0'and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RsReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RsReadyTemp(5) <= IssuequeRsReadyReg(6);
else
RsReadyTemp(6) <= IssuequeRsReadyReg(6);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = '1') or (IssuequeRsPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = '1')) and IssuequeRsReadyReg(7) ='0'and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RsReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RsReadyTemp(6) <= IssuequeRsReadyReg(7);
else
RsReadyTemp(7) <= IssuequeRsReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
----------------------------------------------------------------------------------------------------
--------------------------------- ------------------------------
process ( clk , Resetb )
begin
if ( Resetb = '0' ) then
IssuequeInstrValReg <= (others => '0') ;
IssuequeRsReadyReg <= (others => '0');
IssuequeRtReadyReg <= (others => '0');
IssuequeJR <= (others => '0');
IssuequeJRrs <= (others => '0');
IssuequeJAL <= (others => '0');
elsif ( Clk'event and Clk = '1' ) then
IssuequeRsReadyReg <= RsReadyTemp;
IssuequeRtReadyReg <= RtReadyTemp;
-- end if;
for I in 6 downto 0 loop
if ( Flush(I) = '1' ) then
IssuequeInstrValReg(I) <= '0' ;
-- translate_off
Issuequeinstruction(I) <= (others => '0') ;
-- translate_on
else
if ( En(I) = '1' ) then --update
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I + 1) ;
IssuequeRsPhyAddrReg(I) <= IssuequeRsPhyAddrReg(I + 1);
IssuequeRdPhyAddrReg(I) <= IssuequeRdPhyAddrReg(I + 1);
IssuequeRtPhyAddrReg(I) <= IssuequeRtPhyAddrReg(I + 1);
IssuequeRobTag(I) <= IssuequeRobTag(I + 1);
IssuequeRegWrite(I) <= IssuequeRegWrite(I + 1);
IssuequeOpcodeReg(I) <= IssuequeOpcodeReg(I + 1);
IssuequeBranchPredict(I) <= IssuequeBranchPredict(I + 1);
IssuequeBranch(I) <= IssuequeBranch(I + 1);
IssuequeBranchAddr(I) <= IssuequeBranchAddr(I + 1);
IssuequeBranchPCBits(I) <= IssuequeBranchPCBits(I + 1);
IssuequeJR(I) <= IssuequeJR(I + 1);
IssuequeJRrs(I) <= IssuequeJRrs(I + 1);
IssuequeJAL(I) <= IssuequeJAL(I + 1);
IssuequeImmediate(I) <= IssuequeImmediate(I + 1);
-- translate_off
Issuequeinstruction(I) <= Issuequeinstruction(I + 1);
-- translate_on
else
---If can be removed ---
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I) ;
end if ;
end if ;
end loop;
if ( Flush(7) = '1' ) then
IssuequeInstrValReg(7) <= '0' ;
-- translate_off
Issuequeinstruction(7) <= (others => '0') ;
-- translate_on
else
if ( En(7) = '1' ) then
IssuequeInstrValReg(7) <= Dis_Issquenable;
IssuequeRdPhyAddrReg(7) <= Dis_NewRdPhyAddr ;
IssuequeOpcodeReg(7) <= Dis_Opcode ;
IssuequeRobTag(7) <= Dis_RobTag;
IssuequeRegWrite(7) <= Dis_RegWrite;
IssuequeRtPhyAddrReg(7) <= Dis_RtPhyAddr ;
IssuequeRsPhyAddrReg(7) <= Dis_RsPhyAddr ;
IssuequeBranchPredict(7) <= Dis_BranchPredict;
IssuequeBranch(7) <= Dis_Branch;
IssuequeBranchAddr(7) <= Dis_BranchOtherAddr;
IssuequeBranchPCBits(7) <= Dis_BranchPCBits;
IssuequeRsReadyReg(7) <= Dis_RsDataRdy;
IssuequeRtReadyReg(7) <= Dis_RtDataRdy;
IssuequeJR(7) <= Dis_Jr31Inst;
IssuequeJRrs(7) <= Dis_JrRsInst;
IssuequeJAL(7) <= Dis_JalInst;
IssuequeImmediate(7) <= Dis_Immediate;
-- translate_off
Issuequeinstruction(7) <= Dis_instruction;
-- translate_on
else
IssuequeInstrValReg(7) <= IssuequeInstrValReg(7) ;
end if ;
end if ;
end if ;
end process ;
--- Selecting the Output to Go to Execution Unit, Physical Register Filed, Issue Unit
Iss_RsPhyAddrAlu <= IssuequeRsPhyAddrReg(CONV_INTEGER (unsigned( OutSelect_result))) ;
Iss_RtPhyAddrAlu <= IssuequeRtPhyAddrReg (CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRdPhyAddr <= IssuequeRdPhyAddrReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRegWrite <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RdPhyAddrAlu <= IssuedRdPhyAddr;
Iss_OpcodeAlu <= IssuequeOpcodeReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RobTagAlu <= IssuequeRobTag(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RegWriteAlu <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchPredictAlu <= IssuequeBranchPredict(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAlu <= IssuequeBranch(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAddrAlu <= IssuequeBranchAddr(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchUptAddrAlu <= IssuequeBranchPCBits(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrInstAlu <= IssuequeJR(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JalInstAlu <= IssuequeJAL(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrRsInstAlu <= IssuequeJrRs(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_ImmediateAlu <= IssuequeImmediate(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_off
Iss_instructionAlu <= Issuequeinstruction(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_on
end behav ;
|
gpl-2.0
|
5eeb31726cecb72141e102096cd3dcd5
| 0.519789 | 4.793352 | false | false | false | false |
lvoudour/arty-uart
|
src/uart_rx.vhd
| 1 | 4,968 |
--------------------------------------------------------------------------------
--
-- UART Rx module
--
-- 8 bit data, 1 stop bit, no parity. Intended for the Digilent Arty Artix-7
-- FPGA board, but can be easily used in other projects without modification.
--
-- Signals:
-- clk : clock of frequency G_CLOCK_FREQ
-- rst : active high synchronous reset
-- rx_in : Rx data line. Should be routed to the Tx pin of the external
-- UART device.
-- rx_data_out : 8 bit data received
-- rx_valid_out : 1 clk cycle pulse that indicates rx_data_out is valid.
--
-- Parameters:
-- G_BAUD_RATE : UART baud rate
-- G_CLOCK_FREQ : clk frequency. Can be fractional
--
-- Optimally, the baud rate must be an integer multiple of the clock
-- frequency. If not, it's rouded to the closest integer. In such cases
-- care must be taken to ensure sampling does not deviate significantly from
-- the center of the "eye"(ie. the middle of the received bit).
--
-- It is recommended to use sync flip-flops and a glitch filter before
-- connecting the rx input to the external UART device.
--
-- Arty FPGA board specific notes:
-- The FT2232H chip does not support baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud
-- and 11 Mbaud.
-- http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf
--
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity uart_rx is
generic(
G_BAUD_RATE : positive := 1250000;
G_CLOCK_FREQ : real := 100.0e6
);
port(
clk : in std_logic;
rst : in std_logic;
rx_in : in std_logic;
rx_data_out : out std_logic_vector(7 downto 0);
rx_valid_out : out std_logic
);
end entity uart_rx;
architecture rtl of uart_rx is
constant C_CLK_DIVISOR : positive := positive(round(G_CLOCK_FREQ / real(G_BAUD_RATE)));
constant C_DIV_WIDTH : positive := positive(ceil(log2(real(C_CLK_DIVISOR))));
type fsm_rx_type is (
RX_IDLE,
RX_DATA,
RX_STOP
);
signal fsm_rx_state : fsm_rx_type := RX_IDLE;
signal cnt_div_r : unsigned(C_DIV_WIDTH-1 downto 0) := (others=>'0');
signal cnt_data_r : unsigned(7 downto 0) := (others=>'0');
signal rx_data_sr : std_logic_vector(7 downto 0) := (others=>'0');
signal rx_r : std_logic := '0';
signal rx_falling_edge_c : std_logic := '0';
signal rx_valid_r : std_logic := '0';
begin
rx_falling_edge_c <= (not rx_in) and rx_r;
-- A counter is used to synchronize the clock to the baud rate. The counter
-- is reset at the falling edge of the start bit. Sampling should be done
-- exactly halfway (ie. after C_CLK_DIVISOR/2 cycles)
proc_div_counter:
process(clk)
begin
if rising_edge(clk) then
rx_r <= rx_in;
-- reset counter
if (rx_falling_edge_c = '1') and (fsm_rx_state = RX_IDLE) then
cnt_div_r <= (others=>'0');
else
if (cnt_div_r = C_CLK_DIVISOR - 1) then
cnt_div_r <= (others=>'0');
else
cnt_div_r <= cnt_div_r + 1;
end if;
end if;
end if;
end process;
proc_fsm_rx:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
rx_valid_r <= '0';
fsm_rx_state <= RX_IDLE;
else
rx_valid_r <= '0';
case fsm_rx_state is
-- Wait for the start bit
when RX_IDLE =>
-- We're checking rx_r and not rx_in
-- just in case the counter happens to be halway at the falling edge,
-- causing a false trigger
cnt_data_r <= (others=>'0');
if (rx_r = '0') and (cnt_div_r = C_CLK_DIVISOR/2 - 1) then
fsm_rx_state <= RX_DATA;
end if;
-- Sample the data bits and shift them into a register
when RX_DATA =>
if (cnt_div_r = C_CLK_DIVISOR/2 - 1) then
rx_data_sr <= rx_r & rx_data_sr(7 downto 1);
if (cnt_data_r = 7) then
fsm_rx_state <= RX_STOP;
else
cnt_data_r <= cnt_data_r + 1;
end if;
end if;
-- Check for the stop bit
when RX_STOP =>
if (cnt_div_r = C_CLK_DIVISOR/2 - 1) then
-- raise the valid flag only if the stop bit is 1
if (rx_r = '1') then
rx_valid_r <= '1';
end if;
fsm_rx_state <= RX_IDLE;
end if;
when others =>
fsm_rx_state <= RX_IDLE;
end case;
end if;
end if;
end process;
rx_data_out <= rx_data_sr;
rx_valid_out <= rx_valid_r;
end architecture;
|
mit
|
31230f9aede6eb2b7de0740c82d6e211
| 0.545089 | 3.478992 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/CDB.vhd
| 1 | 11,783 |
------------------------------------------
-- cdb_r1.vhd
-- Author : Vaibhav Dhotre
-- Date : 05/02/2010
-- Tomasulo 2010
-- cdb control mux
-- University of Southern California
-------------------------------------------
-- This CDB is the same as pervious design. Only modification is Rob depth
-- of the instruction on CDB is calculated and given to all modules.
-- For a branch, jr $31 instruction if mispredicted a flush signal is generated
-- and informed to all the required modules.
-------------------------------------------
--LIBRARY DECLARATION
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use IEEE.NUMERIC_STD.ALL;
--ENTITY DECLARATION
entity cdb is
generic(
Resetb_ACTIVE_VALUE : std_logic := '0'
);
port(
Clk : in std_logic;
Resetb : in std_logic;
-- from ROB
Rob_TopPtr : in std_logic_vector (4 downto 0 ) ;
-- from integer execution unit
Alu_RdData : in std_logic_vector(31 downto 0);
Alu_RdPhyAddr : in std_logic_vector(5 downto 0);
Alu_BranchAddr : in std_logic_vector(31 downto 0);
Alu_Branch : in std_logic;
Alu_BranchOutcome : in std_logic;
Alu_BranchUptAddr : in std_logic_vector( 2 downto 0 );
Iss_Int : in std_logic;
Alu_BranchPredict : in std_logic;
Alu_JrFlush : in std_logic;
Alu_RobTag : in std_logic_vector( 4 downto 0);
Alu_RdWrite : in std_logic;
-- translate_off
Alu_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- from mult execution unit
Mul_RdData : in std_logic_vector(31 downto 0); -- mult_data coming from the multiplier
Mul_RdPhyAddr : in std_logic_vector(5 downto 0); -- mult_prfaddr coming from the multiplier
Mul_Done : in std_logic ; -- this is the valid bit coming from the bottom most pipeline register in the multiplier wrapper
Mul_RobTag : in std_logic_vector( 4 downto 0);
Mul_RdWrite : in std_logic;
-- translate_off
Mul_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- from div execution unit
Div_Rddata : in std_logic_vector(31 downto 0); -- div_data coming from the divider
Div_RdPhyAddr : in std_logic_vector(5 downto 0); -- div_prfaddr coming from the divider
Div_Done : in std_logic ; -- this is the valid bit coming from the bottom most pipeline register in the multiplier wrapper
Div_RobTag : in std_logic_vector( 4 downto 0);
Div_RdWrite : in std_logic;
-- translate_off
Div_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- from load buffer and store word
Lsbuf_Data : in std_logic_vector(31 downto 0);
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0);
Iss_Lsb : in std_logic;
Lsbuf_RobTag : in std_logic_vector( 4 downto 0);
Lsbuf_SwAddr : in std_logic_vector(31 downto 0);
Lsbuf_RdWrite : in std_logic;
-- translate_off
Lsbuf_instruction : in std_logic_vector(31 downto 0);
-- translate_on
--outputs of cdb
-- translate_off
Cdb_instruction : out std_logic_vector(31 downto 0);
-- translate_on
Cdb_Valid : out std_logic;
Cdb_PhyRegWrite : out std_logic;
Cdb_Data : out std_logic_vector(31 downto 0);
Cdb_RobTag : out std_logic_vector(4 downto 0);
Cdb_BranchAddr : out std_logic_vector(31 downto 0);
Cdb_BranchOutcome : out std_logic;
Cdb_BranchUpdtAddr : out std_logic_vector( 2 downto 0 );
Cdb_Branch : out std_logic;
Cdb_Flush : out std_logic;
Cdb_RobDepth : out std_logic_vector (4 downto 0 );
Cdb_RdPhyAddr : out std_logic_vector (5 downto 0 );
Cdb_SwAddr : out std_logic_vector (31 downto 0)
);
end cdb;
architecture Behavioral of cdb is
-- depth of instruction in various queues
signal Int_instDepth : std_logic_vector ( 4 downto 0 ); --from the various issue queues
signal Lsbuf_instDepth : std_logic_vector ( 4 downto 0 );
signal Mult_instDepth : std_logic_vector ( 4 downto 0 );
signal Div_instDepth : std_logic_vector ( 4 downto 0 );
-- intermediate signals
signal issue_int_temp : std_logic ;
signal issue_Lsbuf_temp : std_logic ;
signal issue_Mult_temp : std_logic ;
signal issue_Div_temp : std_logic ;
signal Cdb_RobTag_temp : std_logic_vector ( 4 downto 0 ) ;
signal Cdb_RobDepth_temp : std_logic_vector (4 downto 0 ) ;
signal Cdb_Flush_temp : std_logic;
begin
-- to calculate the depth of the instruction
-- tells you how many instructions are there between the current instruction and comitting instruction
Int_instDepth <= unsigned(Alu_RobTag) - unsigned(Rob_TopPtr ) ;
Lsbuf_instDepth <= unsigned(Lsbuf_RobTag) - unsigned(Rob_TopPtr ) ;
Mult_instDepth <= unsigned(Mul_RobTag) - unsigned(Rob_TopPtr ) ;
Div_instDepth <= unsigned(Div_RobTag) - unsigned(Rob_TopPtr ) ;
--CDB will calculate the depth of the current instrcution.
Cdb_RobDepth_temp <= Cdb_RobTag_temp - Rob_TopPtr + 32;
Cdb_RobDepth <= Cdb_RobDepth_temp;
Cdb_RobTag <= Cdb_RobTag_temp;
Cdb_Flush <= Cdb_Flush_temp;
process ( Iss_Int , Int_instDepth , Cdb_Flush_temp , Cdb_RobDepth_temp ) -- if robflush is true and instruction is younger to branch instruction flush the instruction
begin
if ( Cdb_Flush_temp = '1' and Int_instDepth > Cdb_RobDepth_temp ) then
issue_int_temp <= '0'; -- if flush then invalidate the data coming on CDB
else
issue_int_temp <= Iss_Int ;
end if ;
end process ;
process ( Iss_Lsb , Lsbuf_instDepth , Cdb_Flush_temp , Cdb_RobDepth_temp ) -- if robflush is true and instruction is younger to branch instruction flush the instruction
begin
if ( Cdb_Flush_temp = '1' and Lsbuf_instDepth > Cdb_RobDepth_temp ) then
issue_Lsbuf_temp <= '0'; -- if flush then invalidate the data coming on CDB
else
issue_Lsbuf_temp <= Iss_Lsb ;
end if ;
end process ;
--------------------------------------------------
process ( Mul_Done, Mult_instDepth , Cdb_Flush_temp , Cdb_RobDepth_temp ) -- if robflush is true and instruction is younger to branch instruction, flush the instruction
begin
if ( Cdb_Flush_temp = '1' and Mult_instDepth > Cdb_RobDepth_temp )then
issue_Mult_temp <= '0' ; -- if flush then invalidate the data coming on CDB
else
issue_Mult_temp <= Mul_Done ;
end if ;
end process ;
process ( Div_Done, Div_instDepth, Cdb_Flush_temp , Cdb_RobDepth_temp ) -- if robflush is true and instruction is younger to branch instruction, flush the instruction
begin
if ( Cdb_Flush_temp = '1' and Div_instDepth > Cdb_RobDepth_temp ) then
issue_Div_temp <= '0' ; -- if flush then invalidate the data coming on CDB
else
issue_Div_temp <= Div_Done ;
end if ;
end process ;
process ( Clk,Resetb )
begin
if ( Resetb = '0' ) then
Cdb_Valid <= '0' ;
Cdb_BranchOutcome <= '0' ;
Cdb_Branch <= '0' ;
Cdb_PhyRegWrite <= '0' ;
Cdb_Flush_temp <= '0' ;
Cdb_Data <= ( others => 'X' ) ;
Cdb_BranchUpdtAddr <= ( others => 'X' ) ;
elsif( Clk'event and Clk = '1' ) then
Cdb_Valid <= issue_int_temp or issue_Lsbuf_temp or issue_Mult_temp or issue_Div_temp ;
Cdb_BranchOutcome <= '0' ;
Cdb_Branch <= '0' ;
Cdb_PhyRegWrite <= '0' ;
Cdb_SwAddr <= (others => '0');
Cdb_Flush_temp <= Alu_JrFlush and Iss_Int; -- changed by Manpreet Alu_JrFlush is generated by ALU continuously without validating it with ISS_Int
Cdb_BranchUpdtAddr <= Alu_BranchUptAddr;
if( issue_int_temp = '1' ) then
Cdb_Data <= Alu_RdData;
Cdb_RdPhyAddr <= Alu_RdPhyAddr ;
Cdb_RobTag_Temp <= Alu_RobTag;
Cdb_BranchAddr <= Alu_BranchAddr;
Cdb_BranchOutcome <= Alu_BranchOutcome;
Cdb_PhyRegWrite <= Alu_RdWrite;
-- translate_off
Cdb_instruction <= Alu_instruction;
-- translate_on
Cdb_Branch <= Alu_Branch;
if(Alu_Branch = '1') then
if(Alu_BranchOutcome = Alu_BranchPredict) then
Cdb_Flush_temp <= Alu_JrFlush; --Flush if mispredicted.
else
Cdb_Flush_temp <= '1';
end if;
else
Cdb_Flush_temp <= Alu_JrFlush;
end if ;
end if;
if( issue_Lsbuf_temp = '1' ) then
Cdb_Data <= Lsbuf_Data ;
Cdb_RdPhyAddr <= Lsbuf_PhyAddr ;
Cdb_RobTag_temp<= Lsbuf_RobTag;
Cdb_SwAddr <= Lsbuf_SwAddr;
Cdb_PhyRegWrite<= Lsbuf_RdWrite;
-- translate_off
Cdb_instruction <= Lsbuf_instruction;
-- translate_on
end if ;
if( issue_Mult_temp = '1' ) then
Cdb_Data <= Mul_RdData ;
Cdb_RdPhyAddr <= Mul_RdPhyAddr ;
Cdb_RobTag_temp <= Mul_RobTag;
Cdb_PhyRegWrite <= Mul_RdWrite;
-- translate_off
Cdb_instruction <= Mul_instruction;
-- translate_on
end if ;
if( issue_Div_temp = '1' ) then
Cdb_Data <= Div_Rddata ;
Cdb_RdPhyAddr <= Div_RdPhyAddr ;
Cdb_RobTag_temp<= Div_RobTag;
Cdb_PhyRegWrite<= Div_RdWrite;
-- translate_off
Cdb_instruction <= Div_instruction;
-- translate_on
end if ;
end if ;
end process ;
end Behavioral;
|
gpl-2.0
|
604e1f55f6da154f7272ab68391f1401
| 0.492489 | 4.41973 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/adder1bit_comb.vhd
| 1 | 2,095 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: adder1bit_comb.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity adder1bit_comb is
port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Z : out std_logic;
Cout : out std_logic);
end adder1bit_comb;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of adder1bit_comb is
begin
Z <= (A xor B) xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end rtl;
|
gpl-3.0
|
e5d8936793c44310352db7078e9396c6
| 0.471572 | 4.890187 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/TX_SEND_FIFO/simulation/fg_tb_synth.vhd
| 1 | 10,347 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : TX_SEND_FIFO_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
c373d4114a6e7c72d2973afeeb931c90
| 0.46023 | 4.109214 | false | false | false | false |
csrhau/sandpit
|
VHDL/adder/test_adder.vhdl
| 1 | 1,011 |
library ieee;
use ieee.std_logic_1164.all;
entity test_adder is
end test_adder;
architecture behavioural of test_adder is
signal x, y, sum, carry: std_logic;
component adder is
port (
x, y: in std_logic;
sum, carry: out std_logic
);
end component;
begin
adder_0: adder port map (
x => x, y=>y,
sum => sum, carry => carry
);
process
begin
x <= '1';
y <= '1';
wait for 1 ns;
assert carry = '1' and sum = '0'
report "result should be 0 carry 1" severity error;
x <= '0';
y <= '0';
wait for 1 ns;
assert carry = '0' and sum = '0'
report "result should be 0" severity error;
x <= '1';
y <= '0';
wait for 1 ns;
assert carry = '0' and sum = '1'
report "result should be 1" severity error;
x <= '0';
y <= '1';
wait for 1 ns;
assert carry = '0' and sum = '1'
report "result should be 1" severity error;
wait;
end process;
end behavioural;
|
mit
|
edcdd88349ad5923703cdf113b8f14d0
| 0.536103 | 3.358804 | false | true | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_POST_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,389 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT WR_FLASH_POST_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
644b150edabd0fb77718ed7b684a1fc5
| 0.502854 | 3.923183 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_sort_selection_only.vhd
| 3 | 10,398 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
-- In the original program,
-- Bubble_sort sorts the first 5 items in data memory (location 0 ~ 4)
-- Selection_sort sorts the next 5 items in data memory (location 5 ~ 9)
--
-- This test stream contains only selection_sort for the ease of debugging. It will sort 5 items in location 5 ~ 9
-- Only the first instruction ADD $0, $0, $0 was replaced with ADD $31, $4, $0 for proper initialization.
--
-- In our design, it takes 9170ns to complete execution of both sort and checker.
--
signal mem : mem_type := (
X"01215020_00BF4820_00A01020_0080F820", -- Loc 0C, 08, 04, 00
X"007F6819_00612020_00A01820_00003020", -- Loc 1C, 18, 14, 10
X"009F7019_02E0B020_01A06020_8DB70000", -- Loc 2C, 28, 24, 20
X"01C06020_10C00002_0316302A_8DD80000", -- Loc 3C, 38, 34, 30
X"1000FFF7_108A0001_00812020_0300B020", -- Loc 4C, 48, 44, 40
X"00611820_AD970001_ADB60001_00000020", -- Loc 5C, 58, 54, 50
X"00000020_1000FFEC_10690001_00612020", -- Loc 6C, 68, 64, 60
X"00BFE019_035FD820_00BFD019_00000020", -- Loc 7C, 78, 74, 70
X"03DDC82A_8F7E0000_8F5D0000_039AE020", -- Loc 8C, 88, 84, 80
X"037FD820_035FD020_1000FFFF_13200001", -- Loc 9C, 98, 94, 90
X"00000020_00000020_1000FFF7_137C0001", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- SELECTION SORT
--
-- Preconditions on Register file
-- Registers set to their register number
-- ex) $0 = 0, $1 = 1, $2 = 2 ...... $31 = 31
-- Author: Byung-Yeob Kim, EE560 TA
-- Date: Aug-01-2008
-- University of Southern California
--
--000 0080F820 add $31, $4, $0 -- $31 = 4 *** INITIALIZATION FOR SELECTION SORT ***
--004 00A01020 add $2, $5, $0 -- set min = 5
--008 00BF4820 add $9, $5, $31 -- $9 = 9
--00c 01215020 add $10, $9, $1 -- $10 = 10
--
--010 00003020 add $6, $0, $0 -- slt_result = 0
--014 00A01820 add $3, $5, $0 -- i = 5
--018 00612020 add $4, $3, $1 -- j = i+1 *** SELECTION SORT STARTS HERE ***
--01c 007F6819 mul $13, $3, $31 -- ai = i*4
--
--020 8DB70000 lw $23, 0($13) -- mi = M(ai)
--024 01A06020 add $12, $13, $0 -- amin = ai
--028 02E0B020 add $22, $23, $0 -- mmin = mi
--02c 009F7019 mul $14, $4, $31 -- aj = j*4
--
--030 8DD80000 lw $24, 0($14) -- mj = M(aj)
--034 0316302A slt $6, $24, $22 -- (mj < mmin)
--038 10C00002 beq $6, $0, 2 -- if(no)
--03c 01C06020 add $12, $14, $0 -- amin = aj
--
--040 0300B020 add $22, $24, $0 -- mmin = mj
--044 00812020 add $4, $4, $1 -- j++
--048 108A0001 beq $4, $10, 1 -- (j = 10)
--04c 1000FFF7 beq $0, $0, -9 -- if(no)
--
--050 00000020 add $0, $0, $0 -- nop
--054 ADB60001 sw $22, 0 ($13) -- M(ai) = mmin // swap
--058 AD970001 sw $23, 0 ($12) -- M(amin) = mi // swap
--05c 00611820 add $3, $3, $1 -- i++
--
--060 00612020 add $4, $3, $1 -- j = i+1
--064 10690001 beq $3, $9, 1 -- (i==9)
--068 1000FFEC beq $0, $0, -20 -- if(no)
--06c 00000020 add $0, $0, $0 -- nop
--
--070 00000020 add $0, $0, $0 -- *** CHECKER FOR THE NEXT 5 ITEMS ***
--074 00BFD019 mul $26, $5, $31 -- addr1 = num_of_items * 4
--078 035FD820 add $27, $26, $31 -- addr2 = addr1 + 4
--07c 00BFE019 mul $28, $5, $31 -- addr3 = num_of_items * 4
--
--080 039AE020 add $28, $28, $26 -- addr3 = addr3 + addr1
--084 8F5D0000 lw $29, 0 ($26) -- maddr1 = M(addr1)
--088 8F7E0000 lw $30, 0 ($27) -- maddr2 = M(addr2)
--06c 03DDC82A slt $25, $30, $29 -- (maddr2 < maddr1) ? -- corrected
--
--070 13200001 beq $25, $0, 1 -- if no, proceed to the next data -- corrected
--094 1000FFFF beq $0, $0, -1 -- else, You're stuck here
--098 035FD020 add $26, $26, $31 -- addr1 = addr1 + 4
--09c 037FD820 add $27, $27, $31 -- addr2 = addr2 + 4
--
--100 137C0001 beq $27, $28, 1 -- if all tested, proceed to the next program
--104 1000FFF7 beq $0, $0, -9 -- else test next data
--108 00000020 add $0, $0, $0 -- noop
--10c 00000020 add $0, $0, $0 -- noop
--
--
--REG FILE USED BY BUBBLE SORT
--Initilaly, the content of a register is assumed to be same as its register number.
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> ak address of k
--$3 ----> ai address of i
--$4 ----> aj address of j
--$5 ----> 5 num_of_items (items at location 0~4 will be sorted)
--$6 ----> result_of_slt
--$13 ----> mi M(ai)
--$14 ----> mj M(aj)
--$25~$30 -> RESERVED for the checker
--$31 ----> 4 conatant for calculating word address
--
--REG FILE USED BY SELECTION SORT
--
--$0 ----> 0 constant
--$1 ----> 1 constant
--$2 ----> min index of the minimum value
--$3 ----> i index i
--$4 ----> j index j
--$5 ----> 5 num_of_items (items at location 5~9 will be sorted)
--$6 ----> result of slt
--$9 ----> 9 constant
--$10 ----> 10 constant
--$12 ----> amin address of min
--$13 ----> ai address of i
--$14 ----> aj address of j
--$15~$21 -> don't care
--$22 ----> mmin M(amin)
--$23 ----> mi M(ai)
--$24 ----> mj M(aj)
--$25~$30 -> RESERVED for checker
--$31 ----> 4 for calculating word address
--
--REG FILE USED BY CHECKER
--
--$26 ----> addr1 starting point
--$27 ----> addr2 ending point
--$28 ----> addr3 bound
--$29 ----> maddr1 M(addr1)
--$30 ----> maddr2 M(addr2)
--
|
gpl-2.0
|
82c4735d5c0ffaf7e7a375330f72c2ae
| 0.613099 | 2.827849 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_FIFO/example_design/WR_FLASH_FIFO_top_wrapper.vhd
| 1 | 19,277 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: WR_FLASH_FIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity WR_FLASH_FIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(256-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(12-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(12-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end WR_FLASH_FIFO_top_wrapper;
architecture xilinx of WR_FLASH_FIFO_top_wrapper is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component WR_FLASH_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_i <= wr_clk;
rd_clk_i <= rd_clk;
fg1 : WR_FLASH_FIFO_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
89c8d30709292215afb6127a441b1c3b
| 0.484982 | 3.958316 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/simulation/checker.vhd
| 2 | 5,393 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
ELSE
EN_R <= EN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_R='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
gpl-2.0
|
35a85142204e0880d00a20a863b8358a
| 0.592991 | 4.366802 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/debouncer.vhd
| 1 | 3,733 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: debouncer.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garces
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity debouncer is
port (
clk : in STD_LOGIC;
rst : in std_logic;
x : in STD_LOGIC;
pulso2Hz: in std_logic;
xDeb : out STD_LOGIC
);
end debouncer;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture arq of debouncer is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
type t_st is (s0, s1, s2, s3);
signal current_state, next_state: t_st;
begin
-----------------------------------------------------------------------------
-- Calculo el estado siguiente
-----------------------------------------------------------------------------
p_next_state: process(current_state, pulso2Hz, x)
begin
case current_state is
when s0 =>
if x = '1' then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
next_state <= s2;
when s2 =>
if pulso2Hz = '1' then
next_state <= s3;
else
next_state <= s2;
end if;
when s3 =>
if pulso2Hz = '1' then
next_state <= s0;
else
next_state <= s3;
end if;
when others =>
next_state <= s0;
end case;
end process p_next_state;
-----------------------------------------------------------------------------
-- Salidas de la FSM (Moore)
-----------------------------------------------------------------------------
p_salidasMoore: process(current_state)
begin
case current_state is
when s1 =>
xDeb <= '1';
when others =>
xDeb <= '0';
end case;
end process p_salidasMoore;
-----------------------------------------------------------------------------
-- Proceso de actualizacion del estado:
-----------------------------------------------------------------------------
p_update_state: process(clk, rst)
begin
if rst = '1' then
current_state <= s0;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process p_update_state;
end arq;
|
gpl-3.0
|
84688eb4a40bfe8377f50cc492421dc5
| 0.426313 | 4.653367 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_3/Cfc_withBRAM.vhd
| 1 | 16,116 |
-------------------------------------------------------------------------------
--
-- Design : CFC Unit
-- Project : Tomasulo Processor
-- Entity : CFC
-- Author : Rajat Shah
-- Company : University of Southern California
-- Last Updated : April 15th, 2010
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cfc is
port ( --global signals
Clk :in std_logic; --Global Clock Signal
Resetb :in std_logic; --Global Reset Signal
--interface with dispatch unit
Dis_InstValid :in std_logic; --Flag indicating if the instruction dispatched is valid or not
Dis_CfcBranchTag :in std_logic_vector(4 downto 0); --ROB Tag of the branch instruction
Dis_CfcRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address
Dis_CfcRsAddr :in std_logic_vector(4 downto 0); --Rs Logical Address
Dis_CfcRtAddr :in std_logic_vector(4 downto 0); --Rt Logical Address
Dis_CfcNewRdPhyAddr :in std_logic_vector(5 downto 0); --New Physical Register Address assigned to Rd by Dispatch
Dis_CfcRegWrite :in std_logic; --Flag indicating whether current instruction being dispatched is register writing or not
Dis_CfcBranch :in std_logic; --Flag indicating whether current instruction being dispatched is branch or not
Dis_Jr31Inst :in std_logic; --Flag indicating if the current instruction is Jr 31 or not
Cfc_RdPhyAddr :out std_logic_vector(5 downto 0); --Previous Physical Register Address of Rd
Cfc_RsPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rs
Cfc_RtPhyAddr :out std_logic_vector(5 downto 0); --Latest Physical Register Address of Rt
Cfc_Full :out std_logic; --Flag indicating whether checkpoint table is full or not
--interface with ROB
Rob_TopPtr :in std_logic_vector(4 downto 0); --ROB tag of the intruction at the Top
Rob_Commit :in std_logic; --Flag indicating whether instruction is committing in this cycle or not
Rob_CommitRdAddr :in std_logic_vector(4 downto 0); --Rd Logical Address of committing instruction
Rob_CommitRegWrite :in std_logic; --Indicates if instruction is writing to register or not
Rob_CommitCurrPhyAddr :in std_logic_vector(5 downto 0); --Physical Register Address of Rd of committing instruction
--signals from cfc to ROB in case of CDB flush
Cfc_RobTag :out std_logic_vector(4 downto 0); --Rob Tag of the instruction to which rob_bottom is moved after branch misprediction (also to php)
--interface with FRL
Frl_HeadPtr :in std_logic_vector(4 downto 0); --Head Pointer of the FRL when a branch is dispatched
Cfc_FrlHeadPtr :out std_logic_vector(4 downto 0); --Value to which FRL has to jump on CDB Flush
--interface with CDB
Cdb_Flush :in std_logic; --Flag indicating that current instruction is mispredicted or not
Cdb_RobTag :in std_logic_vector(4 downto 0); --ROB Tag of the mispredicted branch
Cdb_RobDepth :in std_logic_vector(4 downto 0) --Depth of mispredicted branch from ROB Top
);
end cfc;
architecture cfc_arch of cfc is
--Signal declaration for 8 copies of checkpoints - Each 32 deep and 6 bit wide
type cfc_checkpoint_type is array(0 to 255) of std_logic_vector(5 downto 0);
signal Cfc_RsList, Cfc_RtList, Cfc_RdList : cfc_checkpoint_type; --3 BRAM, each containing flattened 8 tables
--Signal declaration for committed checkpoint (Retirement RAT) - 32 deep and 6 bit wide
type committed_type is array(0 to 31) of std_logic_vector(5 downto 0);
signal Committed_RsList, Committed_RtList, Committed_RdList : committed_type :=(
"000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111"); -- 3 copies of committed list initialize to 0 to 31
--Signal declaration for 8 copies of Dirty Flag Array(DFA) validating each checkpoints - Each 32 deep and 1 bit wide
type dfa_checkpoint_type is array(0 to 31) of std_logic;
type dfa_array_type is array (0 to 7) of dfa_checkpoint_type;
signal Dfa_List : dfa_array_type;
type checkpoint_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Checkpoint_TagArray: checkpoint_tag_type; --8 deep and 5 bit wide array for storing ROB tag of checkpointed branch instructions
type Frl_HeadPtrArray_type is array (0 to 7) of std_logic_vector (4 downto 0);
signal Frl_HeadPtrArray: Frl_HeadPtrArray_type;
type depth_tag_type is array (0 to 7) of std_logic_vector(4 downto 0);
signal Depth_Array: depth_tag_type;
type Cfc_Valid_Array_type is array (0 to 7) of std_logic;
signal Cfc_ValidArray: Cfc_Valid_Array_type;
signal Full, Empty : std_logic; --flag indicating if all 8 checkpoints are used or empty
signal Head_Pointer, Tail_Pointer: std_logic_vector(2 downto 0); --Head Pointer indicates active checkpoint while tail pointer indicates oldest uncommitted branch
signal Checkpoint_MatchArray: std_logic_vector (7 downto 0); --Array indicating if the instruction on CDB matches any checkpointed branch
signal DFA_RsValid, DFA_RtValid, DFA_RdValid: std_logic;
signal Cfc_RsList_temp, Cfc_RtList_temp, Cfc_RdList_temp: std_logic_vector (5 downto 0);
signal Committed_RsList_temp, Committed_RtList_temp, Committed_RdList_temp: std_logic_vector (5 downto 0);
signal Next_Head_Pointer: std_logic_vector (2 downto 0); --Temporary Head_pointer generated during CDB Flush
begin
Depth_Array(0) <= Checkpoint_TagArray(0) - Rob_TopPtr; -- std_logic_vector is treated as unsigned because of library declaration IEEE_STD_LOGIC_UNSIGNED
Depth_Array(1) <= Checkpoint_TagArray(1) - Rob_TopPtr;
Depth_Array(2) <= Checkpoint_TagArray(2) - Rob_TopPtr;
Depth_Array(3) <= Checkpoint_TagArray(3) - Rob_TopPtr;
Depth_Array(4) <= Checkpoint_TagArray(4) - Rob_TopPtr;
Depth_Array(5) <= Checkpoint_TagArray(5) - Rob_TopPtr;
Depth_Array(6) <= Checkpoint_TagArray(6) - Rob_TopPtr;
Depth_Array(7) <= Checkpoint_TagArray(7) - Rob_TopPtr;
--Combinational assignment determining if the instruction on CDB is a frozen branch or not
Checkpoint_MatchArray(0) <= '1' when ((Checkpoint_TagArray(0) = Cdb_RobTag) and (Cfc_ValidArray(0) = '1')) else
'0';
Checkpoint_MatchArray(1) <= '1' when ((Checkpoint_TagArray(1) = Cdb_RobTag) and (Cfc_ValidArray(1) = '1')) else
'0';
Checkpoint_MatchArray(2) <= '1' when ((Checkpoint_TagArray(2) = Cdb_RobTag) and (Cfc_ValidArray(2) = '1')) else
'0';
Checkpoint_MatchArray(3) <= '1' when ((Checkpoint_TagArray(3) = Cdb_RobTag) and (Cfc_ValidArray(3) = '1')) else
'0';
Checkpoint_MatchArray(4) <= '1' when ((Checkpoint_TagArray(4) = Cdb_RobTag) and (Cfc_ValidArray(4) = '1')) else
'0';
Checkpoint_MatchArray(5) <= '1' when ((Checkpoint_TagArray(5) = Cdb_RobTag) and (Cfc_ValidArray(5) = '1')) else
'0';
Checkpoint_MatchArray(6) <= '1' when ((Checkpoint_TagArray(6) = Cdb_RobTag) and (Cfc_ValidArray(6) = '1')) else
'0';
Checkpoint_MatchArray(7) <= '1' when ((Checkpoint_TagArray(7) = Cdb_RobTag) and (Cfc_ValidArray(7) = '1')) else
'0';
Cfc_Full <= Full;
--Task 0: Complete the Full and empty conditions depending on the Head_Pointer and Tail_pointer values
Full <= ; --Flag indicating that all 8 checkpoints (7 frozen + 1 Active) are being used
Empty <= ; --Flag indicating that there is no frozen checkpoint
Cfc_FrlHeadPtr <= Frl_HeadPtrArray(conv_integer(Next_Head_Pointer));
Cfc_RobTag <= Checkpoint_Tagarray(conv_integer(Next_Head_Pointer));
CfcUpdate: process (Clk, Resetb)
begin
if(Resetb = '0') then
Head_Pointer <= "000"; --Here the Head_Pointer points to the active checkpoint and not to the empty location
Tail_Pointer <= "000";
for I in 0 to 7 loop
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
Cfc_ValidArray(I) <= '0';
end loop;
elsif (Clk'event and Clk = '1') then
--Releasing the oldest checkpoint if the branch reaches top of ROB
if ((Rob_Commit = '1') and (Rob_TopPtr = Checkpoint_TagArray(conv_integer(Tail_Pointer))) and ((Tail_Pointer - Next_Head_Pointer) /= "00")) then
Tail_Pointer <= Tail_Pointer + '1';
Cfc_ValidArray(conv_integer(Tail_Pointer)) <= '0';
for I in 0 to 31 loop
Dfa_List(conv_integer(Tail_Pointer))(I) <= '0';
end loop;
end if;
if (Cdb_Flush = '1') then
---- ADDED BY MANPREET--- need to invalidate the active rat dfa bits
for J in 0 to 31 loop
Dfa_List(conv_integer(Head_Pointer))(J) <= '0';
end loop;
-----------------------------
for I in 0 to 7 loop
-- changed by Manpreet.. shouldnt invalidate the rat corresponding to branch_tag = cdb_robtag as
-- it contains instructions before the flushed branch and will become the active rat
if (Cdb_RobDepth < Depth_Array(I)) then --Invalidating all the younger checkpoints and clearing the Dfa_List
Cfc_ValidArray(I)<='0';
for J in 0 to 31 loop
Dfa_List(I)(J) <= '0';
end loop;
end if;
if (Cdb_RobDepth = Depth_Array(I)) then
Cfc_ValidArray(I)<='0';
end if ;
end loop;
Head_Pointer <= Next_Head_Pointer;
else
-- Task 1: Update the DFA bit of the Active Checkpoint on dispatch of Register Writing Instruction
-- Task 2: Create a new checkpoint for dispatched branch (i.e. freeze the active checkpoint)
if ((Dis_CfcBranch = '1' or Dis_Jr31Inst = '1')and Dis_InstValid = '1' and ((Full /= '1') or ((Rob_Commit = '1') and ))) then -- Task 2.1 - some conditions missing - think structural hazard - can't dispatch branch if all checkpoints are in use. But what if a branch is committing as well?
-- Task 2.2 - what things need to be done for a new checkpoint? Tagarray, validarray, FRL headpointer and the headpointer should be updated.
end if;
end if;
end if;
end process;
--Combinational Process to determine new head pointer during branch misprediction
CDB_Flush_Process: process (Cdb_Flush, Checkpoint_MatchArray, Frl_HeadPtrArray, Checkpoint_TagArray, Head_Pointer)
begin
Next_Head_Pointer <= Head_Pointer;
if (Cdb_Flush = '1') then
Case Checkpoint_MatchArray is --Case statement to move the head pointer on branch misprediction to corresponding frozen checkpoint
when "00000001" =>
Next_Head_Pointer <= "000";
when "00000010" =>
Next_Head_Pointer <= "001";
when "00000100" =>
Next_Head_Pointer <= "010";
when "00001000" =>
Next_Head_Pointer <= "011";
when "00010000" =>
Next_Head_Pointer <= "100";
when "00100000" =>
Next_Head_Pointer <= "101";
when "01000000" =>
Next_Head_Pointer <= "110";
when "10000000" =>
Next_Head_Pointer <= "111";
when others =>
Next_Head_Pointer <= "XXX";
end case;
end if;
end process;
--Process to find the latest value of Rs to be given to Dispatch
Dispatch_RsRead_Process: process (Clk,Resetb)
variable found_Rs1, found_Rs2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RsPointer: std_logic_vector(2 downto 0);
begin
if (Resetb = '0') then
Committed_RsList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
for I in 7 downto 0 loop
--This condition in the loop checks the 8 DFA table from Head_Pointer to Physical Bottom area to see which DFA bit is set first
if (I <= Head_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer1 := I; --storing the pointer to corresponding DFA
found_Rs1 := '1';
exit;
else
found_Rs1 := '0';
end if;
end if;
end loop ;
-- This condition n the loop scan the 8 DFA table from Physical Top to Tail_Pointer area to see which DFA bit is set first
for I in 7 downto 0 loop
if (I >= Tail_Pointer) then
if (Dfa_List(I)(conv_integer(Dis_CfcRsAddr)) = '1') then
BRAM_pointer2 := I; --storing the pointer to corresponding DFA
found_Rs2 := '1';
exit;
else
found_Rs2 := '0';
end if;
end if;
end loop;
-- Task 3: Use found_Rs1, found_Rs2, BRAM_pointer1 and BRAM_pointer2 to set BRAM_Rspointer and Dfa_RsValid
-- Dfa_RsValid tells if the Rs register is present in any of the 8 checkpoints or not
-- BRAM_Rspointer gives which checkpoint it is present in. Set it to "000" by default.
-- Task 4: Update Committed_Rslist when a register-writing instruction is committed
if (Dis_InstValid = '1') then
if (Dis_CfcRegWrite = '1') then --setting the DFA bit in the active checkpoint corresponding to Rd Addr location
Cfc_RsList(conv_integer(Head_Pointer & Dis_CfcRdAddr)) <= Dis_CfcNewRdPhyAddr;
end if;
Cfc_RsList_temp <= Cfc_RsList(conv_integer(BRAM_RsPointer & Dis_CfcRsAddr)); --concatenating the pointer & logical Rs address value to read BRAM
Committed_RsList_temp <= Committed_RsList(conv_integer(Dis_CfcRsAddr));
end if;
end if;
end process;
process (Dfa_RsValid, Cfc_RsList_temp, Committed_RsList_temp)--mux to select between the checkpoint value or committed value
begin
if (Dfa_RsValid = '1') then
Cfc_RsPhyAddr <= Cfc_RsList_temp;
else
Cfc_RsPhyAddr <= Committed_RsList_temp;
end if;
end process;
-- Task 5: same process as above for finding the latest value of Rt
Dispatch_RtRead_Process: process(Clk,Resetb)
variable found_Rt1, found_Rt2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RtPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RtList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
end if;
end process;
process (Dfa_RtValid, Cfc_RtList_temp, Committed_RtList_temp)
begin
if (Dfa_RtValid = '1') then
Cfc_RtPhyAddr <= Cfc_RtList_temp;
else
Cfc_RtPhyAddr <= Committed_RtList_temp;
end if;
end process;
-- Task 6: same process as above for finding the latest value of Rd
Dispatch_RdRead_Process: process(Clk,Resetb)
variable found_Rd1, found_Rd2: std_logic;
variable BRAM_pointer1, BRAM_pointer2: integer;
variable BRAM_RdPointer: std_logic_vector (2 downto 0);
begin
if (Resetb = '0') then
Committed_RdList <= ("000000", "000001", "000010", "000011", "000100", "000101", "000110", "000111",
"001000", "001001", "001010", "001011", "001100", "001101", "001110", "001111",
"010000", "010001", "010010", "010011", "010100", "010101", "010110", "010111",
"011000", "011001", "011010", "011011", "011100", "011101", "011110", "011111");
elsif (Clk'event and Clk = '1') then
end if;
end process;
process (Dfa_RdValid, Cfc_RdList_temp, Committed_RdList_temp)
begin
if (Dfa_RdValid = '1') then
Cfc_RdPhyAddr <= Cfc_RdList_temp;
else
Cfc_RdPhyAddr <= Committed_RdList_temp;
end if;
end process;
end cfc_arch;
|
gpl-2.0
|
610abb1d04728acabfab7b53eb909993
| 0.657359 | 3.659401 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/incrCuenta3bits.vhd
| 1 | 2,057 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: incrCuenta3bits.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity incrCuenta3bits is
Port ( num_in : in STD_LOGIC_VECTOR (2 downto 0);
num_out : out STD_LOGIC_VECTOR (2 downto 0));
end incrCuenta3bits;
architecture arq of incrCuenta3bits is
begin
p_outputs: process(num_in)
begin
if num_in = "000" then
num_out <= "001";
elsif num_in = "001" then
num_out <= "010";
elsif num_in = "010" then
num_out <= "011";
elsif num_in = "011" then
num_out <= "100";
elsif num_in = "100" then
num_out <= "101";
elsif num_in = "101" then
num_out <= "110";
elsif num_in = "110" then
num_out <= "111";
else
num_out <= "000";
end if;
end process p_outputs;
end arq;
|
gpl-3.0
|
2546c7484b1ae33c99fa194cf53e2588
| 0.571706 | 3.85206 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/asyn_fifo_distrib_64.vhd
| 1 | 3,440 |
----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. --
----------------------------------------------------------------------
-- You must compile the wrapper file asyn_fifo_distrib_64.vhd when simulating
-- the core, asyn_fifo_distrib_64. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Express, Exemplar and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;
ENTITY asyn_fifo_distrib_64 IS
port (
din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
almost_full: OUT std_logic;
almost_empty: OUT std_logic;
wr_count: OUT std_logic_VECTOR(3 downto 0);
rd_count: OUT std_logic_VECTOR(3 downto 0));
END asyn_fifo_distrib_64;
ARCHITECTURE asyn_fifo_distrib_64_a OF asyn_fifo_distrib_64 IS
component wrapped_asyn_fifo_distrib_64
port (
din: IN std_logic_VECTOR(15 downto 0);
wr_en: IN std_logic;
wr_clk: IN std_logic;
rd_en: IN std_logic;
rd_clk: IN std_logic;
ainit: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
almost_full: OUT std_logic;
almost_empty: OUT std_logic;
wr_count: OUT std_logic_VECTOR(3 downto 0);
rd_count: OUT std_logic_VECTOR(3 downto 0));
end component;
-- Configuration specification
for all : wrapped_asyn_fifo_distrib_64 use entity XilinxCoreLib.async_fifo_v3_0(behavioral)
generic map(
c_wr_count_width => 4,
c_has_rd_err => 0,
c_data_width => 16,
c_has_almost_full => 1,
c_rd_err_low => 0,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_fifo_depth => 63,
c_rd_count_width => 4,
c_has_wr_err => 0,
c_has_almost_empty => 1,
c_rd_ack_low => 0,
c_has_wr_count => 1,
c_use_blockmem => 0,
c_has_rd_ack => 0,
c_has_rd_count => 1,
c_wr_err_low => 0,
c_enable_rlocs => 0);
BEGIN
U0 : wrapped_asyn_fifo_distrib_64
port map (
din => din,
wr_en => wr_en,
wr_clk => wr_clk,
rd_en => rd_en,
rd_clk => rd_clk,
ainit => ainit,
dout => dout,
full => full,
empty => empty,
almost_full => almost_full,
almost_empty => almost_empty,
wr_count => wr_count,
rd_count => rd_count);
END asyn_fifo_distrib_64_a;
-- synopsys translate_on
|
gpl-3.0
|
bfabc87e9fa3a1b8df151037731f74b5
| 0.607849 | 3.254494 | false | false | false | false |
csrhau/sandpit
|
VHDL/data_types/test_slv.vhdl
| 1 | 1,313 |
library ieee;
use ieee.std_logic_1164.all;
entity test_slv is
end test_slv;
architecture behavioural of test_slv is
signal input : std_logic_vector(5 downto 0);
function popcnt(vector : std_logic_vector) return natural is
variable result : natural range 0 to vector'length := 0;
begin
for i in vector'range loop
if vector(i) = '1' then
result := result + 1;
end if;
end loop;
return result;
end function popcnt;
signal test_offsets_1 : std_logic_vector (7 downto 0) := "11110000";
signal test_offsets_2 : std_logic_vector (8 downto 1);
begin
process
variable result : natural range 0 to 6;
begin
input <= "000000";
result := popcnt(input);
assert result = 0
report "Result should be 0 for 000000" severity error;
input <= "000001";
wait for 1 ns;
result := popcnt(input);
assert result = 1
report "Result should be 1 for 000001" severity error;
input <= "111110";
wait for 1 ns;
result := popcnt(input);
assert result = 5
report "Result should be 5 for 111110" severity error;
test_offsets_2 <= test_offsets_1;
wait for 1 ns;
assert test_offsets_2 = "11110000"
report "can mix and match non-zero offsets" severity error;
wait;
end process;
end behavioural;
|
mit
|
7c096231134f8f6def2d987ba4cb9021
| 0.648896 | 3.783862 | false | true | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Move_FIFO_4KB/example_design/Move_FIFO_4KB_top.vhd
| 1 | 5,222 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Move_FIFO_4KB_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity Move_FIFO_4KB_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end Move_FIFO_4KB_top;
architecture xilinx of Move_FIFO_4KB_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component Move_FIFO_4KB is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(8-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : Move_FIFO_4KB PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
5d3f38b1791fcbeef1e4f0759cfce0d7
| 0.511107 | 4.75592 | false | false | false | false |
BBN-Q/APS2-TDM
|
testbenches/ApsCmdConstants.vhd
| 1 | 2,230 |
-- ApsCmdConstants.vhd
--
-- This provides menmonic definitions for the command word fields
--
--
-- REVISIONS
--
-- 7/9/2013 CRJ
-- Created
--
-- 8/13/2013 CRJ
-- Initial release
--
-- END REVISIONS
--
library ieee;
use ieee.std_logic_1164.all;
package ApsCmdConstants is
-- Constants used in the command packets from the host
-- Command Word Format:
--
-- D<31> ACK Flag
-- D<30> SEQ Error Flag
-- D<29> Channel select 0/1
-- D<28> R/!W
-- D<27:24> CMD<3:0>, Command
-- D<23:16> MODE from host (command mode) / STAT from APS (command completion status)
-- D<15:0> CNT<15:0>, 32-bit read or write count. For writes, CNT data words follow the address
-- Define the bit fields in the command word
constant APS_ACK_BIT : natural := 31;
constant APS_SEQ_BIT : natural := 30;
constant APS_CHAN_BIT : natural := 29;
constant APS_RW_BIT : natural := 28;
constant APS_NOACK_BIT : natural := 27;
-- Define the bit ranges in the command word
subtype APS_CMD_RANGE is natural range 26 downto 24;
subtype APS_MODE_RANGE is natural range 23 downto 16;
subtype APS_STAT_RANGE is natural range 23 downto 16;
subtype APS_CNT_RANGE is natural range 15 downto 0;
-- Define the bit ranges in the User CIF
subtype CIF_CNT_RANGE is natural range 15 downto 0;
subtype CIF_MODE_RANGE is natural range 23 downto 16;
subtype CIF_ADDR_RANGE is natural range 56 downto 25;
constant CIF_RW_BIT : natural := 24;
-- Define the bit ranges in the User COF
subtype COF_CNT_RANGE is natural range 15 downto 0;
subtype COF_STAT_RANGE is natural range 23 downto 16;
-- Define the command values
constant APS_PKT_RESET : std_logic_vector(2 downto 0) := "000";
constant APS_PKT_USRIO : std_logic_vector(2 downto 0) := "001";
constant APS_PKT_EPIO : std_logic_vector(2 downto 0) := "010";
constant APS_PKT_CFGIO : std_logic_vector(2 downto 0) := "011";
constant APS_PKT_CFGRUN : std_logic_vector(2 downto 0) := "100";
constant APS_PKT_CFGDAT : std_logic_vector(2 downto 0) := "101";
constant APS_PKT_CFGCTL : std_logic_vector(2 downto 0) := "110";
constant APS_PKT_STAT : std_logic_vector(2 downto 0) := "111";
end package ApsCmdConstants;
|
mpl-2.0
|
352e5a58df4ed1c158b74387b954934f
| 0.67713 | 3.227207 | false | false | false | false |
lenchv/fpga-lab.node.js
|
vhdl/ps2/web_ps2_rx.vhd
| 1 | 4,400 |
-- Иммитация передачи байта от устройства к хосту по протоколу PS/2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity web_ps2_rx is
generic (
constant MAIN_FREQ: positive := 50_000_000;
constant FREQ_DIVIDER: positive := 20_000 -- 10 kHz, clock PS/2 = 10 - 16.7 kHz
);
port (
clk, reset: in std_logic;
ps2d, ps2c: out std_logic;
rx_en: in std_logic;
rx_done: out std_logic;
data_i: in std_logic_vector(7 downto 0)
);
end web_ps2_rx;
architecture Behavioral of web_ps2_rx is
constant max_ps2_counter : natural := MAIN_FREQ / FREQ_DIVIDER;
signal ps2_counter: natural range 0 to max_ps2_counter := 0; -- счетчик для генерации частоты устройства
type state_type is (s_wait, s_data, s_end);
signal state: state_type := s_wait;
signal bit_count: unsigned(3 downto 0); -- bit counter - data + parity + stop
signal buff: std_logic_vector(9 downto 0);
signal ris_edge, fall_edge, rx_en_edge: std_logic;
signal rx_en_reg: std_logic_vector(1 downto 0);
begin
inst_ps2_clk: entity work.web_ps2_clk
port map(
clk => clk,
reset => reset,
en => rx_en,
ps2_clk => ps2c,
rising => ris_edge,
falling => fall_edge
);
proc_detect_en: process(clk, reset)
begin
if reset = '1' then
rx_en_reg <= (others => '0');
elsif rising_edge(clk) then
rx_en_reg <= rx_en_reg(0) & rx_en;
end if;
end process;
rx_en_edge <= '1' when rx_en_reg(1) = '0' and rx_en_reg(0) = '1' else '0';
proc_rx: process(clk, reset)
begin
if reset = '1' then
state <= s_wait;
bit_count <= (others => '0');
rx_done <= '0';
elsif rising_edge(clk) then
rx_done <= '0';
case state is
when s_wait =>
-- ждем включения
if rx_en_edge = '1' then
state <= s_data;
buff <= '1' -- stop bit
& (not (data_i(0) xor data_i(1) xor data_i(2) xor data_i(3) -- parity
xor data_i(4) xor data_i(5) xor data_i(6) xor data_i(7)))
& data_i; -- data
ps2d <= '0'; -- start bit
bit_count <= "1001";
end if;
when s_data =>
-- по фронту клока пс/2 передаем бит данных
if ris_edge = '1' then
ps2d <= buff(0); -- data bit
buff <= '0' & buff(9 downto 1);
if bit_count = "000" then
state <= s_end;
else
bit_count <= bit_count - 1;
end if;
end if;
when s_end =>
if fall_edge = '1' then
rx_done <= '1';
state <= s_wait;
end if;
end case;
end if;
end process;
end Behavioral;
--------------------------------------------------------------------------------------------------------------------------------------------------
-- IDLE 100us IDLE
-- | | | |
-- ____|______| ____| ____ ____ ____ ____ ____ ____ ____ ____ ____ _|___
-- CLK | |____| |____| |____| |____| |____| |____| |____| |____| |____| |____| |____| |
-- ____| | ___|____ ________ ________ ________ ________ ________ ________ ________ ________ __________|____
-- DATA |______| S __<___|D0 _><___ D1 _><___ D2 _><___ D3 _><__ D4 __><__ D5 __><__ D6 __><__ D7 __><___ P __>/ S |
-- | | | |
-- _________________________________________________________________________________________________________________
-- TX_EN ____| |___
---------------------------------------------------------------------------------------------------------------------------------------------------
|
mit
|
edd3d3366861c74e8a68fbb0eeee98f9
| 0.359888 | 3.763668 | false | false | false | false |
BBN-Q/APS2-TDM
|
src/TriggerOutLogic.vhd
| 1 | 3,308 |
-- TriggerOutLogic.vhd
--
-- Serializes the triggers written to the input FIFO by the User Logic.
-- The FIFO allows the trigger output logic and the User Logic clock to have independent clocks.
--
-- REVISIONS
--
-- 3/6/2014 CRJ
-- Created
--
-- 7/30/2014 CRJ
-- Updated comments
--
-- 7/31/2014 CRJ
-- Modified to allow use of I/O buffer for loopback
--
-- 8/5/2014 CRJ
-- Unmodified
--
-- 8/28/2014 CRJ
-- Changed back to 0xF0 clock, since now bit slipping in logic versus the input cell
--
-- END REVISIONS
--
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TriggerOutLogic is
port
(
-- These clocks are usually generated from SYS_MMCM.
CLK_100MHZ : in std_logic; -- 100 MHz trigger output serial clock, must be from same MMCM as CLK_400MHZ
CLK_400MHZ : in std_logic; -- 400 MHz DDR serial output clock
RESET : in std_logic; -- Asynchronous reset for the trigger logic
TRIG_TX : in std_logic_vector(7 downto 0); -- Current trigger value, synchronous to CLK_100MHZ
TRIG_VALID : in std_logic; -- Valid flag for TRIG_TX
TRIG_CLKP : out std_logic; -- 100MHz Serial Clock
TRIG_CLKN : out std_logic;
TRIG_DATP : out std_logic; -- 800 Mbps Serial Data
TRIG_DATN : out std_logic
);
end TriggerOutLogic;
architecture behavior of TriggerOutLogic is
signal ClkOutP : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal ClkOutN : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal DatOutP : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal DatOutN : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal DataOut : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal SerTrigIn : std_logic_vector(7 downto 0);
signal SerTrigOut : std_logic_vector(7 downto 0);
signal SerDatOut : std_logic_vector(15 downto 0);
signal dTRIG_VALID : std_logic;
begin
-- Connect serial output vectors to output pins
TRIG_CLKP <= ClkOutP(0);
TRIG_CLKN <= ClkOutN(0);
TRIG_DATP <= DatOutP(0);
TRIG_DATN <= DatOutN(0);
-- Data sent externally LSB first, because the SelectIO wizard IP internally
-- assigns the LSB to D1 of the OSERDESE2.
-- Fixed 0xF0 clock pattern.
SCLK1 : entity work.SEROUT8
port map
(
data_out_to_pins_p => ClkOutP,
data_out_to_pins_n => ClkOutN,
clk_in => CLK_400MHZ,
clk_div_in => CLK_100MHZ,
data_out_from_device => "11110000", -- Fixed clock data pattern, sent LSB first.
io_reset => RESET
);
SDAT1 : entity work.SEROUT8
port map
(
data_out_to_pins_p => DatOutP,
data_out_to_pins_n => DatOutN,
clk_in => CLK_400MHZ,
clk_div_in => CLK_100MHZ,
data_out_from_device => SerTrigOut, -- Trigger Byte
io_reset => RESET
);
-- One level of input data pipelining to allow for easier routing
process(CLK_100MHZ, RESET)
begin
if RESET = '1' then
SerTrigIn <= (others => '0');
dTRIG_VALID <= '0';
elsif rising_edge(CLK_100MHZ) then
SerTrigIn <= TRIG_TX;
dTRIG_VALID <= TRIG_VALID;
end if;
end process;
-- Only present non-zero data when there is a valid input
-- The output is ALWAYS writing. When there are not triggers, it writes 0xFF
SerTrigOut <= SerTrigIn when dTRIG_VALID = '1' else x"ff";
end behavior;
|
mpl-2.0
|
4dbdf1c8762f0f1a7453dee9eb0eb7e5
| 0.655381 | 3.344793 | false | false | false | false |
PRETgroup/goFB
|
goFB/templates/vhdl/_entityFB.vhd
| 1 | 1,696 |
{{define "_entityFB"}}
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$specialIO := getSpecialIO $block .Blocks}}
entity {{$block.Name}} is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
{{if $block.EventInputs}}
--input events
{{range $index, $event := $block.EventInputs}}{{$event.Name}}_eI : in std_logic := '0';
{{end}}{{end}}
{{if $block.EventOutputs}}
--output events
{{range $index, $event := $block.EventOutputs}}{{$event.Name}}_eO : out std_logic;
{{end}}{{end}}
{{if $block.InputVars}}
--input variables
{{range $index, $var := $block.InputVars}}{{$var.Name}}_I : in {{getVhdlType $var.Type}} := {{if eq (getVhdlType $var.Type) "std_logic"}}'0'{{else}}(others => '0'){{end}}; --type was {{$var.Type}}
{{end}}{{end}}
{{if $block.OutputVars}}
--output variables
{{range $index, $var := $block.OutputVars}}{{$var.Name}}_O : out {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}
{{if $block.BasicFB}}{{if $specialIO.InternalVars}}
--special emitted internal vars for I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if variableIsTOPIO_IN $var}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{else if $block.CompositeFB}}{{if $specialIO.InternalVars}}
--special emitted internal variables for child I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if variableIsTOPIO_IN $var}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{end}}
--for done signal
done : out std_logic
);
end entity;
{{end}}
|
mit
|
1d6a53e213b452a81d491b4781154737
| 0.616745 | 3.146568 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/read_data_fifo/simulation/fg_tb_pkg.vhd
| 2 | 11,537 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT read_data_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
203122ea6df139216a0736a963432ea1
| 0.503164 | 3.917487 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_FIFO/simulation/fg_tb_pkg.vhd
| 1 | 11,386 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT WR_FLASH_FIFO_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
7a84a90115038d62beab77f1a959eae1
| 0.503074 | 3.92215 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RECV_REQ_QUEUE/simulation/fg_tb_pkg.vhd
| 1 | 11,326 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT RECV_REQ_QUEUE_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
e6c110dbe6d365a24d2f3332fae74175
| 0.504503 | 3.931274 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_summation.vhd
| 3 | 6,986 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"00002020_00001820_01401020_0080F820", -- Loc 0C, 08, 04, 00
X"00000020_00003820_00003020_00002820", -- Loc 1C, 18, 14, 10
X"00C53020_8C850000_007F2019_005F3819", -- Loc 2C, 28, 24, 20
X"1000FFF9_10620001_00611820_ACE60000", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- 0080F820 -- ADD $31, $4, $0 -- $31 = 4
-- 01401020 -- ADD $2, $10, $0 -- num_of_items = 10
-- 00001820 -- ADD $3, $0, $0 -- read_index = 0
-- 00002020 -- ADD $4, $0, $0 -- read_addr = 0
-- 00002820 -- ADD $5, $0, $0 -- read_val = 0
-- 00003020 -- ADD $6, $0, $0 -- sum = 0
-- 00003820 -- ADD $7, $0, $0 -- write_addr = 0
-- 00000020 -- noop
-- 005F3819 -- MUL $7, $2, $31 -- write_addr = num_of_items * 4
-- 007F2019 -- MUL $4, $3, $31 -- read_addr = index * 4
-- 8C850000 -- LW $5 ,0( $4) -- read_val = M(read_addr)
-- 00C53020 -- Add $6, $6, $5 -- sum = sum + value
-- ACE60000 -- SW $6 ,0( $7) -- M(write_addr) = sum
-- 00611820 -- Add $3, $3, $1 -- index++
-- 10620001 -- BEQ $3 ,$2 ,1 -- (index = num_of_items)?
-- 1000FFF9 -- BEQ $0 ,$0 ,-7 -- jmp
-- 00000020 -- noop
--
-- REGISTERS
-- $0 --> 0
-- $1 --> 1
-- $2 --> 10 num_of_items
-- $3 --> 0 read index
-- $4 --> 0 read addr
-- $5 --> 0 mem_value
-- $6 --> 0 sum
-- $7 --> 0 write addr (0 for version 1, 40 for version 2)
-- $31 --> 4 for address calculation
--
-- MEM
-- Put first n numbers starting from the beginning of the memory.
-- You will get the sum of them at n+1
|
gpl-2.0
|
7dc07b11c7465b3fbc0e329a4290ac89
| 0.652734 | 2.903574 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/rom.vhd
| 1 | 2,450 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: rom.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tablero_rom is
port (
clk: in std_logic;
x : in std_logic_vector(2 downto 0);
y : in std_logic_vector(2 downto 0);
rgb: out std_logic_vector(2 downto 0)
);
end tablero_rom;
architecture arq of tablero_rom is
type memory_slv is array (0 to 7) of std_logic_vector(2 downto 0);
type memory_img is array (0 to 7) of memory_slv;
constant rom_img : memory_img := (
("001","001","001","001","001","001","001","001"),
("001","000","000","000","000","000","000","001"),
("001","000","001","000","000","001","000","001"),
("001","000","000","000","000","000","000","001"),
("001","000","000","000","001","000","000","001"),
("001","000","001","000","000","001","000","001"),
("001","000","000","000","000","000","000","001"),
("001","001","001","001","001","001","001","001")
);
begin
process(clk,x,y )
begin
if clk'event and clk='1' then
rgb(2 downto 0) <= rom_img(to_integer(unsigned(y)))(to_integer(unsigned(x)))(2 downto 0);
end if;
end process;
end arq;
|
gpl-3.0
|
ff391fad0e10f60482a22a620313a453
| 0.56 | 3.651267 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_send_fifo/example_design/pcie_data_send_fifo_top.vhd
| 1 | 6,001 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_data_send_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_data_send_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_data_send_fifo_top;
architecture xilinx of pcie_data_send_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_data_send_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_data_send_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
1e633970d4f8b47b773fb0df0bfb6827
| 0.506749 | 4.659161 | false | false | false | false |
csrhau/sandpit
|
VHDL/flexible_single_port_ram/test_ram.vhdl
| 1 | 1,713 |
library ieee;
use ieee.std_logic_1164.all;
entity test_ram is
end test_ram;
architecture behavioural of test_ram is
component RAM is
port (
clock : in std_logic;
write_enable : in std_logic;
address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector
);
end component RAM;
signal write_enable : std_logic;
signal address : std_logic_vector(9 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
-- Just to prove types don't conflict
signal address2 : std_logic_vector(5 downto 0);
signal data_in2 : std_logic_vector(1 downto 0);
signal data_out2 : std_logic_vector(1 downto 0);
signal period: time := 10 ns;
signal clock : std_logic := '0';
signal finished : std_logic := '0';
begin
clock <= not clock after period/2 when finished='0';
ramcell : RAM port map (clock, write_enable, address, data_in, data_out);
ramcell2 : RAM port map (clock, write_enable, address2, data_in2, data_out2);
process
begin
address <= "0000000000";
address2 <= "000000";
write_enable <= '1';
data_in <= "01010101";
data_in2 <= "01";
wait for period;
assert data_out = "00000000"
report "RAM should be zero initialized" severity error;
write_enable <= '0';
data_in <= "11110000";
wait for period;
assert data_out = "01010101"
report "data should have been written and returned" severity error;
wait for period;
assert data_out = "01010101"
report "data should not be overwritten with write_enable false" severity error;
finished <= '1';
wait;
end process;
end behavioural;
|
mit
|
a01d19e9eb8dd78543d4d5f79c8dadd2
| 0.652656 | 3.561331 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/ls_buffer_ram_reg_array.vhd
| 1 | 3,122 |
-------------------------------------------------------------------------------
-- Design : Register array acting as data cache
-- Project : Tomasulo Processor
-- Author : Rohit Goel
-- Company : University of Southern California
-- Following is the VHDL code for a dual-port RAM with a write clock.
-- There is no read clock. The read port is not a clocked port.
-- This is actually a register array. with no input or output registers.
-- ===================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ls_buffer_ram_reg_array is
generic (ADDR_WIDTH: integer := 6; DATA_WIDTH: integer := 32);
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dia : in std_logic_vector (DATA_WIDTH-1 downto 0);
addrb : in std_logic_vector (ADDR_WIDTH-1 downto 0);
dob : out std_logic_vector (DATA_WIDTH-1 downto 0);
rea : in std_logic ;
mem_wri : out std_logic ;
mem_exc : out std_logic ;
mem_read : out std_logic
-- modified by kapil
--addrc : in std_logic_vector(ADDR_WIDTH-1 downto 0);
--doc : out std_logic_vector(DATA_WIDTH-1 downto 0)
-- end modified by kapil
);
end entity ls_buffer_ram_reg_array;
architecture syn of ls_buffer_ram_reg_array is
type ram_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM : ram_type :=
( X"0000_FFFF", X"0000_0010", X"0000_0020", X"0000_0030", -- 00 04 08 0c
X"0000_0040", X"0000_0050", X"0000_0060", X"0000_0070",
X"0000_0080", X"0000_0001", X"0000_0002", X"0000_00B0",
X"0000_00C0", X"0000_00D0", X"0000_00E0", X"0000_00F0",
X"0000_0100", X"0000_0110", X"0000_0120", X"0000_0130",
X"0000_0140", X"0000_0150", X"0000_0160", X"0000_0170",
X"0000_0180", X"0000_0190", X"0000_01A0", X"0000_01B0",
X"0000_01C0", X"0000_01D0", X"0000_01E0", X"0000_01F0",
X"0000_0200", X"0000_0210", X"0000_0220", X"0000_0230",
X"0000_0240", X"0000_0250", X"0000_0260", X"0000_0270",
X"0000_0280", X"0000_0290", X"0000_02A0", X"0000_02B0",
X"0000_02C0", X"0000_02D0", X"0000_02E0", X"0000_02F0",
X"0000_0300", X"0000_0310", X"0000_0320", X"0000_0330",
X"0000_0340", X"0000_0350", X"0000_0360", X"0000_0370",
X"0000_0380", X"0000_0390", X"0000_03A0", X"0000_03B0",
X"0000_03C0", X"0000_03D0", X"0000_03E0", X"0000_03F0"
);
-- signal read_addrb : std_logic_vector(1 downto 0) := "00";
--signal doc_async : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
process (clka)
begin
if (clka'event and clka = '1') then
mem_read <= rea ;
dob <= RAM(conv_integer(addrb));
mem_wri <= '0' ;
mem_exc <= '0';
if (wea = '1') then
RAM(conv_integer(addra)) <= dia;
mem_wri <= '1' ;
mem_exc <= '0';
else
end if;
end if;
end process;
--doc <= RAM(conv_integer(addrc)); -- not a clocked-port
end architecture syn;
-----------------------------------------------------------------------------
|
gpl-2.0
|
94ee1537d0cdd95facd9d30c006d39e3
| 0.569186 | 2.789991 | false | false | false | false |
tuura/fantasi
|
dependencies/accumulator.vhdl
| 1 | 1,241 |
-- Generic accumulator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Generic_accumulator IS
GENERIC (N : integer := 8);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N downto 0));
END Generic_accumulator;
ARCHITECTURE structural OF Generic_accumulator IS
COMPONENT Generic_register IS
GENERIC (N : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N-1 downto 0));
END COMPONENT;
SIGNAL sum : std_logic_vector(N downto 0);
SIGNAL data_out : std_logic_vector(N downto 0);
BEGIN
sum <= ('0' & DIN) + (data_out);
REG_ACCUMULATOR: Generic_register
GENERIC MAP( N + 1 )
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN,
DIN => sum,
DOUT => data_out);
DOUT <= data_out;
END structural;
|
mit
|
bae867659ba463851544c341e1b76a43
| 0.529412 | 3.495775 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_data_send_fifo/simulation/fg_tb_synth.vhd
| 1 | 11,826 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_data_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
3d319189c36f6df7a5bc0d7b88d4655c
| 0.45586 | 3.972455 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/nueva_pos_rand_async.vhd
| 1 | 5,003 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: nueva_pos_rand_async.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nueva_pos_rand_async is
Port ( up_pos : in STD_LOGIC_VECTOR (2 downto 0);
dw_pos : in STD_LOGIC_VECTOR (2 downto 0);
rg_pos : in STD_LOGIC_VECTOR (2 downto 0);
lf_pos : in STD_LOGIC_VECTOR (2 downto 0);
my_x : in STD_LOGIC_VECTOR (2 downto 0);
my_y : in STD_LOGIC_VECTOR (2 downto 0);
new_x : out STD_LOGIC_VECTOR (2 downto 0);
new_y : out STD_LOGIC_VECTOR (2 downto 0);
bt_rand: in std_logic_vector(1 downto 0)
);
end nueva_pos_rand_async;
architecture arq of nueva_pos_rand_async is
signal rand_num: std_logic_vector(1 downto 0);
signal new_pos_in: std_logic_vector(5 downto 0);
signal pos_valida: std_logic;
signal my_y_add1: std_logic_vector(2 downto 0);
signal my_x_add1: std_logic_vector(2 downto 0);
signal my_y_sub1: std_logic_vector(2 downto 0);
signal my_x_sub1: std_logic_vector(2 downto 0);
COMPONENT incrCuenta3bits
PORT(
num_in : IN std_logic_vector(2 downto 0);
num_out : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
COMPONENT decrCuenta3bits
PORT(
num_in : IN std_logic_vector(2 downto 0);
num_out : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
begin
Inst_incrCuenta3bits_x: incrCuenta3bits PORT MAP(
num_in => my_x,
num_out => my_x_add1
);
Inst_incrCuenta3bits_y: incrCuenta3bits PORT MAP(
num_in => my_y,
num_out => my_y_add1
);
Inst_decrCuenta3bits_x: decrCuenta3bits PORT MAP(
num_in => my_x,
num_out => my_x_sub1
);
Inst_decrCuenta3bits_y: decrCuenta3bits PORT MAP(
num_in => my_y,
num_out => my_y_sub1
);
-- Conexión de señales
---------------------------------------------------------
rand_num <= bt_rand;
new_x <= new_pos_in(2 downto 0);
new_y <= new_pos_in(5 downto 3);
-- Equivalencias entre los números aleatorios y la dirección de desplazamiento:
-- 00 -> Mueve hacia arriba
-- 01 -> Mueve hacia abajo
-- 10 -> Mueve hacia la derecha
-- 11 -> Mueve hacia la izquierda
-- ¿Es válida la dirección de desplazamiento aleatoria generada?
--------------------------------------------------------
p_pos_valida: process(rand_num, up_pos, dw_pos, rg_pos, lf_pos)
begin
-- Si me muevo hacia arriba y no hay pared:
if rand_num = "00" and up_pos = "000" then
pos_valida <= '1';
-- Si me muevo hacia abajo y no hay pared:
elsif rand_num = "01" and dw_pos = "000" then
pos_valida <= '1';
-- Si me muevo hacia la derecha y no hay pared:
elsif rand_num = "10" and rg_pos = "000" then
pos_valida <= '1';
-- Si me muevo hacia la izquierda y no hay pared:
elsif rand_num = "11" and lf_pos = "000" then
pos_valida <= '1';
-- En cualquier otro caso la dirección de desplazamiento no es válida:
else
pos_valida <= '0';
end if;
end process p_pos_valida;
-- Traducimos el número aleatorio en la posicion equivalente dentro del mapa:
---------------------------------------------------------
p_traduce: process(rand_num, my_x, my_y, pos_valida, my_y_add1, my_y_sub1, my_x_add1, my_x_sub1)
begin
if pos_valida = '1' then
if rand_num = "00" then --arriba
new_pos_in <= my_y_add1 & my_x;
elsif rand_num = "01" then --abajo
new_pos_in <= my_y_sub1 & my_x;
elsif rand_num = "10" then --der
new_pos_in <= my_y & my_x_add1;
else --izq
new_pos_in <= my_y & my_x_sub1;
end if;
else
new_pos_in <= my_y & my_x; -- Si no es valida nos mantenemos donde estamos.
end if;
end process p_traduce;
end arq;
|
gpl-3.0
|
94bbc24459f8cf00f622f74e947e920f
| 0.579452 | 3.248701 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_jal_jr_factorial.vhd
| 3 | 8,449 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- $0 : 0
-- $1 : 1
-- $2 : 2
-- $3 : 3
-- $4 : 4
-- $5 : 5
-- $29: contains fixed bottom of stack for $31 values
-- The program calculates factorial of the number n
-- addi $4, $0, n ---put factorial candidate in $4
-- addi $3, $0, n ---put factorial candidate in $3
-- slt $5, $4, $2 ---check if no. is zero or one
-- bne $5, $1, skiptwo ---go ahead if no. is not 0 or 1
-- add $5, $1, $0 ---no. is 0 or 1, ans is 1
-- jump exit --- exit the code. $5 has final ans.
-- skiptwo: jal subroutine ---calculate factorial. goto function.
-- add $5, $3, $0 ---store final ans. in $5
-- exit: jump exit ---jump here infinitely
-- subroutine:
-- addi $29, $29, -4 --decrement address
-- sw $31,0($29) --put contents of $31 into location pointed by $29
-- sub $4, $4, $1 ---$4=$4 - 1
-- mul $3, $3, $4 ---$3=$3 * $4
-- beq $1, $4, outofloop ---check if $4 has reached 1
-- jal subroutine; --- if $4 /= 1, do 1 more iteration
-- outofloop: lw $31,0($29)
-- addi $29, $29, 4
-- jr $31 ---start exiting the loop
---------------------------------------------------
--EXPECTED RESULT
-- The stream calculates factorial 4 and puts the final result in $5.
-- $5 is mapped to physical register 32
-- Thus the final contents of physical register 32 should be 24(d) = 18(h)
---------------------------------------------------
signal mem : mem_type :=
( X"14A10002_0082282A_20030004_20040004", -- Loc 0C, 08, 04, 00 bne_slt_addi_addi
X"00602820_0C000009_08000008_00202820", -- Loc 1C, 18, 14, 10 add_jal_jump_add
X"00812022_AFBF0000_23BDFFFC_08000014", -- Loc 2C, 28, 24, 20 sub_sw_addi_jump
X"8FBF0000_0C000009_10240001_00641819", -- Loc 3C, 38, 34, 30 lw_jal_beq_mul
X"00000020_AC0C0020_03E00008_23BD0004", -- Loc 4C, 48, 44, 40 jr_addi
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
gpl-2.0
|
993735322a2360f63ee7153f45e23255
| 0.625636 | 3.076839 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/incrCuenta8bits_conFin.vhd
| 1 | 3,820 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: incrCuenta8bits_conFin.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity incrCuenta8bits_conFin is
Port ( num_in : in STD_LOGIC_VECTOR (7 downto 0);
num_out : out STD_LOGIC_VECTOR (7 downto 0);
fin: out std_logic
);
end incrCuenta8bits_conFin;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of incrCuenta8bits_conFin is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal aux: std_logic_vector(6 downto 0);
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT adder1bit_comb
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
adder_0: adder1bit_comb port map(
A => num_in(0),
B => '1',
Cin => '0',
Z => num_out(0),
Cout => aux(0)
);
adder_1: adder1bit_comb port map(
A => num_in(1),
B => aux(0),
Cin => '0',
Z => num_out(1),
Cout => aux(1)
);
adder_2: adder1bit_comb port map(
A => num_in(2),
B => aux(1),
Cin => '0',
Z => num_out(2),
Cout => aux(2)
);
adder_3: adder1bit_comb port map(
A => num_in(3),
B => aux(2),
Cin => '0',
Z => num_out(3),
Cout => aux(3)
);
adder_4: adder1bit_comb port map(
A => num_in(4),
B => aux(3),
Cin => '0',
Z => num_out(4),
Cout => aux(4)
);
adder_5: adder1bit_comb port map(
A => num_in(5),
B => aux(4),
Cin => '0',
Z => num_out(5),
Cout => aux(5)
);
adder_6: adder1bit_comb port map(
A => num_in(6),
B => aux(5),
Cin => '0',
Z => num_out(6),
Cout => aux(6)
);
adder_7: adder1bit_comb PORT MAP(
A => num_in(7),
B => aux(6),
Cin => '0',
Z => num_out(7),
Cout => fin
);
end rtl;
|
gpl-3.0
|
a5d4694007ddf8fd359961b0c929bec9
| 0.428235 | 3.911885 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/read_data_fifo/simulation/fg_tb_dgen.vhd
| 7 | 5,099 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
|
gpl-2.0
|
bba653d8f0762c0d46bea0c0c6ca8f16
| 0.591292 | 3.986708 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/gc_command_fifo/simulation/fg_tb_synth.vhd
| 1 | 10,126 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(29-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(29-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(29-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(29-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 29,
C_DOUT_WIDTH => 29,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 29,
C_DIN_WIDTH => 29,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 29,
C_DIN_WIDTH => 29,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : gc_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
261fac646b45bd538863a423dac4a338
| 0.45714 | 4.172229 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_sim/megatb/i_fetch_test_stream_min_finder.vhd
| 3 | 8,076 |
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
-- DATE OF LAST RIVISON: 07/28/08 BY PRASHESH
-- THE GIVEN PROGRAM FINDS MINIMUM NUMBER FROM THE FIRST 10 LOCATION OF DATA MEM
-- ADD $31, $0, $0 --$31 is set to X?00000000?.
-- ADD $11, $10, $0 --
-- ADD $30, $14, $30--
-- ADD $10, $0, $0 --
-- LW $2, 0($31) --Content of memory location 0 goes to $2
-- BEQ $A, $B, GOTO2-- $A is counter to track 10 numbers. -- INSTRUCTION WITH LABEL LOOP
-- ADD $31, $31, $4 --$31 is incremented by 4 so it can point to the next memory location
-- LW $3, 0($31) --Content of Memory location 2 goes to $3
-- SLT $5, $3, $2 --Check if ($3) < ($2)
-- ADD $10, $10, $1 --Increment counter $10
-- BEQ $5, $1, GOTO1-- If ($3) < ($2) then
-- JMP LOOP --If ($3) ? ($2) then
-- ADD $2, $3, $0 --Move ($3)-->($2) IF $3< $2 --INSTRUCTION WITH LABEL GOTO1
-- JMP LOOP --Jump to loop
-- SW $2,0($30) --Store ($2) at memory location 11. ($30)-->4 --INSTRUCTION WITH LABEL GOTO2
-- LW $6, 0($16) --Content of memory location 12 goes to $6 --> THIS BRANCH IS NEVER TAKEN
-- BEQ $2, $6, -4 --If ($2) = ($6) then ? this branch is always taken
-- JMP HERE -- LOCATION WITH LABEL HERE
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type :=
(X"00005020_01DEF020_01405820_0000F820", -- Loc 0C, 08, 04, 00
X"8FE30000_03E4F820_114B0008_8FE20000", -- Loc 1C, 18, 14, 10
X"08000005_10A10001_01415020_0062282A", -- Loc 2C, 28, 24, 20
X"8E060000_AFC20000_08000005_00601020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_08000011_1046FFF4", -- Loc 4C, 48, 44, 40
-- a bunch of NOP instructions (ADD $0 $0 $0) to fill the space
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
gpl-2.0
|
5cefe2d23bc534f9a6fde9b0d39d30d3
| 0.644131 | 2.992219 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/ssd_command_fifo/simulation/fg_tb_dverif.vhd
| 35 | 5,486 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fg_tb_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
gpl-2.0
|
70fb8791d97b69ff4b4f0cb036920143
| 0.573642 | 4.090977 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_3/exercise_IQ_LSQ/issueque.vhd
| 1 | 52,814 |
-------------------------------------------------------------------------------
--
-- Design : Issue Queue
-- Project : Tomasulo Processor
-- Author : Vaibhav Dhotre,Prasanjeet Das
-- Company : University of Southern California
-- Updated : 03/15/2010, 07/13/2010
-- TASK : Complete the seven TODO sections
-------------------------------------------------------------------------------
--
-- File : issueque.vhd
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : The issue queue stores instructions and dispatches instructions
-- to the issue block as and when they are ready to be executed
-- Higher priority is given to instructions which has been in the
-- queue for the longest time
-- This is the code for the integer issue queue, the codes for
-- Multiplier queue and divider queue are provided separately
-------------------------------------------------------------------------------
--library declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
-- Entity declaration
entity issueque is
port (
-- Global Clk and dispatch Signals
Clk : in std_logic ;
Resetb : in std_logic ;
-- Information to be captured from the Output of LsBuffer
Lsbuf_PhyAddr : in std_logic_vector(5 downto 0) ;
Lsbuf_RdWrite : in std_logic;
Iss_Lsb : in std_logic;
-- Information to be captured from the Write port of Physical Register file
Cdb_RdPhyAddr : in std_logic_vector(5 downto 0) ;
Cdb_PhyRegWrite : in std_logic;
-- Information from the Dispatch Unit
Dis_Issquenable : in std_logic ;
Dis_RsDataRdy : in std_logic ;
Dis_RtDataRdy : in std_logic ;
Dis_RegWrite : in std_logic;
Dis_RsPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RtPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_NewRdPhyAddr : in std_logic_vector ( 5 downto 0 ) ;
Dis_RobTag : in std_logic_vector ( 4 downto 0 ) ;
Dis_Opcode : in std_logic_vector ( 2 downto 0 ) ;
Dis_Immediate : in std_logic_vector ( 15 downto 0 );
Dis_Branch : in std_logic;
Dis_BranchPredict : in std_logic;
Dis_BranchOtherAddr : in std_logic_vector ( 31 downto 0 );
Dis_BranchPCBits : in std_logic_vector ( 2 downto 0 ) ;
Issque_IntQueueFull : out std_logic ;
Issque_IntQueueTwoOrMoreVacant : out std_logic;
Dis_Jr31Inst : in std_logic;
Dis_JalInst : in std_logic;
Dis_JrRsInst : in std_logic;
-- translate_off
Dis_instruction : in std_logic_vector(31 downto 0);
-- translate_on
-- Interface with the Issue Unit
IssInt_Rdy : out std_logic ;
Iss_Int : in std_logic ;
-- Interface with the Multiply execution unit
Mul_RdPhyAddr : in std_logic_vector(5 downto 0);
Mul_ExeRdy : in std_logic;
Div_RdPhyAddr : in std_logic_vector(5 downto 0);
Div_ExeRdy : in std_logic;
-- Interface with the Physical Register File
Iss_RsPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RtPhyAddrAlu : out std_logic_vector(5 downto 0) ;
-- Interface with the Execution unit (ALU)
Iss_RdPhyAddrAlu : out std_logic_vector(5 downto 0) ;
Iss_RobTagAlu : out std_logic_vector(4 downto 0);
Iss_OpcodeAlu : out std_logic_vector(2 downto 0) ; --add branch information
Iss_BranchAddrAlu : out std_logic_vector(31 downto 0);
Iss_BranchAlu : out std_logic;
Iss_RegWriteAlu : out std_logic;
Iss_BranchUptAddrAlu : out std_logic_vector(2 downto 0);
Iss_BranchPredictAlu : out std_logic;
Iss_JalInstAlu : out std_logic;
Iss_JrInstAlu : out std_logic;
Iss_JrRsInstAlu : out std_logic;
Iss_ImmediateAlu : out std_logic_vector(15 downto 0);
-- translate_off
Iss_instructionAlu : out std_logic_vector(31 downto 0);
-- translate_on
-- Interface with ROB
Cdb_Flush : in std_logic;
Rob_TopPtr : in std_logic_vector ( 4 downto 0 ) ;
Cdb_RobDepth : in std_logic_vector ( 4 downto 0 )
) ;
end issueque;
-- Architecture
architecture behav of issueque is
-- Type declarations
-- Declarations of Register Array for the Issue Queue and Issue Priority Register
type array_8_5 is array (0 to 7) of std_logic_vector(4 downto 0) ; --TAG
type array_8_6 is array (0 to 7) of std_logic_vector(5 downto 0) ; --REG
type array_8_3 is array (0 to 7) of std_logic_vector(2 downto 0) ; --OPCODE
type array_8_32 is array(0 to 7) of std_logic_vector(31 downto 0) ; --BRANCHADDR
type array_8_16 is array(0 to 7) of std_logic_vector(15 downto 0) ; --IMMEDIATEADDR
type array_8_1 is array(0 to 7) of std_logic; --BRANCHPredict
-- Signals declarations.
signal Flush : std_logic_vector(7 downto 0);
signal En : std_logic_vector(7 downto 0);
signal OutSelect : std_logic_vector(2 downto 0);
signal OutSelecttemp : std_logic_vector(7 downto 0);
signal OutSelectEmpty : std_logic_vector(7 downto 0);
signal OutSelectJRrstemp : std_logic_vector(7 downto 0);
signal OutSelectJRrs : std_logic_vector(2 downto 0);
signal OutSelect_result : std_logic_vector(2 downto 0);
signal RtReadyTemp : std_logic_vector(7 downto 0);
signal RsReadyTemp : std_logic_vector(7 downto 0);
signal IssuedRdPhyAddr : std_logic_vector(5 downto 0);
SIGNAL IssuequeBranchPredict : array_8_1;
SIGNAL IssuequeJR : array_8_1;
SIGNAL IssuequeJRrs : array_8_1;
SIGNAL IssuequeJAL : array_8_1;
SIGNAL IssuequeBranch : array_8_1;
SIGNAL IssuequeRegWrite : array_8_1;
SIGNAL IssuequeBranchAddr : array_8_32;
-- translate_off
SIGNAL Issuequeinstruction : array_8_32;
-- translate_on
SIGNAL IssuequeBranchPCBits : array_8_3;
SIGNAL IssuequeRsPhyAddrReg : array_8_6;
SIGNAL IssuequeRtPhyAddrReg : array_8_6;
SIGNAL IssuequeRdPhyAddrReg : array_8_6;
SIGNAL IssuequeOpcodeReg : array_8_3;
SIGNAL IssuequeRobTag : array_8_5;
SIGNAL IssuequeImmediate : array_8_16;
SIGNAL IssuequeRtReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeRsReadyReg : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeInstrValReg : std_logic_vector (7 DOWNTO 0);
SIGNAL Entemp : std_logic_vector (7 DOWNTO 0);
SIGNAL EnJRrstemp : std_logic_vector (7 DOWNTO 0);
SIGNAL IssuequeReadyTemp , IssuequefullTemp_Upper, IssuequefullTemp_Lower, UpperHalf_Has_Two_or_More_vacant, LowerHalf_Has_Two_or_More_vacant : std_logic ;
SIGNAL Buffer0Depth , Buffer1Depth ,Buffer2Depth ,Buffer3Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL Buffer4Depth , Buffer5Depth ,Buffer6Depth ,Buffer7Depth : std_logic_vector( 4 downto 0 ) ;
SIGNAL IssuedRegWrite : std_logic;
begin
----------------------Generating Issuque ready -------------------------------------
---DisJAL only Instruction valid.
--###############################################################################################
-- TODO 1: Generate the IssuequeReadyTemp signal which is asserted when
--################################################################################################
-- For anyone of the 8 entries in the issue queue
-- NOTE: where [i] is from 0 to 7
-- The instruction [i] is valid and
-- instruction [i] is JAL or (JR with Rs register ready) or (JRrs with Rs register ready) or other int type instructions with both Rs register and Rt register ready
IssuequeReadyTemp <= --------------------------------------------------------------
--//JAL on slide 8 of 14
--//JR and RS ready
--//RS and RT registers ready (for add, sub, etc instructions) and instruction valid ready
IssInt_Rdy <= IssuequeReadyTemp ;
---------- ----------Done Generating issuque Ready --------------------------------
--##################################################################################################
--------------------- Generating Full Condition-------------------------------------
--**********************************************************************************
-- This process generates the issueque full signal :
-- If you are issuing an instruction then the issueque is not full otherwise
-- issueque is full if all the eight entries are valid
--***********************************************************************************
--###############################################################################################
-- TODO 2: Generate the Full control signal
--################################################################################################
process ( IssuequeInstrValReg ,Iss_Int ) --ISSUEBLKDONE FROM ISSUE UNIT telling you that a instruction is issued
begin
if ( Iss_Int = '1' ) then
IssuequefullTemp_Upper <= ----- ; --Fill in the initial values of these two signals.
IssuequefullTemp_Lower <= ----- ; //not(or(check valid bits))
else
IssuequefullTemp_Upper <=IssuequeInstrValReg(7) and IssuequeInstrValReg(6) and
IssuequeInstrValReg(5) and IssuequeInstrValReg(4);
IssuequefullTemp_Lower <=IssuequeInstrValReg(3) and IssuequeInstrValReg(2) and
IssuequeInstrValReg(1) and IssuequeInstrValReg(0) ;
end if ;
end process ;
Issque_IntQueueFull <= -- ------------------------------------------; --Complete the right hand side of the expression //full when both upper and lower are full
--##################################################################################################
--------------- Nearly Full Signal ------------------------------
--**********************************************************************************
-- This process generates the issueque Nearly full signal :
-- The nearly full signal is generated for the first stage of dispatch unit for the following case
-- where both the stages have instructions to be issued in the same queue.
-- 1. Only one slot vacant in issueque: The instruction in first stage cannot be issued by dispatch.
-- 2. Two or more slots vacant in issueque: The instruction in first stage of dispatch finds a slot in issueque.
--***********************************************************************************
--###############################################################################################
-- TODO 3: Generate the Nearly Full control signal
--################################################################################################
UpperHalf_Has_Two_or_More_vacant <=(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(6))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(7)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(5))) or
(not(IssuequeInstrValReg(6)) and not(IssuequeInstrValReg(4))) or
(not(IssuequeInstrValReg(5)) and not(IssuequeInstrValReg(4))) ;
LowerHalf_Has_Two_or_More_vacant <= (not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(2))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(3)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(1))) or
(not(IssuequeInstrValReg(2)) and not(IssuequeInstrValReg(0))) or
(not(IssuequeInstrValReg(1)) and not(IssuequeInstrValReg(0))) ;
Issque_IntQueueTwoOrMoreVacant <= ---------------------------------------------------------; --complete this statement //OR the upper and lower two vacant, OR one in upper and one in lower
-- NOTE : Two or more vacant only if
-- (a) UpperHalf Has Two or More vacant
-- (b) LowerHalf Has Two or More vacant
-- (c) Identify the third case when you need to deal with both the halfs simultaneoulsy
-- i.e) atleast one slot vacant in lower half and atleast one slot vacant in upper half
------------------ Done Generating Full and Nearly Full Condition -------------------------------
--##################################################################################################
------------------- Generating OutSelect and En-----------------------------------------
-- issue the instruction if instruction and data are valid
OUT_SELECT:
for I in 0 to 7 generate
OutSelecttemp(I) <= (IssuequeInstrValReg(I) and (IssuequeJAL(I) or(IssuequeRsReadyReg(I) and (IssuequeRtReadyReg(I) or IssuequeJR(I) or IssuequeJRrs(I))))) ; -- this has the priority in being issued
OutSelectJRrstemp(I) <= (IssuequeInstrValReg(I) and IssuequeRsReadyReg(I) and IssuequeJRrs(I)) ;
end generate OUT_SELECT;
--***************************************************************************************
-- This process generates the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelecttemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelecttemp(0) = '1' ) then
OutSelect <= "000";
else
if ( OutSelecttemp(1) = '1' ) then
OutSelect <= "001";
else
if ( OutSelecttemp(2) = '1') then
OutSelect <= "010";
else
if ( OutSelecttemp(3) = '1') then
OutSelect <= "011";
else
if ( OutSelecttemp(4) = '1') then
OutSelect <= "100";
else
if ( OutSelecttemp(5) = '1') then
OutSelect <= "101";
else
if ( OutSelecttemp(6) = '1') then
OutSelect <= "110";
else
OutSelect <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
--***************************************************************************************
-- This process generates to give priority to JRrs instruction in the issue queue.
-- the mux select signal to let the ready instruction to be issued
-- the priority is given to "0"th entry
--****************************************************************************************
process ( OutSelectJRrstemp ) --TO SELECT AMONGST THE 8 ENTRIES
begin
if ( OutSelectJRrstemp(0) = '1' ) then
OutSelectJRrs <= "000";
else
if ( OutSelectJRrstemp(1) = '1' ) then
OutSelectJRrs <= "001";
else
if ( OutSelectJRrstemp(2) = '1') then
OutSelectJRrs <= "010";
else
if ( OutSelectJRrstemp(3) = '1') then
OutSelectJRrs <= "011";
else
if ( OutSelectJRrstemp(4) = '1') then
OutSelectJRrs <= "100";
else
if ( OutSelectJRrstemp(5) = '1') then
OutSelectJRrs <= "101";
else
if ( OutSelectJRrstemp(6) = '1') then
OutSelectJRrs <= "110";
else
OutSelectJRrs <= "111";
end if ;
end if ;
end if;
end if ;
end if ;
end if;
end if ;
end process ;
process ( OutSelect , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelect) is
when "000" => Entemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => Entemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => Entemp <= "11111100" ;
when "011" => Entemp <= "11111000" ;
when "100" => Entemp <= "11110000" ;
when "101" => Entemp <= "11100000" ;
when "110" => Entemp <= "11000000" ;
when others => Entemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
Entemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
Entemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
Entemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
Entemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
Entemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
Entemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
process ( OutSelectJRrs , Iss_Int ,IssuequeInstrValReg , Dis_Issquenable )
begin
if ( Iss_Int = '1' ) then
Case ( OutSelectJRrs) is
when "000" => EnJRrstemp <= "11111111" ; --UPDATE ALL 8 (BECAUSE THE BOTTOMMOST ONE IS GIVEN OUT)
when "001" => EnJRrstemp <= "11111110" ; --UPDATE 7 (BECAUSE THE LAST BUT ONE IS GIVEN OUT)
when "010" => EnJRrstemp <= "11111100" ;
when "011" => EnJRrstemp <= "11111000" ;
when "100" => EnJRrstemp <= "11110000" ;
when "101" => EnJRrstemp <= "11100000" ;
when "110" => EnJRrstemp <= "11000000" ;
when others => EnJRrstemp <= "10000000" ;
end case ;
else --WHY THIS CLAUSE --update till you become valid (YOU ARE NOT ISSUED BUT YOU SHOULD BE UPDATED AS PER INSTRUCTION VALID BIT)
EnJRrstemp(0) <= (not (IssuequeInstrValReg(0) )) ; --check *===NOTE 1==*, also, remember that you will shift update as soon as an instruction gets ready.
EnJRrstemp(1) <= (not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0)) ) ;
EnJRrstemp(2) <= (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) )) or ( not (IssuequeInstrValReg(0) )) ;
EnJRrstemp(3) <= (not (IssuequeInstrValReg(3) )) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ; --this is where dispatch writes (DISPATCH WRITES TO THE "3rd" ENTRY)
EnJRrstemp(4) <= (not (IssuequeInstrValReg(4) )) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(5) <= (not (IssuequeInstrValReg(5) )) or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) ) ) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(6) <= (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
EnJRrstemp(7) <= Dis_Issquenable or (not (IssuequeInstrValReg(7) )) or (not (IssuequeInstrValReg(6) )) or (not (IssuequeInstrValReg(5) ) )or (not (IssuequeInstrValReg(4) ) ) or (not (IssuequeInstrValReg(3) ) ) or (not (IssuequeInstrValReg(2) )) or ( not (IssuequeInstrValReg(1) ) ) or ( not (IssuequeInstrValReg(0) ) ) ;
end if ;
end process ;
En <= EnJRrstemp when (OutSelectJRrstemp /= "00000000") else Entemp; -- To given JRrs priority
OutSelect_result <= OutSelectJRrs when (OutSelectJRrstemp /= "00000000") else OutSelect; -- To given JRrs priority
------------------------------------Done Generating Enable ------------------------------------------
------------------------------- Generating Flush Condition for Queues -----------------
--###############################################################################################
-- TODO 4: Calculation of buffer depth to help in selective flushing
-- fill in the eight expressions
--################################################################################################
-- you arrive at the younger instruction to branch by first calcualting its depth using the tag and top pointer of rob
-- and comparing its depth with depth of branch instruction (known as Cdb_RobDepth)
Buffer0Depth <= -------------------------------; //unsigned mod subtraction (TP - ROBtag?)
Buffer1Depth <= -------------------------------;
Buffer2Depth <= -------------------------------;
Buffer3Depth <= -------------------------------;
Buffer4Depth <= -------------------------------;
Buffer5Depth <= -------------------------------;
Buffer6Depth <= -------------------------------;
Buffer7Depth <= -------------------------------;
--################################################################################################
--***************************************************************************************************************
-- This process does the selective flushing, if the instruction is younger to branch and there is an intent to flush
-- Flush the instruction if it is a valid instruction, this is an additional qualification which is unnecessary
-- We are just flushing the valid instructions and not caring about invalid instructions
--*****************************************************************************************************************
--###############################################################################################
-- TODO 5: Complete the code on selective flusing
-- fill in the missing expressions
-- NOTE: Remember the queue is from 7 downto 0
-- buffer 7th is at top so dispatch writes to it
-- buffer 0 is at the bottom
--################################################################################################
process ( Cdb_Flush , Cdb_RobDepth , Buffer0Depth , Buffer1Depth ,
Buffer2Depth , Buffer3Depth , Buffer4Depth , Buffer5Depth ,
Buffer6Depth , Buffer7Depth , En ,IssuequeInstrValReg)
begin
Flush <= (others => '0') ;
if ( Cdb_Flush = '1' ) then
if ( Buffer0Depth > Cdb_RobDepth ) then -- WHY THIS CONDITION?? CHECK WETHER THE INSTRUCTION IS AFTER BRANCH OR NOT(i.e, instruction is younger to branch)
if ( En(0) = '0' ) then -- NOT UPDATING HENCE FLUSH IF INSTRUCTION IS VALID
Flush(0) <= IssuequeInstrValReg(0) ; --just to make sure that flush only valid instruction
end if ;
end if ;
if ( Buffer1Depth > Cdb_RobDepth ) then -- check for younger instructions
if ( En(0) = '1' ) then
Flush(0) <= ---------------------------------------; Hint: Take into account the shift mechanism so is it i or i+1 or i - 1? //if you're shifting, flush the instruction that is 1 ahead
else
Flush(1) <= IssuequeInstrValReg(1) ;-- NO UPDATION SO FLUSH(1) IS THE STATUS OF INSTRUCTION (1)
end if ;
else
Flush(1) <= '0' ;
end if ;
if ( Buffer2Depth > Cdb_RobDepth ) then
if ( En(1) = '1' ) then
Flush(1) <= ---------------------------------------;
else
Flush(2) <= IssuequeInstrValReg(2) ;
end if ;
else
Flush(2) <= '0' ;
end if ;
if ( Buffer3Depth > Cdb_RobDepth ) then
if ( En(2) = '1' ) then
Flush(2) <= ---------------------------------------;
else
Flush(3) <= IssuequeInstrValReg(3) ;
end if ;
else
Flush(3) <= '0' ;
end if ;
if ( Buffer4Depth > Cdb_RobDepth ) then
if ( En(3) = '1' ) then
Flush(3) <= ---------------------------------------;
else
Flush(4) <= IssuequeInstrValReg(4) ;
end if ;
else
Flush(4) <= '0' ;
end if ;
if ( Buffer5Depth > Cdb_RobDepth ) then
if ( En(4) = '1' ) then
Flush(4) <= ---------------------------------------;
else
Flush(5) <= IssuequeInstrValReg(5) ;
end if ;
else
Flush(5) <= '0' ;
end if ;
if ( Buffer6Depth > Cdb_RobDepth ) then
if ( En(5) = '1' ) then
Flush(5) <= ---------------------------------------;
else
Flush(6) <= IssuequeInstrValReg(6) ;
end if ;
else
Flush(6) <= '0' ;
end if ;
if ( Buffer7Depth > Cdb_RobDepth ) then
if ( En(6) = '1' ) then
Flush(6) <= ---------------------------------------;
else
Flush(7) <= IssuequeInstrValReg(7) ;
end if ;
else
Flush(7) <= '0' ;
end if ;
end if ;
end process ;
-------------------- Done Generating Flush Condition ----------------------
--###############################################################################################
-- TODO 6: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RtReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction being issued for ALU Queue, load - store queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit and do the forwarding if necessary.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process ( IssuequeRtPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Lsbuf_RdWrite, Iss_Lsb, IssuequeRegWrite , IssuequeInstrValReg, IssuequeRtReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RtReadyTemp <= (others => '0') ;
if (( (IssuequeRtPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(0) ='0' and IssuequeInstrValReg(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RtReadyTemp(0) <= IssuequeRtReadyReg(0);
end if ;
if (( (IssuequeRtPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(1) ='0' and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RtReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RtReadyTemp(0) <= IssuequeRtReadyReg(1);
else
RtReadyTemp(1) <= IssuequeRtReadyReg(1);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(2) ='0' and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RtReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RtReadyTemp(1) <= IssuequeRtReadyReg(2);
else
RtReadyTemp(2) <= IssuequeRtReadyReg(2);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(3) ='0' and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RtReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RtReadyTemp(2) <= IssuequeRtReadyReg(3);
else
RtReadyTemp(3) <= IssuequeRtReadyReg(3);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(4) ='0' and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RtReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RtReadyTemp(3) <= IssuequeRtReadyReg(4);
else
RtReadyTemp(4) <= IssuequeRtReadyReg(4);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(5) ='0' and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RtReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RtReadyTemp(4) <= IssuequeRtReadyReg(5);
else
RtReadyTemp(5) <= IssuequeRtReadyReg(5);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(6) ='0' and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RtReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RtReadyTemp(5) <= IssuequeRtReadyReg(6);
else
RtReadyTemp(6) <= IssuequeRtReadyReg(6);
end if;
end if ;
if (( (IssuequeRtPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRtPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRtPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRtPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRtReadyReg(7) ='0' and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RtReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RtReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RtReadyTemp(6) <= IssuequeRtReadyReg(7);
else
RtReadyTemp(7) <= IssuequeRtReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
--###############################################################################################
-- TODO 7: fill in the missing values of the signals Cdb_PhyRegWrite and IssuedRegWrite the forwarding conditions
-- replace the "-*'" by '1' or '0'
--################################################################################################
--*****************************************************************************************************************************
-- This processes does the updation of the various RsReadyTemp entries in the issue queues
-- If there is a valid instruction in the queue with stale ready signal and cdb_declares result then compare the tag and put into queue
-- Also check the instruction begin issued for load - store queue, ALU queue, instruction in 3rd stage of Multiplier execution unit
-- and output of divider execution unit.
-- If En signal indicates shift update then either do self update or shift update accordingly
-- *****************************************************************************************************************************
process (IssuequeRsPhyAddrReg, Cdb_RdPhyAddr, Cdb_PhyRegWrite, Lsbuf_PhyAddr, Iss_Lsb, Lsbuf_RdWrite,IssuequeInstrValReg, IssuequeRsReadyReg, En, Mul_RdPhyAddr, Div_RdPhyAddr, IssuedRdPhyAddr, Mul_ExeRdy, Div_ExeRdy, Iss_Int )
begin
RsReadyTemp <= (others => '0');
if (( (IssuequeRsPhyAddrReg(0) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRsPhyAddrReg(0) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(0) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(0) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(0) ='0'and IssuequeInstrValReg(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --UPDATE FROM CDB
else
RsReadyTemp(0) <= IssuequeRsReadyReg(0);
end if ;
if (( (IssuequeRsPhyAddrReg(1) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRsPhyAddrReg(1) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(1) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(1) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(1) ='0'and IssuequeInstrValReg(1) = '1' ) then
if ( En(0) = '1' ) then
RsReadyTemp(0) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(1) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(0) = '1') then
RsReadyTemp(0) <= IssuequeRsReadyReg(1);
else
RsReadyTemp(1) <= IssuequeRsReadyReg(1);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(2) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRsPhyAddrReg(2) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(2) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(2) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(2) ='0'and IssuequeInstrValReg(2) = '1' ) then
if ( En(1) = '1' ) then
RsReadyTemp(1) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(2) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(1) = '1') then
RsReadyTemp(1) <= IssuequeRsReadyReg(2);
else
RsReadyTemp(2) <= IssuequeRsReadyReg(2);
end if;
end if ;
if (((IssuequeRsPhyAddrReg(3) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRsPhyAddrReg(3) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(3) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(3) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(3) ='0'and IssuequeInstrValReg(3) = '1' ) then
if ( En(2) = '1' ) then
RsReadyTemp(2) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(3) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(2) = '1') then
RsReadyTemp(2) <= IssuequeRsReadyReg(3);
else
RsReadyTemp(3) <= IssuequeRsReadyReg(3);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(4) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or(IssuequeRsPhyAddrReg(4) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(4) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(4) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(4) ='0'and IssuequeInstrValReg(4) = '1' ) then
if ( En(3) = '1' ) then
RsReadyTemp(3) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(4) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(3) = '1') then
RsReadyTemp(3) <= IssuequeRsReadyReg(4);
else
RsReadyTemp(4) <= IssuequeRsReadyReg(4);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(5) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRsPhyAddrReg(5) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(5) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(5) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(5) ='0'and IssuequeInstrValReg(5) = '1' ) then
if ( En(4) = '1' ) then
RsReadyTemp(4) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(5) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(4) = '1') then
RsReadyTemp(4) <= IssuequeRsReadyReg(5);
else
RsReadyTemp(5) <= IssuequeRsReadyReg(5);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(6) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRsPhyAddrReg(6) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(6) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(6) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(6) ='0'and IssuequeInstrValReg(6) = '1' ) then
if ( En(5) = '1' ) then
RsReadyTemp(5) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(6) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(5) = '1') then
RsReadyTemp(5) <= IssuequeRsReadyReg(6);
else
RsReadyTemp(6) <= IssuequeRsReadyReg(6);
end if;
end if ;
if (( (IssuequeRsPhyAddrReg(7) = Cdb_RdPhyAddr and Cdb_PhyRegWrite = "-*-") or (IssuequeRsPhyAddrReg(7) = Lsbuf_PhyAddr and Lsbuf_RdWrite = '1' and Iss_Lsb = '1') or (IssuequeRsPhyAddrReg(7) = Mul_RdPhyAddr and Mul_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = Div_RdPhyAddr and Div_ExeRdy = '1') or (IssuequeRsPhyAddrReg(7) = IssuedRdPhyAddr and Iss_Int = '1' and IssuedRegWrite = "-*-")) and IssuequeRsReadyReg(7) ='0'and IssuequeInstrValReg(7) = '1' ) then
if ( En(6) = '1' ) then
RsReadyTemp(6) <= '1' ; --SHIFT UPDATE
else
RsReadyTemp(7) <= '1' ; --buffer1 UPDATES itself ?? *===NOTE 1==* -- enabling the self updation till the invalid instruction becomes valid
end if ;
else
if ( En(6) = '1') then
RsReadyTemp(6) <= IssuequeRsReadyReg(7);
else
RsReadyTemp(7) <= IssuequeRsReadyReg(7);
end if;
end if ;
end process ;
--###############################################################################################
----------------------------------------------------------------------------------------------------
--------------------------------- ------------------------------
process ( clk , Resetb )
begin
if ( Resetb = '0' ) then
IssuequeInstrValReg <= (others => '0') ;
IssuequeRsReadyReg <= (others => '0');
IssuequeRtReadyReg <= (others => '0');
IssuequeJR <= (others => '0');
IssuequeJRrs <= (others => '0');
IssuequeJAL <= (others => '0');
elsif ( Clk'event and Clk = '1' ) then
IssuequeRsReadyReg <= RsReadyTemp;
IssuequeRtReadyReg <= RtReadyTemp;
-- end if;
for I in 6 downto 0 loop
if ( Flush(I) = '1' ) then
IssuequeInstrValReg(I) <= '0' ;
-- translate_off
Issuequeinstruction(I) <= (others => '0') ;
-- translate_on
else
if ( En(I) = '1' ) then --update
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I + 1) ;
IssuequeRsPhyAddrReg(I) <= IssuequeRsPhyAddrReg(I + 1);
IssuequeRdPhyAddrReg(I) <= IssuequeRdPhyAddrReg(I + 1);
IssuequeRtPhyAddrReg(I) <= IssuequeRtPhyAddrReg(I + 1);
IssuequeRobTag(I) <= IssuequeRobTag(I + 1);
IssuequeRegWrite(I) <= IssuequeRegWrite(I + 1);
IssuequeOpcodeReg(I) <= IssuequeOpcodeReg(I + 1);
IssuequeBranchPredict(I) <= IssuequeBranchPredict(I + 1);
IssuequeBranch(I) <= IssuequeBranch(I + 1);
IssuequeBranchAddr(I) <= IssuequeBranchAddr(I + 1);
IssuequeBranchPCBits(I) <= IssuequeBranchPCBits(I + 1);
IssuequeJR(I) <= IssuequeJR(I + 1);
IssuequeJRrs(I) <= IssuequeJRrs(I + 1);
IssuequeJAL(I) <= IssuequeJAL(I + 1);
IssuequeImmediate(I) <= IssuequeImmediate(I + 1);
-- translate_off
Issuequeinstruction(I) <= Issuequeinstruction(I + 1);
-- translate_on
else
---If can be removed ---
IssuequeInstrValReg(I) <= IssuequeInstrValReg(I) ;
end if ;
end if ;
end loop;
if ( Flush(7) = '1' ) then
IssuequeInstrValReg(7) <= '0' ;
-- translate_off
Issuequeinstruction(7) <= (others => '0') ;
-- translate_on
else
if ( En(7) = '1' ) then
IssuequeInstrValReg(7) <= Dis_Issquenable;
IssuequeRdPhyAddrReg(7) <= Dis_NewRdPhyAddr ;
IssuequeOpcodeReg(7) <= Dis_Opcode ;
IssuequeRobTag(7) <= Dis_RobTag;
IssuequeRegWrite(7) <= Dis_RegWrite;
IssuequeRtPhyAddrReg(7) <= Dis_RtPhyAddr ;
IssuequeRsPhyAddrReg(7) <= Dis_RsPhyAddr ;
IssuequeBranchPredict(7) <= Dis_BranchPredict;
IssuequeBranch(7) <= Dis_Branch;
IssuequeBranchAddr(7) <= Dis_BranchOtherAddr;
IssuequeBranchPCBits(7) <= Dis_BranchPCBits;
IssuequeRsReadyReg(7) <= Dis_RsDataRdy;
IssuequeRtReadyReg(7) <= Dis_RtDataRdy;
IssuequeJR(7) <= Dis_Jr31Inst;
IssuequeJRrs(7) <= Dis_JrRsInst;
IssuequeJAL(7) <= Dis_JalInst;
IssuequeImmediate(7) <= Dis_Immediate;
-- translate_off
Issuequeinstruction(7) <= Dis_instruction;
-- translate_on
else
IssuequeInstrValReg(7) <= IssuequeInstrValReg(7) ;
end if ;
end if ;
end if ;
end process ;
--- Selecting the Output to Go to Execution Unit, Physical Register Filed, Issue Unit
Iss_RsPhyAddrAlu <= IssuequeRsPhyAddrReg(CONV_INTEGER (unsigned( OutSelect_result))) ;
Iss_RtPhyAddrAlu <= IssuequeRtPhyAddrReg (CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRdPhyAddr <= IssuequeRdPhyAddrReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
IssuedRegWrite <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RdPhyAddrAlu <= IssuedRdPhyAddr;
Iss_OpcodeAlu <= IssuequeOpcodeReg(CONV_INTEGER(unsigned( OutSelect_result))) ;
Iss_RobTagAlu <= IssuequeRobTag(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_RegWriteAlu <= IssuequeRegWrite(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchPredictAlu <= IssuequeBranchPredict(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAlu <= IssuequeBranch(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchAddrAlu <= IssuequeBranchAddr(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_BranchUptAddrAlu <= IssuequeBranchPCBits(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrInstAlu <= IssuequeJR(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JalInstAlu <= IssuequeJAL(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_JrRsInstAlu <= IssuequeJrRs(CONV_INTEGER(unsigned( OutSelect_result)));
Iss_ImmediateAlu <= IssuequeImmediate(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_off
Iss_instructionAlu <= Issuequeinstruction(CONV_INTEGER(unsigned( OutSelect_result)));
-- translate_on
end behav ;
|
gpl-2.0
|
7b561c46141dd6fdfd1b5eb486d13c31
| 0.509126 | 4.89245 | false | false | false | false |
lvoudour/arty-uart
|
src/uart.vhd
| 1 | 6,357 |
--------------------------------------------------------------------------------
--
-- UART top module
--
-- 8 bit data, 1 stop bit, no parity. Intended for the Digilent Arty Artix-7
-- FPGA board, but can be easily used in other projects without modification.
--
-- Signals:
-- clk : Clock of frequency G_CLOCK_FREQ
-- rst : Active high synchronous reset
-- tx_data_in : Tx data
-- tx_data_wr_in : Tx data FIFO write enable
-- tx_fifo_full_out : Tx FIFO full
-- tx_out : Tx data line. Should be routed to the Rx pin
-- of the external UART device.
-- rx_in : Rx data line. Should be routed to the Tx pin
-- of the external UART device.
-- rx_data_rd_in : Rx FIFO read enable
-- rx_data_out : Rx data
-- rx_fifo_empty_out : Rx FIFO empty
--
-- Parameters:
-- G_BAUD_RATE : UART baud rate
-- G_CLOCK_FREQ : clk frequency. Can be fractional
--
-- Data tranasction is done through small (16 deep) FIFOs. rx_data_out
-- is valid 1 clk cycle after rx_data_rd_in is asserted. Any attempt
-- to read data when the Rx FIFO is empty is ignored (rx_data_out is
-- invalid). Any attempt to send more data while the Tx FIFO is full
-- is also ignored (data on tx_data_in is dropped).
--
-- Optimally, the baud rate must be an integer multiple of the clock
-- frequency. If not, it's rounded to the closest integer. In such cases
-- care must be taken to ensure sampling does not deviate significantly from
-- the center of the "eye"(ie. the middle of the received bit).
--
-- It is recommended to use sync flip-flops and a glitch filter before
-- connecting the rx input to the external UART device.
--
-- Arty FPGA board specific notes:
-- The FT2232H chip does not support baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud
-- and 11 Mbaud.
-- http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf
--
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart is
generic(
G_BAUD_RATE : positive := 1250000;
G_CLOCK_FREQ : real := 100.0e6
);
port(
clk : in std_logic;
rst : in std_logic;
tx_data_in : in std_logic_vector(7 downto 0);
tx_data_wr_in : in std_logic;
tx_fifo_full_out : out std_logic;
tx_out : out std_logic;
rx_in : in std_logic;
rx_data_rd_in : in std_logic;
rx_data_out : out std_logic_vector(7 downto 0);
rx_fifo_empty_out : out std_logic
);
end entity uart;
architecture rtl of uart is
signal fifo_tx_dout_i : std_logic_vector(7 downto 0) := (others=>'0');
signal fifo_tx_full_i : std_logic := '0';
signal fifo_tx_rd_en_r : std_logic := '0';
signal fifo_tx_empty_i : std_logic := '0';
signal tx_en_r : std_logic := '0';
signal tx_ready_i : std_logic := '0';
signal fifo_rx_din_r : std_logic_vector(7 downto 0) := (others=>'0');
signal fifo_rx_wr_en_r : std_logic := '0';
signal fifo_rx_full_i : std_logic := '0';
signal fifo_rx_empty_i : std_logic := '0';
signal rx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal rx_valid_i : std_logic := '0';
begin
---------------------------------------------
-- Tx
---------------------------------------------
tx_fifo_full_out <= fifo_tx_full_i;
fifo_tx_inst : entity work.fifo_srl(rtl)
generic map(
G_DATA_WIDTH => 8,
G_DEPTH => 16
)
port map(
clk => clk,
rst => rst,
din => tx_data_in,
wr_en => tx_data_wr_in,
full => fifo_tx_full_i,
dout => fifo_tx_dout_i,
rd_en => fifo_tx_rd_en_r,
empty => fifo_tx_empty_i
);
proc_fifo_tx:
process(clk)
begin
if rising_edge(clk) then
tx_en_r <= fifo_tx_rd_en_r;
if (rst = '1') then
fifo_tx_rd_en_r <= '0';
else
-- Fetch new data from the FIFO only when the FIFO is not empty and
-- the Tx is not busy. Allow one clk cycle for the data to be fetched and
-- one more for tx_ready to update.
fifo_tx_rd_en_r <= '0';
if (tx_ready_i = '1') and (fifo_tx_empty_i = '0') and (fifo_tx_rd_en_r='0') and (tx_en_r='0') then
fifo_tx_rd_en_r <= '1';
end if;
end if;
end if;
end process;
uart_tx_inst : entity work.uart_tx(rtl)
generic map(
G_BAUD_RATE => G_BAUD_RATE,
G_CLOCK_FREQ => G_CLOCK_FREQ
)
port map(
clk => clk,
rst => rst,
tx_data_in => fifo_tx_dout_i,
tx_en_in => tx_en_r,
tx_ready_out => tx_ready_i,
tx_out => tx_out
);
---------------------------------------------
-- Rx
---------------------------------------------
rx_fifo_empty_out <= fifo_rx_empty_i;
fifo_rx_inst : entity work.fifo_srl(rtl)
generic map(
G_DATA_WIDTH => 8,
G_DEPTH => 16
)
port map(
clk => clk,
rst => rst,
din => fifo_rx_din_r,
wr_en => fifo_rx_wr_en_r,
full => fifo_rx_full_i,
dout => rx_data_out,
rd_en => rx_data_rd_in,
empty => fifo_rx_empty_i
);
proc_fifo_rx:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
fifo_rx_wr_en_r <= '0';
else
fifo_rx_din_r <= rx_data_i;
-- Write data to the FIFO only when the FIFO is not full and
-- the Rx has valid data.
fifo_rx_wr_en_r <= '0';
if (rx_valid_i = '1') and (fifo_rx_full_i = '0') then
fifo_rx_wr_en_r <= '1';
end if;
end if;
end if;
end process;
uart_rx_inst: entity work.uart_rx(rtl)
generic map(
G_BAUD_RATE => G_BAUD_RATE,
G_CLOCK_FREQ => G_CLOCK_FREQ
)
port map(
clk => clk,
rst => rst,
rx_in => rx_in,
rx_data_out => rx_data_i,
rx_valid_out => rx_valid_i
);
end architecture rtl;
|
mit
|
64c95b9c697a56c32680a7d8b9966aac
| 0.517068 | 3.275116 | false | false | false | false |
cheehieu/tomasulo-processor
|
sw/tomasulo_syn/code/bpb_NEW.vhd
| 2 | 7,498 |
------------------------------------------------------------------------------
--
-- Design : Branch Predicton Buffer
-- Project : Tomasulo Processor
-- Entity : bpb
-- Author : kapil
-- Company : University of Southern California
-- Last Updated : June 24, 2010
-- Last Updated by : Waleed Dweik
-- Modification : 1. Modify the branch prediction to use the most well-known state machine of the 2-bit saturating counter
-- 2. Update old comments
-------------------------------------------------------------------------------
--
-- Description : 2 - bit wide / 8 deep
-- each 2 bit locn is a state machine
-- 2 bit saturating counter
-- 00 strongly nottaken
-- 01 mildly nottaken
-- 10 mildly taken
-- 11 strongly taken
--
-------------------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------------------------------------
entity bpb is
port (
Clk : in std_logic;
Resetb : in std_logic;
---- Interaction with Cdb -------------------
Dis_CdbUpdBranch : in std_logic; -- indicates that a branch appears on Cdb(wen to bpb)
Dis_CdbUpdBranchAddr : in std_logic_vector(2 downto 0);-- indiactes the last 3 bit addr of the branch on the Cdb
Dis_CdbBranchOutcome : in std_logic; -- indiacates the outocome of the branch to the bpb: 0 means nottaken and 1 means taken
---- Interaction with dispatch --------------
Bpb_BranchPrediction : out std_logic; --This bit tells the dispatch what the prediction actually based on bpb state-mc
Dis_BpbBranchPCBits : in std_logic_vector(2 downto 0) ;--indiaces the 3 least sig bits of the current instr being dispatched
Dis_BpbBranch : in std_logic -- indiactes that there is a branch instr in the dispatch (ren to the bpb)
);
end bpb;
architecture behv of bpb is
subtype sat_counters is std_logic_vector(1 downto 0);
type bpb_array is array (0 to 7) of sat_counters ;
signal bpb_array_r: bpb_array ; -- An array of 8 2-bit saturating counters represents 8 location bpb.
signal Bpb_read_status,Bpb_write_status : std_logic_vector(1 downto 0);
begin
---------------------------------------------------------------------------
-- Task1: Complete the following 2 concurrent statements for Bpb read and write status:
-- Hint: You may want to use CONV_INTEGER function to convert from std_logic_vector to an integer
-- Bpb_read_status represets the 2-bit counter value in the Bpb entry addressed by the branch instruction in dispatch.
-- Bpb_read_status tells whether branch should predicted Taken (11,10) or not Taken (00,01)
Bpb_read_status <= bpb_array_r(0) when Dis_BpbBranchPCBits = "000" else
bpb_array_r(1) when Dis_BpbBranchPCBits = "001" else
bpb_array_r(2) when Dis_BpbBranchPCBits = "010" else
bpb_array_r(3) when Dis_BpbBranchPCBits = "011" else
bpb_array_r(4) when Dis_BpbBranchPCBits = "100" else
bpb_array_r(5) when Dis_BpbBranchPCBits = "101" else
bpb_array_r(6) when Dis_BpbBranchPCBits = "110" else
bpb_array_r(7) when Dis_BpbBranchPCBits = "111";
-- Bpb_write_status represents the 2-bit counter value in the Bpb entry addressed by the branch instruction on the Cdb.
-- Bpb_write_status is used along with the actual outcome of the branch on Cdb to update the corresponding Bpb entry.
--Bpb_write_status <= --
---------------------------------------------------------------------------
-- Update Process
-- This prcoess is used to update the Bpb entry indexed by the PC[4:2] of the branch instruction which appears on Cdb.
-- The update process is based on the State machine for a 2-bit saturating counter which is given in the slide set.
bpb_write: process (Clk,Resetb)
variable write_data_bpb: std_logic_vector(1 downto 0);
variable bpb_waddr_mask ,bpb_index_addr,raw_bpb_addr: std_logic_vector(7 downto 0);
begin
if (Resetb = '0') then
-------------------------------Initialize register file contents(!! weakly taken, weakly not taken alternatvely!!) here----------------------------------
bpb_array_r <= (
"01", -- $0
"10", -- $1
"01", -- $2
"10", -- $3
"01", -- $4
"10", -- $5
"01", -- $6
"10" -- $7
);
elsif(Clk'event and Clk='1') then
if (Dis_CdbUpdBranch = '1')then
bpb_waddr_mask := X"FF";
else
bpb_waddr_mask := X"00";
end if ;
case Dis_CdbUpdBranchAddr is
when "000" => raw_bpb_addr := ("00000001");
when "001" => raw_bpb_addr := ("00000010");
when "010" => raw_bpb_addr := ("00000100");
when "011" => raw_bpb_addr := ("00001000");
when "100" => raw_bpb_addr := ("00010000");
when "101" => raw_bpb_addr := ("00100000");
when "110" => raw_bpb_addr := ("01000000");
when others => raw_bpb_addr := ("10000000");
end case ;
bpb_index_addr := raw_bpb_addr and bpb_waddr_mask ;
---------------------------------------------------------------------------
-- Task2: Add the Code inside the for loop to modify Bpb entries:
-- Hint: According to the current counter value of the corresponding entry and the actual outcome of the branch on Cdb you can
-- decide what is the new prediction value should be based on the state machine given in the slides.
---------------------------------------------------------------------------
for i in 0 to 7 loop
if (bpb_index_addr(i) = '1') then
case (bpb_array_r(i)) is
when "00" =>
if (Dis_CdbBranchOutcome = '1') then
bpb_array_r(i) <= "01";
end if;
when "01" =>
if (Dis_CdbBranchOutcome = '1') then
bpb_array_r(i) <= "10";
else
bpb_array_r(i) <= "00";
end if;
when "10" =>
if (Dis_CdbBranchOutcome = '1') then
bpb_array_r(i) <= "11";
else
bpb_array_r(i) <= "01";
end if;
when others =>
if (Dis_CdbBranchOutcome = '0') then
bpb_array_r(i) <= "10";
end if;
end case;
end if;
end loop;
end if;
end process bpb_write;
-- Prediction Process
-- This prcoess generates Bpb_BranchPrediction signal which indicates the prediction for branch instruction
-- The signal is always set to '0' except when there is a branch instruction in dispatch and the prediction is either Strongly Taken or Taken.
bpb_predict : process(Bpb_read_status ,Dis_BpbBranch)
begin
Bpb_BranchPrediction<= '0';
if (Bpb_read_status(1) = '0' ) then
Bpb_BranchPrediction<= '0';
else
Bpb_BranchPrediction<= '1' and Dis_BpbBranch;
end if ;
end process;
end behv;
|
gpl-2.0
|
fde3b07ae3a3dd71783384c60e9fc77b
| 0.521606 | 4.284571 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/cont10.vhd
| 1 | 4,319 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont10.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity cont10 is
Port ( clk : in STD_LOGIC;
ena : in STD_LOGIC;
rst: in std_logic;
fin : out STD_LOGIC);
end cont10;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of cont10 is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal reg_cuenta: std_logic_vector(3 downto 0);
signal reg_cuenta_in: std_logic_vector(3 downto 0);
signal fin_aux: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
-- COMPONENT adder4bits_comb
-- PORT(
-- A : IN std_logic_vector(3 downto 0);
-- B : IN std_logic_vector(3 downto 0);
-- Cin : IN std_logic;
-- Z : OUT std_logic_vector(3 downto 0);
-- Cout : OUT std_logic
-- );
-- END COMPONENT;
COMPONENT adder4bits_comb_noCout
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
Z : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
fin <= fin_aux;
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
-- Inst_adder4bits_comb: adder4bits_comb PORT MAP(
-- A => reg_cuenta,
-- B => "0001",
-- Cin => '0',
-- Z => reg_cuenta_in
-- --Cout => disconnected
-- );
Inst_adder4bits_comb_noCout: adder4bits_comb_noCout PORT MAP(
A => reg_cuenta,
B => "0001",
Cin => '0',
Z => reg_cuenta_in
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
p_cuenta: process(clk, ena, rst)
begin
if rst = '1' then
reg_cuenta <= (others => '0');
fin_aux <= '0';
elsif rising_edge(clk) then
if fin_aux = '1' then
reg_cuenta <= (others => '0');
fin_aux <= '0';
elsif ena = '1' then
if reg_cuenta = "1001" then
fin_aux <= '1';
reg_cuenta <= (others => '0');
else
reg_cuenta <= reg_cuenta_in;
fin_aux <= '0';
end if;
else
fin_aux <= '0';
reg_cuenta <= reg_cuenta;
end if;
end if;
end process p_cuenta;
end rtl;
|
gpl-3.0
|
f40a56ccc1bc9f32f45f02857ba80a16
| 0.417883 | 4.369433 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/rx_data_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,429 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rx_data_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
0ba131391c5d25aa8051ecb06c38c978
| 0.503281 | 3.936962 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/controller_command_fifo/simulation/fg_tb_pkg.vhd
| 2 | 11,334 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT controller_command_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
daf2b39b68ffa2d44d46f6e7dd5142ee
| 0.504764 | 3.934051 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
right_shift.vhd
| 1 | 3,821 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity right_shift is
generic (
SHIFT_BITS : positive := 1;
WORD_WIDTH : positive := 8;
NUM_WORDS : positive := 2);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic := '1';
input : in std_logic_vector(WORD_WIDTH*NUM_WORDS-1 downto 0);
shift_amount : in std_logic_vector(SHIFT_BITS-1 downto 0);
output : out std_logic_vector(WORD_WIDTH*NUM_WORDS-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic);
end right_shift;
architecture DEFAULT of right_shift is
constant LEVELS : positive := SHIFT_BITS;
type word_array is array (0 to LEVELS-1, 0 to NUM_WORDS-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
signal words : word_array;
type input_array is array (0 to NUM_WORDS-1) of std_logic_vector(WORD_WIDTH-1 downto 0);
signal inputs : input_array;
type shift_array is array (0 to LEVELS-1) of std_logic_vector(SHIFT_BITS-1 downto 0);
signal shift : shift_array;
begin
-- convert input vector into 2d array
process(input)
begin
for i in 0 to NUM_WORDS-1 loop
inputs(i) <= input(input'length-i*WORD_WIDTH-1 downto input'length-(i+1)*WORD_WIDTH);
end loop;
end process;
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to LEVELS-1 loop
for j in 0 to NUM_WORDS-1 loop
words(i, j) <= (others => '0');
end loop;
shift(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
-- level 0
for j in 0 to NUM_WORDS-1 loop
if (en = '1') then
if (shift_amount(LEVELS-1) = '1') then
if (j-2**(LEVELS-1) < 0) then
words(0, j) <= (others => '0');
else
words(0, j) <= inputs(j-2**(LEVELS-1));
end if;
else
words(0, j) <= inputs(j);
end if;
shift(0) <= shift_amount;
end if;
end loop;
for i in 1 to LEVELS-1 loop
shift(i) <= shift(i-1);
for j in 0 to NUM_WORDS-1 loop
if (en = '1') then
if (shift(i-1)(LEVELS-i-1) = '1') then
-- if word to shift from doesn't exist, shift in 0
-- else, shift in words based on the level
if (j-2**(LEVELS-i-1) < 0) then
words(i, j) <= (others => '0');
else
words(i, j) <= words(i-1, j-2**(LEVELS-i-1));
end if;
else
words(i, j) <= words(i-1, j);
end if;
end if;
end loop;
end loop;
end if;
end process;
process(words)
begin
for i in 0 to NUM_WORDS-1 loop
output((NUM_WORDS-i)*WORD_WIDTH-1 downto (NUM_WORDS-i-1)*WORD_WIDTH) <= words(LEVELS-1, i);
end loop;
end process;
U_DELAY : entity work.delay
generic map (
width => 1,
cycles => LEVELS,
init => "0")
port map (
clk => clk,
rst => rst,
en => en,
input(0) => valid_in,
output(0) => valid_out);
end DEFAULT;
|
gpl-3.0
|
65c76b94f241a940e2cabf099eb88e86
| 0.434965 | 3.988518 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/contMod8_comb.vhd
| 1 | 3,936 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: contMod8_comb.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity incrementadorCuenta8bits is
Port ( num_in : in STD_LOGIC_VECTOR (7 downto 0);
num_out : out STD_LOGIC_VECTOR (7 downto 0)
);
end incrementadorCuenta8bits;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of incrementadorCuenta8bits is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal aux: std_logic_vector(6 downto 0);
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT adder1bit_comb
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
COMPONENT adder1bit_noCout
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
adder_0: adder1bit_comb port map(
A => num_in(0),
B => '1',
Cin => '0',
Z => num_out(0),
Cout => aux(0)
);
adder_1: adder1bit_comb port map(
A => num_in(1),
B => aux(0),
Cin => '0',
Z => num_out(1),
Cout => aux(1)
);
adder_2: adder1bit_comb port map(
A => num_in(2),
B => aux(1),
Cin => '0',
Z => num_out(2),
Cout => aux(2)
);
adder_3: adder1bit_comb port map(
A => num_in(3),
B => aux(2),
Cin => '0',
Z => num_out(3),
Cout => aux(3)
);
adder_4: adder1bit_comb port map(
A => num_in(4),
B => aux(3),
Cin => '0',
Z => num_out(4),
Cout => aux(4)
);
adder_5: adder1bit_comb port map(
A => num_in(5),
B => aux(4),
Cin => '0',
Z => num_out(5),
Cout => aux(5)
);
adder_6: adder1bit_comb port map(
A => num_in(6),
B => aux(5),
Cin => '0',
Z => num_out(6),
Cout => aux(6)
);
adder_7: adder1bit_noCout PORT MAP(
A => num_in(7),
B => aux(6),
Cin => '0',
Z => num_out(7)
);
end rtl;
|
gpl-3.0
|
bcc45285315fbd152111859315fc7cdf
| 0.432893 | 3.883514 | false | false | false | false |
tuura/fantasi
|
dependencies/FSM-enable-nodes.vhd
| 1 | 4,615 |
-- Generic size shift register for enabling the nodes inside the network
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY FSM_ENABLE_NODES IS
GENERIC (NODES : integer := 8;
ADDR : integer := 3);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
M_SET : IN std_logic;
ZERO : IN std_logic;
ONE : IN std_logic;
DIN : IN std_logic_vector(ADDR-1 downto 0);
SH_DONE : OUT std_logic;
DOUT : OUT std_logic_vector(NODES-1 downto 0));
END FSM_ENABLE_NODES;
ARCHITECTURE structural OF FSM_ENABLE_NODES IS
COMPONENT Generic_shift_register_enable IS
GENERIC (N : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
SHF_EN : IN std_logic;
DIN : IN std_logic;
DOUT : OUT std_logic_vector(N-1 downto 0));
END COMPONENT;
COMPONENT Generic_register IS
GENERIC (N : integer);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DIN : IN std_logic_vector(N-1 downto 0);
DOUT : OUT std_logic_vector(N-1 downto 0));
END COMPONENT;
COMPONENT Generic_zero_comparator IS
GENERIC (N : integer);
PORT (
OP : IN std_logic_vector(N-1 downto 0);
EN : IN std_logic;
EQ : OUT std_logic);
END COMPONENT;
COMPONENT SYNC_LATCH IS
PORT (
DIN : IN std_logic;
CLK : IN std_logic;
RST : IN std_logic;
EN : IN std_logic;
DOUT : OUT std_logic);
END COMPONENT;
SIGNAL data_pin : std_logic_vector(ADDR-1 downto 0);
SIGNAL count : std_logic_vector(ADDR-1 downto 0);
SIGNAL count_minus_one : std_logic_vector(ADDR-1 downto 0);
SIGNAL zero1 : std_logic;
SIGNAL one1 : std_logic;
SIGNAL shift : std_logic;
SIGNAL shift_zero : std_logic;
SIGNAL shift_one : std_logic;
SIGNAL data_in : std_logic;
SIGNAL count_en : std_logic;
SIGNAL stop : std_logic;
SIGNAL one_end : std_logic;
type state_zero is (S0,S1,S2);
signal CR_ZERO, NX: state_zero;
type state_one is (T0,T1,T2,T3);
signal CR_ONE, TX: state_one;
BEGIN
-- zero synch latch
ZERO_LATCH : SYNC_LATCH
port map(
DIN => ZERO,
CLK => CLK,
RST => RST,
EN => EN,
DOUT => zero1);
-- one synch latch
ONE_LATCH : SYNC_LATCH
port map(
DIN => ONE,
CLK => CLK,
RST => RST,
EN => EN,
DOUT => one1);
-- hold the value to enable and disable the nodes
SR : Generic_shift_register_enable
generic map(NODES)
port map(
CLK => CLK,
RST => M_SET,
SHF_EN => shift,
DIN => data_in,
DOUT => DOUT);
-- hold the current number of ones to shift in
REG : Generic_register
generic map(ADDR)
port map(
CLK => CLK,
RST => RST,
EN => EN,
DIN => data_pin,
DOUT => count);
-- Initial counter value (MUX)
OR_GEN : for i in 0 to (ADDR-1) generate
data_pin(i) <= (count_minus_one(i) AND count_en) OR (DIN(i) AND NOT(count_en));
end generate;
-- decrease the value of the counter
count_minus_one <= count - 1;
-- check when to stop shifting ones
ZERO_COMP : Generic_zero_comparator
generic map(ADDR)
port map(
OP => count,
EN => EN,
EQ => stop);
-- FSMs to control the structure
process (CLK,RST)
begin
if (RST='1') then
CR_ZERO <= S0;
CR_ONE <= T0;
elsif (CLK'event and CLK='1') then
CR_ZERO <= NX;
CR_ONE <= TX;
end if;
end process;
process (CR_ZERO, zero1)
begin
case CR_ZERO is
when S0 =>
shift_zero <= '0';
if zero1 = '1' then
NX <= S1;
else
NX <= S0;
end if;
when S1 =>
shift_zero <= '1';
NX <= S2;
when S2 =>
shift_zero <= '0';
NX <= S0;
end case;
end process;
process (CR_ONE, one1, stop)
begin
case CR_ONE is
when T0 =>
count_en <= '0';
shift_one <= '0';
data_in <= '0';
one_end <= '1';
if one1 = '1' then
TX <= T1;
else
TX <= T0;
end if;
when T1 =>
count_en <= '1';
shift_one <= '0';
data_in <= '0';
one_end <= '0';
TX <= T2;
when T2 =>
count_en <= '1';
shift_one <= '1';
data_in <= '1';
one_end <= '0';
if stop = '1' then
TX <= T3;
else
TX <= T2;
end if;
when T3 =>
count_en <= '0';
shift_one <= '0';
data_in <= '0';
one_end <= '1';
TX <= T0;
end case;
end process;
shift <= shift_one OR shift_zero;
SH_DONE <= one_end;
END structural;
|
mit
|
e48c9d70e5c84d7e4894e8ebf17a7cd1
| 0.550379 | 2.826087 | false | false | false | false |
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