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int64 1
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int64 137
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| content
stringlengths 137
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stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
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| ratio
float64 1.51
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bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
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class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/gc_command_fifo/example_design/gc_command_fifo_top.vhd
| 1 | 5,162 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: gc_command_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity gc_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end gc_command_fifo_top;
architecture xilinx of gc_command_fifo_top is
SIGNAL clk_i : std_logic;
component gc_command_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(29-1 DOWNTO 0);
DOUT : OUT std_logic_vector(29-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : gc_command_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
e3d9e3edaefd34ee1f21f8a0ae305728
| 0.518404 | 4.897533 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/fifo_generator_v9_3/simulation/fifo_generator_v9_3_synth.vhd
| 1 | 11,066 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v9_3_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_generator_v9_3_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fifo_generator_v9_3_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(25-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fifo_generator_v9_3_dgen
GENERIC MAP (
C_DIN_WIDTH => 25,
C_DOUT_WIDTH => 25,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fifo_generator_v9_3_dverif
GENERIC MAP (
C_DOUT_WIDTH => 25,
C_DIN_WIDTH => 25,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fifo_generator_v9_3_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 25,
C_DIN_WIDTH => 25,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fifo_generator_v9_3_inst : fifo_generator_v9_3_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
apache-2.0
|
afa7b831d2341e5bfc5ae1a98708d250
| 0.461233 | 3.93948 | false | false | false | false |
lvoudour/arty-uart
|
src/fifo_ram.vhd
| 1 | 4,414 |
--------------------------------------------------------------------------------
--
-- RAM based synchronous FIFO
--
-- Signals:
-- clk : clock
-- rst : synchronous reset (active high)
-- din : data input
-- wr_en : write enable
-- full : FIFO full flag
-- dout : data output
-- rd_en : read enable
-- empty : FIFO empty flag
--
-- Parameters:
-- G_DATA_WIDTH : Bit width of the data input/output
-- G_DEPTH : FIFO depth
--
-- Read/Write:
-- dout is valid 1 clk cycle after rd_en goes high. din is written into the
-- FIFO 1 clk cycle after wr_en goes high.
-- Simultaneous rd/wr operations do not change the state of the FIFO (ie. FIFO
-- will not go empty or full)
--
-- Empty/Full flags
-- At reset empty flag is set high and full low. Empty flag goes low 1 clk cycle
-- after the first wr_en and high after the last valid rd_en. Full goes high 1
-- clk cycle after the last valid wr_en and low after the first rd_en.
-- Any subsequent rd_en/wr_en when empty/full respecively is ignored and FIFO
-- state doesn't change (ie. it stays empty or full)
--
-- Arty FPGA board specific notes:
-- Vivado infers a distributed (LUT based) RAM or a BRAM depending on the depth
-- and bit width. Using the default parameters (G_DEPTH=16 anf G_DATA_WIDTH=8)
-- will always infer distributed RAM. Should work with most Xilinx FPGAs.
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity fifo_ram is
generic(
G_DATA_WIDTH : positive := 8;
G_DEPTH : positive := 16
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic_vector(G_DATA_WIDTH-1 downto 0);
wr_en : in std_logic;
full : out std_logic;
dout : out std_logic_vector(G_DATA_WIDTH-1 downto 0);
rd_en : in std_logic;
empty : out std_logic
);
end entity fifo_ram;
architecture rtl of fifo_ram is
constant C_ADDR_WIDTH : natural := natural(ceil(log2(real(G_DEPTH))));
type ram_array is array (G_DEPTH-1 downto 0) of std_logic_vector (G_DATA_WIDTH-1 downto 0);
signal fifo : ram_array := (others=>(others=>'0'));
signal wr_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal rd_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal next_wr_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal next_rd_ptr : unsigned(C_ADDR_WIDTH-1 downto 0) := (others=>'0');
signal empty_r : std_logic := '1';
signal full_r : std_logic := '0';
begin
next_wr_ptr <= wr_ptr + 1;
next_rd_ptr <= rd_ptr + 1;
proc_wr_data:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
wr_ptr <= (others=>'0');
else
-- Write operation is valid when the FIFO is not full or
-- when there's a simultaneous read operation
if (wr_en = '1') and ((full_r = '0') or (rd_en='1')) then
fifo(to_integer(wr_ptr)) <= din;
wr_ptr <= next_wr_ptr;
end if;
end if;
end if;
end process;
proc_rd_data:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
rd_ptr <= (others=>'0');
else
-- Read operation is valid when the FIFO is not empty or
-- when there's a simultaneous write operation
if (rd_en = '1') and ((empty_r = '0') or (wr_en='1')) then
dout <= fifo(to_integer(rd_ptr));
rd_ptr <= next_rd_ptr;
end if;
end if;
end if;
end process;
proc_flags:
process(clk)
begin
if rising_edge(clk) then
if (rst = '1') then
full_r <= '0';
empty_r <= '1';
else
if (wr_en = '1') and (rd_en = '0') then
empty_r <= '0';
if (next_wr_ptr = rd_ptr) then
full_r <= '1';
end if;
elsif (wr_en = '0') and (rd_en = '1') then
full_r <= '0';
if (next_rd_ptr = wr_ptr) then
empty_r <= '1';
end if;
end if;
end if;
end if;
end process;
full <= full_r;
empty <= empty_r;
end architecture rtl;
|
mit
|
f52caf907c25ff60a95fdb7c78996af5
| 0.552333 | 3.369466 | false | false | false | false |
csrhau/sandpit
|
VHDL/tdma_bus/test_byte_bus.vhdl
| 1 | 1,415 |
library ieee;
use ieee.std_logic_1164.all;
entity test_byte_bus is
end test_byte_bus;
architecture behavioural of test_byte_bus is
component byte_bus is
generic (
bus_length : natural
);
port (
clock : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end component byte_bus;
signal clock: std_logic;
signal data_bus : std_logic_vector(7 downto 0);
begin
BBUS: byte_bus generic map(4)
port map (clock, data_bus);
process
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000000"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000001"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000010"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000011"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000000"
report "Writer should cycle back to start" severity error;
wait;
end process;
end behavioural;
|
mit
|
250c067351d72c18ee6674d60d8e628b
| 0.604947 | 3.684896 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RX_RECV_FIFO/example_design/RX_RECV_FIFO_top_wrapper.vhd
| 1 | 18,998 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RX_RECV_FIFO_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity RX_RECV_FIFO_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(4-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(4-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(5-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end RX_RECV_FIFO_top_wrapper;
architecture xilinx of RX_RECV_FIFO_top_wrapper is
SIGNAL clk_i : std_logic;
component RX_RECV_FIFO_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : RX_RECV_FIFO_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
1bcf2cc655afb16dd62fe3cc0874be42
| 0.486156 | 3.965352 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/LEDDecoder.vhd
| 1 | 1,072 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- LEDDecoder.vhd
--
--
--**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LEDDecoder is
Port ( d : in std_logic_vector(3 downto 0);
s : out std_logic_vector(6 downto 0));
end LEDDecoder;
architecture Behavioral of LEDDecoder is
begin
s <= "1110111" when d=x"0" else
"0010010" when d=x"1" else
"1011101" when d=x"2" else
"1011011" when d=x"3" else
"0111010" when d=x"4" else
"1101011" when d=x"5" else
"1101111" when d=x"6" else
"1010010" when d=x"7" else
"1111111" when d=x"8" else
"1111011" when d=x"9" else
"1111110" when d=x"A" else
"0101111" when d=x"B" else
"0001101" when d=x"C" else
"0011111" when d=x"D" else
"1101101" when d=x"E" else
"1101100";
end Behavioral;
|
gpl-3.0
|
57cd8363e619fae947b83cf8593e1dd4
| 0.547575 | 3.152941 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/RECV_REQ_QUEUE/simulation/fg_tb_top.vhd
| 2 | 5,678 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 5
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
73740db999ab0e83721707a48ad86539
| 0.616238 | 4.175 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/FIFO_DDR_DATA_IN/example_design/FIFO_DDR_DATA_IN_top.vhd
| 1 | 5,087 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FIFO_DDR_DATA_IN_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity FIFO_DDR_DATA_IN_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end FIFO_DDR_DATA_IN_top;
architecture xilinx of FIFO_DDR_DATA_IN_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component FIFO_DDR_DATA_IN is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(16-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : FIFO_DDR_DATA_IN PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
2e4d55766d5d2726535e7e2ac39c541f
| 0.519167 | 4.710185 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/cont255_V2.vhd
| 1 | 3,892 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: cont255_V2.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity cont255_V2 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ena: in STD_LOGIC;
fin : out STD_LOGIC
);
end cont255_V2;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of cont255_V2 is
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT incrCuenta8bits_conFin
PORT(
num_in : IN std_logic_vector(7 downto 0);
num_out : OUT std_logic_vector(7 downto 0);
fin : OUT std_logic
);
END COMPONENT;
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal reg_cuenta: std_logic_vector(7 downto 0);
signal reg_cuenta_in: std_logic_vector(7 downto 0);
signal fin_aux: std_logic;
signal ff_fin: std_logic;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
fin <= ff_fin;
incr_0: incrCuenta8bits_conFin PORT MAP(
num_in => reg_cuenta,
num_out => reg_cuenta_in,
fin => fin_aux
);
-----------------------------------------------------------------------------
-- Procesos
-----------------------------------------------------------------------------
-- Biestable de cuenta
p_cuenta: process(rst, clk, ff_fin)
begin
if rst = '1' then
reg_cuenta <= (others => '0');
elsif rising_edge(clk) then
if ff_fin = '0' and ena = '1' then -- Si no ha terminado y esta habilitado
reg_cuenta <= reg_cuenta_in; -- cuenta++
elsif ff_fin = '1' then
reg_cuenta <= (others => '0');
else
reg_cuenta <= reg_cuenta;
end if;
end if;
end process p_cuenta;
-- Biestable ff_fin
p_ff_fin: process(rst, clk, fin_aux)
begin
if rst = '1' then
ff_fin <= '0';
elsif rising_edge(clk) then
if fin_aux = '1' then
ff_fin <= '1';
else
ff_fin <= '0';
end if;
end if;
end process p_ff_fin;
end rtl;
|
gpl-3.0
|
a0b79277b81f9e7cf05b1c262f9d89ac
| 0.432391 | 4.528522 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/GC_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,317 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT GC_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
202537dc0d1df18c87cd4d79cbfffd30
| 0.504109 | 3.930879 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/ssd_command_fifo/simulation/fg_tb_pctrl.vhd
| 20 | 15,357 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-2.0
|
efa713989155cbf039dd56d0bee86a4a
| 0.518982 | 3.374423 | false | false | false | false |
csrhau/sandpit
|
VHDL/tdma_bus/test_bus_writer.vhdl
| 1 | 1,742 |
library ieee;
use ieee.std_logic_1164.all;
entity test_bus_writer is
end test_bus_writer;
architecture behavioural of test_bus_writer is
component bus_writer is
generic (
bus_length : natural;
bus_index : natural;
value : std_logic_vector(7 downto 0)
);
port (
clock : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end component bus_writer;
signal clock : std_logic;
signal data_bus : std_logic_vector(7 downto 0);
begin
WRITER: bus_writer generic map (
bus_length => 3,
bus_index => 1, --- The middle one
value => "11111111"
)
port map (
clock,
data_bus
);
process
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "ZZZZZZZZ"
report "No data should be recieved on tick 0" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "11111111"
report "Data should be recieved on tick 1" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "ZZZZZZZZ"
report "No data should be recieved on tick 2" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "ZZZZZZZZ"
report "No data should be recieved on tick 3" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "11111111"
report "Data should be recieved on tick 4" severity error;
wait;
end process;
end behavioural;
|
mit
|
e23107f0d3ebeb4857ba9c6443be23e0
| 0.546498 | 3.914607 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/pcie_data_rec_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,650 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_rec_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(12-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
79201a2424375268fa6a0ffe4a06cf4b
| 0.502318 | 3.92388 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/TX_SEND_FIFO/simulation/fg_tb_top.vhd
| 3 | 5,679 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 53
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
3dac14a3ea10e89cbc1bdccfe6e56e8f
| 0.616306 | 4.175735 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Finished_Cmd_FIFO/simulation/fg_tb_synth.vhd
| 1 | 9,900 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : Finished_Cmd_FIFO_top
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
e7f1ab896da975889765a1aefbbc0c96
| 0.459293 | 4.168421 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/decrCuenta3bits.vhd
| 1 | 2,057 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: decrCuenta3bits.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decrCuenta3bits is
Port ( num_in : in STD_LOGIC_VECTOR (2 downto 0);
num_out : out STD_LOGIC_VECTOR (2 downto 0));
end decrCuenta3bits;
architecture arq of decrCuenta3bits is
begin
p_outputs: process(num_in)
begin
if num_in = "111" then
num_out <= "110";
elsif num_in = "110" then
num_out <= "101";
elsif num_in = "101" then
num_out <= "100";
elsif num_in = "100" then
num_out <= "011";
elsif num_in = "011" then
num_out <= "010";
elsif num_in = "010" then
num_out <= "001";
elsif num_in = "001" then
num_out <= "000";
else
num_out <= "111";
end if;
end process p_outputs;
end arq;
|
gpl-3.0
|
6e6e2912cec8e64da1d60a5163b1248f
| 0.571706 | 3.85206 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_send_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,651 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_send_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
9601b2925cec57bcd42de2bf3c313ca8
| 0.50236 | 3.924217 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/Move_FIFO_4KB/simulation/fg_tb_synth.vhd
| 1 | 11,215 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 16,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 16,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 16,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : Move_FIFO_4KB_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
a1a8fb5a0a4050c40246c551c7357d28
| 0.454837 | 3.9657 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/read_data_fifo/simulation/fg_tb_pctrl.vhd
| 5 | 18,527 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-2.0
|
def83ae39bae36cfd5c6011beab3979d
| 0.508231 | 3.237854 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_command_rec_fifo/example_design/pcie_command_rec_fifo_top.vhd
| 1 | 5,850 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pcie_command_rec_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pcie_command_rec_fifo_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pcie_command_rec_fifo_top;
architecture xilinx of pcie_command_rec_fifo_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pcie_command_rec_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pcie_command_rec_fifo PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
d7ee43b629297f666e047f075a6328e9
| 0.511966 | 4.657643 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/fantasma3.vhd
| 1 | 10,976 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: fantasma3.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fantasma3 is
Port ( -- Señales generales:
clk_50MHz : in std_logic; -- Reloj
rst : in std_logic; -- Reset
p2Hz : in std_logic; -- Pulso para retrasar el movimiento
ini : in std_logic; -- Fantasma tiene permiso para actualizarse.
fin : out std_logic; -- Fantasma ha terminado de actualizarse.
-- Lecutra de la RAM:
ram_addr_rd : out std_logic_vector(5 downto 0);
ram_data_rd : in std_logic_vector(2 downto 0);
-- Escritura en la RAM:
ram_addr_wr : out std_logic_vector(5 downto 0);
ram_data_wr : out std_logic_vector(2 downto 0);
ram_we : out std_logic;
-- Otros:
bt_rand : in std_logic_vector(1 downto 0)
);
end fantasma3;
architecture arq of fantasma3 is
-- Estados de la FSM:
type t_st is (espera, up_1, up_2, dw_1, dw_2, rg_1, rg_2, lf_1, lf_2, new_pos, wr_pos1, wr_pos2);
signal current_state, next_state : t_st; -- Estados actual y siguiente.
-- Registros con los colores de las posiciones circundantes:
signal ff_up_pos: std_logic_vector(2 downto 0);
signal ff_dw_pos: std_logic_vector(2 downto 0);
signal ff_rg_pos: std_logic_vector(2 downto 0);
signal ff_lf_pos: std_logic_vector(2 downto 0);
-- Senales con las direcciones para acceder a las posiciones circundantes:
signal up_addr: std_logic_vector(5 downto 0);
signal dw_addr: std_logic_vector(5 downto 0);
signal rg_addr: std_logic_vector(5 downto 0);
signal lf_addr: std_logic_vector(5 downto 0);
-- Registros con la posicion del fantasma:
signal my_pos_x: std_logic_vector(2 downto 0);
signal my_pos_y: std_logic_vector(2 downto 0);
signal my_pos_x_in: std_logic_vector(2 downto 0);
signal my_pos_y_in: std_logic_vector(2 downto 0);
-- Señales de carga de registros:
--all_ld <= my_ld & ff_up_ld & ff_dw_ld & ff_rg_ld & ff_lf_ld;
signal all_ld: std_logic_vector(4 downto 0); -- Todas las señales juntas
COMPONENT nueva_pos_rand_async
PORT(
up_pos : IN std_logic_vector(2 downto 0);
dw_pos : IN std_logic_vector(2 downto 0);
rg_pos : IN std_logic_vector(2 downto 0);
lf_pos : IN std_logic_vector(2 downto 0);
my_x : IN std_logic_vector(2 downto 0);
my_y : IN std_logic_vector(2 downto 0);
new_x : OUT std_logic_vector(2 downto 0);
new_y : OUT std_logic_vector(2 downto 0);
bt_rand: in std_logic_vector(1 downto 0)
);
END COMPONENT;
COMPONENT pos_circundantes
PORT(
my_x : IN std_logic_vector(2 downto 0);
my_y : IN std_logic_vector(2 downto 0);
addr_up : OUT std_logic_vector(5 downto 0);
addr_dw : OUT std_logic_vector(5 downto 0);
addr_rg : OUT std_logic_vector(5 downto 0);
addr_lf : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
begin
Inst_nueva_pos_rand: nueva_pos_rand_async PORT MAP(
up_pos => ff_up_pos,
dw_pos => ff_dw_pos,
rg_pos => ff_rg_pos,
lf_pos => ff_lf_pos,
my_x => my_pos_x,
my_y => my_pos_y,
new_x => my_pos_x_in,
new_y => my_pos_y_in,
bt_rand => bt_rand
);
Inst_pos_circundantes: pos_circundantes PORT MAP(
my_x => my_pos_x,
my_y => my_pos_y,
addr_up => up_addr,
addr_dw => dw_addr,
addr_rg => rg_addr,
addr_lf => lf_addr
);
---------------------------------------------------
-- Proceso de calculo del estado siguiente y salidas mealy
---------------------------------------------------
p_next_state : process (current_state, ini, p2Hz) is
begin
case current_state is
when espera =>
if ini = '1' then
next_state <= up_1;
else
next_state <= espera;
end if;
when up_1 =>
next_state <= up_2;
when up_2 =>
next_state <= dw_1;
when dw_1 =>
next_state <= dw_2;
when dw_2 =>
next_state <= rg_1;
when rg_1 =>
next_state <= rg_2;
when rg_2 =>
next_state <= lf_1;
when lf_1 =>
next_state <= lf_2;
when lf_2 =>
-- Comentar para realizar simulaciones.
if p2Hz = '1' then
next_state <= new_pos;
else
next_state <= current_state;
end if;
when new_pos =>
next_state <= wr_pos1;
when wr_pos1 =>
next_state <= wr_pos2;
when wr_pos2 =>
next_state <= espera;
end case;
end process p_next_state;
---------------------------------------------------
-- Proceso de asignación de valores a las salidas
---------------------------------------------------
p_outputs : process (current_state, up_addr, dw_addr, rg_addr, lf_addr, my_pos_y, my_pos_x)
begin
case current_state is
-- Standby
when espera =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '1';
all_ld <= "00000";
-- Leer arriba (1)
when up_1 =>
ram_addr_rd <= up_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer arriba (2)
when up_2 =>
ram_addr_rd <= up_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "01000";
-- Leer abajo (1)
when dw_1 =>
ram_addr_rd <= dw_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer abajo (2)
when dw_2 =>
ram_addr_rd <= dw_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00100";
-- Leer derecha (1)
when rg_1 =>
ram_addr_rd <= rg_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer derecha (2)
when rg_2 =>
ram_addr_rd <= rg_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00010";
-- Leer izquierda (1)
when lf_1 =>
ram_addr_rd <= lf_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Leer izquierda (2)
when lf_2 =>
ram_addr_rd <= lf_addr;
ram_addr_wr <= (others => '0');
ram_data_wr <= (others => '0');
ram_we <= '0';
fin <= '0';
all_ld <= "00001";
-- Calcular nueva posicion
when new_pos =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= my_pos_y & my_pos_x;
ram_data_wr <= "000"; -- COLOR NEGRO
ram_we <= '1';
fin <= '0';
all_ld <= "10000"; -- Aqui tengo que escribirla ya
-- Escribir nueva posicion (1)
when wr_pos1 =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= my_pos_y & my_pos_x;
ram_data_wr <= "110"; -- COLOR AMARILLO
ram_we <= '0';
fin <= '0';
all_ld <= "00000";
-- Escribir nueva posicion (2)
when wr_pos2 =>
ram_addr_rd <= (others => '0');
ram_addr_wr <= my_pos_y & my_pos_x;
ram_data_wr <= "110"; -- COLOR AMARILLO
ram_we <= '1';
fin <= '0';
all_ld <= "00000";
end case;
end process p_outputs;
---------------------------------------------------
-- Proceso de actualizacion del estado
---------------------------------------------------
p_update_state: process (clk_50MHz, rst) is
begin
if rst = '1' then
current_state <= espera;
elsif rising_edge(clk_50MHz) then
current_state <= next_state;
end if;
end process p_update_state;
--------------------------------------------------
-- Procesos de carga y reset de registros
--------------------------------------------------
p_regs: process(clk_50MHz, rst, all_ld)
begin
if rst = '1' then
ff_up_pos <= (others => '0');
ff_dw_pos <= (others => '0');
ff_rg_pos <= (others => '0');
ff_lf_pos <= (others => '0');
my_pos_x <= "110";
my_pos_y <= "110";
elsif rising_edge(clk_50MHz) then
-- Carga la posicion de arriba
if all_ld = "01000" then
ff_up_pos <= ram_data_rd;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga la posicion de abajo
elsif all_ld = "00100" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ram_data_rd;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga la posicion derecha:
elsif all_ld = "00010" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ram_data_rd;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga la posicion izquierda:
elsif all_ld = "00001" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ram_data_rd;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
-- Carga mi propia posicion:
elsif all_ld = "10000" then
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x_in;
my_pos_y <= my_pos_y_in;
-- No carga ninguno
else
ff_up_pos <= ff_up_pos;
ff_dw_pos <= ff_dw_pos;
ff_rg_pos <= ff_rg_pos;
ff_lf_pos <= ff_lf_pos;
my_pos_x <= my_pos_x;
my_pos_y <= my_pos_y;
end if;
end if;
end process p_regs;
end arq;
|
gpl-3.0
|
674804db18e0f2c4de6bee36b29dbc3f
| 0.518313 | 2.914498 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/simulation/data_gen.vhd
| 2 | 5,024 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Data Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: data_gen.vhd
--
-- Description:
-- Data Generator
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY DATA_GEN IS
GENERIC ( DATA_GEN_WIDTH : INTEGER := 32;
DOUT_WIDTH : INTEGER := 32;
DATA_PART_CNT : INTEGER := 1;
SEED : INTEGER := 2
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR
);
END DATA_GEN;
ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS
CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8);
SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0);
SIGNAL LOCAL_CNT : INTEGER :=1;
SIGNAL DATA_GEN_I : STD_LOGIC :='0';
BEGIN
LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0);
DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH));
DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE (CLK)) THEN
IF(EN ='1' AND (DATA_PART_CNT =1)) THEN
LOCAL_CNT <=1;
ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN
IF(LOCAL_CNT = 1) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN
LOCAL_CNT <= LOCAL_CNT+1;
ELSE
LOCAL_CNT <= 1;
END IF;
ELSE
LOCAL_CNT <= 1;
END IF;
END IF;
END PROCESS;
RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
RAND_GEN_INST:ENTITY work.RANDOM
GENERIC MAP(
WIDTH => 8,
SEED => (SEED+N)
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DATA_GEN_I,
RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N)
);
END GENERATE RAND_GEN;
END ARCHITECTURE;
|
gpl-2.0
|
ddfc73ee40c3b841c8af6c0234bfa1e0
| 0.581608 | 4.279387 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_data_rec_fifo/simulation/fg_tb_synth.vhd
| 1 | 11,825 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(11-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_data_rec_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
056eb4d7293df2818965190034fab7a7
| 0.455814 | 3.97212 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_command_send_fifo/simulation/fg_tb_synth.vhd
| 1 | 11,717 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : pcie_command_send_fifo_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
7a79018fa4ad002c0f9664f91cd8f35c
| 0.456772 | 3.965144 | false | false | false | false |
gxliu/ARM-Cortex-M0
|
hdl/extnd.vhd
| 1 | 817 |
library ieee;
use ieee.std_logic_1164.all;
entity extnd is
port ( input : in std_logic_vector (31 downto 0);
sign : in std_logic; -- 1:sign 0:zero extend
byte : in std_logic; -- 1:byte 0:halfword extend
outpt : out std_logic_vector (31 downto 0));
end extnd;
architecture Behavioral of extnd is
begin
outpt(7 downto 0 ) <= input(7 downto 0);
outpt(15 downto 8 ) <= input(15 downto 8) when byte = '0' else
(15 downto 8 => input(7)) when sign = '1' else
(15 downto 8 => '0');
outpt(31 downto 16) <= (31 downto 16 => '0') when sign = '0' else
(31 downto 16 => input(7)) when byte = '1' else
(31 downto 16 => input(15));
end Behavioral;
|
mit
|
fc29d32d4c91cf345874d4937d25f01f
| 0.516524 | 3.599119 | false | false | false | false |
lvoudour/arty-uart
|
sim/tb_uart.vhd
| 1 | 5,915 |
--------------------------------------------------------------------------------
--
-- UART Loopback Testbench
--
-- Self checking testbench that wires the UART in loopback configuration (Rx
-- data is echoed back to Tx). An ASCII text is transmitted from the external
-- device and the testbench checks that the same text is received by the
-- external device.
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb_uart is
end entity tb_uart;
architecture behv of tb_uart is
------------------------------------------
-- uart_tx
------------------------------------------
-- Emulates an external UART device Tx
-- txdata : Data to transmit
-- tx : Tx data line
-- T_UART : UART period (bit duration)
procedure uart_tx (
variable txdata : in std_logic_vector(7 downto 0);
signal tx : inout std_logic;
constant T_UART : in time) is
begin
tx <= '0'; -- start bit
wait for T_UART;
for i in 0 to 7 loop
tx <= txdata(i);
wait for T_UART;
end loop;
tx <= '1'; -- stop bit
wait for T_UART;
end uart_tx;
------------------------------------------
-- uart_rx
------------------------------------------
-- Emulates an external UART device Rx
-- rx : Rx data line
-- rxdata : Data received
-- T_UART : UART period (bit duration)
procedure uart_rx (
signal rx : in std_logic;
variable rxdata : out std_logic_vector(7 downto 0);
constant T_UART : in time) is
begin
wait until falling_edge(rx);
wait for T_UART/2;
for n in 0 to 7 loop
wait for T_UART;
rxdata(n) := rx;
end loop;
wait for T_UART;
assert (rx = '1') report "Incorrect UART stop bit" severity error;
end uart_rx;
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
constant C_UART_PERIOD : time := 800 ns; -- 1.25 Mbaud
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal tx_i : std_logic := '1';
signal tx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal tx_data_wr_i : std_logic := '0';
signal tx_fifo_full_i : std_logic := '0';
signal rx_i : std_logic := '1';
signal rx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal rx_data_rd_i : std_logic := '0';
signal rx_fifo_empty_i : std_logic := '0';
signal transmitted_text : string(1 to 9) := "TEST_1234";
begin
clk <= not clk after C_CLK_PERIOD/2;
rst <= '1', '0' after 1000 ns;
-- Loopback. Connect rx fifo output to tx fifo input
tx_data_i <= rx_data_i;
-- External device UART transmitter
proc_external_uart_tx:
process
variable txdata : std_logic_vector(7 downto 0) := (others=>'0');
begin
wait until falling_edge(rst);
-- transmit each character of the string (least significant char first)
for n in transmitted_text'range loop
wait for 133 ns; -- wait some arbitrary amount of time
txdata := std_logic_vector(to_unsigned(character'pos(transmitted_text(n)), 8));
uart_tx(txdata, rx_i, C_UART_PERIOD);
end loop;
wait;
end process;
-- Read/Write UART Rx/Tx FIFOs
proc_loopback:
process
begin
wait until falling_edge(rst);
-- Repeat for every character
for n in transmitted_text'range loop
-- wait until rx fifo has some data
if (rx_fifo_empty_i='1') then
wait until rx_fifo_empty_i = '0';
end if;
-- Read pulse
wait until rising_edge(clk);
rx_data_rd_i <= '1';
wait until rising_edge(clk);
rx_data_rd_i <= '0';
-- check if tx fifo is full before writing
-- any data (not really necessary in loopback
-- configuration)
if (tx_fifo_full_i = '1') then
wait until tx_fifo_full_i = '0';
end if;
-- Write pulse
wait until rising_edge(clk);
tx_data_wr_i <= '1';
wait until rising_edge(clk);
tx_data_wr_i <= '0';
end loop;
wait;
end process;
-- External device UART receiver
proc_external_uart_rx:
process
variable rxdata : std_logic_vector(7 downto 0) := (others=>'0');
variable received_text : string(transmitted_text'range);
begin
-- Receive characters and store them in a string
for n in transmitted_text'range loop
uart_rx(tx_i, rxdata, C_UART_PERIOD);
received_text(n) := character'val(to_integer(unsigned(rxdata)));
end loop;
-- Fail simulation if received text is not equal to the transmitted text
assert (received_text = transmitted_text)
report "Received text: " & received_text & " is not equal to trasmitted text: " & transmitted_text
severity failure;
-- All is well. Report success
assert false
report "Successfuly received transmitted text: " & received_text
severity note;
wait;
end process;
------------------------------------------------
-- UART
------------------------------------------------
uart_inst : entity work.uart(rtl)
generic map(
G_BAUD_RATE => 1250000,
G_CLOCK_FREQ => 100.0e6
)
port map(
clk => clk,
rst => rst,
tx_data_in => tx_data_i,
tx_data_wr_in => tx_data_wr_i,
tx_fifo_full_out => tx_fifo_full_i,
tx_out => tx_i,
rx_in => rx_i,
rx_data_rd_in => rx_data_rd_i,
rx_data_out => rx_data_i,
rx_fifo_empty_out => rx_fifo_empty_i
);
end architecture behv;
|
mit
|
6bd6c8fd1957ca05aa394e5d4302518d
| 0.542857 | 3.774729 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RAM_WRITE/simulation/bmg_tb_synth.vhd
| 1 | 8,361 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_TB IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE BMG_TB_ARCH OF BMG_TB IS
COMPONENT RAM_WRITE_top
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(255 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(255 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC;
SIGNAL RESET_SYNC_R2 : STD_LOGIC;
SIGNAL RESET_SYNC_R3 : STD_LOGIC;
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC;
SIGNAL RESETB_SYNC_R2 : STD_LOGIC;
SIGNAL RESETB_SYNC_R3 : STD_LOGIC;
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_buf: bufg
PORT map(
i => CLK_IN,
o => clk_in_i
);
CLKA <= clk_in_i;
clkb_buf: bufg
PORT map(
i => CLKB_IN,
o => clkb_in_i
);
CLKB <= clkb_in_i;
RSTA <= RESET_IN;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESET_IN;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 256,
READ_WIDTH => 256 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECK_DATA_TDP(0),
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECK_DATA_TDP(1),
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
BMG_PORT: RAM_WRITE_top PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
gpl-2.0
|
e9d6fb09a13451f34e7cb2fbf7a7aebb
| 0.569549 | 3.709406 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/RD_DATA_FIFO/simulation/fg_tb_pctrl.vhd
| 1 | 18,258 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 12 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
gpl-2.0
|
be81f89a4e0d95bbf0d46c892b8aad91
| 0.508325 | 3.246444 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/controller_command_fifo/simulation/fg_tb_synth.vhd
| 2 | 10,036 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(5-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : controller_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
a76bb760fd68b2347a948981ff1bc70d
| 0.459247 | 4.172973 | false | false | false | false |
bitflippersanonymous/fpga-camera
|
src/digital_camera.vhd
| 1 | 9,315 |
--**********************************************************************************
-- Copyright 2013, Ryan Henderson
-- CMOS digital camera controller and frame capture device
--
-- digital_camera.vhd
--
-- Top level file for the project
--
-- ppd(7) is tied to program pin. 0 is clk
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.comp_pckgs.all;
ENTITY digital_camera IS
PORT(
--Test Ports
init_cycle_complete_test_port: out std_logic;
-- XSA-100 MISC
clkin : in std_logic;
rst : in std_logic;
s : out std_logic_vector(6 downto 0); -- Segments
ce_n : out std_logic; -- Flash enable
dips : in std_logic_vector(3 downto 0); -- 4 Dip switches
pps : out std_logic_vector(6 downto 3); -- pport status pins for upload
ppd : in std_logic_vector(6 downto 0); -- pport data pins for download
-- XSA-100 SDRAM
sclkfb : in std_logic;
sclk : out std_logic;
cke : out std_logic; -- clock-enable to SDRAM
cs_n : out std_logic; -- chip-select to SDRAM
ras_n : out std_logic; -- command input to SDRAM
cas_n : out std_logic; -- command input to SDRAM
we_n : out std_logic; -- command input to SDRAM
ba : out unsigned(1 downto 0); -- SDRAM bank address bits
sAddr : out unsigned(12-1 downto 0); -- SDRAM row/column address
sData : inout unsigned(16-1 downto 0);-- SDRAM in/out databus
dqmh : out std_logic; -- high databits I/O mask
dqml : out std_logic; -- low databits I/O mask
--KAC-1310
mclk_KAC : out std_logic;
init_KAC : out std_logic;
--sync_KAC : out std_logic; --Can also be done through I2C. Save pins
sof_KAC : in std_logic;
vclk_KAC : in std_logic;
hclk_KAC : in std_logic;
pix_KAC : in std_logic_vector(9 downto 0);
scl : inout std_logic;
sda : inout std_logic
);
END digital_camera;
ARCHITECTURE digital_camera_arch OF digital_camera IS
-- Signals arranged by who outputs them
-- pport_01
signal clk_pp : std_logic;
signal cmd : std_logic_vector(5 downto 0);
signal pp_fifo_need_data : std_logic;
-- MCSG_01
signal start_upload : std_logic;
signal abort_upload : std_logic;
signal start_addr_upload : std_logic_vector(22 downto 0);
signal end_addr_upload : std_logic_vector(22 downto 0);
signal start_KAC : std_logic;
signal r_w_KAC : std_logic;
signal Data_KAC_in : std_logic_vector(7 downto 0);
signal Addr_KAC : std_logic_vector(7 downto 0);
signal init_cycle_complete : std_logic;
-- ram_control_0
signal ram_to_pp_data : std_logic_vector(15 downto 0);
signal pp_fifo_wr_en : std_logic;
-- KAC_I2C_01
signal done_KAC : std_logic;
signal Data_KAC_out : std_logic_vector(7 downto 0);
-- KAC_data
signal rd_en_KAC : std_logic;
signal dout_KAC : std_logic_vector(15 downto 0);
signal dump_data_req_KAC : std_logic;
signal start_new_frame : std_logic;
-- Misc used by led decoder
signal display_output : std_logic_vector(3 downto 0);
-- inphase_clks
signal rst_int : std_logic;
signal clk_12_5Mhz : std_logic;
signal clk_50Mhz : std_logic;
signal clk_100Mhz : std_logic;
-- IBUFGs
signal bufclkin : std_logic;
signal bufsclkfb : std_logic;
signal bufhclk_KAC : std_logic;
constant KAC_I2C_ADDR : std_logic_vector(6 downto 0) := "0110011";
constant DS1621_I2C_ADDR : std_logic_vector(6 downto 0) := "1001111";
BEGIN
ce_n <= '1';
mclk_KAC <= clk_12_5Mhz;
--test port for sim
-- init_cycle_complete_test_port <= init_cycle_complete; -- for test bench 'z'
init_cycle_complete_test_port <= 'Z' ;
--SDRAM Test
display_output <= "00" & pix_KAC(9 downto 8) when dips = "0111" else
pix_KAC(7 downto 4) when dips = "1011" else
pix_KAC(3 downto 0) when dips = "1101" else
"0000";
-- Just so I can use pin 18 which is a clock input, I need to put it on a global
-- buffer.
ibufghclk: IBUFG port map(I=>hclk_KAC, O=>bufhclk_KAC);
ibufclkin: IBUFG port map(I=>clkin, O=>bufclkin);
ibufsclkfb: IBUFG port map(I=>sclkfb, O=>bufsclkfb);
inphase_clks: clock_generation
PORT MAP
(
bufclkin => bufclkin,
rst_n => rst,
bufsclkfb => bufsclkfb,
rst_int => rst_int,
clk_12_5Mhz => clk_12_5Mhz,
clk_50Mhz => clk_50Mhz,
clk_100Mhz => clk_100Mhz,
sclk => sclk
);
see_somptin: LEDDecoder
PORT MAP
(
d => display_output,
s => s
);
-- Generate a 12.5Mhz clock for the image sensor. Do this division with a dll so it
-- is not skewed. Moved skew from 4ns to 2ns
-- generate_m_clk_KAC: clockdivider
-- GENERIC MAP ( divide_by => 5)
-- PORT MAP
-- (
-- clk => clkin,
-- rst => rst,
-- slow_clk => clk_12_5Mhz
-- );
--
-- clk_50Mhz <= clkin;
-- sclk <= bufsclkfb; --clkin;
-- bufhclk_KAC <= hclk_KAC;
-- Control module. Generates control signals based on commands from pc
-- Controls KAC_I2C_01 and pport_01 modules
MCSG_01: master_control_signal_generator -- um, my names are getting a little out of hand
port map
(
clk_50Mhz => clk_50Mhz, -- in system clk
clk_12_5Mhz => clk_12_5Mhz, -- in same as mclk
clk_pp => clk_pp, -- in debounced clk from pport
rst => rst, -- in push button reset
cmd => cmd, -- in cmds from pp_upload
start_upload => start_upload, -- out signal pp_upload to start
abort_upload => abort_upload, -- out signal pp_upload to abort
start_addr => start_addr_upload, -- out where in memory to start upload
end_addr => end_addr_upload, -- out where in memory to stop
init_cycle_complete => init_cycle_complete, -- out wait for sensor & sdram
init_KAC => init_KAC, -- out resets image sensor
--sync_KAC => sync_KAC, -- out KAC sync pin
start_KAC => start_KAC,
done_KAC => done_KAC,
r_w_KAC => r_w_KAC,
Addr_KAC => Addr_KAC,
Data_KAC_in => Data_KAC_in, -- Data to send by i2c
Data_KAC_out => Data_KAC_out -- Data back from i2c ...
);
-- I2C interface tailored to read and write byte wide registers in the KAC
-- device.
KAC_I2C_01: KAC_i2c
GENERIC MAP (I2C_ADDR => KAC_I2C_ADDR)
PORT MAP
(
clk => clk_50Mhz, -- in system clk
nReset => rst, -- in push button reset
start_KAC => start_KAC, -- in start I2C transfer
done_KAC => done_KAC, -- out I2C transfer done
r_w_KAC => r_w_KAC, -- in direction of transfer 0 read 1 write
Addr_KAC => Addr_KAC, -- in Address of register in I2C device
Data_KAC_in => Data_KAC_in, -- in data to write at addressed register
Data_KAC_out => Data_KAC_out, -- out data read from addressed register
SCL => SCL, -- inout I2C clock line
SDA => SDA -- inout I2C data line
);
-- KAC pixel reader and formatter
KAC_data_01: KAC_data
port map
(
clk_50Mhz => clk_50Mhz, -- : in std_logic;
clk_12_5Mhz => clk_12_5Mhz, -- : in std_logic;
rst => rst, -- : in std_logic;
-- Internal logic I/O
rd_en => rd_en_KAC, -- : in std_logic;
dout => dout_KAC, -- : out std_logic_vector(15 downto 0);
dump_data_req => dump_data_req_KAC, -- : out std_logic;
start_new_frame => start_new_frame,
init_cycle_complete => init_cycle_complete,
-- KAC-1310 I/O
sof_KAC => sof_KAC,
vclk_KAC => vclk_KAC,
hclk_KAC => bufhclk_KAC,
pix_KAC => pix_KAC -- : in std_logic_vector(9 downto 0)
);
--PPort Module
pport_01: pp_upload
port map
(
clk_50Mhz => clk_50Mhz, -- in system clk
clk_pp => clk_pp, -- out debounced clk from pport
rst => rst, -- in push button reset
pps => pps, -- out parallel port status pins
ppd => ppd, -- in parallel port data pins including non-debounced clock
upload_data => ram_to_pp_data, -- in input to fifo
cmd => cmd, -- out command from the pc to mcsg
start_upload => start_upload, -- reset fifo on upload start
wr_en => pp_fifo_wr_en, -- in control when to write to the fifo
need_data => pp_fifo_need_data -- out flag that fifo is almost empty
);
ram_control_01: ram_control
PORT MAP
(
clk_50Mhz => clk_50Mhz, -- : in std_logic;
rst => rst, -- : in std_logic;
-- PPort
pp_data_out => ram_to_pp_data, -- : out ..._vector(15 downto 0);
start_upload => start_upload, -- : in std_logic;
abort_upload => abort_upload, -- : in std_logic;
start_addr_upload => start_addr_upload, -- : in ..._vector(22 downto 0);
end_addr_upload => end_addr_upload, -- : in ..._vector(22 downto 0);
pp_fifo_wr_en => pp_fifo_wr_en, -- : out std_logic;
pp_fifo_need_data => pp_fifo_need_data, -- : in std_logic;
-- KAC_data
rd_en_KAC => rd_en_KAC, -- : in std_logic;
dout_KAC => dout_KAC, -- : out ..._vector(15 downto 0);
dump_data_req_KAC => dump_data_req_KAC, -- : out std_logic;
start_new_frame => start_new_frame,
-- SDRAM Controller stuff
cke => cke, -- out clock-enable to SDRAM
cs_n => cs_n, -- out chip-select to SDRAM
ras_n => ras_n, -- out command input to SDRAM
cas_n => cas_n, -- out command input to SDRAM
we_n => we_n, -- out command input to SDRAM
ba => ba, -- out SDRAM bank address bits
sAddr => sAddr, -- out SDRAM row/column address
sData => sData, -- inout SDRAM in/out databus
dqmh => dqmh, -- out high databits I/O mask
dqml => dqml -- out low databits I/O mask
);
END digital_camera_arch;
|
gpl-3.0
|
d97b7e0507abeaf725b1a2dbbe2b0902
| 0.621041 | 2.79982 | false | false | false | false |
gxliu/ARM-Cortex-M0
|
hdl/regfile_no_clk.vhd
| 1 | 1,170 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity regfile_no_clk is
port ( clk : in std_logic;
write_en: in std_logic;
addr_r1 : in std_logic_vector (3 downto 0);
addr_r2 : in std_logic_vector (3 downto 0);
addr_w1 : in std_logic_vector (3 downto 0);
data_w1 : in std_logic_vector (31 downto 0);
pc_next : in std_logic_vector (31 downto 0);
data_r1 : out std_logic_vector (31 downto 0);
data_r2 : out std_logic_vector (31 downto 0);
data_pc : out std_logic_vector (31 downto 0));
end regfile_no_clk;
architecture Behavioral of regfile_no_clk is
type type_reg_file is array(15 downto 0) of std_logic_vector(31 downto 0) ;
signal reg_file : type_reg_file := (others => (others => '0'));
begin
write_port : process(clk)
begin
if rising_edge(clk) then
if write_en = '1' then
reg_file(conv_integer(addr_w1)) <= data_w1;
end if;
reg_file(15) <= pc_next;
end if;
end process;
data_r1 <= reg_file(conv_integer(addr_r1));
data_r2 <= reg_file(conv_integer(addr_r2));
data_pc <= reg_file(15);
end Behavioral;
|
mit
|
30252e5a0a76bed2f6da06f5de159ec1
| 0.617094 | 2.917706 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/controller_command_fifo/example_design/controller_command_fifo_top.vhd
| 1 | 5,053 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: controller_command_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity controller_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end controller_command_fifo_top;
architecture xilinx of controller_command_fifo_top is
SIGNAL clk_i : std_logic;
component controller_command_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : controller_command_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
1299a04ce3f36c6b3cc5b63612c3fa98
| 0.528795 | 4.944227 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/rx_data_fifo/example_design/rx_data_fifo_top_wrapper.vhd
| 1 | 19,338 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rx_data_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity rx_data_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end rx_data_fifo_top_wrapper;
architecture xilinx of rx_data_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component rx_data_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : rx_data_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
6a798f29a4c14b484da5bba20bcfde25
| 0.484745 | 3.977376 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/tx_buf/example_design/tx_buf_top_wrapper.vhd
| 1 | 19,302 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: tx_buf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity tx_buf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end tx_buf_top_wrapper;
architecture xilinx of tx_buf_top_wrapper is
SIGNAL clk_i : std_logic;
component tx_buf_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : tx_buf_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
c4ec2f7aa627d8aab05e2ef9f961ab93
| 0.484095 | 3.979794 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/tx_buf/example_design/tx_buf_top.vhd
| 1 | 5,271 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: tx_buf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity tx_buf_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end tx_buf_top;
architecture xilinx of tx_buf_top is
SIGNAL clk_i : std_logic;
component tx_buf is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : tx_buf PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
f497c3254c248b1a8825715610530249
| 0.512996 | 4.907821 | false | false | false | false |
csrhau/sandpit
|
VHDL/striped_gol/test_sequencer.vhdl
| 1 | 5,690 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_sequencer is
constant ADDR_BITS: natural := 3;
constant ROWS: natural := 8;
type input_deck is array(integer range <>) of std_logic_vector(9 downto 0);
type output_deck is array(integer range <>) of std_logic_vector(7 downto 0);
end test_sequencer;
architecture behavioural of test_sequencer is
component sequencer is
generic (
rows : natural;
addr_bits : natural
);
port (
clock : in std_logic;
input : in std_logic_vector(9 downto 0);
output: out std_logic_vector(8 downto 1);
address : out std_logic_vector(addr_bits-1 downto 0);
write_enable : out std_logic
);
end component sequencer;
constant test_input : input_deck(0 to 7) := (
0 => "1110000111",
1 => "0000000001",
2 => "0000000010",
3 => "0000000011",
4 => "1110001000",
5 => "1010011100",
6 => "1110001000",
7 => "0000000000"
);
constant test_output: output_deck(2 to 9) := (
2 => "10000001",
3 => "10000001",
4 => "10000010",
5 => "00000001",
6 => "10000011",
7 => "01001101",
8 => "00101010",
9 => "01001110"
);
signal clock : std_logic;
signal write_enable : std_logic;
signal input : std_logic_vector(9 downto 0);
signal output : std_logic_vector(8 downto 1);
signal address : std_logic_vector(ADDR_BITS-1 downto 0);
begin
SEQ: sequencer generic map(rows => ROWS, addr_bits => ADDR_BITS)
port map(clock, input, output, address, write_enable);
process
begin
wait for 1 ns;
assert address = "111"
report "T0 read address should be last row of RAM" severity error;
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
input <= test_input(to_integer(unsigned(address)));
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_INIT -> SEQ_FIRST_ROW
wait for 1 ns; -- Here, the data_in will match the last line of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "000"
report "T1 read address should be row 0 of RAM" severity error;
input <= test_input(to_integer(unsigned(address)));
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_FIRST_ROW -> SEQ_UPDATE
wait for 1 ns; -- Here, data_in will match line 0 of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "001"
report "T2 read address should be row 1 of RAM" severity error;
input <= test_input(to_integer(unsigned(address)));
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_UPDATE -> SEQ advance
wait for 1 ns;
assert write_enable = '1'
report "T3 should write out the first calculation" severity error;
assert address = "000"
report "T3 should write to row 0" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_advance -> SEQ_update
wait for 1 ns;
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "010"
report "T4 read address should be row 2 of RAM" severity error;
for i in 1 to 5 loop
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert write_enable = '1'
report "Update should write out a result" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert write_enable = '0'
report "Advance should schedule input" severity error;
end loop;
-- This is the interesting bit
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_UPDATE -> SEQ_FLUSH
wait for 1 ns;
assert write_enable = '1'
report "Tn should write out the nnd calculation" severity error;
assert address = "110"
report "Tn should write to row 3" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_FLUSH -> SEQ_INIT
wait for 1 ns;
assert write_enable = '1'
report "Write should be enabled for the final flush" severity error;
assert address = "111"
report "The final flush should write to the final row" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_INIT -> SEQ_FIRST_ROW
wait for 1 ns; -- Here, the data_in will match the last line of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "000"
report "T1 read address should be row 0 of RAM" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_FIRST_ROW -> SEQ_UPDATE
wait for 1 ns; -- Here, data_in will match line 0 of the GOL strip
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "001"
report "T2 read address should be row 1 of RAM" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_UPDATE -> SEQ advance
wait for 1 ns;
assert write_enable = '1'
report "T3 should write out the first calculation" severity error;
assert address = "000"
report "T3 should write to row 0" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1'; -- SEQ_advance -> SEQ_update
wait for 1 ns;
assert write_enable = '0'
report "Write should be disabled at this point" severity error;
assert address = "010"
report "T4 read address should be row 2 of RAM" severity error;
wait;
end process;
end behavioural;
|
mit
|
db890eefc63593ca11fcc87f7f91eea2
| 0.61529 | 3.758256 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/GC_fifo/example_design/GC_fifo_top.vhd
| 1 | 4,953 |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: GC_fifo_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity GC_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end GC_fifo_top;
architecture xilinx of GC_fifo_top is
SIGNAL clk_i : std_logic;
component GC_fifo is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : GC_fifo PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
gpl-2.0
|
638fd8a99548eb0dfa84a68f71008829
| 0.520493 | 4.90396 | false | false | false | false |
albertomg994/VHDL_Projects
|
AmgPacman/src/freqDividerV3.vhd
| 1 | 4,338 |
-- ========== Copyright Header Begin =============================================
-- AmgPacman File: freqDividerV3.vhd
-- Copyright (c) 2015 Alberto Miedes Garcés
-- DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
--
-- The above named program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- The above named program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Foobar. If not, see <http://www.gnu.org/licenses/>.
-- ========== Copyright Header End ===============================================
----------------------------------------------------------------------------------
-- Engineer: Alberto Miedes Garcés
-- Correo: [email protected]
-- Create Date: January 2015
-- Target Devices: Spartan3E - XC3S500E - Nexys 2 (Digilent)
----------------------------------------------------------------------------------
-- Notas adicinales:
----------------------------------------------------------------------------------
-- IMPORTANTE: las salidas clk_1KHz, clk_100Hz y clk_2Hz mandan pulsos, no el reloj
-- completo. Tengo pendiente acabarlo. La frecuencia de entrada al modulo debe ser 50MHz,
-- que es la frecuencia de reloj de la Nexys2.
----------------------------------------------------------------------------------
-- Reporte de sintesis:
----------------------------------------------------------------------------------
-- Minimum period: 5.085ns (Maximum Frequency: 196.638MHz).
-- Codigo del divisor libre de warnings (en principio).
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- =================================================================================
-- ENTITY
-- =================================================================================
entity freqDividerV3 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
clk_1KHz : out STD_LOGIC;
pulso_2Hz: out std_logic
);
end freqDividerV3;
-- =================================================================================
-- ARCHITECTURE
-- =================================================================================
architecture rtl of freqDividerV3 is
-----------------------------------------------------------------------------
-- Declaracion de senales
-----------------------------------------------------------------------------
signal pulso_1KHz_aux: std_logic;
signal pulso_100Hz_aux: std_logic;
-----------------------------------------------------------------------------
-- Componentes
-----------------------------------------------------------------------------
COMPONENT modulo1KHz
PORT(
clk_50MHz : IN std_logic;
rst : IN std_logic;
clk_1KHz : OUT std_logic;
pulso_1KHz : OUT std_logic
);
END COMPONENT;
COMPONENT modulo100Hz
PORT(
clk_50MHz : IN std_logic;
ena : IN std_logic;
rst: in std_logic;
pulso_100Hz : OUT std_logic
);
END COMPONENT;
COMPONENT modulo2Hz
PORT(
clk_50MHz : IN std_logic;
ena : IN std_logic;
rst : IN std_logic;
pulso_2Hz : OUT std_logic
);
END COMPONENT;
begin
-----------------------------------------------------------------------------
-- Conexion de senales
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Conexion de componentes
-----------------------------------------------------------------------------
Inst_modulo1KHz: modulo1KHz PORT MAP(
clk_50MHz => clk,
rst => rst,
clk_1KHz => clk_1KHz,
pulso_1KHz => pulso_1KHz_aux
);
modulo100Hz_0: modulo100Hz PORT MAP(
clk_50MHz => clk,
ena => pulso_1KHz_aux,
rst => rst,
pulso_100Hz => pulso_100Hz_aux
);
modulo2Hz_0: modulo2Hz PORT MAP(
clk_50MHz => clk,
ena => pulso_100Hz_aux,
rst => rst,
pulso_2Hz => pulso_2Hz
);
end rtl;
|
gpl-3.0
|
fce56e36f48fbd4befd61778705ddec4
| 0.438653 | 4.833891 | false | false | false | false |
asm2750/Neopixel_TX_Core
|
demo/mojo_ise_project/ipcore_dir/clk_wiz_v3_6/simulation/clk_wiz_v3_6_tb.vhd
| 1 | 6,153 |
-- file: clk_wiz_v3_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clk_wiz_v3_6_tb is
end clk_wiz_v3_6_tb;
architecture test of clk_wiz_v3_6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 20.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clk_wiz_v3_6_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clk_wiz_v3_6_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
apache-2.0
|
97965db7b4c6754fb0f610c89e97339a
| 0.637413 | 4.208618 | false | false | false | false |
P3Stor/P3Stor
|
pcie/IP core/pcie_command_rec_fifo/simulation/fg_tb_pkg.vhd
| 1 | 11,597 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_command_rec_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(9-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
gpl-2.0
|
e1117b336bd2b86089d64d5110fe4b99
| 0.503061 | 3.920554 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/rx_data_fifo/simulation/fg_tb_synth.vhd
| 1 | 10,795 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(7-1 DOWNTO 0);
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 6,
C_RD_PNTR_WIDTH => 6,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : rx_data_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
gpl-2.0
|
989368456203b50b4ce38a83d226a77b
| 0.458824 | 4.123377 | false | false | false | false |
ARC-Lab-UF/volunteer_files
|
cache.vhd
| 1 | 9,725 |
-- Greg Stitt
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
-------------------------------------------------------------------------------
-- Generics Description
-- num_sets : The number of sets in the cache.
-- word_width : The number of bits in a "word," where a word is the unit of
-- data read from and written to the cache.
-- words_per_block : The number of words in a block. (CURRENTLY NOT SUPPORTED)
-- addr_width : The number of bits in the address being looked up in the cache.
-- Must be >= clog2(num_blocks).
-- associativity : The number of blocks per set.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Port Description:
-- clk : Clock input
-- rst : Reset (active high)
-- en : Enable input (active high), stalls the pipeline when '0'
-- wr_addr : The address to write data to when handling a miss
-- wr_data : Input for providing data to the cache on a miss
-- wr_en : Assert to write wr_data to wr_addr in cache
-- rd_addr : The address to read from in the cache
-- rd_data : The output from the cache on a hit
-- rd_data_valid : Asserted when rd_data contains valid data. Will remain
-- asserted for 1 cycle unless en='0'
-- ready : Asserted (active high) when cache can accept new address requests.
-- When not asserted, all inputs are ignored.
-------------------------------------------------------------------------------
entity cache is
generic (
num_sets : positive := 16;
word_width : positive := 8;
words_per_block : positive := 1;
addr_width : positive := 16;
associativity : positive := 1);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
rd_addr : in std_logic_vector(addr_width-1 downto 0);
rd_en : in std_logic;
rd_data : out std_logic_vector(word_width-1 downto 0);
rd_data_valid : out std_logic;
ready : out std_logic;
-- Signals for handling misses
wr_addr : in std_logic_vector(addr_width-1 downto 0);
wr_data : in std_logic_vector(word_width*words_per_block-1 downto 0);
wr_way_id : in std_logic_vector(bitsNeeded(associativity)-1 downto 0);
wr_en : in std_logic;
miss : out std_logic;
miss_addr : out std_logic_vector(addr_width-1 downto 0);
miss_valid_ways : out std_logic_vector(associativity-1 downto 0)
);
end cache;
architecture default of cache is
constant DATA_WIDTH : positive := word_width*words_per_block;
constant TAG_WIDTH : positive := addr_width - bitsNeeded(num_sets);
subtype TAG_RANGE is natural range addr_width-1 downto addr_width-TAG_WIDTH;
constant BLOCK_WIDTH : positive := 1+TAG_WIDTH+DATA_WIDTH;
constant SET_WIDTH : positive := BLOCK_WIDTH*associativity;
--constant NUM_SETS : positive := integer(ceil(real(num_sets)/real(associativity)));
type block_array is array (associativity-1 downto 0) of std_logic_vector(BLOCK_WIDTH-1 downto 0);
signal ram_out : block_array;
signal way : block_array;
signal rd_addr_delayed : std_logic_vector(rd_addr'range);
signal rd_addr_r : std_logic_vector(rd_addr'range);
signal wr_data_complete : std_logic_vector(wr_data'length+TAG_WIDTH downto 0);
signal valid : std_logic_vector(associativity-1 downto 0);
signal way_tag_eq : std_logic_vector(associativity-1 downto 0);
signal way_hit : std_logic_vector(associativity-1 downto 0);
type way_data_array is array (associativity-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal way_data : way_data_array;
signal hit : std_logic;
signal request_valid : std_logic;
signal ready_s : std_logic;
signal miss_handled : std_logic;
signal data_ready : std_logic;
signal hit_r : std_logic;
signal hit_data : std_logic_vector(rd_data'range);
signal hit_data_r : std_logic_vector(rd_data'range);
signal way_wr_en : std_logic_vector(associativity-1 downto 0);
begin
assert(words_per_block = 1) severity failure;
-- Wwrite to the cache the valid bit, the tag, and the actual wr data
wr_data_complete <= '1' & wr_addr(TAG_RANGE) & wr_data;
-- RAM to implement each way of the cache
U_WAYS : for i in 0 to associativity-1 generate
way_wr_en(i) <= '1' when wr_en = '1' and wr_way_id = std_logic_vector(to_unsigned(i, wr_way_id'length)) else '0';
U_RAM : entity work.ram(SYNC_READ)
generic map(
num_words => NUM_SETS,
word_width => SET_WIDTH,
addr_width => bitsNeeded(NUM_SETS))
port map (
clk => clk,
wen => way_wr_en(i),
waddr => wr_addr(bitsNeeded(num_sets)-1 downto 0),
wdata => wr_data_complete,
raddr => rd_addr(bitsNeeded(num_sets)-1 downto 0),
rdata => ram_out(i));
end generate;
-- Register the RAM output for faster clock
process(clk, rst)
begin
if (rst = '1') then
for i in 0 to associativity-1 loop
way(i) <= (others => '0');
end loop;
elsif (rising_edge(clk)) then
if (ready_s = '1') then
for i in 0 to associativity-1 loop
way(i) <= ram_out(i);
end loop;
end if;
end if;
end process;
-- Delay the input addr by the latency of the memory
U_DELAY_ADDR : entity work.delay
generic map (
cycles => 2,
width => addr_width,
init => std_logic_vector(to_unsigned(0, addr_width)))
port map (
clk => clk,
rst => rst,
en => ready_s,
input => rd_addr,
output => rd_addr_delayed
);
-- Delay the input tag by the latency of the memory
U_DELAY_REQUEST : entity work.delay
generic map (
cycles => 2,
width => 1,
init => "0")
port map (
clk => clk,
rst => rst,
en => ready_s,
input(0) => rd_en,
output(0) => request_valid
);
-- Check all set ways for a hit
U_CHECK_TAG : for i in 0 to associativity-1 generate
constant TAG_LSB : positive := DATA_WIDTH;
constant TAG_MSB : positive := TAG_LSB + TAG_WIDTH - 1;
subtype WAY_TAG_RANGE is natural range TAG_MSB downto TAG_LSB;
constant WAY_VALID_INDEX : positive := TAG_MSB + 1;
constant DATA_LSB : natural := 0;
constant DATA_MSB : positive := DATA_LSB + DATA_WIDTH - 1;
subtype WAY_DATA_RANGE is natural range DATA_MSB downto DATA_LSB;
begin
way_tag_eq(i) <= '1' when way(i)(WAY_TAG_RANGE) = rd_addr_delayed(TAG_RANGE) else '0';
valid(i) <= way(i)(WAY_VALID_INDEX);
way_hit(i) <= way_tag_eq(i) and valid(i);
way_data(i) <= way(i)(WAY_DATA_RANGE);
end generate;
-- Or all the way hits together to determine an overall hit
-- NOTE: Will need to be pipelined for large associativities.
process(way_hit)
variable temp_hit : std_logic;
begin
temp_hit := way_hit(0);
for i in 0 to associativity-1 loop
temp_hit := temp_hit or way_hit(i);
end loop;
hit <= temp_hit;
end process;
-- Use a mux to select the right way for the output.
-- NOTE: Will need to be pipelined for large associativities.
process(way_hit, way_data)
begin
hit_data <= way_data(0);
for i in 0 to associativity-1 loop
if (way_hit(i) = '1') then
hit_data <= way_data(i);
end if;
end loop;
end process;
-------------------------------------------------------------------
-- Add an extra pipeline stage for handling misses
-- Registers for handling miss
process(clk, rst)
begin
if (rst = '1') then
hit_r <= '0';
hit_data_r <= (others => '0');
rd_addr_r <= (others => '0');
elsif (rising_edge(clk)) then
if (ready_s = '1') then
hit_r <= hit;
hit_data_r <= hit_data;
rd_addr_r <= rd_addr_delayed;
miss_valid_ways <= valid;
end if;
end if;
end process;
-- A miss has been handled when there is a write to the originally
-- requested address.
-- NOTE: might need to be pipelined
miss_handled <= '1' when wr_addr = rd_addr_r and wr_en = '1' else '0';
miss <= not hit_r;
miss_addr <= rd_addr_r;
-- Data is ready to be output when there was a hit, or when the miss has
-- been handled by an external write.
data_ready <= hit_r or miss_handled;
rd_data_valid <= data_ready;
-- Mux to select cache data (for a hit) or external data (for a miss)
rd_data <= hit_data_r when hit_r = '1' else wr_data;
-- The cache is ready when it is enabled and either there is not currently
-- a valid request, or the data is ready on a valid request.
ready_s <= en and (not request_valid or (data_ready and request_valid));
ready <= ready_s;
end default;
|
gpl-3.0
|
6ded00b8070e08de46426387602badff
| 0.546324 | 3.836292 | false | false | false | false |
corneydavid/HT_FPGA
|
Exercises/Demonstrations/Failing Path in CLIP/DemoClipAdder.vhd
| 1 | 872 |
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DemoClipAdder is
port (
clk : in std_logic;
aReset : in std_logic;
cPortA : in std_logic_vector(63 downto 0);
cPortB : in std_logic_vector(63 downto 0);
cPortC : in std_logic_vector(63 downto 0);
cPortD : in std_logic_vector(63 downto 0);
cPortE : in std_logic_vector(63 downto 0);
cAddOut : out std_logic_vector(63 downto 0) := (others => '0')
);
end DemoClipAdder;
architecture rtl of DemoClipAdder is
begin
process(aReset, clk) begin
if(aReset = '1') then
cAddOut <= (others => '0');
elsif rising_edge(clk) then
cAddOut <= std_logic_vector(signed(cPortA) + signed(cPortB) + signed(cPortC) + signed(cPortD) + signed(cPortE));
end if;
end process;
end rtl;
|
apache-2.0
|
6fab654429bfbc855be0c97f884fd66c
| 0.604358 | 3.353846 | false | false | false | false |
P3Stor/P3Stor
|
ftl/Dynamic_Controller/ipcore_dir/WR_FLASH_POST_FIFO/simulation/fg_tb_top.vhd
| 2 | 6,021 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 12
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
gpl-2.0
|
d91a18ef99b578ee5a51da724e241a74
| 0.612025 | 4.095918 | false | false | false | false |
peteg944/music-fpga
|
Enlightened Main Project/fpga_top.vhd
| 1 | 4,629 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fpga_top is
Port ( clk : in STD_LOGIC;
led : out STD_LOGIC;
bluetooth_rxd : out STD_LOGIC;
bluetooth_txd : in STD_LOGIC;
display_rgb1 : out STD_LOGIC_VECTOR (2 downto 0);
display_rgb2 : out STD_LOGIC_VECTOR (2 downto 0);
display_addr : out STD_LOGIC_VECTOR (3 downto 0);
display_clk : out STD_LOGIC;
display_oe : out STD_LOGIC;
display_lat : out STD_LOGIC;
usb_rxd : out STD_LOGIC;
usb_txd : in STD_LOGIC;
height : in STD_LOGIC_VECTOR (3 downto 0);
mode : in STD_LOGIC;
on_off : in STD_LOGIC;
sysclk : in STD_LOGIC;
pll_locked : in STD_LOGIC
);
end fpga_top;
architecture rtl of fpga_top is
--component pll
-- port
-- (-- Clock in ports
-- CLK_IN : in std_logic;
-- -- Clock out ports
-- CLK_OUT1 : out std_logic;
-- CLK_OUT2 : out std_logic;
-- -- Status and control signals
-- RESET : in std_logic;
-- LOCKED : out std_logic
-- );
--end component;
component uart_rx
generic (
log2_oversampling : integer := 7);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end component;
component display_control
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
display_ena : in STD_LOGIC;
ram_data : in STD_LOGIC_VECTOR (47 downto 0);
ram_address : out STD_LOGIC_VECTOR ( 8 downto 0);
display_rgb1 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_rgb2 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_addr : out STD_LOGIC_VECTOR ( 3 downto 0);
display_clk : out STD_LOGIC;
display_oe : out STD_LOGIC;
display_lat : out STD_LOGIC);
end component;
component animationV
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
height : in STD_LOGIC_VECTOR ( 3 downto 0);
ram_address : in STD_LOGIC_VECTOR ( 8 downto 0);
ram_data : out STD_LOGIC_VECTOR (47 downto 0);
mode : in STD_LOGIC;
on_off : in STD_LOGIC);
end component;
--signal sysclk : std_logic;
signal uart_clk : std_logic;
--signal pll_locked : std_logic;
signal rst : std_logic;
signal rgb_addr : std_logic_vector(8 downto 0);
signal rgb_data : std_logic_vector(47 downto 0);
signal rgb_frame : std_logic;
signal uart_active : std_logic;
signal uart_data : std_logic_vector(47 downto 0);
signal anim_data : std_logic_vector(47 downto 0);
signal gnd0 : std_logic := '0';
signal vcc0 : std_logic := '1';
--signal height : std_logic_vector(3 downto 0) := "0011";
begin
--led <= pll_locked and rgb_frame;
rst <= not pll_locked;
bluetooth_rxd <= '1';
usb_rxd <= '1';
--pll_inst : pll
-- port map
-- (-- Clock in ports
-- CLK_IN => clk,
-- -- Clock out ports
-- CLK_OUT1 => sysclk,
-- CLK_OUT2 => uart_clk,
-- -- Status and control signals
-- RESET => gnd0,
-- LOCKED => pll_locked);
rx_i : uart_rx
generic map (
log2_oversampling => 7)
port map (
RST => rst,
RDCLK => sysclk,
CLKOSX => uart_clk,
--RXD => bluetooth_txd,
RXD => usb_txd,
RDADDR => rgb_addr,
RDDATA => uart_data,
FRAMESEL => rgb_frame);
disp_i : display_control
port map (
clk => sysclk,
rst => rst,
display_ena => vcc0,
ram_data => rgb_data,
ram_address => rgb_addr,
display_rgb1 => display_rgb1,
display_rgb2 => display_rgb2,
display_addr => display_addr,
display_clk => display_clk,
display_oe => display_oe,
display_lat => display_lat);
anim_i : animationV
port map (
clk => sysclk,
rst => rst,
height => height,
ram_address => rgb_addr,
ram_data => anim_data,
mode => mode,
on_off => on_off);
--rgb_data <= uart_data when (uart_active = '1') else anim_data;
rgb_data <= anim_data;
uart_proc : process (rst, sysclk)
begin
if rst = '1' then
uart_active <= '1';
elsif rising_edge(sysclk) then
if rgb_frame = '0' then
uart_active <= '1';
end if;
end if;
end process uart_proc;
end rtl;
|
mit
|
d59d96d51494675af3ae24b0491f76dd
| 0.540289 | 3.185822 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_pd.vhd
| 1 | 28,820 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_pd.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- This module is replicated in phy_pd_top for each DQS signal. This module
-- contains the logic that calibrates PD (moves DQS such that clk_cpt rising
-- edge is aligned with DQS rising edge) and maintains this phase relationship
-- by moving clk_cpt as necessary.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_pd.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_pd.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_pd is
generic (
TCQ : integer := 100;
SIM_CAL_OPTION : string := "NONE"; -- "NONE", "FAST_CAL", "SKIP_CAL" (same as "NONE")
PD_LHC_WIDTH : integer := 16 -- synth low & high cntr physical width
);
port (
dbg_pd : out std_logic_vector(99 downto 0); -- debug signals
dqs_dly_val_in : in std_logic_vector(4 downto 0);
dqs_dly_val : out std_logic_vector(4 downto 0);
pd_en_maintain : out std_logic; -- maintenance enable
pd_incdec_maintain : out std_logic; -- maintenance inc/dec
pd_cal_done : out std_logic; -- calibration done (level)
pd_cal_start : in std_logic; -- calibration start (pulse or level)
dfi_init_complete : in std_logic;
pd_read_valid : in std_logic; -- advance cntrs only when true
trip_points : in std_logic_vector(1 downto 0); -- the 2 rising clock samples of the nibble
-- Debug
dbg_pd_off : in std_logic;
dbg_pd_maintain_off : in std_logic;
dbg_pd_inc_cpt : in std_logic; -- one clk period pulse
dbg_pd_dec_cpt : in std_logic; -- one clk period pulse
dbg_pd_inc_dqs : in std_logic; -- one clk period pulse
dbg_pd_dec_dqs : in std_logic; -- one clk period pulse
dbg_pd_disab_hyst : in std_logic;
dbg_pd_msb_sel : in std_logic_vector(3 downto 0); -- selects effective msb of high &
-- low cntrs
clk : in std_logic; -- clkmem/2
rst : in std_logic
);
end phy_pd;
architecture trans of phy_pd is
-- merge two SIM_CAL_OPTION values into new localparam
function CALC_FAST_SIM return string is
begin
if ((SIM_CAL_OPTION = "FAST_CAL") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) then
return "YES";
else
return "NO";
end if;
end function CALC_FAST_SIM;
constant FAST_SIM : string := CALC_FAST_SIM;
-- width of low and high counters
function CALC_LHC_WIDTH return integer is
begin
if (FAST_SIM = "YES") then
return (6);
else
return PD_LHC_WIDTH;
end if;
end function CALC_LHC_WIDTH;
-- width of calibration done counter (6 for synthesis, less for simulation)
function CALC_CDC_WIDTH return integer is
begin
if (FAST_SIM = "YES") then
return (3);
else
return (6);
end if;
end function CALC_CDC_WIDTH;
--***************************************************************************
-- Local parameters (other than state assignments)
--***************************************************************************
constant LHC_WIDTH : integer := CALC_LHC_WIDTH;
constant CDC_WIDTH : integer := CALC_CDC_WIDTH;
constant RVPLS_WIDTH : integer := 1; -- this controls the pipeline delay of pd_read_valid
-- set to 1 for normal operation
--***************************************************************************
-- pd state assignments
--***************************************************************************
constant PD_IDLE : std_logic_vector(2 downto 0) := "000";
constant PD_CLR_CNTRS : std_logic_vector(2 downto 0) := "001";
constant PD_INC_CNTRS : std_logic_vector(2 downto 0) := "010";
constant PD_UPDATE : std_logic_vector(2 downto 0) := "011";
constant PD_WAIT : std_logic_vector(2 downto 0) := "100";
--***************************************************************************
-- constants for pd_done logic
--***************************************************************************
constant PD_DONE_IDLE : std_logic_vector(3 downto 0) := "0000";
constant PD_DONE_MAX : std_logic_vector(3 downto 0) := "1010";
--***************************************************************************
-- Internal signals
--***************************************************************************
signal pd_en_maintain_d : std_logic;
signal pd_incdec_maintain_d : std_logic;
signal low_d : std_logic_vector(LHC_WIDTH-1 downto 0);
signal high_d : std_logic_vector(LHC_WIDTH-1 downto 0);
signal ld_dqs_dly_val_r : std_logic; -- combinatorial
signal dqs_dly_val_r : std_logic_vector(4 downto 0);
signal pd_cal_done_i : std_logic; -- pd_cal_done internal
signal first_calib_sample : std_logic;
signal rev_direction : std_logic;
signal rev_direction_ce : std_logic;
signal pd_en_calib : std_logic; -- calibration enable
signal pd_incdec_calib : std_logic; -- calibration inc/dec
signal pd_en : std_logic;
signal pd_incdec : std_logic;
signal reset : std_logic; -- rst is synchronized to clk
signal pd_state_r : std_logic_vector(2 downto 0);
signal pd_next_state : std_logic_vector(2 downto 0); -- combinatorial
signal low : std_logic_vector(LHC_WIDTH-1 downto 0);-- low counter
signal high : std_logic_vector(LHC_WIDTH-1 downto 0);-- high counter
signal samples_done : std_logic;
signal samples_done_pl : std_logic_vector(2 downto 0);
signal inc_cntrs : std_logic;
signal clr_low_high : std_logic;
signal low_high_ce : std_logic;
signal update_phase : std_logic;
signal calib_done_cntr : std_logic_vector(CDC_WIDTH-1 downto 0);
signal calib_done_cntr_inc : std_logic;
signal calib_done_cntr_ce : std_logic;
signal high_ge_low : std_logic;
signal l_addend : std_logic_vector(1 downto 0);
signal h_addend : std_logic_vector(1 downto 0);
signal read_valid_pl : std_logic;
signal enab_maintenance : std_logic;
signal pd_done_state_r : std_logic_vector(3 downto 0);
signal pd_done_next_state : std_logic_vector(3 downto 0);
signal pd_incdec_done : std_logic; -- combinatorial
signal pd_incdec_done_next : std_logic; -- combinatorial
signal block_change : std_logic;
signal low_nearly_done : std_logic;
signal high_nearly_done : std_logic;
signal pd_incdec_tp : std_logic;
signal low_done : std_logic; -- PD_DEBUG not defined
signal high_done : std_logic;
signal hyst_mux_sel : std_logic_vector(3 downto 0);
signal mux_sel : std_logic_vector(3 downto 0);
signal low_mux : std_logic; -- combinatorial
signal high_mux : std_logic; -- combinatorial
signal low_nearly_done_r : std_logic;
signal high_nearly_done_r : std_logic;
begin
--***************************************************************************
-- low_done and high_done
--***************************************************************************
-- select MSB during calibration - during maintanence,
-- determined by dbg_pd_msb_sel. Add case to handle
-- fast simulation to prevent overflow of counter
-- since LHC_WIDTH is set to small value for fast sim
mux_sel <= dbg_pd_msb_sel when ((pd_cal_done_i = '1') and not(FAST_SIM = "YES")) else
std_logic_vector(to_unsigned((LHC_WIDTH-1),4));
process (mux_sel,low)
begin
low_mux <= low(to_integer(unsigned(mux_sel)));
end process;
process (mux_sel,high)
begin
high_mux <= high(to_integer(unsigned(mux_sel)));
end process;
process(clk)
begin
if (clk'event and clk = '1') then
if (clr_low_high = '1') then
low_done <= '0' after TCQ*1 ps;
high_done <= '0' after TCQ*1 ps;
else
low_done <= low_mux after TCQ*1 ps;
high_done <= high_mux after TCQ*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- block_change (hysteresis) logic
--***************************************************************************
-- select MSB used to determine hysteresis level. Add case to handle
-- fast simulation to prevent out-of-bounds index since LHC_WIDTH is set
-- to small value for fast sim. If DEBUG PORT is disabled, dbg_pd_msb_sel
-- must be hardcoded to appropriate value in upper-level module.
hyst_mux_sel <= std_logic_vector(to_unsigned((LHC_WIDTH-2), 4)) when (FAST_SIM = "YES") else
(dbg_pd_msb_sel-'1');
process (hyst_mux_sel,low)
begin
low_nearly_done <= low(to_integer(unsigned(hyst_mux_sel)));
end process;
process (hyst_mux_sel,high)
begin
high_nearly_done <= high(to_integer(unsigned(hyst_mux_sel)));
end process;
-- pipeline low_nearly_done and high_nearly_done
process(clk)
begin
if (clk'event and clk = '1') then
if ((reset = '1') or (dbg_pd_disab_hyst = '1')) then
low_nearly_done_r <= '0' after TCQ*1 ps;
high_nearly_done_r <= '0' after TCQ*1 ps;
else
low_nearly_done_r <= low_nearly_done after TCQ*1 ps;
high_nearly_done_r <= high_nearly_done after TCQ*1 ps;
end if;
end if;
end process;
block_change <= ((high_done and low_done) or low_nearly_done_r) when (high_done='1') else
((high_done and low_done) or high_nearly_done_r);
--***************************************************************************
-- samples_done and high_ge_low
--***************************************************************************
samples_done <= (low_done or high_done) and not(clr_low_high); -- ~clr_low_high makes samples_done de-assert one cycle sooner
high_ge_low <= high_done;
--***************************************************************************
-- Debug
--***************************************************************************
-- Temporary debug assignments and logic - remove for release code.
-- Disabling of PD is allowed either before or after calibration
-- Usage: dbg_pd_off = 1 to disable PD. If disabled prior to initialization
-- it should remain off - turning it on later will result in bad behavior
-- since the DQS early/late tap delays will not have been properly initialized.
-- If disabled after initial calibration, it can later be re-enabled
-- without reseting the system.
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
pd_incdec_tp <= '0' after TCQ*1 ps;
elsif (pd_en = '1') then
pd_incdec_tp <= pd_incdec after TCQ*1 ps;
end if;
end if;
end process;
dbg_pd(0) <= pd_en;
dbg_pd(1) <= pd_incdec;
dbg_pd(2) <= pd_cal_done_i;
dbg_pd(3) <= pd_cal_start;
dbg_pd(4) <= samples_done;
dbg_pd(5) <= inc_cntrs;
dbg_pd(6) <= clr_low_high;
dbg_pd(7) <= low_high_ce;
dbg_pd(8) <= update_phase;
dbg_pd(9) <= calib_done_cntr_inc;
dbg_pd(10) <= calib_done_cntr_ce;
dbg_pd(11) <= first_calib_sample;
dbg_pd(12) <= rev_direction;
dbg_pd(13) <= rev_direction_ce;
dbg_pd(14) <= pd_en_calib;
dbg_pd(15) <= pd_incdec_calib;
dbg_pd(16) <= read_valid_pl;
dbg_pd(17) <= pd_read_valid;
dbg_pd(18) <= pd_incdec_tp;
dbg_pd(19) <= block_change;
dbg_pd(20) <= low_nearly_done_r;
dbg_pd(21) <= high_nearly_done_r;
dbg_pd(23 downto 22) <= (others => '0'); -- spare scalor bits
dbg_pd(29 downto 24) <= ('0' & dqs_dly_val_r); -- 1 spare bit
dbg_pd(33 downto 30) <= ('0' & pd_state_r); -- 1 spare bit
dbg_pd(37 downto 34) <= ('0' & pd_next_state); -- 1 spare bit
gen_LHC_WIDTH_6: if (LHC_WIDTH = 6) generate
dbg_pd(53 downto 44) <= (others => '0');
dbg_pd(69 downto 60) <= (others => '0');
dbg_pd(43 downto 38) <= high;
dbg_pd(59 downto 54) <= low;
end generate;
gen_LHC_WIDTH_16: if (LHC_WIDTH = 16) generate
dbg_pd(53 downto 38) <= high; -- 16 bits max
dbg_pd(69 downto 54) <= low; -- 16 bits max
end generate;
dbg_pd(73 downto 70) <= pd_done_state_r;
dbg_pd(74+CDC_WIDTH-1 downto 74) <= calib_done_cntr;
dbg_pd(81 downto 74+CDC_WIDTH) <= (others => '0'); -- 8 bits max
dbg_pd(83 downto 82) <= l_addend;
dbg_pd(85 downto 84) <= h_addend;
dbg_pd(87 downto 86) <= trip_points;
dbg_pd(99 downto 88) <= (others => '0'); -- spare
--***************************************************************************
-- pd_read_valid pipeline shifter
--***************************************************************************
gen_rvpls: if (RVPLS_WIDTH = 0) generate
read_valid_pl <= pd_read_valid;
end generate;
gen_rvpls_1: if (RVPLS_WIDTH = 1) generate
signal read_valid_shftr : std_logic_vector(RVPLS_WIDTH-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
read_valid_shftr(0) <= '0' after TCQ*1 ps;
else
read_valid_shftr(0) <= pd_read_valid after TCQ*1 ps;
end if;
end if;
end process;
read_valid_pl <= read_valid_shftr(RVPLS_WIDTH-1);
end generate;
gen_rvpls_gt1: if (not(RVPLS_WIDTH = 0) and not(RVPLS_WIDTH = 1)) generate
signal read_valid_shftr : std_logic_vector(RVPLS_WIDTH-1 downto 0);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
read_valid_shftr <= (others => '0') after TCQ*1 ps;
else
read_valid_shftr <= (read_valid_shftr(RVPLS_WIDTH-2 downto 0) & pd_read_valid) after TCQ*1 ps;
end if;
end if;
end process;
read_valid_pl <= read_valid_shftr(RVPLS_WIDTH-1);
end generate;
--***************************************************************************
-- phase shift interface
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
pd_en <= '0' after TCQ*1 ps;
else
pd_en <= update_phase after TCQ*1 ps;
end if;
end if;
end process;
pd_incdec <= high_ge_low;
--***************************************************************************
-- inc/dec control
--***************************************************************************
rev_direction_ce <= first_calib_sample and pd_en and (pd_incdec xnor dqs_dly_val_r(4));
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
first_calib_sample <= '1' after TCQ*1 ps;
rev_direction <= '0' after TCQ*1 ps;
else
if (pd_en = '1') then
first_calib_sample <= '0' after TCQ*1 ps;
end if;
if (rev_direction_ce = '1') then
rev_direction <= '1' after TCQ*1 ps;
end if;
end if;
end if;
end process;
pd_en_calib <= (pd_en and not(pd_cal_done_i) and not(first_calib_sample)) or dbg_pd_inc_dqs or dbg_pd_dec_dqs;
pd_incdec_calib <= (pd_incdec xor rev_direction) or dbg_pd_inc_dqs;
enab_maintenance <= dfi_init_complete and not(dbg_pd_maintain_off);
pd_en_maintain_d <= (pd_en and pd_cal_done_i and enab_maintenance and not(block_change)) or dbg_pd_inc_cpt or dbg_pd_dec_cpt;
pd_incdec_maintain_d <= (not(pd_incdec_calib) or dbg_pd_inc_cpt) and not(dbg_pd_dec_cpt);
process (clk) -- pipeline maintenance control signals
begin
if (clk'event and clk = '1') then
if (reset = '1') then
pd_en_maintain <= '0' after TCQ*1 ps;
pd_incdec_maintain <= '0' after TCQ*1 ps;
else
pd_en_maintain <= pd_en_maintain_d after TCQ*1 ps;
pd_incdec_maintain <= pd_incdec_maintain_d after TCQ*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- dqs delay value counter
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
dqs_dly_val_r <= (others => '0') after TCQ*1 ps;
elsif (ld_dqs_dly_val_r = '1') then
dqs_dly_val_r <= dqs_dly_val_in after TCQ*1 ps;
else
if (pd_en_calib = '1') then
if (pd_incdec_calib = '1') then
dqs_dly_val_r <= dqs_dly_val_r + '1' after TCQ*1 ps;
else
dqs_dly_val_r <= dqs_dly_val_r - '1' after TCQ*1 ps;
end if;
end if;
end if;
end if;
end process;
dqs_dly_val <= dqs_dly_val_r;
--***************************************************************************
-- reset synchronization
--***************************************************************************
process (clk, rst)
begin
if (rst = '1') then
reset <= '1' after TCQ*1 ps;
elsif (clk'event and clk = '1') then
reset <= '0' after TCQ*1 ps;
end if;
end process;
--***************************************************************************
-- State register
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
pd_state_r <= (others => '0') after TCQ*1 ps;
else
pd_state_r <= pd_next_state after TCQ*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- Next pd state
--***************************************************************************
process (pd_state_r, pd_cal_start, dbg_pd_off, samples_done_pl(2), pd_incdec_done)
begin
pd_next_state <= PD_IDLE; -- default state is idle
ld_dqs_dly_val_r <= '0';
case (pd_state_r) is
-- (0) wait for pd_cal_start
when PD_IDLE =>
if (pd_cal_start = '1') then
pd_next_state <= PD_CLR_CNTRS;
ld_dqs_dly_val_r <= '1';
end if;
-- (1) clr low and high counters
when PD_CLR_CNTRS =>
if (dbg_pd_off = '0') then
pd_next_state <= PD_INC_CNTRS;
else
pd_next_state <= PD_CLR_CNTRS;
end if;
-- (2) conditionally inc low and high counters
when PD_INC_CNTRS =>
if (samples_done_pl(2) = '1') then
pd_next_state <= PD_UPDATE;
else
pd_next_state <= PD_INC_CNTRS;
end if;
-- (3) pulse pd_en
when PD_UPDATE =>
pd_next_state <= PD_WAIT;
-- (4) wait for pd_incdec_done
when PD_WAIT =>
if (pd_incdec_done = '1') then
pd_next_state <= PD_CLR_CNTRS;
else
pd_next_state <= PD_WAIT;
end if;
when others =>
null;
end case;
end process;
--***************************************************************************
-- pd state translations
--***************************************************************************
inc_cntrs <= (read_valid_pl and not(samples_done)) when (pd_state_r = PD_INC_CNTRS) else '0';
clr_low_high <= '1' when (pd_state_r = PD_CLR_CNTRS) else reset;
low_high_ce <= inc_cntrs;
update_phase <= '1' when (pd_state_r = PD_UPDATE) else '0';
--***************************************************************************
-- pd_cal_done generator
--***************************************************************************
calib_done_cntr_inc <= high_ge_low xnor calib_done_cntr(0);
calib_done_cntr_ce <= update_phase and not(calib_done_cntr(CDC_WIDTH-1)) and not(first_calib_sample);
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
calib_done_cntr <= (others => '0') after TCQ*1 ps;
elsif (calib_done_cntr_ce = '1') then
calib_done_cntr <= (calib_done_cntr + calib_done_cntr_inc) after TCQ*1 ps;
end if;
end if;
end process;
pd_cal_done_i <= calib_done_cntr(CDC_WIDTH-1) or dbg_pd_off;
pd_cal_done <= pd_cal_done_i;
--***************************************************************************
-- addemd gemerators (pipelined)
--***************************************************************************
-- trip_points h_addend l_addend
-- ----------- -------- --------
-- 00 00 10
-- 01 01 01
-- 10 01 01
-- 11 10 00
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
l_addend <= (others => '0') after TCQ*1 ps;
h_addend <= (others => '0') after TCQ*1 ps;
else
l_addend <= ( (not(trip_points(1)) and not(trip_points(0))) & (trip_points(1) xor trip_points(0)) ) after TCQ*1 ps;
h_addend <= ( (trip_points(1) and trip_points(0)) & (trip_points(1) xor trip_points(0)) ) after TCQ*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- low counter
--***************************************************************************
process (l_addend, low)
variable low_d1 : std_logic_vector(LHC_WIDTH-1 downto 0);
begin
low_d1(LHC_WIDTH-1 downto 2) := (others => '0');
low_d1(1 downto 0) := l_addend;
low_d <= low + low_d1;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (clr_low_high = '1') then
low <= (others => '0') after TCQ*1 ps;
elsif (low_high_ce = '1') then
low <= low_d after TCQ*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- high counter
--***************************************************************************
process (h_addend, high)
variable high_d1 : std_logic_vector(LHC_WIDTH-1 downto 0);
begin
high_d1(LHC_WIDTH-1 downto 2) := (others => '0');
high_d1(1 downto 0) := h_addend;
high_d <= high + high_d1;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (clr_low_high = '1') then
high <= (others => '0') after TCQ*1 ps;
elsif (low_high_ce = '1') then
high <= high_d after TCQ*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- samples_done pipeline shifter
--***************************************************************************
-- This shifter delays samples_done rising edge until the nearly_done logic has completed
-- the pass through its pipeline.
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
samples_done_pl <= (others => '0') after TCQ*1 ps;
else
samples_done_pl <= ( (samples_done_pl(1) and samples_done) &
(samples_done_pl(0) and samples_done) & samples_done ) after TCQ*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- pd_done logic
--***************************************************************************
-- This logic adds a delay after pd_en is pulsed. This delay is necessary
-- to allow the effect of the delay tap change to cycle through to the addends,
-- where it can then be sampled in the low and high counters.
-- the following represents pd_done registers
process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
pd_done_state_r <= (others => '0') after TCQ*1 ps;
pd_incdec_done <= '0' after TCQ*1 ps;
else
pd_done_state_r <= pd_done_next_state after TCQ*1 ps;
pd_incdec_done <= pd_incdec_done_next after TCQ*1 ps;
end if;
end if;
end process;
-- pd_done next generator
process (pd_done_state_r, pd_en)
begin
pd_done_next_state <= pd_done_state_r + '1'; -- dflt pd_done_next_state is + 1
pd_incdec_done_next <= '0'; -- dflt pd_incdec_done is false
case (pd_done_state_r) is
-- (0) wait for pd_en
when PD_DONE_IDLE =>
if (pd_en = '0') then
pd_done_next_state <= PD_DONE_IDLE;
end if;
-- (10)
when PD_DONE_MAX =>
pd_done_next_state <= PD_DONE_IDLE;
pd_incdec_done_next <= '1';
when others =>
null;
end case;
end process;
end trans;
|
lgpl-3.0
|
56566b054caec6abac02fb9b2cffc983
| 0.495559 | 3.854487 | false | false | false | false |
z3774/sparcv8-monocycle
|
sparcv8_v6_monociclo_tb.vhd
| 1 | 1,331 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY sparcv8_v6_monociclo_tb IS
END sparcv8_v6_monociclo_tb;
ARCHITECTURE behavior OF sparcv8_v6_monociclo_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sparcv8_v6_monociclo
PORT(
clk : IN std_logic;
reset : IN std_logic;
alurs : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal alurs : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sparcv8_v6_monociclo PORT MAP (
clk => clk,
reset => reset,
alurs => alurs
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 40 ns;
reset <= '0';
wait;
end process;
END;
|
gpl-3.0
|
7a9d1a998a2346037d7bb228fdecd326
| 0.58302 | 3.759887 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/7k325ffg900/sfifo_15x128.vhd
| 1 | 143,990 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68d
-- \ \ Application: netgen
-- / / Filename: sfifo_15x128.vhd
-- /___/ /\ Timestamp: Fri Sep 20 18:15:23 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/sfifo_15x128.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/sfifo_15x128.vhd
-- Device : 7k325tffg900-2
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/sfifo_15x128.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7k325ffg900/tmp/_cg/sfifo_15x128.vhd
-- # of Entities : 1
-- Design Name : sfifo_15x128
-- Xilinx : /opt/Xilinx/14.6/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity sfifo_15x128 is
port (
clk : in STD_LOGIC := 'X';
rst : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 127 downto 0 );
dout : out STD_LOGIC_VECTOR ( 127 downto 0 )
);
end sfifo_15x128;
architecture STRUCTURE of sfifo_15x128 is
signal N1 : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_275 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en : STD_LOGIC;
signal NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_279 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_GND_12_o_MUX_2_o : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_GND_12_o_MUX_1_o : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_567 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_570 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_573 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_574 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_1_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_3_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_4_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i_584 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i_585 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_1_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_3_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_1_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_3_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_4_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_600 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_601 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_1_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_2_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_3_Q : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_605 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6_608 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_609 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5_610 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_611 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_612 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N5 : STD_LOGIC;
signal N6 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N14 : STD_LOGIC;
signal N16 : STD_LOGIC;
signal N17 : STD_LOGIC;
signal N19 : STD_LOGIC;
signal N21 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0 : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg : STD_LOGIC_VECTOR ( 1 downto 1 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1 : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count : STD_LOGIC_VECTOR ( 3 downto 1 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1 : STD_LOGIC_VECTOR ( 0 downto 0 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count : STD_LOGIC_VECTOR ( 3 downto 1 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad : STD_LOGIC_VECTOR ( 4 downto 1 );
signal U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad : STD_LOGIC_VECTOR ( 4 downto 1 );
begin
full <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_275;
empty <= U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_279;
prog_full <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i;
prog_empty <= NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i;
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => rst,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_573,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg : FDP
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_GND_12_o_MUX_2_o,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg : FDP
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_GND_12_o_MUX_1_o,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d3_573
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_567
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_570
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_574,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg_1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1 : FD
generic map(
INIT => '0'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1 : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => N1,
PRE => rst,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d1_574
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_i_279
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_4_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_3_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_1_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i_584
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i_585
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_3_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_1_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_i_275
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_4_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_3_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_1_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_600
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_601
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0),
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_3_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_2_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
CLR => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_wr_rst_reg(1),
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_1_Q,
Q => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_ram_rd_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_ram_wr_en_i1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en1 : LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278,
I1 => rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_Mmux_rd_rst_asreg_GND_12_o_MUX_2_o11 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d1_568,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_GND_12_o_MUX_2_o
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_Mmux_wr_rst_asreg_GND_12_o_MUX_1_o11 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d1_571,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_GND_12_o_MUX_1_o
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_569,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_asreg_d2_567,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_rd_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb1 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_572,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_asreg_d2_570,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_wr_rst_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o_3_1 : LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(4),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_pad(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_1 :
LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
O =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4 : LUT6
generic map(
INIT => X"0A0ACECEFF0AFFCE"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5 : LUT6
generic map(
INIT => X"22F222F2FFFF22F2"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6 : LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6_608
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o7 : LUT6
generic map(
INIT => X"FFFFFFFFAAAAA8AA"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o6_608,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_605,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5 : LUT6
generic map(
INIT => X"FFFFFFFF4F44FFFF"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o5_607,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5_610
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb7 : LUT5
generic map(
INIT => X"FF44FF40"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o4_606,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_609,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb5_610,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_611,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_2_Q,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i : FDP
generic map(
INIT => '1'
)
port map (
C => clk,
D => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_612,
PRE => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_grstd1_grst_full_rst_d2_408,
Q => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot : LUT5
generic map(
INIT => X"45440444"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_RST_FULL_GEN_409,
I1 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_rd_en_i_600,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_diff_pntr_3_PWR_41_o_equal_7_o,
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_ram_wr_en_i_601,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_prog_full_i_rstpot_612
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_2_11 : LUT6
generic map(
INIT => X"6696669696996696"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_2_11 :
LUT6
generic map(
INIT => X"9996966699969996"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_3_11_SW0 :
LUT4
generic map(
INIT => X"44D4"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => N2
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_3_11_SW0 :
LUT4
generic map(
INIT => X"693C"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
O => N5
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_3_11_SW1 :
LUT4
generic map(
INIT => X"D22D"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
O => N6
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_3_11 :
LUT6
generic map(
INIT => X"FFFFE8EE17110000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => N5,
I5 => N6,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_3_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11_SW0 :
LUT5
generic map(
INIT => X"69669969"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
O => N8
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11_SW1 :
LUT6
generic map(
INIT => X"9969996999696966"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => N9
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11_SW2 :
LUT6
generic map(
INIT => X"9969696669666966"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => N10
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_4_11 :
LUT6
generic map(
INIT => X"FFAADF8A75205500"
)
port map (
I0 =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_lut_2_Q,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I3 => N8,
I4 => N10,
I5 => N9,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_4_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_SW0 : LUT6
generic map(
INIT => X"FFFF2FF22FF2FFFF"
)
port map (
I0 => wr_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
O => N12
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3 : LUT6
generic map(
INIT => X"0000000084210000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I5 => N12,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_going_empty_leaving_empty_OR_6_o3_605
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_SW0 : LUT6
generic map(
INIT => X"D0000D0000D0000D"
)
port map (
I0 => rd_en,
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
O => N14
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3 : LUT6
generic map(
INIT => X"0990000000000000"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I5 => N14,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_comb3_609
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_cy_3_11_SW0 :
LUT6
generic map(
INIT => X"75F7757510511010"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
O => N16
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_cy_3_11_SW1 :
LUT6
generic map(
INIT => X"75F7757510511010"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
O => N17
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_4_11 : LUT6
generic map(
INIT => X"9969666699996696"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => N16,
I5 => N17,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_4_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_SW0 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(4),
O => N19
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot : LUT6
generic map(
INIT => X"AAAABAAA8AAAAAAA"
)
port map (
I0 => NlwRenamedSig_OI_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i,
I1 => N19,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_diff_pntr_pad(2),
I4 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_wr_en_i_584,
I5 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_ram_rd_en_i_585,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_prog_empty_i_rstpot_611
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_3_11_SW2 :
LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
O => N21
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_3_11 : LUT6
generic map(
INIT => X"9969999966666696"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_rd_en,
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
I4 => N21,
I5 => N2,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_3_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_Madd_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_xor_1_11 : LUT6
generic map(
INIT => X"5A965A5A5AA55A5A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278,
I4 => rd_en,
I5 => wr_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_gpe_rdpe_wr_pntr_rd_pad_4_rd_pntr_inv_pad_4_add_2_OUT_1_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_Madd_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_xor_1_11 :
LUT6
generic map(
INIT => X"5A965A5A5AA55A5A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_grss_rsts_ram_empty_fb_i_278,
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_wsts_ram_full_fb_i_562,
I4 => wr_en,
I5 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_gwss_gpf_wrpf_wr_pntr_plus1_pad_4_rd_pntr_wr_inv_pad_4_add_2_OUT_1_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Madd_gc0_count_3_GND_427_o_add_0_OUT_xor_2_11 : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Madd_gc0_count_3_GND_427_o_add_0_OUT_xor_3_11 : LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_3_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_Madd_gc0_count_3_GND_427_o_add_0_OUT_xor_1_11 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_3_GND_427_o_add_0_OUT_1_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Madd_gcc0_gc0_count_3_GND_435_o_add_0_OUT_xor_2_11 : LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_2_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Madd_gcc0_gc0_count_3_GND_435_o_add_0_OUT_xor_3_11 : LUT4
generic map(
INIT => X"AA6A"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(3),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(2),
I2 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I3 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_3_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_Madd_gcc0_gc0_count_3_GND_435_o_add_0_OUT_xor_1_11 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count(1),
I1 => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_3_GND_435_o_add_0_OUT_1_Q
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_wr_pntr_0_inv1_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wr_pntr_plus1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rd_pntr_0_inv1_INV_0 : INV
port map (
I => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
O => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rd_pntr_plus1(0)
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram :
RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
CASCADEINA =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
CASCADEINB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
CASCADEOUTA =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
ENBWREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
INJECTDBITERR =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
INJECTSBITERR =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
REGCEAREGCE =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
REGCEB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
RSTRAMARSTRAM => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
RSTRAMB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
RSTREGARSTREG =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
RSTREGB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0,
ADDRARDADDR(14) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(13) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(12) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(11) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(10) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
ADDRARDADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
ADDRARDADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
ADDRARDADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
ADDRARDADDR(5) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(4) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(15) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0,
ADDRBWRADDR(14) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(13) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(12) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(11) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(10) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
ADDRBWRADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
ADDRBWRADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
ADDRBWRADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
ADDRBWRADDR(5) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(4) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIADI(31) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIADI(30) => din(99),
DIADI(29) => din(98),
DIADI(28) => din(97),
DIADI(27) => din(96),
DIADI(26) => din(95),
DIADI(25) => din(94),
DIADI(24) => din(93),
DIADI(23) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIADI(22) => din(92),
DIADI(21) => din(91),
DIADI(20) => din(90),
DIADI(19) => din(89),
DIADI(18) => din(88),
DIADI(17) => din(87),
DIADI(16) => din(86),
DIADI(15) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIADI(14) => din(85),
DIADI(13) => din(84),
DIADI(12) => din(83),
DIADI(11) => din(82),
DIADI(10) => din(81),
DIADI(9) => din(80),
DIADI(8) => din(79),
DIADI(7) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIADI(6) => din(78),
DIADI(5) => din(77),
DIADI(4) => din(76),
DIADI(3) => din(75),
DIADI(2) => din(74),
DIADI(1) => din(73),
DIADI(0) => din(72),
DIBDI(31) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIBDI(30) => din(127),
DIBDI(29) => din(126),
DIBDI(28) => din(125),
DIBDI(27) => din(124),
DIBDI(26) => din(123),
DIBDI(25) => din(122),
DIBDI(24) => din(121),
DIBDI(23) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIBDI(22) => din(120),
DIBDI(21) => din(119),
DIBDI(20) => din(118),
DIBDI(19) => din(117),
DIBDI(18) => din(116),
DIBDI(17) => din(115),
DIBDI(16) => din(114),
DIBDI(15) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIBDI(14) => din(113),
DIBDI(13) => din(112),
DIBDI(12) => din(111),
DIBDI(11) => din(110),
DIBDI(10) => din(109),
DIBDI(9) => din(108),
DIBDI(8) => din(107),
DIBDI(7) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIBDI(6) => din(106),
DIBDI(5) => din(105),
DIBDI(4) => din(104),
DIBDI(3) => din(103),
DIBDI(2) => din(102),
DIBDI(1) => din(101),
DIBDI(0) => din(100),
DIPADIP(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIPADIP(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIPADIP(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIPADIP(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIPBDIP(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIPBDIP(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIPBDIP(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIPBDIP(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DOADO(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) => dout(99),
DOADO(29) => dout(98),
DOADO(28) => dout(97),
DOADO(27) => dout(96),
DOADO(26) => dout(95),
DOADO(25) => dout(94),
DOADO(24) => dout(93),
DOADO(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) => dout(92),
DOADO(21) => dout(91),
DOADO(20) => dout(90),
DOADO(19) => dout(89),
DOADO(18) => dout(88),
DOADO(17) => dout(87),
DOADO(16) => dout(86),
DOADO(15) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) => dout(85),
DOADO(13) => dout(84),
DOADO(12) => dout(83),
DOADO(11) => dout(82),
DOADO(10) => dout(81),
DOADO(9) => dout(80),
DOADO(8) => dout(79),
DOADO(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOADO_7_UNCONNECTED
,
DOADO(6) => dout(78),
DOADO(5) => dout(77),
DOADO(4) => dout(76),
DOADO(3) => dout(75),
DOADO(2) => dout(74),
DOADO(1) => dout(73),
DOADO(0) => dout(72),
DOBDO(31) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) => dout(127),
DOBDO(29) => dout(126),
DOBDO(28) => dout(125),
DOBDO(27) => dout(124),
DOBDO(26) => dout(123),
DOBDO(25) => dout(122),
DOBDO(24) => dout(121),
DOBDO(23) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) => dout(120),
DOBDO(21) => dout(119),
DOBDO(20) => dout(118),
DOBDO(19) => dout(117),
DOBDO(18) => dout(116),
DOBDO(17) => dout(115),
DOBDO(16) => dout(114),
DOBDO(15) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) => dout(113),
DOBDO(13) => dout(112),
DOBDO(12) => dout(111),
DOBDO(11) => dout(110),
DOBDO(10) => dout(109),
DOBDO(9) => dout(108),
DOBDO(8) => dout(107),
DOBDO(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOBDO_7_UNCONNECTED
,
DOBDO(6) => dout(106),
DOBDO(5) => dout(105),
DOBDO(4) => dout(104),
DOBDO(3) => dout(103),
DOBDO(2) => dout(102),
DOBDO(1) => dout(101),
DOBDO(0) => dout(100),
DOPADOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEA(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEA(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEA(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEBWE(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram :
RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 72,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 72
)
port map (
CASCADEINA =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
CASCADEINB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
CASCADEOUTA =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clk,
CLKBWRCLK => clk,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_tmp_ram_rd_en,
ENBWREN => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
INJECTDBITERR =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
INJECTSBITERR =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
REGCEAREGCE =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
REGCEB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
RSTRAMARSTRAM => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_rstblk_ngwrdrst_grst_rd_rst_reg_0_Q,
RSTRAMB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
RSTREGARSTREG =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
RSTREGB =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0,
ADDRARDADDR(14) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(13) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(12) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(11) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(10) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(3),
ADDRARDADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(2),
ADDRARDADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(1),
ADDRARDADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_rd_rpntr_gc0_count_d1(0),
ADDRARDADDR(5) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(4) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRARDADDR(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(15) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0,
ADDRBWRADDR(14) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(13) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(12) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(11) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(10) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(9) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(3),
ADDRBWRADDR(8) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(2),
ADDRBWRADDR(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(1),
ADDRBWRADDR(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_gl0_wr_wpntr_gcc0_gc0_count_d1(0),
ADDRBWRADDR(5) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(4) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
ADDRBWRADDR(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
DIADI(31) => din(34),
DIADI(30) => din(33),
DIADI(29) => din(32),
DIADI(28) => din(31),
DIADI(27) => din(30),
DIADI(26) => din(29),
DIADI(25) => din(28),
DIADI(24) => din(27),
DIADI(23) => din(25),
DIADI(22) => din(24),
DIADI(21) => din(23),
DIADI(20) => din(22),
DIADI(19) => din(21),
DIADI(18) => din(20),
DIADI(17) => din(19),
DIADI(16) => din(18),
DIADI(15) => din(16),
DIADI(14) => din(15),
DIADI(13) => din(14),
DIADI(12) => din(13),
DIADI(11) => din(12),
DIADI(10) => din(11),
DIADI(9) => din(10),
DIADI(8) => din(9),
DIADI(7) => din(7),
DIADI(6) => din(6),
DIADI(5) => din(5),
DIADI(4) => din(4),
DIADI(3) => din(3),
DIADI(2) => din(2),
DIADI(1) => din(1),
DIADI(0) => din(0),
DIBDI(31) => din(70),
DIBDI(30) => din(69),
DIBDI(29) => din(68),
DIBDI(28) => din(67),
DIBDI(27) => din(66),
DIBDI(26) => din(65),
DIBDI(25) => din(64),
DIBDI(24) => din(63),
DIBDI(23) => din(61),
DIBDI(22) => din(60),
DIBDI(21) => din(59),
DIBDI(20) => din(58),
DIBDI(19) => din(57),
DIBDI(18) => din(56),
DIBDI(17) => din(55),
DIBDI(16) => din(54),
DIBDI(15) => din(52),
DIBDI(14) => din(51),
DIBDI(13) => din(50),
DIBDI(12) => din(49),
DIBDI(11) => din(48),
DIBDI(10) => din(47),
DIBDI(9) => din(46),
DIBDI(8) => din(45),
DIBDI(7) => din(43),
DIBDI(6) => din(42),
DIBDI(5) => din(41),
DIBDI(4) => din(40),
DIBDI(3) => din(39),
DIBDI(2) => din(38),
DIBDI(1) => din(37),
DIBDI(0) => din(36),
DIPADIP(3) => din(35),
DIPADIP(2) => din(26),
DIPADIP(1) => din(17),
DIPADIP(0) => din(8),
DIPBDIP(3) => din(71),
DIPBDIP(2) => din(62),
DIPBDIP(1) => din(53),
DIPBDIP(0) => din(44),
DOADO(31) => dout(34),
DOADO(30) => dout(33),
DOADO(29) => dout(32),
DOADO(28) => dout(31),
DOADO(27) => dout(30),
DOADO(26) => dout(29),
DOADO(25) => dout(28),
DOADO(24) => dout(27),
DOADO(23) => dout(25),
DOADO(22) => dout(24),
DOADO(21) => dout(23),
DOADO(20) => dout(22),
DOADO(19) => dout(21),
DOADO(18) => dout(20),
DOADO(17) => dout(19),
DOADO(16) => dout(18),
DOADO(15) => dout(16),
DOADO(14) => dout(15),
DOADO(13) => dout(14),
DOADO(12) => dout(13),
DOADO(11) => dout(12),
DOADO(10) => dout(11),
DOADO(9) => dout(10),
DOADO(8) => dout(9),
DOADO(7) => dout(7),
DOADO(6) => dout(6),
DOADO(5) => dout(5),
DOADO(4) => dout(4),
DOADO(3) => dout(3),
DOADO(2) => dout(2),
DOADO(1) => dout(1),
DOADO(0) => dout(0),
DOBDO(31) => dout(70),
DOBDO(30) => dout(69),
DOBDO(29) => dout(68),
DOBDO(28) => dout(67),
DOBDO(27) => dout(66),
DOBDO(26) => dout(65),
DOBDO(25) => dout(64),
DOBDO(24) => dout(63),
DOBDO(23) => dout(61),
DOBDO(22) => dout(60),
DOBDO(21) => dout(59),
DOBDO(20) => dout(58),
DOBDO(19) => dout(57),
DOBDO(18) => dout(56),
DOBDO(17) => dout(55),
DOBDO(16) => dout(54),
DOBDO(15) => dout(52),
DOBDO(14) => dout(51),
DOBDO(13) => dout(50),
DOBDO(12) => dout(49),
DOBDO(11) => dout(48),
DOBDO(10) => dout(47),
DOBDO(9) => dout(46),
DOBDO(8) => dout(45),
DOBDO(7) => dout(43),
DOBDO(6) => dout(42),
DOBDO(5) => dout(41),
DOBDO(4) => dout(40),
DOBDO(3) => dout(39),
DOBDO(2) => dout(38),
DOBDO(1) => dout(37),
DOBDO(0) => dout(36),
DOPADOP(3) => dout(35),
DOPADOP(2) => dout(26),
DOPADOP(1) => dout(17),
DOPADOP(0) => dout(8),
DOPBDOP(3) => dout(71),
DOPBDOP(2) => dout(62),
DOPBDOP(1) => dout(53),
DOPBDOP(0) => dout(44),
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_SDP_WIDE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEA(2) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEA(1) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEA(0) =>
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR,
WEBWE(7) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(6) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(5) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(4) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(3) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(2) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(1) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en,
WEBWE(0) => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_ram_wr_en
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_XST_GND : GND
port map (
G => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_DBITERR
);
U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_XST_VCC : VCC
port map (
P => U0_xst_fifo_generator_gconvfifo_rf_grf_rf_gntv_or_sync_fifo_mem_gbm_gbmg_gbmga_ngecc_bmg_gnativebmg_native_blk_mem_gen_valid_cstr_N0
);
end STRUCTURE;
-- synthesis translate_on
|
lgpl-3.0
|
c8d88d8ad7bc11ecc5752941062396cc
| 0.712279 | 2.863763 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-multicore/multicore_top.vhd
| 1 | 19,906 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.msx_pack.all;
entity multicore_top is
generic (
hdmi_output_g : boolean := false
);
port (
-- Clocks
clock_50_i : in std_logic;
-- Buttons
btn_n_i : in std_logic_vector( 4 downto 1);
btn_oe_n_i : in std_logic;
btn_clr_n_i : in std_logic;
-- SRAM (AS7C34096)
sram_addr_o : out std_logic_vector(18 downto 0) := (others => '0');
sram_data_io : inout std_logic_vector( 7 downto 0) := (others => 'Z');
sram_we_n_o : out std_logic := '1';
sram_ce_n_o : out std_logic_vector( 1 downto 0) := (others => '1');
sram_oe_n_o : out std_logic := '1';
-- PS2
ps2_clk_io : inout std_logic := 'Z';
ps2_data_io : inout std_logic := 'Z';
ps2_mouse_clk_io : inout std_logic := 'Z';
ps2_mouse_data_io : inout std_logic := 'Z';
-- SD Card
sd_cs_n_o : out std_logic := '1';
sd_sclk_o : out std_logic := '0';
sd_mosi_o : out std_logic := '0';
sd_miso_i : in std_logic;
-- Joystick
joy1_up_i : in std_logic;
joy1_down_i : in std_logic;
joy1_left_i : in std_logic;
joy1_right_i : in std_logic;
joy1_p6_io : inout std_logic := 'Z';
joy1_p7_o : out std_logic := '1';
joy1_p9_io : inout std_logic := 'Z';
joy2_up_i : in std_logic;
joy2_down_i : in std_logic;
joy2_left_i : in std_logic;
joy2_right_i : in std_logic;
joy2_p6_io : inout std_logic;
joy2_p7_o : out std_logic := '1';
joy2_p9_io : inout std_logic;
-- Audio
dac_l_o : out std_logic := '0';
dac_r_o : out std_logic := '0';
ear_i : in std_logic;
mic_o : out std_logic := '0';
-- VGA
vga_r_o : out std_logic_vector( 2 downto 0) := (others => '0');
vga_g_o : out std_logic_vector( 2 downto 0) := (others => '0');
vga_b_o : out std_logic_vector( 2 downto 0) := (others => '0');
vga_hsync_n_o : out std_logic := '1';
vga_vsync_n_o : out std_logic := '1';
-- Debug
leds_n_o : out std_logic_vector( 7 downto 0) := (others => '0')
);
end entity;
architecture behavior of multicore_top is
-- Buttons
signal btn_por_n_s : std_logic;
signal btn_reset_n_s : std_logic;
signal btn_scan_s : std_logic;
-- Resets
signal pll_locked_s : std_logic;
signal por_s : std_logic;
signal reset_s : std_logic;
signal soft_reset_k_s : std_logic;
signal soft_reset_s_s : std_logic;
signal soft_por_s : std_logic;
signal soft_rst_cnt_s : unsigned(7 downto 0) := X"FF";
-- Clocks
signal clock_mem_s : std_logic;
signal clock_master_s : std_logic;
signal clock_vdp_s : std_logic;
signal clock_cpu_s : std_logic;
signal clock_psg_en_s : std_logic;
signal clock_3m_s : std_logic;
signal turbo_on_s : std_logic;
signal clock_vga_s : std_logic;
signal clock_dvi_s : std_logic;
-- RAM
signal ram_addr_s : std_logic_vector(22 downto 0); -- 8MB
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_ce_s : std_logic;
signal ram_oe_s : std_logic;
signal ram_we_s : std_logic;
-- VRAM memory
signal vram_addr_s : std_logic_vector(13 downto 0); -- 16K
signal vram_do_s : std_logic_vector( 7 downto 0);
signal vram_di_s : std_logic_vector( 7 downto 0);
signal vram_ce_s : std_logic;
signal vram_oe_s : std_logic;
signal vram_we_s : std_logic;
-- Audio
signal audio_scc_s : signed(14 downto 0);
signal audio_psg_s : unsigned( 7 downto 0);
signal beep_s : std_logic;
signal audio_l_s : unsigned(15 downto 0);
signal audio_r_s : unsigned(15 downto 0);
signal audio_l_amp_s : unsigned(15 downto 0);
signal audio_r_amp_s : unsigned(15 downto 0);
signal volumes_s : volumes_t;
-- Video
signal rgb_col_s : std_logic_vector( 3 downto 0);
-- signal rgb_hsync_n_s : std_logic;
-- signal rgb_vsync_n_s : std_logic;
signal cnt_hor_s : std_logic_vector( 8 downto 0);
signal cnt_ver_s : std_logic_vector( 7 downto 0);
signal vga_hsync_n_s : std_logic;
signal vga_vsync_n_s : std_logic;
signal vga_blank_s : std_logic;
signal vga_col_s : std_logic_vector( 3 downto 0);
signal vga_r_s : std_logic_vector( 3 downto 0);
signal vga_g_s : std_logic_vector( 3 downto 0);
signal vga_b_s : std_logic_vector( 3 downto 0);
signal scanlines_en_s : std_logic;
signal odd_line_s : std_logic;
signal sound_hdmi_l_s : std_logic_vector(15 downto 0);
signal sound_hdmi_r_s : std_logic_vector(15 downto 0);
signal tdms_r_s : std_logic_vector( 9 downto 0);
signal tdms_g_s : std_logic_vector( 9 downto 0);
signal tdms_b_s : std_logic_vector( 9 downto 0);
signal tdms_p_s : std_logic_vector( 3 downto 0);
signal tdms_n_s : std_logic_vector( 3 downto 0);
-- Keyboard
signal rows_s : std_logic_vector( 3 downto 0);
signal cols_s : std_logic_vector( 7 downto 0);
signal caps_en_s : std_logic;
signal extra_keys_s : std_logic_vector( 3 downto 0);
signal keyb_valid_s : std_logic;
signal keyb_data_s : std_logic_vector( 7 downto 0);
signal keymap_addr_s : std_logic_vector( 8 downto 0);
signal keymap_data_s : std_logic_vector( 7 downto 0);
signal keymap_we_s : std_logic;
-- Joystick
signal joy1_out_s : std_logic;
signal joy2_out_s : std_logic;
-- Bus
signal bus_addr_s : std_logic_vector(15 downto 0);
signal bus_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal bus_data_to_s : std_logic_vector( 7 downto 0);
signal bus_rd_n_s : std_logic;
signal bus_wr_n_s : std_logic;
signal bus_m1_n_s : std_logic;
signal bus_iorq_n_s : std_logic;
signal bus_mreq_n_s : std_logic;
signal bus_sltsl1_n_s : std_logic;
signal bus_sltsl2_n_s : std_logic;
begin
-- PLL1
pll: entity work.pll1
port map (
inclk0 => clock_50_i,
c0 => clock_master_s, -- 21.477
c1 => clock_mem_s, -- 42.954
locked => pll_locked_s
);
-- PLL2
pll2: entity work.pll2
port map (
inclk0 => clock_50_i,
c0 => clock_vga_s, -- 25.200
c1 => clock_dvi_s -- 126.000
);
-- Clocks
clks: entity work.clocks
port map (
clock_i => clock_master_s,
por_i => not pll_locked_s,
turbo_on_i => turbo_on_s,
clock_vdp_o => clock_vdp_s,
clock_5m_en_o => open,
clock_cpu_o => clock_cpu_s,
clock_psg_en_o => clock_psg_en_s,
clock_3m_o => clock_3m_s
);
-- The MSX1
the_msx: entity work.msx
generic map (
hw_id_g => 5,
hw_txt_g => "Multicore Board",
hw_version_g => actual_version,
video_opt_g => 3, -- No dblscan and external palette (Color in rgb_r_o)
ramsize_g => 512,
hw_hashwds_g => '0'
)
port map (
-- Clocks
clock_i => clock_master_s,
clock_vdp_i => clock_vdp_s,
clock_cpu_i => clock_cpu_s,
clock_psg_en_i => clock_psg_en_s,
-- Turbo
turbo_on_k_i => extra_keys_s(3), -- F11
turbo_on_o => turbo_on_s,
-- Resets
reset_i => reset_s,
por_i => por_s,
softreset_o => soft_reset_s_s,
-- Options
opt_nextor_i => '1',
opt_mr_type_i => "00",
opt_vga_on_i => '0',
-- RAM
ram_addr_o => ram_addr_s,
ram_data_i => ram_data_from_s,
ram_data_o => ram_data_to_s,
ram_ce_o => ram_ce_s,
ram_we_o => ram_we_s,
ram_oe_o => ram_oe_s,
-- ROM
rom_addr_o => open,--rom_addr_s,
rom_data_i => ram_data_from_s,
rom_ce_o => open,--rom_ce_s,
rom_oe_o => open,--rom_oe_s,
-- External bus
bus_addr_o => bus_addr_s,
bus_data_i => bus_data_from_s,
bus_data_o => bus_data_to_s,
bus_rd_n_o => bus_rd_n_s,
bus_wr_n_o => bus_wr_n_s,
bus_m1_n_o => bus_m1_n_s,
bus_iorq_n_o => bus_iorq_n_s,
bus_mreq_n_o => bus_mreq_n_s,
bus_sltsl1_n_o => bus_sltsl1_n_s,
bus_sltsl2_n_o => bus_sltsl2_n_s,
bus_wait_n_i => '1',
bus_nmi_n_i => '1',
bus_int_n_i => '1',
-- VDP RAM
vram_addr_o => vram_addr_s,
vram_data_i => vram_do_s,
vram_data_o => vram_di_s,
vram_ce_o => vram_ce_s,
vram_oe_o => vram_oe_s,
vram_we_o => vram_we_s,
-- Keyboard
rows_o => rows_s,
cols_i => cols_s,
caps_en_o => caps_en_s,
keyb_valid_i => keyb_valid_s,
keyb_data_i => keyb_data_s,
keymap_addr_o => keymap_addr_s,
keymap_data_o => keymap_data_s,
keymap_we_o => keymap_we_s,
-- Audio
audio_scc_o => audio_scc_s,
audio_psg_o => audio_psg_s,
beep_o => beep_s,
volumes_o => volumes_s,
-- K7
k7_motor_o => open,
k7_audio_o => mic_o,
k7_audio_i => ear_i,
-- Joystick
joy1_up_i => joy1_up_i,
joy1_down_i => joy1_down_i,
joy1_left_i => joy1_left_i,
joy1_right_i => joy1_right_i,
joy1_btn1_i => joy1_p6_io,
joy1_btn1_o => joy1_p6_io,
joy1_btn2_i => joy1_p9_io,
joy1_btn2_o => joy1_p9_io,
joy1_out_o => joy1_out_s,
joy2_up_i => joy2_up_i,
joy2_down_i => joy2_down_i,
joy2_left_i => joy2_left_i,
joy2_right_i => joy2_right_i,
joy2_btn1_i => joy2_p6_io,
joy2_btn1_o => joy2_p6_io,
joy2_btn2_i => joy2_p9_io,
joy2_btn2_o => joy2_p9_io,
joy2_out_o => joy2_out_s,
-- Video
cnt_hor_o => cnt_hor_s,
cnt_ver_o => cnt_ver_s,
rgb_r_o => rgb_col_s,
rgb_g_o => open,
rgb_b_o => open,
hsync_n_o => open,--rgb_hsync_n_s,
vsync_n_o => open,--rgb_vsync_n_s,
ntsc_pal_o => open,
vga_on_k_i => '0',
scanline_on_k_i=> '0',
vga_en_o => open,
-- SPI/SD
flspi_cs_n_o => open,
spi_cs_n_o => sd_cs_n_o,
spi_sclk_o => sd_sclk_o,
spi_mosi_o => sd_mosi_o,
spi_miso_i => sd_miso_i,
sd_pres_n_i => '0',
sd_wp_i => '0',
-- DEBUG
D_wait_o => open,
D_slots_o => open,
D_ipl_en_o => open
);
joy1_p7_o <= not joy1_out_s; -- for Sega Genesis joypad
joy2_p7_o <= not joy2_out_s; -- for Sega Genesis joypad
-- Keyboard PS/2
keyb: entity work.keyboard
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
-- MSX
rows_coded_i => rows_s,
cols_o => cols_s,
keymap_addr_i => keymap_addr_s,
keymap_data_i => keymap_data_s,
keymap_we_i => keymap_we_s,
-- LEDs
led_caps_i => caps_en_s,
-- PS/2 interface
ps2_clk_io => ps2_clk_io,
ps2_data_io => ps2_data_io,
-- Direct Access
keyb_valid_o => keyb_valid_s,
keyb_data_o => keyb_data_s,
--
reset_o => soft_reset_k_s,
por_o => soft_por_s,
reload_core_o => open,
extra_keys_o => extra_keys_s
);
-- RAM and VRAM
sram0: entity work.dpSRAM_5128
port map (
clk_i => clock_mem_s,
-- Port 0
porta0_addr_i => "11101" & vram_addr_s,
porta0_ce_i => vram_ce_s,
porta0_oe_i => vram_oe_s,
porta0_we_i => vram_we_s,
porta0_data_i => vram_di_s,
porta0_data_o => vram_do_s,
-- Port 1
porta1_addr_i => ram_addr_s(18 downto 0),
porta1_ce_i => ram_ce_s,
porta1_oe_i => ram_oe_s,
porta1_we_i => ram_we_s,
porta1_data_i => ram_data_to_s,
porta1_data_o => ram_data_from_s,
-- SRAM in board
sram_addr_o => sram_addr_o,
sram_data_io => sram_data_io,
sram_ce_n_o => sram_ce_n_o(0),
sram_oe_n_o => sram_oe_n_o,
sram_we_n_o => sram_we_n_o
);
-- Audio
mixer: entity work.mixeru
port map (
clock_i => clock_master_s,
reset_i => reset_s,
volumes_i => volumes_s,
beep_i => beep_s,
ear_i => ear_i,
audio_scc_i => audio_scc_s,
audio_psg_i => audio_psg_s,
jt51_left_i => (others => '0'),
jt51_right_i => (others => '0'),
opll_mo_i => (others => '0'),
opll_ro_i => (others => '0'),
audio_mix_l_o => audio_l_s,
audio_mix_r_o => audio_r_s
);
audio_l_amp_s <= audio_l_s(15) & audio_l_s(13 downto 0) & "0";
audio_r_amp_s <= audio_r_s(15) & audio_r_s(13 downto 0) & "0";
-- Left Channel
audiol : entity work.dac
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_3m_s,
dac_i => audio_l_amp_s,
dac_o => dac_l_o
);
-- Right Channel
audior : entity work.dac
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_3m_s,
dac_i => audio_r_amp_s,
dac_o => dac_r_o
);
-- Glue logic
-- Resets
btn_por_n_s <= btn_n_i(2) or btn_n_i(4);
btn_reset_n_s <= btn_n_i(3) or btn_n_i(4);
por_s <= '1' when pll_locked_s = '0' or soft_por_s = '1' or btn_por_n_s = '0' else '0';
reset_s <= '1' when soft_rst_cnt_s = X"01" or btn_reset_n_s = '0' else '0';
process(reset_s, clock_master_s)
begin
if reset_s = '1' then
soft_rst_cnt_s <= X"00";
elsif rising_edge(clock_master_s) then
if (soft_reset_k_s = '1' or soft_reset_s_s = '1' or por_s = '1') and soft_rst_cnt_s = X"00" then
soft_rst_cnt_s <= X"FF";
elsif soft_rst_cnt_s /= X"00" then
soft_rst_cnt_s <= soft_rst_cnt_s - 1;
end if;
end if;
end process;
---------------------------------
-- scanlines
btnscl: entity work.debounce
generic map (
counter_size_g => 16
)
port map (
clk_i => clock_master_s,
button_i => btn_n_i(1) or btn_n_i(2),
result_o => btn_scan_s
);
process (por_s, btn_scan_s)
begin
if por_s = '1' then
scanlines_en_s <= '0';
elsif falling_edge(btn_scan_s) then
scanlines_en_s <= not scanlines_en_s;
end if;
end process;
-- VGA framebuffer
vga: entity work.vga
port map (
I_CLK => clock_master_s,
I_CLK_VGA => clock_vga_s,
I_COLOR => rgb_col_s,
I_HCNT => cnt_hor_s,
I_VCNT => cnt_ver_s,
O_HSYNC => vga_hsync_n_s,
O_VSYNC => vga_vsync_n_s,
O_COLOR => vga_col_s,
O_HCNT => open,
O_VCNT => open,
O_H => open,
O_BLANK => vga_blank_s
);
-- Scanlines
process(vga_hsync_n_s,vga_vsync_n_s)
begin
if vga_vsync_n_s = '0' then
odd_line_s <= '0';
elsif rising_edge(vga_hsync_n_s) then
odd_line_s <= not odd_line_s;
end if;
end process;
-- Index => RGB
process (clock_vga_s)
variable vga_col_v : integer range 0 to 15;
variable vga_rgb_v : std_logic_vector(15 downto 0);
variable vga_r_v : std_logic_vector( 3 downto 0);
variable vga_g_v : std_logic_vector( 3 downto 0);
variable vga_b_v : std_logic_vector( 3 downto 0);
type ram_t is array (natural range 0 to 15) of std_logic_vector(15 downto 0);
constant rgb_c : ram_t := (
-- RB0G
0 => X"0000",
1 => X"0000",
2 => X"240C",
3 => X"570D",
4 => X"5E05",
5 => X"7F07",
6 => X"D405",
7 => X"4F0E",
8 => X"F505",
9 => X"F707",
10 => X"D50C",
11 => X"E80C",
12 => X"230B",
13 => X"CB09",
14 => X"CC0C",
15 => X"FF0F"
);
begin
if rising_edge(clock_vga_s) then
vga_col_v := to_integer(unsigned(vga_col_s));
vga_rgb_v := rgb_c(vga_col_v);
if scanlines_en_s = '1' then
--
if vga_rgb_v(15 downto 12) > 1 and odd_line_s = '1' then
vga_r_s <= vga_rgb_v(15 downto 12) - 2;
else
vga_r_s <= vga_rgb_v(15 downto 12);
end if;
--
if vga_rgb_v(11 downto 8) > 1 and odd_line_s = '1' then
vga_b_s <= vga_rgb_v(11 downto 8) - 2;
else
vga_b_s <= vga_rgb_v(11 downto 8);
end if;
--
if vga_rgb_v(3 downto 0) > 1 and odd_line_s = '1' then
vga_g_s <= vga_rgb_v(3 downto 0) - 2;
else
vga_g_s <= vga_rgb_v(3 downto 0);
end if;
else
vga_r_s <= vga_rgb_v(15 downto 12);
vga_b_s <= vga_rgb_v(11 downto 8);
vga_g_s <= vga_rgb_v( 3 downto 0);
end if;
end if;
end process;
uh: if hdmi_output_g generate
sound_hdmi_l_s <= '0' & std_logic_vector(audio_l_amp_s(15 downto 1));
sound_hdmi_r_s <= '0' & std_logic_vector(audio_r_amp_s(15 downto 1));
-- HDMI
hdmi: entity work.hdmi
generic map (
FREQ => 25200000, -- pixel clock frequency
FS => 48000, -- audio sample rate - should be 32000, 41000 or 48000 = 48KHz
CTS => 25200, -- CTS = Freq(pixclk) * N / (128 * Fs)
N => 6144 -- N = 128 * Fs /1000, 128 * Fs /1500 <= N <= 128 * Fs /300 (Check HDMI spec 7.2 for details)
)
port map (
I_CLK_PIXEL => clock_vga_s,
I_R => vga_r_s & vga_r_s,
I_G => vga_g_s & vga_g_s,
I_B => vga_b_s & vga_b_s,
I_BLANK => vga_blank_s,
I_HSYNC => vga_hsync_n_s,
I_VSYNC => vga_vsync_n_s,
-- PCM audio
I_AUDIO_ENABLE => '1',
I_AUDIO_PCM_L => sound_hdmi_l_s,
I_AUDIO_PCM_R => sound_hdmi_r_s,
-- TMDS parallel pixel synchronous outputs (serialize LSB first)
O_RED => tdms_r_s,
O_GREEN => tdms_g_s,
O_BLUE => tdms_b_s
);
hdmio: entity work.hdmi_out_altera
port map (
clock_pixel_i => clock_vga_s,
clock_tdms_i => clock_dvi_s,
red_i => tdms_r_s,
green_i => tdms_g_s,
blue_i => tdms_b_s,
tmds_out_p => tdms_p_s,
tmds_out_n => tdms_n_s
);
vga_hsync_n_o <= tdms_p_s(2); -- 2+ 10
vga_vsync_n_o <= tdms_n_s(2); -- 2- 11
vga_b_o(2) <= tdms_p_s(1); -- 1+ 144
vga_b_o(1) <= tdms_n_s(1); -- 1- 143
vga_r_o(0) <= tdms_p_s(0); -- 0+ 133
vga_g_o(2) <= tdms_n_s(0); -- 0- 132
vga_r_o(1) <= tdms_p_s(3); -- CLK+ 113
vga_r_o(2) <= tdms_n_s(3); -- CLK- 112
end generate;
nuh: if not hdmi_output_g generate
vga_r_o <= vga_r_s(3 downto 1);
vga_g_o <= vga_g_s(3 downto 1);
vga_b_o <= vga_b_s(3 downto 1);
vga_hsync_n_o <= vga_hsync_n_s;
vga_vsync_n_o <= vga_vsync_n_s;
end generate;
-- DEBUG
leds_n_o(0) <= not turbo_on_s;
-- leds_n_o(1) <= not caps_en_s;
-- leds_n_o(2) <= not soft_reset_k_s;
-- leds_n_o(3) <= not soft_por_s;
end architecture;
|
gpl-3.0
|
c37fc7b5e61d38e9e4cc3d2b990a5002
| 0.558425 | 2.305536 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/bram_x64.vhd
| 1 | 365,528 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68d
-- \ \ Application: netgen
-- / / Filename: bram_x64.vhd
-- /___/ /\ Timestamp: Fri Sep 6 17:21:24 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.vhd
-- Device : 6vlx240tff1156-1
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.vhd
-- # of Entities : 1
-- Design Name : bram_x64
-- Xilinx : /opt/Xilinx/14.6/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity bram_x64 is
port (
clka : in STD_LOGIC := 'X';
clkb : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
web : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end bram_x64;
architecture STRUCTURE of bram_x64 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => N1
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(63),
DIADI(6) => dina(62),
DIADI(5) => dina(61),
DIADI(4) => dina(60),
DIADI(3) => dina(59),
DIADI(2) => dina(58),
DIADI(1) => dina(57),
DIADI(0) => dina(56),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(63),
DIBDI(6) => dinb(62),
DIBDI(5) => dinb(61),
DIBDI(4) => dinb(60),
DIBDI(3) => dinb(59),
DIBDI(2) => dinb(58),
DIBDI(1) => dinb(57),
DIBDI(0) => dinb(56),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(63),
DOADO(6) => douta(62),
DOADO(5) => douta(61),
DOADO(4) => douta(60),
DOADO(3) => douta(59),
DOADO(2) => douta(58),
DOADO(1) => douta(57),
DOADO(0) => douta(56),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(63),
DOBDO(6) => doutb(62),
DOBDO(5) => doutb(61),
DOBDO(4) => doutb(60),
DOBDO(3) => doutb(59),
DOBDO(2) => doutb(58),
DOBDO(1) => doutb(57),
DOBDO(0) => doutb(56),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(7),
WEA(2) => wea(7),
WEA(1) => wea(7),
WEA(0) => wea(7),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(7),
WEBWE(2) => web(7),
WEBWE(1) => web(7),
WEBWE(0) => web(7)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(55),
DIADI(6) => dina(54),
DIADI(5) => dina(53),
DIADI(4) => dina(52),
DIADI(3) => dina(51),
DIADI(2) => dina(50),
DIADI(1) => dina(49),
DIADI(0) => dina(48),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(55),
DIBDI(6) => dinb(54),
DIBDI(5) => dinb(53),
DIBDI(4) => dinb(52),
DIBDI(3) => dinb(51),
DIBDI(2) => dinb(50),
DIBDI(1) => dinb(49),
DIBDI(0) => dinb(48),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(55),
DOADO(6) => douta(54),
DOADO(5) => douta(53),
DOADO(4) => douta(52),
DOADO(3) => douta(51),
DOADO(2) => douta(50),
DOADO(1) => douta(49),
DOADO(0) => douta(48),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(55),
DOBDO(6) => doutb(54),
DOBDO(5) => doutb(53),
DOBDO(4) => doutb(52),
DOBDO(3) => doutb(51),
DOBDO(2) => doutb(50),
DOBDO(1) => doutb(49),
DOBDO(0) => doutb(48),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(6),
WEA(2) => wea(6),
WEA(1) => wea(6),
WEA(0) => wea(6),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(6),
WEBWE(2) => web(6),
WEBWE(1) => web(6),
WEBWE(0) => web(6)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(47),
DIADI(6) => dina(46),
DIADI(5) => dina(45),
DIADI(4) => dina(44),
DIADI(3) => dina(43),
DIADI(2) => dina(42),
DIADI(1) => dina(41),
DIADI(0) => dina(40),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(47),
DIBDI(6) => dinb(46),
DIBDI(5) => dinb(45),
DIBDI(4) => dinb(44),
DIBDI(3) => dinb(43),
DIBDI(2) => dinb(42),
DIBDI(1) => dinb(41),
DIBDI(0) => dinb(40),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(47),
DOADO(6) => douta(46),
DOADO(5) => douta(45),
DOADO(4) => douta(44),
DOADO(3) => douta(43),
DOADO(2) => douta(42),
DOADO(1) => douta(41),
DOADO(0) => douta(40),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(47),
DOBDO(6) => doutb(46),
DOBDO(5) => doutb(45),
DOBDO(4) => doutb(44),
DOBDO(3) => doutb(43),
DOBDO(2) => doutb(42),
DOBDO(1) => doutb(41),
DOBDO(0) => doutb(40),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(5),
WEA(2) => wea(5),
WEA(1) => wea(5),
WEA(0) => wea(5),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(5),
WEBWE(2) => web(5),
WEBWE(1) => web(5),
WEBWE(0) => web(5)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(39),
DIADI(6) => dina(38),
DIADI(5) => dina(37),
DIADI(4) => dina(36),
DIADI(3) => dina(35),
DIADI(2) => dina(34),
DIADI(1) => dina(33),
DIADI(0) => dina(32),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(39),
DIBDI(6) => dinb(38),
DIBDI(5) => dinb(37),
DIBDI(4) => dinb(36),
DIBDI(3) => dinb(35),
DIBDI(2) => dinb(34),
DIBDI(1) => dinb(33),
DIBDI(0) => dinb(32),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(39),
DOADO(6) => douta(38),
DOADO(5) => douta(37),
DOADO(4) => douta(36),
DOADO(3) => douta(35),
DOADO(2) => douta(34),
DOADO(1) => douta(33),
DOADO(0) => douta(32),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(39),
DOBDO(6) => doutb(38),
DOBDO(5) => doutb(37),
DOBDO(4) => doutb(36),
DOBDO(3) => doutb(35),
DOBDO(2) => doutb(34),
DOBDO(1) => doutb(33),
DOBDO(0) => doutb(32),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(4),
WEA(2) => wea(4),
WEA(1) => wea(4),
WEA(0) => wea(4),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(4),
WEBWE(2) => web(4),
WEBWE(1) => web(4),
WEBWE(0) => web(4)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(31),
DIADI(6) => dina(30),
DIADI(5) => dina(29),
DIADI(4) => dina(28),
DIADI(3) => dina(27),
DIADI(2) => dina(26),
DIADI(1) => dina(25),
DIADI(0) => dina(24),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(31),
DIBDI(6) => dinb(30),
DIBDI(5) => dinb(29),
DIBDI(4) => dinb(28),
DIBDI(3) => dinb(27),
DIBDI(2) => dinb(26),
DIBDI(1) => dinb(25),
DIBDI(0) => dinb(24),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(31),
DOADO(6) => douta(30),
DOADO(5) => douta(29),
DOADO(4) => douta(28),
DOADO(3) => douta(27),
DOADO(2) => douta(26),
DOADO(1) => douta(25),
DOADO(0) => douta(24),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(31),
DOBDO(6) => doutb(30),
DOBDO(5) => doutb(29),
DOBDO(4) => doutb(28),
DOBDO(3) => doutb(27),
DOBDO(2) => doutb(26),
DOBDO(1) => doutb(25),
DOBDO(0) => doutb(24),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(3),
WEA(2) => wea(3),
WEA(1) => wea(3),
WEA(0) => wea(3),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(3),
WEBWE(2) => web(3),
WEBWE(1) => web(3),
WEBWE(0) => web(3)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(23),
DIADI(6) => dina(22),
DIADI(5) => dina(21),
DIADI(4) => dina(20),
DIADI(3) => dina(19),
DIADI(2) => dina(18),
DIADI(1) => dina(17),
DIADI(0) => dina(16),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(23),
DIBDI(6) => dinb(22),
DIBDI(5) => dinb(21),
DIBDI(4) => dinb(20),
DIBDI(3) => dinb(19),
DIBDI(2) => dinb(18),
DIBDI(1) => dinb(17),
DIBDI(0) => dinb(16),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(23),
DOADO(6) => douta(22),
DOADO(5) => douta(21),
DOADO(4) => douta(20),
DOADO(3) => douta(19),
DOADO(2) => douta(18),
DOADO(1) => douta(17),
DOADO(0) => douta(16),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(23),
DOBDO(6) => doutb(22),
DOBDO(5) => doutb(21),
DOBDO(4) => doutb(20),
DOBDO(3) => doutb(19),
DOBDO(2) => doutb(18),
DOBDO(1) => doutb(17),
DOBDO(0) => doutb(16),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(2),
WEA(2) => wea(2),
WEA(1) => wea(2),
WEA(0) => wea(2),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(2),
WEBWE(2) => web(2),
WEBWE(1) => web(2),
WEBWE(0) => web(2)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(15),
DIADI(6) => dina(14),
DIADI(5) => dina(13),
DIADI(4) => dina(12),
DIADI(3) => dina(11),
DIADI(2) => dina(10),
DIADI(1) => dina(9),
DIADI(0) => dina(8),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(15),
DIBDI(6) => dinb(14),
DIBDI(5) => dinb(13),
DIBDI(4) => dinb(12),
DIBDI(3) => dinb(11),
DIBDI(2) => dinb(10),
DIBDI(1) => dinb(9),
DIBDI(0) => dinb(8),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(15),
DOADO(6) => douta(14),
DOADO(5) => douta(13),
DOADO(4) => douta(12),
DOADO(3) => douta(11),
DOADO(2) => douta(10),
DOADO(1) => douta(9),
DOADO(0) => douta(8),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(15),
DOBDO(6) => doutb(14),
DOBDO(5) => doutb(13),
DOBDO(4) => doutb(12),
DOBDO(3) => doutb(11),
DOBDO(2) => doutb(10),
DOBDO(1) => doutb(9),
DOBDO(0) => doutb(8),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(1),
WEA(2) => wea(1),
WEA(1) => wea(1),
WEA(0) => wea(1),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(1),
WEBWE(2) => web(1),
WEBWE(1) => web(1),
WEBWE(0) => web(1)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(7),
DIADI(6) => dina(6),
DIADI(5) => dina(5),
DIADI(4) => dina(4),
DIADI(3) => dina(3),
DIADI(2) => dina(2),
DIADI(1) => dina(1),
DIADI(0) => dina(0),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(7),
DIBDI(6) => dinb(6),
DIBDI(5) => dinb(5),
DIBDI(4) => dinb(4),
DIBDI(3) => dinb(3),
DIBDI(2) => dinb(2),
DIBDI(1) => dinb(1),
DIBDI(0) => dinb(0),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(7),
DOADO(6) => douta(6),
DOADO(5) => douta(5),
DOADO(4) => douta(4),
DOADO(3) => douta(3),
DOADO(2) => douta(2),
DOADO(1) => douta(1),
DOADO(0) => douta(0),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(7),
DOBDO(6) => doutb(6),
DOBDO(5) => doutb(5),
DOBDO(4) => doutb(4),
DOBDO(3) => doutb(3),
DOBDO(2) => doutb(2),
DOBDO(1) => doutb(1),
DOBDO(0) => doutb(0),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
-- synthesis translate_on
|
lgpl-3.0
|
64572e741c98714f8de32852d45057fa
| 0.747582 | 3.217534 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/peripheral/swioports.vhd
| 2 | 14,795 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.msx_pack.all;
entity swioports is
port (
por_i : in std_logic;
reset_i : in std_logic;
clock_i : in std_logic;
clock_cpu_i : in std_logic;
addr_i : in std_logic_vector( 7 downto 0);
cs_i : in std_logic;
rd_i : in std_logic;
wr_i : in std_logic;
data_i : in std_logic_vector( 7 downto 0);
data_o : out std_logic_vector( 7 downto 0);
has_data_o : out std_logic;
--
hw_id_i : in std_logic_vector( 7 downto 0);
hw_txt_i : in string;
hw_version_i : in std_logic_vector( 7 downto 0);
hw_memsize_i : in std_logic_vector( 7 downto 0);
hw_hashwds_i : in std_logic;
nextor_en_i : in std_logic;
mr_type_i : in std_logic_vector( 1 downto 0);
vga_on_i : in std_logic;
turbo_on_k_i : in std_logic;
vga_on_k_i : in std_logic;
scanline_on_k_i: in std_logic;
vertfreq_on_k_i: in std_logic;
vertfreq_csw_i : in std_logic;
vertfreq_d_i : in std_logic;
keyb_valid_i : in std_logic;
keyb_data_i : in std_logic_vector( 7 downto 0);
--
nextor_en_o : out std_logic;
mr_type_o : out std_logic_vector( 1 downto 0);
turbo_on_o : out std_logic;
reload_o : out std_logic;
softreset_o : out std_logic;
vga_en_o : out std_logic;
scanline_en_o : out std_logic;
ntsc_pal_o : out std_logic; -- 0 = NTSC
keymap_addr_o : out std_logic_vector( 8 downto 0);
keymap_data_o : out std_logic_vector( 7 downto 0);
keymap_we_o : out std_logic;
volumes_o : out volumes_t
);
end entity;
architecture Behavior of swioports is
constant MYMKID_C : std_logic_vector(7 downto 0) := X"28";
constant PANAMKID_C : std_logic_vector(7 downto 0) := X"08";
constant OCMMKID_C : std_logic_vector(7 downto 0) := X"D4";
signal maker_id_s : std_logic_vector(7 downto 0);
signal has_data_mkid_s : std_logic;
signal has_data_regv_s : std_logic;
signal reg_addr_q : std_logic_vector(7 downto 0);
signal reg_data_s : std_logic_vector(7 downto 0);
signal nextor_en_q : std_logic;
signal mapper_q : std_logic_vector(1 downto 0);
signal turbo_on_q : std_logic := '0';
signal reload_q : std_logic := '0';
signal softreset_q : std_logic := '0';
signal spulse_r_s : std_logic_vector(1 downto 0) := (others => '0');
signal spulse_w_s : std_logic_vector(1 downto 0) := (others => '0');
signal keyfifo_r_s : std_logic := '0';
signal keyfifo_w_s : std_logic := '0';
signal keyfifo_data_s : std_logic_vector(7 downto 0);
signal keyfifo_empty_s : std_logic;
signal keyfifo_full_s : std_logic;
signal keymap_addr_q : unsigned(8 downto 0);
signal keymap_data_q : std_logic_vector(7 downto 0);
signal keymap_we_s : std_logic;
signal vga_en_q : std_logic;
signal scanline_en_q : std_logic := '0';
signal ntsc_pal_q : std_logic := '0';
signal volumes_q : volumes_t;
begin
-- PS/2 keyscan FIFO
ps2fifo : entity work.fifo
generic map (
DATA_WIDTH_G => 8,
FIFO_DEPTH_G => 16
)
port map (
clock_i => clock_i,
reset_i => reset_i,
write_en_i => keyfifo_w_s,
data_i => keyb_data_i,
read_en_i => keyfifo_r_s,
data_o => keyfifo_data_s,
empty_o => keyfifo_empty_s,
full_o => keyfifo_full_s
);
keyfifo_r_s <= '1' when spulse_r_s = "01" else '0';
keyfifo_w_s <= '1' when spulse_w_s = "01" else '0';
-- Maker ID
process (reset_i, clock_cpu_i)
begin
if reset_i = '1' then
maker_id_s <= (others => '0');
elsif falling_edge(clock_cpu_i) then
if cs_i = '1' and wr_i = '1' and addr_i = X"40" then
if data_i = PANAMKID_C or data_i = MYMKID_C or data_i = OCMMKID_C then
maker_id_s <= data_i;
else
maker_id_s <= X"00";
end if;
end if;
end if;
end process;
-- Reading Maker ID
has_data_mkid_s <= '1' when addr_i = X"40" else '0';
-- Has data to reading
has_data_o <= '1' when cs_i = '1' and rd_i = '1' and has_data_mkid_s = '1' else
'1' when cs_i = '1' and rd_i = '1' and has_data_regv_s = '1' else
'0';
data_o <= not maker_id_s when has_data_mkid_s = '1' else
reg_data_s when has_data_regv_s = '1' else
(others => '1');
-- Set register number (only if maker id = 40)
process (reset_i, clock_cpu_i)
begin
if reset_i = '1' then
reg_addr_q <= (others => '0');
elsif falling_edge(clock_cpu_i) then
if cs_i = '1' and wr_i = '1' and maker_id_s = MYMKID_C and addr_i = X"48" then
reg_addr_q <= data_i;
end if;
end if;
end process;
-- Write to Switched I/O ports
process (por_i, reset_i, clock_cpu_i, nextor_en_i, mr_type_i, vga_on_i)
variable turbo_on_de_v : std_logic_vector(1 downto 0) := "00";
variable vga_on_de_v : std_logic_vector(1 downto 0) := "00";
variable scln_on_de_v : std_logic_vector(1 downto 0) := "00";
variable vf_on_de_v : std_logic_vector(1 downto 0) := "00";
variable keymap_we_a_v : std_logic;
begin
if por_i = '1' then
nextor_en_q <= nextor_en_i;
mapper_q <= mr_type_i;
turbo_on_q <= '0';
vga_en_q <= vga_on_i;
scanline_en_q <= '0';
ntsc_pal_q <= '0';
reload_q <= '0';
-- default volumes
volumes_q.beep <= std_logic_vector(to_unsigned(default_vol_beep, 8));
volumes_q.ear <= std_logic_vector(to_unsigned(default_vol_ear, 8));
volumes_q.psg <= std_logic_vector(to_unsigned(default_vol_psg, 8));
volumes_q.scc <= std_logic_vector(to_unsigned(default_vol_scc, 8));
volumes_q.opll <= std_logic_vector(to_unsigned(default_vol_opll, 8));
volumes_q.aux1 <= std_logic_vector(to_unsigned(default_vol_aux1, 8));
elsif reset_i = '1' then
softreset_q <= '0';
keymap_we_s <= '0';
elsif falling_edge(clock_cpu_i) then
turbo_on_de_v := turbo_on_de_v(0) & turbo_on_k_i;
vga_on_de_v := vga_on_de_v(0) & vga_on_k_i;
scln_on_de_v := scln_on_de_v(0) & scanline_on_k_i;
vf_on_de_v := vf_on_de_v(0) & vertfreq_on_k_i;
if turbo_on_de_v = "01" then
turbo_on_q <= not turbo_on_q;
end if;
if vga_on_de_v = "01" then
vga_en_q <= not vga_en_q;
end if;
if scln_on_de_v = "01" then
scanline_en_q <= not scanline_en_q;
end if;
if vf_on_de_v = "01" then
ntsc_pal_q <= not ntsc_pal_q;
end if;
keymap_we_s <= '0'; -- default
-- Vertical frequency control by VDP
if vertfreq_csw_i = '1' then
ntsc_pal_q <= vertfreq_d_i;
end if;
-- Panasonic
if cs_i = '1' and wr_i = '1' and maker_id_s = PANAMKID_C then
if addr_i = X"41" then
turbo_on_q <= not data_i(0);
end if;
-- MSX1FPGA ID
elsif cs_i = '1' and wr_i = '1' and maker_id_s = MYMKID_C and addr_i = X"49" then
case reg_addr_q is
when X"0A" =>
reload_q <= data_i(7);
softreset_q <= data_i(0);
when X"0D" =>
keymap_addr_q(7 downto 0) <= unsigned(data_i);
when X"0E" =>
keymap_addr_q(8 downto 8) <= unsigned(data_i(0 downto 0));
when X"0F" =>
keymap_data_q <= data_i;
keymap_we_s <= '1';
when X"10" =>
ntsc_pal_q <= data_i(3);
scanline_en_q <= data_i(2);
vga_en_q <= data_i(1);
nextor_en_q <= data_i(0);
when X"11" =>
mapper_q <= data_i(1 downto 0);
when X"12" =>
turbo_on_q <= data_i(0);
when X"20" =>
volumes_q.beep <= data_i;
when X"21" =>
volumes_q.ear <= data_i;
when X"22" =>
volumes_q.psg <= data_i;
when X"23" =>
volumes_q.scc <= data_i;
when X"24" =>
volumes_q.opll <= data_i;
when X"25" =>
volumes_q.aux1 <= data_i;
when others =>
null;
end case;
-- KdL ID (only for MGLOCM)
elsif cs_i = '1' and wr_i = '1' and maker_id_s = OCMMKID_C then
if addr_i = X"41" then
-- Smart Command
if data_i = X"03" then
turbo_on_q <= '0';
elsif data_i = X"0A" then
turbo_on_q <= '1';
elsif data_i = X"0F" then
mapper_q <= "00";
elsif data_i = X"10" then
mapper_q <= "00";
elsif data_i = X"11" then
mapper_q <= "01";
elsif data_i = X"12" then
mapper_q <= "01";
elsif data_i = X"13" then
mapper_q <= "11";
elsif data_i = X"14" then
mapper_q <= "11";
elsif data_i = X"41" then
turbo_on_q <= '1';
end if;
end if;
end if;
if keymap_we_a_v = '1' and keymap_we_s = '0' then
keymap_addr_q <= keymap_addr_q + 1;
end if;
keymap_we_a_v := keymap_we_s;
end if;
end process;
-- Detect edges for reading and writing FIFO
process (reset_i, clock_i)
begin
if reset_i = '1' then
spulse_r_s <= (others => '0');
spulse_w_s <= (others => '0');
elsif rising_edge(clock_i) then
spulse_w_s <= spulse_w_s(0) & keyb_valid_i;
spulse_r_s <= spulse_r_s(0) & '0';
if cs_i = '1' and rd_i = '1' and maker_id_s = MYMKID_C and addr_i = X"49" then
if reg_addr_q = X"0C" then
spulse_r_s(0) <= '1';
end if;
end if;
end if;
end process;
-- Reading register
process (reset_i, clock_cpu_i)
variable index_v : integer range 0 to 20 := 0;
variable reading_v : boolean := false;
variable char_v : character;
begin
if reset_i = '1' then
reading_v := false;
index_v := 0;
elsif falling_edge(clock_cpu_i) then
has_data_regv_s <= '0';
reg_data_s <= (others => '0');
-- Panasonic
if cs_i = '1' and rd_i = '1' and maker_id_s = PANAMKID_C then
if addr_i = X"41" then
reg_data_s <= "0000000" & not turbo_on_q;
has_data_regv_s <= '1';
end if;
-- MSX1FPGA ID
elsif cs_i = '1' and rd_i = '1' and maker_id_s = MYMKID_C and addr_i = X"49" then
case reg_addr_q is
when X"00" =>
reg_data_s <= hw_id_i;
has_data_regv_s <= '1';
index_v := 0;
when X"01" =>
if index_v = hw_txt_i'length then
reg_data_s <= (others => '0');
else
char_v := hw_txt_i(index_v + 1);
reg_data_s <= std_logic_vector(to_unsigned(character'pos(char_v), 8));
end if;
has_data_regv_s <= '1';
reading_v := true;
when X"02" =>
reg_data_s <= hw_version_i;
has_data_regv_s <= '1';
when X"03" =>
reg_data_s <= hw_memsize_i;
has_data_regv_s <= '1';
when X"04" =>
reg_data_s <= "0000000" & hw_hashwds_i;
has_data_regv_s <= '1';
when X"0B" =>
reg_data_s <= "000000" & keyfifo_empty_s & keyfifo_full_s;
has_data_regv_s <= '1';
when X"0C" =>
reg_data_s <= keyfifo_data_s;
has_data_regv_s <= '1';
when X"10" =>
reg_data_s <= "0000" & ntsc_pal_q & scanline_en_q & vga_en_q & nextor_en_q;
has_data_regv_s <= '1';
when X"11" =>
reg_data_s <= "000000" & mapper_q;
has_data_regv_s <= '1';
when X"12" =>
reg_data_s <= "0000000" & turbo_on_q;
has_data_regv_s <= '1';
when X"20" =>
reg_data_s <= volumes_q.beep;
has_data_regv_s <= '1';
when X"21" =>
reg_data_s <= volumes_q.ear;
has_data_regv_s <= '1';
when X"22" =>
reg_data_s <= volumes_q.psg;
has_data_regv_s <= '1';
when X"23" =>
reg_data_s <= volumes_q.scc;
has_data_regv_s <= '1';
when X"24" =>
reg_data_s <= volumes_q.opll;
has_data_regv_s <= '1';
when X"25" =>
reg_data_s <= volumes_q.aux1;
has_data_regv_s <= '1';
when others =>
null;
end case;
-- KdL ID
elsif cs_i = '1' and rd_i = '1' and maker_id_s = OCMMKID_C then
if addr_i = X"42" then
reg_data_s <= nextor_en_q & "0" & mapper_q & "0000";
has_data_regv_s <= '1';
elsif addr_i = X"49" then
reg_data_s <= "01000000";
has_data_regv_s <= '1';
elsif addr_i = X"4E" then
reg_data_s <= nextor_en_q & "0" & mapper_q & "0000";
has_data_regv_s <= '1';
elsif addr_i = X"4F" then
reg_data_s <= "00000100";
has_data_regv_s <= '1';
end if;
elsif reading_v then
if index_v < hw_txt_i'length then
index_v := index_v + 1;
end if;
reading_v := false;
end if;
end if;
end process;
--
nextor_en_o <= nextor_en_q;
mr_type_o <= mapper_q;
turbo_on_o <= turbo_on_q;
reload_o <= reload_q;
softreset_o <= softreset_q;
keymap_addr_o <= std_logic_vector(keymap_addr_q);
keymap_data_o <= keymap_data_q;
keymap_we_o <= keymap_we_s;
vga_en_o <= vga_en_q;
scanline_en_o <= scanline_en_q;
ntsc_pal_o <= ntsc_pal_q;
volumes_o <= volumes_q;
end architecture;
|
gpl-3.0
|
cd77cc6e045b4b5c73acd1620e70d938
| 0.559446 | 2.532957 | false | false | false | false |
peteg944/music-fpga
|
Experimental/Zedboard UART/fpga_top.vhd
| 1 | 4,706 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fpga_top is
Port ( clk : in STD_LOGIC;
led : out STD_LOGIC;
bluetooth_rxd : out STD_LOGIC;
bluetooth_txd : in STD_LOGIC;
display_rgb1 : out STD_LOGIC_VECTOR (2 downto 0);
display_rgb2 : out STD_LOGIC_VECTOR (2 downto 0);
display_addr : out STD_LOGIC_VECTOR (3 downto 0);
display_clk : out STD_LOGIC;
display_oe : out STD_LOGIC;
display_lat : out STD_LOGIC;
usb_rxd : out STD_LOGIC;
usb_txd : in STD_LOGIC;
height : in STD_LOGIC_VECTOR (3 downto 0);
mode : in STD_LOGIC;
on_off : in STD_LOGIC;
sysclk : in STD_LOGIC;
uartclk : in STD_LOGIC;
pll_locked : in STD_LOGIC;
uart_active : in STD_LOGIC
);
end fpga_top;
architecture rtl of fpga_top is
--component pll
-- port
-- (-- Clock in ports
-- CLK_IN : in std_logic;
-- -- Clock out ports
-- CLK_OUT1 : out std_logic;
-- CLK_OUT2 : out std_logic;
-- -- Status and control signals
-- RESET : in std_logic;
-- LOCKED : out std_logic
-- );
--end component;
component uart_rx
generic (
log2_oversampling : integer := 7);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end component;
component display_control
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
display_ena : in STD_LOGIC;
ram_data : in STD_LOGIC_VECTOR (47 downto 0);
ram_address : out STD_LOGIC_VECTOR ( 8 downto 0);
display_rgb1 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_rgb2 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_addr : out STD_LOGIC_VECTOR ( 3 downto 0);
display_clk : out STD_LOGIC;
display_oe : out STD_LOGIC;
display_lat : out STD_LOGIC);
end component;
component animationV
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
height : in STD_LOGIC_VECTOR ( 3 downto 0);
ram_address : in STD_LOGIC_VECTOR ( 8 downto 0);
ram_data : out STD_LOGIC_VECTOR (47 downto 0);
mode : in STD_LOGIC;
on_off : in STD_LOGIC);
end component;
--signal sysclk : std_logic;
--signal uart_clk : std_logic;
--signal pll_locked : std_logic;
signal rst : std_logic;
signal rgb_addr : std_logic_vector(8 downto 0);
signal rgb_data : std_logic_vector(47 downto 0);
signal rgb_frame : std_logic;
--signal uart_active : std_logic;
signal uart_data : std_logic_vector(47 downto 0);
signal anim_data : std_logic_vector(47 downto 0);
signal gnd0 : std_logic := '0';
signal vcc0 : std_logic := '1';
--signal height : std_logic_vector(3 downto 0) := "0011";
begin
--led <= pll_locked and rgb_frame;
rst <= not pll_locked;
bluetooth_rxd <= '1';
usb_rxd <= '1';
--pll_inst : pll
-- port map
-- (-- Clock in ports
-- CLK_IN => clk,
-- -- Clock out ports
-- CLK_OUT1 => sysclk,
-- CLK_OUT2 => uart_clk,
-- -- Status and control signals
-- RESET => gnd0,
-- LOCKED => pll_locked);
rx_i : uart_rx
generic map (
log2_oversampling => 7)
port map (
RST => rst,
RDCLK => sysclk,
CLKOSX => uartclk,
--RXD => bluetooth_txd,
RXD => usb_txd,
RDADDR => rgb_addr,
RDDATA => uart_data,
FRAMESEL => rgb_frame);
disp_i : display_control
port map (
clk => sysclk,
rst => rst,
display_ena => vcc0,
ram_data => rgb_data,
ram_address => rgb_addr,
display_rgb1 => display_rgb1,
display_rgb2 => display_rgb2,
display_addr => display_addr,
display_clk => display_clk,
display_oe => display_oe,
display_lat => display_lat);
anim_i : animationV
port map (
clk => sysclk,
rst => rst,
height => height,
ram_address => rgb_addr,
ram_data => anim_data,
mode => mode,
on_off => on_off);
rgb_data <= uart_data when (uart_active = '1') else anim_data;
--rgb_data <= anim_data;
uart_proc : process (rst, sysclk)
begin
if rst = '1' then
--uart_active <= '1';
elsif rising_edge(sysclk) then
if rgb_frame = '0' then
--uart_active <= '1';
end if;
end if;
end process uart_proc;
end rtl;
|
mit
|
15c9e4e017b8a1b2a175ef292e9418f6
| 0.539312 | 3.18188 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd
| 1 | 7,277 |
------------------------------------------------------------------------------
-- Title : Wishbone Ethernet MAC Wrapper
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-26-08
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone Wrapper for RS232 Master
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-26-08 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
entity wb_rs232_syscon is
generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rstn_i : in std_logic;
-- External ports
rs232_rxd_i : in std_logic;
rs232_txd_o : out std_logic;
-- Reset to FPGA logic
rstn_o : out std_logic;
-- WISHBONE master
m_wb_adr_o : out std_logic_vector(31 downto 0);
m_wb_sel_o : out std_logic_vector(3 downto 0);
m_wb_we_o : out std_logic;
m_wb_dat_o : out std_logic_vector(31 downto 0);
m_wb_dat_i : in std_logic_vector(31 downto 0);
m_wb_cyc_o : out std_logic;
m_wb_stb_o : out std_logic;
m_wb_ack_i : in std_logic;
m_wb_err_i : in std_logic;
m_wb_stall_i : in std_logic;
m_wb_rty_i : in std_logic
);
end wb_rs232_syscon;
architecture rtl of wb_rs232_syscon is
signal rst : std_logic;
signal rst_out : std_logic;
signal m_wb_adr_out : std_logic_vector(31 downto 0);
signal m_wb_sel_out : std_logic_vector(3 downto 0);
signal m_wb_we_out : std_logic;
signal m_wb_dat_out : std_logic_vector(31 downto 0);
signal m_wb_dat_in : std_logic_vector(31 downto 0);
signal m_wb_cyc_out : std_logic;
signal m_wb_stb_out : std_logic;
signal m_wb_ack_in : std_logic;
signal m_wb_err_in : std_logic;
signal m_wb_stall_in : std_logic;
signal m_wb_rty_in : std_logic;
component rs232_syscon_top_1_0
port (
clk_i : in std_logic;
reset_i : in std_logic;
ack_i : in std_logic;
err_i : in std_logic;
rs232_rxd_i : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rst_o : out std_logic;
stb_o : out std_logic;
cyc_o : out std_logic;
adr_o : out std_logic_vector(31 downto 0);
we_o : out std_logic;
rs232_txd_o : out std_logic;
sel_o : out std_logic_vector(3 downto 0)
);
end component;
begin
rst <= not wb_rstn_i;
-- ETHMAC master interface is byte addressed, classic wishbone
cmp_ma_iface_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => false,
g_master_mode => g_ma_interface_mode,
g_master_granularity => g_ma_address_granularity,
g_slave_use_struct => false,
g_slave_mode => CLASSIC,
g_slave_granularity => BYTE
)
port map (
clk_sys_i => wb_clk_i,
rst_n_i => wb_rstn_i,
sl_adr_i => m_wb_adr_out,
sl_dat_i => m_wb_dat_out,
sl_sel_i => m_wb_sel_out,
sl_cyc_i => m_wb_cyc_out,
sl_stb_i => m_wb_stb_out,
sl_we_i => m_wb_we_out,
sl_dat_o => m_wb_dat_in,
sl_ack_o => m_wb_ack_in,
sl_stall_o => open,
sl_int_o => open,
sl_rty_o => open,
sl_err_o => m_wb_err_in,
ma_adr_o => m_wb_adr_o,
ma_dat_o => m_wb_dat_o,
ma_sel_o => m_wb_sel_o,
ma_cyc_o => m_wb_cyc_o,
ma_stb_o => m_wb_stb_o,
ma_we_o => m_wb_we_o,
ma_dat_i => m_wb_dat_i,
ma_ack_i => m_wb_ack_i,
ma_stall_i => m_wb_stall_i,
ma_rty_i => m_wb_rty_i,
ma_err_i => m_wb_err_i
);
cmp_rs232_syscon_top_1_0 : rs232_syscon_top_1_0
port map (
clk_i => wb_clk_i,
reset_i => rst,
ack_i => m_wb_ack_in,
err_i => m_wb_err_in,
rs232_rxd_i => rs232_rxd_i,
data_in => m_wb_dat_in,
data_out => m_wb_dat_out,
rst_o => rst_out,
stb_o => m_wb_stb_out,
cyc_o => m_wb_cyc_out,
adr_o => m_wb_adr_out,
we_o => m_wb_we_out,
rs232_txd_o => rs232_txd_o,
sel_o => m_wb_sel_out
);
rstn_o <= not rst_out;
end rtl;
|
lgpl-3.0
|
c398a2473fc1a9c2dab0bbefaeb3cde0
| 0.337089 | 4.360096 | false | false | false | false |
freecores/camellia-vhdl
|
looping/fl.vhd
| 1 | 2,587 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 01/22/2008
-- Last Update: 02/21/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous FL and FL^-1 functions
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity FL is
port(
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
fl_k : in STD_LOGIC_VECTOR (0 to 63);
fli_k : in STD_LOGIC_VECTOR (0 to 63);
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end FL;
architecture RTL of FL is
signal fl_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b2 : STD_LOGIC_VECTOR (0 to 31);
begin
--FL function
fl_a1 <= fl_in(0 to 31) and fl_k(0 to 31);
fl_a2 <= (fl_a1(1 to 31) & fl_a1(0)) xor fl_in(32 to 63);
fl_b1 <= fl_a2 or fl_k(32 to 63);
fl_b2 <= fl_in(0 to 31) xor fl_b1;
fl_out <= fl_b2 & fl_a2;
--FL^-1 function
fli_a1 <= fli_in(32 to 63) or fli_k(32 to 63);
fli_a2 <= fli_in(0 to 31) xor fli_a1;
fli_b1 <= fli_a2 and fli_k(0 to 31);
fli_b2 <= (fli_b1(1 to 31) & fli_b1(0)) xor fli_in(32 to 63);
fli_out <= fli_a2 & fli_b2;
end RTL;
|
gpl-3.0
|
39031a0a1273a24f415cd08801132077
| 0.590646 | 3.254088 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/video/vdp18/vdp18_ctrl.vhd
| 2 | 11,567 |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_ctrl.vhd,v 1.26 2006/06/18 10:47:01 arnim Exp $
--
-- Timing Controller
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vdp18_pack.opmode_t;
use work.vdp18_pack.hv_t;
use work.vdp18_pack.access_t;
entity vdp18_ctrl is
port (
clock_i : in std_logic;
clk_en_5m37_i : in boolean;
reset_i : in boolean;
opmode_i : in opmode_t;
vram_read_i : in boolean;
vram_write_i : in boolean;
vram_ce_o : out std_logic;
vram_oe_o : out std_logic;
num_pix_i : in hv_t;
num_line_i : in hv_t;
vert_inc_i : in boolean;
reg_blank_i : in boolean;
reg_size1_i : in boolean;
stop_sprite_i : in boolean;
clk_en_acc_o : out boolean;
access_type_o : out access_t;
vert_active_o : out boolean;
hor_active_o : out boolean;
irq_o : out boolean
);
end vdp18_ctrl;
use work.vdp18_pack.all;
architecture rtl of vdp18_ctrl is
-----------------------------------------------------------------------------
-- This enables a workaround for a bug in XST.
-- ISE 8.1.02i implements wrong functionality otherwise :-(
--
constant xst_bug_wa_c : boolean := true;
--
-----------------------------------------------------------------------------
signal access_type_s : access_t;
-- pragma translate_off
-- Testbench signals --------------------------------------------------------
--
signal ac_s : std_logic_vector(3 downto 0);
--
-----------------------------------------------------------------------------
-- pragma translate_on
signal vert_active_q,
hor_active_q : boolean;
signal sprite_active_q : boolean;
signal sprite_line_act_q : boolean;
begin
-- pragma translate_off
-- Testbench signals --------------------------------------------------------
--
ac_s <= enum_to_vec_f(access_type_s);
--
-----------------------------------------------------------------------------
-- pragma translate_on
-----------------------------------------------------------------------------
-- Process decode_access
--
-- Purpose:
-- Decode horizontal counter value to access type.
--
decode_access: process (opmode_i,num_pix_i,vert_active_q,sprite_line_act_q,reg_size1_i)
variable num_pix_plus_6_v : hv_t;
variable mod_6_v : hv_t;
variable num_pix_plus_8_v : hv_t;
variable num_pix_plus_32_v : hv_t;
variable num_pix_spr_v : integer;
begin
-- default assignment
access_type_s <= AC_CPU;
-- prepare number of pixels for pattern operations
num_pix_plus_6_v := num_pix_i + 6;
num_pix_plus_8_v := num_pix_i + 8;
num_pix_plus_32_v := num_pix_i + 32;
num_pix_spr_v := to_integer(num_pix_i and "111111110");
case opmode_i is
-- Graphics I, II and Multicolor Mode -----------------------------------
when OPMODE_GRAPH1 |
OPMODE_GRAPH2 |
OPMODE_MULTIC =>
--
-- Patterns
--
if vert_active_q then
if num_pix_plus_8_v(0) = '0' then
if not xst_bug_wa_c then
-- original code, we want this
case num_pix_plus_8_v(6 to 7) is
when "01" =>
access_type_s <= AC_PNT;
when "10" =>
if opmode_i /= OPMODE_MULTIC then
-- no access to pattern color table in multicolor mode
access_type_s <= AC_PCT;
end if;
when "11" =>
access_type_s <= AC_PGT;
when others =>
null;
end case;
else
-- workaround for XST bug, we need this
if num_pix_plus_8_v(6 to 7) = "01" then
access_type_s <= AC_PNT;
elsif num_pix_plus_8_v(6 to 7) = "10" then
if opmode_i /= OPMODE_MULTIC then
access_type_s <= AC_PCT;
end if;
elsif num_pix_plus_8_v(6 to 7) = "11" then
access_type_s <= AC_PGT;
end if;
end if;
end if;
end if;
--
-- Sprite test
--
if sprite_line_act_q then
if num_pix_i(0) = '0' and
num_pix_i(0 to 5) /= "011111" and
num_pix_i(6 to 7) = "00" and
num_pix_i(4 to 5) /= "00" then
-- sprite test interleaved with pattern accesses
access_type_s <= AC_STST;
end if;
if (num_pix_plus_32_v(0 to 4) = "00000" or
num_pix_plus_32_v(0 to 5) = "000010") and
num_pix_plus_32_v(6 to 7) /= "00" then
-- sprite tests before starting pattern phase
access_type_s <= AC_STST;
end if;
--
-- Sprite Attribute Table and Sprite Pattern Table
--
case num_pix_spr_v is
when 250 | -78 |
-62 | -46 =>
access_type_s <= AC_SATY;
when 254 | -76 |
-60 | -44 =>
access_type_s <= AC_SATX;
when 252 | -74 |
-58 | -42 =>
access_type_s <= AC_SATN;
when -86 | -70 |
-54 | -38 =>
access_type_s <= AC_SATC;
when -84 | -68 |
-52 | -36 =>
access_type_s <= AC_SPTH;
when -82 | -66 |
-50 | -34 =>
if reg_size1_i then
access_type_s <= AC_SPTL;
end if;
when others =>
null;
end case;
end if;
-- Text Mode ------------------------------------------------------------
when OPMODE_TEXTM =>
if vert_active_q and
num_pix_plus_6_v(0) = '0' and
num_pix_plus_6_v(0 to 4) /= "01111" then
--
mod_6_v := mod_6_f(num_pix_plus_6_v);
case mod_6_v(6 to 7) is
when "00" =>
access_type_s <= AC_PNT;
when "10" =>
access_type_s <= AC_PGT;
when others =>
null;
end case;
end if;
-- Unknown --------------------------------------------------------------
when others =>
null;
end case;
end process decode_access;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process vert_flags
--
-- Purpose:
-- Track the vertical position with flags.
--
vert_flags: process (clock_i, reset_i)
begin
if reset_i then
vert_active_q <= false;
sprite_active_q <= false;
sprite_line_act_q <= false;
elsif clock_i'event and clock_i = '1' then
if clk_en_5m37_i then
-- line-local sprite processing
if sprite_active_q then
-- sprites are globally enabled
if vert_inc_i then
-- reload at beginning of every new line
-- => scan with STST
sprite_line_act_q <= true;
end if;
if num_pix_i = hv_sprite_start_c then
-- reload when access to sprite memory starts
sprite_line_act_q <= true;
end if;
end if;
if vert_inc_i then
-- global sprite processing
if reg_blank_i then
sprite_active_q <= false;
sprite_line_act_q <= false;
elsif num_line_i = -2 then
-- start at line -1
sprite_active_q <= true;
-- initialize immediately
sprite_line_act_q <= true;
elsif num_line_i = 191 then
-- stop at line 192
sprite_active_q <= false;
-- force stop
sprite_line_act_q <= false;
end if;
-- global vertical display
if reg_blank_i then
vert_active_q <= false;
elsif num_line_i = -1 then
-- start vertical display at line 0
vert_active_q <= true;
elsif num_line_i = 191 then
-- stop at line 192
vert_active_q <= false;
end if;
end if;
if stop_sprite_i then
-- stop processing of sprites in this line
sprite_line_act_q <= false;
end if;
end if;
end if;
end process vert_flags;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process hor_flags
--
-- Purpose:
-- Track the horizontal position.
--
hor_flags: process (clock_i, reset_i)
begin
if reset_i then
hor_active_q <= false;
elsif clock_i'event and clock_i = '1' then
if clk_en_5m37_i then
if not reg_blank_i and num_pix_i = -1 then
hor_active_q <= true;
end if;
if opmode_i = OPMODE_TEXTM then
if num_pix_i = 239 then
hor_active_q <= false;
end if;
else
if num_pix_i = 255 then
hor_active_q <= false;
end if;
end if;
end if;
end if;
end process hor_flags;
--
-----------------------------------------------------------------------------
vram_ctrl: process (clock_i)
variable read_b_v : boolean;
begin
if rising_edge(clock_i) then
if clk_en_5m37_i then
vram_ce_o <= '0';
vram_oe_o <= '0';
if access_type_s = AC_CPU then
if vram_read_i and not read_b_v then
vram_ce_o <= '1';
vram_oe_o <= '1';
read_b_v := true;
elsif vram_write_i and not read_b_v then
vram_ce_o <= '1';
--
read_b_v := true;
else
read_b_v := false;
end if;
else
if not read_b_v then
vram_ce_o <= '1';
vram_oe_o <= '1';
read_b_v := true;
else
read_b_v := false;
end if;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Ouput mapping
-----------------------------------------------------------------------------
-- generate clock enable for flip-flops working on access_type
clk_en_acc_o <= clk_en_5m37_i and num_pix_i(8) = '1';
access_type_o <= access_type_s;
vert_active_o <= vert_active_q;
hor_active_o <= hor_active_q;
irq_o <= vert_inc_i and num_line_i = 191;
end rtl;
|
gpl-3.0
|
e51d1a5944e46ee5f9c6cb52eea8ab45
| 0.517074 | 3.306747 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/tx_Transact.vhd
| 1 | 51,067 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: tx_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.30 - Memory buffer applied and structure regulated for DPR. 25.03.2008
--
-- Revision 1.20 - Literal assignments rewritten. 02.08.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.06 - BRAM output and FIFO output both registered. 01.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity tx_Transact is
port (
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction
s_axis_tx_tlast : out std_logic;
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
s_axis_tx_tvalid : out std_logic;
s_axis_tx_tready : in std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : out std_logic;
us_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Read interface for Tx port
Regs_RdAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Irpt Channel
Irpt_Req : in std_logic;
Irpt_RE : out std_logic;
Irpt_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- PIO MRd Channel
pioCplD_Req : in std_logic;
pioCplD_RE : out std_logic;
pioCplD_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- downstream MRd Channel
dsMRd_Req : in std_logic;
dsMRd_RE : out std_logic;
dsMRd_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- upstream MWr/MRd Channel
usTlp_Req : in std_logic;
usTlp_RE : out std_logic;
usTlp_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : out std_logic;
us_Last_sof : out std_logic;
us_Last_eof : out std_logic;
-- Message routing method
Msg_Routing : in std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
-- DDR read port
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
Tx_TimeOut : out std_logic;
Tx_wb_TimeOut : out std_logic;
Tx_Reset : in std_logic;
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end tx_Transact;
architecture Behavioral of tx_Transact is
type TxTrnStates is (St_TxIdle, -- Idle
St_d_CmdReq, -- Issue the read command to MemReader
St_d_CmdAck, -- Wait for the read command ACK from MemReader
St_d_Header0, -- 1st Header for TLP with payload
St_d_Header2, -- 2nd Header for TLP with payload
-- St_d_HeaderPlus, -- Extra Header for TLP4 with payload
St_d_1st_Data, -- Last Header for TLP3/4 with payload
St_d_Payload, -- Data for TLP with payload
St_d_Payload_used, -- Data flow from memory buffer discontinued
St_d_Tail, -- Last data for TLP with payload
St_d_Tail_chk, -- Last data extended for TLP with payload
St_nd_Prepare, -- Prepare for 1st Header of TLP without payload
-- St_nd_Header1, -- 1st Header for TLP without payload
St_nd_Header2, -- 2nd Header for TLP without payload
-- St_nd_HeaderPlus, -- Extra Header for TLP4 without payload
St_nd_HeaderLast, -- Tail processing for the last dword of TLP w/o payload
St_nd_Arbitration -- One extra cycle for arbitration
);
-- State variables
signal TxTrn_State : TxTrnStates;
-- Signals with the arbitrator
signal take_an_Arbitration : std_logic;
signal Req_Bundle : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Read_a_Buffer : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Ack_Indice : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal b1_Tx_Indicator : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal vec_ChQout_Valid : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Tx_Busy : std_logic;
-- Channel buffer output token bits
signal usTLP_is_MWr : std_logic;
signal TLP_is_CplD : std_logic;
-- Bit information, telling whether the outgoing TLP has payload
signal ChBuf_has_Payload : std_logic;
signal ChBuf_No_Payload : std_logic;
-- Channel buffers output OR'ed and registered
signal Trn_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal Trn_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Addresses from different channel buffer
signal wbaddr_piocpld : std_logic_vector(C_WB_AWIDTH-1 downto 0);
signal mAddr_usTlp : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
signal DDRAddr_usTlp : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
signal WBAddr_usTlp : std_logic_vector(C_WB_AWIDTH-1 downto 0);
signal Regs_Addr_pioCplD : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal DDRAddr_pioCplD : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
-- BAR number
signal BAR_pioCplD : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
signal BAR_usTlp : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Misc. info.
signal AInc_usTlp : std_logic;
signal pioCplD_is_0Leng : std_logic;
-- Delay for requests from Channel Buffers
signal Irpt_Req_r1 : std_logic;
signal pioCplD_Req_r1 : std_logic;
signal dsMRd_Req_r1 : std_logic;
signal usTlp_Req_r1 : std_logic;
-- Registered channel buffer outputs
signal Irpt_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal dsMRd_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Req_Min_Leng : std_logic;
signal pioCplD_Req_2DW_Leng : std_logic;
signal usTlp_Req_Min_Leng : std_logic;
signal usTlp_Req_2DW_Leng : std_logic;
-- Channel buffer read enables
signal Irpt_RE_i : std_logic;
signal pioCplD_RE_i : std_logic;
signal dsMRd_RE_i : std_logic;
signal usTlp_RE_i : std_logic;
-- Flow controls
signal us_FC_stop_i : std_logic;
-- Local reset for tx
signal trn_tx_Reset_n : std_logic;
-- Alias for transaction interface signals
signal s_axis_tx_tdata_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal s_axis_tx_tkeep_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal s_axis_tx_tlast_i : std_logic;
signal s_axis_tx_tvalid_i : std_logic;
signal s_axis_tx_tdsc_i : std_logic;
signal s_axis_tx_terrfwd_i : std_logic;
signal s_axis_tx_tready_i : std_logic;
signal tx_buf_av_i : std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
signal trn_tsof_n_i : std_logic;
-- Upstream DMA transferred bytes count up
signal us_DMA_Bytes_Add_i : std_logic;
signal us_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
--------------------- Memory Reader -----------------------------
---
--- Memory reader is the interface to access all sorts of memories
--- BRAM, FIFO, Registers, as well as possible DDR SDRAM
---
-------------------------------------------------------------------
component
tx_Mem_Reader
port(
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One : in std_logic;
RdNumber_eq_Two : in std_logic;
StartAddr : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord : in std_logic;
is_CplD : in std_logic;
BAR_value : in std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req : in std_logic;
RdCmd_Ack : out std_logic;
mbuf_WE : out std_logic;
mbuf_Din : out std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
mbuf_Full : in std_logic;
mbuf_aFull : in std_logic;
Tx_TimeOut : out std_logic;
Tx_wb_TimeOut : out std_logic;
mReader_Rst_n : in std_logic;
user_clk : in std_logic
);
end component;
signal RdNumber : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal RdNumber_eq_One : std_logic;
signal RdNumber_eq_Two : std_logic;
signal StartAddr : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Shift_1st_QWord : std_logic;
signal is_CplD : std_logic;
signal BAR_value : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
signal RdCmd_Req : std_logic;
signal RdCmd_Ack : std_logic;
signal mbuf_reset_n : std_logic;
signal mbuf_WE : std_logic;
signal mbuf_Din : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_Full : std_logic;
signal mbuf_aFull : std_logic;
signal mbuf_RE : std_logic;
signal mbuf_Qout : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_Empty : std_logic;
-- Calculated infomation
signal mbuf_RE_ok : std_logic;
signal mbuf_Qvalid : std_logic;
--------------------- Output arbitration ------------------------
---
--- For sake of fairness, the priorities are cycled every time
--- a service is done, after which the priority of the request
--- just serviced is set to the lowest and other lower priorities
--- increased and higher stay.
---
-------------------------------------------------------------------
component
Tx_Output_Arbitor
port(
rst_n : in std_logic;
clk : in std_logic;
arbtake : in std_logic;
Req : in std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
bufread : out std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
Ack : out std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0)
);
end component;
begin
-- Connect outputs
s_axis_tx_tdata <= s_axis_tx_tdata_i;
s_axis_tx_tkeep <= s_axis_tx_tkeep_i;
s_axis_tx_tlast <= s_axis_tx_tlast_i;
s_axis_tx_tvalid <= s_axis_tx_tvalid_i;
s_axis_tx_tdsc <= s_axis_tx_tdsc_i;
s_axis_tx_terrfwd <= s_axis_tx_terrfwd_i;
us_Last_sof <= usTLP_is_MWr and not trn_tsof_n_i;
us_Last_eof <= usTLP_is_MWr and not s_axis_tx_tlast_i;
-- Connect inputs
s_axis_tx_tready_i <= s_axis_tx_tready;
tx_buf_av_i <= tx_buf_av;
-- Always deasserted
s_axis_tx_tdsc_i <= '0';
s_axis_tx_terrfwd_i <= '0';
-- Upstream DMA transferred bytes counting up
us_DMA_Bytes_Add <= us_DMA_Bytes_Add_i;
us_DMA_Bytes <= us_DMA_Bytes_i;
-- Flow controls
us_FC_stop <= us_FC_stop_i;
---------------------------------------------------------------------------------
-- Synchronous Calculation: us_FC_stop, pio_FC_stop
--
Synch_Calc_FC_stop :
process (user_clk, Tx_Reset)
begin
if Tx_Reset = '1' then
us_FC_stop_i <= '1';
elsif user_clk'event and user_clk = '1' then
if tx_buf_av_i(C_TBUF_AWIDTH-1 downto 1) /= C_ALL_ZEROS(C_TBUF_AWIDTH-1 downto 1) then
us_FC_stop_i <= '0';
else
us_FC_stop_i <= '1';
end if;
end if;
end process;
-- Channel buffer read enable
Irpt_RE <= Irpt_RE_i;
pioCplD_RE <= pioCplD_RE_i;
dsMRd_RE <= dsMRd_RE_i;
usTlp_RE <= usTlp_RE_i;
-- -----------------------------------
-- Synchronized Local reset
--
Syn_Local_Reset :
process (user_clk, user_reset)
begin
if user_reset = '1' then
trn_tx_Reset_n <= '0';
elsif user_clk'event and user_clk = '1' then
trn_tx_Reset_n <= not Tx_Reset;
end if;
end process;
------------------------------------------------------------
--- Memory reader
------------------------------------------------------------
ABB_Tx_MReader :
tx_Mem_Reader
port map(
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_sof => wb_rdc_sof, -- : out std_logic;
wb_rdc_v => wb_rdc_v, -- : out std_logic;
wb_rdc_din => wb_rdc_din, -- : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full => wb_rdc_full, --: in std_logic;
wb_FIFO_re => wb_FIFO_re , -- OUT std_logic;
wb_FIFO_empty => wb_FIFO_empty , -- IN std_logic;
wb_FIFO_qout => wb_FIFO_qout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr => Regs_RdAddr , -- OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout => Regs_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber => RdNumber , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber_eq_One => RdNumber_eq_One , -- IN std_logic;
RdNumber_eq_Two => RdNumber_eq_Two , -- IN std_logic;
StartAddr => StartAddr , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord => Shift_1st_QWord , -- IN std_logic;
is_CplD => is_CplD , -- IN std_logic;
BAR_value => BAR_value , -- IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req => RdCmd_Req , -- IN std_logic;
RdCmd_Ack => RdCmd_Ack , -- OUT std_logic;
mbuf_WE => mbuf_WE , -- OUT std_logic;
mbuf_Din => mbuf_Din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
mbuf_Full => mbuf_Full , -- IN std_logic;
mbuf_aFull => mbuf_aFull , -- IN std_logic;
Tx_TimeOut => Tx_TimeOut , -- OUT std_logic;
Tx_wb_TimeOut => Tx_wb_TimeOut , -- OUT std_logic;
mReader_Rst_n => trn_tx_Reset_n , -- IN std_logic;
user_clk => user_clk -- IN std_logic
);
--------------------- Memory Buffer -----------------------------
---
--- A unified memory buffer holding the payload for the next tx TLP
--- 34 bits wide, wherein 2 additional framing bits
--- temporarily 64 data depth, possibly deepened.
---
-------------------------------------------------------------------
ABB_Tx_MBuffer :
generic_sync_fifo
generic map (
g_data_width => 72,
g_size => 128,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => true,
g_with_count => false,
g_almost_full_threshold => 125)
port map(
rst_n_i => mbuf_reset_n,
clk_i => user_clk,
d_i => mbuf_din,
we_i => mbuf_we,
q_o => mbuf_qout,
rd_i => mbuf_re,
empty_o => mbuf_empty,
full_o => mbuf_full,
almost_empty_o => open,
almost_full_o => mbuf_afull,
count_o => open);
mbuf_RE <= mbuf_RE_ok and (s_axis_tx_tready_i or not s_axis_tx_tvalid_i);
---------------------------------------------------------------------------------
-- Synchronous Delay: mbuf_Qout Valid
--
Synchron_Delay_mbuf_Qvalid :
process (user_clk, Tx_Reset)
begin
if Tx_Reset = '1' then
mbuf_Qvalid <= '0';
elsif user_clk'event and user_clk = '1' then
if mbuf_Qvalid = '0' and mbuf_RE = '1' and mbuf_Empty = '0' then -- a valid data is going out
mbuf_Qvalid <= '1';
elsif mbuf_Qvalid = '1' and mbuf_RE = '1' and mbuf_Empty = '1' then -- an invalid data is going out
mbuf_Qvalid <= '0';
else -- state stays
mbuf_Qvalid <= mbuf_Qvalid;
end if;
end if;
end process;
------------------------------------------------------------
--- Output arbitration
------------------------------------------------------------
O_Arbitration :
Tx_Output_Arbitor
port map(
rst_n => trn_tx_Reset_n,
clk => user_clk,
arbtake => take_an_Arbitration,
Req => Req_Bundle,
bufread => Read_a_Buffer,
Ack => Ack_Indice
);
-----------------------------------------------------
-- Synchronous Delay: Channel Requests
--
Synchron_Delay_ChRequests :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Irpt_Req_r1 <= Irpt_Req;
pioCplD_Req_r1 <= pioCplD_Req;
dsMRd_Req_r1 <= dsMRd_Req;
usTlp_Req_r1 <= usTlp_Req;
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: Tx_Busy
--
Synchron_Delay_Tx_Busy :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Tx_Busy <= (b1_Tx_Indicator(C_CHAN_INDEX_IRPT) and vec_ChQout_Valid(C_CHAN_INDEX_IRPT))
or (b1_Tx_Indicator(C_CHAN_INDEX_MRD) and vec_ChQout_Valid(C_CHAN_INDEX_MRD))
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS))
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US));
end if;
end process;
-- ---------------------------------------------
-- Reg : Channel Buffer Qout has Payload
--
Reg_ChBuf_with_Payload :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
ChBuf_has_Payload <= (b1_Tx_Indicator(C_CHAN_INDEX_MRD) and TLP_is_CplD and vec_ChQout_Valid(C_CHAN_INDEX_MRD))
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and usTLP_is_MWr and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US));
end if;
end process;
-- ---------------------------------------------
-- Channel Buffer Qout has no Payload
-- (! subordinate to ChBuf_has_Payload ! )
--
ChBuf_No_Payload <= Tx_Busy;
-- Arbitrator inputs
Req_Bundle(C_CHAN_INDEX_IRPT) <= Irpt_Req_r1;
Req_Bundle(C_CHAN_INDEX_MRD) <= pioCplD_Req_r1;
Req_Bundle(C_CHAN_INDEX_DMA_DS) <= dsMRd_Req_r1;
Req_Bundle(C_CHAN_INDEX_DMA_US) <= usTlp_Req_r1;
-- Arbitrator outputs
b1_Tx_Indicator(C_CHAN_INDEX_IRPT) <= Ack_Indice(C_CHAN_INDEX_IRPT);
b1_Tx_Indicator(C_CHAN_INDEX_MRD) <= Ack_Indice(C_CHAN_INDEX_MRD);
b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) <= Ack_Indice(C_CHAN_INDEX_DMA_DS);
b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) <= Ack_Indice(C_CHAN_INDEX_DMA_US);
-- Arbitrator reads channel buffers
Irpt_RE_i <= Read_a_Buffer(C_CHAN_INDEX_IRPT);
pioCplD_RE_i <= Read_a_Buffer(C_CHAN_INDEX_MRD);
dsMRd_RE_i <= Read_a_Buffer(C_CHAN_INDEX_DMA_DS);
usTlp_RE_i <= Read_a_Buffer(C_CHAN_INDEX_DMA_US);
-- determine whether the upstream TLP is an MWr or an MRd.
usTLP_is_MWr <= usTlp_Qout (C_CHBUF_FMT_BIT_TOP);
TLP_is_CplD <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP);
-- check if the Channel buffer output is valid
vec_ChQout_Valid(C_CHAN_INDEX_IRPT) <= Irpt_Qout (C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_MRD) <= pioCplD_Qout(C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS) <= dsMRd_Qout (C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_DMA_US) <= usTlp_Qout (C_CHBUF_QVALID_BIT);
-- -----------------------------------
-- Delay : Channel_Buffer_Qout
-- Bit-mapping is done
--
Delay_Channel_Buffer_Qout :
process (user_clk, trn_tx_Reset_n)
begin
if trn_tx_Reset_n = '0' then
Irpt_Qout_to_TLP <= (others => '0');
pioCplD_Qout_to_TLP <= (others => '0');
dsMRd_Qout_to_TLP <= (others => '0');
usTlp_Qout_to_TLP <= (others => '0');
pioCplD_Req_Min_Leng <= '0';
pioCplD_Req_2DW_Leng <= '0';
usTlp_Req_Min_Leng <= '0';
usTlp_Req_2DW_Leng <= '0';
Regs_Addr_pioCplD <= (others => '1');
wbaddr_piocpld <= (others => '1');
mAddr_usTlp <= (others => '1');
AInc_usTlp <= '1';
BAR_pioCplD <= (others => '1');
BAR_usTlp <= (others => '1');
pioCplD_is_0Leng <= '0';
elsif user_clk'event and user_clk = '1' then
if b1_Tx_Indicator(C_CHAN_INDEX_IRPT) = '1' then
Irpt_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header Hi
Irpt_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= Irpt_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
-- Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_OF_MSG; --Irpt_Qout(C_CHBUF_MSGTYPE_BIT_TOP downto C_CHBUF_MSGTYPE_BIT_BOT);
Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_TOP
downto C_TLP_TYPE_BIT_BOT+1+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT)
& Msg_Routing;
Irpt_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= Irpt_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
Irpt_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= Irpt_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header Lo
Irpt_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
Irpt_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= Irpt_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
Irpt_Qout_to_TLP(C_MSG_CODE_BIT_TOP downto C_MSG_CODE_BIT_BOT) <= Irpt_Qout(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT);
-- 2nd headers all zero
-- ...
else
Irpt_Qout_to_TLP <= (others => '0');
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_MRD) = '1' then
pioCplD_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header Hi
pioCplD_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_COMPLETION; --pioCplD_Qout(C_CHBUF_TYPE_BIT_TOP downto C_CHBUF_TYPE_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= pioCplD_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= pioCplD_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header Lo
pioCplD_Qout_to_TLP(C_CPLD_CPLT_ID_BIT_TOP downto C_CPLD_CPLT_ID_BIT_BOT) <= localID;
pioCplD_Qout_to_TLP(C_CPLD_CS_BIT_TOP downto C_CPLD_CS_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT);
pioCplD_Qout_to_TLP(C_CPLD_BC_BIT_TOP downto C_CPLD_BC_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT);
-- 2nd header Hi
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_REQID_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_REQID_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT);
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_TAG_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_TAG_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_TAG_BIT_TOP downto C_CHBUF_CPLD_TAG_BIT_BOT);
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_LA_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_LA_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT);
-- no 2nd header Lo
if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
then
pioCplD_Req_Min_Leng <= '1';
else
pioCplD_Req_Min_Leng <= '0';
end if;
if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
then
pioCplD_Req_2DW_Leng <= '1';
else
pioCplD_Req_2DW_Leng <= '0';
end if;
-- Misc
Regs_Addr_pioCplD <= pioCplD_Qout(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
wbaddr_piocpld <= pioCplD_Qout(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT);
DDRAddr_pioCplD <= pioCplD_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
BAR_pioCplD <= pioCplD_Qout(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT);
pioCplD_is_0Leng <= pioCplD_Qout(C_CHBUF_0LENG_BIT);
else
pioCplD_Req_Min_Leng <= '0';
pioCplD_Req_2DW_Leng <= '0';
pioCplD_Qout_to_TLP <= (others => '0');
Regs_Addr_pioCplD <= (others => '1');
wbaddr_piocpld <= (others => '1');
DDRAddr_pioCplD <= (others => '1');
BAR_pioCplD <= (others => '1');
pioCplD_is_0Leng <= '0';
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) = '1' then
usTlp_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header HI
usTlp_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= usTlp_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= usTlp_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= usTlp_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header LO
usTlp_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
usTlp_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= usTlp_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT);
-- 2nd header HI (Address)
-- usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
if usTlp_Qout(C_CHBUF_FMT_BIT_BOT) = '1' then -- 4DW MWr
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT+32);
else
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
end if;
-- 2nd header LO (Address)
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1-32 downto C_DBUS_WIDTH) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
--
if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
then
usTlp_Req_Min_Leng <= '1';
else
usTlp_Req_Min_Leng <= '0';
end if;
if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
then
usTlp_Req_2DW_Leng <= '1';
else
usTlp_Req_2DW_Leng <= '0';
end if;
-- Misc
DDRAddr_usTlp <= usTlp_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
WBAddr_usTlp <= usTlp_Qout(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT);
mAddr_usTlp <= usTlp_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- !! C_CHBUF_MA_BIT_BOT);
AInc_usTlp <= usTlp_Qout(C_CHBUF_AINC_BIT);
BAR_usTlp <= usTlp_Qout(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT);
else
usTlp_Req_Min_Leng <= '0';
usTlp_Req_2DW_Leng <= '0';
usTlp_Qout_to_TLP <= (others => '0');
DDRAddr_usTlp <= (others => '1');
WBAddr_usTlp <= (others => '1');
mAddr_usTlp <= (others => '1');
AInc_usTlp <= '1';
BAR_usTlp <= (others => '1');
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) = '1' then
dsMRd_Qout_to_TLP <= (others => '0'); -- must be 1st argument
-- 1st header HI
dsMRd_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= dsMRd_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= dsMRd_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= dsMRd_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= dsMRd_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header LO
dsMRd_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
dsMRd_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= dsMRd_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT);
-- 2nd header (Address)
dsMRd_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH) <= dsMRd_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
else
dsMRd_Qout_to_TLP <= (others => '0');
end if;
end if;
end process;
-- OR-wired channel buffer outputs
Trn_Qout_wire <= Irpt_Qout_to_TLP
or pioCplD_Qout_to_TLP
or dsMRd_Qout_to_TLP
or usTlp_Qout_to_TLP;
-- ---------------------------------------------------
-- State Machine: Tx output control
--
TxFSM_OutputControl :
process (user_clk, trn_tx_Reset_n)
begin
if trn_tx_Reset_n = '0' then
take_an_Arbitration <= '0';
RdNumber <= (others => '0');
RdNumber_eq_One <= '0';
RdNumber_eq_Two <= '0';
StartAddr <= (others => '0');
Shift_1st_QWord <= '0';
is_CplD <= '0';
BAR_value <= (others => '0');
RdCmd_Req <= '0';
mbuf_reset_n <= '0';
mbuf_RE_ok <= '0';
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_TxIdle;
Trn_Qout_reg <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case TxTrn_State is
when St_TxIdle =>
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
mbuf_RE_ok <= '0';
take_an_Arbitration <= '0';
--ported from TRN to AXI, swap DWORDs
Trn_Qout_reg <= Trn_Qout_wire;
RdNumber <= Trn_Qout_wire (C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One <= pioCplD_Req_Min_Leng or usTlp_Req_Min_Leng;
RdNumber_eq_Two <= pioCplD_Req_2DW_Leng or usTlp_Req_2DW_Leng;
-- BAR_value <= BAR_pioCplD and BAR_usTlp;
RdCmd_Req <= ChBuf_has_Payload;
if pioCplD_is_0Leng = '1' then
BAR_value <= '0' & CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1);
StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord <= '1';
is_CplD <= '0';
elsif BAR_pioCplD = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_pioCplD);
Shift_1st_QWord <= '1';
is_CplD <= '1';
elsif BAR_pioCplD = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= BAR_pioCplD(C_ENCODE_BAR_NUMBER-1 downto 0);
StartAddr <= (C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_WB_AWIDTH) & wbaddr_piocpld);
Shift_1st_QWord <= '1';
is_CplD <= '1';
-- elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
-- BAR_value <= '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
-- StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+4) & mAddr_usTlp & "00";
elsif BAR_usTlp = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
Shift_1st_QWord <= not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
is_CplD <= '0';
elsif BAR_usTlp = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= BAR_usTlp(C_ENCODE_BAR_NUMBER-1 downto 0);
StartAddr <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_WB_AWIDTH) & WBAddr_usTlp;
Shift_1st_QWord <= not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
is_CplD <= '0';
else
BAR_value <= '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= (C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_EP_AWIDTH) & Regs_Addr_pioCplD);
-- and (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+2) & mAddr_usTlp);
Shift_1st_QWord <= '1';
is_CplD <= '0';
end if;
if ChBuf_has_Payload = '1' then
TxTrn_State <= St_d_CmdReq;
mbuf_reset_n <= '1';
elsif ChBuf_No_Payload = '1' then
TxTrn_State <= St_nd_Prepare;
mbuf_reset_n <= '1';
else
TxTrn_State <= St_TxIdle;
mbuf_reset_n <= mbuf_Empty; -- '1';
end if;
--- --- --- --- --- --- --- --- --- --- --- --- ---
--- --- --- --- --- --- --- --- --- --- --- --- ---
when St_nd_Prepare =>
s_axis_tx_tlast_i <= '0';
if s_axis_tx_tready_i = '1' then
TxTrn_State <= St_nd_Header2; -- St_nd_Header1
s_axis_tx_tvalid_i <= '1';
trn_tsof_n_i <= '0';
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
else
TxTrn_State <= St_nd_Prepare;
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tdata_i <= (others => '0');
end if;
when St_nd_Header2 =>
s_axis_tx_tvalid_i <= '1';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_nd_Header2;
take_an_Arbitration <= '0';
trn_tsof_n_i <= trn_tsof_n_i;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i; -- Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
else -- 3DW header
TxTrn_State <= St_nd_HeaderLast;
take_an_Arbitration <= '1';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '1';
if Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then -- 4DW header
s_axis_tx_tkeep_i <= X"FF";
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
else
s_axis_tx_tkeep_i <= X"0F";
s_axis_tx_tdata_i <= X"00000000" & Trn_Qout_reg (C_DBUS_WIDTH-1+32 downto C_DBUS_WIDTH);
end if;
end if;
when St_nd_HeaderLast =>
trn_tsof_n_i <= '1';
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_nd_HeaderLast;
s_axis_tx_tvalid_i <= '1';
s_axis_tx_tlast_i <= '1';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
else
TxTrn_State <= St_nd_Arbitration; -- St_TxIdle;
s_axis_tx_tvalid_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
end if;
when St_nd_Arbitration =>
trn_tsof_n_i <= '1';
TxTrn_State <= St_TxIdle;
s_axis_tx_tvalid_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tkeep_i <= (others => '1');
--- --- --- --- --- --- --- --- --- --- --- --- ---
--- --- --- --- --- --- --- --- --- --- --- --- ---
when St_d_CmdReq =>
if RdCmd_Ack = '1' then
RdCmd_Req <= '0';
TxTrn_State <= St_d_CmdAck;
else
RdCmd_Req <= '1';
TxTrn_State <= St_d_CmdReq;
end if;
when St_d_CmdAck =>
s_axis_tx_tlast_i <= '0';
if mbuf_Empty = '0' and s_axis_tx_tready_i = '1' then
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tdata_i <= (others => '0');
mbuf_RE_ok <= '1';
TxTrn_State <= St_d_Header0; -- St_d_Header1
else
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tdata_i <= (others => '0');
mbuf_RE_ok <= '0';
TxTrn_State <= St_d_CmdAck;
end if;
when St_d_Header0 =>
if s_axis_tx_tready_i = '1' then
take_an_Arbitration <= '1';
s_axis_tx_tvalid_i <= '1';
trn_tsof_n_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
mbuf_RE_ok <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT); -- '1'; -- 4DW
TxTrn_State <= St_d_Header2;
else
take_an_Arbitration <= '0';
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
mbuf_RE_ok <= '0';
TxTrn_State <= St_d_Header0;
end if;
when St_d_Header2 =>
s_axis_tx_tvalid_i <= '1';
s_axis_tx_tkeep_i <= (others => '1');
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_d_Header2;
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
trn_tsof_n_i <= '0';
s_axis_tx_tlast_i <= '0';
mbuf_RE_ok <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT);
elsif Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then -- 4DW header
TxTrn_State <= St_d_1st_Data; -- St_d_HeaderPlus;
s_axis_tx_tdata_i <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
mbuf_RE_ok <= '1';
else -- 3DW header
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 32)
& Trn_Qout_reg (C_DBUS_WIDTH+32-1 downto C_DBUS_WIDTH);
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= not(mbuf_Qout(C_DBUS_WIDTH));
mbuf_RE_ok <= s_axis_tx_tvalid_i and mbuf_Qout(C_DBUS_WIDTH);
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
else
TxTrn_State <= St_d_1st_Data;
end if;
end if;
when St_d_1st_Data =>
mbuf_RE_ok <= s_axis_tx_tvalid_i and mbuf_Qout(C_DBUS_WIDTH);
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_d_1st_Data;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tvalid_i <= '1';
elsif mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= mbuf_Qvalid; -- '0';
elsif mbuf_Qvalid = '0' then
TxTrn_State <= St_d_Payload_used;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= '0';
else
TxTrn_State <= St_d_Payload;
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= '1';
end if;
when St_d_Payload =>
mbuf_RE_ok <= '1';
take_an_Arbitration <= '0';
if s_axis_tx_tready_i = '0' then
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tlast_i <= s_axis_tx_tlast_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tvalid_i <= '1';
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail;
elsif mbuf_Qvalid = '1' then
TxTrn_State <= St_d_Payload;
else
TxTrn_State <= St_d_Payload_used;
end if;
else
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tlast_i <= not(mbuf_Qout(C_DBUS_WIDTH));
s_axis_tx_tvalid_i <= not(mbuf_Qout(C_DBUS_WIDTH)) or mbuf_Qvalid;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
elsif mbuf_Qvalid = '1' then
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_d_Payload;
else
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_d_Payload_used;
end if;
end if;
when St_d_Payload_used =>
mbuf_RE_ok <= '1';
take_an_Arbitration <= '0';
if s_axis_tx_tvalid_i = '1' then
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= mbuf_Qvalid and s_axis_tx_tready_i;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
else
s_axis_tx_tlast_i <= '0';
s_axis_tx_tkeep_i <= (others => '1');
end if;
if mbuf_Qvalid = '1' then
TxTrn_State <= St_d_Payload;
else
TxTrn_State <= St_d_Payload_used;
end if;
elsif mbuf_Qvalid = '1' then
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tvalid_i <= '1';
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
else
s_axis_tx_tlast_i <= '0';
s_axis_tx_tkeep_i <= (others => '1');
end if;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
else
TxTrn_State <= St_d_Payload;
end if;
else
TxTrn_State <= St_d_Payload_used;
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
s_axis_tx_tlast_i <= s_axis_tx_tlast_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tvalid_i <= '0';
end if;
when St_d_Tail =>
take_an_Arbitration <= '0';
mbuf_RE_ok <= '0';
s_axis_tx_tvalid_i <= '1';
if s_axis_tx_tready_i = '0' then
TxTrn_State <= St_d_Tail;
s_axis_tx_tlast_i <= s_axis_tx_tlast_i;
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
else
TxTrn_State <= St_d_Tail_chk;
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
s_axis_tx_tdata_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
end if;
when St_d_Tail_chk =>
take_an_Arbitration <= '0';
mbuf_RE_ok <= '0';
if s_axis_tx_tready_i = '0' then
s_axis_tx_tvalid_i <= '1';
s_axis_tx_tlast_i <= '1';
s_axis_tx_tkeep_i <= s_axis_tx_tkeep_i;
s_axis_tx_tdata_i <= s_axis_tx_tdata_i;
TxTrn_State <= St_d_Tail_chk;
else
s_axis_tx_tvalid_i <= '0';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_TxIdle;
end if;
when others =>
take_an_Arbitration <= '0';
RdNumber <= (others => '0');
RdNumber_eq_One <= '0';
RdNumber_eq_Two <= '0';
StartAddr <= (others => '0');
BAR_value <= (others => '0');
RdCmd_Req <= '0';
mbuf_reset_n <= '1';
mbuf_RE_ok <= '0';
s_axis_tx_tvalid_i <= '0';
trn_tsof_n_i <= '1';
s_axis_tx_tlast_i <= '0';
s_axis_tx_tdata_i <= (others => '0');
s_axis_tx_tkeep_i <= (others => '1');
TxTrn_State <= St_TxIdle;
end case;
end if;
end process;
---------------------------------------------------------------------------------
-- Synchronous Accumulation: us_DMA_Bytes
--
Synch_Acc_us_DMA_Bytes :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
us_DMA_Bytes_i <= '0' & s_axis_tx_tdata_i(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) & "00";
if s_axis_tx_tdata_i(C_TLP_FMT_BIT_TOP) = '1'
and s_axis_tx_tdata_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) then
us_DMA_Bytes_Add_i <= not trn_tsof_n_i
and s_axis_tx_tvalid_i
and s_axis_tx_tready_i;
else
us_DMA_Bytes_Add_i <= '0';
end if;
end if;
end process;
end architecture Behavioral;
|
lgpl-3.0
|
809dc90d57bc862988bdd7e2a0943ebe
| 0.523019 | 3.131216 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_read.vhd
| 1 | 17,151 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_read.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Top-level module for PHY-layer read logic
-- 1. Read clock (capture, resync) generation
-- 2. Synchronization of control from MC into resync clock domain
-- 3. Synchronization of data/valid into MC clock domain
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_read.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_read.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_read is
generic (
TCQ : integer := 100;
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3333; -- Internal clock period (in ps)
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
IODELAY_GRP : string := "IODELAY_MIG"; -- May be assigned unique name
-- when mult IP cores in design
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 0; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 0; -- # DQS groups in I/O column #4
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"11100F0E0D0C0B0A09080706050403020100";
-- DQS grps in col #1
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #2
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #3
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000"
);
port (
clk_mem : in std_logic;
clk : in std_logic;
rst : in std_logic;
clk_rd_base : in std_logic;
-- Read clock generation/distribution signals
dlyrst_cpt : in std_logic;
dlyce_cpt : in std_logic_vector(DQS_WIDTH-1 downto 0);
dlyinc_cpt : in std_logic_vector(DQS_WIDTH-1 downto 0);
dlyrst_rsync : in std_logic;
dlyce_rsync : in std_logic_vector(3 downto 0);
dlyinc_rsync : in std_logic_vector(3 downto 0);
clk_cpt : out std_logic_vector(DQS_WIDTH-1 downto 0);
clk_rsync : out std_logic_vector(3 downto 0);
rst_rsync : out std_logic_vector(3 downto 0);
rdpath_rdy : out std_logic;
-- Control for command sync logic
mc_data_sel : in std_logic;
rd_active_dly : in std_logic_vector(4 downto 0);
-- Captured data in resync clock domain
rd_data_rise0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_rise1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_dqs_rise0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_rise1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
-- DFI signals from MC/PHY rdlvl logic
dfi_rddata_en : in std_logic;
phy_rddata_en : in std_logic;
-- Synchronized data/valid back to MC/PHY rdlvl logic
dfi_rddata_valid : out std_logic;
dfi_rddata_valid_phy : out std_logic;
dfi_rddata : out std_logic_vector((4*DQ_WIDTH-1) downto 0);
dfi_rd_dqs : out std_logic_vector((4*DQS_WIDTH-1) downto 0);
-- Debug bus
dbg_cpt_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0); -- CPT IODELAY tap count
dbg_rsync_tap_cnt : out std_logic_vector(19 downto 0); -- RSYNC IODELAY tap count
dbg_phy_read : out std_logic_vector(255 downto 0) -- general purpose debug
);
end phy_read;
architecture trans of phy_read is
-- Declare intermediate signals for referenced outputs
signal rst_rsync_xhdl0 : std_logic_vector(3 downto 0);
signal clk_rsync_xhdl1 : std_logic_vector(3 downto 0);
------- component phy_rdclk_gen ------
component phy_rdclk_gen
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3333; -- Internal clock period (in ps)
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
DQS_WIDTH : integer := 1; -- # of DQS (strobe),
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 0; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 0; -- # DQS groups in I/O column #4
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic; -- Memory clock
clk : in std_logic; -- Internal (logic) half-rate clock
clk_rd_base : in std_logic; -- Base capture clock
rst : in std_logic; -- Logic reset
dlyrst_cpt : in std_logic; -- Capture clock IDELAY shared reset
dlyce_cpt : in std_logic_vector(DQS_WIDTH - 1 downto 0); -- Capture clock IDELAY enable
dlyinc_cpt : in std_logic_vector(DQS_WIDTH - 1 downto 0); -- Capture clock IDELAY inc/dec
dlyrst_rsync : in std_logic; -- Resync clock IDELAY reset
dlyce_rsync : in std_logic_vector(3 downto 0); -- Resync clock IDELAY enable
dlyinc_rsync : in std_logic_vector(3 downto 0); -- Resync clock IDELAY inc/dec
clk_cpt : out std_logic_vector(DQS_WIDTH - 1 downto 0);-- Data capture clock
clk_rsync : out std_logic_vector(3 downto 0); -- Resynchronization clock
rst_rsync : out std_logic_vector(3 downto 0); -- Resync clock domain reset
-- debug control signals
dbg_cpt_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);-- CPT IODELAY tap count
dbg_rsync_tap_cnt : out std_logic_vector(19 downto 0) -- RSYNC IODELAY tap count
);
end component;
-------- component phy_rdctrl_sync --------
component phy_rdctrl_sync
generic (
TCQ : integer := 100
);
port (
clk : in std_logic;
rst_rsync : in std_logic; -- Use only CLK_RSYNC[0] reset
-- Control for control sync logic
mc_data_sel : in std_logic;
rd_active_dly : in std_logic_vector(4 downto 0);
-- DFI signals from MC/PHY rdlvl logic
dfi_rddata_en : in std_logic;
phy_rddata_en : in std_logic;
-- Control for read logic, initialization logic
dfi_rddata_valid : out std_logic;
dfi_rddata_valid_phy : out std_logic;
rdpath_rdy : out std_logic -- asserted when read path
-- ready for use
);
end component;
------- component phy_rddata_sync ------
component phy_rddata_sync
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_WIDTH : integer := 8; -- # # of DQ per DQS
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 4; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 4; -- # DQS groups in I/O column #4
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"11100F0E0D0C0B0A09080706050403020100";
-- DQS grps in col #1
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #2
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #3
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000"
);
port (
clk : in std_logic;
clk_rsync : in std_logic_vector(3 downto 0);
rst_rsync : in std_logic_vector(3 downto 0);
-- Captured data in resync clock domain
rd_data_rise0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall0 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_rise1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_data_fall1 : in std_logic_vector((DQ_WIDTH-1) downto 0);
rd_dqs_rise0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall0 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_rise1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
rd_dqs_fall1 : in std_logic_vector((DQS_WIDTH-1) downto 0);
-- Synchronized data/valid back to MC/PHY rdlvl logic
dfi_rddata : out std_logic_vector((4*DQ_WIDTH-1) downto 0);
dfi_rd_dqs : out std_logic_vector((4*DQS_WIDTH-1) downto 0)
);
end component;
begin
-- Drive the outputs with intermediate signals
rst_rsync <= rst_rsync_xhdl0;
clk_rsync <= clk_rsync_xhdl1;
--***************************************************************************
-- Assign signals for Debug Port
--***************************************************************************
-- Currently no assignments - add as needed
dbg_phy_read <= (others => '0');
--***************************************************************************
-- Read clocks (capture, resynchronization) generation
--***************************************************************************
u_phy_rdclk_gen: phy_rdclk_gen
generic map (
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
CLK_PERIOD => CLK_PERIOD,
DQS_WIDTH => DQS_WIDTH,
REFCLK_FREQ => REFCLK_FREQ,
IODELAY_GRP => IODELAY_GRP,
nDQS_COL0 => nDQS_COL0,
nDQS_COL1 => nDQS_COL1,
nDQS_COL2 => nDQS_COL2,
nDQS_COL3 => nDQS_COL3
)
port map (
clk_mem => clk_mem,
clk => clk,
clk_rd_base => clk_rd_base,
rst => rst,
dlyrst_cpt => dlyrst_cpt,
dlyce_cpt => dlyce_cpt,
dlyinc_cpt => dlyinc_cpt,
dlyrst_rsync => dlyrst_rsync,
dlyce_rsync => dlyce_rsync,
dlyinc_rsync => dlyinc_rsync,
clk_cpt => clk_cpt,
clk_rsync => clk_rsync_xhdl1,
rst_rsync => rst_rsync_xhdl0,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_rsync_tap_cnt => dbg_rsync_tap_cnt
);
--***************************************************************************
-- Synchronization of read enable signal from MC/PHY rdlvl logic
--***************************************************************************
u_phy_rdctrl_sync: phy_rdctrl_sync
generic map (
TCQ => TCQ
)
port map (
clk => clk,
rst_rsync => rst_rsync_xhdl0(0),
mc_data_sel => mc_data_sel,
rd_active_dly => rd_active_dly,
dfi_rddata_en => dfi_rddata_en,
phy_rddata_en => phy_rddata_en,
dfi_rddata_valid => dfi_rddata_valid,
dfi_rddata_valid_phy => dfi_rddata_valid_phy,
rdpath_rdy => rdpath_rdy
);
--***************************************************************************
-- Synchronization of read data and accompanying valid signal back to MC/
-- PHY rdlvl logic
--***************************************************************************
u_phy_rddata_sync: phy_rddata_sync
generic map (
TCQ => TCQ,
DQ_WIDTH => DQ_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_WIDTH => DRAM_WIDTH,
nDQS_COL0 => nDQS_COL0,
nDQS_COL1 => nDQS_COL1,
nDQS_COL2 => nDQS_COL2,
nDQS_COL3 => nDQS_COL3,
DQS_LOC_COL0 => DQS_LOC_COL0,
DQS_LOC_COL1 => DQS_LOC_COL1,
DQS_LOC_COL2 => DQS_LOC_COL2,
DQS_LOC_COL3 => DQS_LOC_COL3
)
port map (
clk => clk,
clk_rsync => clk_rsync_xhdl1,
rst_rsync => rst_rsync_xhdl0,
rd_data_rise0 => rd_data_rise0,
rd_data_fall0 => rd_data_fall0,
rd_data_rise1 => rd_data_rise1,
rd_data_fall1 => rd_data_fall1,
rd_dqs_rise0 => rd_dqs_rise0,
rd_dqs_fall0 => rd_dqs_fall0,
rd_dqs_rise1 => rd_dqs_rise1,
rd_dqs_fall1 => rd_dqs_fall1,
dfi_rddata => dfi_rddata,
dfi_rd_dqs => dfi_rd_dqs
);
end architecture trans;
|
lgpl-3.0
|
6376b77d240af54399031a28355e29c5
| 0.521602 | 3.89088 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_state.vhd
| 1 | 47,384 |
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : bank_state.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Tue Jun 30 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
-- Primary bank state machine. All bank specific timing is generated here.
--
-- Conceptually, when a bank machine is assigned a request, conflicts are
-- checked. If there is a conflict, then the new request is added
-- to the queue for that rank-bank.
--
-- Eventually, that request will find itself at the head of the queue for
-- its rank-bank. Forthwith, the bank machine will begin arbitration to send an
-- activate command to the DRAM. Once arbitration is successful and the
-- activate is sent, the row state machine waits the RCD delay. The RAS
-- counter is also started when the activate is sent.
--
-- Upon completion of the RCD delay, the bank state machine will begin
-- arbitration for sending out the column command. Once the column
-- command has been sent, the bank state machine waits the RTP latency, and
-- if the command is a write, the RAS counter is loaded with the WR latency.
--
-- When the RTP counter reaches zero, the pre charge wait state is entered.
-- Once the RAS timer reaches zero, arbitration to send a precharge command
-- begins.
--
-- Upon successful transmission of the precharge command, the bank state
-- machine waits the precharge period and then rejoins the idle list.
--
-- For an open rank-bank hit, a bank machine passes management of the rank-bank to
-- a bank machine that is managing the subsequent request to the same page. A bank
-- machine can either be a "passer" or a "passee" in this handoff. There
-- are two conditions that have to occur before an open bank can be passed.
-- A spatial condition, ie same rank-bank and row address. And a temporal condition,
-- ie the passee has completed it work with the bank, but has not issued a precharge.
--
-- The spatial condition is signalled by pass_open_bank_ns. The temporal condition
-- is when the column command is issued, or when the bank_wait_in_progress
-- signal is true. Bank_wait_in_progress is true when the RTP timer is not
-- zero, or when the RAS/WR timer is not zero and the state machine is waiting
-- to send out a precharge command.
--
-- On an open bank pass, the passer transitions from the temporal condition
-- noted above and performs the end of request processing and eventually lands
-- in the act_wait_r state.
--
-- On an open bank pass, the passee lands in the col_wait_r state and waits
-- for its chance to send out a column command.
--
-- Since there is a single data bus shared by all columns in all ranks, there
-- is a single column machine. The column machine is primarily in charge of
-- managing the timing on the DQ data bus. It reserves states for data transfer,
-- driver turnaround states, and preambles. It also has the ability to add
-- additional programmable delay for read to write changeovers. This read to write
-- delay is generated in the column machine which inhibits writes via the
-- inhbt_wr_r signal.
--
-- There is a rank machine for every rank. The rank machines are responsible
-- for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed
-- in the bank machine since it is closely coupled to the operation of the
-- bank machine and is timing critical.
--
-- Since a bank machine can be working on a request for any rank, all rank machines
-- inhibits are input to all bank machines. Based on the rank of the current
-- request, each bank machine selects the rank information corresponding
-- to the rank of its current request.
--
-- Since driver turnaround states and WTR delays are so severe with DDRIII, the
-- memory interface has the ability to promote requests that use the same
-- driver as the most recent request. There is logic in this block that
-- detects when the driver for its request is the same as the driver for
-- the most recent request. In such a case, this block will send out special
-- "same" request early enough to eliminate dead states when there is no
-- driver changeover.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity bank_state is
generic (
TCQ : integer := 100;
ADDR_CMD_MODE : string := "1T";
BM_CNT_WIDTH : integer := 2;
BURST_MODE : string := "8";
CWL : integer := 5;
DATA_BUF_ADDR_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
ECC : string := "OFF";
ID : integer := 0;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
nCNFG2RD_EN : integer := 2;
nCNFG2WR : integer := 2;
nOP_WAIT : integer := 0;
nRAS_CLKS : integer := 10;
nRP : integer := 10;
nRTP : integer := 4;
nRCD : integer := 5;
nWTP_CLKS : integer := 5;
ORDERING : string := "NORM";
RANKS : integer := 4;
RANK_WIDTH : integer := 4;
RAS_TIMER_WIDTH : integer := 5;
STARVE_LIMIT : integer := 2
);
port (
start_rcd : out std_logic;
act_wait_r : out std_logic;
ras_timer_ns : out std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
end_rtp : out std_logic;
rd_half_rmw : out std_logic;
bank_wait_in_progress : out std_logic;
start_pre_wait : out std_logic;
op_exit_req : out std_logic;
pre_wait_r : out std_logic;
allow_auto_pre : out std_logic;
precharge_bm_end : out std_logic;
demand_act_priority : out std_logic;
rts_row : out std_logic;
act_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
demand_priority : out std_logic;
rtc : out std_logic;
col_rdy_wr : out std_logic;
rts_col : out std_logic;
wr_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
rd_this_rank_r : out std_logic_vector(RANKS - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
bm_end : in std_logic;
pass_open_bank_r : in std_logic;
sending_row : in std_logic;
rcv_open_bank : in std_logic;
sending_col : in std_logic;
rd_wr_r : in std_logic;
req_wr_r : in std_logic;
rd_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
req_data_buf_addr_r : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_valid : in std_logic;
rd_rmw : in std_logic;
ras_timer_ns_in : in std_logic_vector((2 * (RAS_TIMER_WIDTH * nBANK_MACHS)) - 1 downto 0);
rb_hit_busies_r : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
idle_r : in std_logic;
passing_open_bank : in std_logic;
low_idle_cnt_r : in std_logic;
op_exit_grant : in std_logic;
tail_r : in std_logic;
auto_pre_r : in std_logic;
pass_open_bank_ns : in std_logic;
req_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
req_rank_r_in : in std_logic_vector((RANK_WIDTH * nBANK_MACHS * 2) - 1 downto 0);
start_rcd_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
inhbt_act_faw_r : in std_logic_vector(RANKS - 1 downto 0);
wait_for_maint_r : in std_logic;
head_r : in std_logic;
sent_row : in std_logic;
demand_act_priority_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
order_q_zero : in std_logic;
sent_col : in std_logic;
q_has_rd : in std_logic;
q_has_priority : in std_logic;
req_priority_r : in std_logic;
idle_ns : in std_logic;
demand_priority_in : in std_logic_vector((nBANK_MACHS * 2) - 1 downto 0);
io_config_strobe : in std_logic;
io_config_valid_r : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
wtr_inhbt_config_r : in std_logic_vector(RANKS - 1 downto 0);
inhbt_rd_config : in std_logic;
inhbt_wr_config : in std_logic;
inhbt_rd_r : in std_logic_vector(RANKS - 1 downto 0);
dq_busy_data : in std_logic
);
end entity bank_state;
architecture trans of bank_state is
function REDUCTION_AND( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '1';
begin
for i in A'range loop
tmp := tmp and A(i);
end loop;
return tmp;
end function REDUCTION_AND;
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
function REDUCTION_NOR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp nor A(i);
end loop;
return tmp;
end function REDUCTION_NOR;
function clogb2(size: integer) return integer is
variable tmp : integer := 1;
variable tmp_size : std_logic_vector (31 downto 0);
begin
tmp_size := std_logic_vector(TO_UNSIGNED((size - 1),32));
while ( to_integer(UNSIGNED(tmp_size)) > 1 ) loop
tmp_size := std_logic_vector(UNSIGNED(tmp_size) srl 1);
tmp := tmp + 1;
end loop;
return tmp;
end function clogb2;
function fRCD_CLKS (nCK_PER_CLK: integer; nRCD : integer ; ADDR_CMD_MODE : string)
return integer is
begin
if (nCK_PER_CLK = 1) then
return (nRCD);
else
if (ADDR_CMD_MODE = "2T") then
return ( nRCD/2 + (nRCD mod 2));
else
return nRCD/2;
end if;
end if ;
end function fRCD_CLKS;
function fRTP_CLKS (nCK_PER_CLK: integer; nRTP : integer ; ADDR_CMD_MODE : string)
return integer is
begin
if (nCK_PER_CLK = 1) then
return (nRTP);
else
if (ADDR_CMD_MODE = "2T") then
return ( nRTP/2 + (nRTP mod 2));
else
return (nRTP/2 + 1);
end if;
end if ;
end function fRTP_CLKS;
function fRP_CLKS (nCK_PER_CLK: integer; nRP : integer )
return integer is
begin
if (nCK_PER_CLK = 1) then
return (nRP);
else
return ( nRP/2 + (nRP mod 2));
end if ;
end function fRP_CLKS;
function fRCD_CLKS_M2 (nRCD_CLKS: integer)
return integer is
begin
if (nRCD_CLKS - 2 < 0) then
return 0;
else
return nRCD_CLKS-2;
end if;
end fRCD_CLKS_M2;
function fRTP_CLKS_M1 (nRTP_CLKS: integer)
return integer is
begin
if (nRTP_CLKS - 1 <= 0) then
return 0;
else
return nRTP_CLKS-1;
end if;
end fRTP_CLKS_M1;
-- Subtract two because there are a minimum of two fabric states from
-- end of RP timer until earliest possible arb to send act.
function fRP_CLKS_M2 (nRP_CLKS: integer)
return integer is
begin
if (nRP_CLKS - 2 <= 0) then
return 0;
else
return nRP_CLKS-2;
end if;
end fRP_CLKS_M2;
signal bm_end_r1 : std_logic;
signal col_wait_r : std_logic;
signal act_wait_r_lcl : std_logic;
signal start_rcd_lcl : std_logic;
signal act_wait_ns : std_logic;
-- RCD timer
-- For nCK_PER_CLK == 2, since column commands are delayed one
-- state relative to row commands, we don't need to add the remainder.
-- Unless 2T mode, in which case we're not offset and the remainder
-- must be added.
constant nRCD_CLKS : integer := fRCD_CLKS(nCK_PER_CLK,nRCD,ADDR_CMD_MODE);
constant nRCD_CLKS_M2 : integer := fRCD_CLKS_M2(nRCD_CLKS);
constant RCD_TIMER_WIDTH : integer := clogb2(nRCD_CLKS_M2+1);
constant ZERO : integer := 0;
constant ONE : integer := 1;
signal rcd_timer_r : std_logic_vector(RCD_TIMER_WIDTH - 1 downto 0) := (others => '0' );
signal end_rcd : std_logic;
signal rcd_active_r : std_logic := '0';
-- Generated so that the config can be started during the RCD, if
-- possible.
signal allow_early_rd_config : std_logic;
signal allow_early_wr_config : std_logic;
signal rmw_rd_done : std_logic := '0';
signal rd_half_rmw_lcl : std_logic := '0';
signal rmw_wait_r : std_logic := '0';
signal col_wait_ns : std_logic;
-- Set up various RAS timer parameters, wires, etc.
constant TWO : integer := 2;
signal ras_timer_r : std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
signal passed_ras_timer : std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
signal i : integer;
signal start_wtp_timer : std_logic;
signal ras_timer_passed_ns : std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
signal ras_timer_zero_ns : std_logic;
signal ras_timer_zero_r : std_logic;
-- RTP timer. Unless 2T mode, add one to account for fixed row command
-- to column command offset of -1.
constant nRTP_CLKS : integer := fRTP_CLKS(nCK_PER_CLK,nRTP,ADDR_CMD_MODE);
constant nRTP_CLKS_M1 : integer := fRTP_CLKS_M1(nRTP_CLKS);
constant RTP_TIMER_WIDTH : integer := clogb2(nRTP_CLKS_M1 + 1);
signal rtp_timer_ns : std_logic_vector(RTP_TIMER_WIDTH - 1 downto 0);
signal rtp_timer_r : std_logic_vector(RTP_TIMER_WIDTH - 1 downto 0);
signal sending_col_not_rmw_rd : std_logic;
signal end_rtp_lcl : std_logic;
-- Optionally implement open page mode timer.
constant OP_WIDTH : integer := clogb2(nOP_WAIT + 1);
signal start_pre : std_logic;
signal pre_wait_ns : std_logic;
signal pre_request : std_logic;
-- precharge timer.
constant nRP_CLKS : integer := fRP_CLKS(nCK_PER_CLK,nRP) ;
constant nRP_CLKS_M2 : integer := fRP_CLKS_M2(nRP_CLKS);
constant RP_TIMER_WIDTH : integer := clogb2(nRP_CLKS_M2 + 1);
signal rp_timer_r : std_logic_vector(RP_TIMER_WIDTH - 1 downto 0) :=(others => '0');
signal inhbt_act_rrd : std_logic;
signal j : integer;
signal my_inhbt_act_faw : std_logic;
signal act_req : std_logic;
signal rts_act_denied : std_logic;
signal act_starve_limit_cntr_ns : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
signal act_starve_limit_cntr_r : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
signal demand_act_priority_r : std_logic;
signal demand_act_priority_ns : std_logic;
signal act_demanded : std_logic := '0';
signal row_demand_ok : std_logic;
signal act_this_rank_ns : std_logic_vector(RANKS - 1 downto 0);
signal req_bank_rdy_ns : std_logic;
signal req_bank_rdy_r : std_logic;
signal rts_col_denied : std_logic;
constant STARVE_LIMIT_CNT : integer := STARVE_LIMIT * nBANK_MACHS;
constant STARVE_LIMIT_WIDTH : integer := clogb2(STARVE_LIMIT_CNT);
signal starve_limit_cntr_r : std_logic_vector(STARVE_LIMIT_WIDTH - 1 downto 0);
signal starve_limit_cntr_ns : std_logic_vector(STARVE_LIMIT_WIDTH - 1 downto 0);
signal starved : std_logic;
signal demand_priority_r : std_logic;
signal demand_priority_ns : std_logic;
signal demanded : std_logic := '0';
signal demanded_prior_r : std_logic;
signal demanded_prior_ns : std_logic;
signal demand_ok : std_logic;
signal pre_config_match_ns : std_logic;
signal pre_config_match_r : std_logic;
signal io_config_match : std_logic;
signal early_config : std_logic;
signal my_wtr_inhbt_config : std_logic;
signal my_inhbt_rd : std_logic;
signal allow_rw : std_logic;
signal col_rdy : std_logic;
signal col_cmd_rts : std_logic;
signal override_demand_ns : std_logic;
signal override_demand_r : std_logic;
signal wr_this_rank_ns : std_logic_vector(RANKS - 1 downto 0);
signal rd_this_rank_ns : std_logic_vector(RANKS - 1 downto 0);
signal rcd_timer_ns : std_logic_vector(RCD_TIMER_WIDTH - 1 downto 0);
signal end_rcd_ns : std_logic;
signal rcd_active_ns : std_logic;
signal op_wait_r : std_logic;
signal op_active : std_logic;
signal op_wait_ns : std_logic;
signal op_cnt_ns : std_logic_vector(OP_WIDTH-1 downto 0);
signal op_cnt_r : std_logic_vector(OP_WIDTH-1 downto 0);
signal rp_timer_ns : std_logic_vector(RP_TIMER_WIDTH -1 downto 0);
-- Declare intermediate signals for referenced outputs
signal act_wait_r_int0 : std_logic;
signal ras_timer_ns_int1 : std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
signal start_pre_wait_int3 : std_logic;
signal pre_wait_r_int1 : std_logic;
signal my_rmw_rd_ns : std_logic;
signal rmw_wait_ns : std_logic;
signal inhbt_config : std_logic;
--Temporary signal added to hold the default value of the rd_half_rmw
--signal when it is not driven
signal rd_half_rmw_temp : std_logic := '0';
--Register dfi_rddata_valid and rd_rmw to align them to req_data_buf_addr_r
signal dfi_rddata_valid_r : std_logic;
signal rd_rmw_r : std_logic;
begin
-- Drive referenced outputs
act_wait_r <= act_wait_r_int0;
start_pre_wait <= start_pre_wait_int3;
pre_wait_r <= pre_wait_r_int1;
process (clk)
begin
if (clk'event and clk = '1') then
bm_end_r1 <= bm_end after (TCQ)*1 ps;
end if;
end process;
start_rcd_lcl <= act_wait_r_lcl and sending_row;
start_rcd <= start_rcd_lcl;
act_wait_ns <= rst or ((act_wait_r_lcl and not(start_rcd_lcl) and
not(rcv_open_bank)
) or
bm_end_r1 or
(pass_open_bank_r and bm_end)
);
process (clk)
begin
if (clk'event and clk = '1') then
act_wait_r_lcl <= act_wait_ns after (TCQ)*1 ps;
end if;
end process;
act_wait_r_int0 <= act_wait_r_lcl;
rcd_timer_1 : if (nRCD_CLKS <= 1) generate
process (start_rcd_lcl)
begin
end_rcd <= start_rcd_lcl;
end process;
process (end_rcd)
begin
allow_early_rd_config <= end_rcd;
end process;
process (end_rcd)
begin
allow_early_wr_config <= end_rcd;
end process;
end generate;
rcd_timer_2 : if (nRCD_CLKS = 2) generate
process (start_rcd_lcl)
begin
end_rcd <= start_rcd_lcl;
end process;
int_i1: if (nCNFG2RD_EN > 0) generate
process (end_rcd)
begin
allow_early_rd_config <= end_rcd;
end process;
end generate;
int_i2: if (nCNFG2WR > 0) generate
process (end_rcd)
begin
allow_early_wr_config <= end_rcd;
end process;
end generate;
end generate;
rcd_timer_gt_2 : if (nRCD_CLKS > 2) generate
process (rcd_timer_r, rst, start_rcd_lcl)
variable rcd_timer_ns_v : std_logic_vector(RCD_TIMER_WIDTH - 1 downto 0);
begin
if (rst = '1') then
rcd_timer_ns_v := (others => '0');
else
rcd_timer_ns_v := rcd_timer_r;
if (start_rcd_lcl = '1') then
rcd_timer_ns_v := std_logic_vector(TO_UNSIGNED(nRCD_CLKS_M2,RCD_TIMER_WIDTH));
elsif ((REDUCTION_OR(rcd_timer_r)) = '1') then
rcd_timer_ns_v := rcd_timer_r - std_logic_vector(TO_UNSIGNED(1,1));
end if;
end if;
rcd_timer_ns <= rcd_timer_ns_v;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rcd_timer_r <= rcd_timer_ns after (TCQ)*1 ps;
end if;
end process;
end_rcd_ns <= '1' when (rcd_timer_ns = std_logic_vector(TO_UNSIGNED(1,RCD_TIMER_WIDTH))) else '0';
process (clk)
begin
if (clk'event and clk = '1') then
end_rcd <= end_rcd_ns;
end if;
end process;
rcd_active_ns <= REDUCTION_OR(rcd_timer_ns);
process (clk)
begin
if (clk'event and clk = '1') then
rcd_active_r <= rcd_active_ns after (TCQ)*1 ps;
end if;
end process;
allow_early_rd_config <= '1' when ((to_integer( UNSIGNED(rcd_timer_r)) <= nCNFG2RD_EN) and rcd_active_r = '1') or
((nCNFG2RD_EN > nRCD_CLKS) and start_rcd_lcl = '1') else '0';
allow_early_wr_config <= '1' when ((to_integer( UNSIGNED(rcd_timer_r)) <= nCNFG2WR) and rcd_active_r = '1') or
((nCNFG2WR > nRCD_CLKS) and start_rcd_lcl = '1') else '0';
end generate;
rd_half_rmw <= rd_half_rmw_temp;
rmw_on : if (not (ECC = "OFF")) generate
-- Delay dfi_rddata_valid and rd_rmw by one cycle to align them
-- to req_data_buf_addr_r so that rmw_wait_r clears properly
process (clk)
begin
if (clk'event and clk = '1') then
dfi_rddata_valid_r <= dfi_rddata_valid after (TCQ)*1 ps;
rd_rmw_r <= rd_rmw after (TCQ)*1 ps;
end if;
end process;
my_rmw_rd_ns <= '1' when ((dfi_rddata_valid_r = '1') and (rd_rmw_r = '1') and (rd_data_addr = req_data_buf_addr_r))
else '0';
int12 : if (CWL = 8) generate
process (my_rmw_rd_ns)
begin
rmw_rd_done <= my_rmw_rd_ns;
end process;
end generate;
int13 : if (not(CWL = 8)) generate
process (clk)
begin
if (clk'event and clk = '1') then
rmw_rd_done <= my_rmw_rd_ns after (TCQ)*1 ps;
end if;
end process;
end generate;
-- Figure out if the read that's completing is for an RMW for
-- this bank machine. Delay by a state if CWL != 8 since the
-- data is not ready in the RMW buffer for the early write
-- data fetch that happens with ECC and CWL != 8.
-- Create a state bit indicating we're waiting for the read
-- half of the rmw to complete.
process (rd_wr_r, req_wr_r)
begin
rd_half_rmw_lcl <= req_wr_r and rd_wr_r;
end process;
rd_half_rmw_temp <= rd_half_rmw_lcl;
rmw_wait_ns <= not(rst) and ((rmw_wait_r and not(rmw_rd_done)) or (rd_half_rmw_lcl and sending_col));
process (clk)
begin
if (clk'event and clk = '1') then
rmw_wait_r <= rmw_wait_ns after (TCQ)*1 ps;
end if;
end process;
end generate;
-- column wait state machine.
col_wait_ns <= not(rst) and ((col_wait_r and not(sending_col)) or end_rcd or rcv_open_bank or (rmw_rd_done and rmw_wait_r));
process (clk)
begin
if (clk'event and clk = '1') then
col_wait_r <= col_wait_ns after (TCQ)*1 ps;
end if;
end process;
-- On a bank pass, select the RAS timer from the passing bank machine.
process (ras_timer_ns_in, rb_hit_busies_r)
variable passed_ras_timer_v : std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
begin
passed_ras_timer_v := (others => '0');
for i in ID + 1 to (ID + nBANK_MACHS) - 1 loop
if ((rb_hit_busies_r(i)) = '1') then
passed_ras_timer_v := ras_timer_ns_in(i * RAS_TIMER_WIDTH + RAS_TIMER_WIDTH - 1 downto i*RAS_TIMER_WIDTH);
end if;
end loop;
passed_ras_timer <= passed_ras_timer_v;
end process;
-- RAS and (reused for) WTP timer. When an open bank is passed, this
-- timer is passed to the new owner. The existing RAS prevents
-- an activate from occuring too early.
start_wtp_timer <= sending_col and not(rd_wr_r);
process (bm_end_r1, ras_timer_r, rst, start_rcd_lcl, start_wtp_timer)
variable ras_timer_ns_int2 : std_logic_vector(RAS_TIMER_WIDTH - 1 downto 0);
begin
if ((bm_end_r1 or rst) = '1') then
ras_timer_ns_int2 := (others => '0');
else
ras_timer_ns_int2 := ras_timer_r;
if (start_rcd_lcl = '1') then
ras_timer_ns_int2 := std_logic_vector(TO_UNSIGNED(nRAS_CLKS, RAS_TIMER_WIDTH)) -
std_logic_vector(TO_UNSIGNED(2,RAS_TIMER_WIDTH));
end if;
if (start_wtp_timer = '1') then
--CR #534391
--As the timer is being reused, it is essential to compare
--before new value is loaded. There was case where timer(ras_timer_r)
--is getting updated with a new value(nWTP_CLKS-2) at write
--command that was quite less than the timer value at that
--time. This made the tRAS timer to expire earlier and resulted.
--in tRAS timing violation.
if ( to_integer(unsigned (ras_timer_r)) <= nWTP_CLKS - 2 ) then
ras_timer_ns_int2 := std_logic_vector(TO_UNSIGNED(nWTP_CLKS, RAS_TIMER_WIDTH)) -
std_logic_vector(TO_UNSIGNED(2,RAS_TIMER_WIDTH));
else
ras_timer_ns_int2 := ras_timer_r - std_logic_vector(TO_UNSIGNED(1,RAS_TIMER_WIDTH));
end if;
end if;
if ((REDUCTION_OR(ras_timer_r) and not(start_wtp_timer)) = '1') then
ras_timer_ns_int2 := ras_timer_r - std_logic_vector(TO_UNSIGNED(1,RAS_TIMER_WIDTH));
end if;
end if;
ras_timer_ns <= ras_timer_ns_int2;
ras_timer_ns_int1 <= ras_timer_ns_int2;
end process;
ras_timer_passed_ns <= passed_ras_timer when (rcv_open_bank = '1') else
ras_timer_ns_int1;
process (clk)
begin
if (clk'event and clk = '1') then
ras_timer_r <= ras_timer_passed_ns after (TCQ)*1 ps;
end if;
end process;
ras_timer_zero_ns <= '1' when (ras_timer_ns_int1 = 0) else '0';
process (clk)
begin
if (clk'event and clk = '1') then
ras_timer_zero_r <= ras_timer_zero_ns after (TCQ)*1 ps;
end if;
end process;
sending_col_not_rmw_rd <= sending_col and not(rd_half_rmw_lcl);
process (pass_open_bank_r, rst, rtp_timer_r, sending_col_not_rmw_rd)
variable rtp_timer_ns_v : std_logic_vector(RTP_TIMER_WIDTH - 1 downto 0);
begin
rtp_timer_ns_v := rtp_timer_r;
if ((rst or pass_open_bank_r) = '1') then
rtp_timer_ns_v := (others => '0');
else
if (sending_col_not_rmw_rd = '1') then
rtp_timer_ns_v := std_logic_vector(TO_UNSIGNED(nRTP_CLKS_M1,RTP_TIMER_WIDTH)); --nRTP_CLKS_M1
end if;
if ((REDUCTION_OR(rtp_timer_r)) = '1') then
rtp_timer_ns_v := rtp_timer_r - std_logic_vector(TO_UNSIGNED(1,RTP_TIMER_WIDTH ));
end if;
end if;
rtp_timer_ns <= rtp_timer_ns_v;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rtp_timer_r <= rtp_timer_ns after (TCQ)*1 ps;
end if;
end process;
end_rtp_lcl <= '1' when (pass_open_bank_r = '0' ) and
((rtp_timer_r = std_logic_vector(TO_UNSIGNED(1,RTP_TIMER_WIDTH))) or
((nRTP_CLKS_M1 = 0) and (sending_col_not_rmw_rd = '1'))) else '0';
end_rtp <= end_rtp_lcl;
op_mode_disabled : if (nOP_WAIT = 0) generate
bank_wait_in_progress <= sending_col_not_rmw_rd or
REDUCTION_OR(rtp_timer_r) or
(pre_wait_r_int1 and
not(ras_timer_zero_r));
start_pre_wait_int3 <= end_rtp_lcl;
op_exit_req <= '0';
end generate;
op_mode_enabled : if (not(nOP_WAIT = 0)) generate
bank_wait_in_progress <= sending_col or
REDUCTION_OR(rtp_timer_r) or
(pre_wait_r_int1 and
not(ras_timer_zero_r)) or op_wait_r;
op_active <= not(rst) and not(passing_open_bank) and ((end_rtp_lcl and tail_r) or op_wait_r);
op_wait_ns <= not (op_exit_grant) and op_active ;
process (clk)
begin
if (clk'event and clk = '1') then
op_wait_r <= op_wait_ns after (TCQ)*1 ps;
end if;
end process;
start_pre_wait_int3 <= op_exit_grant or (end_rtp_lcl and not(tail_r) and not(passing_open_bank));
int16 : if (nOP_WAIT = -1) generate
op_exit_req <= (low_idle_cnt_r and op_active);
end generate;
int17 : if (not(nOP_WAIT = -1)) generate
op_cnt_ns <= (others => '0') when (passing_open_bank = '1' or op_exit_grant = '1' or rst = '1') else
std_logic_vector(TO_UNSIGNED(nOP_WAIT,OP_WIDTH)) when (end_rtp_lcl = '1') else
op_cnt_r - std_logic_vector(TO_UNSIGNED(1,OP_WIDTH)) when ((REDUCTION_OR(op_cnt_r)) = '1') else
op_cnt_r;
process (clk)
begin
if (clk'event and clk = '1') then
op_cnt_r <= op_cnt_ns after (TCQ)*1 ps;
end if;
end process;
--op_exit_req <= (low_idle_cnt_r and op_active) or (op_wait_r and REDUCTION_NOR(op_cnt_r));
op_exit_req <= (op_wait_r and REDUCTION_NOR(op_cnt_r)); --Changed by KK for improving the
--effeciency in case of known patterns
end generate;
end generate;
allow_auto_pre <= act_wait_r_lcl or rcd_active_r or (col_wait_r and not(sending_col) );
-- precharge wait state machine.
pre_wait_ns <= not(rst) and (not(pass_open_bank_ns) and (start_pre_wait_int3 or (pre_wait_r_int1 and not(start_pre))));
process (clk)
begin
if (clk'event and clk = '1') then
pre_wait_r_int1 <= pre_wait_ns after (TCQ)*1 ps;
end if;
end process;
pre_request <= pre_wait_r_int1 and ras_timer_zero_r and not(auto_pre_r);
start_pre <= pre_wait_r_int1 and ras_timer_zero_r and (sending_row or auto_pre_r);
int18 : if (nRP_CLKS_M2 > ZERO) generate
process (rp_timer_r, rst, start_pre)
begin
if (rst = '1') then
rp_timer_ns <= (others => '0');
else
rp_timer_ns <= rp_timer_r;
if (start_pre = '1') then
rp_timer_ns <= std_logic_vector(TO_UNSIGNED(nRP_CLKS_M2,RP_TIMER_WIDTH ));
elsif ((REDUCTION_OR(rp_timer_r)) = '1') then
rp_timer_ns <= rp_timer_r - std_logic_vector(TO_UNSIGNED(1,RP_TIMER_WIDTH ));
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rp_timer_r <= rp_timer_ns after (TCQ)*1 ps;
end if;
end process;
end generate;
precharge_bm_end <= '1' when (rp_timer_r = std_logic_vector(TO_UNSIGNED(1,RP_TIMER_WIDTH ))) or
(start_pre = '1' and nRP_CLKS_M2 = 0) else '0';
-- Compute RRD related activate inhibit.
-- Compare this bank machine's rank with others, then
-- select result based on grant. An alternative is to
-- select the just issued rank with the grant and simply
-- compare against this bank machine's rank. However, this
-- serializes the selection of the rank and the compare processes.
-- As implemented below, the compare occurs first, then the
-- selection based on grant. This is faster.
int19 : if (RANKS = 1) generate
process ( start_rcd_in)
variable inhbt_act_rrd_tmp :std_logic;
begin
inhbt_act_rrd_tmp := '0';
for j in (ID + 1) to (ID + nBANK_MACHS) - 1 loop
inhbt_act_rrd_tmp := inhbt_act_rrd_tmp or start_rcd_in(j) ;
end loop;
inhbt_act_rrd <= inhbt_act_rrd_tmp;
end process;
end generate;
int20 : if (not(RANKS = 1)) generate
process (req_rank_r, req_rank_r_in, start_rcd_in,rst)
variable inhbt_act_rrd_tmp :std_logic;
begin
inhbt_act_rrd_tmp := '0';
for j in (ID + 1) to (ID + nBANK_MACHS) - 1 loop
if (req_rank_r_in(j*RANK_WIDTH + RANK_WIDTH - 1 downto j * RANK_WIDTH) = req_rank_r) then
inhbt_act_rrd_tmp := inhbt_act_rrd_tmp or start_rcd_in(j) ;
end if;
end loop;
inhbt_act_rrd <= inhbt_act_rrd_tmp;
end process;
end generate;
-- Extract the activate command inhibit for the rank associated
-- with this request. FAW and RRD are computed separately so that
-- gate level timing can be carefully managed.
my_inhbt_act_faw <= inhbt_act_faw_r(conv_integer(req_rank_r));
act_req <= not(idle_r) and head_r and act_wait_r_int0 and ras_timer_zero_r and not(wait_for_maint_r);
-- Implement simple starvation avoidance for act requests. Precharge
-- requests don't need this because they are never gated off by
-- timing events such as inhbt_act_rrd. Priority request timeout
-- is fixed at a single trip around the round robin arbiter.
rts_act_denied <= act_req and sent_row and not(sending_row);
process (act_req, act_starve_limit_cntr_r, rts_act_denied)
begin
act_starve_limit_cntr_ns <= act_starve_limit_cntr_r;
if ((not(act_req)) = '1') then
act_starve_limit_cntr_ns <= (others => '0');
elsif ((rts_act_denied and REDUCTION_AND(act_starve_limit_cntr_r)) = '1') then
act_starve_limit_cntr_ns <= act_starve_limit_cntr_r + '1';
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
act_starve_limit_cntr_r <= act_starve_limit_cntr_ns after (TCQ)*1 ps;
end if;
end process;
demand_act_priority_ns <= act_req and (demand_act_priority_r or
(rts_act_denied and REDUCTION_AND(act_starve_limit_cntr_r)));
process (clk)
begin
if (clk'event and clk = '1') then
demand_act_priority_r <= demand_act_priority_ns after (TCQ)*1 ps;
end if;
end process;
demand_act_priority <= demand_act_priority_r and not(sending_row);
-- compute act_demanded from other demand_act_priorities
int21 : if (nBANK_MACHS > 1) generate
process (demand_act_priority_in((ID + nBANK_MACHS - 1) downto (ID + 1)))
begin
act_demanded <= REDUCTION_OR(demand_act_priority_in((ID + nBANK_MACHS - 1) downto (ID + 1)));
end process;
end generate;
row_demand_ok <= demand_act_priority_r or not(act_demanded);
-- Generate the Request To Send row arbitation signal.
rts_row <= not(sending_row) and row_demand_ok and ((act_req and not(my_inhbt_act_faw) and
not(inhbt_act_rrd)) or pre_request);
-- Provide rank machines early knowledge that this bank machine is
-- going to send an activate to the rank. In this way, the rank
-- machines just need to use the sending_row wire to figure out if
-- they need to keep track of the activate.
process (act_wait_r_int0, req_rank_r)
begin
act_this_rank_ns <= (others => '0');
for i in 0 to RANKS - 1 loop
if (req_rank_r = std_logic_vector(TO_UNSIGNED(i, RANK_WIDTH))) then
act_this_rank_ns(i) <= act_wait_r_int0;
end if;
end loop;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
act_this_rank_r <= act_this_rank_ns after (TCQ)*1 ps;
end if;
end process;
-- Generate request to send column command signal.
req_bank_rdy_ns <= order_q_zero and col_wait_r;
process (clk)
begin
if (clk'event and clk = '1') then
req_bank_rdy_r <= req_bank_rdy_ns after (TCQ)*1 ps;
end if;
end process;
-- Determine is we have been denied a column command request.
rts_col_denied <= req_bank_rdy_r and sent_col and not(sending_col);
-- Implement a starvation limit counter. Count the number of times a
-- request to send a column command has been denied.
process (col_wait_r, rts_col_denied, starve_limit_cntr_r)
begin
if (col_wait_r = '0') then
starve_limit_cntr_ns <= (others => '0');
elsif (rts_col_denied = '1' and (starve_limit_cntr_r /= std_logic_vector(TO_UNSIGNED(STARVE_LIMIT_CNT - 1, STARVE_LIMIT_WIDTH)))) then
starve_limit_cntr_ns <= starve_limit_cntr_r + '1';
else
starve_limit_cntr_ns <= starve_limit_cntr_r;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
starve_limit_cntr_r <= starve_limit_cntr_ns after (TCQ)*1 ps;
end if;
end process;
-- Decide if this bank machine should demand priority. Priority is demanded
-- when starvation limit counter is reached, or a bit in the request.
starved <= '1' when (starve_limit_cntr_r = std_logic_vector(TO_UNSIGNED(STARVE_LIMIT_CNT - 1, STARVE_LIMIT_WIDTH))) and
rts_col_denied = '1'
else '0';
-- compute demanded from other demand_priorities
demand_priority_ns <= not(idle_ns) and col_wait_ns and
(demand_priority_r or (order_q_zero and (req_priority_r or q_has_priority))
or (starved and (q_has_rd or not(req_wr_r)))
);
process (clk)
begin
if (clk'event and clk = '1') then
demand_priority_r <= demand_priority_ns after (TCQ)*1 ps;
end if;
end process;
int22 : if (nBANK_MACHS > 1) generate
process (demand_priority_in((ID + nBANK_MACHS - 1) downto (ID + 1)))
begin
demanded <= REDUCTION_OR(demand_priority_in((ID + nBANK_MACHS - 1) downto (ID + 1)));
end process;
end generate;
-- In order to make sure that there is no starvation amongst a possibly
-- unlimited stream of priority requests, add a second stage to the demand
-- priority signal. If there are no other requests demanding priority, then
-- go ahead and assert demand_priority. If any other requests are asserting
-- demand_priority, hold off asserting demand_priority until these clear, then
-- assert demand priority. Its possible to get multiple requests asserting
-- demand priority simultaneously, but that's OK. Those requests will be
-- serviced, demanded will fall, and another group of requests will be
-- allowed to assert demand_priority.
demanded_prior_ns <= demanded and (demanded_prior_r or not(demand_priority_r));
process (clk)
begin
if (clk'event and clk = '1') then
demanded_prior_r <= demanded_prior_ns after (TCQ)*1 ps;
end if;
end process;
demand_priority <= demand_priority_r and not(demanded_prior_r) and not(sending_col);
demand_ok <= demand_priority_r or not(demanded);
-- Figure out if the request in this bank machine matches the current io
-- configuration.
pre_config_match_ns <= '1' when (io_config_valid_r = '1') and (io_config = not rd_wr_r & req_rank_r)
else '0';
process (clk)
begin
if (clk'event and clk = '1') then
pre_config_match_r <= pre_config_match_ns after (TCQ)*1 ps;
end if;
end process;
int23 : if (nCNFG2WR = 1) generate
io_config_match <= pre_config_match_ns when ((not(rd_wr_r)) = '1') else
not(io_config_strobe) and pre_config_match_r;
end generate;
int24 : if (not(nCNFG2WR = 1)) generate
io_config_match <= pre_config_match_r;
end generate;
-- Compute desire to send a column command independent of whether or not
-- various DRAM timing parameters are met. Ignoring DRAM timing parameters is
-- necessary to insure priority. This is used to drive the demand
-- priority signal.
early_config <= allow_early_wr_config when ((not(rd_wr_r)) = '1') else
allow_early_rd_config;
-- Using rank state provided by the rank machines, figure out if
-- a io configs should wait for WTR.
my_wtr_inhbt_config <= wtr_inhbt_config_r(conv_integer(req_rank_r));
inhbt_config <= (not inhbt_wr_config) when ((not(rd_wr_r)) = '1') else
(not inhbt_rd_config);
rtc <= not(io_config_match) and order_q_zero and
(col_wait_r or early_config) and
demand_ok and not(my_wtr_inhbt_config) and inhbt_config;
-- Using rank state provided by the rank machines, figure out if
-- a read requests should wait for WTR.
my_inhbt_rd <= inhbt_rd_r(conv_integer(req_rank_r));
allow_rw <= '1' when ((not(rd_wr_r)) = '1') else
not(my_inhbt_rd);
-- Column command is ready to arbitrate, except for databus restrictions.
col_rdy <= '1' when (col_wait_r = '1' or
((nRCD_CLKS <= 1) and end_rcd = '1' ) or
(rcv_open_bank = '1' and (DRAM_TYPE = "DDR2") and (BURST_MODE = "4"))) and order_q_zero = '1' else '0';
-- Column command is ready to arbitrate for sending a write. Used
-- to generate early wr_data_addr for ECC mode.
col_rdy_wr <= col_rdy and not(rd_wr_r);
-- Figure out if we're ready to send a column command based on all timing
-- constraints. Use of io_config_match could be replaced by later versions
-- if timing is an issue.
col_cmd_rts <= col_rdy and not(dq_busy_data) and allow_rw and io_config_match;
-- Disable priority feature for one state after a config to insure
-- forward progress on the just installed io config.
override_demand_ns <= io_config_strobe;
process (clk)
begin
if (clk'event and clk = '1') then
override_demand_r <= override_demand_ns;
end if;
end process;
rts_col <= not(sending_col) and (demand_ok or override_demand_r) and col_cmd_rts;
-- As in act_this_rank, wr/rd_this_rank informs rank machines
-- that this bank machine is doing a write/rd. Removes logic
-- after the grant.
process (rd_wr_r, req_rank_r)
variable wr_this_rank_ns_v : std_logic_vector(RANKS - 1 downto 0);
variable rd_this_rank_ns_v : std_logic_vector(RANKS - 1 downto 0);
begin
wr_this_rank_ns_v := (others => '0' );
rd_this_rank_ns_v := (others => '0' );
for i in 0 to RANKS - 1 loop
if (req_rank_r = std_logic_vector(TO_UNSIGNED(i,RANK_WIDTH))) then
wr_this_rank_ns_v(i) := not rd_wr_r;
rd_this_rank_ns_v(i) := rd_wr_r ;
end if;
end loop;
wr_this_rank_ns <= wr_this_rank_ns_v;
rd_this_rank_ns <= rd_this_rank_ns_v;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
wr_this_rank_r <= wr_this_rank_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rd_this_rank_r <= rd_this_rank_ns after (TCQ)*1 ps; -- bank_state
end if;
end process;
end architecture trans;
|
lgpl-3.0
|
3c1c916779f29f8ef7dcfa39d5210896
| 0.568378 | 3.620139 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/tlpControl.vhd
| 1 | 47,406 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:09:49 10/18/2006
-- Design Name:
-- Module Name: tlpControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.20 - Memory space repartitioned. 13.07.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.06 - Timing improved. 17.01.2007
--
-- Revision 1.04 - FIFO added. 20.12.2006
--
-- Revision 1.02 - second release. 14.12.2006
--
-- Revision 1.00 - first release. 18.10.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
entity tlpControl is
port (
-- Wishbone write interface
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_full : in std_logic;
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
wb_timeout : out std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_rst : out std_logic;
-- DDR control interface
DDR_Ready : in std_logic;
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tready : out std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-- Transaction transmit interface
s_axis_tx_tlast : out std_logic;
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
s_axis_tx_tvalid : out std_logic;
s_axis_tx_tready : in std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
-- Interrupt Interface
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
-- Local signals
pcie_link_width : in std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
cfg_dcommand : in std_logic_vector(16-1 downto 0);
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end entity tlpControl;
architecture Behavioral of tlpControl is
---- Rx transaction control
component rx_Transact
port (
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tready : out std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-- MRd Channel
pioCplD_Req : out std_logic;
pioCplD_RE : in std_logic;
pioCplD_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- MRd-downstream packet Channel
dsMRd_Req : out std_logic;
dsMRd_RE : in std_logic;
dsMRd_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Upstream MWr/MRd Channel
usTlp_Req : out std_logic;
usTlp_RE : in std_logic;
usTlp_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : in std_logic;
us_Last_sof : in std_logic;
us_Last_eof : in std_logic;
-- Irpt Channel
Irpt_Req : out std_logic;
Irpt_RE : in std_logic;
Irpt_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- SDRAM and Wishbone pages
sdram_pg : in std_logic_vector(31 downto 0);
wb_pg : in std_logic_vector(31 downto 0);
-- Interrupt Interface
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
-- Wishbone write port
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_FIFO_full : in std_logic;
wb_FIFO_Empty : in std_logic;
wb_FIFO_Reading : in std_logic;
-- Registers Write Port
Regs_WrEn0 : out std_logic;
Regs_WrMask0 : out std_logic_vector(2-1 downto 0);
Regs_WrAddr0 : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin0 : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEn1 : out std_logic;
Regs_WrMask1 : out std_logic_vector(2-1 downto 0);
Regs_WrAddr1 : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin1 : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : out std_logic;
ds_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- --------------------------
-- Registers
DMA_ds_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : in std_logic;
DMA_ds_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : out std_logic;
DMA_ds_Busy : out std_logic;
DMA_ds_Tout : out std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : in std_logic;
dsBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : in std_logic;
dsLeng_Lo7b_True : in std_logic;
dsDMA_Start : in std_logic;
dsDMA_Stop : in std_logic;
dsDMA_Start2 : in std_logic;
dsDMA_Stop2 : in std_logic;
dsDMA_Channel_Rst : in std_logic;
dsDMA_Cmd_Ack : out std_logic;
DMA_us_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : in std_logic;
us_MWr_Param_Vec : in std_logic_vector(6-1 downto 0);
DMA_us_Status : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : out std_logic;
DMA_us_Busy : out std_logic;
DMA_us_Tout : out std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : in std_logic;
usBDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : in std_logic;
usLeng_Lo7b_True : in std_logic;
usDMA_Start : in std_logic;
usDMA_Stop : in std_logic;
usDMA_Start2 : in std_logic;
usDMA_Stop2 : in std_logic;
usDMA_Channel_Rst : in std_logic;
usDMA_Cmd_Ack : out std_logic;
MRd_Channel_Rst : in std_logic;
Sys_IRQ : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof_A : out std_logic;
DDR_wr_eof_A : out std_logic;
DDR_wr_v_A : out std_logic;
DDR_wr_Shift_A : out std_logic;
DDR_wr_Mask_A : out std_logic_vector(2-1 downto 0);
DDR_wr_din_A : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_sof_B : out std_logic;
DDR_wr_eof_B : out std_logic;
DDR_wr_v_B : out std_logic;
DDR_wr_Shift_B : out std_logic;
DDR_wr_Mask_B : out std_logic_vector(2-1 downto 0);
DDR_wr_din_B : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
-- Interrupt generator signals
IG_Reset : in std_logic;
IG_Host_Clear : in std_logic;
IG_Latency : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : out std_logic;
-- Additional
cfg_dcommand : in std_logic_vector(16-1 downto 0);
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end component rx_Transact;
-- Downstream DMA transferred bytes count up
signal ds_DMA_Bytes_Add : std_logic;
signal ds_DMA_Bytes : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
---- Tx transaction control
component tx_Transact
port (
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic;
-- Transaction
s_axis_tx_tlast : out std_logic;
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
s_axis_tx_tvalid : out std_logic;
s_axis_tx_tready : in std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : out std_logic;
us_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- MRd Channel
pioCplD_Req : in std_logic;
pioCplD_RE : out std_logic;
pioCplD_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- MRd-downstream packet Channel
dsMRd_Req : in std_logic;
dsMRd_RE : out std_logic;
dsMRd_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Upstream MWr Channel
usTlp_Req : in std_logic;
usTlp_RE : out std_logic;
usTlp_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : out std_logic;
us_Last_sof : out std_logic;
us_Last_eof : out std_logic;
-- Irpt Channel
Irpt_Req : in std_logic;
Irpt_RE : out std_logic;
Irpt_Qout : in std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- With Rx port
Regs_RdAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Message routing method
Msg_Routing : in std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
-- DDR read port
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
Tx_TimeOut : out std_logic;
Tx_wb_TimeOut : out std_logic;
Tx_Reset : in std_logic;
localID : in std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end component tx_Transact;
-- Upstream DMA transferred bytes count up
signal us_DMA_Bytes_Add : std_logic;
signal us_DMA_Bytes : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- ------------------------------------------------
-- United memory space consisting of registers.
--
component Regs_Group
port (
-- Wishbone Buffer status
wb_FIFO_Rst : out std_logic;
-- Register Write
Regs_WrEnA : in std_logic;
Regs_WrMaskA : in std_logic_vector(2-1 downto 0);
Regs_WrAddrA : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEnB : in std_logic;
Regs_WrMaskB : in std_logic_vector(2-1 downto 0);
Regs_WrAddrB : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinB : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : in std_logic;
ds_DMA_Bytes : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Register Values
DMA_ds_PA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : out std_logic;
DMA_ds_Status : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : in std_logic;
DMA_ds_Tout : in std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : out std_logic;
dsBDA_is_64b : out std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : out std_logic;
dsLeng_Lo7b_True : out std_logic;
dsDMA_Start : out std_logic;
dsDMA_Stop : out std_logic;
dsDMA_Start2 : out std_logic;
dsDMA_Stop2 : out std_logic;
dsDMA_Channel_Rst : out std_logic;
dsDMA_Cmd_Ack : in std_logic;
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : in std_logic;
us_DMA_Bytes : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
DMA_us_PA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : out std_logic;
us_MWr_Param_Vec : out std_logic_vector(6-1 downto 0);
DMA_us_Status : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : in std_logic;
-- DMA_us_Busy : IN std_logic;
DMA_us_Tout : in std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : out std_logic;
usBDA_is_64b : out std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : out std_logic;
usLeng_Lo7b_True : out std_logic;
usDMA_Start : out std_logic;
usDMA_Stop : out std_logic;
usDMA_Start2 : out std_logic;
usDMA_Stop2 : out std_logic;
usDMA_Channel_Rst : out std_logic;
usDMA_Cmd_Ack : in std_logic;
-- Reset signals
MRd_Channel_Rst : out std_logic;
Tx_Reset : out std_logic;
-- to Interrupt module
Sys_IRQ : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System error and info
Tx_TimeOut : in std_logic;
Tx_wb_TimeOut : in std_logic;
Msg_Routing : out std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
pcie_link_width : in std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
cfg_dcommand : in std_logic_vector(16-1 downto 0);
ddr_sdram_ready : in std_logic;
-- Interrupt Generation Signals
IG_Reset : out std_logic;
IG_Host_Clear : out std_logic;
IG_Latency : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : in std_logic;
-- SDRAM and Wishbone paging registers
sdram_pg : out std_logic_vector(31 downto 0);
wb_pg : out std_logic_vector(31 downto 0);
-- Common interface
user_clk : in std_logic;
user_lnk_up : in std_logic;
user_reset : in std_logic
);
end component Regs_Group;
-- DDR write port
signal DDR_wr_sof_A : std_logic;
signal DDR_wr_eof_A : std_logic;
signal DDR_wr_v_A : std_logic;
signal DDR_wr_Shift_A : std_logic;
signal DDR_wr_Mask_A : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_B : std_logic;
signal DDR_wr_eof_B : std_logic;
signal DDR_wr_v_B : std_logic;
signal DDR_wr_Shift_B : std_logic;
signal DDR_wr_Mask_B : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_B : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
:= (others => '0');
signal DDR_wr_sof_A_r1 : std_logic;
signal DDR_wr_eof_A_r1 : std_logic;
signal DDR_wr_v_A_r1 : std_logic;
signal DDR_wr_Shift_A_r1 : std_logic;
signal DDR_wr_Mask_A_r1 : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_A_r2 : std_logic;
signal DDR_wr_eof_A_r2 : std_logic;
signal DDR_wr_v_A_r2 : std_logic;
signal DDR_wr_Shift_A_r2 : std_logic;
signal DDR_wr_Mask_A_r2 : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A_r2 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_A_r3 : std_logic;
signal DDR_wr_eof_A_r3 : std_logic;
signal DDR_wr_v_A_r3 : std_logic;
signal DDR_wr_Shift_A_r3 : std_logic;
signal DDR_wr_Mask_A_r3 : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A_r3 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- eb FIFO read enable
signal wb_FIFO_RdEn_i : std_logic;
-- Flow control signals
signal us_FC_stop : std_logic;
signal us_Last_sof : std_logic;
signal us_Last_eof : std_logic;
-- Signals between Tx_Transact and Rx_Transact
signal pioCplD_Req : std_logic;
signal pioCplD_RE : std_logic;
signal pioCplD_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- MRd-downstream packet Channel
signal dsMRd_Req : std_logic;
signal dsMRd_RE : std_logic;
signal dsMRd_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Upstream MWr Channel
signal usTlp_Req : std_logic;
signal usTlp_RE : std_logic;
signal usTlp_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Irpt Channel
signal Irpt_Req : std_logic;
signal Irpt_RE : std_logic;
signal Irpt_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- SDRAM and Wishbone paging registers
signal sdram_pg_i : std_logic_vector(31 downto 0);
signal wb_pg_i : std_logic_vector(31 downto 0);
-- Registers Write Port
signal Regs_WrEnA : std_logic;
signal Regs_WrMaskA : std_logic_vector(2-1 downto 0);
signal Regs_WrAddrA : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrEnB : std_logic;
signal Regs_WrMaskB : std_logic_vector(2-1 downto 0);
signal Regs_WrAddrB : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Dex parameters to downstream DMA
signal DMA_ds_PA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BDA_eq_Null : std_logic;
signal DMA_ds_Status : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Done_i : std_logic;
signal DMA_ds_Busy_i : std_logic;
signal DMA_ds_Tout : std_logic;
-- Calculation in advance, for better timing
signal dsHA_is_64b : std_logic;
signal dsBDA_is_64b : std_logic;
-- Calculation in advance, for better timing
signal dsLeng_Hi19b_True : std_logic;
signal dsLeng_Lo7b_True : std_logic;
-- Downstream Control Signals
signal dsDMA_Start : std_logic;
signal dsDMA_Stop : std_logic;
signal dsDMA_Start2 : std_logic;
signal dsDMA_Stop2 : std_logic;
signal dsDMA_Cmd_Ack : std_logic;
signal dsDMA_Channel_Rst : std_logic;
-- Dex parameters to upstream DMA
signal DMA_us_PA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_BDA_eq_Null : std_logic;
signal us_MWr_Param_Vec : std_logic_vector(6-1 downto 0);
signal DMA_us_Status : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Done_i : std_logic;
signal DMA_us_Busy_i : std_logic;
signal DMA_us_Tout : std_logic;
-- Calculation in advance, for better timing
signal usHA_is_64b : std_logic;
signal usBDA_is_64b : std_logic;
-- Calculation in advance, for better timing
signal usLeng_Hi19b_True : std_logic;
signal usLeng_Lo7b_True : std_logic;
-- Upstream Control Signals
signal usDMA_Start : std_logic;
signal usDMA_Stop : std_logic;
signal usDMA_Start2 : std_logic;
signal usDMA_Stop2 : std_logic;
signal usDMA_Cmd_Ack : std_logic;
signal usDMA_Channel_Rst : std_logic;
-- MRd Channel Reset
signal MRd_Channel_Rst : std_logic;
-- Tx module Reset
signal Tx_Reset : std_logic;
-- Tx time out
signal Tx_TimeOut : std_logic;
signal Tx_wb_TimeOut : std_logic;
-- Registers read port
signal Regs_RdAddr : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register to Interrupt module
signal Sys_IRQ : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Message routing method
signal Msg_Routing : std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
-- Interrupt Generation Signals
signal IG_Reset : std_logic;
signal IG_Host_Clear : std_logic;
signal IG_Latency : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Asserting : std_logic;
begin
DDR_wr_v <= DDR_wr_v_i;
DDR_wr_sof <= DDR_wr_sof_i;
DDR_wr_eof <= DDR_wr_eof_i;
DDR_wr_Shift <= DDR_wr_Shift_i;
DDR_wr_Mask <= DDR_wr_Mask_i;
DDR_wr_din <= DDR_wr_din_i;
wb_FIFO_re <= wb_FIFO_RdEn_i;
wb_timeout <= Tx_wb_TimeOut;
-- -------------------------------------------------------
-- Delay DDR write port A for 2 cycles
--
SynDelay_DDR_write_PIO :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
DDR_wr_v_A_r1 <= DDR_wr_v_A;
DDR_wr_sof_A_r1 <= DDR_wr_sof_A;
DDR_wr_eof_A_r1 <= DDR_wr_eof_A;
DDR_wr_Shift_A_r1 <= DDR_wr_Shift_A;
DDR_wr_Mask_A_r1 <= DDR_wr_Mask_A;
DDR_wr_din_A_r1 <= DDR_wr_din_A;
DDR_wr_v_A_r2 <= DDR_wr_v_A_r1;
DDR_wr_sof_A_r2 <= DDR_wr_sof_A_r1;
DDR_wr_eof_A_r2 <= DDR_wr_eof_A_r1;
DDR_wr_Shift_A_r2 <= DDR_wr_Shift_A_r1;
DDR_wr_Mask_A_r2 <= DDR_wr_Mask_A_r1;
DDR_wr_din_A_r2 <= DDR_wr_din_A_r1;
DDR_wr_v_A_r3 <= DDR_wr_v_A_r2;
DDR_wr_sof_A_r3 <= DDR_wr_sof_A_r2;
DDR_wr_eof_A_r3 <= DDR_wr_eof_A_r2;
DDR_wr_Shift_A_r3 <= DDR_wr_Shift_A_r2;
DDR_wr_Mask_A_r3 <= DDR_wr_Mask_A_r2;
DDR_wr_din_A_r3 <= DDR_wr_din_A_r2;
end if;
end process;
-- -------------------------------------------------------
-- DDR writes: DDR Writes
--
SynProc_DDR_write :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
DDR_wr_v_i <= DDR_wr_v_A_r3 or DDR_wr_v_B;
if DDR_wr_v_A_r3 = '1' then
DDR_wr_sof_i <= DDR_wr_sof_A_r3;
DDR_wr_eof_i <= DDR_wr_eof_A_r3;
DDR_wr_Shift_i <= DDR_wr_Shift_A_r3;
DDR_wr_Mask_i <= DDR_wr_Mask_A_r3;
DDR_wr_din_i <= DDR_wr_din_A_r3;
elsif DDR_wr_v_B = '1' then
DDR_wr_sof_i <= DDR_wr_sof_B;
DDR_wr_eof_i <= DDR_wr_eof_B;
DDR_wr_Shift_i <= DDR_wr_Shift_B;
DDR_wr_Mask_i <= DDR_wr_Mask_B;
DDR_wr_din_i <= DDR_wr_din_B;
else
DDR_wr_sof_i <= DDR_wr_sof_i;
DDR_wr_eof_i <= DDR_wr_eof_i;
DDR_wr_Shift_i <= DDR_wr_Shift_i;
DDR_wr_Mask_i <= DDR_wr_Mask_i;
DDR_wr_din_i <= DDR_wr_din_i;
end if;
end if;
end process;
-- Rx TLP interface
rx_Itf :
rx_Transact
port map(
-- Common ports
user_clk => user_clk, -- IN std_logic,
user_reset => user_reset, -- IN std_logic,
user_lnk_up => user_lnk_up, -- IN std_logic,
-- Transaction receive interface
m_axis_rx_tlast => m_axis_rx_tlast, -- IN std_logic,
m_axis_rx_tdata => m_axis_rx_tdata, -- IN std_logic_vector(31 downto 0),
m_axis_rx_tkeep => m_axis_rx_tkeep, -- IN STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_rx_terrfwd => m_axis_rx_terrfwd, -- IN std_logic,
m_axis_rx_tvalid => m_axis_rx_tvalid, -- IN std_logic,
m_axis_rx_tready => m_axis_rx_tready, -- OUT std_logic,
rx_np_ok => rx_np_ok, -- OUT std_logic,
rx_np_req => rx_np_req, -- out std_logic;
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit, -- IN std_logic_vector(6 downto 0),
-- trn_rfc_ph_av => trn_rfc_ph_av, -- IN std_logic_vector(7 downto 0),
-- trn_rfc_pd_av => trn_rfc_pd_av, -- IN std_logic_vector(11 downto 0),
-- trn_rfc_nph_av => trn_rfc_nph_av, -- IN std_logic_vector(7 downto 0),
-- trn_rfc_npd_av => trn_rfc_npd_av, -- IN std_logic_vector(11 downto 0),
-- trn_rfc_cplh_av => trn_rfc_cplh_av, -- IN std_logic_vector(7 downto 0),
-- trn_rfc_cpld_av => trn_rfc_cpld_av, -- IN std_logic_vector(11 downto 0),
-- MRd Channel
pioCplD_Req => pioCplD_Req, -- OUT std_logic;
pioCplD_RE => pioCplD_RE, -- IN std_logic;
pioCplD_Qout => pioCplD_Qout, -- OUT std_logic_vector(96 downto 0);
-- downstream MRd Channel
dsMRd_Req => dsMRd_Req, -- OUT std_logic;
dsMRd_RE => dsMRd_RE, -- IN std_logic;
dsMRd_Qout => dsMRd_Qout, -- OUT std_logic_vector(96 downto 0);
-- Upstream MWr/MRd Channel
usTlp_Req => usTlp_Req, -- OUT std_logic;
usTlp_RE => usTlp_RE, -- IN std_logic;
usTlp_Qout => usTlp_Qout, -- OUT std_logic_vector(96 downto 0);
us_FC_stop => us_FC_stop, -- IN std_logic;
us_Last_sof => us_Last_sof, -- IN std_logic;
us_Last_eof => us_Last_eof, -- IN std_logic;
-- Irpt Channel
Irpt_Req => Irpt_Req, -- OUT std_logic;
Irpt_RE => Irpt_RE, -- IN std_logic;
Irpt_Qout => Irpt_Qout, -- OUT std_logic_vector(96 downto 0);
-- SDRAM and Wishbone pages
sdram_pg => sdram_pg_i,
wb_pg => wb_pg_i,
-- Interrupt Interface
cfg_interrupt => cfg_interrupt , -- OUT std_logic;
cfg_interrupt_rdy => cfg_interrupt_rdy , -- IN std_logic;
cfg_interrupt_mmenable => cfg_interrupt_mmenable , -- IN std_logic_VECTOR(2 downto 0);
cfg_interrupt_msienable => cfg_interrupt_msienable , -- IN std_logic;
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_di => cfg_interrupt_di , -- OUT std_logic_VECTOR(7 downto 0);
cfg_interrupt_do => cfg_interrupt_do , -- IN std_logic_VECTOR(7 downto 0);
cfg_interrupt_assert => cfg_interrupt_assert , -- OUT std_logic;
-- Wishbone write port
wb_FIFO_we => wb_FIFO_we , -- OUT std_logic;
wb_FIFO_wsof => wb_FIFO_wsof , -- OUT std_logic;
wb_FIFO_weof => wb_FIFO_weof , -- OUT std_logic;
wb_FIFO_din => wb_FIFO_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_FIFO_full => wb_FIFO_full,
wb_FIFO_Empty => wb_FIFO_Empty , -- IN std_logic;
wb_FIFO_Reading => wb_FIFO_RdEn_i , -- IN std_logic;
-- Register Write
Regs_WrEn0 => Regs_WrEnA , -- OUT std_logic;
Regs_WrMask0 => Regs_WrMaskA , -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr0 => Regs_WrAddrA , -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin0 => Regs_WrDinA , -- OUT std_logic_vector(32-1 downto 0);
Regs_WrEn1 => Regs_WrEnB , -- OUT std_logic;
Regs_WrMask1 => Regs_WrMaskB , -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr1 => Regs_WrAddrB , -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin1 => Regs_WrDinB , -- OUT std_logic_vector(32-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add => ds_DMA_Bytes_Add , -- OUT std_logic;
ds_DMA_Bytes => ds_DMA_Bytes , -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers
DMA_ds_PA => DMA_ds_PA , -- IN std_logic_vector(63 downto 0);
DMA_ds_HA => DMA_ds_HA , -- IN std_logic_vector(63 downto 0);
DMA_ds_BDA => DMA_ds_BDA , -- IN std_logic_vector(63 downto 0);
DMA_ds_Length => DMA_ds_Length , -- IN std_logic_vector(31 downto 0);
DMA_ds_Control => DMA_ds_Control , -- IN std_logic_vector(31 downto 0);
dsDMA_BDA_eq_Null => dsDMA_BDA_eq_Null , -- IN std_logic;
DMA_ds_Status => DMA_ds_Status , -- OUT std_logic_vector(31 downto 0);
DMA_ds_Done => DMA_ds_Done_i , -- OUT std_logic;
DMA_ds_Busy => DMA_ds_Busy_i , -- OUT std_logic;
DMA_ds_Tout => DMA_ds_Tout , -- OUT std_logic;
dsHA_is_64b => dsHA_is_64b , -- IN std_logic;
dsBDA_is_64b => dsBDA_is_64b , -- IN std_logic;
dsLeng_Hi19b_True => dsLeng_Hi19b_True , -- IN std_logic;
dsLeng_Lo7b_True => dsLeng_Lo7b_True , -- IN std_logic;
dsDMA_Start => dsDMA_Start , -- IN std_logic;
dsDMA_Stop => dsDMA_Stop , -- IN std_logic;
dsDMA_Start2 => dsDMA_Start2 , -- IN std_logic;
dsDMA_Stop2 => dsDMA_Stop2 , -- IN std_logic;
dsDMA_Channel_Rst => dsDMA_Channel_Rst , -- IN std_logic;
dsDMA_Cmd_Ack => dsDMA_Cmd_Ack , -- OUT std_logic;
DMA_us_PA => DMA_us_PA , -- IN std_logic_vector(63 downto 0);
DMA_us_HA => DMA_us_HA , -- IN std_logic_vector(63 downto 0);
DMA_us_BDA => DMA_us_BDA , -- IN std_logic_vector(63 downto 0);
DMA_us_Length => DMA_us_Length , -- IN std_logic_vector(31 downto 0);
DMA_us_Control => DMA_us_Control , -- IN std_logic_vector(31 downto 0);
usDMA_BDA_eq_Null => usDMA_BDA_eq_Null , -- IN std_logic;
us_MWr_Param_Vec => us_MWr_Param_Vec , -- IN std_logic_vector(6-1 downto 0);
DMA_us_Status => DMA_us_Status , -- OUT std_logic_vector(31 downto 0);
DMA_us_Done => DMA_us_Done_i , -- OUT std_logic;
DMA_us_Busy => DMA_us_Busy_i , -- OUT std_logic;
DMA_us_Tout => DMA_us_Tout , -- OUT std_logic;
usHA_is_64b => usHA_is_64b , -- IN std_logic;
usBDA_is_64b => usBDA_is_64b , -- IN std_logic;
usLeng_Hi19b_True => usLeng_Hi19b_True , -- IN std_logic;
usLeng_Lo7b_True => usLeng_Lo7b_True , -- IN std_logic;
usDMA_Start => usDMA_Start , -- IN std_logic;
usDMA_Stop => usDMA_Stop , -- IN std_logic;
usDMA_Start2 => usDMA_Start2 , -- IN std_logic;
usDMA_Stop2 => usDMA_Stop2 , -- IN std_logic;
usDMA_Channel_Rst => usDMA_Channel_Rst , -- IN std_logic;
usDMA_Cmd_Ack => usDMA_Cmd_Ack , -- OUT std_logic;
-- Reset signals
MRd_Channel_Rst => MRd_Channel_Rst , -- IN std_logic;
-- to Interrupt module
Sys_IRQ => Sys_IRQ , -- IN std_logic_vector(31 downto 0);
IG_Reset => IG_Reset ,
IG_Host_Clear => IG_Host_Clear ,
IG_Latency => IG_Latency ,
IG_Num_Assert => IG_Num_Assert ,
IG_Num_Deassert => IG_Num_Deassert ,
IG_Asserting => IG_Asserting ,
-- DDR write port
DDR_wr_sof_A => DDR_wr_sof_A , -- OUT std_logic;
DDR_wr_eof_A => DDR_wr_eof_A , -- OUT std_logic;
DDR_wr_v_A => DDR_wr_v_A , -- OUT std_logic;
DDR_wr_Shift_A => DDR_wr_Shift_A , -- OUT std_logic;
DDR_wr_Mask_A => DDR_wr_Mask_A , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_A => DDR_wr_din_A , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_sof_B => DDR_wr_sof_B , -- OUT std_logic;
DDR_wr_eof_B => DDR_wr_eof_B , -- OUT std_logic;
DDR_wr_v_B => DDR_wr_v_B , -- OUT std_logic;
DDR_wr_Shift_B => DDR_wr_Shift_B , -- OUT std_logic;
DDR_wr_Mask_B => DDR_wr_Mask_B , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_B => DDR_wr_din_B , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
-- Additional
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(15 downto 0)
localID => localID -- IN std_logic_vector(15 downto 0)
);
-- Tx TLP interface
tx_Itf :
tx_Transact
port map(
-- Common ports
user_clk => user_clk, -- IN std_logic,
user_reset => user_reset, -- IN std_logic,
user_lnk_up => user_lnk_up, -- IN std_logic,
-- Transaction
s_axis_tx_tlast => s_axis_tx_tlast, -- OUT std_logic,
s_axis_tx_tdata => s_axis_tx_tdata, -- OUT std_logic_vector(31 downto 0),
s_axis_tx_tkeep => s_axis_tx_tkeep, -- OUT STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tx_terrfwd => s_axis_tx_terrfwd, -- OUT std_logic,
s_axis_tx_tvalid => s_axis_tx_tvalid, -- OUT std_logic,
s_axis_tx_tready => s_axis_tx_tready, -- IN std_logic,
s_axis_tx_tdsc => s_axis_tx_tdsc, -- OUT std_logic,
tx_buf_av => tx_buf_av, -- IN std_logic_vector(6 downto 0),
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add => us_DMA_Bytes_Add, -- OUT std_logic;
us_DMA_Bytes => us_DMA_Bytes, -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- MRd Channel
pioCplD_Req => pioCplD_Req, -- IN std_logic;
pioCplD_RE => pioCplD_RE, -- OUT std_logic;
pioCplD_Qout => pioCplD_Qout, -- IN std_logic_vector(96 downto 0);
-- downstream MRd Channel
dsMRd_Req => dsMRd_Req, -- IN std_logic;
dsMRd_RE => dsMRd_RE, -- OUT std_logic;
dsMRd_Qout => dsMRd_Qout, -- IN std_logic_vector(96 downto 0);
-- Upstream MWr/MRd Channel
usTlp_Req => usTlp_Req, -- IN std_logic;
usTlp_RE => usTlp_RE, -- OUT std_logic;
usTlp_Qout => usTlp_Qout, -- IN std_logic_vector(96 downto 0);
us_FC_stop => us_FC_stop, -- OUT std_logic;
us_Last_sof => us_Last_sof, -- OUT std_logic;
us_Last_eof => us_Last_eof, -- OUT std_logic;
-- Irpt Channel
Irpt_Req => Irpt_Req, -- IN std_logic;
Irpt_RE => Irpt_RE, -- OUT std_logic;
Irpt_Qout => Irpt_Qout, -- IN std_logic_vector(96 downto 0);
-- Wishbone read command port
wb_rdc_sof => wb_rdc_sof, --out std_logic;
wb_rdc_v => wb_rdc_v, --out std_logic;
wb_rdc_din => wb_rdc_din, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full => wb_rdc_full, --in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re => wb_FIFO_RdEn_i, -- OUT std_logic;
wb_FIFO_empty => wb_FIFO_empty , -- IN std_logic;
wb_FIFO_qout => wb_FIFO_qout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers read
Regs_RdAddr => Regs_RdAddr, -- OUT std_logic_vector(15 downto 0);
Regs_RdQout => Regs_RdQout, -- IN std_logic_vector(31 downto 0);
-- Message routing method
Msg_Routing => Msg_Routing,
-- DDR read port
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
Tx_TimeOut => Tx_TimeOut, -- OUT std_logic;
Tx_wb_TimeOut => Tx_wb_TimeOut, -- OUT std_logic;
Tx_Reset => Tx_Reset, -- IN std_logic;
localID => localID -- IN std_logic_vector(15 downto 0)
);
-- ------------------------------------------------
-- Unified memory space
-- ------------------------------------------------
Memory_Space :
Regs_Group
port map(
-- Wishbone Buffer status + reset
wb_FIFO_Rst => wb_FIFO_Rst , -- OUT std_logic;
-- Registers
Regs_WrEnA => Regs_WrEnA , -- IN std_logic;
Regs_WrMaskA => Regs_WrMaskA , -- IN std_logic_vector(2-1 downto 0);
Regs_WrAddrA => Regs_WrAddrA , -- IN std_logic_vector(16-1 downto 0);
Regs_WrDinA => Regs_WrDinA , -- IN std_logic_vector(32-1 downto 0);
Regs_WrEnB => Regs_WrEnB , -- IN std_logic;
Regs_WrMaskB => Regs_WrMaskB , -- IN std_logic_vector(2-1 downto 0);
Regs_WrAddrB => Regs_WrAddrB , -- IN std_logic_vector(16-1 downto 0);
Regs_WrDinB => Regs_WrDinB , -- IN std_logic_vector(32-1 downto 0);
Regs_RdAddr => Regs_RdAddr , -- IN std_logic_vector(15 downto 0);
Regs_RdQout => Regs_RdQout , -- OUT std_logic_vector(31 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add => ds_DMA_Bytes_Add , -- IN std_logic;
ds_DMA_Bytes => ds_DMA_Bytes , -- IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Register values
DMA_ds_PA => DMA_ds_PA , -- OUT std_logic_vector(63 downto 0);
DMA_ds_HA => DMA_ds_HA , -- OUT std_logic_vector(63 downto 0);
DMA_ds_BDA => DMA_ds_BDA , -- OUT std_logic_vector(63 downto 0);
DMA_ds_Length => DMA_ds_Length , -- OUT std_logic_vector(31 downto 0);
DMA_ds_Control => DMA_ds_Control , -- OUT std_logic_vector(31 downto 0);
dsDMA_BDA_eq_Null => dsDMA_BDA_eq_Null , -- OUT std_logic;
DMA_ds_Status => DMA_ds_Status , -- IN std_logic_vector(31 downto 0);
DMA_ds_Done => DMA_ds_Done_i , -- IN std_logic;
DMA_ds_Tout => DMA_ds_Tout , -- IN std_logic;
dsHA_is_64b => dsHA_is_64b , -- OUT std_logic;
dsBDA_is_64b => dsBDA_is_64b , -- OUT std_logic;
dsLeng_Hi19b_True => dsLeng_Hi19b_True , -- OUT std_logic;
dsLeng_Lo7b_True => dsLeng_Lo7b_True , -- OUT std_logic;
dsDMA_Start => dsDMA_Start , -- OUT std_logic;
dsDMA_Stop => dsDMA_Stop , -- OUT std_logic;
dsDMA_Start2 => dsDMA_Start2 , -- OUT std_logic;
dsDMA_Stop2 => dsDMA_Stop2 , -- OUT std_logic;
dsDMA_Channel_Rst => dsDMA_Channel_Rst , -- OUT std_logic;
dsDMA_Cmd_Ack => dsDMA_Cmd_Ack , -- IN std_logic;
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add => us_DMA_Bytes_Add , -- IN std_logic;
us_DMA_Bytes => us_DMA_Bytes , -- IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
DMA_us_PA => DMA_us_PA , -- OUT std_logic_vector(63 downto 0);
DMA_us_HA => DMA_us_HA , -- OUT std_logic_vector(63 downto 0);
DMA_us_BDA => DMA_us_BDA , -- OUT std_logic_vector(63 downto 0);
DMA_us_Length => DMA_us_Length , -- OUT std_logic_vector(31 downto 0);
DMA_us_Control => DMA_us_Control , -- OUT std_logic_vector(31 downto 0);
usDMA_BDA_eq_Null => usDMA_BDA_eq_Null , -- OUT std_logic;
us_MWr_Param_Vec => us_MWr_Param_Vec , -- OUT std_logic_vector(6-1 downto 0);
DMA_us_Status => DMA_us_Status , -- IN std_logic_vector(31 downto 0);
DMA_us_Done => DMA_us_Done_i , -- IN std_logic;
DMA_us_Tout => DMA_us_Tout , -- IN std_logic;
usHA_is_64b => usHA_is_64b , -- OUT std_logic;
usBDA_is_64b => usBDA_is_64b , -- OUT std_logic;
usLeng_Hi19b_True => usLeng_Hi19b_True , -- OUT std_logic;
usLeng_Lo7b_True => usLeng_Lo7b_True , -- OUT std_logic;
usDMA_Start => usDMA_Start , -- OUT std_logic;
usDMA_Stop => usDMA_Stop , -- OUT std_logic;
usDMA_Start2 => usDMA_Start2 , -- OUT std_logic;
usDMA_Stop2 => usDMA_Stop2 , -- OUT std_logic;
usDMA_Channel_Rst => usDMA_Channel_Rst , -- OUT std_logic;
usDMA_Cmd_Ack => usDMA_Cmd_Ack , -- IN std_logic;
-- Reset signals
MRd_Channel_Rst => MRd_Channel_Rst , -- OUT std_logic;
Tx_Reset => Tx_Reset , -- OUT std_logic;
-- to Interrupt module
Sys_IRQ => Sys_IRQ , -- OUT std_logic_vector(31 downto 0);
-- System error and info
Tx_TimeOut => Tx_TimeOut ,
Tx_wb_TimeOut => Tx_wb_TimeOut ,
Msg_Routing => Msg_Routing ,
pcie_link_width => pcie_link_width ,
cfg_dcommand => cfg_dcommand ,
ddr_sdram_ready => DDR_Ready,
-- Interrupt Generation Signals
IG_Reset => IG_Reset ,
IG_Host_Clear => IG_Host_Clear ,
IG_Latency => IG_Latency ,
IG_Num_Assert => IG_Num_Assert ,
IG_Num_Deassert => IG_Num_Deassert ,
IG_Asserting => IG_Asserting ,
-- SDRAM and Wishbone paging signals
sdram_pg => sdram_pg_i,
wb_pg => wb_pg_i,
-- Common
user_clk => user_clk , -- IN std_logic;
user_lnk_up => user_lnk_up , -- IN std_logic,
user_reset => user_reset -- IN std_logic;
);
end architecture Behavioral;
|
lgpl-3.0
|
7713bf2e7b8ae86143539b1576ba8ab4
| 0.567797 | 3.044897 | false | false | false | false |
peteg944/music-fpga
|
Experimental/RainbowMatrix and Partial Spectrum/fpga_top.vhd
| 1 | 4,762 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fpga_top is
Port ( clk : in STD_LOGIC;
led : out STD_LOGIC;
bluetooth_rxd : out STD_LOGIC;
bluetooth_txd : in STD_LOGIC;
display_rgb1 : out STD_LOGIC_VECTOR (2 downto 0);
display_rgb2 : out STD_LOGIC_VECTOR (2 downto 0);
display_addr : out STD_LOGIC_VECTOR (3 downto 0);
display_clk : out STD_LOGIC;
display_oe : out STD_LOGIC;
display_lat : out STD_LOGIC;
usb_rxd : out STD_LOGIC;
usb_txd : in STD_LOGIC;
height : in STD_LOGIC_VECTOR (3 downto 0);
mode : in STD_LOGIC;
on_off : in STD_LOGIC;
sysclk : in STD_LOGIC;
pll_locked : in STD_LOGIC;
xn_index : in STD_LOGIC_VECTOR (7 downto 0)
);
end fpga_top;
architecture rtl of fpga_top is
--component pll
-- port
-- (-- Clock in ports
-- CLK_IN : in std_logic;
-- -- Clock out ports
-- CLK_OUT1 : out std_logic;
-- CLK_OUT2 : out std_logic;
-- -- Status and control signals
-- RESET : in std_logic;
-- LOCKED : out std_logic
-- );
--end component;
component uart_rx
generic (
log2_oversampling : integer := 7);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end component;
component display_control
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
display_ena : in STD_LOGIC;
ram_data : in STD_LOGIC_VECTOR (47 downto 0);
ram_address : out STD_LOGIC_VECTOR ( 8 downto 0);
display_rgb1 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_rgb2 : out STD_LOGIC_VECTOR ( 2 downto 0);
display_addr : out STD_LOGIC_VECTOR ( 3 downto 0);
display_clk : out STD_LOGIC;
display_oe : out STD_LOGIC;
display_lat : out STD_LOGIC);
end component;
component animationV
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
height : in STD_LOGIC_VECTOR ( 3 downto 0);
ram_address : in STD_LOGIC_VECTOR ( 8 downto 0);
ram_data : out STD_LOGIC_VECTOR (47 downto 0);
mode : in STD_LOGIC;
xn_index : in STD_LOGIC_VECTOR (7 downto 0);
on_off : in STD_LOGIC);
end component;
--signal sysclk : std_logic;
signal uart_clk : std_logic;
--signal pll_locked : std_logic;
signal rst : std_logic;
signal rgb_addr : std_logic_vector(8 downto 0);
signal rgb_data : std_logic_vector(47 downto 0);
signal rgb_frame : std_logic;
signal uart_active : std_logic;
signal uart_data : std_logic_vector(47 downto 0);
signal anim_data : std_logic_vector(47 downto 0);
signal gnd0 : std_logic := '0';
signal vcc0 : std_logic := '1';
--signal height : std_logic_vector(3 downto 0) := "0011";
begin
--led <= pll_locked and rgb_frame;
rst <= not pll_locked;
bluetooth_rxd <= '1';
usb_rxd <= '1';
--pll_inst : pll
-- port map
-- (-- Clock in ports
-- CLK_IN => clk,
-- -- Clock out ports
-- CLK_OUT1 => sysclk,
-- CLK_OUT2 => uart_clk,
-- -- Status and control signals
-- RESET => gnd0,
-- LOCKED => pll_locked);
rx_i : uart_rx
generic map (
log2_oversampling => 7)
port map (
RST => rst,
RDCLK => sysclk,
CLKOSX => uart_clk,
--RXD => bluetooth_txd,
RXD => usb_txd,
RDADDR => rgb_addr,
RDDATA => uart_data,
FRAMESEL => rgb_frame);
disp_i : display_control
port map (
clk => sysclk,
rst => rst,
display_ena => vcc0,
ram_data => rgb_data,
ram_address => rgb_addr,
display_rgb1 => display_rgb1,
display_rgb2 => display_rgb2,
display_addr => display_addr,
display_clk => display_clk,
display_oe => display_oe,
display_lat => display_lat);
anim_i : animationV
port map (
clk => sysclk,
rst => rst,
height => height,
ram_address => rgb_addr,
ram_data => anim_data,
mode => mode,
xn_index => xn_index,
on_off => on_off);
--rgb_data <= uart_data when (uart_active = '1') else anim_data;
rgb_data <= anim_data;
uart_proc : process (rst, sysclk)
begin
if rst = '1' then
uart_active <= '1';
elsif rising_edge(sysclk) then
if rgb_frame = '0' then
uart_active <= '1';
end if;
end if;
end process uart_proc;
end rtl;
|
mit
|
9b813b0d532b350fd998195d5b9cb1be
| 0.541159 | 3.176785 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dly_ctrl.vhd
| 1 | 33,605 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_dly_ctrl.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Mon Jun 30 2008
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Multiplexing for all DQ/DQS/Capture and resynchronization clock
-- IODELAY elements
-- Scope of this module:
-- IODELAYs controlled:
-- 1. DQ (rdlvl/writes)
-- 2. DQS (wrlvl/phase detector)
-- 3. Capture clock (rdlvl/phase detector)
-- 4. Resync clock (rdlvl/phase detector)
-- Functions performed:
-- 1. Synchronization (from GCLK to BUFR domain)
-- 2. Multi-rank IODELAY lookup (NOT YET SUPPORTED)
-- NOTES:
-- 1. Per-bit DQ control not yet supported
-- 2. Multi-rank control not yet supported
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_dly_ctrl.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_dly_ctrl.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_dly_ctrl is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQ_WIDTH))
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
RANK_WIDTH : integer := 1; -- # of ranks of DRAM
nCWL : integer := 5; -- Write CAS latency (in clk cyc)
REG_CTRL : string := "OFF"; -- "ON" for registered DIMM
WRLVL : string := "ON"; -- Enable write leveling
PHASE_DETECT : string := "ON"; -- Enable read phase detector
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 0; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 0; -- # DQS groups in I/O column #4
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"000000000000000000000000000003020100";
-- DQS grps in col #1
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000007060504";
-- DQS grps in col #2
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
-- DQS grps in col #3
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DEBUG_PORT : string := "OFF" -- Enable debug port
);
port (
clk : in std_logic;
rst : in std_logic;
clk_rsync : in std_logic_vector(3 downto 0);
rst_rsync : in std_logic_vector(3 downto 0);
-- Operation status, control signals
wrlvl_done : in std_logic;
rdlvl_done : in std_logic_vector(1 downto 0);
pd_cal_done : in std_logic;
mc_data_sel : in std_logic;
mc_ioconfig : in std_logic_vector(RANK_WIDTH downto 0);
mc_ioconfig_en : in std_logic;
phy_ioconfig : in std_logic_vector(0 downto 0);
phy_ioconfig_en : in std_logic;
dqs_oe : in std_logic;
-- DQ, DQS IODELAY controls for write leveling
dlyval_wrlvl_dqs : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyval_wrlvl_dq : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
-- Capture Clock / Resync Clock IODELAY controls for read leveling
dlyce_rdlvl_cpt : in std_logic_vector((DQS_WIDTH-1) downto 0);
dlyinc_rdlvl_cpt : in std_logic;
dlyce_rdlvl_rsync : in std_logic_vector(3 downto 0);
dlyinc_rdlvl_rsync : in std_logic;
dlyval_rdlvl_dq : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyval_rdlvl_dqs : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
-- Phase detector IODELAY control for DQS, Capture Clock
dlyce_pd_cpt : in std_logic_vector((DQS_WIDTH-1) downto 0);
dlyinc_pd_cpt : in std_logic_vector((DQS_WIDTH-1) downto 0);
dlyval_pd_dqs : in std_logic_vector((5*DQS_WIDTH-1) downto 0);
-- IODELAY controls
dlyval_dqs : out std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyval_dq : out std_logic_vector((5*DQS_WIDTH-1) downto 0);
dlyrst_cpt : out std_logic;
dlyce_cpt : out std_logic_vector((DQS_WIDTH-1) downto 0);
dlyinc_cpt : out std_logic_vector((DQS_WIDTH-1) downto 0);
dlyrst_rsync : out std_logic;
dlyce_rsync : out std_logic_vector(3 downto 0);
dlyinc_rsync : out std_logic_vector(3 downto 0);
-- Debug Port
dbg_pd_off : in std_logic
);
end phy_dly_ctrl;
architecture trans of phy_dly_ctrl is
-- Type definitions
type dbg_ports1 is array (0 to (DQS_WIDTH-1)) of std_logic_vector(4 downto 0);
type dbg_ports2 is array (0 to (DQ_WIDTH-1)) of std_logic_vector(4 downto 0);
type dbg_ports3 is array (0 to 3) of std_logic_vector(4 downto 0);
signal dlyce_cpt_mux : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dlyce_rsync_mux : std_logic_vector(3 downto 0);
signal dlyinc_cpt_mux : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dlyinc_rsync_mux : std_logic_vector(3 downto 0);
signal dqs_oe_r : std_logic;
signal dqs_wr : std_logic;
signal mux_ioconfig : std_logic_vector(0 downto 0);
signal mux_ioconfig_en : std_logic;
signal mux_rd_wr : std_logic;
signal mux_rd_wr_last_r : std_logic;
signal rd_wr_r : std_logic;
signal rd_wr_rsync_r : std_logic_vector(3 downto 0);
signal rd_wr_rsync_tmp_r : std_logic_vector(3 downto 0);
signal rd_wr_rsync_tmp_r1 : std_logic_vector(3 downto 0);
signal dlyce_rdlvl_cpt_0_r : std_logic;
signal dlyce_cpt_iodelay : std_logic_vector((DQS_WIDTH-1) downto 0);
-- Declare intermediate signals for referenced outputs
signal dlyce_cpt_xhdl1 : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dlyinc_cpt_xhdl3 : std_logic_vector((DQS_WIDTH-1) downto 0);
signal dlyrst_cpt_xhdl5 : std_logic;
signal dlyrst_rsync_xhdl6 : std_logic;
signal dlyce_rsync_xhdl2 : std_logic_vector(3 downto 0);
signal dlyinc_rsync_xhdl4 : std_logic_vector(3 downto 0);
signal dlyval_dqs_xhdl8 : std_logic_vector((5*DQS_WIDTH-1) downto 0);
signal dlyval_dq_xhdl9 : std_logic_vector((5*DQS_WIDTH-1) downto 0);
begin
-- Drive the outputs with intermediate signals
dlyce_cpt <= dlyce_cpt_xhdl1;
dlyrst_cpt <= dlyrst_cpt_xhdl5;
dlyrst_rsync <= dlyrst_rsync_xhdl6;
dlyce_rsync <= dlyce_rsync_xhdl2;
dlyinc_rsync <= dlyinc_rsync_xhdl4;
dlyinc_cpt <= dlyinc_cpt_xhdl3;
dlyval_dqs <= dlyval_dqs_xhdl8;
dlyval_dq <= dlyval_dq_xhdl9;
--***************************************************************************
-- IODELAY RESET CONTROL:
-- RST for IODELAY is used to control parallel loading of IODELAY (dlyval)
-- For all IODELAYs where glitching of outputs is permitted, always assert
-- RST (i.e. control logic can change outputs without worrying about
-- synchronization of control bits causing output glitching). For all other
-- IODELAYs (CPT, RSYNC), only assert RST when DLYVAL is stable
--***************************************************************************
dlyrst_cpt_xhdl5 <= rst;
dlyrst_rsync_xhdl6 <= rst;
--***************************************************************************
-- IODELAY MUX CONTROL LOGIC AND CLOCK SYNCHRONIZATION
-- This logic determines the main MUX control logic for selecting what gets
-- fed to the IODELAY taps. Output signal is MUX_IOCFG = [0 for write, 1 for
-- read]. This logic is in the CLK domain, and needs to be synchronized to
-- each of the individual CLK_RSYNC[x] domains
--***************************************************************************
-- Select between either MC or PHY control
mux_ioconfig(0) <= mc_ioconfig(RANK_WIDTH) when (mc_data_sel = '1') else
phy_ioconfig(0);
mux_ioconfig_en <= mc_ioconfig_en when (mc_data_sel = '1') else
phy_ioconfig_en;
mux_rd_wr <= mux_ioconfig(0);
process (clk)
begin
if (clk'event and clk = '1') then
dqs_oe_r <= dqs_oe after TCQ*1 ps;
end if;
end process;
-- Generate indication when write is occurring - necessary to prevent
-- situation where a read request comes in on DFI before the current
-- write has been completed on the DDR bus - in that case, the IODELAY
-- value should remain at the write value until the write is completed
-- on the DDR bus.
process (dqs_oe, mux_rd_wr_last_r)
begin
dqs_wr <= mux_rd_wr_last_r or dqs_oe;
end process;
-- Store value of MUX_IOCONFIG when enable(latch) signal asserted
process (clk)
begin
if (clk'event and clk = '1') then
if (mux_ioconfig_en = '1') then
mux_rd_wr_last_r <= mux_rd_wr after TCQ*1 ps;
end if;
end if;
end process;
-- New value of MUX_IOCONFIG gets reflected right away as soon as
-- enable/latch signal is asserted. This signal indicates whether a
-- write or read is occurring (1 = write, 0 = read). Add dependence on
-- DQS_WR to account for pipelining - prevent read value from being
-- loaded until previous write is finished
process (clk)
begin
if (clk'event and clk = '1') then
if (mux_ioconfig_en = '1') then
if ((dqs_wr = '1') and (DRAM_TYPE = "DDR3")) then
rd_wr_r <= '1' after TCQ*1 ps;
else
rd_wr_r <= mux_rd_wr after TCQ*1 ps;
end if;
else
if ((dqs_wr = '1') and (DRAM_TYPE = "DDR3")) then
rd_wr_r <= '1' after TCQ*1 ps;
else
rd_wr_r <= mux_rd_wr after TCQ*1 ps;
end if;
end if;
end if;
end process;
-- Synchronize MUX control to each of the individual clock domains
gen_sync_rd_wr: for r_i in 0 to 3 generate
gen_cwl_ddr2: if (DRAM_TYPE = "DDR2") generate
gen_cwl_ddr2_ls_4: if (nCWL <= 3) generate
-- one less pipeline stage for cwl<= 3
process (clk_rsync(r_i))
begin
if (clk_rsync(r_i)'event and clk_rsync(r_i) = '1') then
rd_wr_rsync_tmp_r(r_i) <= rd_wr_r after TCQ*1 ps;
rd_wr_rsync_r(r_i) <= rd_wr_rsync_tmp_r(r_i) after TCQ*1 ps;
end if;
end process;
end generate;
gen_cwl_ddr2_gt_3: if (nCWL > 3) generate
process (clk_rsync(r_i))
begin
if (clk_rsync(r_i)'event and clk_rsync(r_i) = '1') then
rd_wr_rsync_tmp_r(r_i) <= rd_wr_r after TCQ*1 ps;
rd_wr_rsync_tmp_r1(r_i)<= rd_wr_rsync_tmp_r(r_i) after TCQ*1 ps;
rd_wr_rsync_r(r_i) <= rd_wr_rsync_tmp_r1(r_i) after TCQ*1 ps;
end if;
end process;
end generate;
end generate;
gen_cwl_5_ddr3: if (((nCWL = 5) or
((nCWL = 6) and (REG_CTRL = "ON"))) and
(DRAM_TYPE /= "DDR2")) generate
-- For CWL = 5, bypass one of the pipeline registers for speed
-- purposes (need to load IODELAY value as soon as possible on write,
-- time between IOCONFIG_EN and OSERDES.WC assertion is shorter than
-- for all other CWL values. Rely on built in registers in IODELAY to
-- reduce metastability?
-- NOTE: 2nd case added where we consider the case of registered
-- DIMM and an nCWL value (as passed to this module) of 6 to be
-- the same case, because the actual CWL value = 5 (as programmed
-- in the DRAM - see module phy_top for CWL_M adjustment) and more
-- importantly, the controller (MC) treats the CWL as 5 for bus
-- turnaround purposes, and on a WRITE->READ, it the extra clock
-- cycle is needed to program the new value of the IODELAY before
-- the read data is captured. Note that we may want to apply this
-- case as well for DDR2 registered DIMMs as well
process (clk_rsync(r_i))
begin
if (clk_rsync(r_i)'event and clk_rsync(r_i) = '1') then
rd_wr_rsync_r(r_i) <= rd_wr_r after TCQ*1 ps;
end if;
end process;
end generate;
gen_cwl_gt_5_ddr3: if ((not((nCWL = 5) or
((nCWL = 6) and (REG_CTRL = "ON")))) and
(DRAM_TYPE /= "DDR2")) generate
-- Otherwise, use two pipeline stages in CLK_RSYNC domain to
-- reduce metastability
process (clk_rsync(r_i))
begin
if (clk_rsync(r_i)'event and clk_rsync(r_i) = '1') then
rd_wr_rsync_tmp_r(r_i) <= rd_wr_r after TCQ*1 ps;
rd_wr_rsync_r(r_i) <= rd_wr_rsync_tmp_r(r_i) after TCQ*1 ps;
end if;
end process;
end generate;
end generate;
--***************************************************************************
-- IODELAY CE/INC MUX LOGIC
-- Increment/Enable MUX logic for Capture and Resynchronization clocks.
-- No synchronization of these signals to another clock domain is
-- required - the capture and resync clock IODELAY control ports are
-- clocked by CLK
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rdlvl_done(1) = '0') then
-- If read leveling not completed, rdlvl logic has control of capture
-- and resync clock adjustment IODELAYs
dlyce_cpt_mux <= dlyce_rdlvl_cpt after TCQ*1 ps;
dlyinc_cpt_mux <= (others => dlyinc_rdlvl_cpt) after TCQ*1 ps;
dlyce_rsync_mux <= dlyce_rdlvl_rsync after TCQ*1 ps;
dlyinc_rsync_mux <= (others => dlyinc_rdlvl_rsync) after TCQ*1 ps;
else
if ((PHASE_DETECT = "OFF") or ((DEBUG_PORT = "ON") and (dbg_pd_off = '1'))) then
-- If read phase detector is off, give control of CPT/RSYNC IODELAY
-- taps to the read leveling logic. Normally the read leveling logic
-- will not be changing the IODELAY values after initial calibration.
-- However, the debug port interface for changing the CPT/RSYNC
-- tap values does go through the PHY_RDLVL module - if the user
-- has this capability enabled, then that module will change the
-- IODELAY tap values. Note that use of the debug interface to change
-- the CPT/RSYNC tap values is limiting to changing the tap values
-- only when the read phase detector is turned off - otherwise, if
-- the read phase detector is on, it will simply "undo" any changes
-- to the tap count made via the debug port interface
dlyce_cpt_mux <= dlyce_rdlvl_cpt after TCQ*1 ps;
dlyinc_cpt_mux <= (others => dlyinc_rdlvl_cpt) after TCQ*1 ps;
dlyce_rsync_mux <= dlyce_rdlvl_rsync after TCQ*1 ps;
dlyinc_rsync_mux <= (others => dlyinc_rdlvl_rsync) after TCQ*1 ps;
else
-- Else read phase detector has control of capture/rsync phases
dlyce_cpt_mux <= dlyce_pd_cpt after TCQ*1 ps;
dlyinc_cpt_mux <= dlyinc_pd_cpt after TCQ*1 ps;
-- Phase detector does not control RSYNC - rely on RSYNC positioning
-- to be able to handle entire possible range that phase detector can
-- vary the capture clock IODELAY taps. In the future, we may want to
-- change to allow phase detector to vary RSYNC taps, if there is
-- insufficient margin to allow for a "static" scheme
dlyce_rsync_mux <= "0000" after TCQ*1 ps;
dlyinc_rsync_mux <= "0000" after TCQ*1 ps;
end if;
end if;
end if;
end process;
dlyce_cpt_xhdl1 <= dlyce_cpt_mux;
dlyinc_cpt_xhdl3 <= dlyinc_cpt_mux;
dlyce_rsync_xhdl2 <= dlyce_rsync_mux;
dlyinc_rsync_xhdl4 <= dlyinc_rsync_mux;
--***************************************************************************
-- SYNCHRONIZATION FOR CLK <-> CLK_RSYNC[X] DOMAINS
--***************************************************************************
--***************************************************************************
-- BIT STEERING EQUATIONS:
-- What follows are 4 generate loops - each of which handles "bit
-- steering" for each of the I/O columns. The first loop is always
-- instantited. The other 3 will only be instantiated depending on the
-- number of I/O columns used
--***************************************************************************
gen_c0: if (nDQS_COL0 > 0) generate
gen_loop_c0: for c0_i in 0 to (nDQS_COL0-1) generate
--*****************************************************************
-- DQ/DQS DLYVAL MUX LOGIC
-- This is the MUX logic to control the parallel load delay values for
-- DQ and DQS IODELAYs. There are up to 4 MUX's, one for each
-- CLK_RSYNC[x] clock domain. Each MUX can handle a variable amount
-- of DQ/DQS IODELAYs depending on the particular user pin assignment
-- (e.g. how many I/O columns are used, and the particular DQS groups
-- assigned to each I/O column). The MUX select (S), and input lines
-- (A,B) are configured:
-- S: MUX_IO_CFG_RSYNC[x]
-- A: value of DQ/DQS IODELAY from write leveling logic
-- B: value of DQ/DQS IODELAY from read phase detector logic (DQS) or
-- from read leveling logic (DQ). NOTE: The value of DQS may also
-- depend on the read leveling logic with per-bit deskew support.
-- This may require another level of MUX prior to this MUX
-- The parallel signals from the 3 possible sources (wrlvl, rdlvl, read
-- phase detector) are not synchronized to CLK_RSYNC< but also are not
-- timing critical - i.e. the IODELAY output can glitch briefly.
-- Therefore, there is no need to synchronize any of these sources
-- prior to the MUX (although a MAXDELAY constraint to ensure these
-- async paths aren't too long - they should be less than ~2 clock
-- cycles) should be added
--*****************************************************************
process (clk_rsync(0))
begin
if (clk_rsync(0)'event and clk_rsync(0) = '1') then
if (rd_wr_rsync_r(0) = '1') then
-- Load write IODELAY values
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) )
<= dlyval_wrlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) ) after TCQ*1 ps;
-- Write DQ IODELAY values are byte-wide only
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) )
<= dlyval_wrlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) ) after TCQ*1 ps;
else
-- Load read IODELAY values
if ((PHASE_DETECT = "ON") and (rdlvl_done(1) = '1')) then -- pd has control
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) )
<= dlyval_pd_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) ) after TCQ*1 ps;
else
-- Read Leveling logic has control of DQS (used only if IODELAY
-- taps are required for either per-bit or low freq calibration)
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) )
<= dlyval_rdlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) ) after TCQ*1 ps;
end if;
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) )
<= dlyval_rdlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) ) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
--*****************************************************************
-- The next 3 cases are for the other 3 banks. Conditionally include
-- only if multiple banks are supported. There's probably a better
-- way of instantiating these 3 other cases without taking up so much
-- space....
--*****************************************************************
-- I/O COLUMN #2
gen_c1: if (nDQS_COL1 > 0) generate
gen_loop_c1: for c1_i in 0 to (nDQS_COL1-1) generate
process (clk_rsync(1))
begin
if (clk_rsync(1)'event and clk_rsync(1) = '1') then
if (rd_wr_rsync_r(1) = '1') then
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) )
<= dlyval_wrlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) ) after TCQ*1 ps;
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) )
<= dlyval_wrlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) ) after TCQ*1 ps;
else
if ((PHASE_DETECT = "ON") and (rdlvl_done(1) = '1')) then -- pd has control
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) )
<= dlyval_pd_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) ) after TCQ*1 ps;
else
-- Read Leveling logic has control of DQS (used only if IODELAY
-- taps are required for either per-bit or low freq calibration)
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) )
<= dlyval_rdlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) ) after TCQ*1 ps;
end if;
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) )
<= dlyval_rdlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) ) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
-- I/O COLUMN #3
gen_c2: if (nDQS_COL2 > 0) generate
gen_loop_c2: for c2_i in 0 to (nDQS_COL2-1) generate
process (clk_rsync(2))
begin
if (clk_rsync(2)'event and clk_rsync(2) = '1') then
if (rd_wr_rsync_r(2) = '1') then
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) )
<= dlyval_wrlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) ) after TCQ*1 ps;
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) )
<= dlyval_wrlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) ) after TCQ*1 ps;
else
if ((PHASE_DETECT = "ON") and (rdlvl_done(1) = '1')) then -- pd has control
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) )
<= dlyval_pd_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) ) after TCQ*1 ps;
else
-- Read Leveling logic has control of DQS (used only if IODELAY
-- taps are required for either per-bit or low freq calibration)
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) )
<= dlyval_rdlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) ) after TCQ*1 ps;
end if;
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) )
<= dlyval_rdlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) ) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
-- I/O COLUMN #4
gen_c3: if (nDQS_COL3 > 0) generate
gen_loop_c3: for c3_i in 0 to (nDQS_COL3-1) generate
process (clk_rsync(3))
begin
if (clk_rsync(3)'event and clk_rsync(3) = '1') then
if (rd_wr_rsync_r(3) = '1') then
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) )
<= dlyval_wrlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) ) after TCQ*1 ps;
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) )
<= dlyval_wrlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) ) after TCQ*1 ps;
else
if ((PHASE_DETECT = "ON") and (rdlvl_done(1) = '1')) then -- pd has control
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) )
<= dlyval_pd_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) ) after TCQ*1 ps;
else
-- Read Leveling logic has control of DQS (used only if IODELAY
-- taps are required for either per-bit or low freq calibration)
dlyval_dqs_xhdl8( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) )
<= dlyval_rdlvl_dqs( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) ) after TCQ*1 ps;
end if;
dlyval_dq_xhdl9( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) )
<= dlyval_rdlvl_dq( (5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) + 4 downto
(5*TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) ) after TCQ*1 ps;
end if;
end if;
end process;
end generate;
end generate;
end trans;
|
lgpl-3.0
|
66820e3796e862ef0183892ece3c711f
| 0.549829 | 3.489616 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-de2/pll2.vhd
| 1 | 16,445 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll2.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll2 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END pll2;
ARCHITECTURE SYN OF pll2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 9,
clk0_duty_cycle => 50,
clk0_multiply_by => 8,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 16,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=pll2",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
630c3926bae8311ebb9d762eaf36486f
| 0.684646 | 3.277855 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/rx_MRd_Channel.vhd
| 1 | 20,501 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: abyszuk
--
-- Design Name:
-- Module Name: rx_MRd_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.30 - Ported to AXI and OHWR general-cores components 12.2013
--
-- Revision 1.20 - Literal assignments removed. 30.07.2007
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity rx_MRd_Transact is
port (
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
-- m_axis_rx_tready : OUT std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
sdram_pg : in std_logic_vector(31 downto 0);
wb_pg : in std_logic_vector(31 downto 0);
MRd_Type : in std_logic_vector(3 downto 0);
Tlp_straddles_4KB : in std_logic;
-- MRd Channel
pioCplD_Req : out std_logic;
pioCplD_RE : in std_logic;
pioCplD_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Channel reset (from MWr channel)
Channel_Rst : in std_logic;
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end entity rx_MRd_Transact;
architecture Behavioral of rx_MRd_Transact is
type RxMRdTrnStates is (ST_MRd_RESET
, ST_MRd_IDLE
, ST_MRd_HEAD2
, ST_MRd_Tail
);
-- State variables
signal RxMRdTrn_NextState : RxMRdTrnStates;
signal RxMRdTrn_State : RxMRdTrnStates;
-- trn_rx stubs
signal trn_rsof_n_i : std_logic;
signal in_packet_reg : std_logic;
signal m_axis_rx_tdata_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tbar_hit_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- delays
signal m_axis_rx_tdata_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tbar_hit_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- BAR encoded
signal Encoded_BAR_Index : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Reset
signal local_Reset : std_logic;
signal local_Reset_n : std_logic;
-- Output signals
-- signal m_axis_rx_tready_i : std_logic;
signal rx_np_ok_i : std_logic := '1';
signal rx_np_req_i : std_logic := '1';
-- Throttle
signal trn_rx_throttle : std_logic;
signal MRd_Has_3DW_Header : std_logic;
signal MRd_Has_4DW_Header : std_logic;
signal Tlp_is_Zero_Length : std_logic;
signal Illegal_Leng_on_FIFO : std_logic;
-- Signal with MRd channel FIFO
signal pioCplD_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_RE_i : std_logic;
signal pioCplD_we : std_logic;
signal pioCplD_empty_i : std_logic;
signal pioCplD_full : std_logic;
signal pioCplD_prog_Full : std_logic;
signal pioCplD_prog_full_r1 : std_logic;
signal pioCplD_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Request for output arbitration
signal pioCplD_Req_i : std_logic;
-- Busy/Done state bits generation
type FSM_Request is (
REQST_Idle
, REQST_1Read
, REQST_Decision
, REQST_nFIFO_Req
-- , REQST_Quantity
-- , REQST_FIFO_Req
);
signal FSM_REQ_pio : FSM_Request;
begin
-- positive reset and local
local_Reset <= user_reset or Channel_Rst;
local_reset_n <= not local_reset;
-- MRd channel buffer control
-- pioCplD_RE_i <= pioCplD_RE;
pioCplD_Qout <= pioCplD_Qout_i;
pioCplD_Req <= pioCplD_Req_i; -- and not FIFO_Reading;
-- Output to the core as handshaking
m_axis_rx_tdata_i <= m_axis_rx_tdata;
m_axis_rx_tbar_hit_i <= m_axis_rx_tbar_hit;
-- Output to the core as handshaking
rx_np_ok <= rx_np_ok_i;
rx_np_ok_i <= not pioCplD_prog_full_r1;
rx_np_req <= rx_np_req_i;
rx_np_req_i <= rx_np_ok_i;
-- ( m_axis_rx_tvalid seems never deasserted during packet)
trn_rx_throttle <= not m_axis_rx_tvalid; -- or m_axis_rx_tready_i;
-- ------------------------------------------------
-- Synchronous Delay: m_axis_rx_tdata + m_axis_rx_tbar_hit
--
Synch_Delay_m_axis_rx_tdata :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
m_axis_rx_tdata_r1 <= m_axis_rx_tdata_i;
m_axis_rx_tbar_hit_r1 <= m_axis_rx_tbar_hit_i;
end if;
end process;
-- ------------------------------------------------
-- States synchronous
--
Syn_RxTrn_States :
process (user_clk, local_Reset)
begin
if local_Reset = '1' then
RxMRdTrn_State <= ST_MRd_RESET;
elsif user_clk'event and user_clk = '1' then
RxMRdTrn_State <= RxMRdTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates :
process (
RxMRdTrn_State
, MRd_Type
, trn_rx_throttle
, rx_np_ok_i
)
begin
case RxMRdTrn_State is
when ST_MRd_RESET =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
when ST_MRd_IDLE =>
if rx_np_ok_i = '1' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when others =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when ST_MRd_HEAD2 =>
if trn_rx_throttle = '1' then
RxMRdTrn_NextState <= ST_MRd_HEAD2;
else
RxMRdTrn_NextState <= ST_MRd_Tail;
end if;
when ST_MRd_Tail => -- support back-to-back transactions
if rx_np_ok_i = '1' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when others =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when others =>
RxMRdTrn_NextState <= ST_MRd_RESET;
end case;
end process;
-- ------------------------------------------------
-- Synchronous calculation: Encoded_BAR_Index
--
Syn_Calc_Encoded_BAR_Index :
process (user_clk, local_Reset)
begin
if local_Reset = '1' then
Encoded_BAR_Index <= (others => '1');
elsif user_clk'event and user_clk = '1' then
if m_axis_rx_tbar_hit(0) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(1) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(1, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(2) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(2, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(3) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(3, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(4) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(4, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(5) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(5, C_ENCODE_BAR_NUMBER);
elsif m_axis_rx_tbar_hit(6) = '1' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(6, C_ENCODE_BAR_NUMBER);
else
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(7, C_ENCODE_BAR_NUMBER);
end if;
end if;
end process;
-- ----------------------------------------------------------------------------------
--
-- Synchronous output: MRd FIFO write port
--
-- PIO Channel Buffer (128-bit) definition:
-- Note: Type not shows in this buffer
--
-- 127 ~ xxx : Peripheral address
-- xxy ~ 97 : reserved
-- 96 : Zero-length
-- 95 : reserved
-- 94 : Valid
-- 93 ~ 68 : reserved
-- 67 ~ 65 : BAR number
-- 64 ~ 49 : Requester ID
-- 48 ~ 41 : Tag
-- 40 ~ 34 : Lower Address
-- 33 ~ 31 : Completion Status
-- 30 ~ 19 : Byte count
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
RxFSM_Output_pioCplD_WR :
process (user_clk, local_Reset)
begin
if local_Reset = '1' then
pioCplD_we <= '0';
pioCplD_din <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxMRdTrn_State is
when ST_MRd_HEAD2 =>
pioCplD_we <= '0';
if Illegal_Leng_on_FIFO = '1' then -- Cpl : unsupported request
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT) <= C_FMT3_NO_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT) <= "001";
else
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT) <= C_FMT3_WITH_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT) <= "000";
end if;
pioCplD_din(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT);
pioCplD_din(C_CHBUF_TD_BIT) <= '0';
pioCplD_din(C_CHBUF_EP_BIT) <= '0';
pioCplD_din(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT);
-- <= m_axis_rx_tdata_r1(C_TLP_ATTR_BIT_TOP) & C_NO_SNOOP; -- downto C_TLP_ATTR_BIT_BOT);
pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
pioCplD_din(C_CHBUF_QVALID_BIT) <= '1';
pioCplD_din(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT);
pioCplD_din(C_CHBUF_CPLD_TAG_BIT_TOP downto C_CHBUF_CPLD_TAG_BIT_BOT) <= m_axis_rx_tdata_r1(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT);
pioCplD_din(C_CHBUF_0LENG_BIT) <= Tlp_is_Zero_Length;
if Tlp_is_Zero_Length = '1' then
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT) <= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
else
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT) <= Encoded_BAR_Index;
end if;
when ST_MRd_Tail =>
if MRd_Has_4DW_Header = '1' then
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT+32 downto 0+32);
if m_axis_rx_tbar_hit_r1(CINT_REGS_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT+32 downto 0+32);
elsif m_axis_rx_tbar_hit_r1(CINT_DDR_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1+32 downto 0+32);
elsif m_axis_rx_tbar_hit_r1(CINT_FIFO_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT)
<= wb_pg(C_CHBUF_WB_BIT_TOP-C_CHBUF_WB_BIT_BOT-C_WB_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_WB_PG_WIDTH-1+32 downto 0+32);
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
end if;
else
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT downto 0);
if m_axis_rx_tbar_hit_r1(CINT_REGS_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= m_axis_rx_tdata_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT downto 0);
elsif m_axis_rx_tbar_hit_r1(CINT_DDR_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= sdram_pg(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT-C_DDR_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_DDR_PG_WIDTH-1 downto 0);
elsif m_axis_rx_tbar_hit_r1(CINT_FIFO_SPACE_BAR) = '1' then
pioCplD_din(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT)
<= wb_pg(C_CHBUF_WB_BIT_TOP-C_CHBUF_WB_BIT_BOT-C_WB_PG_WIDTH downto 0) &
m_axis_rx_tdata_r1(C_WB_PG_WIDTH-1 downto 0);
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
end if;
end if;
if pioCplD_din(C_CHBUF_0LENG_BIT) = '1' then -- Zero-length
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= CONV_STD_LOGIC_VECTOR(1, C_CHBUF_CPLD_BC_BIT_TOP-C_CHBUF_CPLD_BC_BIT_BOT+1);
else
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) &"00";
end if;
if m_axis_rx_tbar_hit_r1(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ZEROS(CINT_BAR_SPACES-1 downto 0) then
pioCplD_we <= not Tlp_straddles_4KB; --'1';
else
pioCplD_we <= '0';
end if;
when others =>
pioCplD_we <= '0';
pioCplD_din <= pioCplD_din;
end case;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MRd_Has_4DW_Header
-- : Tlp_is_Zero_Length
--
Syn_Capture_MRd_Has_4DW_Header :
process (user_clk, user_reset)
begin
if user_reset = '1' then
MRd_Has_3DW_Header <= '0';
MRd_Has_4DW_Header <= '0';
Tlp_is_Zero_Length <= '0';
Illegal_Leng_on_FIFO <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' then
MRd_Has_3DW_Header <= not m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT) and not m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT+1);
MRd_Has_4DW_Header <= m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT) and not m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT+1);
--Tlp_is_Zero_Length <= not (m_axis_rx_tdata_i(3) or m_axis_rx_tdata_i(2) or m_axis_rx_tdata_i(1) or m_axis_rx_tdata_i(0));
if m_axis_rx_tdata(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) = C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG - 1 downto 0) then
Tlp_is_Zero_Length <= '1';
else
Tlp_is_Zero_Length <= '0';
end if;
if m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) /= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
and m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) /= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
and m_axis_rx_tbar_hit(CINT_FIFO_SPACE_BAR) = '1'
then
Illegal_Leng_on_FIFO <= '1';
else
Illegal_Leng_on_FIFO <= '0';
end if;
else
MRd_Has_3DW_Header <= MRd_Has_3DW_Header;
MRd_Has_4DW_Header <= MRd_Has_4DW_Header;
Tlp_is_Zero_Length <= Tlp_is_Zero_Length;
Illegal_Leng_on_FIFO <= Illegal_Leng_on_FIFO;
end if;
end if;
end process;
-- -------------------------------------------------
-- MRd TLP Buffer
-- -------------------------------------------------
pioCplD_Buffer :
generic_sync_fifo
generic map (
g_data_width => 128,
g_size => 16,
g_show_ahead => false,
g_with_empty => true,
g_with_full => false,
g_with_almost_empty => false,
g_with_almost_full => true,
g_with_count => false,
g_almost_full_threshold => 12)
port map (
rst_n_i => local_Reset_n,
clk_i => user_clk,
d_i => pioCplD_din,
we_i => pioCplD_we,
q_o => pioCplD_Qout_wire,
rd_i => pioCplD_RE_i,
empty_o => pioCplD_empty_i,
full_o => pioCplD_full,
almost_empty_o => open,
almost_full_o => pioCplD_prog_Full,
count_o => open);
-- ---------------------------------------------
-- Request for arbitration
--
Synch_Req_Proc :
process (local_Reset, user_clk)
begin
if local_Reset = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (others => '0');
pioCplD_Qout_reg <= (others => '0');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
elsif user_clk'event and user_clk = '1' then
case FSM_REQ_pio is
when REQST_IDLE =>
if pioCplD_empty_i = '0' then
pioCplD_RE_i <= '1';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_1Read;
else
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_IDLE;
end if;
when REQST_1Read =>
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_Decision;
when REQST_Decision =>
pioCplD_Qout_reg <= pioCplD_Qout_wire;
pioCplD_Qout_i <= pioCplD_Qout_i;
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
when REQST_nFIFO_Req =>
if pioCplD_RE = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_reg;
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
else
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
end if;
when others =>
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (others => '0');
pioCplD_Qout_reg <= (others => '0');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
pioCplD_prog_full_r1 <= pioCplD_prog_Full;
end if;
end process;
-- ---------------------------------
-- Regenerate trn_rsof_n signal as in old TRN core
--
TRN_rsof_n_make :
process (user_clk, user_reset)
begin
if user_reset = '1' then
in_packet_reg <= '0';
elsif rising_edge(user_clk) then
if (m_axis_rx_tvalid) = '1' then
in_packet_reg <= not(m_axis_rx_tlast);
end if;
end if;
end process;
trn_rsof_n_i <= not(m_axis_rx_tvalid and not(in_packet_reg));
end architecture Behavioral;
|
lgpl-3.0
|
c441684e4dfab85b9c58f23e8ececf9f
| 0.545729 | 3.115653 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd
| 1 | 14,502 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc150_pkg.all;
entity fmc150_testbench is
generic(
g_sim : integer := 0
);
port
(
rst : in std_logic;
clk_100Mhz : in std_logic;
clk_200Mhz : in std_logic;
adc_clk_ab_p : in std_logic;
adc_clk_ab_n : in std_logic;
-- Start Simulation Only!
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
-- End of Simulation Only!
adc_cha_p : in std_logic_vector(6 downto 0);
adc_cha_n : in std_logic_vector(6 downto 0);
adc_chb_p : in std_logic_vector(6 downto 0);
adc_chb_n : in std_logic_vector(6 downto 0);
-- Start Simulation Only!
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
-- End of Simulation Only!
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
external_clock : in std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic;
adc_delay_update_i : in std_logic;
adc_str_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_cha_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_chb_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_str_cntvalueout_o : out std_logic_vector(4 downto 0);
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
mmcm_adc_locked_o : out std_logic
);
end fmc150_testbench;
architecture rtl of fmc150_testbench is
----------------------------------------------------------------------------------------------------
-- Constant declaration
----------------------------------------------------------------------------------------------------
constant ADC_STR_IDELAY : integer := 0; -- Initial number of delay taps on ADC clock input
constant ADC_CHA_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port A
constant ADC_CHB_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port B
----------------------------------------------------------------------------------------------------
-- Signal declaration
----------------------------------------------------------------------------------------------------
signal clk_ab_l : std_logic;
signal clk_ab_dly : std_logic;
signal adc_cha_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal adc_cha_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal adc_cha_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_chb_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal adc_chb_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal adc_chb_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_dout_a : std_logic_vector(15 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_dout_b : std_logic_vector(15 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_str : std_logic;
signal clk_adc : std_logic;
signal mmcm_adc_locked : std_logic;
signal fmc150_ctrl_in : t_fmc150_ctrl_in;
signal fmc150_ctrl_out : t_fmc150_ctrl_out;
signal clk_to_fpga : std_logic;
signal clk_adc_2x : std_logic;
signal dac_din_c : std_logic_vector(15 downto 0);
signal dac_din_d : std_logic_vector(15 downto 0);
signal adc_str_fbin, adc_str_out, adc_str_2x_out, adc_str_fbout : std_logic;
-- simulation only
signal toggle_ff_q : std_logic := '0';
signal toggle_ff_d : std_logic := '0';
begin
-- Synthesis Only
gen_clk : if (g_sim = 0) generate
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
--CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 16.000,
--CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 8,
--CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
--CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010,
-- Not used. Just to bypass Xilinx errors
-- Just input 61.44 MHz input clock
CLKIN2_PERIOD => 16.276,
REF_JITTER2 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
end generate;
-- Double clock circuit. only for SIMULATION!
gen_clk_sim : if (g_sim = 1) generate
clk_adc <= sim_adc_clk_i;
clk_adc_2x <= sim_adc_clk2x_i;
end generate;
clk_adc_o <= clk_adc;--adc_str;
-- ADC Interface
cmp_adc_if : fmc150_adc_if
generic map(
g_sim => g_sim
)
port map
(
--clk_200MHz_i => clk_200MHz,
clk_100MHz_i => clk_100MHz,
rst_i => mmcm_adc_locked,
str_p_i => adc_clk_ab_p,
str_n_i => adc_clk_ab_n,
cha_p_i => adc_cha_p,
cha_n_i => adc_cha_n,
chb_p_i => adc_chb_p,
chb_n_i => adc_chb_n,
cha_data_o => adc_cha_sdr,
chb_data_o => adc_chb_sdr,
str_o => adc_str,
-- Not used for now. Should it be removed?
clk_adc_i => adc_str,--clk_adc,
delay_update_i => adc_delay_update_i,
str_cntvalue_i => adc_str_cntvaluein_i,
cha_cntvalue_i => adc_cha_cntvaluein_i,
chb_cntvalue_i => adc_chb_cntvaluein_i,
str_cntvalue_o => adc_str_cntvalueout_o
);
-- Extend to 16-bit and register ADC data output
-- p_extend_adc_output : process (clk_adc)
-- begin
-- if (rising_edge(clk_adc)) then
gen_data : if (g_sim = 0) generate
p_extend_adc_output : process (adc_str)
begin
if (rising_edge(adc_str)) then
-- Left justify the data of both channels on 16-bits
adc_dout_a <= adc_cha_sdr(13) & adc_cha_sdr(13) & adc_cha_sdr;
adc_dout_b <= adc_chb_sdr(13) & adc_chb_sdr(13) & adc_chb_sdr;
-- adc_dout_a <= std_logic_vector(unsigned(adc_dout_a)+1);
-- adc_dout_b <= std_logic_vector(unsigned(adc_dout_b)-1);
end if;
end process;
end generate;
gen_data_sim : if (g_sim = 1) generate
adc_dout_a <= sim_adc_cha_data_i(13) & sim_adc_cha_data_i(13) & sim_adc_cha_data_i;
adc_dout_b <= sim_adc_chb_data_i(13) & sim_adc_chb_data_i(13) & sim_adc_chb_data_i;
end generate;
adc_dout_o <= adc_dout_a & adc_dout_b;
--adc_dout_o <= dac_din_c & dac_din_d;
-- DAC Interface
cmp_dac_if : fmc150_dac_if
port map
(
rst_i => mmcm_adc_locked,
clk_dac_i => clk_adc,
clk_dac_2x_i => clk_adc_2x,
dac_din_c_i => dac_din_c,
dac_din_d_i => dac_din_d,
dac_data_p_o => dac_data_p,
dac_data_n_o => dac_data_n,
dac_dclk_p_o => dac_dclk_p,
dac_dclk_n_o => dac_dclk_n,
dac_frame_p_o => dac_frame_p,
dac_frame_n_o => dac_frame_n,
txenable_o => txenable
);
mmcm_adc_locked_o <= mmcm_adc_locked;
-- Reference signal generation (need external netlist file)
-- cmp_sin_cos : sin_cos
-- port map
-- (
-- clk => clk_adc,
-- cosine => dac_din_c,
-- sine => dac_din_d,
-- phase_out => open
-- );
-- FMC150 control (SPI and direct signals)
cmp_fmc150_ctrl : fmc150_spi_ctrl
generic map(
g_sim => g_sim
)
port map
(
rst => rst,
clk => clk_100MHz,
rd_n_wr => rd_n_wr,
addr => addr,
idata => idata,
odata => odata,
busy => busy,
cdce72010_valid => cdce72010_valid,
ads62p49_valid => ads62p49_valid,
dac3283_valid => dac3283_valid,
amc7823_valid => amc7823_valid,
external_clock => external_clock,
adc_n_en => adc_n_en,
adc_sdo => adc_sdo,
adc_reset => adc_reset,
cdce_n_en => cdce_n_en,
cdce_sdo => cdce_sdo,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => ref_en,
pll_status => pll_status,
dac_n_en => dac_n_en,
dac_sdo => dac_sdo,
mon_n_en => mon_n_en,
mon_sdo => mon_sdo,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
spi_sclk => spi_sclk,
spi_sdata => spi_sdata,
prsnt_m2c_l => prsnt_m2c_l
);
end rtl;
|
lgpl-3.0
|
b453140d8f519519c58d59c73ce599a1
| 0.428699 | 3.777546 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/bpm_pcie_k7.vhd
| 1 | 69,409 |
----------------------------------------------------------------------------------
-- Company: Creotech
-- Engineer: Adrian Byszuk ([email protected])
--
-- Design Name:
-- Module Name: bpm_pcie_k7 - Behavioral
-- Project Name:
-- Target Devices: XC7K350T on KC705 devkit
-- Tool versions: ISE 14.4, ISE 14.6
-- Description: This is TOP module for the versatile firmware for PCIe communication.
-- It provides DMA engine with scatter-gather (linked list) functionality.
-- DDR memory is supported through BAR2. Wishbone endpoint is accessible through BAR3.
--
-- Dependencies: Xilinx PCIe core for 7 series. Xilinx DDR core for 7 series.
--
-- Revision: 2.00 - Original file completely rewritten by abyszuk.
--
-- Revision 1.00 - File Released
--
-- Additional Comments: This file can be used both as TOP module for independent operation, or
-- instantiated in another projects. To use it in your project, change INSTANTIATED generic to
-- "TRUE" and uncomment relevant interface sections in entity declaration. ATTENTION: you also
-- have to comment out dummy signal with names exactly the same as port names (it was necessary so
-- that XST won't complain about missing signal names).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bpm_pcie_k7 is
generic (
SIMULATION : string := "FALSE";
INSTANTIATED : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 512;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1;
SIM_BYPASS_INIT_CAL : string := "FAST"
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
sys_clk_p : in std_logic; --100 MHz PCIe Clock
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
-- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end entity bpm_pcie_k7;
architecture Behavioral of bpm_pcie_k7 is
constant DDR_ADDR_WIDTH : integer := 28;
component pcie_core
generic (
PL_FAST_TRAIN : string := "FALSE";
PCIE_EXT_CLK : string := "FALSE";
UPSTREAM_FACING : string := "TRUE";
PIPE_SIM_MODE : string := "FALSE"
);
port (
-------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
-------------------------------------------------------------------------------------------------------------------
pci_exp_txp : out std_logic_vector(3 downto 0);
pci_exp_txn : out std_logic_vector(3 downto 0);
pci_exp_rxp : in std_logic_vector(3 downto 0);
pci_exp_rxn : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 2. Clocking Interface --
-------------------------------------------------------------------------------------------------------------------
PIPE_PCLK_IN : in std_logic;
PIPE_RXUSRCLK_IN : in std_logic;
PIPE_RXOUTCLK_IN : in std_logic_vector(3 downto 0);
PIPE_DCLK_IN : in std_logic;
PIPE_USERCLK1_IN : in std_logic;
PIPE_USERCLK2_IN : in std_logic;
PIPE_OOBCLK_IN : in std_logic;
PIPE_MMCM_LOCK_IN : in std_logic;
PIPE_TXOUTCLK_OUT : out std_logic;
PIPE_RXOUTCLK_OUT : out std_logic_vector(3 downto 0);
PIPE_PCLK_SEL_OUT : out std_logic_vector(3 downto 0);
PIPE_GEN3_OUT : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 3. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out : out std_logic;
user_reset_out : out std_logic;
user_lnk_up : out std_logic;
-- TX
tx_buf_av : out std_logic_vector(5 downto 0);
tx_cfg_req : out std_logic;
tx_err_drop : out std_logic;
s_axis_tx_tready : out std_logic;
s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
s_axis_tx_tlast : in std_logic;
s_axis_tx_tvalid : in std_logic;
s_axis_tx_tuser : in std_logic_vector(3 downto 0);
tx_cfg_gnt : in std_logic;
-- RX
m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
m_axis_rx_tlast : out std_logic;
m_axis_rx_tvalid : out std_logic;
m_axis_rx_tready : in std_logic;
m_axis_rx_tuser : out std_logic_vector(21 downto 0);
rx_np_ok : in std_logic;
rx_np_req : in std_logic;
-- Flow Control
fc_cpld : out std_logic_vector(11 downto 0);
fc_cplh : out std_logic_vector(7 downto 0);
fc_npd : out std_logic_vector(11 downto 0);
fc_nph : out std_logic_vector(7 downto 0);
fc_pd : out std_logic_vector(11 downto 0);
fc_ph : out std_logic_vector(7 downto 0);
fc_sel : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 4. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EP and RP --
---------------------------------------------------------------------
cfg_mgmt_do : out std_logic_vector (31 downto 0);
cfg_mgmt_rd_wr_done : out std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state : out std_logic_vector(2 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_pmcsr_pme_status : out std_logic;
cfg_received_func_lvl_rst : out std_logic;
-- Management Interface
cfg_mgmt_di : in std_logic_vector (31 downto 0);
cfg_mgmt_byte_en : in std_logic_vector (3 downto 0);
cfg_mgmt_dwaddr : in std_logic_vector (9 downto 0);
cfg_mgmt_wr_en : in std_logic;
cfg_mgmt_rd_en : in std_logic;
cfg_mgmt_wr_readonly : in std_logic;
-- Error Reporting Interface
cfg_err_ecrc : in std_logic;
cfg_err_ur : in std_logic;
cfg_err_cpl_timeout : in std_logic;
cfg_err_cpl_unexpect : in std_logic;
cfg_err_cpl_abort : in std_logic;
cfg_err_posted : in std_logic;
cfg_err_cor : in std_logic;
cfg_err_atomic_egress_blocked : in std_logic;
cfg_err_internal_cor : in std_logic;
cfg_err_malformed : in std_logic;
cfg_err_mc_blocked : in std_logic;
cfg_err_poisoned : in std_logic;
cfg_err_norecovery : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy : out std_logic;
cfg_err_locked : in std_logic;
cfg_err_acs : in std_logic;
cfg_err_internal_uncor : in std_logic;
cfg_trn_pending : in std_logic;
cfg_pm_halt_aspm_l0s : in std_logic;
cfg_pm_halt_aspm_l1 : in std_logic;
cfg_pm_force_state_en : in std_logic;
cfg_pm_force_state : std_logic_vector(1 downto 0);
cfg_dsn : std_logic_vector(63 downto 0);
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt : in std_logic;
cfg_interrupt_rdy : out std_logic;
cfg_interrupt_assert : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_interrupt_stat : in std_logic;
cfg_pciecap_interrupt_msgnum : in std_logic_vector(4 downto 0);
cfg_to_turnoff : out std_logic;
cfg_turnoff_ok : in std_logic;
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_pm_wake : in std_logic;
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
cfg_pm_send_pme_to : in std_logic;
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
cfg_ds_device_number : in std_logic_vector(4 downto 0);
cfg_ds_function_number : in std_logic_vector(2 downto 0);
cfg_mgmt_wr_rw1c_as_rw : in std_logic;
cfg_msg_received : out std_logic;
cfg_msg_data : out std_logic_vector(15 downto 0);
cfg_bridge_serr_en : out std_logic;
cfg_slot_control_electromech_il_ctl_pulse : out std_logic;
cfg_root_control_syserr_corr_err_en : out std_logic;
cfg_root_control_syserr_non_fatal_err_en : out std_logic;
cfg_root_control_syserr_fatal_err_en : out std_logic;
cfg_root_control_pme_int_en : out std_logic;
cfg_aer_rooterr_corr_err_reporting_en : out std_logic;
cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;
cfg_aer_rooterr_fatal_err_reporting_en : out std_logic;
cfg_aer_rooterr_corr_err_received : out std_logic;
cfg_aer_rooterr_non_fatal_err_received : out std_logic;
cfg_aer_rooterr_fatal_err_received : out std_logic;
cfg_msg_received_err_cor : out std_logic;
cfg_msg_received_err_non_fatal : out std_logic;
cfg_msg_received_err_fatal : out std_logic;
cfg_msg_received_pm_as_nak : out std_logic;
cfg_msg_received_pm_pme : out std_logic;
cfg_msg_received_pme_to_ack : out std_logic;
cfg_msg_received_assert_int_a : out std_logic;
cfg_msg_received_assert_int_b : out std_logic;
cfg_msg_received_assert_int_c : out std_logic;
cfg_msg_received_assert_int_d : out std_logic;
cfg_msg_received_deassert_int_a : out std_logic;
cfg_msg_received_deassert_int_b : out std_logic;
cfg_msg_received_deassert_int_c : out std_logic;
cfg_msg_received_deassert_int_d : out std_logic;
cfg_msg_received_setslotpowerlimit : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 5. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_auton : in std_logic;
pl_upstream_prefer_deemph : in std_logic;
pl_sel_lnk_rate : out std_logic;
pl_sel_lnk_width : out std_logic_vector(1 downto 0);
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_phy_lnk_up : out std_logic;
pl_tx_pm_state : out std_logic_vector(2 downto 0);
pl_rx_pm_state : out std_logic_vector(1 downto 0);
pl_link_upcfg_cap : out std_logic;
pl_link_gen2_cap : out std_logic;
pl_link_partner_gen2_supported : out std_logic;
pl_initial_link_width : out std_logic_vector(2 downto 0);
pl_directed_change_done : out std_logic;
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst : out std_logic;
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
pl_transmit_hot_rst : in std_logic;
pl_downstream_deemph_source : in std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 6. AER interface --
-------------------------------------------------------------------------------------------------------------------
cfg_err_aer_headerlog : in std_logic_vector(127 downto 0);
cfg_aer_interrupt_msgnum : in std_logic_vector(4 downto 0);
cfg_err_aer_headerlog_set : out std_logic;
cfg_aer_ecrc_check_en : out std_logic;
cfg_aer_ecrc_gen_en : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 7. VC interface --
-------------------------------------------------------------------------------------------------------------------
cfg_vc_tcvc_map : out std_logic_vector(6 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 8. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
pipe_mmcm_rst_n : in std_logic;
sys_clk : in std_logic;
sys_rst_n : in std_logic);
end component;
component ddr_core
generic(
SIM_BYPASS_INIT_CAL : string;
SIMULATION : string;
RST_ACT_LOW : integer
);
port(
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
app_addr : in std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_rst : in std_logic
);
end component ddr_core;
-- -----------------------------------------------------------------------
-- DDR SDRAM control module
-- -----------------------------------------------------------------------
component bram_DDRs_Control_loopback
generic (
C_ASYNFIFO_WIDTH : integer;
P_SIMULATION : boolean
);
port (
DDR_wr_sof : in std_logic;
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_FA : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_sof : in std_logic;
DDR_rdc_eof : in std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_FA : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : out std_logic;
DDR_Blinker : out std_logic;
mem_clk : in std_logic;
user_clk : in std_logic;
Sim_Zeichen : out std_logic;
user_reset : in std_logic
);
end component;
component DDR_Transact
generic (
SIMULATION : string;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
DDR_UI_DATAWIDTH : integer;
DDR_DQ_WIDTH : integer;
DEVICE_TYPE : string -- "VIRTEX6"
-- "KINTEX7"
-- "ARTIX7"
);
port (
--ext logic interface to memory core
-- memory controller interface --
memc_ui_clk : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_UI_DATAWIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_rd_valid : out std_logic;
-- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ext logic interface
-- PCIE interface
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--/PCIE interface
-- Common interface
DDR_Ready : out std_logic;
-- DDR core UI
app_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : out std_logic_vector(2 downto 0);
app_en : out std_logic;
app_wdf_data : out std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_wdf_end : out std_logic;
app_wdf_mask : out std_logic_vector((DDR_UI_DATAWIDTH)/8-1 downto 0);
app_wdf_wren : out std_logic;
app_rd_data : in std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_rd_data_end : in std_logic;
app_rd_data_valid : in std_logic;
app_rdy : in std_logic;
app_wdf_rdy : in std_logic;
ui_clk : in std_logic;
ui_clk_sync_rst : in std_logic;
init_calib_complete : in std_logic;
--clocking & reset
user_clk : in std_logic;
user_reset : in std_logic
);
end component;
signal DDR_wr_sof : std_logic;
signal DDR_wr_eof : std_logic;
signal DDR_wr_v : std_logic;
signal DDR_wr_Shift : std_logic;
signal DDR_wr_Mask : std_logic_vector(2-1 downto 0);
signal DDR_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full : std_logic;
signal DDR_rdc_sof : std_logic;
signal DDR_rdc_eof : std_logic;
signal DDR_rdc_v : std_logic;
signal DDR_rdc_Shift : std_logic;
signal DDR_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_rdc_full : std_logic;
signal DDR_FIFO_RdEn : std_logic;
signal DDR_FIFO_Empty : std_logic;
signal DDR_FIFO_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Ready : std_logic;
-- -----------------------------------------------------------------------
-- Wishbone interface module
-- -----------------------------------------------------------------------
component wb_transact is
port (
-- PCIE user clk
user_clk : in std_logic;
-- Write port
wr_we : in std_logic;
wr_sof : in std_logic;
wr_eof : in std_logic;
wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full : out std_logic;
-- Read command port
rdc_sof : in std_logic;
rdc_v : in std_logic;
rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full : out std_logic;
rd_tout : in std_logic;
-- Read data port
rd_ren : in std_logic;
rd_empty : out std_logic;
rd_dout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk : in std_logic;
wb_rst : in std_logic;
addr_o : out std_logic_vector(28 downto 0);
dat_i : in std_logic_vector(63 downto 0);
dat_o : out std_logic_vector(63 downto 0);
we_o : out std_logic;
sel_o : out std_logic_vector(0 downto 0);
stb_o : out std_logic;
ack_i : in std_logic;
cyc_o : out std_logic;
--RESET from PCIe
rst : in std_logic
);
end component;
signal wbone_clk : std_logic;
signal wb_wr_we : std_logic;
signal wb_wr_wsof : std_logic;
signal wb_wr_weof : std_logic;
signal wb_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_wr_pfull : std_logic;
signal wb_wr_full : std_logic;
signal wb_rdc_sof : std_logic;
signal wb_rdc_v : std_logic;
signal wb_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdc_full : std_logic;
signal wb_timeout : std_logic;
signal wb_rdd_ren : std_logic;
signal wb_rdd_dout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdd_pempty : std_logic;
signal wb_rdd_empty : std_logic;
signal wbone_rst : std_logic;
signal wb_fifo_rst : std_logic;
signal wbone_addr : std_logic_vector(28 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
------------- COMPONENT Declaration: tlpControl ------
--
component tlpControl
port (
-- Wishbone interface
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_full : in std_logic;
wb_FIFO_Rst : out std_logic;
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
wb_timeout : out std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR control interface
DDR_Ready : in std_logic;
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Transaction layer interface
user_lnk_up : in std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
user_clk : in std_logic;
user_reset : in std_logic;
m_axis_rx_tvalid : in std_logic;
s_axis_tx_tready : in std_logic;
m_axis_rx_tlast : in std_logic;
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
pcie_link_width : in std_logic_vector(5 downto 0);
localId : in std_logic_vector(15 downto 0);
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(6 downto 0);
s_axis_tx_tvalid : out std_logic;
m_axis_rx_tready : out std_logic;
s_axis_tx_tlast : out std_logic;
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- TRN Layer signals
signal tx_err_drop : std_logic;
signal tx_cfg_gnt : std_logic;
signal fc_cpld : std_logic_vector (12-1 downto 0);
signal fc_cplh : std_logic_vector (8-1 downto 0);
signal fc_npd : std_logic_vector (12-1 downto 0);
signal fc_nph : std_logic_vector (8-1 downto 0);
signal fc_pd : std_logic_vector (12-1 downto 0);
signal fc_ph : std_logic_vector (8-1 downto 0);
signal fc_sel : std_logic_vector (3-1 downto 0);
signal cfg_dcommand2 : std_logic_vector (16-1 downto 0);
signal tx_cfg_req : std_logic;
signal pl_initial_link_width : std_logic_vector (3-1 downto 0);
signal pl_lane_reversal_mode : std_logic_vector (2-1 downto 0);
signal pl_link_gen2_cap : std_logic;
signal pl_link_partner_gen2_supported : std_logic;
signal pl_link_upcfg_cap : std_logic;
signal pl_ltssm_state : std_logic_vector (6-1 downto 0);
signal pl_received_hot_rst : std_logic;
signal pl_sel_lnk_rate : std_logic;
signal pl_sel_lnk_width : std_logic_vector (2-1 downto 0);
signal pl_directed_link_auton : std_logic;
signal pl_directed_link_change : std_logic_vector (2-1 downto 0);
signal pl_directed_link_speed : std_logic;
signal pl_directed_link_width : std_logic_vector (2-1 downto 0);
signal pl_upstream_prefer_deemph : std_logic;
-- Wires used for external clocking connectivity
signal PIPE_PCLK_IN : std_logic := '0';
signal PIPE_RXUSRCLK_IN : std_logic := '0';
signal PIPE_RXOUTCLK_IN : std_logic_vector(3 downto 0) := (others => '0');
signal PIPE_DCLK_IN : std_logic := '0';
signal PIPE_USERCLK1_IN : std_logic := '0';
signal PIPE_USERCLK2_IN : std_logic := '0';
signal PIPE_OOBCLK_IN : std_logic := '0';
signal PIPE_MMCM_LOCK_IN : std_logic := '0';
signal PIPE_TXOUTCLK_OUT : std_logic;
signal PIPE_RXOUTCLK_OUT : std_logic_vector(3 downto 0);
signal PIPE_PCLK_SEL_OUT : std_logic_vector(3 downto 0);
signal PIPE_GEN3_OUT : std_logic;
----------------------------------------------------
signal user_reset_int1 : std_logic;
signal user_lnk_up_int1 : std_logic;
signal user_clk : std_logic;
signal user_reset : std_logic;
signal user_lnk_up : std_logic;
signal s_axis_tx_tdata : std_logic_vector(63 downto 0);
signal s_axis_tx_tkeep : std_logic_vector(7 downto 0);
signal s_axis_tx_tlast : std_logic;
signal s_axis_tx_tvalid : std_logic;
signal s_axis_tx_tready : std_logic;
signal s_axis_tx_tuser : std_logic_vector(3 downto 0);
signal s_axis_tx_tdsc : std_logic;
signal s_axis_tx_terrfwd : std_logic;
signal tx_buf_av : std_logic_vector(5 downto 0);
signal m_axis_rx_tdata : std_logic_vector(63 downto 0);
signal m_axis_rx_tkeep : std_logic_vector(7 downto 0);
signal m_axis_rx_tlast : std_logic;
signal m_axis_rx_tvalid : std_logic;
signal m_axis_rx_tready : std_logic;
signal m_axis_rx_terrfwd : std_logic;
signal m_axis_rx_tuser : std_logic_vector(21 downto 0);
signal rx_np_ok : std_logic;
signal rx_np_req : std_logic;
signal m_axis_rx_tbar_hit : std_logic_vector(6 downto 0);
signal trn_rfc_nph_av : std_logic_vector(7 downto 0);
signal trn_rfc_npd_av : std_logic_vector(11 downto 0);
signal trn_rfc_ph_av : std_logic_vector(7 downto 0);
signal trn_rfc_pd_av : std_logic_vector(11 downto 0);
signal trn_rfc_cplh_av : std_logic_vector(7 downto 0);
signal trn_rfc_cpld_av : std_logic_vector(11 downto 0);
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_mgmt_rd_wr_done : std_logic;
signal cfg_di : std_logic_vector(31 downto 0);
signal cfg_mgmt_byte_en : std_logic_vector(3 downto 0);
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_mgmt_wr_en : std_logic;
signal cfg_mgmt_rd_en : std_logic;
signal cfg_err_cor : std_logic;
signal cfg_err_ur : std_logic;
signal cfg_err_cpl_rdy : std_logic;
signal cfg_err_ecrc : std_logic;
signal cfg_err_cpl_timeout : std_logic;
signal cfg_err_cpl_abort : std_logic;
signal cfg_err_cpl_unexpect : std_logic;
signal cfg_err_posted : std_logic;
signal cfg_err_locked : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_interrupt : std_logic;
signal cfg_interrupt_rdy : std_logic;
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
signal cfg_interrupt_assert : std_logic;
signal cfg_interrupt_msixenable : std_logic;
signal cfg_interrupt_msixfm : std_logic;
signal cfg_turnoff_ok : std_logic;
signal cfg_to_turnoff : std_logic;
signal cfg_pm_wake : std_logic;
signal cfg_pcie_link_state : std_logic_vector(2 downto 0);
signal cfg_trn_pending : std_logic;
signal cfg_bus_number : std_logic_vector(7 downto 0);
signal cfg_device_number : std_logic_vector(4 downto 0);
signal cfg_function_number : std_logic_vector(2 downto 0);
signal cfg_dsn : std_logic_vector(63 downto 0);
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal fast_train_simulation_only : std_logic;
signal two_plm_auto_config : std_logic_vector(1 downto 0);
signal cfg_mgmt_di : std_logic_vector(31 downto 0);
signal cfg_mgmt_dwaddr : std_logic_vector(9 downto 0);
signal cfg_mgmt_wr_readonly : std_logic;
signal cfg_err_atomic_egress_blocked : std_logic;
signal cfg_err_internal_cor : std_logic;
signal cfg_err_malformed : std_logic;
signal cfg_err_mc_blocked : std_logic;
signal cfg_err_poisoned : std_logic;
signal cfg_err_norecovery : std_logic;
signal cfg_err_acs : std_logic;
signal cfg_err_internal_uncor : std_logic;
signal cfg_err_aer_headerlog : std_logic_vector(127 downto 0);
signal cfg_aer_interrupt_msgnum : std_logic_vector(4 downto 0);
signal cfg_err_aer_headerlog_set : std_logic;
signal cfg_aer_ecrc_check_en : std_logic;
signal cfg_aer_ecrc_gen_en : std_logic;
signal cfg_pm_halt_aspm_l0s : std_logic;
signal cfg_pm_halt_aspm_l1 : std_logic;
signal cfg_pm_force_state_en : std_logic;
signal cfg_pm_force_state : std_logic_vector(1 downto 0);
signal cfg_interrupt_stat : std_logic;
signal cfg_pciecap_interrupt_msgnum : std_logic_vector(4 downto 0);
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
signal sys_reset_c : std_logic;
signal reset_n : std_logic;
signal localId : std_logic_vector(15 downto 0);
signal pcie_link_width : std_logic_vector(5 downto 0);
----- DDR core User Interface signals -----------------------
signal app_addr : std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal ddr_ui_clk : std_logic;
signal ddr_ui_reset : std_logic;
signal ddr_calib_done : std_logic;
begin
sys_reset_c <= not sys_reset_n_c;
sys_reset_n_ibuf : IBUF
port map (
O => sys_reset_n_c,
I => sys_rst_n
);
pcieclk_ibuf : IBUFDS_GTE2
port map (
O => sys_clk_c,
ODIV2 => open,
I => sys_clk_p,
IB => sys_clk_n,
CEB => '0'
);
cfg_err_cor <= '0';
cfg_err_ur <= '0';
cfg_err_ecrc <= '0';
cfg_err_cpl_timeout <= '0';
cfg_err_cpl_abort <= '0';
cfg_err_cpl_unexpect <= '0';
cfg_err_posted <= '1';
cfg_err_locked <= '1';
cfg_err_tlp_cpl_header <= (others => '0');
cfg_trn_pending <= '0';
cfg_pm_wake <= '0';
--
fc_sel <= (others => '0');
pl_directed_link_auton <= '0';
pl_directed_link_change <= (others => '0');
pl_directed_link_speed <= '0';
pl_directed_link_width <= (others => '0');
pl_upstream_prefer_deemph <= '0';
tx_cfg_gnt <= '1';
s_axis_tx_tuser <= s_axis_tx_tdsc & '0' & s_axis_tx_terrfwd & '0';
m_axis_rx_terrfwd <= m_axis_rx_tuser(1);
m_axis_rx_tbar_hit <= m_axis_rx_tuser(8 downto 2);
--
cfg_di <= (others => '0');
cfg_dwaddr <= (others => '1');
cfg_mgmt_byte_en <= (others => '0');
cfg_mgmt_wr_en <= '0';
cfg_mgmt_rd_en <= '0';
cfg_dsn <= X"00000001" & X"01" & X"000A35"; -- //this is taken from GUI -
cfg_turnoff_ok <= '1';
localId <= cfg_bus_number & cfg_device_number & cfg_function_number;
pcie_link_width <= cfg_lstatus(9 downto 4);
user_lnk_up_int_i : FDPE
generic map (
INIT => '0'
)
port map (
Q => user_lnk_up,
D => user_lnk_up_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
user_reset_i : FDPE
generic map (
INIT => '1'
)
port map (
Q => user_reset,
D => user_reset_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
-- --------------------------------------------------------------
-- --------------------------------------------------------------
pcie_core_i : pcie_core
generic map(
PL_FAST_TRAIN => PL_FAST_TRAIN,
PCIE_EXT_CLK => "FALSE",
PIPE_SIM_MODE => PIPE_SIM_MODE
)
port map(
--------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
--------------------------------------------------------------------------------------------------------------------
--TX
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- RX
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
-------------------------------------------------------------------------------------------------------------------
-- 2. Clocking Interface - For Partial Reconfig Support --
-------------------------------------------------------------------------------------------------------------------
PIPE_PCLK_IN => PIPE_PCLK_IN,
PIPE_RXUSRCLK_IN => PIPE_RXUSRCLK_IN,
PIPE_RXOUTCLK_IN => PIPE_RXOUTCLK_IN,
PIPE_DCLK_IN => PIPE_DCLK_IN,
PIPE_USERCLK1_IN => PIPE_USERCLK1_IN,
PIPE_USERCLK2_IN => PIPE_USERCLK2_IN,
PIPE_OOBCLK_IN => PIPE_OOBCLK_IN,
PIPE_MMCM_LOCK_IN => PIPE_MMCM_LOCK_IN,
PIPE_TXOUTCLK_OUT => PIPE_TXOUTCLK_OUT,
PIPE_RXOUTCLK_OUT => PIPE_RXOUTCLK_OUT,
PIPE_PCLK_SEL_OUT => PIPE_PCLK_SEL_OUT,
PIPE_GEN3_OUT => PIPE_GEN3_OUT,
-------------------------------------------------------------------------------------------------------------------
-- 3. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out => user_clk ,
user_reset_out => user_reset_int1,
user_lnk_up => user_lnk_up_int1,
-- TX
tx_buf_av => tx_buf_av ,
tx_cfg_req => tx_cfg_req ,
tx_err_drop => tx_err_drop ,
s_axis_tx_tready => s_axis_tx_tready ,
s_axis_tx_tdata => s_axis_tx_tdata ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
s_axis_tx_tuser => s_axis_tx_tuser,
tx_cfg_gnt => tx_cfg_gnt ,
-- RX
m_axis_rx_tdata => m_axis_rx_tdata ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
m_axis_rx_tuser => m_axis_rx_tuser,
rx_np_ok => rx_np_ok ,
rx_np_req => rx_np_req ,
-- Flow Control
fc_cpld => fc_cpld ,
fc_cplh => fc_cplh ,
fc_npd => fc_npd ,
fc_nph => fc_nph ,
fc_pd => fc_pd ,
fc_ph => fc_ph ,
fc_sel => fc_sel ,
-------------------------------------------------------------------------------------------------------------------
-- 4. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EP and RP --
---------------------------------------------------------------------
cfg_mgmt_do => open ,
cfg_mgmt_rd_wr_done => open ,
cfg_status => cfg_status ,
cfg_command => cfg_command ,
cfg_dstatus => cfg_dstatus ,
cfg_dcommand => cfg_dcommand ,
cfg_lstatus => cfg_lstatus ,
cfg_lcommand => cfg_lcommand ,
cfg_dcommand2 => cfg_dcommand2 ,
cfg_pcie_link_state => cfg_pcie_link_state ,
cfg_pmcsr_pme_en => open ,
cfg_pmcsr_pme_status => open ,
cfg_pmcsr_powerstate => open ,
cfg_received_func_lvl_rst => open ,
cfg_mgmt_di => cfg_mgmt_di ,
cfg_mgmt_byte_en => cfg_mgmt_byte_en ,
cfg_mgmt_dwaddr => cfg_mgmt_dwaddr ,
cfg_mgmt_wr_en => cfg_mgmt_wr_en ,
cfg_mgmt_rd_en => cfg_mgmt_rd_en ,
cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly ,
cfg_err_ecrc => cfg_err_ecrc ,
cfg_err_ur => cfg_err_ur ,
cfg_err_cpl_timeout => cfg_err_cpl_timeout ,
cfg_err_cpl_unexpect => cfg_err_cpl_unexpect ,
cfg_err_cpl_abort => cfg_err_cpl_abort ,
cfg_err_posted => cfg_err_posted ,
cfg_err_cor => cfg_err_cor ,
cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked ,
cfg_err_internal_cor => cfg_err_internal_cor ,
cfg_err_malformed => cfg_err_malformed ,
cfg_err_mc_blocked => cfg_err_mc_blocked ,
cfg_err_poisoned => cfg_err_poisoned ,
cfg_err_norecovery => cfg_err_norecovery ,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy => cfg_err_cpl_rdy ,
cfg_err_locked => cfg_err_locked ,
cfg_err_acs => cfg_err_acs ,
cfg_err_internal_uncor => cfg_err_internal_uncor ,
cfg_trn_pending => cfg_trn_pending ,
cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s ,
cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1 ,
cfg_pm_force_state_en => cfg_pm_force_state_en ,
cfg_pm_force_state => cfg_pm_force_state ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_assert => cfg_interrupt_assert ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_stat => cfg_interrupt_stat ,
cfg_pciecap_interrupt_msgnum => cfg_pciecap_interrupt_msgnum ,
cfg_to_turnoff => cfg_to_turnoff ,
cfg_turnoff_ok => cfg_turnoff_ok ,
cfg_bus_number => cfg_bus_number ,
cfg_device_number => cfg_device_number ,
cfg_function_number => cfg_function_number ,
cfg_pm_wake => cfg_pm_wake ,
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
cfg_pm_send_pme_to => '0' ,
cfg_ds_bus_number => x"00" ,
cfg_ds_device_number => "00000" ,
cfg_ds_function_number => "000" ,
cfg_mgmt_wr_rw1c_as_rw => '0' ,
cfg_msg_received => open ,
cfg_msg_data => open ,
cfg_bridge_serr_en => open ,
cfg_slot_control_electromech_il_ctl_pulse => open ,
cfg_root_control_syserr_corr_err_en => open ,
cfg_root_control_syserr_non_fatal_err_en => open ,
cfg_root_control_syserr_fatal_err_en => open ,
cfg_root_control_pme_int_en => open ,
cfg_aer_rooterr_corr_err_reporting_en => open ,
cfg_aer_rooterr_non_fatal_err_reporting_en => open ,
cfg_aer_rooterr_fatal_err_reporting_en => open ,
cfg_aer_rooterr_corr_err_received => open ,
cfg_aer_rooterr_non_fatal_err_received => open ,
cfg_aer_rooterr_fatal_err_received => open ,
cfg_msg_received_err_cor => open ,
cfg_msg_received_err_non_fatal => open ,
cfg_msg_received_err_fatal => open ,
cfg_msg_received_pm_as_nak => open ,
cfg_msg_received_pm_pme => open ,
cfg_msg_received_pme_to_ack => open ,
cfg_msg_received_assert_int_a => open ,
cfg_msg_received_assert_int_b => open ,
cfg_msg_received_assert_int_c => open ,
cfg_msg_received_assert_int_d => open ,
cfg_msg_received_deassert_int_a => open ,
cfg_msg_received_deassert_int_b => open ,
cfg_msg_received_deassert_int_c => open ,
cfg_msg_received_deassert_int_d => open ,
-------------------------------------------------------------------------------------------------------------------
-- 5. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_auton => pl_directed_link_auton ,
pl_directed_link_change => pl_directed_link_change ,
pl_directed_link_speed => pl_directed_link_speed ,
pl_directed_link_width => pl_directed_link_width ,
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
pl_sel_lnk_rate => pl_sel_lnk_rate ,
pl_sel_lnk_width => pl_sel_lnk_width ,
pl_ltssm_state => pl_ltssm_state ,
pl_lane_reversal_mode => pl_lane_reversal_mode ,
pl_phy_lnk_up => open ,
pl_tx_pm_state => open ,
pl_rx_pm_state => open ,
cfg_dsn => cfg_dsn ,
pl_link_upcfg_cap => pl_link_upcfg_cap ,
pl_link_gen2_cap => pl_link_gen2_cap ,
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
pl_initial_link_width => pl_initial_link_width ,
pl_directed_change_done => open ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst => pl_received_hot_rst ,
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
pl_transmit_hot_rst => '0' ,
pl_downstream_deemph_source => '0' ,
-------------------------------------------------------------------------------------------------------------------
-- 6. AER interface --
-------------------------------------------------------------------------------------------------------------------
cfg_err_aer_headerlog => cfg_err_aer_headerlog ,
cfg_aer_interrupt_msgnum => cfg_aer_interrupt_msgnum ,
cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set ,
cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en ,
cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en ,
-------------------------------------------------------------------------------------------------------------------
-- 7. VC interface --
-------------------------------------------------------------------------------------------------------------------
cfg_vc_tcvc_map => open ,
-------------------------------------------------------------------------------------------------------------------
-- 8. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
pipe_mmcm_rst_n => sys_reset_n_c,
sys_clk => sys_clk_c ,
sys_rst_n => sys_reset_n_c
);
-- ---------------------------------------------------------------
-- tlp control module
-- ---------------------------------------------------------------
-- workaround pcie core bug
--m_axis_rx_tkeep(7 downto 1) <= X"0" & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0);
theTlpControl :
tlpControl
port map (
-- Wishbone FIFO interface
wb_FIFO_we => wb_wr_we , -- OUT std_logic;
wb_FIFO_wsof => wb_wr_wsof , -- OUT std_logic;
wb_FIFO_weof => wb_wr_weof , -- OUT std_logic;
wb_FIFO_din => wb_wr_din(C_DBUS_WIDTH-1 downto 0) , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_full => wb_wr_full,
wb_FIFO_re => wb_rdd_ren , -- OUT std_logic;
wb_FIFO_empty => wb_rdd_empty , -- IN std_logic;
wb_FIFO_qout => wb_rdd_dout(C_DBUS_WIDTH-1 downto 0) , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_sof => wb_rdc_sof, --out std_logic;
wb_rdc_v => wb_rdc_v, --out std_logic;
wb_rdc_din => wb_rdc_din, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full => wb_rdc_full, --in std_logic;
wb_timeout => wb_timeout,
wb_FIFO_Rst => wb_fifo_rst, -- OUT std_logic;
-------------------
-- DDR Interface
DDR_Ready => DDR_Ready , -- IN std_logic;
DDR_wr_sof => DDR_wr_sof , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof , -- OUT std_logic;
DDR_wr_v => DDR_wr_v , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- OUT std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-------------------
-- Transaction Interface
user_lnk_up => user_lnk_up ,
rx_np_ok => rx_np_ok ,
rx_np_req => rx_np_req ,
s_axis_tx_tdsc => s_axis_tx_tdsc ,
tx_buf_av => tx_buf_av ,
s_axis_tx_terrfwd => s_axis_tx_terrfwd ,
user_clk => user_clk ,
user_reset => user_reset ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
s_axis_tx_tready => s_axis_tx_tready ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_terrfwd => m_axis_rx_terrfwd ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tdata => m_axis_rx_tdata ,
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_assert => cfg_interrupt_assert ,
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tdata => s_axis_tx_tdata ,
cfg_dcommand => cfg_dcommand ,
pcie_link_width => pcie_link_width ,
localId => localId
);
-- -----------------------------------------------------------------------
-- DDR SDRAM: control module
-- -----------------------------------------------------------------------
LoopBack_BRAM_Off : if not USE_LOOPBACK_TEST generate
DDRs_ctrl_module : DDR_Transact
generic map (
SIMULATION => SIMULATION,
DATA_WIDTH => C_DBUS_WIDTH,
ADDR_WIDTH => DDR_ADDR_WIDTH,
DDR_UI_DATAWIDTH => DDR_PAYLOAD_WIDTH,
DDR_DQ_WIDTH => DDR_DQ_WIDTH,
DEVICE_TYPE => "KINTEX7"
)
port map(
memc_ui_clk => memc_ui_clk, --: out std_logic;
memc_cmd_rdy => memc_cmd_rdy, --: out std_logic;
memc_cmd_en => memc_cmd_en, --: in std_logic;
memc_cmd_instr => memc_cmd_instr, --: in std_logic_vector(2 downto 0);
memc_cmd_addr => memc_cmd_addr, --: in std_logic_vector(31 downto 0);
memc_wr_en => memc_wr_en, --: in std_logic;
memc_wr_end => memc_wr_end, --: in std_logic;
memc_wr_mask => memc_wr_mask, --: in std_logic_vector(64/8-1 downto 0);
memc_wr_data => memc_wr_data, --: in std_logic_vector(64-1 downto 0);
memc_wr_rdy => memc_wr_rdy, --: out std_logic;
memc_rd_data => memc_rd_data, --: out std_logic_vector(64-1 downto 0);
memc_rd_valid => memc_rd_valid, --: out std_logic;
memarb_acc_req => memarb_acc_req, --: in std_logic;
memarb_acc_gnt => memarb_acc_gnt, --: out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready, -- OUT std_logic;
-- DDR core User Interface signals
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
init_calib_complete => ddr_calib_done,
--clocking & reset
user_clk => user_clk , -- IN std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
LoopBack_BRAM_On : if USE_LOOPBACK_TEST generate
DDRs_ctrl_module :
bram_DDRs_Control_loopback
generic map (
C_ASYNFIFO_WIDTH => 72 ,
P_SIMULATION => false
)
port map(
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_sof => DDR_wr_sof , -- IN std_logic;
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_FA => '0', -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- IN std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- IN std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_FA => '0', -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready , -- OUT std_logic;
DDR_Blinker => open, -- OUT std_logic;
mem_clk => user_clk , -- IN
user_clk => user_clk , -- IN std_logic;
Sim_Zeichen => open , -- OUT std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
Wishbone_intf :
wb_transact
port map(
-- PCIE user clk
user_clk => user_clk, --in std_logic;
-- Write port
wr_we => wb_wr_we, --in std_logic;
wr_sof => wb_wr_wsof, --in std_logic;
wr_eof => wb_wr_weof, --in std_logic;
wr_din => wb_wr_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full => wb_wr_full, --out std_logic;
-- Read command port
rdc_sof => wb_rdc_sof, --in std_logic;
rdc_v => wb_rdc_v, --in std_logic;
rdc_din => wb_rdc_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full => wb_rdc_full,--out std_logic;
rd_tout => wb_timeout,
-- Read data port
rd_ren => wb_rdd_ren, --in std_logic;
rd_empty => wb_rdd_empty, --out std_logic;
rd_dout => wb_rdd_dout, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk => wbone_clk, --in std_logic;
wb_rst => wbone_rst, --in std_logic;
addr_o => wbone_addr(28 downto 0), --out std_logic_vector(31 downto 0);
dat_i => wbone_mdin, --in std_logic_vector(63 downto 0);
dat_o => wbone_mdout, --out std_logic_vector(63 downto 0);
we_o => wbone_we, --out std_logic;
sel_o => wbone_sel, --out std_logic_vector(0 downto 0);
stb_o => wbone_stb, --out std_logic;
ack_i => wbone_ack, --in std_logic;
cyc_o => wbone_cyc, --out std_logic;
--RESET from PCIe
rst => user_reset --in std_logic
);
wbone_clk <= CLK_I;
wbone_rst <= RST_I;
wbone_mdin <= DAT_I;
wbone_ack <= ACK_I;
ADDR_O <= wbone_addr;
DAT_O <= wbone_mdout;
WE_O <= wbone_we;
SEL_O <= wbone_sel(0);
STB_O <= wbone_stb;
CYC_O <= wbone_cyc;
ext_rst_o <= wb_fifo_rst;
u_ddr_core : ddr_core
generic map (
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
RST_ACT_LOW => 1
)
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
init_calib_complete => ddr_calib_done,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_sr_active => app_sr_active,
app_ref_req => '0',
app_ref_ack => app_ref_ack,
app_zq_req => '0',
app_zq_ack => app_zq_ack,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
-- System Clock Ports
sys_clk_p => ddr_sys_clk_p,
sys_clk_n => ddr_sys_clk_n,
-- Reference Clock Ports
--clk_ref_i => ddr_ref_clk,
sys_rst => sys_reset_n_c
);
memc_ui_rst <= ddr_ui_reset;
end Behavioral;
|
lgpl-3.0
|
018f7e51fbdd9f9550083086ada5258b
| 0.485643 | 3.577046 | false | false | false | false |
VectorBlox/risc-v
|
ip/idram/src/idram_components.vhd
| 1 | 6,043 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.idram_utils.all;
package idram_components is
component idram is
generic (
--Port types: 0 = AXI4Lite, 1 = AXI3, 2 = AXI4
INSTR_PORT_TYPE : natural range 0 to 2 := 0;
DATA_PORT_TYPE : natural range 0 to 2 := 0;
SIZE : integer := 32768;
RAM_WIDTH : integer := 32;
ADDR_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
instr_AWID : in std_logic_vector(13 downto 0);
instr_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
instr_AWLEN : in std_logic_vector(7-(4*(INSTR_PORT_TYPE mod 2)) downto 0);
instr_AWSIZE : in std_logic_vector(2 downto 0);
instr_AWBURST : in std_logic_vector(1 downto 0);
instr_AWLOCK : in std_logic_vector(1 downto 0);
instr_AWCACHE : in std_logic_vector(3 downto 0);
instr_AWPROT : in std_logic_vector(2 downto 0);
instr_AWVALID : in std_logic;
instr_AWREADY : out std_logic;
instr_WID : in std_logic_vector(13 downto 0);
instr_WDATA : in std_logic_vector(RAM_WIDTH-1 downto 0);
instr_WSTRB : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
instr_WLAST : in std_logic;
instr_WVALID : in std_logic;
instr_WREADY : out std_logic;
instr_BID : out std_logic_vector(13 downto 0);
instr_BRESP : out std_logic_vector(1 downto 0);
instr_BVALID : out std_logic;
instr_BREADY : in std_logic;
instr_ARID : in std_logic_vector(13 downto 0);
instr_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
instr_ARLEN : in std_logic_vector(7-(4*(INSTR_PORT_TYPE mod 2)) downto 0);
instr_ARSIZE : in std_logic_vector(2 downto 0);
instr_ARBURST : in std_logic_vector(1 downto 0);
instr_ARLOCK : in std_logic_vector(1 downto 0);
instr_ARCACHE : in std_logic_vector(3 downto 0);
instr_ARPROT : in std_logic_vector(2 downto 0);
instr_ARVALID : in std_logic;
instr_ARREADY : out std_logic;
instr_RID : out std_logic_vector(13 downto 0);
instr_RDATA : out std_logic_vector(RAM_WIDTH-1 downto 0);
instr_RRESP : out std_logic_vector(1 downto 0);
instr_RLAST : out std_logic;
instr_RVALID : out std_logic;
instr_RREADY : in std_logic;
data_AWID : in std_logic_vector(13 downto 0);
data_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_AWLEN : in std_logic_vector(7-(4*(DATA_PORT_TYPE mod 2)) downto 0);
data_AWSIZE : in std_logic_vector(2 downto 0);
data_AWBURST : in std_logic_vector(1 downto 0);
data_AWLOCK : in std_logic_vector(1 downto 0);
data_AWCACHE : in std_logic_vector(3 downto 0);
data_AWPROT : in std_logic_vector(2 downto 0);
data_AWVALID : in std_logic;
data_AWREADY : out std_logic;
data_WID : in std_logic_vector(13 downto 0);
data_WDATA : in std_logic_vector(RAM_WIDTH-1 downto 0);
data_WSTRB : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
data_WLAST : in std_logic;
data_WVALID : in std_logic;
data_WREADY : out std_logic;
data_BID : out std_logic_vector(13 downto 0);
data_BRESP : out std_logic_vector(1 downto 0);
data_BVALID : out std_logic;
data_BREADY : in std_logic;
data_ARID : in std_logic_vector(13 downto 0);
data_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_ARLEN : in std_logic_vector(7-(4*(DATA_PORT_TYPE mod 2)) downto 0);
data_ARSIZE : in std_logic_vector(2 downto 0);
data_ARBURST : in std_logic_vector(1 downto 0);
data_ARLOCK : in std_logic_vector(1 downto 0);
data_ARCACHE : in std_logic_vector(3 downto 0);
data_ARPROT : in std_logic_vector(2 downto 0);
data_ARVALID : in std_logic;
data_ARREADY : out std_logic;
data_RID : out std_logic_vector(13 downto 0);
data_RDATA : out std_logic_vector(RAM_WIDTH-1 downto 0);
data_RRESP : out std_logic_vector(1 downto 0);
data_RLAST : out std_logic;
data_RVALID : out std_logic;
data_RREADY : in std_logic
);
end component;
component idram_behav is
generic (
RAM_DEPTH : integer := 1024;
RAM_WIDTH : integer := 32;
WRITE_FIRST : boolean := false
);
port (
clk : in std_logic;
instr_address : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
instr_data_in : in std_logic_vector(RAM_WIDTH-1 downto 0);
instr_we : in std_logic;
instr_en : in std_logic;
instr_be : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
instr_readdata : out std_logic_vector(RAM_WIDTH-1 downto 0);
data_address : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
data_data_in : in std_logic_vector(RAM_WIDTH-1 downto 0);
data_we : in std_logic;
data_en : in std_logic;
data_be : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
data_readdata : out std_logic_vector(RAM_WIDTH-1 downto 0)
);
end component;
component tdp_ram_behav is
generic (
RAM_DEPTH : integer := 1024;
RAM_WIDTH : integer := 8;
WRITE_FIRST : boolean := false
);
port (
address_a : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
address_b : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
clk : in std_logic;
data_a : in std_logic_vector(RAM_WIDTH-1 downto 0);
data_b : in std_logic_vector(RAM_WIDTH-1 downto 0);
wren_a : in std_logic;
wren_b : in std_logic;
en_a : in std_logic;
en_b : in std_logic;
readdata_a : out std_logic_vector(RAM_WIDTH-1 downto 0);
readdata_b : out std_logic_vector(RAM_WIDTH-1 downto 0)
);
end component;
end package idram_components;
|
bsd-3-clause
|
59984a72a69d807b4f165451c5968b3b
| 0.594738 | 3.209241 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/Registers.vhd
| 1 | 88,966 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: Regs_Group - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--
-- Revision 1.10 - Readability improved by FOR-LOOP used 19.03.2007
--
-- Revision 1.00 - File Created 06.02.2007
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Regs_Group is
port (
-- Event Buffer status + reset
wb_FIFO_Rst : out std_logic;
-- Write interface
Regs_WrEnA : in std_logic;
Regs_WrMaskA : in std_logic_vector(2-1 downto 0);
Regs_WrAddrA : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEnB : in std_logic;
Regs_WrMaskB : in std_logic_vector(2-1 downto 0);
Regs_WrAddrB : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinB : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register Read interface
Regs_RdAddr : in std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : in std_logic;
ds_DMA_Bytes : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers to/from Downstream Engine
DMA_ds_PA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : out std_logic; -- obsolete
DMA_ds_Status : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : in std_logic;
DMA_ds_Tout : in std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : out std_logic;
dsBDA_is_64b : out std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : out std_logic;
dsLeng_Lo7b_True : out std_logic;
-- Downstream Control Signals
dsDMA_Start : out std_logic;
dsDMA_Stop : out std_logic;
dsDMA_Start2 : out std_logic;
dsDMA_Stop2 : out std_logic;
dsDMA_Channel_Rst : out std_logic;
dsDMA_Cmd_Ack : in std_logic;
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : in std_logic;
us_DMA_Bytes : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers to/from Upstream Engine
DMA_us_PA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : out std_logic; -- obsolete
us_MWr_Param_Vec : out std_logic_vector(6-1 downto 0);
DMA_us_Status : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : in std_logic;
DMA_us_Tout : in std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : out std_logic;
usBDA_is_64b : out std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : out std_logic;
usLeng_Lo7b_True : out std_logic;
-- Upstream Control Signals
usDMA_Start : out std_logic;
usDMA_Stop : out std_logic;
usDMA_Start2 : out std_logic;
usDMA_Stop2 : out std_logic;
usDMA_Channel_Rst : out std_logic;
usDMA_Cmd_Ack : in std_logic;
-- MRd Channel Reset
MRd_Channel_Rst : out std_logic;
-- Tx module reset
Tx_Reset : out std_logic;
-- to Interrupts Module
Sys_IRQ : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System error and info
Tx_TimeOut : in std_logic;
Tx_wb_TimeOut : in std_logic;
Msg_Routing : out std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
pcie_link_width : in std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
cfg_dcommand : in std_logic_vector(16-1 downto 0);
ddr_sdram_ready : in std_logic;
-- Interrupt Generation Signals
IG_Reset : out std_logic;
IG_Host_Clear : out std_logic;
IG_Latency : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : in std_logic;
-- SDRAM and Wishbone paging registers
sdram_pg : out std_logic_vector(31 downto 0);
wb_pg : out std_logic_vector(31 downto 0);
-- Clock and reset
user_clk : in std_logic;
user_lnk_up : in std_logic;
user_reset : in std_logic
);
end Regs_Group;
architecture Behavioral of Regs_Group is
----------------------------------------------------------------------------
----------------------------------------------------------------------------
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
------ Delay signals
signal Regs_WrEn_r1 : std_logic;
signal Regs_WrAddr_r1 : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrMask_r1 : std_logic_vector(2-1 downto 0);
signal Regs_WrDin_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrEn_r2 : std_logic;
signal Regs_WrDin_r2 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_Wr_dma_V_hi_r2 : std_logic;
signal Regs_Wr_dma_nV_hi_r2 : std_logic;
signal Regs_Wr_dma_V_nE_hi_r2 : std_logic;
signal Regs_Wr_dma_V_lo_r2 : std_logic;
signal Regs_Wr_dma_nV_lo_r2 : std_logic;
signal Regs_Wr_dma_V_nE_lo_r2 : std_logic;
signal WrDin_r1_not_Zero_Hi : std_logic_vector(4-1 downto 0);
signal WrDin_r2_not_Zero_Hi : std_logic;
signal WrDin_r1_not_Zero_Lo : std_logic_vector(4-1 downto 0);
signal WrDin_r2_not_Zero_Lo : std_logic;
-- Calculation in advance, just for better timing
signal Regs_WrDin_Hi19b_True_hq_r2 : std_logic;
signal Regs_WrDin_Lo7b_True_hq_r2 : std_logic;
signal Regs_WrDin_Hi19b_True_lq_r2 : std_logic;
signal Regs_WrDin_Lo7b_True_lq_r2 : std_logic;
signal Regs_WrEnA_r1 : std_logic;
signal Regs_WrEnB_r1 : std_logic;
signal Regs_WrEnA_r2 : std_logic;
signal Regs_WrEnB_r2 : std_logic;
-- Register write mux signals
signal Reg_WrMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_WrMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
-- Signals for Tx reading
signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdQout_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register read mux signals
signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
-- Event Buffer
signal wb_FIFO_Rst_i : std_logic;
signal wb_FIFO_Rst_b1 : std_logic;
signal wb_FIFO_Rst_b2 : std_logic;
signal wb_FIFO_Rst_b3 : std_logic;
signal wb_FIFO_Rst_b4 : std_logic;
signal wb_FIFO_Rst_b5 : std_logic;
-- Downstream DMA registers
signal DMA_ds_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Upstream DMA registers
signal DMA_us_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System Interrupt Status/Control
signal Sys_IRQ_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- General Control and Status
signal Sys_Error_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Error_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Error_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal sdram_pg_i : std_logic_vector(32-1 downto 0);
signal sdram_pg_o_hi : std_logic_vector(32-1 downto 0);
signal sdram_pg_o_lo : std_logic_vector(32-1 downto 0);
signal wb_pg_i : std_logic_vector(32-1 downto 0);
signal wb_pg_o_hi : std_logic_vector(32-1 downto 0);
signal wb_pg_o_lo : std_logic_vector(32-1 downto 0);
-- Hardward version
signal HW_Version_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal HW_Version_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Signal as the source of interrupts
signal IG_Host_Clear_i : std_logic;
signal IG_Reset_i : std_logic;
-- Interrupt Generator Control
signal IG_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Latency
signal IG_Latency_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Latency_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Latency_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Assert number
signal IG_Num_Assert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Deassert number
signal IG_Num_Deassert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- IntClr character is written
signal Command_is_Host_iClr_Hi : std_logic;
signal Command_is_Host_iClr_Lo : std_logic;
-- Downstream Registers
signal DMA_ds_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Last_Ctrl_Word_ds : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
signal dsHA_is_64b_i : std_logic;
signal dsBDA_is_64b_i : std_logic;
-- Calculation in advance, for better timing
signal dsLeng_Hi19b_True_i : std_logic;
signal dsLeng_Lo7b_True_i : std_logic;
-- Downstream Control Signals
signal dsDMA_Start_i : std_logic;
signal dsDMA_Stop_i : std_logic;
signal dsDMA_Start2_i : std_logic;
signal dsDMA_Start2_r1 : std_logic;
signal dsDMA_Stop2_i : std_logic;
signal dsDMA_Channel_Rst_i : std_logic;
signal ds_Param_Modified : std_logic;
-- Upstream Registers
signal DMA_us_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Last_Ctrl_Word_us : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
signal usHA_is_64b_i : std_logic;
signal usBDA_is_64b_i : std_logic;
-- Calculation in advance, for better timing
signal usLeng_Hi19b_True_i : std_logic;
signal usLeng_Lo7b_True_i : std_logic;
-- Upstream Control Signals
signal usDMA_Start_i : std_logic;
signal usDMA_Stop_i : std_logic;
signal usDMA_Start2_i : std_logic;
signal usDMA_Start2_r1 : std_logic;
signal usDMA_Stop2_i : std_logic;
signal usDMA_Channel_Rst_i : std_logic;
signal us_Param_Modified : std_logic;
-- Reset character is written
signal Command_is_Reset_Hi : std_logic;
signal Command_is_Reset_Lo : std_logic;
-- MRd channel reset
signal MRd_Channel_Rst_i : std_logic;
-- Tx module reset
signal Tx_Reset_i : std_logic;
begin
-- Event buffer reset
wb_FIFO_Rst <= wb_FIFO_Rst_i;
-- MRd channel reset
MRd_Channel_Rst <= MRd_Channel_Rst_i;
-- Tx module reset
Tx_Reset <= Tx_Reset_i;
-- Upstream DMA engine reset
usDMA_Channel_Rst <= usDMA_Channel_Rst_i;
-- Downstream DMA engine reset
dsDMA_Channel_Rst <= dsDMA_Channel_Rst_i;
sdram_pg <= sdram_pg_i;
wb_pg <= wb_pg_i;
-- Upstream DMA registers
DMA_us_PA <= DMA_us_PA_i;
DMA_us_HA <= DMA_us_HA_i;
DMA_us_BDA <= DMA_us_BDA_i;
DMA_us_Length <= DMA_us_Length_i;
DMA_us_Control <= DMA_us_Control_i;
usDMA_BDA_eq_Null <= '0';
DMA_us_Status_i <= DMA_us_Status;
usHA_is_64b <= usHA_is_64b_i;
usBDA_is_64b <= usBDA_is_64b_i;
usLeng_Hi19b_True <= usLeng_Hi19b_True_i;
usLeng_Lo7b_True <= usLeng_Lo7b_True_i;
usDMA_Start <= usDMA_Start_i;
usDMA_Stop <= usDMA_Stop_i;
usDMA_Start2 <= usDMA_Start2_r1;
-- usDMA_Start2 <= usDMA_Start2_i;
usDMA_Stop2 <= usDMA_Stop2_i;
-- Downstream DMA registers
DMA_ds_PA <= DMA_ds_PA_i;
DMA_ds_HA <= DMA_ds_HA_i;
DMA_ds_BDA <= DMA_ds_BDA_i;
DMA_ds_Length <= DMA_ds_Length_i;
DMA_ds_Control <= DMA_ds_Control_i;
dsDMA_BDA_eq_Null <= '0';
DMA_ds_Status_i <= DMA_ds_Status;
dsHA_is_64b <= dsHA_is_64b_i;
dsBDA_is_64b <= dsBDA_is_64b_i;
dsLeng_Hi19b_True <= dsLeng_Hi19b_True_i;
dsLeng_Lo7b_True <= dsLeng_Lo7b_True_i;
dsDMA_Start <= dsDMA_Start_i;
dsDMA_Stop <= dsDMA_Stop_i;
dsDMA_Start2 <= dsDMA_Start2_r1;
-- dsDMA_Start2 <= dsDMA_Start2_i;
dsDMA_Stop2 <= dsDMA_Stop2_i;
-- Register to Interrupt handler module
Sys_IRQ <= Sys_IRQ_i;
-- Message routing method
Msg_Routing <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT);
-- us_MWr_TLP_Param
us_MWr_Param_Vec <= General_Control_i(13 downto 8);
-- ------------- Interrupt generator generation ----------------------
Gen_IG : if IMP_INT_GENERATOR generate
IG_Reset <= IG_Reset_i;
IG_Host_Clear <= IG_Host_Clear_i; -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR);
IG_Latency <= IG_Latency_i;
IG_Num_Assert_i <= IG_Num_Assert;
IG_Num_Deassert_i <= IG_Num_Deassert;
-- -----------------------------------------------
-- Synchronous Registered: IG_Control_i
SysReg_IntGen_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Control_i <= (others => '0');
IG_Reset_i <= '1';
IG_Host_Clear_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
IG_Reset_i <= Command_is_Reset_Hi;
IG_Host_Clear_i <= Command_is_Host_iClr_Hi;
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
IG_Reset_i <= Command_is_Reset_Lo;
IG_Host_Clear_i <= Command_is_Host_iClr_Lo;
else
IG_Control_i <= IG_Control_i;
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Latency_i
SysReg_IntGen_Latency :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Latency_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if IG_Reset_i = '1' then
IG_Latency_i <= (others => '0');
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
IG_Latency_i <= IG_Latency_i;
end if;
end if;
end process;
end generate;
NotGen_IG : if not IMP_INT_GENERATOR generate
IG_Reset <= '0';
IG_Host_Clear <= '0';
IG_Latency <= (others => '0');
IG_Num_Assert_i <= (others => '0');
IG_Num_Deassert_i <= (others => '0');
IG_Control_i <= (others => '0');
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
IG_Latency_i <= (others => '0');
end generate;
-- ----------------------------------------------
-- Synchronous Delay : Sys_IRQ_i
--
Synch_Delay_Sys_IRQ :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Sys_IRQ_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0)
<= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0)
and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0);
end if;
end process;
-- ----------------------------------------------
-- Registers writing
--
Regs_WrAddr_i <= Regs_WrAddrA and Regs_WrAddrB;
Regs_WrMask_i <= Regs_WrMaskA or Regs_WrMaskB;
Regs_WrDin_i <= Regs_WrDinA or
(Regs_WrDinB(C_DBUS_WIDTH/2-1 downto 0) & Regs_WrDinB(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2));
-- ----------------------------------------------
-- Registers reading
--
Regs_RdAddr_i <= Regs_RdAddr;
Regs_RdQout <= Regs_RdQout_i;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrEn
--
Synch_Delay_Regs_WrEn :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_WrEn_r1 <= Regs_WrEnA or Regs_WrEnB;
Regs_WrEn_r2 <= Regs_WrEn_r1;
Regs_WrEnA_r1 <= Regs_WrEnA;
Regs_WrEnA_r2 <= Regs_WrEnA_r1;
Regs_WrEnB_r1 <= Regs_WrEnB;
Regs_WrEnB_r2 <= Regs_WrEnB_r1;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrAddr
--
Synch_Delay_Regs_WrAddr :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_WrAddr_r1 <= Regs_WrAddr_i;
Regs_WrMask_r1 <= Regs_WrMask_i;
end if;
end process;
-- ----------------------------------------------------
-- Synchronous Delay : dsDMA_Start2
-- usDMA_Start2
-- (Special recipe for 64-bit successive descriptors)
--
Synch_Delay_DMA_Start2 :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
dsDMA_Start2_r1 <= dsDMA_Start2_i and not dsDMA_Cmd_Ack;
usDMA_Start2_r1 <= usDMA_Start2_i and not usDMA_Cmd_Ack;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrDin_i
--
Synch_Delay_Regs_WrDin :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_WrDin_r1 <= Regs_WrDin_i;
Regs_WrDin_r2 <= Regs_WrDin_r1;
if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then
WrDin_r1_not_Zero_Hi(3) <= '0';
else
WrDin_r1_not_Zero_Hi(3) <= '1';
end if;
if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then
WrDin_r1_not_Zero_Hi(2) <= '0';
else
WrDin_r1_not_Zero_Hi(2) <= '1';
end if;
if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then
WrDin_r1_not_Zero_Hi(1) <= '0';
else
WrDin_r1_not_Zero_Hi(1) <= '1';
end if;
if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then
WrDin_r1_not_Zero_Hi(0) <= '0';
else
WrDin_r1_not_Zero_Hi(0) <= '1';
end if;
if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then
WrDin_r2_not_Zero_Hi <= '0';
else
WrDin_r2_not_Zero_Hi <= '1';
end if;
if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then
WrDin_r1_not_Zero_Lo(3) <= '0';
else
WrDin_r1_not_Zero_Lo(3) <= '1';
end if;
if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then
WrDin_r1_not_Zero_Lo(2) <= '0';
else
WrDin_r1_not_Zero_Lo(2) <= '1';
end if;
if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then
WrDin_r1_not_Zero_Lo(1) <= '0';
else
WrDin_r1_not_Zero_Lo(1) <= '1';
end if;
if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then
WrDin_r1_not_Zero_Lo(0) <= '0';
else
WrDin_r1_not_Zero_Lo(0) <= '1';
end if;
if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then
WrDin_r2_not_Zero_Lo <= '0';
else
WrDin_r2_not_Zero_Lo <= '1';
end if;
end if;
end process;
-- -----------------------------------------------------------
-- Synchronous Delay : DMA Commands Write Valid and not End
--
Synch_Delay_dmaCmd_Wr_Valid_and_End :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_Wr_dma_V_hi_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32);
Regs_Wr_dma_nV_hi_r2 <= Regs_WrEn_r1
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32);
Regs_Wr_dma_V_nE_hi_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32);
Regs_Wr_dma_V_lo_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID);
Regs_Wr_dma_nV_lo_r2 <= Regs_WrEn_r1
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID);
Regs_Wr_dma_V_nE_lo_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END);
end if;
end process;
-- ------------------------------------------------
-- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2
-- Regs_WrDin_Lo7b_True_r2 x2
--
Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
then
Regs_WrDin_Hi19b_True_hq_r2 <= '0';
else
Regs_WrDin_Hi19b_True_hq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
then -- ! Lowest 2 bits ignored !
Regs_WrDin_Lo7b_True_hq_r2 <= '0';
else
Regs_WrDin_Lo7b_True_hq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
= C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
then
Regs_WrDin_Hi19b_True_lq_r2 <= '0';
else
Regs_WrDin_Hi19b_True_lq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
then -- ! Lowest 2 bits ignored !
Regs_WrDin_Lo7b_True_lq_r2 <= '0';
else
Regs_WrDin_Lo7b_True_lq_r2 <= '1';
end if;
end if;
end process;
-- ---------------------------------------
--
Write_DMA_Registers_Mux :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Reg_WrMuxer_Hi <= (others => '0');
Reg_WrMuxer_Lo <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Hi(0) <= not Regs_WrMask_r1(1);
else
Reg_WrMuxer_Hi(0) <= '0';
end if;
for k in 1 to C_NUM_OF_ADDRESSES-1 loop
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Hi(k) <= not Regs_WrMask_r1(1);
else
Reg_WrMuxer_Hi(k) <= '0';
end if;
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Lo(k) <= not Regs_WrMask_r1(0);
else
Reg_WrMuxer_Lo(k) <= '0';
end if;
end loop;
end if;
end process;
-- -----------------------------------------------
-- System Interrupt Status Control
-- -----------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: Sys_Int_Enable_i
SysReg_Sys_Int_Enable :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Sys_Int_Enable_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN) = '1'
then
Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN) = '1'
then
Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
Sys_Int_Enable_i <= Sys_Int_Enable_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- DDR SDRAM address page
-- -----------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: wb_pg
SDRAM_Addr_page :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
sdram_pg_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_SDRAM_PG) = '1'
then
sdram_pg_i <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_SDRAM_PG) = '1'
then
sdram_pg_i <= Regs_WrDin_r2(32-1 downto 0);
else
sdram_pg_i <= sdram_pg_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Wishbone endpoint address page
-- -----------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: wb_pg_i
Wishbone_addr_page :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
wb_pg_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_WB_PG) = '1'
then
wb_pg_i <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_WB_PG) = '1'
then
wb_pg_i <= Regs_WrDin_r2(32-1 downto 0);
else
wb_pg_i <= wb_pg_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- System General Control Register
-- -----------------------------------------------
-- -----------------------------------------------
-- Synchronous Registered: General_Control
SysReg_General_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
General_Control_i <= (others => '0');
General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT)
<= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT
downto C_TLP_TYPE_BIT_BOT);
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL) = '1'
then
General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL) = '1'
then
General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
General_Control_i <= General_Control_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Control_i
SysReg_IntGen_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Control_i <= (others => '0');
IG_Reset_i <= '1';
IG_Host_Clear_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
IG_Reset_i <= Command_is_Reset_Hi;
IG_Host_Clear_i <= Command_is_Host_iClr_Hi;
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL) = '1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
IG_Reset_i <= Command_is_Reset_Lo;
IG_Host_Clear_i <= Command_is_Host_iClr_Lo;
else
IG_Control_i <= IG_Control_i;
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Latency_i
SysReg_IntGen_Latency :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
IG_Latency_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if IG_Reset_i = '1' then
IG_Latency_i <= (others => '0');
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY) = '1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
IG_Latency_i <= IG_Latency_i;
end if;
end if;
end process;
-- ------------------------------------------------------
-- DMA Upstream Registers
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_PA_i
RxTrn_DMA_us_PA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_PA_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_PA_i <= (others => '0');
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH) = '1' then
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH) = '1' then
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32);
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) = '1' then
DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) = '1' then
DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_PA_i(32-1 downto 0) <= DMA_us_PA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_HA_i
RxTrn_DMA_us_HA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_HA_i <= (others => '1');
usHA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_HA_i <= (others => '1');
usHA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) = '1' then
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32);
usHA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) = '1' then
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
usHA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32);
usHA_is_64b_i <= usHA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) = '1' then
DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) = '1' then
DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_HA_i(32-1 downto 0) <= DMA_us_HA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_BDA_i
Syn_Output_DMA_us_BDA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_BDA_i <= (others => '0');
usBDA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_BDA_i <= (others => '0');
usBDA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH) = '1' then
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
usBDA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH) = '1' then
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
usBDA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32);
usBDA_is_64b_i <= usBDA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL) = '1' then
DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL) = '1' then
DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_BDA_i(32-1 downto 0) <= DMA_us_BDA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_Length_i
RxTrn_DMA_us_Length :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_Length_i <= (others => '0');
usLeng_Hi19b_True_i <= '0';
usLeng_Lo7b_True_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_Length_i <= (others => '0');
usLeng_Hi19b_True_i <= '0';
usLeng_Lo7b_True_i <= '0';
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG) = '1' then
DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG) = '1' then
DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2;
else
DMA_us_Length_i <= DMA_us_Length_i;
usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i;
usLeng_Lo7b_True_i <= usLeng_Lo7b_True_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous us_Param_Modified
SynReg_us_Param_Modified :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
us_Param_Modified <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1'
or usDMA_Start_i = '1'
or usDMA_Start2_i = '1'
then
us_Param_Modified <= '0';
elsif Regs_WrEn_r2 = '1' and
(
Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG) = '1'
)
then
us_Param_Modified <= '1';
else
us_Param_Modified <= us_Param_Modified;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Control_i
Syn_Output_DMA_us_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_Control_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
elsif Regs_Wr_dma_nV_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
elsif Regs_Wr_dma_nV_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
else
DMA_us_Control_i <= DMA_us_Control_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Register: Last_Ctrl_Word_us
Hold_Last_Ctrl_Word_us :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
elsif Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
elsif Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified = '1'
and usDMA_Stop_i = '0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
else
Last_Ctrl_Word_us <= Last_Ctrl_Word_us;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Start_Stop
Syn_Output_DMA_us_Start_Stop :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
usDMA_Start_i <= '0';
usDMA_Stop_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not usDMA_Stop_i
and not Command_is_Reset_Hi
and us_Param_Modified;
usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not Command_is_Reset_Hi;
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not usDMA_Stop_i
and not Command_is_Reset_Lo
and us_Param_Modified;
usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not Command_is_Reset_Lo;
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
and us_Param_Modified;
usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
and us_Param_Modified;
usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif usDMA_Cmd_Ack = '1'
then
usDMA_Start_i <= '0';
usDMA_Stop_i <= usDMA_Stop_i;
else
usDMA_Start_i <= usDMA_Start_i;
usDMA_Stop_i <= usDMA_Stop_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Start2_Stop2
Syn_Output_DMA_us_Start2_Stop2 :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= '0';
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= '0';
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '0'
then
usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif usDMA_Cmd_Ack = '1' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= usDMA_Stop2_i;
else
usDMA_Start2_i <= usDMA_Start2_i;
usDMA_Stop2_i <= usDMA_Stop2_i;
end if;
end if;
end process;
-- ------------------------------------------------------
-- DMA Downstream Registers
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: DMA_ds_PA_i
RxTrn_DMA_ds_PA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_PA_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_PA_i <= (others => '0');
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH) = '1' then
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH) = '1' then
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32);
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) = '1' then
DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) = '1' then
DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_PA_i(32-1 downto 0) <= DMA_ds_PA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_ds_HA_i
RxTrn_DMA_ds_HA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_HA_i <= (others => '1');
dsHA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_HA_i <= (others => '1');
dsHA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) = '1' then
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsHA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) = '1' then
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
dsHA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32);
dsHA_is_64b_i <= dsHA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) = '1' then
DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) = '1' then
DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_HA_i(32-1 downto 0) <= DMA_ds_HA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_BDA_i
Syn_Output_DMA_ds_BDA :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_BDA_i <= (others => '0');
dsBDA_is_64b_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_BDA_i <= (others => '0');
dsBDA_is_64b_i <= '0';
else
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH) = '1' then
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsBDA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH) = '1' then
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
dsBDA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32);
dsBDA_is_64b_i <= dsBDA_is_64b_i;
end if;
if Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL) = '1' then
DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL) = '1' then
DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_BDA_i(32-1 downto 0) <= DMA_ds_BDA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- Synchronous Registered: DMA_ds_Length_i
RxTrn_DMA_ds_Length :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_Length_i <= (others => '0');
dsLeng_Hi19b_True_i <= '0';
dsLeng_Lo7b_True_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_Length_i <= (others => '0');
dsLeng_Hi19b_True_i <= '0';
dsLeng_Lo7b_True_i <= '0';
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG) = '1' then
DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2;
elsif Regs_WrEn_r2 = '1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG) = '1' then
DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2;
else
DMA_ds_Length_i <= DMA_ds_Length_i;
dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i;
dsLeng_Lo7b_True_i <= dsLeng_Lo7b_True_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous ds_Param_Modified
SynReg_ds_Param_Modified :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
ds_Param_Modified <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1'
or dsDMA_Start_i = '1'
or dsDMA_Start2_i = '1'
then
ds_Param_Modified <= '0';
elsif Regs_WrEn_r2 = '1' and
(
-- Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1'
-- or
Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL) = '1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG) = '1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG) = '1'
)
then
ds_Param_Modified <= '1';
else
ds_Param_Modified <= ds_Param_Modified;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Control_i
Syn_Output_DMA_ds_Control :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_Control_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
elsif Regs_Wr_dma_nV_Hi_r2 = '1'
and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1')
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_ds_Control_i <= Last_Ctrl_Word_ds;
else
DMA_ds_Control_i <= DMA_ds_Control_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Register: Last_Ctrl_Word_ds
Hold_Last_Ctrl_Word_ds :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
elsif Regs_Wr_dma_V_nE_Hi_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and ds_Param_Modified = '1'
and dsDMA_Stop_i = '0'
then
Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
else
Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Start_Stop
Syn_Output_DMA_ds_Start_Stop :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
dsDMA_Start_i <= '0';
dsDMA_Stop_i <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not dsDMA_Stop_i
and not Command_is_Reset_Hi
and ds_Param_Modified;
dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not Command_is_Reset_Hi;
elsif Regs_WrEnA_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not dsDMA_Stop_i
and not Command_is_Reset_Lo
and ds_Param_Modified;
dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not Command_is_Reset_Lo;
elsif Regs_WrEnA_r2 = '1'
and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1')
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '0'
then
dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END)
and ds_Param_Modified;
dsDMA_Stop_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif dsDMA_Cmd_Ack = '1'
then
dsDMA_Start_i <= '0';
dsDMA_Stop_i <= dsDMA_Stop_i;
else
dsDMA_Start_i <= dsDMA_Start_i;
dsDMA_Stop_i <= dsDMA_Stop_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Start2_Stop2
Syn_Output_DMA_ds_Start2_Stop2 :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= '0';
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= '0';
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '1'
then
dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '1'
then
dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32) = '0'
then
dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnB_r2 = '1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID) = '0'
then
dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif dsDMA_Cmd_Ack = '1' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= dsDMA_Stop2_i;
else
dsDMA_Start2_i <= dsDMA_Start2_i;
dsDMA_Stop2_i <= dsDMA_Stop2_i;
end if;
end if;
end process;
------------------------------------------------------------------------
-- Reset signals --
------------------------------------------------------------------------
-- --------------------------------------
-- Identification: Command_is_Reset
--
Synch_Capture_Command_is_Reset :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Command_is_Reset_Hi <= '0';
Command_is_Reset_Lo <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32) = C_CHANNEL_RST_BITS then
Command_is_Reset_Hi <= '1';
else
Command_is_Reset_Hi <= '0';
end if;
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0) = C_CHANNEL_RST_BITS then
Command_is_Reset_Lo <= '1';
else
Command_is_Reset_Lo <= '0';
end if;
end if;
end process;
-- --------------------------------------
-- Identification: Command_is_Host_iClr
--
Synch_Capture_Command_is_Host_iClr :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Command_is_Host_iClr_Hi <= '0';
Command_is_Host_iClr_Lo <= '0';
elsif user_clk'event and user_clk = '1' then
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32) = C_HOST_ICLR_BITS then
Command_is_Host_iClr_Hi <= '1';
else
Command_is_Host_iClr_Hi <= '0';
end if;
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0) = C_HOST_ICLR_BITS then
Command_is_Host_iClr_Lo <= '1';
else
Command_is_Host_iClr_Lo <= '0';
end if;
end if;
end process;
-------------------------------------------
-- Synchronous output: usDMA_Channel_Rst_i
--
Syn_Output_usDMA_Channel_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
usDMA_Channel_Rst_i <= '1';
elsif user_clk'event and user_clk = '1' then
usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
and Command_is_Reset_Hi
)
or (Regs_Wr_dma_V_LO_r2
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
and Command_is_Reset_Lo
);
end if;
end process;
-------------------------------------------
-- Synchronous output: dsDMA_Channel_Rst_i
--
Syn_Output_dsDMA_Channel_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
dsDMA_Channel_Rst_i <= '1';
elsif user_clk'event and user_clk = '1' then
dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
and Command_is_Reset_Hi
)
or
(Regs_Wr_dma_V_Lo_r2
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
and Command_is_Reset_Lo
);
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: MRd_Channel_Rst_i
--
Syn_Output_MRd_Channel_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
MRd_Channel_Rst_i <= '1';
elsif user_clk'event and user_clk = '1' then
MRd_Channel_Rst_i <= Regs_WrEn_r2
and (
(Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL)
and Command_is_Reset_Hi)
or
(Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL)
and Command_is_Reset_Lo)
);
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: Tx_Reset_i
--
Syn_Output_Tx_Reset :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Tx_Reset_i <= '1';
elsif user_clk'event and user_clk = '1' then
Tx_Reset_i <= Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL)
and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL)
and Command_is_Reset_Lo));
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: wb_FIFO_Rst_i
--
Syn_Output_wb_FIFO_Rst :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
wb_FIFO_Rst_i <= '1';
wb_FIFO_Rst_b5 <= '1';
wb_FIFO_Rst_b4 <= '1';
wb_FIFO_Rst_b3 <= '1';
wb_FIFO_Rst_b2 <= '1';
wb_FIFO_Rst_b1 <= '1';
elsif user_clk'event and user_clk = '1' then
wb_FIFO_Rst_i <= wb_FIFO_Rst_b1 or wb_FIFO_Rst_b2 or wb_FIFO_Rst_b3 or wb_FIFO_Rst_b4 or wb_FIFO_Rst_b5;
wb_FIFO_Rst_b5 <= wb_FIFO_Rst_b4;
wb_FIFO_Rst_b4 <= wb_FIFO_Rst_b3;
wb_FIFO_Rst_b3 <= wb_FIFO_Rst_b2;
wb_FIFO_Rst_b2 <= wb_FIFO_Rst_b1;
wb_FIFO_Rst_b1 <= Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON)
and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON)
and Command_is_Reset_Lo));
end if;
end process;
-- -----------------------------------------------
-- Synchronous Calculation: DMA_us_Transf_Bytes
--
Syn_Calc_DMA_us_Transf_Bytes :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_us_Transf_Bytes_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_Transf_Bytes_i <= (others => '0');
elsif us_DMA_Bytes_Add = '1' then
DMA_us_Transf_Bytes_i(32-1 downto 0) <= DMA_us_Transf_Bytes_i(32-1 downto 0) + us_DMA_Bytes;
else
DMA_us_Transf_Bytes_i <= DMA_us_Transf_Bytes_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Calculation: DMA_ds_Transf_Bytes
--
Syn_Calc_DMA_ds_Transf_Bytes :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
DMA_ds_Transf_Bytes_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_Transf_Bytes_i <= (others => '0');
elsif ds_DMA_Bytes_Add = '1' then
DMA_ds_Transf_Bytes_i(32-1 downto 0) <= DMA_ds_Transf_Bytes_i(32-1 downto 0) + ds_DMA_Bytes;
else
DMA_ds_Transf_Bytes_i <= DMA_ds_Transf_Bytes_i;
end if;
end if;
end process;
----------------------------------------------------------
--------------- Tx reading registers -------------------
----------------------------------------------------------
----------------------------------------------------------
-- Synch Register: Read Selection
--
Tx_DMA_Reg_RdMuxer :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Reg_RdMuxer_Hi <= (others => '0');
Reg_RdMuxer_Lo <= (others => '0');
elsif user_clk'event and user_clk = '1' then
for k in 0 to C_NUM_OF_ADDRESSES-1 loop
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) = C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
and Regs_RdAddr_i(2-1 downto 0) = "00"
then
Reg_RdMuxer_Hi(k) <= '1';
else
Reg_RdMuxer_Hi(k) <= '0';
end if;
end loop;
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) = C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2) = C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2)
and Regs_RdAddr_i(2-1 downto 0) = "00"
then
Reg_RdMuxer_Lo(0) <= '1';
else
Reg_RdMuxer_Lo(0) <= '0';
end if;
for k in 1 to C_NUM_OF_ADDRESSES-1 loop
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) = C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2) = CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
and Regs_RdAddr_i(2-1 downto 0) = "00"
then
Reg_RdMuxer_Lo(k) <= '1';
else
Reg_RdMuxer_Lo(k) <= '0';
end if;
end loop;
end if;
end process;
-- -------------------------------------------------------
--
Sys_Int_Status_i <= (
CINT_BIT_TX_DDR_TOUT_ISR => tx_timeout,
CINT_BIT_TX_WB_TOUT_ISR => tx_wb_timeout,
CINT_BIT_DSTOUT_IN_ISR => DMA_ds_Tout ,
CINT_BIT_USTOUT_IN_ISR => DMA_us_Tout ,
CINT_BIT_INTGEN_IN_ISR => IG_Asserting,
CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done ,
CINT_BIT_US_DONE_IN_ISR => DMA_us_Done ,
others => '0'
);
--------------------------------------------------------------------------
-- Upstream Registers
--------------------------------------------------------------------------
-- Peripheral Address Start point
DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH) = '1'
else (others => '0');
DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH) = '1'
else (others => '0');
DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH) = '1'
else (others => '0');
DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL) = '1'
else (others => '0');
-- Length
DMA_us_Length_o_Hi(32-1 downto 0)
<= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG) = '1'
else (others => '0');
-- Control word
DMA_us_Control_o_Hi(32-1 downto 0)
<= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_us_Status_o_Hi(32-1 downto 0)
<= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_us_Transf_Bytes_o_Hi(32-1 downto 0)
<= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC) = '1'
else (others => '0');
-- Peripheral Address Start point
DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH) = '1'
else (others => '0');
DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH) = '1'
else (others => '0');
DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH) = '1'
else (others => '0');
DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL) = '1'
else (others => '0');
-- Length
DMA_us_Length_o_Lo(32-1 downto 0)
<= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG) = '1'
else (others => '0');
-- Control word
DMA_us_Control_o_Lo(32-1 downto 0)
<= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_us_Status_o_Lo(32-1 downto 0)
<= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_us_Transf_Bytes_o_Lo(32-1 downto 0)
<= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- Downstream Registers
--------------------------------------------------------------------------
-- Peripheral Address Start point
DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH) = '1'
else (others => '0');
DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH) = '1'
else (others => '0');
DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH) = '1'
else (others => '0');
DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL) = '1'
else (others => '0');
-- Length
DMA_ds_Length_o_Hi(32-1 downto 0)
<= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG) = '1'
else (others => '0');
-- Control word
DMA_ds_Control_o_Hi(32-1 downto 0)
<= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_ds_Status_o_Hi(32-1 downto 0)
<= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0)
<= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC) = '1'
else (others => '0');
-- Peripheral Address Start point
DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH) = '1'
else (others => '0');
DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL) = '1'
else (others => '0');
-- Host Address Start point
DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH) = '1'
else (others => '0');
DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL) = '1'
else (others => '0');
-- Next Descriptor Address
DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH) = '1'
else (others => '0');
DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL) = '1'
else (others => '0');
-- Length
DMA_ds_Length_o_Lo(32-1 downto 0)
<= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG) = '1'
else (others => '0');
-- Control word
DMA_ds_Control_o_Lo(32-1 downto 0)
<= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL) = '1'
else (others => '0');
-- Status (Read only)
DMA_ds_Status_o_Lo(32-1 downto 0)
<= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA) = '1'
else (others => '0');
-- Tranferred bytes (Read only)
DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0)
<= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- System Interrupt Status
--------------------------------------------------------------------------
Sys_Int_Status_o_Hi(32-1 downto 0)
<= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT) = '1'
else (others => '0');
Sys_Int_Enable_o_Hi(32-1 downto 0)
<= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN) = '1'
else (others => '0');
Sys_Int_Status_o_Lo(32-1 downto 0)
<= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT) = '1'
else (others => '0');
Sys_Int_Enable_o_Lo(32-1 downto 0)
<= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN) = '1'
else (others => '0');
-- ----------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------------
Gen_IG_Read : if IMP_INT_GENERATOR generate
--------------------------------------------------------------------------
-- Interrupt Generator Latency
--------------------------------------------------------------------------
IG_Latency_o_Hi(32-1 downto 0)
<= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY) = '1'
else (others => '0');
IG_Latency_o_Lo(32-1 downto 0)
<= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- Interrupt Generator Statistics
--------------------------------------------------------------------------
IG_Num_Assert_o_Hi(32-1 downto 0)
<= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT) = '1'
else (others => '0');
IG_Num_Deassert_o_Hi(32-1 downto 0)
<= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT) = '1'
else (others => '0');
IG_Num_Assert_o_Lo(32-1 downto 0)
<= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT) = '1'
else (others => '0');
IG_Num_Deassert_o_Lo(32-1 downto 0)
<= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT) = '1'
else (others => '0');
end generate;
NotGen_IG_Read : if not IMP_INT_GENERATOR generate
IG_Latency_o_Hi(32-1 downto 0) <= (others => '0');
IG_Latency_o_Lo(32-1 downto 0) <= (others => '0');
IG_Num_Assert_o_Hi(32-1 downto 0) <= (others => '0');
IG_Num_Deassert_o_Hi(32-1 downto 0) <= (others => '0');
IG_Num_Assert_o_Lo(32-1 downto 0) <= (others => '0');
IG_Num_Deassert_o_Lo(32-1 downto 0) <= (others => '0');
end generate;
--------------------------------------------------------------------------
-- System Error
--------------------------------------------------------------------------
Synch_Sys_Error_i :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Sys_Error_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER) <= Tx_TimeOut;
Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER) <= Tx_wb_TimeOut;
end if;
end process;
--------------------------------------------------------------------------
-- General Status and Control
--------------------------------------------------------------------------
Synch_General_Status_i :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
General_Status_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
General_Status_i(32-1 downto 32-16) <= cfg_dcommand;
General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT) <= pcie_link_width;
General_Status_i(CINT_BIT_DDR_RDY_GSR) <= ddr_sdram_ready;
end if;
end process;
Sys_Error_o_Hi(32-1 downto 0)
<= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR) = '1'
else (others => '0');
General_Status_o_Hi(32-1 downto 0)
<= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS) = '1'
else (others => '0');
General_Control_o_Hi(32-1 downto 0)
<= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL) = '1'
else (others => '0');
sdram_pg_o_hi
<= sdram_pg_i when Reg_RdMuxer_Hi(CINT_ADDR_SDRAM_PG) = '1'
else (others => '0');
wb_pg_o_hi
<= wb_pg_i when Reg_RdMuxer_Hi(CINT_ADDR_WB_PG) = '1'
else (others => '0');
Sys_Error_o_Lo(32-1 downto 0)
<= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR) = '1'
else (others => '0');
General_Status_o_Lo(32-1 downto 0)
<= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS) = '1'
else (others => '0');
General_Control_o_Lo(32-1 downto 0)
<= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL) = '1'
else (others => '0');
sdram_pg_o_lo
<= sdram_pg_i when Reg_RdMuxer_Lo(CINT_ADDR_SDRAM_PG) = '1'
else (others => '0');
wb_pg_o_lo
<= wb_pg_i when Reg_RdMuxer_Lo(CINT_ADDR_WB_PG) = '1'
else (others => '0');
--------------------------------------------------------------------------
-- Hardware version
--------------------------------------------------------------------------
HW_Version_o_Hi(32-1 downto 0)
<= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION) = '1'
else (others => '0');
HW_Version_o_Lo(32-1 downto 0)
<= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION) = '1'
else (others => '0');
-----------------------------------------------------
-- Sequential : Regs_RdQout_i
--
Synch_Regs_RdQout :
process (user_clk, user_lnk_up)
begin
if user_lnk_up = '0' then
Regs_RdQout_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
Regs_RdQout_i(64-1 downto 32) <=
HW_Version_o_Hi (32-1 downto 0)
or Sys_Error_o_Hi (32-1 downto 0)
or General_Status_o_Hi (32-1 downto 0)
or General_Control_o_Hi(32-1 downto 0)
or sdram_pg_o_hi(32-1 downto 0)
or wb_pg_o_hi(32-1 downto 0)
or Sys_Int_Status_o_Hi (32-1 downto 0)
or Sys_Int_Enable_o_Hi (32-1 downto 0)
-- or DMA_us_PA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_PA_o_Hi (32-1 downto 0)
or DMA_us_HA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_HA_o_Hi (32-1 downto 0)
or DMA_us_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_BDA_o_Hi (32-1 downto 0)
or DMA_us_Length_o_Hi (32-1 downto 0)
or DMA_us_Control_o_Hi (32-1 downto 0)
or DMA_us_Status_o_Hi (32-1 downto 0)
or DMA_us_Transf_Bytes_o_Hi (32-1 downto 0)
-- or DMA_ds_PA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_PA_o_Hi (32-1 downto 0)
or DMA_ds_HA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_HA_o_Hi (32-1 downto 0)
or DMA_ds_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_BDA_o_Hi (32-1 downto 0)
or DMA_ds_Length_o_Hi (32-1 downto 0)
or DMA_ds_Control_o_Hi (32-1 downto 0)
or DMA_ds_Status_o_Hi (32-1 downto 0)
or DMA_ds_Transf_Bytes_o_Hi (32-1 downto 0)
or IG_Latency_o_Hi (32-1 downto 0)
or IG_Num_Assert_o_Hi (32-1 downto 0)
or IG_Num_Deassert_o_Hi(32-1 downto 0);
Regs_RdQout_i(32-1 downto 0) <=
HW_Version_o_Lo (32-1 downto 0)
or Sys_Error_o_Lo (32-1 downto 0)
or General_Status_o_Lo (32-1 downto 0)
or General_Control_o_Lo(32-1 downto 0)
or sdram_pg_o_lo(32-1 downto 0)
or wb_pg_o_lo(32-1 downto 0)
or Sys_Int_Status_o_Lo (32-1 downto 0)
or Sys_Int_Enable_o_Lo (32-1 downto 0)
-- or DMA_us_PA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_PA_o_Lo (32-1 downto 0)
or DMA_us_HA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_HA_o_Lo (32-1 downto 0)
or DMA_us_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_BDA_o_Lo (32-1 downto 0)
or DMA_us_Length_o_Lo (32-1 downto 0)
or DMA_us_Control_o_Lo (32-1 downto 0)
or DMA_us_Status_o_Lo (32-1 downto 0)
or DMA_us_Transf_Bytes_o_Lo (32-1 downto 0)
-- or DMA_ds_PA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_PA_o_Lo (32-1 downto 0)
or DMA_ds_HA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_HA_o_Lo (32-1 downto 0)
or DMA_ds_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_BDA_o_Lo (32-1 downto 0)
or DMA_ds_Length_o_Lo (32-1 downto 0)
or DMA_ds_Control_o_Lo (32-1 downto 0)
or DMA_ds_Status_o_Lo (32-1 downto 0)
or DMA_ds_Transf_Bytes_o_Lo (32-1 downto 0)
or IG_Latency_o_Lo (32-1 downto 0)
or IG_Num_Assert_o_Lo (32-1 downto 0)
or IG_Num_Deassert_o_Lo(32-1 downto 0);
end if;
end process;
end Behavioral;
|
lgpl-3.0
|
f8818ddaac61cac99397972b008319ab
| 0.546344 | 2.933848 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd
| 1 | 5,752 |
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity fmc150_dac_if is
port
(
rst_i : in std_logic;
clk_dac_i : in std_logic;
clk_dac_2x_i : in std_logic;
dac_din_c_i : in std_logic_vector(15 downto 0);
dac_din_d_i : in std_logic_vector(15 downto 0);
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic
);
end fmc150_dac_if;
architecture rtl of fmc150_dac_if is
signal frame : std_logic;
signal io_rst : std_logic;
signal dac_dclk_prebuf : std_logic;
signal dac_data_prebuf : std_logic_vector(7 downto 0);
signal dac_frame_prebuf : std_logic;
begin
---------------------------------------------------------------------------------------------------
-- Reset sequence
----------------------------------------------------------------------------------------------------
process (rst_i, clk_dac_i)
variable cnt : integer range 0 to 1023 := 0;
begin
if (rst_i = '0') then
cnt := 0;
io_rst <= '0';
frame <= '0';
txenable_o <= '0';
elsif (rising_edge(clk_dac_i)) then
if (cnt < 1023) then
cnt := cnt + 1;
else
cnt := cnt;
end if;
-- The OSERDES blocks are synchronously reset for one clock cycle...
if (cnt = 255) then
io_rst <= '1';
else
io_rst <= '0';
end if;
-- Then a frame pulse is transmitted to the DAC...
if (cnt = 511) then
frame <= '1';
else
frame <= '0';
end if;
-- Finally the TX enable for the DAC can be pulled high.
if (cnt = 1023) then
txenable_o <= '1';
end if;
end if;
end process;
-- Output SERDES and LVDS buffer for DAC clock
oserdes_clock : oserdes
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 1
)
port map (
oq => dac_dclk_prebuf,
shiftout1 => open,
shiftout2 => open,
tq => open,
clk => clk_dac_2x_i,
clkdiv => clk_dac_i,
d1 => '1',
d2 => '0',
d3 => '1',
d4 => '0',
d5 => '0',
d6 => '0',
oce => '1',
rev => '0',
shiftin1 => '0',
shiftin2 => '0',
sr => io_rst,
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0'
);
-- Output buffer
obufds_clock : obufds_lvdsext_25
port map (
i => dac_dclk_prebuf,
o => dac_dclk_p_o,
ob => dac_dclk_n_o
);
-- Output serdes and LVDS buffers for DAC data
dac_data: for i in 0 to 7 generate
oserdes_data : oserdes
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 1
)
port map (
oq => dac_data_prebuf(i),
shiftout1 => open,
shiftout2 => open,
tq => open,
clk => clk_dac_2x_i,
clkdiv => clk_dac_i,
d1 => dac_din_c_i(i + 8),
d2 => dac_din_c_i(i),
d3 => dac_din_d_i(i + 8),
d4 => dac_din_d_i(i),
d5 => '0',
d6 => '0',
oce => '1',
rev => '0',
shiftin1 => '0',
shiftin2 => '0',
sr => io_rst,
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0'
);
--output buffers
obufds_data : obufds_lvdsext_25
port map (
i => dac_data_prebuf(i),
o => dac_data_p_o(i),
ob => dac_data_n_o(i)
);
end generate;
-- Output serdes and LVDS buffer for DAC frame
oserdes_frame : oserdes
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 1
)
port map (
oq => dac_frame_prebuf,
shiftout1 => open,
shiftout2 => open,
tq => open,
clk => clk_dac_2x_i,
clkdiv => clk_dac_i,
d1 => frame,
d2 => frame,
d3 => frame,
d4 => frame,
d5 => '0',
d6 => '0',
oce => '1',
rev => '0',
shiftin1 => '0',
shiftin2 => '0',
sr => io_rst,
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0'
);
--output buffer
obufds_frame : obufds_lvdsext_25
port map (
i => dac_frame_prebuf,
o => dac_frame_p_o,
ob => dac_frame_n_o
);
end rtl;
|
lgpl-3.0
|
9a38adcb6ec2d1200b8098c928121387
| 0.386996 | 3.539692 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/mixers.vhd
| 2 | 5,305 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.msx_pack.all;
entity mixers is
port (
clock_i : in std_logic;
reset_i : in std_logic;
volumes_i : in volumes_t;
beep_i : in std_logic;
ear_i : in std_logic;
audio_scc_i : in signed(14 downto 0);
audio_psg_i : in unsigned(7 downto 0);
jt51_left_i : in signed(15 downto 0);
jt51_right_i : in signed(15 downto 0);
opll_mo_i : in signed(12 downto 0) := (others => '0');
opll_ro_i : in signed(12 downto 0) := (others => '0');
audio_mix_l_o : out signed(15 downto 0);
audio_mix_r_o : out signed(15 downto 0)
);
end mixers;
-- 32767 0111111111111111
--
-- 16384 0100000000000000
--
-- 1 0000000000000001
-- 0 0000000000000000
-- -1 1111111111111111
--
-- -16384 1100000000000000
--
-- -32767 1000000000000001
-- -32768 1000000000000000
architecture Behavioral of mixers is
constant beep_con_c : signed(15 downto 0) := to_signed(16383, 16);
constant ear_con_c : signed(15 downto 0) := to_signed(16383, 16);
signal pcm_l_s : signed(15 downto 0);
signal pcm_r_s : signed(15 downto 0);
signal beep_con_s : signed(15 downto 0);
signal ear_con_s : signed(15 downto 0);
signal opll_sum_s : signed(12 downto 0);
signal beep_sig_s : signed(16 + volumes_i.beep'length downto 0);
signal ear_sig_s : signed(16 + volumes_i.ear'length downto 0);
signal psg_sig_s : signed(16 + volumes_i.psg'length downto 0);
signal scc_sig_s : signed(16 + volumes_i.scc'length downto 0);
signal opll_sig_s : signed(16 + volumes_i.opll'length downto 0);
signal jt51_l_sig_s : signed(16 + volumes_i.aux1'length downto 0);
signal jt51_r_sig_s : signed(16 + volumes_i.aux1'length downto 0);
begin
beep_con_s <= beep_con_c when beep_i = '1' else (others => '0');
ear_con_s <= ear_con_c when ear_i = '1' else (others => '0');
opll_sum_s <= opll_mo_i + opll_ro_i;
beep_sig_s <= beep_con_s * ('0' & signed(volumes_i.beep));
ear_sig_s <= ear_con_s * ('0' & signed(volumes_i.ear));
psg_sig_s <= ("00" & signed(audio_psg_i) & "000000") * ('0' & signed(volumes_i.psg));
scc_sig_s <= (audio_scc_i(14) & audio_scc_i) * ('0' & signed(volumes_i.scc));
opll_sig_s <= (opll_sum_s(12) & opll_sum_s & "00") * ('0' & signed(volumes_i.opll));
jt51_l_sig_s <= jt51_left_i * ('0' & signed(volumes_i.aux1));
jt51_r_sig_s <= jt51_right_i * ('0' & signed(volumes_i.aux1));
pcm_l_s <= beep_sig_s(beep_sig_s'high downto beep_sig_s'high-15) +
ear_sig_s(ear_sig_s'high downto ear_sig_s'high-15) +
psg_sig_s(psg_sig_s'high downto psg_sig_s'high-15) +
scc_sig_s(scc_sig_s'high downto scc_sig_s'high-15) +
opll_sig_s(opll_sig_s'high downto opll_sig_s'high-15) +
jt51_l_sig_s(jt51_l_sig_s'high downto jt51_l_sig_s'high-15);
--
pcm_r_s <= beep_sig_s(beep_sig_s'high downto beep_sig_s'high-15) +
ear_sig_s(ear_sig_s'high downto ear_sig_s'high-15) +
psg_sig_s(psg_sig_s'high downto psg_sig_s'high-15) +
scc_sig_s(scc_sig_s'high downto scc_sig_s'high-15) +
opll_sig_s(opll_sig_s'high downto opll_sig_s'high-15) +
jt51_r_sig_s(jt51_r_sig_s'high downto jt51_r_sig_s'high-15);
audio_mix_l_o <= pcm_l_s;
audio_mix_r_o <= pcm_r_s;
end Behavioral;
|
gpl-3.0
|
2c85b7818cfaf3790d56d52d5595388e
| 0.647314 | 2.927704 | false | false | false | false |
peteg944/music-fpga
|
LED_Matrix_FPGA_Nexys 3/uart_tx.vhd
| 4 | 6,796 |
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
----------------------------------------------------------------------------------
-- Entity
----------------------------------------------------------------------------------
entity uart_tx is
generic (
use_handshake : boolean := true;
log2_oversampling : integer := 4);
port (
RST : in std_logic;
WRCLK : in std_logic;
CLKOSX : in std_logic;
WREN : in std_logic;
CTS : in std_logic;
WRCOUNT : out std_logic_vector(10 downto 0);
RDCOUNT : out std_logic_vector(10 downto 0);
WRDATA : in std_logic_vector(7 downto 0);
WRRDY : out std_logic;
TXD : out std_logic);
end uart_tx;
----------------------------------------------------------------------------------
-- Architecture
----------------------------------------------------------------------------------
architecture rtl of uart_tx is
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
type STATE_TYPE is (st0_idle, st1_send_start_bit, st2_send_data_bits, st3_send_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal FIFO_FULL : std_logic;
signal FIFO_EMPTY : std_logic;
signal RDEN : std_logic;
signal RDDATA : std_logic_vector(7 downto 0);
-- signal RDCOUNT : std_logic_vector(10 downto 0);
-- signal WRCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVPULSE : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal TXDATA : std_logic;
signal NEXT_TXDATA : std_logic;
begin
----------------------------------------------------------------------------------
-- Component Instantiation
----------------------------------------------------------------------------------
-- Dual-Clock First-In, First-Out (FIFO) RAM Buffer
FIFO_inst : FIFO_DUALCLOCK_MACRO
generic map (
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6"
ALMOST_FULL_OFFSET => X"000F", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"000F", -- Sets the almost empty threshold
DATA_WIDTH => 8, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
ALMOSTEMPTY => open, -- 1-bit output almost empty
ALMOSTFULL => FIFO_FULL, -- 1-bit output almost full
DO => RDDATA, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => FIFO_EMPTY, -- 1-bit output empty
FULL => open, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
RDERR => open, -- 1-bit output read error
WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
WRERR => open, -- 1-bit output write error
DI => WRDATA, -- Input data, width defined by DATA_WIDTH parameter
RDCLK => CLKOSX, -- 1-bit input read clock
RDEN => RDEN, -- 1-bit input read enable
RST => RST, -- 1-bit input reset
WRCLK => WRCLK, -- 1-bit input write clock
WREN => WREN); -- 1-bit input write enable
----------------------------------------------------------------------------------
-- Concurrent Statements
----------------------------------------------------------------------------------
-- Write ready signal for FIFO
WRRDY <= not FIFO_FULL;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
TXDATA <= '1';
TXD <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
TXDATA <= NEXT_TXDATA;
TXD <= TXDATA;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, TXDATA, CTS, DIVPULSE, FIFO_EMPTY, RDDATA, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_TXDATA <= TXDATA;
RDEN <= '0';
BYTECTRINC <= '0';
if (DIVPULSE = '1') then
case STATE is
when st0_idle =>
if (FIFO_EMPTY = '0') and (CTS = '0' or not use_handshake) then
NEXT_STATE <= st1_send_start_bit;
NEXT_TXDATA <= '0';
RDEN <= '1';
BYTECTRINC <= '1';
end if;
when st1_send_start_bit =>
NEXT_STATE <= st2_send_data_bits;
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
BYTECTRINC <= '1';
when st2_send_data_bits =>
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
if (BYTECTR = "111") then
NEXT_STATE <= st3_send_stop_bit;
else
BYTECTRINC <= '1';
end if;
when st3_send_stop_bit =>
NEXT_STATE <= st0_idle;
NEXT_TXDATA <= '1';
when others => null;
end case;
end if;
end process fsm_proc;
-- Clock enable pulse
DIVPULSE <= '1' when (DIVCTR = 2**log2_oversampling-1) else '0';
-- Counter
ctr_proc : process (CLKOSX, RST)
begin
if RST = '1' then
DIVCTR <= (others => '0');
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
DIVCTR <= DIVCTR + 1;
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process ctr_proc;
end rtl;
|
mit
|
192ec08d5d951c57a2327967adc13123
| 0.447616 | 4.424479 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/fmc_adc_common/fmc_adc_clk.vhd
| 1 | 17,659 |
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC clock Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-29-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Clock Interface with FMC ADC boards.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-29-10 1.0 lucas.russo Created
-- 2013-19-08 1.1 lucas.russo Refactored to enable use with other FMC ADC boards
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc_adc_pkg.all;
entity fmc_adc_clk is
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_delay_type : string := "VARIABLE";
g_adc_clock_period : real;
g_default_adc_clk_delay : natural := 0;
g_with_ref_clk : boolean := false;
g_mmcm_param : t_mmcm_param := default_mmcm_param;
g_with_fn_dly_select : boolean := false;
g_with_bufio : boolean := true;
g_with_bufr : boolean := true;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
sys_rst_i : in std_logic;
-----------------------------
-- External ports
-----------------------------
-- ADC clocks. One clock per ADC channel
adc_clk_i : in std_logic;
-----------------------------
-- ADC Delay signals.
-----------------------------
-- ADC fine delay control
adc_clk_fn_dly_i : in t_adc_clk_fn_dly;
adc_clk_fn_dly_o : out t_adc_clk_fn_dly;
-----------------------------
-- ADC output signals.
-----------------------------
adc_clk_chain_priv_o : out t_adc_clk_chain_priv;
adc_clk_chain_glob_o : out t_adc_clk_chain_glob
-----------------------------
-- MMCM general signals
-----------------------------
--mmcm_adc_locked_o : out std_logic
);
end fmc_adc_clk;
architecture rtl of fmc_adc_clk is
alias c_mmcm_param is g_mmcm_param;
-- Clock and reset signals
signal adc_clk_ibufgds : std_logic;
signal adc_clk_ibufgds_dly : std_logic;
-- Clock BUFMR signals
signal adc_clk_bufmr : std_logic;
-- Clock BUFIO/BUFR input signals
signal adc_clk_bufio_in : std_logic;
signal adc_clk_bufr_in : std_logic;
signal adc_clk_mmcm_in : std_logic;
-- Clock internal signals interconnect
signal adc_clk_bufio : std_logic;
signal adc_clk_bufr : std_logic;
signal adc_clk_bufg : std_logic;
signal adc_clk2x_bufg : std_logic;
-- Clock MMCM signals
signal adc_clk_fbin : std_logic;
signal adc_clk_fbout : std_logic;
signal adc_clk_mmcm_out : std_logic;
signal adc_clk2x_mmcm_out : std_logic;
signal mmcm_adc_locked_int : std_logic;
-- Clock delay signals
signal iodelay_update : std_logic;
--signal adc_clk_dly_val_int : std_logic_vector(4 downto 0);
begin
-- Check for unsupported generic configs
-- Supported options
--BUFIO yes / BUFR no (unsupported)
--BUFIO no / BUFR yes (OK)
--BUFIO yes / BUFR yes (OK)
--BUFIO no / BUFR no (OK)
assert not (g_with_bufio and not g_with_bufr) report
"If BUFIO is used, then BUFR must also be!" severity failure;
-----------------------------
-- Clock signal datapath
-----------------------------
-- Delay for Clock Buffers
-- From Virtex-6 SelectIO Datasheet:
-- Sets the type of tap delay line. DEFAULT delay guarantees zero hold times.
-- FIXED delay sets a static delay value. VAR_LOADABLE dynamically loads tap
-- values. VARIABLE delay dynamically adjusts the delay value.
--
-- HIGH_PERFORMANCE_MODE = TRUE reduces the output
-- jitter in exchange of increase power dissipation
gen_adc_clk_var_loadable_iodelay : if (g_delay_type = "VAR_LOADABLE") generate
cmp_ibufds_clk_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_clk_delay,
SIGNAL_PATTERN => "CLOCK",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
c => sys_clk_i,
ce => '0',
--inc => adc_clk_dly_incdec_i,
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
--rst => adc_clk_dly_pulse_i,
rst => iodelay_update,
cntvaluein => adc_clk_fn_dly_i.idelay.val,
cntvalueout => adc_clk_fn_dly_o.idelay.val,
cinvctrl => '0',
t => '1'
);
end generate;
gen_adc_clk_variable_iodelay : if (g_delay_type = "VARIABLE") generate
cmp_ibufds_clk_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_clk_delay,
SIGNAL_PATTERN => "CLOCK",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
c => sys_clk_i,
--ce => adc_clk_dly_pulse_i,
ce => iodelay_update,
inc => adc_clk_fn_dly_i.idelay.incdec,
datain => '0',
odatain => '0',
clkin => '0',
rst => '0',
cntvaluein => adc_clk_fn_dly_i.idelay.val,
cntvalueout => adc_clk_fn_dly_o.idelay.val,
cinvctrl => '0',
t => '1'
);
end generate;
gen_with_fn_dly_select : if (g_with_fn_dly_select) generate
iodelay_update <= '1' when adc_clk_fn_dly_i.idelay.pulse = '1' and
adc_clk_fn_dly_i.sel.which = '1' else '0';
end generate;
gen_without_fn_dly_select : if (not g_with_fn_dly_select) generate
iodelay_update <= adc_clk_fn_dly_i.idelay.pulse;
end generate;
-- Generate BUFMR and connect directly to BUFIO/BUFR
--
-- In Xilinx 7-Series devices, BUFIO/BUFR only drives a single clock region.
-- If BUFIO/BUFR must drive multi clock-regions (up to 3: actual, above and
-- below), we must instanciate a multi-clock buffer (BUFMR) and then drive
-- the BUFIO/BUFR as needed.
gen_bufmr : if (g_fpga_device = "7SERIES") generate
-- We either have BUFIO + BUFR or just BUFR. We only
-- have to check for BUFR, then.
gen_bufmr_7_series : if (g_with_bufr) generate
-- 1-bit output: Clock output (connect to BUFIOs/BUFRs)
-- 1-bit input: Clock input (Connect to IBUFG)
cmp_bufmr : bufmr
port map (
O => adc_clk_bufmr,
I => adc_clk_ibufgds_dly
);
adc_clk_bufio_in <= adc_clk_bufmr;
adc_clk_bufr_in <= adc_clk_bufmr;
end generate;
gen_not_bufmr_7_series : if (not g_with_bufr) generate
adc_clk_bufio_in <= adc_clk_ibufgds_dly;
adc_clk_bufr_in <= adc_clk_ibufgds_dly;
end generate;
end generate;
-- Do not generate BUFMR and connect the input clock directly to BUFIO/BUFR
gen_not_bufmr : if (g_fpga_device = "VIRTEX6") generate
adc_clk_bufio_in <= adc_clk_ibufgds_dly;
adc_clk_bufr_in <= adc_clk_ibufgds_dly;
end generate;
-- BUFIO (better switching characteristics than BUFR and BUFG).
-- It can be used just inside ILOGIC blocks resources, such as
-- an IDDR block.
gen_with_bufio : if (g_with_bufio) generate
cmp_adc_clk_bufio : bufio
port map (
O => adc_clk_bufio,
I => adc_clk_bufio_in
);
end generate;
-- BUFR (better switching characteristics than BUFG).
-- It can drive logic elements (block ram, CLB, DSP tiles,
-- etc) up to 6 clock regions.
gen_with_bufr : if (g_with_bufr) generate
cmp_adc_clk_bufr : bufr
generic map(
SIM_DEVICE => g_fpga_device,
BUFR_DIVIDE => "BYPASS"
)
port map (
CLR => '0',
CE => '1',
I => adc_clk_bufr_in,
O => adc_clk_bufr
);
end generate;
-- MMCM input clock
gen_mmcm_clk_fallback_in : if (not g_with_bufr and not g_with_bufio) generate
adc_clk_mmcm_in <= adc_clk_ibufgds_dly;
end generate;
gen_mmcm_clk_in : if (g_with_bufr) generate
adc_clk_mmcm_in <= adc_clk_bufr;
end generate;
gen_with_ref_clk : if (g_with_ref_clk) generate
-- ADC Clock PLL
cmp_mmcm_adc_clk : MMCM_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
-- Let the synthesis tools select the best appropriate
-- compensation method (as dictated in Virtex-6 clocking
-- resourses guide page 53, note 2)
--COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
--DIVCLK_DIVIDE => 4,
DIVCLK_DIVIDE => c_mmcm_param.divclk,
--CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_MULT_F => c_mmcm_param.clkbout_mult_f,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
-- adc clock
--CLKOUT0_DIVIDE_F => 3.000,
CLKOUT0_DIVIDE_F => c_mmcm_param.clk0_out_div_f,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
-- 2x adc clock.
--CLKOUT1_DIVIDE => 3,
CLKOUT1_DIVIDE => c_mmcm_param.clk1_out_div,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 130 MHZ input clock
CLKIN1_PERIOD => c_mmcm_param.clk0_in_period,
REF_JITTER1 => 0.10,
-- Not used. Just to bypass Xilinx errors
-- Just input 130 MHz input clock
CLKIN2_PERIOD => c_mmcm_param.clk0_in_period,
REF_JITTER2 => 0.10
)
port map(
-- Output clocks
CLKFBOUT => adc_clk_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_clk_mmcm_out,
CLKOUT0B => open,
CLKOUT1 => adc_clk2x_mmcm_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_clk_fbin,
CLKIN1 => adc_clk_mmcm_in,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked_int,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => sys_rst_i
);
-- Global clock buffer for MMCM feedback. Deskew MMCM configuration
cmp_adc_clk_fb_bufg : BUFG
port map(
O => adc_clk_fbin,
I => adc_clk_fbout
);
-- Global clock buffer for FPGA logic
cmp_adc_out_bufg : BUFG
port map(
O => adc_clk_bufg,
I => adc_clk_mmcm_out
);
cmp_adc2x_out_bufg : BUFG
port map(
O => adc_clk2x_bufg,
I => adc_clk2x_mmcm_out
);
end generate;
-- Only instantiate BUFG if BUFIO and BUFR not selected and not a reference clock
gen_without_ref_clk : if (not g_with_ref_clk) generate
gen_without_bufio_bufr : if (not g_with_bufio and not g_with_bufr) generate
cmp_noref_clk_bufg : BUFG
port map(
O => adc_clk_bufg,
I => adc_clk_mmcm_in
);
end generate;
end generate;
-- Clock buffer supported options
--BUFIO yes / BUFR no (unsupported)
--BUFIO no / BUFR yes (OK)
--BUFIO yes / BUFR yes (OK)
--BUFIO no / BUFR no (OK)
-- Output clocks.
-- BUFIO selected
gen_with_bufio_out : if (g_with_bufio) generate
adc_clk_chain_priv_o.adc_clk_bufio <= adc_clk_bufio;
end generate;
-- BUFR selected
gen_with_bufr_out : if (g_with_bufr) generate
adc_clk_chain_priv_o.adc_clk_bufr <= adc_clk_bufr;
-- BUFR selected but BUFIO NOT selected. Output BUFIO clock as BUFR clock
gen_withou_bufio_out : if (not g_with_bufio) generate
adc_clk_chain_priv_o.adc_clk_bufio <= adc_clk_bufr;
end generate;
end generate;
-- BUFR NOT selected and BUFIO NOT selected. Output BUFIO and BUFR as BUFG clock
gen_withou_bufr_bufio_out : if (not g_with_bufio and not g_with_bufr) generate
adc_clk_chain_priv_o.adc_clk_bufr <= adc_clk_bufg;
adc_clk_chain_priv_o.adc_clk_bufio <= adc_clk_bufg;
end generate;
-- Output Reference ADC clock if selected
gen_ref_clks : if (g_with_ref_clk) generate
adc_clk_chain_glob_o.adc_clk_bufg <= adc_clk_bufg;
adc_clk_chain_glob_o.adc_clk2x_bufg <= adc_clk2x_bufg;
end generate;
gen_true_mmcm_lock_ref_clk : if (g_with_ref_clk) generate
adc_clk_chain_glob_o.mmcm_adc_locked <= mmcm_adc_locked_int;
end generate;
gen_false_mmcm_lock_ref_clk : if (not g_with_ref_clk) generate
adc_clk_chain_glob_o.mmcm_adc_locked <= '1';
end generate;
end rtl;
|
lgpl-3.0
|
0332bce9835e2f91825bd9d041fb92c3
| 0.430885 | 4.471765 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_vhdl_2008_pkg.vhd
| 1 | 6,614 |
-- Based on wb_fabric_pkg.vhd from Tomasz Wlostowski
-- Modified by Lucas Russo <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wb_stream_generic_pkg is generic (type g_wbs_address_width,
type c_wbs_data_width);
-- Must be at least 2 bits wide
--constant c_wbs_address_width : integer := 4;
-- Must be at least 16 bits wide. Not a good solution, as streaming interfaces
-- might different widths. FIX ME!
--constant c_wbs_data_width : integer := 64;
subtype t_wbs_address is
std_logic_vector(c_wbs_address_width-1 downto 0);
subtype t_wbs_data is
std_logic_vector(c_wbs_data_width-1 downto 0);
subtype t_wbs_byte_select is
std_logic_vector((c_wbs_data_width/8)-1 downto 0);
constant c_WBS_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WBS_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WBS_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WBS_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wbs_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
error : std_logic;
tag_me : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
type t_wbs_source_out is record
adr : t_wbs_address;
dat : t_wbs_data;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_byte_select;
end record;
subtype t_wbs_sink_in is t_wbs_source_out;
type t_wbs_source_in is record
ack : std_logic;
stall : std_logic;
err : std_logic;
rty : std_logic;
end record;
subtype t_wbs_sink_out is t_wbs_source_in;
--type t_wrf_oob is record
-- valid: std_logic;
-- oob_type : std_logic_vector(3 downto 0);
-- ts_r : std_logic_vector(27 downto 0);
-- ts_f : std_logic_vector(3 downto 0);
-- frame_id : std_logic_vector(15 downto 0);
-- port_id : std_logic_vector(5 downto 0);
--end record;
type t_wbs_source_in_array is array (natural range <>) of t_wbs_source_in;
type t_wbs_source_out_array is array (natural range <>) of t_wbs_source_out;
subtype t_wbs_sink_in_array is t_wbs_source_out_array;
subtype t_wbs_sink_out_array is t_wbs_source_in_array;
function f_marshall_wbs_status (stat : t_wbs_status_reg) return std_logic_vector;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg;
function f_packet_num_bits(packet_size : natural) return natural;
constant cc_dummy_wbs_addr : std_logic_vector(c_wbs_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_wbs_dat : std_logic_vector(c_wbs_data_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_wbs_sel : std_logic_vector(c_wbs_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_src_in : t_wbs_source_in :=
('0', '0', '0', '0');
constant cc_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
-- Components
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_o : out std_logic
);
end component;
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_i : in std_logic
);
end component;
end wb_stream_pkg;
package body wb_stream_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector
is
-- Wishbone bus data_width is at least 16 bits
variable tmp : std_logic_vector(c_wbs_data_width-1 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.error;
tmp(2) := stat.has_smac;
tmp(3) := stat.has_crc;
tmp(15 downto 8) := stat.match_class;
return tmp;
end;
function f_unmarshall_wbs_status(stat : std_logic_vector)
return t_wbs_status_reg
is
variable tmp : t_wbs_status_reg;
begin
tmp.is_hp := stat(0);
tmp.error := stat(1);
tmp.has_smac := stat(2);
tmp.has_crc := stat(3);
tmp.match_class := stat(15 downto 8);
return tmp;
end f_unmarshall_wbs_status;
function f_packet_num_bits(packet_size : natural)
return natural
is
-- Slightly different behaviour than the one located at wishbone_pkg.vhd
function f_ceil_log2(x : natural) return natural is
begin
if x <= 2
then return 1;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
begin
return f_ceil_log2(packet_size);
end f_packet_num_bits;
end wb_stream_pkg;
|
lgpl-3.0
|
f5966cb8457dee54c26eb9124d901e7c
| 0.555186 | 3.320281 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/hdmi2/hdmi_out_altera.vhd
| 2 | 3,303 |
--
-- Copyright (c) 2015 Davor Jadrijevic
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-- SUCH DAMAGE.
--
-- $Id$
--
-- vendor-independent module for simulating differential HDMI output
-- this module tested on scarab and it works :)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hdmi_out_altera is
port (
clock_pixel_i : in std_logic; -- x1
clock_tdms_i : in std_logic; -- x5
red_i : in std_logic_vector(9 downto 0);
green_i : in std_logic_vector(9 downto 0);
blue_i : in std_logic_vector(9 downto 0);
tmds_out_p : out std_logic_vector(3 downto 0);
tmds_out_n : out std_logic_vector(3 downto 0)
);
end entity;
architecture Behavioral of hdmi_out_altera is
signal mod5 : std_logic_vector(2 downto 0);
signal shift_r, shift_g, shift_b : std_logic_vector(9 downto 0);
signal tdms_out_s : std_logic_vector( 7 downto 0);
begin
process (clock_tdms_i)
begin
if rising_edge(clock_tdms_i) then
if mod5(2) = '1' then
mod5 <= "000";
shift_r <= red_i;
shift_g <= green_i;
shift_b <= blue_i;
else
mod5 <= mod5 + "001";
shift_r <= "00" & shift_r(9 downto 2);
shift_g <= "00" & shift_g(9 downto 2);
shift_b <= "00" & shift_b(9 downto 2);
end if;
end if;
end process;
-- HDMI data serialiser
-- Outputs the encoded video data as serial data across the HDMI bus
ddio_inst: entity work.altddio_out1
port map (
datain_h => shift_r(0) & not(shift_r(0)) & shift_g(0) & not(shift_g(0)) & shift_b(0) & not(shift_b(0)) & clock_pixel_i & not(clock_pixel_i),
datain_l => shift_r(1) & not(shift_r(1)) & shift_g(1) & not(shift_g(1)) & shift_b(1) & not(shift_b(1)) & clock_pixel_i & not(clock_pixel_i),
outclock => clock_tdms_i,
dataout => tdms_out_s
);
-- CLK CH2 CH1 CH0
tmds_out_p <= tdms_out_s(1) & tdms_out_s(7) & tdms_out_s(5) & tdms_out_s(3);
tmds_out_n <= tdms_out_s(0) & tdms_out_s(6) & tdms_out_s(4) & tdms_out_s(2);
end Behavioral;
|
gpl-3.0
|
7755ebe8d1fee0ab909b2185a9c3b0f9
| 0.673933 | 3.081157 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.vhd
| 1 | 97,824 |
--*****************************************************************************
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 1.5
-- \ \ Application : MIG
-- / / Filename : ddr_phy_top.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Jan 31 2012
-- \___\/\___\
--
--Device : 7 Series
--Design Name : DDR3 SDRAM
--Purpose : Top level memory interface block. Instantiates a clock
-- and reset generator, the memory controller, the phy and
-- the user interface blocks.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mig_7series_v1_8_ddr_phy_top is
generic (
TCQ : integer := 100; -- Register delay (simulation only)
AL : string := "0"; -- Additive Latency option
BANK_WIDTH : integer := 3; -- # of bank bits
BURST_MODE : string := "8"; -- Burst length
BURST_TYPE : string := "SEQ"; -- Burst type
CA_MIRROR : string := "OFF"; -- C/A mirror opt for DDR3 dual rank
CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory
CL : integer := 5;
COL_WIDTH : integer := 12; -- column address width
CS_WIDTH : integer := 1; -- # of unique CS outputs
CKE_WIDTH : integer := 1; -- # of cke outputs
CWL : integer := 5;
DM_WIDTH : integer := 8; -- # of DM (data mask)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_TYPE : string := "DDR3";
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
MASTER_PHY_CTL : integer := 0; -- The bank number where master PHY_CONTROL resides
LP_DDR_CK_WIDTH : integer := 2;
DATA_IO_IDLE_PWRDWN : string := "ON"; -- "ON" or "OFF"
-- Hard PHY parameters
PHYCTL_CMD_FIFO : string := "FALSE";
-- five fields, one per possible I/O bank, 4 bits in each field,
-- 1 per lane data=1/ctl=0
DATA_CTL_B0 : std_logic_vector(3 downto 0) := X"c";
DATA_CTL_B1 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B2 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B3 : std_logic_vector(3 downto 0) := X"f";
DATA_CTL_B4 : std_logic_vector(3 downto 0) := X"f";
-- defines the byte lanes in I/O banks being used in the interface
-- 1- Used, 0- Unused
BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
-- defines the bit lanes in I/O banks being used in the interface. Each
-- = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
-- control/address/data pin mapping parameters
CK_BYTE_MAP : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
ADDR_MAP : std_logic_vector(191 downto 0) := X"000000000000000000000000000000000000000000000000";
BANK_MAP : std_logic_vector(35 downto 0) := X"000000000";
CAS_MAP : std_logic_vector(11 downto 0) := X"000";
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
CKE_ODT_AUX : string := "FALSE";
CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000";
PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
RAS_MAP : std_logic_vector(11 downto 0) := X"000";
WE_MAP : std_logic_vector(11 downto 0) := X"000";
DQS_BYTE_MAP
: std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
DATA0_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA1_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
-- This parameter must be set based on memory clock frequency
-- It must be set to 4 for frequencies above 533 MHz?? (undecided)
-- and set to 2 for 533 MHz and below
PRE_REV3ES : string := "OFF"; -- Delay O/Ps using Phaser_Out fine dly
nCK_PER_CLK : integer := 2; -- # of memory CKs per fabric CLK
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
ADDR_CMD_MODE : string := "1T"; -- ADDR/CTRL timing: "2T", "1T"
IODELAY_HP_MODE : string := "ON";
BANK_TYPE : string := "HP_IO"; -- # = "HP_LP", "HR_LP", "DEFAULT"
DATA_IO_PRIM_TYPE : string := "DEFAULT"; -- # = "HP_LP", "HR_LP", "DEFAULT"
IODELAY_GRP : string := "IODELAY_MIG";
IBUF_LPWR_MODE : string := "OFF"; -- input buffer low power option
OUTPUT_DRV : string := "HIGH"; -- to calib_top
REG_CTRL : string := "OFF"; -- to calib_top
RTT_NOM : string := "60"; -- to calib_top
RTT_WR : string := "120"; -- to calib_top
tCK : integer := 2500; -- pS
tRFC : integer := 110000; -- pS
DDR2_DQSN_ENABLE : string := "YES"; -- Enable differential DQS for DDR2
WRLVL : string := "OFF"; -- to calib_top
DEBUG_PORT : string := "OFF"; -- to calib_top
RANKS : integer := 4;
ODT_WIDTH : integer := 1;
ROW_WIDTH : integer := 16; -- DRAM address bus width
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
-- calibration Address. The address given below will be used for calibration
-- read and write operations.
CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000"; -- Calibration row address
CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000"; -- Calibration column address
CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000"; -- Calibration bank address
-- Simulation /debug options
SIM_BYPASS_INIT_CAL : string := "OFF";
-- Parameter used to force skipping
-- or abbreviation of initialization
-- and calibration. Overrides
-- SIM_INIT_OPTION, SIM_CAL_OPTION,
-- and disables various other blocks
--parameter SIM_INIT_OPTION = "SKIP_PU_DLY", -- Skip various init steps
--parameter SIM_CAL_OPTION = "NONE", -- Skip various calib steps
REFCLK_FREQ : real := 200.0; -- IODELAY ref clock freq (MHz)
USE_CS_PORT : integer := 1; -- Support chip select output
USE_DM_PORT : integer := 1; -- Support data mask output
USE_ODT_PORT : integer := 1; -- Support ODT output
RD_PATH_REG : integer := 0 -- optional registers in the read path
-- to MC for timing improvement.
-- =1 enabled, = 0 disabled
);
port (
clk : in std_logic; -- Fabric logic clock
-- To MC, calib_top, hard PHY
clk_ref : in std_logic; -- Idelay_ctrl reference clock
-- To hard PHY (external source)
freq_refclk : in std_logic; -- To hard PHY for Phasers
mem_refclk : in std_logic; -- Memory clock to hard PHY
pll_lock : in std_logic; -- System PLL lock signal
sync_pulse : in std_logic; -- 1/N sync pulse used to
-- synchronize all PHASERS
error : in std_logic; -- Support for TG error detect
rst_tg_mc : out std_logic; -- Support for TG error detect
device_temp : in std_logic_vector(11 downto 0);
tempmon_sample_en : in std_logic;
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
rst : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
-- From MC
mc_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mc_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
mc_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
mc_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
mc_reset_n : in std_logic;
mc_odt : in std_logic_vector(1 downto 0);
mc_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
-- AUX - For ODT and CKE assertion during reads and writes
mc_aux_out0 : in std_logic_vector(3 downto 0);
mc_aux_out1 : in std_logic_vector(3 downto 0);
mc_cmd_wren : in std_logic;
mc_ctl_wren : in std_logic;
mc_cmd : in std_logic_vector(2 downto 0);
mc_cas_slot : in std_logic_vector(1 downto 0);
mc_data_offset : in std_logic_vector(5 downto 0);
mc_data_offset_1 : in std_logic_vector(5 downto 0);
mc_data_offset_2 : in std_logic_vector(5 downto 0);
mc_rank_cnt : in std_logic_vector(1 downto 0);
-- Write
mc_wrdata_en : in std_logic;
mc_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
mc_wrdata_mask : in std_logic_vector((2*nCK_PER_CLK*(DQ_WIDTH/8))-1 downto 0);
idle : in std_logic;
-- DDR bus signals
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
dbg_rddata_valid : out std_logic;
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_pi_phaselock_start : out std_logic;
dbg_pi_phaselocked_done : out std_logic;
dbg_pi_phaselock_err : out std_logic;
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_pi_dqsfound_err : out std_logic;
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrcal_err : out std_logic;
-- FIFO status flags
phy_mc_ctl_full : out std_logic;
phy_mc_cmd_full : out std_logic;
phy_mc_data_full : out std_logic;
-- Calibration status and resultant outputs
init_calib_complete : out std_logic;
init_wrcal_complete : out std_logic;
calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
phy_rddata_valid : out std_logic;
phy_rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
ref_dll_lock : out std_logic;
rst_phaser_ref : in std_logic;
dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic;
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0)
);
end entity;
architecture arch_ddr_phy_top of mig_7series_v1_8_ddr_phy_top is
-- function to OR the bits in a vectored signal
function OR_BR (inp_var: std_logic_vector)
return std_logic is
variable temp: std_logic := '0';
begin
for idx in inp_var'range loop
temp := temp or inp_var(idx);
end loop;
return temp;
end function;
-- Calculate number of slots in the system
function CALC_nSLOTS return integer is
begin
if (OR_BR(SLOT_1_CONFIG) = '1') then
return (2);
else
return (1);
end if;
end function;
function SIM_INIT_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("SKIP_INIT");
elsif (SIM_BYPASS_INIT_CAL = "FAST" or
SIM_BYPASS_INIT_CAL = "SIM_FULL") then
return ("SKIP_PU_DLY");
else
return ("NONE");
end if;
end function;
function SIM_CAL_OPTION_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("SKIP_CAL");
elsif (SIM_BYPASS_INIT_CAL = "FAST") then
return ("FAST_CAL");
elsif (SIM_BYPASS_INIT_CAL = "SIM_FULL" or
SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL") then
return ("FAST_WIN_DETECT");
else
return ("NONE");
end if;
end function;
function CALC_WRLVL_W return string is
begin
if (SIM_BYPASS_INIT_CAL = "SKIP") then
return ("OFF");
else
return (WRLVL);
end if;
end function;
function HIGHEST_BANK_W return integer is
begin
if (BYTE_LANES_B4 /= "0000") then
return (5);
elsif (BYTE_LANES_B3 /= "0000") then
return (4);
elsif (BYTE_LANES_B2 /= "0000") then
return (3);
elsif (BYTE_LANES_B1 /= "0000") then
return (2);
else
return (1);
end if;
end function;
function HIGHEST_LANE_B0_W return integer is
begin
if (BYTE_LANES_B0(3) = '1') then
return (4);
elsif (BYTE_LANES_B0(2) = '1') then
return (3);
elsif (BYTE_LANES_B0(1) = '1') then
return (2);
elsif (BYTE_LANES_B0(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B1_W return integer is
begin
if (BYTE_LANES_B1(3) = '1') then
return (4);
elsif (BYTE_LANES_B1(2) = '1') then
return (3);
elsif (BYTE_LANES_B1(1) = '1') then
return (2);
elsif (BYTE_LANES_B1(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B2_W return integer is
begin
if (BYTE_LANES_B2(3) = '1') then
return (4);
elsif (BYTE_LANES_B2(2) = '1') then
return (3);
elsif (BYTE_LANES_B2(1) = '1') then
return (2);
elsif (BYTE_LANES_B2(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B3_W return integer is
begin
if (BYTE_LANES_B3(3) = '1') then
return (4);
elsif (BYTE_LANES_B3(2) = '1') then
return (3);
elsif (BYTE_LANES_B3(1) = '1') then
return (2);
elsif (BYTE_LANES_B3(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_B4_W return integer is
begin
if (BYTE_LANES_B4(3) = '1') then
return (4);
elsif (BYTE_LANES_B4(2) = '1') then
return (3);
elsif (BYTE_LANES_B4(1) = '1') then
return (2);
elsif (BYTE_LANES_B4(0) = '1') then
return (1);
else
return (0);
end if;
end function;
function HIGHEST_LANE_W return integer is
begin
if (HIGHEST_LANE_B4_W /= 0) then
return (HIGHEST_LANE_B4_W+16);
elsif (HIGHEST_LANE_B3_W /= 0) then
return (HIGHEST_LANE_B3_W+12);
elsif (HIGHEST_LANE_B2_W /= 0) then
return (HIGHEST_LANE_B2_W+8);
elsif (HIGHEST_LANE_B1_W /= 0) then
return (HIGHEST_LANE_B1_W+4);
else
return (HIGHEST_LANE_B0_W);
end if;
end function;
function N_CTL_LANES_B0 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B0(idx)) = '1' and BYTE_LANES_B0(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B1 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B1(idx)) = '1' and BYTE_LANES_B1(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B2 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B2(idx)) = '1' and BYTE_LANES_B2(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B3 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B3(idx)) = '1' and BYTE_LANES_B3(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function N_CTL_LANES_B4 return integer is
variable temp: integer := 0;
begin
for idx in 0 to 3 loop
if (not(DATA_CTL_B4(idx)) = '1' and BYTE_LANES_B4(idx) = '1') then
temp := temp + 1;
else
temp := temp;
end if;
end loop;
return temp;
end function;
function CTL_BANK_B0 return std_logic is
begin
if ((not(DATA_CTL_B0(0)) = '1' and BYTE_LANES_B0(0) = '1') or
(not(DATA_CTL_B0(1)) = '1' and BYTE_LANES_B0(1) = '1') or
(not(DATA_CTL_B0(2)) = '1' and BYTE_LANES_B0(2) = '1') or
(not(DATA_CTL_B0(3)) = '1' and BYTE_LANES_B0(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B1 return std_logic is
begin
if ((not(DATA_CTL_B1(0)) = '1' and BYTE_LANES_B1(0) = '1') or
(not(DATA_CTL_B1(1)) = '1' and BYTE_LANES_B1(1) = '1') or
(not(DATA_CTL_B1(2)) = '1' and BYTE_LANES_B1(2) = '1') or
(not(DATA_CTL_B1(3)) = '1' and BYTE_LANES_B1(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B2 return std_logic is
begin
if ((not(DATA_CTL_B2(0)) = '1' and BYTE_LANES_B2(0) = '1') or
(not(DATA_CTL_B2(1)) = '1' and BYTE_LANES_B2(1) = '1') or
(not(DATA_CTL_B2(2)) = '1' and BYTE_LANES_B2(2) = '1') or
(not(DATA_CTL_B2(3)) = '1' and BYTE_LANES_B2(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B3 return std_logic is
begin
if ((not(DATA_CTL_B3(0)) = '1' and BYTE_LANES_B3(0) = '1') or
(not(DATA_CTL_B3(1)) = '1' and BYTE_LANES_B3(1) = '1') or
(not(DATA_CTL_B3(2)) = '1' and BYTE_LANES_B3(2) = '1') or
(not(DATA_CTL_B3(3)) = '1' and BYTE_LANES_B3(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_B4 return std_logic is
begin
if ((not(DATA_CTL_B4(0)) = '1' and BYTE_LANES_B4(0) = '1') or
(not(DATA_CTL_B4(1)) = '1' and BYTE_LANES_B4(1) = '1') or
(not(DATA_CTL_B4(2)) = '1' and BYTE_LANES_B4(2) = '1') or
(not(DATA_CTL_B4(3)) = '1' and BYTE_LANES_B4(3) = '1')) then
return ('1') ;
else
return ('0') ;
end if;
end function;
function CTL_BANK_W return std_logic_vector is
variable ctl_bank_var : std_logic_vector(2 downto 0);
begin
if (CTL_BANK_B0 = '1') then
ctl_bank_var := "000";
elsif (CTL_BANK_B1 = '1') then
ctl_bank_var := "001";
elsif (CTL_BANK_B2 = '1') then
ctl_bank_var := "010";
elsif (CTL_BANK_B3 = '1') then
ctl_bank_var := "011";
elsif (CTL_BANK_B4 = '1') then
ctl_bank_var := "100";
else
ctl_bank_var := "000";
end if;
return (ctl_bank_var);
end function;
function ODD_PARITY (inp_var : std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for idx in inp_var'range loop
tmp := tmp XOR inp_var(idx);
end loop;
return tmp;
end ODD_PARITY;
-- Calculate number of slots in the system
constant nSLOTS : integer := CALC_nSLOTS;
constant CLK_PERIOD : integer := tCK * nCK_PER_CLK;
-- Parameter used to force skipping or abbreviation of initialization
-- and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
-- disables various other blocks depending on the option selected
-- This option should only be used during simulation. In the case of
-- the "SKIP" option, the testbench used should also not be modeling
-- propagation delays.
-- Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
-- "NONE" = options determined by the individual parameter settings
-- "SIM_FULL" = skip power-up delay. FULL calibration performed without
-- averaging algorithm turned ON during window detection.
-- "SKIP" = skip power-up delay. Skip calibration not yet supported.
-- "FAST" = skip power-up delay, and calibrate (read leveling, write
-- leveling, and phase detector) only using one DQS group, and
-- apply the results to all other DQS groups.
constant SIM_INIT_OPTION : string := SIM_INIT_OPTION_W;
constant SIM_CAL_OPTION : string := SIM_CAL_OPTION_W;
constant WRLVL_W : string := CALC_WRLVL_W;
constant HIGHEST_BANK : integer := HIGHEST_BANK_W;
-- constant HIGHEST_LANE_B0 = HIGHEST_LANE_B0_W;
-- constant HIGHEST_LANE_B1 = HIGHEST_LANE_B1_W;
-- constant HIGHEST_LANE_B2 = HIGHEST_LANE_B2_W;
-- constant HIGHEST_LANE_B3 = HIGHEST_LANE_B3_W;
-- constant HIGHEST_LANE_B4 = HIGHEST_LANE_B4_W;
constant HIGHEST_LANE : integer := HIGHEST_LANE_W;
constant N_CTL_LANES : integer := N_CTL_LANES_B0 + N_CTL_LANES_B1 + N_CTL_LANES_B2 + N_CTL_LANES_B3 + N_CTL_LANES_B4;
-- Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
-- This should be the case since the PLL should be placed adjacent
-- to the same IO Bank as Ck/Addr/Cmd and Control
constant CTL_BANK : std_logic_vector(2 downto 0):= CTL_BANK_W;
function CTL_BYTE_LANE_W return std_logic_vector is
variable ctl_byte_lane_var: std_logic_vector(7 downto 0);
begin
if (N_CTL_LANES = 4) then
ctl_byte_lane_var := "11100100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00100100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00110100";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00111000";
elsif (N_CTL_LANES = 3 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00111001";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1'))) then
ctl_byte_lane_var := "00000100";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001100";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001110";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00001001";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
(not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
(not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
(not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
(not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
(not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
ctl_byte_lane_var := "00001101";
elsif (N_CTL_LANES = 2 and
(((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
(not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
(not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
(not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
(not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
(not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
ctl_byte_lane_var := "00001000";
else
ctl_byte_lane_var := "11100100";
end if;
return (ctl_byte_lane_var);
end function;
constant CTL_BYTE_LANE : std_logic_vector(7 downto 0):= CTL_BYTE_LANE_W;
component mig_7series_v1_8_ddr_mc_phy_wrapper is
generic (
TCQ : integer;
tCK : integer;
BANK_TYPE : string;
DATA_IO_PRIM_TYPE : string;
DATA_IO_IDLE_PWRDWN :string;
IODELAY_GRP : string;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
BANK_WIDTH : integer;
CKE_WIDTH : integer;
CS_WIDTH : integer;
CK_WIDTH : integer;
CWL : integer;
DDR2_DQSN_ENABLE : string;
DM_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
RANKS : integer;
ODT_WIDTH : integer;
REG_CTRL : string;
ROW_WIDTH : integer;
USE_CS_PORT : integer;
USE_DM_PORT : integer;
USE_ODT_PORT : integer;
IBUF_LPWR_MODE : string;
LP_DDR_CK_WIDTH : integer;
PHYCTL_CMD_FIFO : string;
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
PHY_0_BITLANES : std_logic_vector(47 downto 0);
PHY_1_BITLANES : std_logic_vector(47 downto 0);
PHY_2_BITLANES : std_logic_vector(47 downto 0);
HIGHEST_BANK : integer;
HIGHEST_LANE : integer;
CK_BYTE_MAP : std_logic_vector(143 downto 0);
ADDR_MAP : std_logic_vector(191 downto 0);
BANK_MAP : std_logic_vector(35 downto 0);
CAS_MAP : std_logic_vector(11 downto 0);
CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
CKE_MAP : std_logic_vector(95 downto 0);
ODT_MAP : std_logic_vector(95 downto 0);
CKE_ODT_AUX : string;
CS_MAP : std_logic_vector(119 downto 0);
PARITY_MAP : std_logic_vector(11 downto 0);
RAS_MAP : std_logic_vector(11 downto 0);
WE_MAP : std_logic_vector(11 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
DATA0_MAP : std_logic_vector(95 downto 0);
DATA1_MAP : std_logic_vector(95 downto 0);
DATA2_MAP : std_logic_vector(95 downto 0);
DATA3_MAP : std_logic_vector(95 downto 0);
DATA4_MAP : std_logic_vector(95 downto 0);
DATA5_MAP : std_logic_vector(95 downto 0);
DATA6_MAP : std_logic_vector(95 downto 0);
DATA7_MAP : std_logic_vector(95 downto 0);
DATA8_MAP : std_logic_vector(95 downto 0);
DATA9_MAP : std_logic_vector(95 downto 0);
DATA10_MAP : std_logic_vector(95 downto 0);
DATA11_MAP : std_logic_vector(95 downto 0);
DATA12_MAP : std_logic_vector(95 downto 0);
DATA13_MAP : std_logic_vector(95 downto 0);
DATA14_MAP : std_logic_vector(95 downto 0);
DATA15_MAP : std_logic_vector(95 downto 0);
DATA16_MAP : std_logic_vector(95 downto 0);
DATA17_MAP : std_logic_vector(95 downto 0);
MASK0_MAP : std_logic_vector(107 downto 0);
MASK1_MAP : std_logic_vector(107 downto 0);
SIM_CAL_OPTION : string;
MASTER_PHY_CTL : integer
);
port (
rst : in std_logic;
clk : in std_logic;
freq_refclk : in std_logic;
mem_refclk : in std_logic;
pll_lock : in std_logic;
sync_pulse : in std_logic;
idelayctrl_refclk : in std_logic;
phy_cmd_wr_en : in std_logic;
phy_data_wr_en : in std_logic;
phy_ctl_wd : in std_logic_vector(31 downto 0);
phy_ctl_wr : in std_logic;
phy_if_empty_def : in std_logic;
phy_if_reset : in std_logic;
data_offset_1 : in std_logic_vector(5 downto 0);
data_offset_2 : in std_logic_vector(5 downto 0);
aux_in_1 : in std_logic_vector(3 downto 0);
aux_in_2 : in std_logic_vector(3 downto 0);
idelaye2_init_val : out std_logic_vector(4 downto 0);
oclkdelay_init_val : out std_logic_vector(5 downto 0);
if_empty : out std_logic;
phy_ctl_full : out std_logic;
phy_cmd_full : out std_logic;
phy_data_full : out std_logic;
phy_pre_data_a_full : out std_logic;
ddr_clk : out std_logic_vector(CK_WIDTH*LP_DDR_CK_WIDTH-1 downto 0);
phy_mc_go : out std_logic;
phy_write_calib : in std_logic;
phy_read_calib : in std_logic;
calib_in_common : in std_logic;
calib_sel : in std_logic_vector(5 downto 0);
calib_zero_inputs : in std_logic_vector(HIGHEST_BANK-1 downto 0);
calib_zero_ctrl : in std_logic_vector(HIGHEST_BANK-1 downto 0);
po_fine_enable : in std_logic_vector(2 downto 0);
po_coarse_enable : in std_logic_vector(2 downto 0);
po_fine_inc : in std_logic_vector(2 downto 0);
po_coarse_inc : in std_logic_vector(2 downto 0);
po_counter_load_en : in std_logic;
po_counter_read_en : in std_logic;
po_sel_fine_oclk_delay : in std_logic_vector(2 downto 0);
po_counter_load_val : in std_logic_vector(8 downto 0);
po_counter_read_val : out std_logic_vector(8 downto 0);
pi_counter_read_val : out std_logic_vector(5 downto 0);
pi_rst_dqs_find : in std_logic_vector(HIGHEST_BANK-1 downto 0);
pi_fine_enable : in std_logic;
pi_fine_inc : in std_logic;
pi_counter_load_en : in std_logic;
pi_counter_load_val : in std_logic_vector(5 downto 0);
idelay_ce : in std_logic;
idelay_inc : in std_logic;
idelay_ld : in std_logic;
idle : in std_logic;
pi_phase_locked : out std_logic;
pi_phase_locked_all : out std_logic;
pi_dqs_found : out std_logic;
pi_dqs_found_all : out std_logic;
pi_dqs_out_of_range : out std_logic;
phy_init_data_sel : in std_logic;
mux_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
mux_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
mux_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
mux_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_odt : in std_logic_vector(1 downto 0);
mux_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
parity_in : in std_logic_vector(nCK_PER_CLK-1 downto 0);
mux_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
mux_wrdata_mask : in std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
mux_reset_n : in std_logic;
rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
ddr_parity : out std_logic;
ddr_ras_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_pi_counter_read_en : in std_logic;
ref_dll_lock : out std_logic;
rst_phaser_ref : in std_logic;
dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0)
);
end component mig_7series_v1_8_ddr_mc_phy_wrapper;
component mig_7series_v1_8_ddr_calib_top is
generic (
TCQ : integer;
nCK_PER_CLK : integer;
tCK : integer;
CLK_PERIOD : integer;
N_CTL_LANES : integer;
DRAM_TYPE : string;
PRBS_WIDTH : integer;
HIGHEST_LANE : integer;
HIGHEST_BANK : integer;
BANK_TYPE : string;
BYTE_LANES_B0 : std_logic_vector(3 downto 0);
BYTE_LANES_B1 : std_logic_vector(3 downto 0);
BYTE_LANES_B2 : std_logic_vector(3 downto 0);
BYTE_LANES_B3 : std_logic_vector(3 downto 0);
BYTE_LANES_B4 : std_logic_vector(3 downto 0);
DATA_CTL_B0 : std_logic_vector(3 downto 0);
DATA_CTL_B1 : std_logic_vector(3 downto 0);
DATA_CTL_B2 : std_logic_vector(3 downto 0);
DATA_CTL_B3 : std_logic_vector(3 downto 0);
DATA_CTL_B4 : std_logic_vector(3 downto 0);
DQS_BYTE_MAP : std_logic_vector(143 downto 0);
CTL_BYTE_LANE : std_logic_vector(7 downto 0);
CTL_BANK : std_logic_vector(2 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
BANK_WIDTH : integer;
CA_MIRROR : string;
COL_WIDTH : integer;
nCS_PER_RANK : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_WIDTH : integer;
ROW_WIDTH : integer;
RANKS : integer;
CS_WIDTH : integer;
CKE_WIDTH : integer;
DDR2_DQSN_ENABLE : string;
PER_BIT_DESKEW : string;
CALIB_ROW_ADD : std_logic_vector(15 downto 0);
CALIB_COL_ADD : std_logic_vector(11 downto 0);
CALIB_BA_ADD : std_logic_vector(2 downto 0);
AL : string;
ADDR_CMD_MODE : string;
BURST_MODE : string;
BURST_TYPE : string;
nCL : integer;
nCWL : integer;
tRFC : integer;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string;
USE_ODT_PORT : integer;
WRLVL : string;
PRE_REV3ES : string;
SIM_INIT_OPTION : string;
SIM_CAL_OPTION : string;
CKE_ODT_AUX : string;
DEBUG_PORT : string
);
port (
clk : in std_logic;
rst : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
phy_ctl_ready : in std_logic;
phy_ctl_full : in std_logic;
phy_cmd_full : in std_logic;
phy_data_full : in std_logic;
write_calib : out std_logic;
read_calib : out std_logic;
calib_ctl_wren : out std_logic;
calib_cmd_wren : out std_logic;
calib_seq : out std_logic_vector(1 downto 0);
calib_aux_out : out std_logic_vector(3 downto 0);
calib_cke : out std_logic_vector(nCK_PER_CLK-1 downto 0);
calib_odt : out std_logic_vector(1 downto 0);
calib_cmd : out std_logic_vector(2 downto 0);
calib_wrdata_en : out std_logic;
calib_rank_cnt : out std_logic_vector(1 downto 0);
calib_cas_slot : out std_logic_vector(1 downto 0);
calib_data_offset_0 : out std_logic_vector(5 downto 0);
calib_data_offset_1 : out std_logic_vector(5 downto 0);
calib_data_offset_2 : out std_logic_vector(5 downto 0);
phy_address : out std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
phy_bank : out std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
phy_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
phy_ras_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_cas_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_we_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
phy_reset_n : out std_logic;
calib_sel : out std_logic_vector(5 downto 0);
calib_in_common : out std_logic;
calib_zero_inputs : out std_logic_vector(HIGHEST_BANK-1 downto 0);
calib_zero_ctrl : out std_logic_vector(HIGHEST_BANK-1 downto 0);
phy_if_empty_def : out std_logic;
phy_if_reset : out std_logic;
pi_phaselocked : in std_logic;
pi_phase_locked_all : in std_logic;
pi_found_dqs : in std_logic;
pi_dqs_found_all : in std_logic;
pi_dqs_found_lanes : in std_logic_vector(HIGHEST_LANE-1 downto 0);
pi_counter_read_val : in std_logic_vector(5 downto 0);
pi_rst_stg1_cal : out std_logic_vector(HIGHEST_BANK-1 downto 0);
pi_en_stg2_f : out std_logic;
pi_stg2_f_incdec : out std_logic;
pi_stg2_load : out std_logic;
pi_stg2_reg_l : out std_logic_vector(5 downto 0);
idelay_ce : out std_logic;
idelay_inc : out std_logic;
idelay_ld : out std_logic;
po_sel_stg2stg3 : out std_logic_vector(2 downto 0);
po_stg2_c_incdec : out std_logic_vector(2 downto 0);
po_en_stg2_c : out std_logic_vector(2 downto 0);
po_stg2_f_incdec : out std_logic_vector(2 downto 0);
po_en_stg2_f : out std_logic_vector(2 downto 0);
po_counter_load_en : out std_logic;
po_counter_read_val : in std_logic_vector(8 downto 0);
device_temp : in std_logic_vector(11 downto 0);
tempmon_sample_en : in std_logic;
phy_if_empty : in std_logic;
idelaye2_init_val : in std_logic_vector(4 downto 0);
oclkdelay_init_val : in std_logic_vector(5 downto 0);
tg_err : in std_logic;
rst_tg_mc : out std_logic;
phy_wrdata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
dlyval_dq : out std_logic_vector(5*RANKS*DQ_WIDTH-1 downto 0);
phy_rddata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
phy_rddata_valid : out std_logic;
calib_writes : out std_logic;
init_calib_complete : out std_logic;
init_wrcal_complete : out std_logic;
pi_phase_locked_err : out std_logic;
pi_dqsfound_err : out std_logic;
wrcal_err : out std_logic;
dbg_pi_phaselock_start : out std_logic;
dbg_pi_dqsfound_start : out std_logic;
dbg_pi_dqsfound_done : out std_logic;
dbg_wrcal_start : out std_logic;
dbg_wrcal_done : out std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_phy_wrcal : out std_logic_vector(99 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
dbg_sel_pi_incdec : in std_logic;
dbg_sel_po_incdec : in std_logic;
dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
dbg_pi_f_inc : in std_logic;
dbg_pi_f_dec : in std_logic;
dbg_po_f_inc : in std_logic;
dbg_po_f_stg23_sel : in std_logic;
dbg_po_f_dec : in std_logic;
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_sel_all_idel_cpt : in std_logic;
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_calib_top : out std_logic_vector(255 downto 0);
dbg_phy_init : out std_logic_vector(255 downto 0);
dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
dbg_oclkdelay_calib_start : out std_logic;
dbg_oclkdelay_calib_done : out std_logic
);
end component mig_7series_v1_8_ddr_calib_top;
signal phy_din : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
signal phy_dout : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
signal ddr_cmd_ctl_data : std_logic_vector(HIGHEST_LANE*12-1 downto 0);
signal aux_out : std_logic_vector((((HIGHEST_LANE+3)/4)*4)-1 downto 0);
signal ddr_clk : std_logic_vector(CK_WIDTH * LP_DDR_CK_WIDTH-1 downto 0);
signal phy_mc_go : std_logic;
signal phy_ctl_full : std_logic;
signal phy_cmd_full : std_logic;
signal phy_data_full : std_logic;
signal phy_pre_data_a_full : std_logic;
signal if_empty : std_logic;
signal phy_write_calib : std_logic;
signal phy_read_calib : std_logic;
signal rst_stg1_cal : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal calib_sel : std_logic_vector(5 downto 0);
signal calib_in_common : std_logic;
signal calib_zero_inputs : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal calib_zero_ctrl : std_logic_vector(HIGHEST_BANK-1 downto 0);
signal pi_phase_locked : std_logic;
signal pi_phase_locked_all : std_logic;
signal pi_found_dqs : std_logic;
signal pi_dqs_found_all : std_logic;
signal pi_dqs_out_of_range : std_logic;
signal pi_enstg2_f : std_logic;
signal pi_stg2_fincdec : std_logic;
signal pi_stg2_load : std_logic;
signal pi_stg2_reg_l : std_logic_vector(5 downto 0);
signal idelay_ce : std_logic;
signal idelay_inc : std_logic;
signal idelay_ld : std_logic;
signal po_sel_stg2stg3 : std_logic_vector(2 downto 0);
signal po_stg2_cincdec : std_logic_vector(2 downto 0);
signal po_enstg2_c : std_logic_vector(2 downto 0);
signal po_stg2_fincdec : std_logic_vector(2 downto 0);
signal po_enstg2_f : std_logic_vector(2 downto 0);
signal po_counter_read_val : std_logic_vector(8 downto 0);
signal pi_counter_read_val : std_logic_vector(5 downto 0);
signal phy_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal parity : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
signal phy_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
signal phy_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal phy_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal phy_reset_n : std_logic;
signal calib_aux_out : std_logic_vector(3 downto 0);
signal calib_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal calib_odt : std_logic_vector(1 downto 0);
signal calib_ctl_wren : std_logic;
signal calib_cmd_wren : std_logic;
signal calib_wrdata_en : std_logic;
signal calib_cmd : std_logic_vector(2 downto 0);
signal calib_seq : std_logic_vector(1 downto 0);
signal calib_data_offset_0 : std_logic_vector(5 downto 0);
signal calib_data_offset_1 : std_logic_vector(5 downto 0);
signal calib_data_offset_2 : std_logic_vector(5 downto 0);
signal calib_rank_cnt : std_logic_vector(1 downto 0);
signal calib_cas_slot : std_logic_vector(1 downto 0);
signal mux_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
signal mux_aux_out : std_logic_vector(3 downto 0);
signal aux_out_map : std_logic_vector(3 downto 0);
signal mux_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
signal mux_cmd : std_logic_vector(2 downto 0);
signal mux_cmd_wren : std_logic;
signal mux_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal mux_ctl_wren : std_logic;
signal mux_cas_slot : std_logic_vector(1 downto 0);
signal mux_data_offset : std_logic_vector(5 downto 0);
signal mux_data_offset_1 : std_logic_vector(5 downto 0);
signal mux_data_offset_2 : std_logic_vector(5 downto 0);
signal mux_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_rank_cnt : std_logic_vector(1 downto 0);
signal mux_reset_n : std_logic;
signal mux_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal mux_wrdata_mask : std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
signal mux_wrdata_en : std_logic;
signal mux_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
signal mux_odt : std_logic_vector(1 downto 0);
signal phy_if_empty_def : std_logic;
signal phy_if_reset : std_logic;
signal phy_init_data_sel : std_logic;
signal rd_data_map : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal phy_rddata_valid_w : std_logic;
signal rddata_valid_reg : std_logic;
signal rd_data_reg : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
signal idelaye2_init_val : std_logic_vector(4 downto 0);
signal oclkdelay_init_val : std_logic_vector(5 downto 0);
signal mc_cs_n_temp : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
signal calib_rd_data_offset_i0 : std_logic_vector(6*RANKS-1 downto 0);
signal init_wrcal_complete_i : std_logic;
signal phy_ctl_wd_i : std_logic_vector(31 downto 0);
signal po_counter_load_en : std_logic;
signal parity_0_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_1_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_2_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal parity_3_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
signal dbg_pi_dqs_found_lanes_phy4lanes_i : std_logic_vector(11 downto 0);
signal all_zeros : std_logic_vector(8 downto 0):= (others => '0');
attribute keep : string;
attribute max_fanout : integer;
attribute keep of phy_rddata_valid_w : signal is "true";
attribute max_fanout of phy_rddata_valid_w : signal is 3;
begin
--***************************************************************************
dbg_rddata_valid <= rddata_valid_reg;
dbg_rddata <= rd_data_reg;
dbg_rd_data_offset <= calib_rd_data_offset_i0;
calib_rd_data_offset_0 <= calib_rd_data_offset_i0;
dbg_pi_phaselocked_done <= pi_phase_locked_all;
dbg_po_counter_read_val <= po_counter_read_val;
dbg_pi_counter_read_val <= pi_counter_read_val;
dbg_pi_dqs_found_lanes_phy4lanes <= dbg_pi_dqs_found_lanes_phy4lanes_i;
init_wrcal_complete <= init_wrcal_complete_i;
--***************************************************************************
clock_gen : for i in 0 to (CK_WIDTH-1) generate
ddr_ck(i) <= ddr_clk(LP_DDR_CK_WIDTH * i);
ddr_ck_n(i) <= ddr_clk((LP_DDR_CK_WIDTH * i) + 1);
end generate;
--***************************************************************************
-- During memory initialization and calibration the calibration logic drives
-- the memory signals. After calibration is complete the memory controller
-- drives the memory signals.
-- Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
--***************************************************************************
cs_rdimm : if((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (RANKS = 1) and (nCS_PER_RANK = 2)) generate
cs_rdimm_gen: for v in 0 to (CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK)-1 generate
cs_rdimm_gen_i : if((v mod (CS_WIDTH*nCS_PER_RANK)) = 0) generate
mc_cs_n_temp(v) <= mc_cs_n(v) ;
end generate;
cs_rdimm_gen_j : if(not((v mod (CS_WIDTH*nCS_PER_RANK)) = 0)) generate
mc_cs_n_temp(v) <= '1' ;
end generate;
end generate;
end generate;
cs_others : if(not(REG_CTRL = "ON") or not(DRAM_TYPE = "DDR3") or not(RANKS = 1) or not(nCS_PER_RANK = 2)) generate
mc_cs_n_temp <= mc_cs_n ;
end generate;
mux_wrdata <= mc_wrdata when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_wrdata;
mux_wrdata_mask <= mc_wrdata_mask when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else (others => '0');
mux_address <= mc_address when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_address;
mux_bank <= mc_bank when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_bank;
mux_cs_n <= mc_cs_n_temp when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cs_n;
mux_ras_n <= mc_ras_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_ras_n;
mux_cas_n <= mc_cas_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cas_n;
mux_we_n <= mc_we_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_we_n;
mux_reset_n <= mc_reset_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_reset_n;
mux_aux_out <= mc_aux_out0 when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_aux_out;
mux_odt <= mc_odt when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_odt;
mux_cke <= mc_cke when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_cke;
mux_cmd_wren <= mc_cmd_wren when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cmd_wren;
mux_ctl_wren <= mc_ctl_wren when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_ctl_wren;
mux_wrdata_en <= mc_wrdata_en when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_wrdata_en;
mux_cmd <= mc_cmd when (phy_init_data_sel ='1' or init_wrcal_complete_i ='1') else calib_cmd;
mux_cas_slot <= mc_cas_slot when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cas_slot;
mux_data_offset <= mc_data_offset when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_0;
mux_data_offset_1 <= mc_data_offset_1 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_1;
mux_data_offset_2 <= mc_data_offset_2 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_2;
-- Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
mux_rank_cnt <= "00";
-- Assigning cke & odt for DDR2 & DDR3
-- No changes for DDR3 & DDR2 dual rank
-- DDR2 single rank systems might potentially need 3 odt signals.
-- Aux_out[2] will have the odt toggled by phy and controller
-- wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
-- all of the three odt bits or some of them might be used.
-- mapping done in mc_phy_wrapper module
aux_out_gen : if(CKE_ODT_AUX = "TRUE") generate
aux_out_map <= (mux_aux_out(1) & mux_aux_out(1) & mux_aux_out(1) &
mux_aux_out(0)) when ((DRAM_TYPE = "DDR2") and
(RANKS = 1)) else
mux_aux_out;
end generate;
wo_aux_out_gen : if(not(CKE_ODT_AUX = "TRUE")) generate
aux_out_map <= "0000";
end generate;
init_calib_complete <= phy_init_data_sel;
phy_mc_ctl_full <= phy_ctl_full;
phy_mc_cmd_full <= phy_cmd_full;
phy_mc_data_full <= phy_pre_data_a_full;
--***************************************************************************
-- Generate parity for DDR3 RDIMM.
--***************************************************************************
gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
gen_ddr3_parity_4by1: if (nCK_PER_CLK = 4) generate
parity_0_wire <= (mux_address((ROW_WIDTH*4)-1 downto ROW_WIDTH*3) &
mux_bank((BANK_WIDTH*4)-1 downto BANK_WIDTH*3) &
mux_cas_n(3) & mux_ras_n(3) & mux_we_n(3));
parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
mux_ras_n(0) & mux_we_n(0));
parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
parity_3_wire <= (mux_address((ROW_WIDTH*3)-1 downto ROW_WIDTH*2) &
mux_bank((BANK_WIDTH*3)-1 downto BANK_WIDTH*2) &
mux_cas_n(2) & mux_ras_n(2) & mux_we_n(2));
process (clk)
begin
if (clk'event and clk = '1') then
parity(0) <= ODD_PARITY(parity_0_wire) after (TCQ) * 1 ps;
end if;
end process;
process (mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
begin
parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
parity(2) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
parity(3) <= ODD_PARITY(parity_3_wire) after (TCQ) * 1 ps;
end process;
end generate;
gen_ddr3_parity_2by1: if ( not(nCK_PER_CLK = 4)) generate
parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
mux_ras_n(0) & mux_we_n(0));
parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
end if;
end process;
process(mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
begin
parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
end process;
end generate;
end generate;
gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
gen_ddr3_noparity_4by1 : if (nCK_PER_CLK = 4) generate
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= '0' after (TCQ)*1 ps;
parity(1) <= '0' after (TCQ)*1 ps;
parity(2) <= '0' after (TCQ)*1 ps;
parity(3) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr3_noparity_2by1 : if (not(nCK_PER_CLK = 4)) generate
process (clk)
begin
if (clk'event and clk='1') then
parity(0) <= '0' after (TCQ)*1 ps;
parity(1) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
end generate;
--***************************************************************************
-- Code for optional register stage in read path to MC for timing
--***************************************************************************
RD_REG_TIMING : if(RD_PATH_REG = 1) generate
process (clk)
begin
if (clk'event and clk='1') then
rddata_valid_reg <= phy_rddata_valid_w after (TCQ)*1 ps;
rd_data_reg <= rd_data_map after (TCQ)*1 ps;
end if;
end process;
end generate;
RD_REG_NO_TIMING : if( not(RD_PATH_REG = 1)) generate
process (phy_rddata_valid_w, rd_data_map)
begin
rddata_valid_reg <= phy_rddata_valid_w;
rd_data_reg <= rd_data_map;
end process;
end generate;
phy_rddata_valid <= rddata_valid_reg;
phy_rd_data <= rd_data_reg;
--***************************************************************************
-- Hard PHY and accompanying bit mapping logic
--***************************************************************************
phy_ctl_wd_i <= ("00000" & mux_cas_slot & calib_seq & mux_data_offset &
mux_rank_cnt & "000" & aux_out_map & "00000" & mux_cmd);
u_ddr_mc_phy_wrapper : mig_7series_v1_8_ddr_mc_phy_wrapper
generic map (
TCQ => TCQ,
tCK => tCK,
BANK_TYPE => BANK_TYPE,
DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
IODELAY_GRP => IODELAY_GRP,
DATA_IO_IDLE_PWRDWN=> DATA_IO_IDLE_PWRDWN,
nCK_PER_CLK => nCK_PER_CLK,
nCS_PER_RANK => nCS_PER_RANK,
BANK_WIDTH => BANK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
CS_WIDTH => CS_WIDTH,
CK_WIDTH => CK_WIDTH,
CWL => CWL,
DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
DM_WIDTH => DM_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
RANKS => RANKS,
ODT_WIDTH => ODT_WIDTH,
REG_CTRL => REG_CTRL,
ROW_WIDTH => ROW_WIDTH,
USE_CS_PORT => USE_CS_PORT,
USE_DM_PORT => USE_DM_PORT,
USE_ODT_PORT => USE_ODT_PORT,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
LP_DDR_CK_WIDTH => LP_DDR_CK_WIDTH,
PHYCTL_CMD_FIFO => PHYCTL_CMD_FIFO,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
PHY_0_BITLANES => PHY_0_BITLANES,
PHY_1_BITLANES => PHY_1_BITLANES,
PHY_2_BITLANES => PHY_2_BITLANES,
HIGHEST_BANK => HIGHEST_BANK,
HIGHEST_LANE => HIGHEST_LANE,
CK_BYTE_MAP => CK_BYTE_MAP,
ADDR_MAP => ADDR_MAP,
BANK_MAP => BANK_MAP,
CAS_MAP => CAS_MAP,
CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
CKE_MAP => CKE_MAP,
ODT_MAP => ODT_MAP,
CKE_ODT_AUX => CKE_ODT_AUX,
CS_MAP => CS_MAP,
PARITY_MAP => PARITY_MAP,
RAS_MAP => RAS_MAP,
WE_MAP => WE_MAP,
DQS_BYTE_MAP => DQS_BYTE_MAP,
DATA0_MAP => DATA0_MAP,
DATA1_MAP => DATA1_MAP,
DATA2_MAP => DATA2_MAP,
DATA3_MAP => DATA3_MAP,
DATA4_MAP => DATA4_MAP,
DATA5_MAP => DATA5_MAP,
DATA6_MAP => DATA6_MAP,
DATA7_MAP => DATA7_MAP,
DATA8_MAP => DATA8_MAP,
DATA9_MAP => DATA9_MAP,
DATA10_MAP => DATA10_MAP,
DATA11_MAP => DATA11_MAP,
DATA12_MAP => DATA12_MAP,
DATA13_MAP => DATA13_MAP,
DATA14_MAP => DATA14_MAP,
DATA15_MAP => DATA15_MAP,
DATA16_MAP => DATA16_MAP,
DATA17_MAP => DATA17_MAP,
MASK0_MAP => MASK0_MAP,
MASK1_MAP => MASK1_MAP,
SIM_CAL_OPTION => SIM_CAL_OPTION,
MASTER_PHY_CTL => MASTER_PHY_CTL
)
port map (
rst => rst,
clk => clk,
-- For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
-- For memory frequencies below 400 MHz mem_refclk = mem_refclk and
-- freq_refclk = 2x or 4x mem_refclk such that it remains in the
-- 400~1066 MHz range
freq_refclk => freq_refclk,
mem_refclk => mem_refclk,
pll_lock => pll_lock,
sync_pulse => sync_pulse,
idelayctrl_refclk => clk_ref,
phy_cmd_wr_en => mux_cmd_wren,
phy_data_wr_en => mux_wrdata_en,
-- phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
-- DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
-- AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
-- The fields ACTPRE, and BankCount are only used
-- when the hard PHY counters are used by the MC.
phy_ctl_wd => phy_ctl_wd_i,
phy_ctl_wr => mux_ctl_wren,
phy_if_empty_def => phy_if_empty_def,
phy_if_reset => phy_if_reset,
data_offset_1 => mux_data_offset_1,
data_offset_2 => mux_data_offset_2,
aux_in_1 => aux_out_map,
aux_in_2 => aux_out_map,
idelaye2_init_val => idelaye2_init_val,
oclkdelay_init_val => oclkdelay_init_val,
if_empty => if_empty,
phy_ctl_full => phy_ctl_full,
phy_cmd_full => phy_cmd_full,
phy_data_full => phy_data_full,
phy_pre_data_a_full => phy_pre_data_a_full,
ddr_clk => ddr_clk,
phy_mc_go => phy_mc_go,
phy_write_calib => phy_write_calib,
phy_read_calib => phy_read_calib,
calib_in_common => calib_in_common,
calib_sel => calib_sel,
calib_zero_inputs => calib_zero_inputs,
calib_zero_ctrl => calib_zero_ctrl,
po_fine_enable => po_enstg2_f,
po_coarse_enable => po_enstg2_c,
po_fine_inc => po_stg2_fincdec,
po_coarse_inc => po_stg2_cincdec,
po_counter_load_en => po_counter_load_en,
po_counter_read_en => '1',
po_sel_fine_oclk_delay => po_sel_stg2stg3,
po_counter_load_val => all_zeros,
po_counter_read_val => po_counter_read_val,
pi_counter_read_val => pi_counter_read_val,
pi_rst_dqs_find => rst_stg1_cal,
pi_fine_enable => pi_enstg2_f,
pi_fine_inc => pi_stg2_fincdec,
pi_counter_load_en => pi_stg2_load,
pi_counter_load_val => pi_stg2_reg_l,
idelay_ce => idelay_ce,
idelay_inc => idelay_inc,
idelay_ld => idelay_ld,
idle => idle,
pi_phase_locked => pi_phase_locked,
pi_phase_locked_all => pi_phase_locked_all,
pi_dqs_found => pi_found_dqs,
pi_dqs_found_all => pi_dqs_found_all,
-- Currently not being used. May be used in future if periodic reads
-- become a requirement. This output could also be used to signal a
-- catastrophic failure in read capture and the need for re-cal
pi_dqs_out_of_range => pi_dqs_out_of_range,
phy_init_data_sel => phy_init_data_sel,
mux_address => mux_address,
mux_bank => mux_bank,
mux_cas_n => mux_cas_n,
mux_cs_n => mux_cs_n,
mux_ras_n => mux_ras_n,
mux_odt => mux_odt,
mux_cke => mux_cke,
mux_we_n => mux_we_n,
parity_in => parity,
mux_wrdata => mux_wrdata,
mux_wrdata_mask => mux_wrdata_mask,
mux_reset_n => mux_reset_n,
rd_data => rd_data_map,
ddr_addr => ddr_addr,
ddr_ba => ddr_ba,
ddr_cas_n => ddr_cas_n,
ddr_cke => ddr_cke,
ddr_cs_n => ddr_cs_n,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
ddr_parity => ddr_parity,
ddr_ras_n => ddr_ras_n,
ddr_we_n => ddr_we_n,
ddr_reset_n => ddr_reset_n,
ddr_dq => ddr_dq,
ddr_dqs => ddr_dqs,
ddr_dqs_n => ddr_dqs_n,
dbg_pi_counter_read_en => '1',
ref_dll_lock => ref_dll_lock,
rst_phaser_ref => rst_phaser_ref,
dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes_i
);
--***************************************************************************
-- Soft memory initialization and calibration logic
--***************************************************************************
u_ddr_calib_top : mig_7series_v1_8_ddr_calib_top
generic map (
TCQ => TCQ,
nCK_PER_CLK => nCK_PER_CLK,
tCK => tCK,
CLK_PERIOD => CLK_PERIOD,
N_CTL_LANES => N_CTL_LANES,
DRAM_TYPE => DRAM_TYPE,
PRBS_WIDTH => 8,
HIGHEST_LANE => HIGHEST_LANE,
HIGHEST_BANK => HIGHEST_BANK,
BANK_TYPE => BANK_TYPE,
BYTE_LANES_B0 => BYTE_LANES_B0,
BYTE_LANES_B1 => BYTE_LANES_B1,
BYTE_LANES_B2 => BYTE_LANES_B2,
BYTE_LANES_B3 => BYTE_LANES_B3,
BYTE_LANES_B4 => BYTE_LANES_B4,
DATA_CTL_B0 => DATA_CTL_B0,
DATA_CTL_B1 => DATA_CTL_B1,
DATA_CTL_B2 => DATA_CTL_B2,
DATA_CTL_B3 => DATA_CTL_B3,
DATA_CTL_B4 => DATA_CTL_B4,
DQS_BYTE_MAP => DQS_BYTE_MAP,
CTL_BYTE_LANE => CTL_BYTE_LANE,
CTL_BANK => CTL_BANK,
SLOT_1_CONFIG => SLOT_1_CONFIG,
BANK_WIDTH => BANK_WIDTH,
CA_MIRROR => CA_MIRROR,
COL_WIDTH => COL_WIDTH,
nCS_PER_RANK => nCS_PER_RANK,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_WIDTH => DRAM_WIDTH,
ROW_WIDTH => ROW_WIDTH,
RANKS => RANKS,
CS_WIDTH => CS_WIDTH,
CKE_WIDTH => CKE_WIDTH,
DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
PER_BIT_DESKEW => "OFF",
CALIB_ROW_ADD => CALIB_ROW_ADD,
CALIB_COL_ADD => CALIB_COL_ADD,
CALIB_BA_ADD => CALIB_BA_ADD,
AL => AL,
ADDR_CMD_MODE => ADDR_CMD_MODE,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
nCL => CL,
nCWL => CWL,
tRFC => tRFC,
OUTPUT_DRV => OUTPUT_DRV,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
RTT_WR => RTT_WR,
USE_ODT_PORT => USE_ODT_PORT,
WRLVL => WRLVL_W,
PRE_REV3ES => PRE_REV3ES,
SIM_INIT_OPTION => SIM_INIT_OPTION,
SIM_CAL_OPTION => SIM_CAL_OPTION,
CKE_ODT_AUX => CKE_ODT_AUX,
DEBUG_PORT => DEBUG_PORT
)
port map (
clk => clk,
rst => rst,
slot_0_present => slot_0_present,
slot_1_present => slot_1_present,
-- PHY Control Block and IN_FIFO status
phy_ctl_ready => phy_mc_go,
phy_ctl_full => '0',
phy_cmd_full => '0',
phy_data_full => '0',
-- hard PHY calibration modes
write_calib => phy_write_calib,
read_calib => phy_read_calib,
-- Signals from calib logic to be MUXED with MC
-- signals before sending to hard PHY
calib_ctl_wren => calib_ctl_wren,
calib_cmd_wren => calib_cmd_wren,
calib_seq => calib_seq,
calib_aux_out => calib_aux_out,
calib_odt => calib_odt,
calib_cke => calib_cke,
calib_cmd => calib_cmd,
calib_wrdata_en => calib_wrdata_en,
calib_rank_cnt => calib_rank_cnt,
calib_cas_slot => calib_cas_slot,
calib_data_offset_0 => calib_data_offset_0,
calib_data_offset_1 => calib_data_offset_1,
calib_data_offset_2 => calib_data_offset_2,
phy_address => phy_address,
phy_bank => phy_bank,
phy_cs_n => phy_cs_n,
phy_ras_n => phy_ras_n,
phy_cas_n => phy_cas_n,
phy_we_n => phy_we_n,
phy_reset_n => phy_reset_n,
-- DQS count and ck/addr/cmd to be mapped to calib_sel
-- based on parameter that defines placement of ctl lanes
-- and DQS byte groups in each bank. When phy_write_calib
-- is de-asserted calib_sel should select CK/addr/cmd/ctl.
calib_sel => calib_sel,
calib_in_common => calib_in_common,
calib_zero_inputs => calib_zero_inputs,
calib_zero_ctrl => calib_zero_ctrl,
phy_if_empty_def => phy_if_empty_def,
phy_if_reset => phy_if_reset,
-- DQS Phaser_IN calibration/status signals
pi_phaselocked => pi_phase_locked,
pi_phase_locked_all => pi_phase_locked_all,
pi_found_dqs => pi_found_dqs,
pi_dqs_found_all => pi_dqs_found_all,
pi_dqs_found_lanes => dbg_pi_dqs_found_lanes_phy4lanes_i(HIGHEST_LANE-1 downto 0),
pi_rst_stg1_cal => rst_stg1_cal,
pi_en_stg2_f => pi_enstg2_f,
pi_stg2_f_incdec => pi_stg2_fincdec,
pi_stg2_load => pi_stg2_load,
pi_stg2_reg_l => pi_stg2_reg_l,
pi_counter_read_val => pi_counter_read_val,
device_temp => device_temp,
tempmon_sample_en => tempmon_sample_en,
-- IDELAY tap enable and inc signals
idelay_ce => idelay_ce,
idelay_inc => idelay_inc,
idelay_ld => idelay_ld,
-- DQS Phaser_OUT calibration/status signals
po_sel_stg2stg3 => po_sel_stg2stg3,
po_stg2_c_incdec => po_stg2_cincdec,
po_en_stg2_c => po_enstg2_c,
po_stg2_f_incdec => po_stg2_fincdec,
po_en_stg2_f => po_enstg2_f,
po_counter_load_en => po_counter_load_en,
po_counter_read_val => po_counter_read_val,
phy_if_empty => if_empty,
idelaye2_init_val => idelaye2_init_val,
oclkdelay_init_val => oclkdelay_init_val,
tg_err => error,
rst_tg_mc => rst_tg_mc,
phy_wrdata => phy_wrdata,
-- From calib logic To data IN_FIFO
-- DQ IDELAY tap value from Calib logic
-- port to be added to mc_phy by Gary
dlyval_dq => open,
-- From data IN_FIFO To Calib logic and MC/UI
phy_rddata => rd_data_map,
-- From calib logic To MC
phy_rddata_valid => phy_rddata_valid_w,
calib_rd_data_offset_0 => calib_rd_data_offset_i0,
calib_rd_data_offset_1 => calib_rd_data_offset_1,
calib_rd_data_offset_2 => calib_rd_data_offset_2,
calib_writes => open,
-- Mem Init and Calibration status To MC
init_calib_complete => phy_init_data_sel,
init_wrcal_complete => init_wrcal_complete_i,
-- Debug Error signals
pi_phase_locked_err => dbg_pi_phaselock_err,
pi_dqsfound_err => dbg_pi_dqsfound_err,
wrcal_err => dbg_wrcal_err,
-- Debug Signals
dbg_pi_phaselock_start => dbg_pi_phaselock_start,
dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
dbg_wrcal_start => dbg_wrcal_start,
dbg_wrcal_done => dbg_wrcal_done,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
dbg_phy_wrlvl => dbg_phy_wrlvl,
dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
dbg_phy_wrcal => dbg_phy_wrcal,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
dbg_sel_pi_incdec => dbg_sel_pi_incdec,
dbg_sel_po_incdec => dbg_sel_po_incdec,
dbg_byte_sel => dbg_byte_sel,
dbg_pi_f_inc => dbg_pi_f_inc,
dbg_pi_f_dec => dbg_pi_f_dec,
dbg_po_f_inc => dbg_po_f_inc,
dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
dbg_po_f_dec => dbg_po_f_dec,
dbg_idel_up_all => dbg_idel_up_all,
dbg_idel_down_all => dbg_idel_down_all,
dbg_idel_up_cpt => dbg_idel_up_cpt,
dbg_idel_down_cpt => dbg_idel_down_cpt,
dbg_sel_idel_cpt => dbg_sel_idel_cpt,
dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
dbg_phy_rdlvl => dbg_phy_rdlvl,
dbg_calib_top => dbg_calib_top,
dbg_phy_init => dbg_phy_init,
dbg_prbs_rdlvl => dbg_prbs_rdlvl,
dbg_dqs_found_cal => dbg_dqs_found_cal,
dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done
);
end architecture arch_ddr_phy_top;
|
lgpl-3.0
|
374d84be6e808ecab3bf4770f65b58a2
| 0.508526 | 3.31169 | false | false | false | false |
VectorBlox/risc-v
|
systems/sim/test_components/putchar.vhd
| 1 | 1,297 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
entity putchar_testbench is
generic (
output_file : string := "putchar.out");
port (
-- inputs:
signal address : in std_logic_vector (1 downto 0);
signal chipselect : in std_logic;
signal clk : in std_logic;
signal reset : in std_logic;
signal write_i : in std_logic;
signal writedata : in std_logic_vector (31 downto 0);
signal waitrequest : out std_logic);
end entity putchar_testbench;
architecture rtl of putchar_testbench is
begin
waitrequest <= '0';
process(clk)
variable uart_byte :std_logic_vector(7 downto 0);
file outfile : text;
variable f_status: FILE_OPEN_STATUS;
variable outline : line;
variable out_chr : character;
variable out_str : string(1 downto 1);
begin
if rising_edge(clk) then
if write_i = '1' and chipselect = '1' then
uart_byte := writedata(uart_byte'range);
file_open(f_status,outfile, OUTPUT_FILE,append_mode);
out_chr := character'val(to_integer(unsigned(uart_byte)));
out_str(1) := out_chr;
write(outfile,out_str);
file_close(outfile);
end if;
end if;
end process;
end rtl;
|
bsd-3-clause
|
3433073e99ec7384ad509bc2cc8361c3
| 0.629144 | 3.422164 | false | true | false | false |
fbelavenuto/msx1fpga
|
src/hdmi2/serializer_generic.vhd
| 2 | 3,294 |
-- (c) EMARD
-- LICENSE=BSD
-- generic (vendor-agnostic) serializer
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY serializer_generic IS
GENERIC
(
C_channel_bits: integer := 10; -- number of bits per channel
C_output_bits: integer := 1; -- output bits per channel
C_channels: integer := 3 -- number of channels to serialize
);
PORT
(
tx_in : IN STD_LOGIC_VECTOR(C_channel_bits*C_channels-1 DOWNTO 0);
tx_inclock : IN STD_LOGIC; -- 10x tx_syncclock
tx_syncclock : IN STD_LOGIC;
tx_out : OUT STD_LOGIC_VECTOR((C_channels+1)*C_output_bits-1 DOWNTO 0) -- one more channel for clock
);
END;
ARCHITECTURE SYN OF serializer_generic IS
signal R_tx_latch: std_logic_vector(C_channel_bits*C_channels-1 downto 0);
signal S_tx_clock: std_logic_vector(C_channel_bits-1 downto 0);
type T_channel_shift is array(0 to C_channels) of std_logic_vector(C_channel_bits-1 downto 0); -- -- one channel more for clock
signal S_channel_latch, R_channel_shift: T_channel_shift;
signal R_pixel_clock_toggle, R_prev_pixel_clock_toggle: std_logic;
signal R_clock_edge: std_logic;
constant C_shift_pad: std_logic_vector(C_output_bits-1 downto 0) := (others => '0');
BEGIN
process(tx_syncclock) -- pixel clock
begin
if rising_edge(tx_syncclock) then
R_tx_latch <= tx_in; -- add the clock to be shifted to the channels
end if;
end process;
-- rename - separate to shifted 4 channels
separate_channels:
for i in 0 to C_channels-1 generate
reverse_bits:
for j in 0 to C_channel_bits-1 generate
S_channel_latch(i)(j) <= R_tx_latch(C_channel_bits*(i+1)-j-1);
end generate;
end generate;
S_channel_latch(3) <= "1111100000"; -- the clock pattern
process(tx_syncclock)
begin
if rising_edge(tx_syncclock) then
R_pixel_clock_toggle <= not R_pixel_clock_toggle;
end if;
end process;
-- shift-synchronous pixel clock edge detection
process(tx_inclock) -- pixel shift clock (250 MHz)
begin
if rising_edge(tx_inclock) then -- pixel clock (25 MHz)
R_prev_pixel_clock_toggle <= R_pixel_clock_toggle;
R_clock_edge <= R_pixel_clock_toggle xor R_prev_pixel_clock_toggle;
end if;
end process;
-- fixme: initial state issue (clock shifting?)
process(tx_inclock) -- pixel shift clock
begin
if rising_edge(tx_inclock) then
if R_clock_edge='1' then -- rising edge detection
R_channel_shift(0) <= S_channel_latch(0);
R_channel_shift(1) <= S_channel_latch(1);
R_channel_shift(2) <= S_channel_latch(2);
R_channel_shift(3) <= S_channel_latch(3);
else
R_channel_shift(0) <= C_shift_pad & R_channel_shift(0)(C_channel_bits-1 downto C_output_bits);
R_channel_shift(1) <= C_shift_pad & R_channel_shift(1)(C_channel_bits-1 downto C_output_bits);
R_channel_shift(2) <= C_shift_pad & R_channel_shift(2)(C_channel_bits-1 downto C_output_bits);
R_channel_shift(3) <= C_shift_pad & R_channel_shift(3)(C_channel_bits-1 downto C_output_bits);
end if;
end if;
end process;
tx_out <= R_channel_shift(3)(C_output_bits-1 downto 0)
& R_channel_shift(2)(C_output_bits-1 downto 0)
& R_channel_shift(1)(C_output_bits-1 downto 0)
& R_channel_shift(0)(C_output_bits-1 downto 0);
END SYN;
|
gpl-3.0
|
c87b9bd5c98955ce51759153a9bf1ee5
| 0.66272 | 3.107547 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/infrastructure.vhd
| 1 | 15,716 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: infrastructure.v
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:11 $
-- \ \ / \ Date Created:Tue Jun 30 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Clock generation/distribution and reset synchronization
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: infrastructure.vhd,v 1.1 2011/06/02 07:18:11 mishra Exp $
--**$Date: 2011/06/02 07:18:11 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/ip_top/infrastructure.vhd,v $
--******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library std;
use std.textio.all;
entity infrastructure is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
CLK_PERIOD : integer := 3000; -- Internal (fabric) clk period
nCK_PER_CLK : integer := 2; -- External (memory) clock period =
-- CLK_PERIOD/nCK_PER_CLK
INPUT_CLK_TYPE : string := "DIFFERENTIAL"; -- input clock type
-- "DIFFERENTIAL","SINGLE_ENDED"
MMCM_ADV_BANDWIDTH : string := "OPTIMIZED"; -- MMCM programming algorithm
CLKFBOUT_MULT_F : integer := 2; -- write PLL VCO multiplier
DIVCLK_DIVIDE : integer := 1; -- write PLL VCO divisor
CLKOUT_DIVIDE : integer := 2; -- VCO output divisor for fast
-- (memory) clocks
RST_ACT_LOW : integer := 1
);
port (
-- Clock inputs
mmcm_clk : in std_logic; -- System clock diff input
-- System reset input
sys_rst : in std_logic; -- core reset from user application
-- MMCM/IDELAYCTRL Lock status
iodelay_ctrl_rdy : in std_logic; -- IDELAYCTRL lock status
-- Clock outputs
clk_mem : out std_logic; -- 2x logic clock
clk : out std_logic; -- 1x logic clock
clk_rd_base : out std_logic; -- 2x base read clock
-- Reset outputs
rstdiv0 : out std_logic; -- Reset CLK and CLKDIV logic (incl I/O)
-- Phase Shift Interface
PSDONE : out std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic
);
end entity infrastructure;
architecture arch_infrastructure of infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on DCM lock status)
-- COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
constant RST_SYNC_NUM : integer := 15;
-- constant RST_SYNC_NUM : integer := 25;;
-- Round up for clk reset delay to ensure that CLKDIV reset deassertion
-- occurs at same time or after CLK reset deassertion (still need to
-- consider route delay - add one or two extra cycles to be sure!)
constant RST_DIV_SYNC_NUM : integer := (RST_SYNC_NUM+1)/2;
constant CLKIN1_PERIOD : real
:= real((CLKFBOUT_MULT_F * CLK_PERIOD))/
real(DIVCLK_DIVIDE * CLKOUT_DIVIDE * nCK_PER_CLK * 1000); -- in ns
constant VCO_PERIOD : integer
:= (DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK);
constant CLKOUT0_DIVIDE_F : integer := CLKOUT_DIVIDE;
constant CLKOUT1_DIVIDE : integer := CLKOUT_DIVIDE * nCK_PER_CLK;
constant CLKOUT2_DIVIDE : integer := CLKOUT_DIVIDE;
constant CLKOUT0_PERIOD : integer := VCO_PERIOD * CLKOUT0_DIVIDE_F;
constant CLKOUT1_PERIOD : integer := VCO_PERIOD * CLKOUT1_DIVIDE ;
constant CLKOUT2_PERIOD : integer := VCO_PERIOD * CLKOUT2_DIVIDE ;
signal clk_bufg : std_logic;
signal clk_mem_bufg : std_logic;
signal clk_mem_pll : std_logic;
signal clk_pll : std_logic;
signal clkfbout_pll : std_logic;
signal pll_lock : std_logic;
-- synthesis syn_maxfan = 10
signal rstdiv0_sync_r : std_logic_vector(RST_DIV_SYNC_NUM-1 downto 0);
-- synthesis syn_maxfan = 10
signal rst_tmp : std_logic;
signal sys_rst_act_hi : std_logic;
attribute syn_maxfan : integer;
attribute syn_maxfan of rstdiv0_sync_r : signal is 10 ;
begin
sys_rst_act_hi <= (not sys_rst) when(RST_ACT_LOW = 1) else (sys_rst);
--synthesis translate_off
print : process is
variable my_line : line;
begin
write(my_line, string'("############# Write Clocks MMCM_ADV Parameters #############"));
writeline(output, my_line);
write(my_line, string'("nCK_PER_CLK = "));
write(my_line, nCK_PER_CLK);
writeline(output, my_line);
write(my_line, string'("CLK_PERIOD = "));
write(my_line, CLK_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKIN1_PERIOD = "));
write(my_line, CLKIN1_PERIOD);
writeline(output, my_line);
write(my_line, string'("DIVCLK_DIVIDE = "));
write(my_line, DIVCLK_DIVIDE);
writeline(output, my_line);
write(my_line, string'("CLKFBOUT_MULT_F = "));
write(my_line, CLKFBOUT_MULT_F);
writeline(output, my_line);
write(my_line, string'("VCO_PERIOD = "));
write(my_line, VCO_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKOUT0_DIVIDE_F = "));
write(my_line, CLKOUT0_DIVIDE_F);
writeline(output, my_line);
write(my_line, string'("CLKOUT1_DIVIDE = "));
write(my_line, CLKOUT1_DIVIDE);
writeline(output, my_line);
write(my_line, string'("CLKOUT2_DIVIDE = "));
write(my_line, CLKOUT2_DIVIDE);
writeline(output, my_line);
write(my_line, string'("CLKOUT0_PERIOD = "));
write(my_line, CLKOUT0_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKOUT1_PERIOD = "));
write(my_line, CLKOUT1_PERIOD);
writeline(output, my_line);
write(my_line, string'("CLKOUT2_PERIOD = "));
write(my_line, CLKOUT2_PERIOD);
writeline(output, my_line);
write(my_line, string'("############################################################"));
writeline(output, my_line);
wait;
end process print;
--synthesis translate_on
--***************************************************************************
-- Assign global clocks:
-- 1. clk_mem : Full rate (used only for IOB)
-- 2. clk : Half rate (used for majority of internal logic)
--***************************************************************************
clk_mem <= clk_mem_bufg;
clk <= clk_bufg;
--***************************************************************************
-- Global base clock generation and distribution
--***************************************************************************
--*****************************************************************
-- NOTES ON CALCULTING PROPER VCO FREQUENCY
-- 1. VCO frequency =
-- 1/((DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK))
-- 2. VCO frequency must be in the range [800MHz, 1.2MHz] for -1 part.
-- The lower limit of 800MHz is greater than the lower supported
-- frequency of 400MHz according to the datasheet because the MMCM
-- jitter performance improves significantly when the VCO is operatin
-- above 800MHz. For speed grades faster than -1, the max VCO frequency
-- will be highe, and the multiply and divide factors can be adjusted
-- according (in general to run the VCO as fast as possible).
--*****************************************************************
u_mmcm_adv : MMCM_ADV
generic map (
BANDWIDTH => MMCM_ADV_BANDWIDTH,
CLOCK_HOLD => FALSE,
COMPENSATION => "INTERNAL",
REF_JITTER1 => 0.005,
REF_JITTER2 => 0.005,
STARTUP_WAIT => FALSE,
CLKIN1_PERIOD => CLKIN1_PERIOD,
CLKIN2_PERIOD => 10.000,
CLKFBOUT_MULT_F => real(CLKFBOUT_MULT_F),
DIVCLK_DIVIDE => DIVCLK_DIVIDE,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(CLKOUT0_DIVIDE_F),
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_PHASE => 0.000,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_PHASE => 0.000,
CLKOUT1_USE_FINE_PS => FALSE,
CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT2_PHASE => 0.000,
CLKOUT2_USE_FINE_PS => TRUE,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT3_PHASE => 0.000,
CLKOUT3_USE_FINE_PS => FALSE,
CLKOUT4_CASCADE => FALSE,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT4_PHASE => 0.000,
CLKOUT4_USE_FINE_PS => FALSE,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500,
CLKOUT5_PHASE => 0.000,
CLKOUT5_USE_FINE_PS => FALSE,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500,
CLKOUT6_PHASE => 0.000,
CLKOUT6_USE_FINE_PS => FALSE
)
port map (
CLKFBOUT => clkfbout_pll,
CLKFBOUTB => open,
CLKFBSTOPPED => open,
CLKINSTOPPED => open,
CLKOUT0 => clk_mem_pll,
CLKOUT0B => open,
CLKOUT1 => clk_pll,
CLKOUT1B => open,
CLKOUT2 => clk_rd_base, -- Performance path for inner columns
CLKOUT2B => open,
CLKOUT3 => open, -- Performance path for outer columns
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
DO => open,
DRDY => open,
LOCKED => pll_lock,
PSDONE => PSDONE,
CLKFBIN => clkfbout_pll,
CLKIN1 => mmcm_clk,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => x"0000",
DWE => '0',
PSCLK => clk_bufg,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PWRDWN => '0',
RST => sys_rst_act_hi
);
u_bufg_clk0 : BUFG
port map (
O => clk_mem_bufg,
I => clk_mem_pll
);
u_bufg_clkdiv0 : BUFG
port map (
O => clk_bufg,
I => clk_pll
);
--***************************************************************************
-- RESET SYNCHRONIZATION DESCRIPTION:
-- Various resets are generated to ensure that:
-- 1. All resets are synchronously deasserted with respect to the clock
-- domain they are interfacing to. There are several different clock
-- domains - each one will receive a synchronized reset.
-- 2. The reset deassertion order starts with deassertion of SYS_RST,
-- followed by deassertion of resets for various parts of the design
-- (see "RESET ORDER" below) based on the lock status of MMCMs.
-- RESET ORDER:
-- 1. User deasserts SYS_RST
-- 2. Reset MMCM and IDELAYCTRL
-- 3. Wait for MMCM and IDELAYCTRL to lock
-- 4. Release reset for all I/O primitives and internal logic
-- OTHER NOTES:
-- 1. Asynchronously assert reset. This way we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers
-- to prevent initial bus contention). Reset deassertion is synchronous.
--***************************************************************************
--*****************************************************************
-- CLK and CLKDIV logic reset
--*****************************************************************
-- Wait for both PLL's and IDELAYCTRL to lock
rst_tmp <= sys_rst_act_hi or (not pll_lock) or (not iodelay_ctrl_rdy);
process(clk_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rstdiv0_sync_r <= (others => '1') after (TCQ)*1 ps;
elsif(clk_bufg'event and clk_bufg = '1') then
rstdiv0_sync_r <= (rstdiv0_sync_r(RST_DIV_SYNC_NUM-2 downto 0) & '0') after (TCQ)*1 ps;
end if;
end process;
rstdiv0 <= rstdiv0_sync_r(RST_DIV_SYNC_NUM-1);
end architecture arch_infrastructure;
|
lgpl-3.0
|
15945c1efbd37c36aeaf8f00eb66eb7f
| 0.555548 | 4.107684 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd
| 1 | 8,621 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dbe_wishbone_pkg.all;
use work.wishbone_pkg.all;
entity wb_dbe_periph is
generic(
-- NOT used!
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period : integer := 100000; -- 100MHz clock, ms granularity
g_num_leds : natural := 8;
g_num_buttons : natural := 8
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- LEDs
led_out_o : out std_logic_vector(g_num_leds-1 downto 0);
led_in_i : in std_logic_vector(g_num_leds-1 downto 0);
led_oen_o : out std_logic_vector(g_num_leds-1 downto 0);
-- Buttons
button_out_o : out std_logic_vector(g_num_buttons-1 downto 0);
button_in_i : in std_logic_vector(g_num_buttons-1 downto 0);
button_oen_o : out std_logic_vector(g_num_buttons-1 downto 0);
-- Wishbone
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic
);
end wb_dbe_periph;
architecture rtl of wb_dbe_periph is
-----------------------------
-- Crossbar component constants
-----------------------------
-- Internal crossbar layout
-- 0 -> Simple UART.
-- 1 -> Board LEDs.
-- 2 -> Board Buttons.
-- 3 -> TICs counter.
constant c_slaves : natural := 4;
-- Number of masters
constant c_masters : natural := 1; -- Top master.
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(c_xwb_uart_sdb, x"00000000"), -- UART
1 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"00000100"), -- LEDs
2 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"00000200"), -- Buttons
3 => f_sdb_embed_device(c_xwb_tics_counter_sdb, x"00000300") -- TICs counter
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"00000400";
signal cbar_slave_in : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
begin
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_in,
slave_o => cbar_slave_out,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_in,
master_o => cbar_master_out
);
-- External master connection
cbar_slave_in(0).adr <= wb_adr_i;
cbar_slave_in(0).dat <= wb_dat_i;
cbar_slave_in(0).sel <= wb_sel_i;
cbar_slave_in(0).we <= wb_we_i;
cbar_slave_in(0).cyc <= wb_cyc_i;
cbar_slave_in(0).stb <= wb_stb_i;
wb_dat_o <= cbar_slave_out(0).dat;
wb_ack_o <= cbar_slave_out(0).ack;
wb_err_o <= cbar_slave_out(0).err;
wb_rty_o <= cbar_slave_out(0).rty;
wb_stall_o <= cbar_slave_out(0).stall;
-- Slave 0 is the UART
cmp_uart : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
slave_i => cbar_master_out(0),
slave_o => cbar_master_in(0),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
-- Slave 1 is the LED driver
cmp_leds : xwb_gpio_port
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => g_num_leds,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Wishbone
slave_i => cbar_master_out(1),
slave_o => cbar_master_in(1),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => led_out_o,
gpio_in_i => led_in_i,
gpio_oen_o => led_oen_o
);
-- Slave 2 is the Button driver
cmp_buttons : xwb_gpio_port
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_pins => g_num_buttons,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Wishbone
slave_i => cbar_master_out(2),
slave_o => cbar_master_in(2),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => button_out_o,
gpio_in_i => button_in_i,
gpio_oen_o => button_oen_o
);
-- Slave 3 is the TICs counter
cmp_xwb_tics : xwb_tics
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => WORD,
--g_interface_mode => g_interface_mode,
--g_address_granularity => g_address_granularity,
g_period => g_cntr_period
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Wishbone
slave_i => cbar_master_out(3),
slave_o => cbar_master_in(3)
);
end rtl;
|
lgpl-3.0
|
7f36b9e06d4ce2df2a1d953f6008e2dc
| 0.407725 | 4.101332 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/video/vdp18/vdp18_pattern.vhd
| 2 | 7,386 |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_pattern.vhd,v 1.8 2006/06/18 10:47:06 arnim Exp $
--
-- Pattern Generation Controller
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.vdp18_pack.opmode_t;
use work.vdp18_pack.access_t;
use work.vdp18_pack.hv_t;
entity vdp18_pattern is
port (
clock_i : in std_logic;
clk_en_5m37_i : in boolean;
clk_en_acc_i : in boolean;
reset_i : in boolean;
opmode_i : in opmode_t;
access_type_i : in access_t;
num_line_i : in hv_t;
vram_d_i : in std_logic_vector(0 to 7);
vert_inc_i : in boolean;
vsync_n_i : in std_logic;
reg_col1_i : in std_logic_vector(0 to 3);
reg_col0_i : in std_logic_vector(0 to 3);
pat_table_o : out std_logic_vector(0 to 9);
pat_name_o : out std_logic_vector(0 to 7);
pat_col_o : out std_logic_vector(0 to 3)
);
end vdp18_pattern;
library ieee;
use ieee.numeric_std.all;
use work.vdp18_pack.all;
architecture rtl of vdp18_pattern is
signal pat_cnt_q : unsigned(0 to 9);
signal pat_name_q,
pat_tmp_q,
pat_shift_q,
pat_col_q : std_logic_vector(0 to 7);
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements:
-- * pattern shift register
-- * pattern color register
-- * pattern counter
--
seq: process (clock_i, reset_i)
begin
if reset_i then
pat_cnt_q <= (others => '0');
pat_name_q <= (others => '0');
pat_tmp_q <= (others => '0');
pat_shift_q <= (others => '0');
pat_col_q <= (others => '0');
elsif clock_i'event and clock_i = '1' then
if clk_en_5m37_i then
-- shift pattern with every pixel clock
pat_shift_q(0 to 6) <= pat_shift_q(1 to 7);
end if;
if clk_en_acc_i then
-- determine register update based on current access type -------------
case access_type_i is
when AC_PNT =>
-- store pattern name
pat_name_q <= vram_d_i;
-- increment pattern counter
pat_cnt_q <= pat_cnt_q + 1;
when AC_PCT =>
-- store pattern color in temporary register
pat_tmp_q <= vram_d_i;
when AC_PGT =>
if opmode_i = OPMODE_MULTIC then
-- set shift register to constant value
-- this value generates 4 bits of color1
-- followed by 4 bits of color0
pat_shift_q <= "11110000";
-- set pattern color from pattern generator memory
pat_col_q <= vram_d_i;
else
-- all other modes:
-- store pattern line in shift register
pat_shift_q <= vram_d_i;
-- move pattern color from temporary register to color register
pat_col_q <= pat_tmp_q;
end if;
when others =>
null;
end case;
end if;
if vert_inc_i then
-- redo patterns of if there are more lines inside this pattern
if num_line_i(0) = '0' then
case opmode_i is
when OPMODE_TEXTM =>
if num_line_i(6 to 8) /= "111" then
pat_cnt_q <= pat_cnt_q - 40;
end if;
when OPMODE_GRAPH1 |
OPMODE_GRAPH2 |
OPMODE_MULTIC =>
if num_line_i(6 to 8) /= "111" then
pat_cnt_q <= pat_cnt_q - 32;
end if;
end case;
end if;
end if;
if vsync_n_i = '0' then
-- reset pattern counter at end of active display area
pat_cnt_q <= (others => '0');
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process col_gen
--
-- Purpose:
-- Generates the color of the current pattern pixel.
--
col_gen: process (opmode_i,
pat_shift_q,
pat_col_q,
reg_col1_i,
reg_col0_i)
variable pix_v : std_logic;
begin
-- default assignment
pat_col_o <= "0000";
pix_v := pat_shift_q(0);
case opmode_i is
-- Text Mode ------------------------------------------------------------
when OPMODE_TEXTM =>
if pix_v = '1' then
pat_col_o <= reg_col1_i;
else
pat_col_o <= reg_col0_i;
end if;
-- Graphics I, II and Multicolor Mode -----------------------------------
when OPMODE_GRAPH1 |
OPMODE_GRAPH2 |
OPMODE_MULTIC =>
if pix_v = '1' then
pat_col_o <= pat_col_q(0 to 3);
else
pat_col_o <= pat_col_q(4 to 7);
end if;
when others =>
null;
end case;
end process col_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
pat_table_o <= std_logic_vector(pat_cnt_q);
pat_name_o <= pat_name_q;
end rtl;
|
gpl-3.0
|
c63d6e0005e8cf1b0b31ed3053326274
| 0.515435 | 4.073911 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/rx_CplD_Channel.vhd
| 1 | 56,008 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: rx_CplD_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity rx_CplD_Transact is
port (
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tready : in std_logic; -- !!
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
CplD_Type : in std_logic_vector(3 downto 0);
Req_ID_Match : in std_logic;
usDex_Tag_Matched : in std_logic;
dsDex_Tag_Matched : in std_logic;
Tlp_has_4KB : in std_logic;
Tlp_has_1DW : in std_logic;
CplD_on_Pool : in std_logic;
CplD_on_EB : in std_logic;
CplD_is_the_Last : in std_logic;
CplD_Tag : in std_logic_vector(C_TAG_WIDTH-1 downto 0);
FC_pop : out std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : out std_logic;
ds_DMA_Bytes : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Tag output to downstream DMA channel
dsDMA_dex_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Handshake Signals with ds Channel for Busy/Done
Tag_Map_Clear : out std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-- Downstream tRAM port A write request
tRAM_weB : in std_logic;
tRAM_addrB : in std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : in std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- Tag output to upstream DMA channel
usDMA_dex_Tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Event Buffer write port
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : out std_logic;
Regs_WrMask : out std_logic_vector(2-1 downto 0);
Regs_WrAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end entity rx_CplD_Transact;
architecture Behavioral of rx_CplD_Transact is
type RxCplDEBStates is (ST_EBWR_IDLE
, ST_EBWR_TAG
, ST_EBWR_DATA
);
signal wb_Write_State : RxCplDEBStates;
type RxCplDTrnStates is (ST_CplD_RESET
, ST_CplD_IDLE
-- , ST_Cpl_HEAD1 -- Cpl Header #1 (not used)
-- , ST_CplD_HEAD1 -- CplD Header #1
, ST_Cpl_HEAD2 -- Cpl Header #2 (not used)
, ST_CplD_HEAD2 -- CplD Header #2
, ST_CplD_AFetch_Special --
, ST_CplD_AFetch_Special_Tail --
, ST_CplD_AFetch -- Target address fetch from tRAM/registers
, ST_CplD_AFetch_THROTTLE -- Target address fetch throttled
, ST_CplD_ONLY_1DW -- Current CplD has only 1 DW
-- , ST_CplD_ONLY_1DW_THROTTLE -- Current CplD has only 1 DW, throttled
, ST_CplD_1ST_DATA -- 1st data payload of the CplD
, ST_CplD_1ST_DATA_THROTTLE -- 1st data payload of the CplD
, ST_CplD_DATA -- data receiving
, ST_CplD_DATA_THROTTLE -- data receiving throttled
, ST_CplD_LAST_DATA -- Last data payload of the CplD
);
-- State variables
signal RxCplDTrn_NextState : RxCplDTrnStates;
signal RxCplDTrn_State : RxCplDTrnStates;
-- State delay
signal RxCplDTrn_State_r1 : RxCplDTrnStates;
signal CplD_State_is_AFetch : std_logic;
signal CplD_State_is_after_AFetch : std_logic;
signal CplD_State_is_AFetch_r1 : std_logic;
-- Shifted-glued payload
signal concat_rd : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- trn_rx stubs
signal m_axis_rx_tdata_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- m_axis_rx_tdata_* in little endian
signal m_axis_rx_tdata_Little : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_Little_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- signal m_axis_rx_tbar_hit_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
signal trn_rsof_n_i : std_logic;
signal in_packet_reg : std_logic;
signal m_axis_rx_tlast_i : std_logic;
signal m_axis_rx_tlast_r1 : std_logic;
signal m_axis_rx_tlast_r2 : std_logic;
signal m_axis_rx_tlast_r3 : std_logic;
signal m_axis_rx_tlast_r4 : std_logic;
-- signal Tlp_has_4KB_r1 : std_logic;
signal m_axis_rx_tkeep_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r2 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r3 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r4 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
-- Whether address increases
signal Addr_Inc : std_logic;
-- Spaces hit
signal FIFO_Space_Hit : std_logic;
signal DDR_Space_Hit : std_logic;
-- DDR write port
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer write port
signal wb_FIFO_we_i : std_logic;
signal wb_FIFO_wsof_i : std_logic;
signal wb_FIFO_weof_i : std_logic;
signal wb_FIFO_sof_marker : std_logic;
signal wb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register write port
signal Regs_WrEn_i : std_logic;
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation @ trn_rsof_n=0
signal Reg_WrAddr_if_last_us : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Reg_WrAddr_if_last_ds : std_logic_vector(C_EP_AWIDTH-1 downto 0);
-- Flow control signals
signal m_axis_rx_tready_i : std_logic;
signal m_axis_rx_tvalid_i : std_logic;
signal m_axis_rx_tvalid_r1 : std_logic;
signal m_axis_rx_tvalid_r2 : std_logic;
signal m_axis_rx_tvalid_r3 : std_logic;
signal m_axis_rx_tvalid_r4 : std_logic;
signal trn_rx_throttle : std_logic;
signal trn_rx_throttle_r1 : std_logic;
signal trn_rx_throttle_r2 : std_logic;
signal trn_rx_throttle_r3 : std_logic;
signal trn_rx_throttle_r4 : std_logic;
-- Downstream DMA transferred bytes count up
signal ds_DMA_Bytes_Add_i : std_logic;
signal ds_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
signal CplD_is_Payloaded : std_logic;
-- Alias for header resolution
signal CplD_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal CplD_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_Leng_in_Bytes_r1 : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_is_1DW : std_logic;
-- Small_CplD means CplD with less than 4 DW payload
signal Small_CplD : std_logic;
signal Small_CplD_r1 : std_logic;
signal RegAddr_us_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal RegAddr_ds_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal CplD_Tag_on_Dex : std_logic;
-- ----------------------------------------------------------------------
signal Req_ID_Match_i : std_logic;
signal Dex_Tag_Matched_i : std_logic;
-- The top bit of the CplD_Tag is for distinguishing data CplD or descriptor CplD
signal MSB_DSP_Tag : std_logic;
signal DSP_Tag_on_RAM : std_logic;
signal DSP_Tag_on_RAM_r1 : std_logic;
signal DSP_Tag_on_RAM_r2 : std_logic;
signal DSP_Tag_on_RAM_r3 : std_logic;
signal DSP_Tag_on_RAM_r4p : std_logic;
signal DSP_Tag_on_FIFO : std_logic;
signal DSP_Tag_on_FIFO_r1 : std_logic;
signal DSP_Tag_on_FIFO_r2 : std_logic;
signal DSP_Tag_on_FIFO_r3 : std_logic;
signal DSP_Tag_on_FIFO_r4p : std_logic;
-- ----------------------------------------------------------------------
signal FC_pop_i : std_logic;
signal Tag_Map_Clear_i : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal Local_Reset_i : std_logic;
-- upstream Descriptors' tags
signal usDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- downstream Descriptors' tags
signal dsDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal tRAM_wea : std_logic_vector(0 downto 0);
signal tRAM_addra : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_dina : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_doutA : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_weB_i : std_logic_vector(0 downto 0);
signal tRAM_DoutA_r1 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_r2 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_dina_aInc : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_latch : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- updates the tag RAM as soon as possible
signal CplD_is_the_Last_r1 : std_logic;
signal Updates_tRAM : std_logic;
signal Updates_tRAM_r1 : std_logic;
signal Update_was_too_late : std_logic;
signal hazard_update : std_logic;
signal hazard_update_r1 : std_logic;
signal hazard_update_r2 : std_logic;
signal hazard_update_r3 : std_logic;
signal hazard_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal hazard_content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tag_matches_hazard : std_logic;
begin
-- Event Buffer write
wb_FIFO_we <= wb_FIFO_we_i;
wb_FIFO_wsof <= wb_FIFO_wsof_i;
wb_FIFO_weof <= wb_FIFO_weof_i;
wb_FIFO_din <= wb_FIFO_din_i;
-- DDR
DDR_wr_sof <= DDR_wr_sof_i;
DDR_wr_eof <= DDR_wr_eof_i;
DDR_wr_v <= DDR_wr_v_i;
DDR_wr_Shift <= DDR_wr_Shift_i;
DDR_wr_Mask <= DDR_wr_Mask_i;
DDR_wr_din <= DDR_wr_din_i;
ds_DMA_Bytes_Add <= ds_DMA_Bytes_Add_i;
ds_DMA_Bytes <= ds_DMA_Bytes_i;
--
Tag_Map_Clear <= Tag_Map_Clear_i;
--
FC_pop <= FC_pop_i;
-- ----------------------------------------------
--
Syn_FC_pop :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_pop_i <= '0';
elsif user_clk'event and user_clk = '1' then
FC_pop_i <= (CplD_on_Pool or CplD_on_EB)
and CplD_is_the_Last
and not MSB_DSP_Tag
and m_axis_rx_tlast_i
and not m_axis_rx_tlast_r1; -- Catch the raising edge of m_axis_rx_tlast
-- and not trn_rx_throttle;
end if;
end process;
-- ----------------------------------------------
-- Synchronous: CplD_is_Payloaded
--
Syn_CplD_is_Payloaded :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_is_Payloaded <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' and trn_rx_throttle = '0' then
CplD_is_Payloaded <= CplD_Type(3) or CplD_Type(1);
else
CplD_is_Payloaded <= CplD_is_Payloaded;
end if;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Accumulation: us_DMA_Bytes
--
Syn_ds_DMA_Bytes_Add :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
ds_DMA_Bytes_Add_i <= '0';
ds_DMA_Bytes_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if m_axis_rx_tlast_i = '1' and trn_rx_throttle = '0'
and CplD_is_Payloaded = '1' and MSB_DSP_Tag = '0'
then
ds_DMA_Bytes_Add_i <= '1';
ds_DMA_Bytes_i <= CplD_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
else
ds_DMA_Bytes_Add_i <= '0';
ds_DMA_Bytes_i <= (others => '0');
end if;
end if;
end process;
-- Registers writing
Regs_WrEn <= Regs_WrEn_i;
Regs_WrMask <= Regs_WrMask_i;
Regs_WrAddr <= Regs_WrAddr_i;
Regs_WrDin <= Regs_WrDin_i;
--- Dex Tag output to us DMA channel
usDMA_dex_Tag <= usDMA_dex_Tag_i;
--- Dex Tag output to ds DMA channel
dsDMA_dex_Tag <= dsDMA_dex_Tag_i;
---------------------------------------------------
Req_ID_Match_i <= Req_ID_Match;
Dex_Tag_Matched_i <= usDex_Tag_Matched or dsDex_Tag_Matched;
-- positive reset
Local_Reset_i <= user_reset;
-- Frame signals
m_axis_rx_tlast_i <= m_axis_rx_tlast;
m_axis_rx_tdata_i <= m_axis_rx_tdata;
m_axis_rx_tkeep_i <= m_axis_rx_tkeep;
m_axis_rx_tvalid_i <= m_axis_rx_tvalid;
m_axis_rx_tready_i <= m_axis_rx_tready;
-- BC of the current TLP payloads
CplD_Leng_in_Bytes <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_TLP_FLD_WIDTH_OF_LENG+3)
& CplD_Length & "00";
-- ( m_axis_rx_tvalid seems never deasserted during packet)
trn_rx_throttle <= not(m_axis_rx_tvalid_i) or not(m_axis_rx_tready_i);
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_AFetch
--
RxFSM_CplD_State_is_AFetch :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
CplD_State_is_AFetch_r1 <= CplD_State_is_AFetch;
case RxCplDTrn_State is
when ST_CplD_AFetch =>
CplD_State_is_AFetch <= '1';
when ST_CplD_AFetch_Special =>
CplD_State_is_AFetch <= '1';
when others =>
CplD_State_is_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_after_AFetch
--
RxFSM_CplD_State_is_after_AFetch :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch_Special_Tail =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_ONLY_1DW =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_1ST_DATA =>
CplD_State_is_after_AFetch <= '1';
when others =>
CplD_State_is_after_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: trn_r*
--
Syn_Delay_trn_r_x :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
m_axis_rx_tlast_r1 <= m_axis_rx_tlast_i;
m_axis_rx_tlast_r2 <= m_axis_rx_tlast_r1;
m_axis_rx_tlast_r3 <= m_axis_rx_tlast_r2;
m_axis_rx_tlast_r4 <= m_axis_rx_tlast_r3;
m_axis_rx_tvalid_r1 <= not(trn_rx_throttle); -- m_axis_rx_tvalid_i;
m_axis_rx_tvalid_r2 <= m_axis_rx_tvalid_r1;
m_axis_rx_tvalid_r3 <= m_axis_rx_tvalid_r2;
m_axis_rx_tvalid_r4 <= m_axis_rx_tvalid_r3;
trn_rx_throttle_r1 <= trn_rx_throttle;
trn_rx_throttle_r2 <= trn_rx_throttle_r1;
trn_rx_throttle_r3 <= trn_rx_throttle_r2;
trn_rx_throttle_r4 <= trn_rx_throttle_r3;
m_axis_rx_tdata_r1 <= m_axis_rx_tdata_i;
m_axis_rx_tdata_r2 <= m_axis_rx_tdata_r1;
m_axis_rx_tdata_r3 <= m_axis_rx_tdata_r2;
m_axis_rx_tdata_r4 <= m_axis_rx_tdata_r3;
m_axis_rx_tkeep_r1 <= m_axis_rx_tkeep_i;
m_axis_rx_tkeep_r2 <= m_axis_rx_tkeep_r1;
m_axis_rx_tkeep_r3 <= m_axis_rx_tkeep_r2;
m_axis_rx_tkeep_r4 <= m_axis_rx_tkeep_r3;
end if;
end process;
-- Endian reversed
m_axis_rx_tdata_Little <= Endian_Invert_64(m_axis_rx_tdata_i(63 downto 32) & m_axis_rx_tdata_i(31 downto 0));
m_axis_rx_tdata_Little_r1 <= Endian_Invert_64(m_axis_rx_tdata_r1(63 downto 32) & m_axis_rx_tdata_r1(31 downto 0));
m_axis_rx_tdata_Little_r2 <= Endian_Invert_64(m_axis_rx_tdata_r2(63 downto 32) & m_axis_rx_tdata_r2(31 downto 0));
m_axis_rx_tdata_Little_r3 <= Endian_Invert_64(m_axis_rx_tdata_r3(63 downto 32) & m_axis_rx_tdata_r3(31 downto 0));
m_axis_rx_tdata_Little_r4 <= Endian_Invert_64(m_axis_rx_tdata_r4(63 downto 32) & m_axis_rx_tdata_r4(31 downto 0));
-- ---------------------------------------------
MSB_DSP_Tag <= CplD_Tag(C_TAG_WIDTH-1);
DSP_Tag_on_RAM <= CplD_on_pool and (not CplD_Tag(C_TAG_WIDTH-1) and not CplD_Tag(C_TAG_WIDTH-2));
DSP_Tag_on_FIFO <= CplD_on_EB and (not CplD_Tag(C_TAG_WIDTH-1) and CplD_Tag(C_TAG_WIDTH-2));
--
-- Delay Synchronous: MSB_DSP_Tag_r1
--
Syn_Delay_MSB_DSP_Tag_r1 :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
DSP_Tag_on_RAM_r1 <= DSP_Tag_on_RAM;
DSP_Tag_on_RAM_r2 <= DSP_Tag_on_RAM_r1;
DSP_Tag_on_RAM_r3 <= DSP_Tag_on_RAM_r2;
DSP_Tag_on_RAM_r4p <= DSP_Tag_on_RAM_r2 or DSP_Tag_on_RAM_r3;
DSP_Tag_on_FIFO_r1 <= DSP_Tag_on_FIFO;
DSP_Tag_on_FIFO_r2 <= DSP_Tag_on_FIFO_r1;
DSP_Tag_on_FIFO_r3 <= DSP_Tag_on_FIFO_r2;
DSP_Tag_on_FIFO_r4p <= DSP_Tag_on_FIFO_r2 or DSP_Tag_on_FIFO_r3;
end if;
end process;
--
-- Delay Synchronous: CplD_Leng_in_Bytes
--
Syn_Delay_CplD_Leng_in_Bytes :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
CplD_Leng_in_Bytes_r1 <= CplD_Leng_in_Bytes;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: RxCplDTrn_State
--
RxFSM_Delay_RxTrn_State :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
RxCplDTrn_State_r1 <= RxCplDTrn_State;
end if;
end process;
-- ----------------------------------------------
-- States synchronous
--
Syn_RxTrn_States :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RxCplDTrn_State <= ST_CplD_RESET;
elsif user_clk'event and user_clk = '1' then
RxCplDTrn_State <= RxCplDTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates :
process (
RxCplDTrn_State
, CplD_Type
, MSB_DSP_Tag
, m_axis_rx_tlast_i
, trn_rx_throttle
, Req_ID_Match_i
, Dex_Tag_Matched_i
)
begin
case RxCplDTrn_State is
when ST_CplD_RESET =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_IDLE =>
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_Cpl_HEAD2 => -- further processing to be done ...
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_HEAD2 =>
if trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_HEAD2;
elsif Req_ID_Match_i = '1' and Dex_Tag_Matched_i = '1' then
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
elsif Req_ID_Match_i = '1' and MSB_DSP_Tag = '0' then
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_AFetch_Special =>
-- !!!!!!!!!!!!!!
-- Suppose 1DW CplD (sof-eof TLP) is not followed back-to-back
-- !!!!!!!!!!!!!!
RxCplDTrn_NextState <= ST_CplD_AFetch_Special_Tail;
when ST_CplD_AFetch_Special_Tail =>
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch_THROTTLE =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_ONLY_1DW =>
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_1ST_DATA =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_1ST_DATA_THROTTLE =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA_THROTTLE =>
if m_axis_rx_tlast_i = '1' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_LAST_DATA => -- Same as IDLE, to support
-- back-to-back transactions
if trn_rx_throttle = '0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when others =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when others =>
RxCplDTrn_NextState <= ST_CplD_RESET;
end case;
end process;
-- -------------------------------------------------
-- Synchronous Registered: Tag_Map_Clear_i
--
RxTrn_Tag_Map_Clear :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_Clear_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
for j in 0 to C_TAG_MAP_WIDTH-1 loop
-- CplD_Tag(C_TAG_WIDTH-2) used as token of BAR
if CplD_Tag(C_TAG_WIDTH-1) = '0'
and CplD_Tag(C_TAG_WIDTH-2-1 downto 0) = CONV_STD_LOGIC_VECTOR(j, C_TAG_WIDTH-2)
and CplD_is_the_Last = '1' then
Tag_Map_Clear_i(j) <= '1';
else
Tag_Map_Clear_i(j) <= '0';
end if;
end loop;
end if;
end process;
-- -------------------------------------------------
-- Synchronous Registered: CplD_Length
--
RxTrn_CplD_Length :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Length <= (others => '0');
CplD_is_1DW <= '0';
Small_CplD <= '0';
Small_CplD_r1 <= '0';
elsif user_clk'event and user_clk = '1' then
Small_CplD_r1 <= Small_CplD;
if trn_rsof_n_i = '0' then
CplD_Length <= Tlp_has_4KB & m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
CplD_is_1DW <= Tlp_has_1DW;
if m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2) = C_ALL_ZEROS(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)
and m_axis_rx_tdata_i(C_TLP_LENG_BIT_BOT+1 downto C_TLP_LENG_BIT_BOT) /= "00"
and m_axis_rx_tdata_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) = "01" -- Cpl/D
then
Small_CplD <= '1';
else
Small_CplD <= '0';
end if;
else
CplD_Length <= CplD_Length;
CplD_is_1DW <= CplD_is_1DW;
Small_CplD <= Small_CplD;
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: Addr_Inc
--
RxFSM_Output_Addr_Inc :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Addr_Inc <= '1';
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
Addr_Inc <= '1';
when ST_CplD_1ST_DATA =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when ST_CplD_ONLY_1DW =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when others =>
Addr_Inc <= Addr_Inc;
end case;
end if;
end process;
-------------------------------------------------
-- Calculation at trn_rsof_n
--
Syn_Dex_wrAddress :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Reg_WrAddr_if_last_us <= (others => '0'); -- C_REGS_BASE_ADDR;
Reg_WrAddr_if_last_ds <= (others => '0'); -- C_REGS_BASE_ADDR;
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' then
Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_CTRL, C_EP_AWIDTH-2-2)
- m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_CTRL, C_EP_AWIDTH-2-2)
- m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
-- Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_STA, C_EP_AWIDTH-2-2) - m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
-- Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_STA, C_EP_AWIDTH-2-2) - m_axis_rx_tdata_i(C_NEXT_BD_LENG_MSB downto 0);
else
Reg_WrAddr_if_last_us <= Reg_WrAddr_if_last_us;
Reg_WrAddr_if_last_ds <= Reg_WrAddr_if_last_ds;
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous: RegAddr_?s_Dex
--
RxFSM_Reg_RegAddr_xs_Dex :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RegAddr_us_Dex <= (others => '1');
RegAddr_ds_Dex <= (others => '1');
elsif user_clk'event and user_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) /= C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_us_Dex <= (others => '1');
elsif CplD_is_the_Last = '1' then -- us last/2nd dex
RegAddr_us_Dex <= Reg_WrAddr_if_last_us;
else -- us 1st/unique dex
RegAddr_us_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) /= C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_ds_Dex <= (others => '1');
elsif CplD_is_the_Last = '1' then -- ds last/2nd dex
RegAddr_ds_Dex <= Reg_WrAddr_if_last_ds;
else -- ds 1st/unique dex
RegAddr_ds_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous Delay: CplD_Tag_on_Dex
--
RxFSM_Delay_CplD_Tag_on_Dex :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Tag_on_Dex <= '0';
elsif user_clk'event and user_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) = C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
elsif CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) = C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
else
CplD_Tag_on_Dex <= '0';
end if;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers
--
RxFSM_Output_DMA_Registers :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_AFetch_Special =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_1ST_DATA =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_ONLY_1DW =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_DATA =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & not(m_axis_rx_tkeep_r1(3) and m_axis_rx_tkeep_r1(0));
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when ST_CplD_LAST_DATA =>
if CplD_Tag_on_Dex = '1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & not(m_axis_rx_tkeep_r1(3) and m_axis_rx_tkeep_r1(0));
Regs_WrDin_i <= m_axis_rx_tdata_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end if;
when others =>
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrDin_i <= (others => '0');
end case;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers write Address
--
RxFSM_Output_DMA_Registers_WrAddr :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrAddr_i <= (others => '1');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_IDLE =>
Regs_WrAddr_i <= (others => '1');
when ST_CplD_AFetch =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_AFetch_Special =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_1ST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_ONLY_1DW =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_LAST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when others =>
Regs_WrAddr_i <= Regs_WrAddr_i;
end case;
end if;
end process;
-----------------------------------------------------
-- Synchronous Register:
-- dsDMA_dex_Tag_i
-- usDMA_dex_Tag_i
--
FSM_Reg_DMA_dex_Tags :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
usDMA_dex_Tag_i <= C_TAG0_DMA_USB;
dsDMA_dex_Tag_i <= C_TAG0_DMA_DSB;
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when ST_CplD_AFetch_Special =>
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if m_axis_rx_tdata_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT) = dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when others =>
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end case;
end if;
end process;
-- -------------------------------------------------------------
-- RAM holding downstream Tags of packet MRd requests
-- -------------------------------------------------------------
tRAM_addra <= CplD_Tag(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_weB_i(0) <= tRAM_weB;
dspTag_BRAM :
generic_dpram
generic map(
g_data_width => 36,
g_size => 64,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => "none",
g_dual_clock => false)
port map(
rst_n_i => '1',
clka_i => user_clk,
clkb_i => user_clk,
wea_i => tRAM_wea(0) ,
aa_i => tRAM_addra ,
da_i => tRAM_dina ,
qa_o => tRAM_doutA ,
web_i => tRAM_weB_i(0) ,
ab_i => tRAM_addrB ,
db_i => tRAM_dinB ,
qb_o => open
);
-- Synchronous delay: CplD_is_the_Last
--
Syn_Delay_CplD_is_the_Last :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
CplD_is_the_Last_r1 <= CplD_is_the_Last;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Updates_tRAM
-- Update happens only at data TLP
-- The last CplD of one MRd does not trigger tRAM update,
-- to enable back-to-back transactions.
--
RxFSM_Output_Updates_tRAM :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Updates_tRAM <= '0';
elsif user_clk'event and user_clk = '1' then
Updates_tRAM <= CplD_State_is_AFetch
and (DSP_Tag_on_RAM_r1 or DSP_Tag_on_FIFO_r1)
-- and not trn_rx_throttle -- m_axis_rx_tvalid_r1
and not CplD_is_the_Last_r1;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Update_was_too_late
-- For 1DW CplD the update might be too late for the
-- next CplD with the same TAG
--
RxFSM_Output_Update_was_too_late :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Update_was_too_late <= '0';
hazard_tag <= (others => '1');
tag_matches_hazard <= '0';
hazard_update <= '0';
hazard_update_r1 <= '0';
hazard_update_r2 <= '0';
hazard_update_r3 <= '0';
elsif user_clk'event and user_clk = '1' then
if Small_CplD_r1 = '1' and CplD_State_is_after_AFetch = '1' then
hazard_update <= '1';
hazard_tag <= CplD_Tag;
else
hazard_update <= '0';
hazard_tag <= hazard_tag;
end if;
if CplD_Tag = hazard_tag then
tag_matches_hazard <= '1';
else
tag_matches_hazard <= '0';
end if;
hazard_update_r1 <= hazard_update;
hazard_update_r2 <= hazard_update_r1;
hazard_update_r3 <= hazard_update_r2;
-- Update_was_too_late <= hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
Update_was_too_late <= hazard_update or hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: Updates_tRAM
--
RxFSM_Delay_Updates_tRAM :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Updates_tRAM_r1 <= Updates_tRAM;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Delay: tRAM_DoutA_r2
--
Delay_tRAM_DoutA :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
tRAM_DoutA_r1 <= hazard_content;
else
tRAM_DoutA_r1 <= tRAM_doutA;
end if;
tRAM_DoutA_r2 <= tRAM_DoutA_r1;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Output: hazard_content
--
Syn_Reg_hazard_content :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
hazard_content <= (others => '1');
elsif user_clk'event and user_clk = '1' then
if tRAM_wea(0) = '1' then
hazard_content <= tRAM_dina;
else
hazard_content <= hazard_content;
end if;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_dina_aInc
--
Syn_Calc_tRAM_dina_aInc :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_dina_aInc <= (CBIT_AINC_IN_TAGRAM => '1',
others => '0'
);
elsif user_clk'event and user_clk = '1' then
tRAM_dina_aInc(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT) <= tRAM_DoutA_r1(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT);
tRAM_dina_aInc(C_TAGBAR_BIT_BOT-1 downto 0) <= tRAM_DoutA_r1(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
+ CplD_Leng_in_Bytes_r1(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
end if;
end process;
tRAM_wea(0) <= Updates_tRAM_r1;
tRAM_dina <= tRAM_dina_aInc;
-- tRAM_dina <= ('1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0))
-- when Addr_Inc='1'
-- else ('0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0));
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_DoutA_latch
--
Syn_tRAM_DoutA_latch :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_DoutA_latch <= (CBIT_AINC_IN_TAGRAM => '1', others => '0');
elsif user_clk'event and user_clk = '1' then
if CplD_State_is_AFetch_r1 = '0' then
tRAM_DoutA_latch <= tRAM_DoutA_latch;
elsif Update_was_too_late = '1' then
tRAM_DoutA_latch <= tRAM_DoutA_r1;
else
tRAM_DoutA_latch <= tRAM_DoutA;
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: DDR_Space_Hit
--
RxFSM_Output_DDR_Space_Hit :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
when ST_CplD_AFetch =>
if m_axis_rx_tlast_r4 = '1' then
DDR_Space_Hit <= DSP_Tag_on_RAM_r1;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= DSP_Tag_on_RAM_r4p;
DDR_wr_v_i <= DSP_Tag_on_RAM_r4p; -- DSP_Tag_on_RAM; -- and not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4);
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= m_axis_rx_tdata_Little_r4;
DDR_wr_Mask_i <= '1' & not(m_axis_rx_tkeep_r4(3) and m_axis_rx_tkeep_r4(0));
elsif DSP_Tag_on_RAM_r1 = '1' then
DDR_Space_Hit <= '1';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
else
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
end if;
when ST_CplD_AFetch_Special =>
if DSP_Tag_on_RAM_r1 = '1' then
DDR_Space_Hit <= '1';
else
DDR_Space_Hit <= '0';
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= m_axis_rx_tlast_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4)) and DDR_Space_Hit;
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= m_axis_rx_tdata_Little_r4;
DDR_wr_Mask_i <= '1' & not(m_axis_rx_tkeep_r4(3) and m_axis_rx_tkeep_r4(0));
when ST_CplD_AFetch_Special_Tail =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_Mask_i <= (others => '0');
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_AFetch_THROTTLE =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= DDR_wr_din_i;
when ST_CplD_1ST_DATA =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_Mask_i <= (others => '0');
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_ONLY_1DW =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_Mask_i <= (others => '0');
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when others =>
if m_axis_rx_tlast_r4 = '1' then
DDR_Space_Hit <= '0';
else
DDR_Space_Hit <= DDR_Space_Hit;
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= m_axis_rx_tlast_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (DDR_wr_sof_i or not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4)) and DDR_Space_Hit;
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= m_axis_rx_tdata_Little_r4;
if DDR_wr_sof_i = '1' then
DDR_wr_Mask_i <= "01";
else
DDR_wr_Mask_i <= not(m_axis_rx_tkeep_r4(4)) & not(m_axis_rx_tkeep_r4(0));
end if;
end case;
end if;
end process;
concat_rd <= m_axis_rx_tdata_r3(31 downto 0) & m_axis_rx_tdata_r4(63 downto 32);
-- -------------------------------------------------
-- Synchronous outputs: wb_FIFO_Write
--
RxFSM_Output_FIFO_Space_Hit :
process (user_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FIFO_Space_Hit <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
FIFO_Space_Hit <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
when ST_CplD_AFetch =>
if DSP_Tag_on_FIFO_r1 = '1' then
FIFO_Space_Hit <= '1';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
else
FIFO_Space_Hit <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= (others => '0');
end if;
when ST_CplD_AFetch_Special =>
if DSP_Tag_on_FIFO_r1 = '1' then
FIFO_Space_Hit <= '1';
else
FIFO_Space_Hit <= '0';
end if;
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= m_axis_rx_tlast_r4 and FIFO_Space_Hit;
wb_FIFO_we_i <= (not (trn_rx_throttle_r4 and not m_axis_rx_tlast_r4)) and FIFO_Space_Hit;
when ST_CplD_AFetch_Special_Tail =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= FIFO_Space_Hit; -- '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= FIFO_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
else
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_AFetch_THROTTLE =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= wb_FIFO_din_i;
when ST_CplD_1ST_DATA =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= FIFO_Space_Hit; -- '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= FIFO_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_ONLY_1DW =>
FIFO_Space_Hit <= FIFO_Space_Hit;
wb_FIFO_wsof_i <= FIFO_Space_Hit; -- '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= FIFO_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
if Update_was_too_late = '1' and tag_matches_hazard = '1' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
wb_FIFO_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when others =>
if m_axis_rx_tlast_r3 = '1' then
FIFO_Space_Hit <= '0';
else
FIFO_Space_Hit <= FIFO_Space_Hit;
end if;
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= m_axis_rx_tlast_r3 and FIFO_Space_Hit;
wb_FIFO_we_i <= (wb_FIFO_wsof_i or not (trn_rx_throttle_r3 and not m_axis_rx_tlast_r3)) and FIFO_Space_Hit;
wb_FIFO_din_i <= Endian_Invert_64(concat_rd);
end case;
end if;
end process;
-- ---------------------------------
-- Regenerate trn_rsof_n signal as in old TRN core
--
TRN_rsof_n_make :
process (user_clk, user_reset)
begin
if user_reset = '1' then
in_packet_reg <= '0';
elsif rising_edge(user_clk) then
if (m_axis_rx_tvalid and m_axis_rx_tready) = '1' then
in_packet_reg <= not(m_axis_rx_tlast);
end if;
end if;
end process;
trn_rsof_n_i <= not(m_axis_rx_tvalid and not(in_packet_reg));
end architecture Behavioral;
|
lgpl-3.0
|
d667cbc4b837c7c842ba8dfb6b021d0f
| 0.534781 | 3.082613 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/vm2413/temporalmixer.vhd
| 2 | 5,665 |
--
-- TemporalMixer.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.vm2413.all;
entity TemporalMixer is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
maddr : out std_logic_vector( 4 downto 0 );
mdata : in SIGNED_LI_TYPE;
mo : out std_logic_vector(9 downto 0);
ro : out std_logic_vector(9 downto 0)
);
end entity;
architecture RTL of TemporalMixer is
signal mmute, rmute : std_logic;
begin
process (clk, reset)
begin
if reset = '1' then
mo <= (others =>'0');
ro <= (others =>'0');
maddr <= (others => '0');
mmute <= '1';
rmute <= '1';
elsif clk'event and clk = '1' then
if clkena='1' then
if stage = 0 then
mo <= "1000000000";
ro <= "1000000000";
if rhythm = '0' then
case slot is
when "00000" => maddr <= "00001"; mmute <='0'; -- CH0
when "00001" => maddr <= "00011"; mmute <='0'; -- CH1
when "00010" => maddr <= "00101"; mmute <='0'; -- CH2
when "00011" => mmute <= '1';
when "00100" => mmute <= '1';
when "00101" => mmute <= '1';
when "00110" => maddr <= "00111"; mmute<='0'; -- CH3
when "00111" => maddr <= "01001"; mmute<='0'; -- CH4
when "01000" => maddr <= "01011"; mmute<='0'; -- CH5
when "01001" => mmute <= '1';
when "01010" => mmute <= '1';
when "01011" => mmute <= '1';
when "01100" => maddr <= "01101"; mmute<='0'; -- CH6
when "01101" => maddr <= "01111"; mmute<='0'; -- CH7
when "01110" => maddr <= "10001"; mmute<='0'; -- CH8
when "01111" => mmute <= '1';
when "10000" => mmute <= '1';
when "10001" => mmute <= '1';
when others =>
end case;
rmute <= '1';
else
case slot is
when "00000" => maddr <= "00001"; mmute <='0'; rmute <='1'; -- CH0
when "00001" => maddr <= "00011"; mmute <='0'; rmute <='1'; -- CH1
when "00010" => maddr <= "00101"; mmute <='0'; rmute <='1'; -- CH2
when "00011" => maddr <= "01111"; mmute <='1'; rmute <='0'; -- SD
when "00100" => maddr <= "10001"; mmute <='1'; rmute <='0'; -- CYM
when "00101" => mmute <='1'; rmute <='1';
when "00110" => maddr <= "00111"; mmute <='0'; rmute <='1'; -- CH3
when "00111" => maddr <= "01001"; mmute <='0'; rmute <='1'; -- CH4
when "01000" => maddr <= "01011"; mmute <='0'; rmute <='1'; -- CH5
when "01001" => maddr <= "01110"; mmute <='1'; rmute <='0'; -- HH
when "01010" => maddr <= "10000"; mmute <='1'; rmute <='0'; -- TOM
when "01011" => maddr <= "01101"; mmute <='1'; rmute <='0'; -- BD
when "01100" => maddr <= "01111"; mmute <='1'; rmute <='0'; -- SD
when "01101" => maddr <= "10001"; mmute <='1'; rmute <='0'; -- CYM
when "01110" => maddr <= "01110"; mmute <='1'; rmute <='0'; -- HH
when "01111" => maddr <= "10000"; mmute <='1'; rmute <='0'; -- TOM
when "10000" => maddr <= "01101"; mmute <='1'; rmute <='0'; -- BD
when "10001" => mmute <='1'; rmute <='1';
when others =>
end case;
end if;
else
if mmute = '0' then
if mdata.sign = '0' then
mo <= "1000000000" + mdata.value;
else
mo <= "1000000000" - mdata.value;
end if;
else
mo <= "1000000000";
end if;
if rmute = '0' then
if mdata.sign = '0' then
ro <= "1000000000" + mdata.value;
else
ro <= "1000000000" - mdata.value;
end if;
else
ro <= "1000000000";
end if;
end if;
end if; end if;
end process;
end architecture;
|
gpl-3.0
|
a11ec4046a9875663d9d6e40bde99dfb
| 0.538041 | 3.906897 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/rd_bitslip.vhd
| 1 | 6,578 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: rd_bitslip.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Shifts and delays data from ISERDES, in both memory clock and internal
-- clock cycles. Used to uniquely shift/delay each byte to align all bytes
-- in data word
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: rd_bitslip.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/rd_bitslip.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity rd_bitslip is
generic (
TCQ : integer := 100
);
port (
clk : in std_logic;
bitslip_cnt : in std_logic_vector(1 downto 0);
clkdly_cnt : in std_logic_vector(1 downto 0);
din : in std_logic_vector(5 downto 0);
qout : out std_logic_vector(3 downto 0)
);
end rd_bitslip;
architecture trans_rd_bitslip of rd_bitslip is
signal din2_r : std_logic;
signal slip_out : std_logic_vector(3 downto 0);
signal slip_out_r : std_logic_vector(3 downto 0);
signal slip_out_r2 : std_logic_vector(3 downto 0);
signal slip_out_r3 : std_logic_vector(3 downto 0);
begin
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
din2_r <= din(2) after (TCQ)*1 ps;
end if;
end process;
--Can shift data from ISERDES from 0-3 fast clock cycles
--NOTE: This is coded combinationally, in order to allow register to
--occur after MUXing of delayed outputs. Timing may be difficult to
--meet on this logic, if necessary, the register may need to be moved
--here instead, or another register added.
process (bitslip_cnt, din, din2_r)
begin
case bitslip_cnt is
when "00" => -- No slip
slip_out <= (din(3) & din(2) & din(1) & din(0));
when "01" => -- Slip = 0.5 cycle
slip_out <= (din(4) & din(3) & din(2) & din(1));
when "10" => -- Slip = 1 cycle
slip_out <= (din(5) & din(4) & din(3) & din(2));
when "11" => -- Slip = 1.5 cycle
slip_out <= (din2_r & din(5) & din(4) & din(3));
when others =>
null;
end case;
end process;
--Can delay up to 3 additional internal clock cycles - this accounts
--not only for delays due to DRAM, PCB routing between different bytes,
--but also differences within the FPGA - e.g. clock skew between different
--I/O columns, and differences in latency between different circular
--buffers or whatever synchronization method (FIFO) is used to get the
--data into the global clock domain
process (clk)
begin
if (clk'event and clk = '1') then
slip_out_r <= slip_out after TCQ*1 ps;
slip_out_r2 <= slip_out_r after TCQ*1 ps;
slip_out_r3 <= slip_out_r2 after TCQ*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
case clkdly_cnt is
when "00" =>
qout <= slip_out after (TCQ)*1 ps;
when "01" =>
qout <= slip_out_r after (TCQ)*1 ps;
when "10" =>
qout <= slip_out_r2 after (TCQ)*1 ps;
when "11" =>
qout <= slip_out_r3 after (TCQ)*1 ps;
when others =>
null;
end case;
end if;
end process;
end trans_rd_bitslip;
|
lgpl-3.0
|
f2036a2285eef7652cd172fca7bfde60
| 0.58574 | 4.003652 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/rom/ipl_rom_mf.vhd
| 2 | 6,136 |
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: ipl_rom_mf.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ipl_rom_mf IS
PORT
(
address : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END ipl_rom_mf;
ARCHITECTURE SYN OF ipl_rom_mf IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../../ROMs/loader/loader.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 13,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../../ROMs/loader/loader.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../../ROMs/loader/loader.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ipl_rom_mf_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
84254073b30ba78d2947a52118874c07
| 0.66721 | 3.546821 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/fmc_adc_common/fmc_adc_buf.vhd
| 1 | 14,477 |
------------------------------------------------------------------------------
-- Title : Wishbone FMC ADC buffers Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-17-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: ADC differential buffers for clock and data.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-12 1.0 lucas.russo Created
-- 2013-19-08 1.1 lucas.russo Refactored to enable use with other FMC ADC boards
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc_adc_pkg.all;
entity fmc_adc_buf is
generic
(
g_with_clk_single_ended : boolean := false;
g_with_data_single_ended : boolean := false;
g_with_data_sdr : boolean := false
);
port
(
-----------------------------
-- External ports
-----------------------------
-- ADC differential clocks. One clock per ADC channel
adc_clk0_p_i : in std_logic := '0';
adc_clk0_n_i : in std_logic := '0';
adc_clk1_p_i : in std_logic := '0';
adc_clk1_n_i : in std_logic := '0';
adc_clk2_p_i : in std_logic := '0';
adc_clk2_n_i : in std_logic := '0';
adc_clk3_p_i : in std_logic := '0';
adc_clk3_n_i : in std_logic := '0';
-- ADC single ended clocks. One clock per ADC channel
adc_clk0_i : in std_logic := '0';
adc_clk1_i : in std_logic := '0';
adc_clk2_i : in std_logic := '0';
adc_clk3_i : in std_logic := '0';
-- Differential ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch0_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch1_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch1_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch2_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch2_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch3_p_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch3_n_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
-- Single ended ADC data channels.
adc_data_ch0_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch1_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch2_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
adc_data_ch3_i : in std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0) := (others => '0');
-- Output clocks
adc_clk0_o : out std_logic;
adc_clk1_o : out std_logic;
adc_clk2_o : out std_logic;
adc_clk3_o : out std_logic;
-- Output data
adc_data_ch0_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0);
adc_data_ch1_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0);
adc_data_ch2_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0);
adc_data_ch3_o : out std_logic_vector(f_num_adc_pins(g_with_data_sdr) - 1 downto 0)
);
end fmc_adc_buf;
architecture rtl of fmc_adc_buf is
-- Number of ADC input pins. This is differente for SDR or DDR ADCs.
constant c_num_in_adc_pins : natural := f_num_adc_pins(g_with_data_sdr);
signal adc_clk0_p_t : std_logic;
signal adc_clk0_n_t : std_logic;
signal adc_clk1_p_t : std_logic;
signal adc_clk1_n_t : std_logic;
signal adc_clk2_p_t : std_logic;
signal adc_clk2_n_t : std_logic;
signal adc_clk3_p_t : std_logic;
signal adc_clk3_n_t : std_logic;
signal adc_data_ch0_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch0_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch1_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch1_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch2_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch2_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch3_p_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
signal adc_data_ch3_n_t : std_logic_vector(f_num_adc_pins(g_with_data_sdr)-1 downto 0);
begin
-- Clock Input
gen_with_input_clk_single_ended : if (g_with_clk_single_ended) generate
adc_clk0_p_t <= adc_clk0_i;
adc_clk1_p_t <= adc_clk1_i;
adc_clk2_p_t <= adc_clk2_i;
adc_clk3_p_t <= adc_clk3_i;
end generate;
gen_without_input_clk_single_ended : if (not g_with_clk_single_ended) generate
adc_clk0_p_t <= adc_clk0_p_i;
adc_clk0_n_t <= adc_clk0_n_i;
adc_clk1_p_t <= adc_clk1_p_i;
adc_clk1_n_t <= adc_clk1_n_i;
adc_clk2_p_t <= adc_clk2_p_i;
adc_clk2_n_t <= adc_clk2_n_i;
adc_clk3_p_t <= adc_clk3_p_i;
adc_clk3_n_t <= adc_clk3_n_i;
end generate;
-- Data Input
gen_with_input_data_single_ended : if (g_with_data_single_ended) generate
adc_data_ch0_p_t <= adc_data_ch0_i;
adc_data_ch1_p_t <= adc_data_ch1_i;
adc_data_ch2_p_t <= adc_data_ch2_i;
adc_data_ch3_p_t <= adc_data_ch3_i;
end generate;
gen_without_input_data_single_ended : if (not g_with_data_single_ended) generate
adc_data_ch0_p_t <= adc_data_ch0_p_i;
adc_data_ch0_n_t <= adc_data_ch0_n_i;
adc_data_ch1_p_t <= adc_data_ch1_p_i;
adc_data_ch1_n_t <= adc_data_ch1_n_i;
adc_data_ch2_p_t <= adc_data_ch2_p_i;
adc_data_ch2_n_t <= adc_data_ch2_n_i;
adc_data_ch3_p_t <= adc_data_ch3_p_i;
adc_data_ch3_n_t <= adc_data_ch3_n_i;
end generate;
-----------------------------
-- ADC clock signal datapath
-----------------------------
gen_with_clk_single_ended : if (g_with_clk_single_ended) generate
cmp_ibuf_adc_clk0 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk0_p_t,
o => adc_clk0_o
);
cmp_ibuf_adc_clk1 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk1_p_t,
o => adc_clk1_o
);
cmp_ibuf_adc_clk2 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk2_p_t,
o => adc_clk2_o
);
cmp_ibuf_adc_clk3 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_clk3_p_t,
o => adc_clk3_o
);
end generate;
-- An IBUGDS intructs the mapper to use the glabal clock nets
--(GCLK pins). Therefore, it gives an error for the following
-- clock topology components, like: BUFIO, BUFR and IODELAY
gen_with_clk_diff : if (not g_with_clk_single_ended) generate
cmp_ibufds_adc_clk0 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk0_p_t,
ib => adc_clk0_n_t,
o => adc_clk0_o
);
cmp_ibufds_adc_clk1 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk1_p_t,
ib => adc_clk1_n_t,
o => adc_clk1_o
);
cmp_ibufds_adc_clk2 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk2_p_t,
ib => adc_clk2_n_t,
o => adc_clk2_o
);
cmp_ibufds_adc_clk3 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk3_p_t,
ib => adc_clk3_n_t,
o => adc_clk3_o
);
end generate;
-----------------------------
-- ADC data signal datapath
-----------------------------
gen_with_data_single_ended : if (g_with_data_single_ended) generate
gen_adc_data_buf : for i in 0 to c_num_in_adc_pins-1 generate
cmp_ibuf_adc_data_ch0 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch0_p_t(i),
o => adc_data_ch0_o(i)
);
cmp_ibuf_adc_data_ch1 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch1_p_t(i),
o => adc_data_ch1_o(i)
);
cmp_ibuf_adc_data_ch2 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch2_p_t(i),
o => adc_data_ch2_o(i)
);
cmp_ibuf_adc_data_ch3 : ibuf
generic map(
IOSTANDARD => "LVDS_25"
)
port map(
i => adc_data_ch3_p_t(i),
o => adc_data_ch3_o(i)
);
end generate;
end generate;
gen_with_data_diff : if (not g_with_data_single_ended) generate
gen_adc_data_buf : for i in 0 to c_num_in_adc_pins-1 generate
cmp_ibufds_adc_data_ch0 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch0_p_t(i),
ib => adc_data_ch0_n_t(i),
o => adc_data_ch0_o(i)
);
cmp_ibufds_adc_data_ch1 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch1_p_t(i),
ib => adc_data_ch1_n_t(i),
o => adc_data_ch1_o(i)
);
cmp_ibufds_adc_data_ch2 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch2_p_t(i),
ib => adc_data_ch2_n_t(i),
o => adc_data_ch2_o(i)
);
cmp_ibufds_adc_data_ch3 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch3_p_t(i),
ib => adc_data_ch3_n_t(i),
o => adc_data_ch3_o(i)
);
end generate;
end generate;
end rtl;
|
lgpl-3.0
|
f1a650f0c76906532aa66b3fce42067b
| 0.393935 | 3.750518 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-de1/de1_top.vhd
| 1 | 18,937 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
--
-- Terasic DE1 top-level
--
-- altera message_off 10540 10541
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.msx_pack.all;
-- Generic top-level entity for Altera DE1 board
entity de1_top is
generic (
per_opll_g : boolean := true;
per_jt51_g : boolean := true
);
port (
-- Clocks
clk50_i : in std_logic;
clk27_i : in std_logic_vector( 1 downto 0);
clk24_i : in std_logic_vector( 1 downto 0);
clk_ext_i : in std_logic;
-- Switches
sw_i : in std_logic_vector( 9 downto 0);
-- Buttons
key_n_i : in std_logic_vector( 3 downto 0);
-- 7 segment displays
display0_o : out std_logic_vector( 6 downto 0) := (others => '1');
display1_o : out std_logic_vector( 6 downto 0) := (others => '1');
display2_o : out std_logic_vector( 6 downto 0) := (others => '1');
display3_o : out std_logic_vector( 6 downto 0) := (others => '1');
-- Red LEDs
ledr_o : out std_logic_vector( 9 downto 0) := (others => '0');
-- Green LEDs
ledg_o : out std_logic_vector( 7 downto 0) := (others => '0');
-- Serial
uart_rx_i : in std_logic;
uart_tx_o : out std_logic := '0';
-- PS/2 Keyboard
ps2_clk_io : inout std_logic := '1';
ps2_dat_io : inout std_logic := '1';
-- I2C
i2c_sclk_io : inout std_logic := '1';
i2c_sdat_io : inout std_logic := '1';
-- Audio
aud_xck_o : out std_logic := '0';
aud_bclk_o : out std_logic := '0';
aud_adclrck_o : out std_logic := '0';
aud_adcdat_i : in std_logic;
aud_daclrck_o : out std_logic := '0';
aud_dacdat_o : out std_logic := '0';
-- SRAM
sram_addr_o : out std_logic_vector(17 downto 0) := (others => '0');
sram_data_io : inout std_logic_vector(15 downto 0) := (others => '0');
sram_ce_n_o : out std_logic := '1';
sram_oe_n_o : out std_logic := '1';
sram_we_n_o : out std_logic := '1';
sram_ub_n_o : out std_logic := '1';
sram_lb_n_o : out std_logic := '1';
-- SDRAM
dram_cke_o : out std_logic := '1';
dram_clk_o : out std_logic := '1';
dram_addr_o : out std_logic_vector(11 downto 0) := (others => '0');
dram_data_io : inout std_logic_vector(15 downto 0) := (others => '0');
dram_cas_n_o : out std_logic := '1';
dram_ras_n_o : out std_logic := '1';
dram_cs_n_o : out std_logic := '1';
dram_we_n_o : out std_logic := '1';
dram_ba_o : out std_logic_vector( 1 downto 0) := "11";
dram_ldqm_o : out std_logic := '1';
dram_udqm_o : out std_logic := '1';
-- Flash
fl_rst_n_o : out std_logic := '1';
fl_addr_o : out std_logic_vector(21 downto 0) := (others => '0');
fl_data_io : inout std_logic_vector( 7 downto 0) := (others => 'Z');
fl_ce_n_o : out std_logic := '1';
fl_oe_n_o : out std_logic := '1';
fl_we_n_o : out std_logic := '1';
-- SD card (SPI mode)
sd_miso_i : in std_logic;
sd_mosi_o : out std_logic := '1';
sd_cs_n_o : out std_logic := '1';
sd_sclk_o : out std_logic := '1';
-- VGA
vga_r_o : out std_logic_vector( 3 downto 0) := (others => '0');
vga_g_o : out std_logic_vector( 3 downto 0) := (others => '0');
vga_b_o : out std_logic_vector( 3 downto 0) := (others => '0');
vga_hsync_n_o : out std_logic := '1';
vga_vsync_n_o : out std_logic := '1';
-- GPIO
gpio0_io : inout std_logic_vector(35 downto 0) := (others => 'Z');
gpio1_io : inout std_logic_vector(35 downto 0) := (others => 'Z')
);
end entity;
architecture behavior of de1_top is
-- Resets
signal pll_locked_s : std_logic;
signal por_s : std_logic;
signal reset_s : std_logic;
signal soft_por_s : std_logic;
signal soft_reset_k_s : std_logic;
signal soft_reset_s_s : std_logic;
signal soft_rst_cnt_s : unsigned( 7 downto 0) := X"FF";
-- Clocks
signal clock_master_s : std_logic;
signal clock_sdram_s : std_logic;
signal clock_vdp_s : std_logic;
signal clock_cpu_s : std_logic;
signal clock_psg_en_s : std_logic;
signal clock_3m_s : std_logic;
signal turbo_on_s : std_logic;
-- RAM
signal ram_addr_s : std_logic_vector(22 downto 0); -- 8MB
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_ce_s : std_logic;
signal ram_oe_s : std_logic;
signal ram_we_s : std_logic;
-- VRAM memory
signal vram_addr_s : std_logic_vector(13 downto 0); -- 16K
signal vram_data_from_s : std_logic_vector( 7 downto 0);
signal vram_data_to_s : std_logic_vector( 7 downto 0);
signal vram_ce_s : std_logic;
signal vram_oe_s : std_logic;
signal vram_we_s : std_logic;
-- Audio
signal audio_scc_s : signed(14 downto 0);
signal audio_psg_s : unsigned(7 downto 0);
signal beep_s : std_logic;
signal ear_s : std_logic;
signal audio_l_s : signed(15 downto 0);
signal audio_r_s : signed(15 downto 0);
signal volumes_s : volumes_t;
-- Video
signal rgb_r_s : std_logic_vector( 3 downto 0);
signal rgb_g_s : std_logic_vector( 3 downto 0);
signal rgb_b_s : std_logic_vector( 3 downto 0);
signal rgb_hsync_n_s : std_logic;
signal rgb_vsync_n_s : std_logic;
signal ntsc_pal_s : std_logic;
signal vga_en_s : std_logic;
-- Keyboard
signal rows_s : std_logic_vector( 3 downto 0);
signal cols_s : std_logic_vector( 7 downto 0);
signal caps_en_s : std_logic;
signal extra_keys_s : std_logic_vector( 3 downto 0);
signal keyb_valid_s : std_logic;
signal keyb_data_s : std_logic_vector( 7 downto 0);
signal keymap_addr_s : std_logic_vector( 8 downto 0);
signal keymap_data_s : std_logic_vector( 7 downto 0);
signal keymap_we_s : std_logic;
-- Joystick (Minimig Standard)
alias J0_UP : std_logic is gpio1_io(34); -- Pin 1
alias J0_DOWN : std_logic is gpio1_io(32); -- Pin 2
alias J0_LEFT : std_logic is gpio1_io(30); -- Pin 3
alias J0_RIGHT : std_logic is gpio1_io(28); -- Pin 4
alias J0_MMB : std_logic is gpio1_io(26); -- Pin 5
alias J0_BTN : std_logic is gpio1_io(35); -- Pin 6
alias J0_BTN2 : std_logic is gpio1_io(29); -- Pin 9
alias J1_UP : std_logic is gpio1_io(24);
alias J1_DOWN : std_logic is gpio1_io(22);
alias J1_LEFT : std_logic is gpio1_io(20);
alias J1_RIGHT : std_logic is gpio1_io(23);
alias J1_MMB : std_logic is gpio1_io(27);
alias J1_BTN : std_logic is gpio1_io(25);
alias J1_BTN2 : std_logic is gpio1_io(21);
-- Bus
signal bus_addr_s : std_logic_vector(15 downto 0);
signal bus_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal bus_data_to_s : std_logic_vector( 7 downto 0);
signal bus_rd_n_s : std_logic;
signal bus_wr_n_s : std_logic;
signal bus_m1_n_s : std_logic;
signal bus_iorq_n_s : std_logic;
signal bus_mreq_n_s : std_logic;
signal bus_sltsl1_n_s : std_logic;
signal bus_sltsl2_n_s : std_logic;
-- JT51
signal jt51_cs_n_s : std_logic;
signal jt51_left_s : signed(15 downto 0) := (others => '0');
signal jt51_right_s : signed(15 downto 0) := (others => '0');
-- OPLL
signal opll_cs_n_s : std_logic := '1';
signal opll_mo_s : signed(12 downto 0) := (others => '0');
signal opll_ro_s : signed(12 downto 0) := (others => '0');
-- Debug
signal D_display_s : std_logic_vector(15 downto 0);
begin
-- PLL
pll_1: entity work.pll1
port map (
inclk0 => clk50_i,
c0 => clock_master_s, -- 21.428571 MHz (6x NTSC)
c1 => clock_sdram_s, -- 85.714286
c2 => dram_clk_o, -- 85.714286 -45°
locked => pll_locked_s
);
-- Clocks
clks: entity work.clocks
port map (
clock_i => clock_master_s,
por_i => not pll_locked_s,
turbo_on_i => turbo_on_s,
clock_vdp_o => clock_vdp_s,
clock_5m_en_o => open,
clock_cpu_o => clock_cpu_s,
clock_psg_en_o => clock_psg_en_s,
clock_3m_o => clock_3m_s
);
-- The MSX1
the_msx: entity work.msx
generic map (
hw_id_g => 1,
hw_txt_g => "DE-1 Board",
hw_version_g => actual_version,
video_opt_g => 0, -- No dblscan
ramsize_g => 8192
)
port map (
-- Clocks
clock_i => clock_master_s,
clock_vdp_i => clock_vdp_s,
clock_cpu_i => clock_cpu_s,
clock_psg_en_i => clock_psg_en_s,
-- Turbo
turbo_on_k_i => extra_keys_s(3), -- F11
turbo_on_o => turbo_on_s,
-- Resets
reset_i => reset_s,
por_i => por_s,
softreset_o => soft_reset_s_s,
-- Options
opt_nextor_i => '1',
opt_mr_type_i => sw_i(2 downto 1),
opt_vga_on_i => '0',
-- RAM
ram_addr_o => ram_addr_s,
ram_data_i => ram_data_from_s,
ram_data_o => ram_data_to_s,
ram_ce_o => ram_ce_s,
ram_we_o => ram_we_s,
ram_oe_o => ram_oe_s,
-- ROM
rom_addr_o => open,
rom_data_i => ram_data_from_s,
rom_ce_o => open,
rom_oe_o => open,
-- External bus
bus_addr_o => bus_addr_s,
bus_data_i => bus_data_from_s,
bus_data_o => bus_data_to_s,
bus_rd_n_o => bus_rd_n_s,
bus_wr_n_o => bus_wr_n_s,
bus_m1_n_o => bus_m1_n_s,
bus_iorq_n_o => bus_iorq_n_s,
bus_mreq_n_o => bus_mreq_n_s,
bus_sltsl1_n_o => bus_sltsl1_n_s,
bus_sltsl2_n_o => bus_sltsl2_n_s,
bus_wait_n_i => '1',
bus_nmi_n_i => '1',
bus_int_n_i => '1',
-- VDP RAM
vram_addr_o => vram_addr_s,
vram_data_i => vram_data_from_s,
vram_data_o => vram_data_to_s,
vram_ce_o => vram_ce_s,
vram_oe_o => vram_oe_s,
vram_we_o => vram_we_s,
-- Keyboard
rows_o => rows_s,
cols_i => cols_s,
caps_en_o => caps_en_s,
keyb_valid_i => keyb_valid_s,
keyb_data_i => keyb_data_s,
keymap_addr_o => keymap_addr_s,
keymap_data_o => keymap_data_s,
keymap_we_o => keymap_we_s,
-- Audio
audio_scc_o => audio_scc_s,
audio_psg_o => audio_psg_s,
beep_o => beep_s,
volumes_o => volumes_s,
-- K7
k7_motor_o => open,
k7_audio_o => open,
k7_audio_i => ear_s,
-- Joystick
joy1_up_i => J0_UP,
joy1_down_i => J0_DOWN,
joy1_left_i => J0_LEFT,
joy1_right_i => J0_RIGHT,
joy1_btn1_i => J0_BTN,
joy1_btn1_o => J0_BTN,
joy1_btn2_i => J0_BTN2,
joy1_btn2_o => J0_BTN2,
joy1_out_o => open,
joy2_up_i => J1_UP,
joy2_down_i => J1_DOWN,
joy2_left_i => J1_LEFT,
joy2_right_i => J1_RIGHT,
joy2_btn1_i => J1_BTN,
joy2_btn1_o => J1_BTN,
joy2_btn2_i => J1_BTN2,
joy2_btn2_o => J1_BTN2,
joy2_out_o => open,
-- Video
rgb_r_o => rgb_r_s,
rgb_g_o => rgb_g_s,
rgb_b_o => rgb_b_s,
hsync_n_o => rgb_hsync_n_s,
vsync_n_o => rgb_vsync_n_s,
ntsc_pal_o => ntsc_pal_s,
vga_on_k_i => extra_keys_s(2), -- Print Screen
scanline_on_k_i=> '0',--extra_keys_s(1), -- Scroll Lock
vga_en_o => vga_en_s,
-- SPI/SD
flspi_cs_n_o => open,
spi_cs_n_o => sd_cs_n_o,
spi_sclk_o => sd_sclk_o,
spi_mosi_o => sd_mosi_o,
spi_miso_i => sd_miso_i,
sd_pres_n_i => '0',
sd_wp_i => '0',
-- DEBUG
D_wait_o => open,
D_slots_o => open,
D_ipl_en_o => open
);
-- Keyboard PS/2
keyb: entity work.keyboard
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
-- MSX
rows_coded_i => rows_s,
cols_o => cols_s,
keymap_addr_i => keymap_addr_s,
keymap_data_i => keymap_data_s,
keymap_we_i => keymap_we_s,
-- LEDs
led_caps_i => caps_en_s,
-- PS/2 interface
ps2_clk_io => ps2_clk_io,
ps2_data_io => ps2_dat_io,
-- Direct Access
keyb_valid_o => keyb_valid_s,
keyb_data_o => keyb_data_s,
--
reset_o => soft_reset_k_s,
por_o => soft_por_s,
reload_core_o => open,
extra_keys_o => extra_keys_s
);
-- VRAM
-- vram: entity work.spram
-- generic map (
-- addr_width_g => 14,
-- data_width_g => 8
-- )
-- port map (
-- clk_i => clock_master_s,
-- we_i => vram_we_s,
-- addr_i => vram_addr_s,
-- data_i => vram_data_to_s,
-- data_o => vram_data_from_s
-- );
sram_addr_o <= "0000" & vram_addr_s;
sram_data_io <= "ZZZZZZZZ" & vram_data_to_s when vram_we_s = '1' else
(others => 'Z');
vram_data_from_s <= sram_data_io( 7 downto 0);
sram_ub_n_o <= '1';
sram_lb_n_o <= '0';
sram_ce_n_o <= not vram_ce_s;
sram_oe_n_o <= not vram_oe_s;
sram_we_n_o <= not vram_we_s;
-- RAM
ram: entity work.ssdram
generic map (
freq_g => 86,
rfsh_cycles_g => 4096,
rfsh_period_g => 64
)
port map (
clock_i => clock_sdram_s,
reset_i => reset_s,
refresh_i => '1',
-- Static RAM bus
addr_i => ram_addr_s,
data_i => ram_data_to_s,
data_o => ram_data_from_s,
cs_i => ram_ce_s,
oe_i => ram_oe_s,
we_i => ram_we_s,
-- SD-RAM ports
mem_cke_o => dram_cke_o,
mem_cs_n_o => dram_cs_n_o,
mem_ras_n_o => dram_ras_n_o,
mem_cas_n_o => dram_cas_n_o,
mem_we_n_o => dram_we_n_o,
mem_udq_o => dram_udqm_o,
mem_ldq_o => dram_ldqm_o,
mem_ba_o => dram_ba_o,
mem_addr_o => dram_addr_o,
mem_data_io => dram_data_io
);
-- Audio
mixer: entity work.mixers
port map (
clock_i => clock_master_s,
reset_i => reset_s,
volumes_i => volumes_s,
beep_i => beep_s,
ear_i => ear_s,
audio_scc_i => audio_scc_s,
audio_psg_i => audio_psg_s,
jt51_left_i => jt51_left_s,
jt51_right_i => jt51_right_s,
opll_mo_i => opll_mo_s,
opll_ro_i => opll_ro_s,
audio_mix_l_o => audio_l_s,
audio_mix_r_o => audio_r_s
);
codec: entity work.WM8731
port map (
clock_i => clk24_i(0),
reset_i => reset_s,
k7_audio_o => ear_s,
audio_l_i => audio_l_s,
audio_r_i => audio_r_s,
i2s_xck_o => aud_xck_o,
i2s_bclk_o => aud_bclk_o,
i2s_adclrck_o => aud_adclrck_o,
i2s_adcdat_i => aud_adcdat_i,
i2s_daclrck_o => aud_daclrck_o,
i2s_dacdat_o => aud_dacdat_o,
i2c_sda_io => i2c_sdat_io,
i2c_scl_io => i2c_sclk_io
);
-- Glue logic
-- Resets
por_s <= '1' when key_n_i(3) = '0' or pll_locked_s = '0' or soft_por_s = '1' else '0';
reset_s <= '1' when key_n_i(0) = '0' or soft_rst_cnt_s = X"00" or por_s = '1' else '0';
process(clock_master_s)
begin
if rising_edge(clock_master_s) then
if reset_s = '1' or por_s = '1' then
soft_rst_cnt_s <= X"FF";
elsif (soft_reset_k_s = '1' or soft_reset_s_s = '1') and soft_rst_cnt_s /= X"00" then
soft_rst_cnt_s <= soft_rst_cnt_s - 1;
end if;
end if;
end process;
-- VGA Output
vga_r_o <= rgb_r_s;
vga_g_o <= rgb_g_s;
vga_b_o <= rgb_b_s;
vga_hsync_n_o <= rgb_hsync_n_s;
vga_vsync_n_o <= rgb_vsync_n_s;
ptjt: if per_jt51_g generate
-- JT51 tests
jt51_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0010000" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x20 - 0x21
jt51: entity work.jt51_wrapper
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
addr_i => bus_addr_s(0),
cs_n_i => jt51_cs_n_s,
wr_n_i => bus_wr_n_s,
rd_n_i => bus_rd_n_s,
data_i => bus_data_to_s,
data_o => bus_data_from_s,
ct1_o => open,
ct2_o => open,
irq_n_o => open,
p1_o => open,
-- Low resolution output (same as real chip)
sample_o => open,
left_o => open,
right_o => open,
-- Full resolution output
xleft_o => jt51_left_s,
xright_o => jt51_right_s,
-- unsigned outputs for sigma delta converters, full resolution
dacleft_o => open,
dacright_o => open
);
end generate;
popll: if per_opll_g generate
-- OPLL tests
opll_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0111110" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x7C - 0x7D
opll1 : entity work.opll
port map (
clock_i => clock_master_s,
clock_en_i => clock_psg_en_s,
reset_i => reset_s,
data_i => bus_data_to_s,
addr_i => bus_addr_s(0),
cs_n => opll_cs_n_s,
we_n => bus_wr_n_s,
melody_o => opll_mo_s,
rythm_o => opll_ro_s
);
end generate;
-- DEBUG
D_display_s <= bus_addr_s;
ledg_o(0) <= turbo_on_s;
ledg_o(1) <= vga_en_s;
ledg_o(2) <= ntsc_pal_s;
ld3: entity work.seg7
port map(
D => D_display_s(15 downto 12),
Q => display3_o
);
ld2: entity work.seg7
port map(
D => D_display_s(11 downto 8),
Q => display2_o
);
ld1: entity work.seg7
port map(
D => D_display_s(7 downto 4),
Q => display1_o
);
ld0: entity work.seg7
port map(
D => D_display_s(3 downto 0),
Q => display0_o
);
end architecture;
|
gpl-3.0
|
693b72fd5fb67cc5f7b1894b9a469bd2
| 0.554183 | 2.30393 | false | false | false | false |
VectorBlox/risc-v
|
systems/sim/test_components/clock_gen.vhd
| 1 | 2,732 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
--Simple clock generator that generates clocks in a manner suitable for
--simulation of synchronous clocks (i.e. all clocks change on the same tick).
entity clock_gen is
generic(
CLK_MHZ : positive := 100
);
port(
clk_out : out std_logic;
clk_out_2x : out std_logic;
clk_out_3x : out std_logic
);
end entity;
architecture rtl of clock_gen is
--Ticks at 1/12 a clock period so as to generate clks 1x/2x/3x (LCM 6, need 2
--phases per clock)
constant TICK_PERIOD_PS : real := (1000.0*1000.0)/(12.0*real(CLK_MHZ));
signal clks : std_logic_vector(2 downto 0);
begin -- architecture rtl
process
variable leftover_time_ps : real := 0.0;
variable wait_time_ps : positive := positive(ROUND(TICK_PERIOD_PS));
begin
clks <= "111";
wait_time_ps := positive(ROUND((2.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((2.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
clks <= "110";
wait_time_ps := positive(ROUND((1.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((1.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
clks <= "100";
wait_time_ps := positive(ROUND((1.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((1.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
clks <= "101";
wait_time_ps := positive(ROUND((2.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((2.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
clks <= "010";
wait_time_ps := positive(ROUND((2.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((2.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
clks <= "011";
wait_time_ps := positive(ROUND((1.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((1.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
clks <= "001";
wait_time_ps := positive(ROUND((1.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((1.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
clks <= "000";
wait_time_ps := positive(ROUND((2.0*TICK_PERIOD_PS)+leftover_time_ps));
leftover_time_ps := ((2.0*TICK_PERIOD_PS)+leftover_time_ps) - real(wait_time_ps);
wait for wait_time_ps*(1 ps);
end process;
clk_out <= clks(2);
clk_out_2x <= clks(1);
clk_out_3x <= clks(0);
end architecture rtl;
|
bsd-3-clause
|
0f8690753cb08992e446a58f57e4fd77
| 0.629575 | 2.900212 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/bpm_pcie_ml605.vhd
| 1 | 55,209 |
----------------------------------------------------------------------------------
-- Company: Creotech
-- Engineer: Adrian Byszuk ([email protected])
--
-- Design Name:
-- Module Name: bpm_pcie_ml605 - Behavioral
-- Project Name:
-- Target Devices: XC7A200T on AC uTCA card from OHWR
-- Tool versions: ISE 14.4, ISE 14.6
-- Description: This is TOP module for the versatile firmware for PCIe communication.
-- It provides DMA engine with scatter-gather (linked list) functionality.
-- DDR memory is supported through BAR1. Wishbone endpoint is accessible through BAR2.
--
-- Dependencies: Xilinx PCIe core for 7 series. Xilinx DDR core for 7 series.
--
-- Revision: 2.00 - Original file completely rewritten by abyszuk.
--
-- Revision 1.00 - File Released
--
-- Additional Comments: This file can be used both as TOP module for independent operation, or
-- instantiated in another projects. To use it in your project, change INSTANTIATED generic to
-- "TRUE" and uncomment relevant interface sections in entity declaration. ATTENTION: you also
-- have to comment out dummy signal with names exactly the same as port names (it was necessary so
-- that XST won't complain about missing signal names).
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity bpm_pcie_ml605 is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1;
SIM_BYPASS_INIT_CAL : string := "FAST"
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
---- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end entity bpm_pcie_ml605;
architecture Behavioral of bpm_pcie_ml605 is
constant DDR_ADDR_WIDTH : integer := 28;
component pcie_core
generic (
PL_FAST_TRAIN : string := "FALSE";
UPSTREAM_FACING : string := "TRUE"
);
port (
-------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
-------------------------------------------------------------------------------------------------------------------
pci_exp_txp : out std_logic_vector(3 downto 0);
pci_exp_txn : out std_logic_vector(3 downto 0);
pci_exp_rxp : in std_logic_vector(3 downto 0);
pci_exp_rxn : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 2. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out : out std_logic;
user_reset_out : out std_logic;
user_lnk_up : out std_logic;
-- TX
tx_buf_av : out std_logic_vector(5 downto 0);
tx_cfg_req : out std_logic;
tx_err_drop : out std_logic;
s_axis_tx_tready : out std_logic;
s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
s_axis_tx_tlast : in std_logic;
s_axis_tx_tvalid : in std_logic;
s_axis_tx_tuser : in std_logic_vector(3 downto 0);
tx_cfg_gnt : in std_logic;
-- RX
m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
m_axis_rx_tlast : out std_logic;
m_axis_rx_tvalid : out std_logic;
m_axis_rx_tready : in std_logic;
m_axis_rx_tuser : out std_logic_vector(21 downto 0);
rx_np_ok : in std_logic;
-- Flow Control
fc_cpld : out std_logic_vector(11 downto 0);
fc_cplh : out std_logic_vector(7 downto 0);
fc_npd : out std_logic_vector(11 downto 0);
fc_nph : out std_logic_vector(7 downto 0);
fc_pd : out std_logic_vector(11 downto 0);
fc_ph : out std_logic_vector(7 downto 0);
fc_sel : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 3. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
cfg_di : in std_logic_vector(31 downto 0);
cfg_byte_en : in std_logic_vector(3 downto 0);
cfg_dwaddr : in std_logic_vector(9 downto 0);
cfg_wr_en : in std_logic;
cfg_rd_en : in std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state : out std_logic_vector(2 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_pmcsr_pme_status : out std_logic;
-- Error Reporting Interface
cfg_err_ecrc : in std_logic;
cfg_err_ur : in std_logic;
cfg_err_cpl_timeout : in std_logic;
cfg_err_cpl_unexpect : in std_logic;
cfg_err_cpl_abort : in std_logic;
cfg_err_posted : in std_logic;
cfg_err_cor : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy : out std_logic;
cfg_err_locked : in std_logic;
cfg_trn_pending : in std_logic;
cfg_dsn : std_logic_vector(63 downto 0);
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt : in std_logic;
cfg_interrupt_rdy : out std_logic;
cfg_interrupt_assert : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_to_turnoff : out std_logic;
cfg_turnoff_ok : in std_logic;
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_pm_wake : in std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 4. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_auton : in std_logic;
pl_upstream_prefer_deemph : in std_logic;
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_link_partner_gen2_supported : out std_logic;
pl_initial_link_width : out std_logic_vector(2 downto 0);
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 6. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
sys_clk : in std_logic;
sys_reset : in std_logic);
end component;
component ddr_v6
generic(
SIM_BYPASS_INIT_CAL : string := "OFF";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Skip memory init &
-- calibration sequence
-- # = "FAST" - Skip memory init & use
-- abbreviated calib sequence
RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port(
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
sda : inout std_logic;
scl : out std_logic;
app_addr : in std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
ui_clk_sync_rst : out std_logic;
ui_clk : out std_logic;
phy_init_done : out std_logic;
sys_clk : in std_logic;
clk_ref : in std_logic;
sys_rst : in std_logic
);
end component ddr_v6;
-- -----------------------------------------------------------------------
-- DDR SDRAM control module
-- -----------------------------------------------------------------------
component bram_DDRs_Control_loopback
generic (
C_ASYNFIFO_WIDTH : integer;
P_SIMULATION : boolean
);
port (
DDR_wr_sof : in std_logic;
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_sof : in std_logic;
DDR_rdc_eof : in std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : out std_logic;
DDR_Blinker : out std_logic;
mem_clk : in std_logic;
user_clk : in std_logic;
Sim_Zeichen : out std_logic;
user_reset : in std_logic
);
end component;
component DDR_Transact
generic (
SIMULATION : string;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
DDR_UI_DATAWIDTH : integer;
DDR_DQ_WIDTH : integer;
DEVICE_TYPE : string -- "VIRTEX6"
-- "KINTEX7"
-- "ARTIX7"
);
port (
--ext logic interface to memory core
-- memory controller interface --
memc_ui_clk : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_UI_DATAWIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_UI_DATAWIDTH-1 downto 0);
memc_rd_valid : out std_logic;
-- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ext logic interface
-- PCIE interface
DDR_wr_eof : in std_logic;
DDR_wr_v : in std_logic;
DDR_wr_Shift : in std_logic;
DDR_wr_Mask : in std_logic_vector(2-1 downto 0);
DDR_wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : out std_logic;
DDR_rdc_v : in std_logic;
DDR_rdc_Shift : in std_logic;
DDR_rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : out std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : in std_logic;
DDR_FIFO_Empty : out std_logic;
DDR_FIFO_RdQout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--/PCIE interface
-- Common interface
DDR_Ready : out std_logic;
-- DDR core UI
app_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : out std_logic_vector(2 downto 0);
app_en : out std_logic;
app_wdf_data : out std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_wdf_end : out std_logic;
app_wdf_mask : out std_logic_vector((DDR_UI_DATAWIDTH)/8-1 downto 0);
app_wdf_wren : out std_logic;
app_rd_data : in std_logic_vector((DDR_UI_DATAWIDTH)-1 downto 0);
app_rd_data_end : in std_logic;
app_rd_data_valid : in std_logic;
app_rdy : in std_logic;
app_wdf_rdy : in std_logic;
ui_clk : in std_logic;
ui_clk_sync_rst : in std_logic;
init_calib_complete : in std_logic;
--clocking & reset
user_clk : in std_logic;
user_reset : in std_logic
);
end component;
signal DDR_wr_sof : std_logic;
signal DDR_wr_eof : std_logic;
signal DDR_wr_v : std_logic;
signal DDR_wr_Shift : std_logic;
signal DDR_wr_Mask : std_logic_vector(2-1 downto 0);
signal DDR_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full : std_logic;
signal DDR_rdc_sof : std_logic;
signal DDR_rdc_eof : std_logic;
signal DDR_rdc_v : std_logic;
signal DDR_rdc_Shift : std_logic;
signal DDR_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_rdc_full : std_logic;
signal DDR_FIFO_RdEn : std_logic;
signal DDR_FIFO_Empty : std_logic;
signal DDR_FIFO_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Ready : std_logic;
-- -----------------------------------------------------------------------
-- Wishbone interface module
-- -----------------------------------------------------------------------
component wb_transact is
port (
-- PCIE user clk
user_clk : in std_logic;
-- Write port
wr_we : in std_logic;
wr_sof : in std_logic;
wr_eof : in std_logic;
wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full : out std_logic;
-- Read command port
rdc_sof : in std_logic;
rdc_v : in std_logic;
rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full : out std_logic;
rd_tout : in std_logic;
-- Read data port
rd_ren : in std_logic;
rd_empty : out std_logic;
rd_dout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk : in std_logic;
wb_rst : in std_logic;
addr_o : out std_logic_vector(28 downto 0);
dat_i : in std_logic_vector(63 downto 0);
dat_o : out std_logic_vector(63 downto 0);
we_o : out std_logic;
sel_o : out std_logic_vector(0 downto 0);
stb_o : out std_logic;
ack_i : in std_logic;
cyc_o : out std_logic;
--RESET from PCIe
rst : in std_logic
);
end component;
signal wbone_clk : std_logic;
signal wb_wr_we : std_logic;
signal wb_wr_wsof : std_logic;
signal wb_wr_weof : std_logic;
signal wb_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_wr_pfull : std_logic;
signal wb_wr_full : std_logic;
signal wb_rdc_sof : std_logic;
signal wb_rdc_v : std_logic;
signal wb_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdc_full : std_logic;
signal wb_timeout : std_logic;
signal wb_rdd_ren : std_logic;
signal wb_rdd_dout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdd_pempty : std_logic;
signal wb_rdd_empty : std_logic;
signal wbone_rst : std_logic;
signal wb_fifo_rst : std_logic;
signal wbone_addr : std_logic_vector(28 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
------------- COMPONENT Declaration: tlpControl ------
--
component tlpControl
port (
-- Wishbone interface
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_FIFO_full : in std_logic;
wb_FIFO_Rst : out std_logic;
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
wb_timeout : out std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR control interface
DDR_Ready : in std_logic;
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Transaction layer interface
user_lnk_up : in std_logic;
rx_np_ok : out std_logic;
rx_np_req : out std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
s_axis_tx_terrfwd : out std_logic;
user_clk : in std_logic;
user_reset : in std_logic;
m_axis_rx_tvalid : in std_logic;
s_axis_tx_tready : in std_logic;
m_axis_rx_tlast : in std_logic;
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
pcie_link_width : in std_logic_vector(5 downto 0);
localId : in std_logic_vector(15 downto 0);
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(6 downto 0);
s_axis_tx_tvalid : out std_logic;
m_axis_rx_tready : out std_logic;
s_axis_tx_tlast : out std_logic;
s_axis_tx_tkeep : out std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
s_axis_tx_tdata : out std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- TRN Layer signals
signal tx_err_drop : std_logic;
signal tx_cfg_gnt : std_logic;
signal fc_cpld : std_logic_vector (12-1 downto 0);
signal fc_cplh : std_logic_vector (8-1 downto 0);
signal fc_npd : std_logic_vector (12-1 downto 0);
signal fc_nph : std_logic_vector (8-1 downto 0);
signal fc_pd : std_logic_vector (12-1 downto 0);
signal fc_ph : std_logic_vector (8-1 downto 0);
signal fc_sel : std_logic_vector (3-1 downto 0);
signal cfg_dcommand2 : std_logic_vector (16-1 downto 0);
signal tx_cfg_req : std_logic;
signal pl_initial_link_width : std_logic_vector (3-1 downto 0);
signal pl_lane_reversal_mode : std_logic_vector (2-1 downto 0);
signal pl_link_partner_gen2_supported : std_logic;
signal pl_received_hot_rst : std_logic;
signal pl_directed_link_auton : std_logic;
signal pl_directed_link_change : std_logic_vector (2-1 downto 0);
signal pl_directed_link_speed : std_logic;
signal pl_directed_link_width : std_logic_vector (2-1 downto 0);
signal pl_upstream_prefer_deemph : std_logic;
-- Wires used for external clocking connectivity
signal PIPE_PCLK_IN : std_logic := '0';
signal PIPE_RXUSRCLK_IN : std_logic := '0';
signal PIPE_RXOUTCLK_IN : std_logic_vector(3 downto 0) := (others => '0');
signal PIPE_DCLK_IN : std_logic := '0';
signal PIPE_USERCLK1_IN : std_logic := '0';
signal PIPE_USERCLK2_IN : std_logic := '0';
signal PIPE_OOBCLK_IN : std_logic := '0';
signal PIPE_MMCM_LOCK_IN : std_logic := '0';
signal PIPE_TXOUTCLK_OUT : std_logic;
signal PIPE_RXOUTCLK_OUT : std_logic_vector(3 downto 0);
signal PIPE_PCLK_SEL_OUT : std_logic_vector(3 downto 0);
signal PIPE_GEN3_OUT : std_logic;
----------------------------------------------------
signal user_reset_int1 : std_logic;
signal user_lnk_up_int1 : std_logic;
signal user_clk : std_logic;
signal user_reset : std_logic;
signal user_lnk_up : std_logic;
signal s_axis_tx_tdata : std_logic_vector(63 downto 0);
signal s_axis_tx_tkeep : std_logic_vector(7 downto 0);
signal s_axis_tx_tlast : std_logic;
signal s_axis_tx_tvalid : std_logic;
signal s_axis_tx_tready : std_logic;
signal s_axis_tx_tuser : std_logic_vector(3 downto 0);
signal s_axis_tx_tdsc : std_logic;
signal s_axis_tx_terrfwd : std_logic;
signal tx_buf_av : std_logic_vector(5 downto 0);
signal m_axis_rx_tdata : std_logic_vector(63 downto 0);
signal m_axis_rx_tkeep : std_logic_vector(7 downto 0);
signal m_axis_rx_tlast : std_logic;
signal m_axis_rx_tvalid : std_logic;
signal m_axis_rx_tready : std_logic;
signal m_axis_rx_terrfwd : std_logic;
signal m_axis_rx_tuser : std_logic_vector(21 downto 0);
signal rx_np_ok : std_logic;
signal rx_np_req : std_logic;
signal m_axis_rx_tbar_hit : std_logic_vector(6 downto 0);
signal trn_rfc_nph_av : std_logic_vector(7 downto 0);
signal trn_rfc_npd_av : std_logic_vector(11 downto 0);
signal trn_rfc_ph_av : std_logic_vector(7 downto 0);
signal trn_rfc_pd_av : std_logic_vector(11 downto 0);
signal trn_rfc_cplh_av : std_logic_vector(7 downto 0);
signal trn_rfc_cpld_av : std_logic_vector(11 downto 0);
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_mgmt_rd_wr_done : std_logic;
signal cfg_di : std_logic_vector(31 downto 0);
signal cfg_mgmt_byte_en : std_logic_vector(3 downto 0);
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_mgmt_wr_en : std_logic;
signal cfg_mgmt_rd_en : std_logic;
signal cfg_err_cor : std_logic;
signal cfg_err_ur : std_logic;
signal cfg_err_cpl_rdy : std_logic;
signal cfg_err_ecrc : std_logic;
signal cfg_err_cpl_timeout : std_logic;
signal cfg_err_cpl_abort : std_logic;
signal cfg_err_cpl_unexpect : std_logic;
signal cfg_err_posted : std_logic;
signal cfg_err_locked : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_interrupt : std_logic;
signal cfg_interrupt_rdy : std_logic;
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
signal cfg_interrupt_msixenable : std_logic;
signal cfg_interrupt_msixfm : std_logic;
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
signal cfg_interrupt_assert : std_logic;
signal cfg_turnoff_ok : std_logic;
signal cfg_to_turnoff : std_logic;
signal cfg_pm_wake : std_logic;
signal cfg_pcie_link_state : std_logic_vector(2 downto 0);
signal cfg_trn_pending : std_logic;
signal cfg_bus_number : std_logic_vector(7 downto 0);
signal cfg_device_number : std_logic_vector(4 downto 0);
signal cfg_function_number : std_logic_vector(2 downto 0);
signal cfg_dsn : std_logic_vector(63 downto 0);
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
signal sys_reset_c : std_logic;
signal reset_n : std_logic;
signal localId : std_logic_vector(15 downto 0);
signal pcie_link_width : std_logic_vector(5 downto 0);
signal ddr_ref_clk_i : std_logic;
----- DDR core User Interface signals -----------------------
signal app_addr : std_logic_vector(DDR_ADDR_WIDTH-1 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_wdf_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
signal app_wdf_wren : std_logic;
signal app_rd_data : std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rdy : std_logic;
signal app_wdf_rdy : std_logic;
signal ddr_ui_clk : std_logic;
signal ddr_ui_reset : std_logic;
signal ddr_calib_done : std_logic;
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_reset_i : std_logic;
begin
sys_reset_c <= not sys_reset_n_c;
sys_reset_n_ibuf : IBUF
port map (
O => sys_reset_n_c,
I => sys_rst_n
);
pcieclk_ibuf : IBUFDS_GTXE1
port map (
O => sys_clk_c,
ODIV2 => open,
I => sys_clk_p,
IB => sys_clk_n,
CEB => '0'
);
cfg_err_cor <= '0';
cfg_err_ur <= '0';
cfg_err_ecrc <= '0';
cfg_err_cpl_timeout <= '0';
cfg_err_cpl_abort <= '0';
cfg_err_cpl_unexpect <= '0';
cfg_err_posted <= '1';
cfg_err_locked <= '1';
cfg_err_tlp_cpl_header <= (others => '0');
cfg_trn_pending <= '0';
cfg_pm_wake <= '0';
--
fc_sel <= (others => '0');
pl_directed_link_auton <= '0';
pl_directed_link_change <= (others => '0');
pl_directed_link_speed <= '0';
pl_directed_link_width <= (others => '0');
pl_upstream_prefer_deemph <= '0';
tx_cfg_gnt <= '1';
s_axis_tx_tuser <= s_axis_tx_tdsc & '0' & s_axis_tx_terrfwd & '0';
m_axis_rx_terrfwd <= m_axis_rx_tuser(1);
m_axis_rx_tbar_hit <= m_axis_rx_tuser(8 downto 2);
--
cfg_di <= (others => '0');
cfg_dwaddr <= (others => '1');
cfg_mgmt_byte_en <= (others => '0');
cfg_mgmt_wr_en <= '0';
cfg_mgmt_rd_en <= '0';
cfg_dsn <= X"00000001" & X"01" & X"000A35"; -- //this is taken from GUI -
cfg_turnoff_ok <= '1';
localId <= cfg_bus_number & cfg_device_number & cfg_function_number;
pcie_link_width <= cfg_lstatus(9 downto 4);
user_lnk_up_int_i : FDPE
generic map (
INIT => '0'
)
port map (
Q => user_lnk_up,
D => user_lnk_up_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
user_reset_i : FDPE
generic map (
INIT => '1'
)
port map (
Q => user_reset,
D => user_reset_int1,
C => user_clk,
CE => '1',
PRE => '0'
);
-- --------------------------------------------------------------
-- --------------------------------------------------------------
pcie_core_i : pcie_core
generic map(
PL_FAST_TRAIN => PL_FAST_TRAIN
)
port map(
--------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
--------------------------------------------------------------------------------------------------------------------
--TX
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- RX
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
-------------------------------------------------------------------------------------------------------------------
-- 2. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out => user_clk ,
user_reset_out => user_reset_int1,
user_lnk_up => user_lnk_up_int1,
-- TX
tx_buf_av => tx_buf_av ,
tx_cfg_req => tx_cfg_req ,
tx_err_drop => tx_err_drop ,
s_axis_tx_tready => s_axis_tx_tready ,
s_axis_tx_tdata => s_axis_tx_tdata ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
s_axis_tx_tuser => s_axis_tx_tuser,
tx_cfg_gnt => tx_cfg_gnt ,
-- RX
m_axis_rx_tdata => m_axis_rx_tdata ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
m_axis_rx_tuser => m_axis_rx_tuser,
rx_np_ok => rx_np_ok ,
-- Flow Control
fc_cpld => fc_cpld ,
fc_cplh => fc_cplh ,
fc_npd => fc_npd ,
fc_nph => fc_nph ,
fc_pd => fc_pd ,
fc_ph => fc_ph ,
fc_sel => fc_sel ,
-------------------------------------------------------------------------------------------------------------------
-- 3. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
cfg_di => cfg_di,
cfg_byte_en => (others => '0'),
cfg_dwaddr => cfg_dwaddr,
cfg_wr_en => '0',
cfg_rd_en => '0',
cfg_status => cfg_status ,
cfg_command => cfg_command ,
cfg_dstatus => cfg_dstatus ,
cfg_dcommand => cfg_dcommand ,
cfg_lstatus => cfg_lstatus ,
cfg_lcommand => cfg_lcommand ,
cfg_dcommand2 => cfg_dcommand2 ,
cfg_pcie_link_state => cfg_pcie_link_state ,
cfg_pmcsr_pme_en => open ,
cfg_pmcsr_pme_status => open ,
cfg_pmcsr_powerstate => open ,
cfg_err_ecrc => cfg_err_ecrc ,
cfg_err_ur => cfg_err_ur ,
cfg_err_cpl_timeout => cfg_err_cpl_timeout ,
cfg_err_cpl_unexpect => cfg_err_cpl_unexpect ,
cfg_err_cpl_abort => cfg_err_cpl_abort ,
cfg_err_posted => cfg_err_posted ,
cfg_err_cor => cfg_err_cor ,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
cfg_err_cpl_rdy => cfg_err_cpl_rdy ,
cfg_err_locked => cfg_err_locked ,
cfg_trn_pending => cfg_trn_pending ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_assert => cfg_interrupt_assert ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_to_turnoff => cfg_to_turnoff ,
cfg_turnoff_ok => cfg_turnoff_ok ,
cfg_bus_number => cfg_bus_number ,
cfg_device_number => cfg_device_number ,
cfg_function_number => cfg_function_number ,
cfg_pm_wake => cfg_pm_wake ,
-------------------------------------------------------------------------------------------------------------------
-- 5. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_auton => pl_directed_link_auton ,
pl_directed_link_change => pl_directed_link_change ,
pl_directed_link_speed => pl_directed_link_speed ,
pl_directed_link_width => pl_directed_link_width ,
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
pl_ltssm_state => open ,
pl_lane_reversal_mode => pl_lane_reversal_mode ,
cfg_dsn => cfg_dsn ,
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
pl_initial_link_width => pl_initial_link_width ,
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst => pl_received_hot_rst ,
-------------------------------------------------------------------------------------------------------------------
-- 6. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
sys_clk => sys_clk_c ,
sys_reset => sys_reset_c
);
-- ---------------------------------------------------------------
-- tlp control module
-- ---------------------------------------------------------------
theTlpControl :
tlpControl
port map (
-- Wishbone FIFO interface
wb_FIFO_we => wb_wr_we , -- OUT std_logic;
wb_FIFO_wsof => wb_wr_wsof , -- OUT std_logic;
wb_FIFO_weof => wb_wr_weof , -- OUT std_logic;
wb_FIFO_din => wb_wr_din(C_DBUS_WIDTH-1 downto 0) , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_fifo_full => wb_wr_full,
wb_FIFO_re => wb_rdd_ren , -- OUT std_logic;
wb_FIFO_empty => wb_rdd_empty , -- IN std_logic;
wb_FIFO_qout => wb_rdd_dout(C_DBUS_WIDTH-1 downto 0) , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_sof => wb_rdc_sof, --out std_logic;
wb_rdc_v => wb_rdc_v, --out std_logic;
wb_rdc_din => wb_rdc_din, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full => wb_rdc_full, --in std_logic;
wb_timeout => wb_timeout,
wb_FIFO_Rst => wb_fifo_rst , -- OUT std_logic;
-------------------
-- DDR Interface
DDR_Ready => DDR_Ready , -- IN std_logic;
DDR_wr_sof => DDR_wr_sof , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof , -- OUT std_logic;
DDR_wr_v => DDR_wr_v , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- OUT std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-------------------
-- Transaction Interface
user_lnk_up => user_lnk_up ,
rx_np_ok => rx_np_ok ,
rx_np_req => rx_np_req ,
s_axis_tx_tdsc => s_axis_tx_tdsc ,
tx_buf_av => tx_buf_av ,
s_axis_tx_terrfwd => s_axis_tx_terrfwd ,
user_clk => user_clk ,
user_reset => user_reset ,
m_axis_rx_tvalid => m_axis_rx_tvalid ,
s_axis_tx_tready => s_axis_tx_tready ,
m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_terrfwd => m_axis_rx_terrfwd ,
m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tdata => m_axis_rx_tdata ,
cfg_interrupt => cfg_interrupt ,
cfg_interrupt_rdy => cfg_interrupt_rdy ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_assert => cfg_interrupt_assert ,
m_axis_rx_tbar_hit => m_axis_rx_tbar_hit ,
s_axis_tx_tvalid => s_axis_tx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready ,
s_axis_tx_tlast => s_axis_tx_tlast ,
s_axis_tx_tkeep => s_axis_tx_tkeep ,
s_axis_tx_tdata => s_axis_tx_tdata ,
cfg_dcommand => cfg_dcommand ,
pcie_link_width => pcie_link_width ,
localId => localId
);
-- -----------------------------------------------------------------------
-- DDR SDRAM: control module USER LOGIC (2 BRAM Module:
-- -----------------------------------------------------------------------
LoopBack_BRAM_Off : if not USE_LOOPBACK_TEST generate
DDRs_ctrl_module : DDR_Transact
generic map (
SIMULATION => SIMULATION,
DATA_WIDTH => C_DBUS_WIDTH,
ADDR_WIDTH => DDR_ADDR_WIDTH,
DDR_UI_DATAWIDTH => DDR_PAYLOAD_WIDTH,
DDR_DQ_WIDTH => DDR_DQ_WIDTH/2, --!!! Fix for differences between Virtex6 and 7 family devices
DEVICE_TYPE => "VIRTEX6"
)
port map(
memc_ui_clk => memc_ui_clk, --: out std_logic;
memc_cmd_rdy => memc_cmd_rdy, --: out std_logic;
memc_cmd_en => memc_cmd_en, --: in std_logic;
memc_cmd_instr => memc_cmd_instr, --: in std_logic_vector(2 downto 0);
memc_cmd_addr => memc_cmd_addr, --: in std_logic_vector(31 downto 0);
memc_wr_en => memc_wr_en, --: in std_logic;
memc_wr_end => memc_wr_end, --: in std_logic;
memc_wr_mask => memc_wr_mask, --: in std_logic_vector(64/8-1 downto 0);
memc_wr_data => memc_wr_data, --: in std_logic_vector(64-1 downto 0);
memc_wr_rdy => memc_wr_rdy, --: out std_logic;
memc_rd_data => memc_rd_data, --: out std_logic_vector(64-1 downto 0);
memc_rd_valid => memc_rd_valid, --: out std_logic;
memarb_acc_req => memarb_acc_req, --: in std_logic;
memarb_acc_gnt => memarb_acc_gnt, --: out std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready, -- OUT std_logic;
-- DDR core User Interface signals
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
init_calib_complete => ddr_calib_done,
--clocking & reset
user_clk => user_clk , -- IN std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
LoopBack_BRAM_On : if USE_LOOPBACK_TEST generate
DDRs_ctrl_module :
bram_DDRs_Control_loopback
generic map (
C_ASYNFIFO_WIDTH => 72 ,
P_SIMULATION => false
)
port map(
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_sof => DDR_wr_sof , -- IN std_logic;
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- IN std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- IN std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready , -- OUT std_logic;
DDR_Blinker => open , -- OUT std_logic;
mem_clk => user_clk , -- IN
user_clk => user_clk , -- IN std_logic;
Sim_Zeichen => open , -- OUT std_logic;
user_reset => user_reset -- IN std_logic
);
end generate;
Wishbone_intf :
wb_transact
port map(
-- PCIE user clk
user_clk => user_clk, --in std_logic;
-- Write port
wr_we => wb_wr_we, --in std_logic;
wr_sof => wb_wr_wsof, --in std_logic;
wr_eof => wb_wr_weof, --in std_logic;
wr_din => wb_wr_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full => wb_wr_full, --out std_logic;
-- Read command port
rdc_sof => wb_rdc_sof, --in std_logic;
rdc_v => wb_rdc_v, --in std_logic;
rdc_din => wb_rdc_din, --in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full => wb_rdc_full,--out std_logic;
rd_tout => wb_timeout,
-- Read data port
rd_ren => wb_rdd_ren, --in std_logic;
rd_empty => wb_rdd_empty, --out std_logic;
rd_dout => wb_rdd_dout, --out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk => wbone_clk, --in std_logic;
wb_rst => wbone_rst, --in std_logic;
addr_o => wbone_addr(28 downto 0), --out std_logic_vector(31 downto 0);
dat_i => wbone_mdin, --in std_logic_vector(63 downto 0);
dat_o => wbone_mdout, --out std_logic_vector(63 downto 0);
we_o => wbone_we, --out std_logic;
sel_o => wbone_sel, --out std_logic_vector(0 downto 0);
stb_o => wbone_stb, --out std_logic;
ack_i => wbone_ack, --in std_logic;
cyc_o => wbone_cyc, --out std_logic;
--RESET from PCIe
rst => user_reset --in std_logic
);
wbone_clk <= CLK_I;
wbone_rst <= RST_I;
wbone_mdin <= DAT_I;
wbone_ack <= ACK_I;
ADDR_O <= wbone_addr;
DAT_O <= wbone_mdout;
WE_O <= wbone_we;
SEL_O <= wbone_sel(0);
STB_O <= wbone_stb;
CYC_O <= wbone_cyc;
ext_rst_o <= wb_fifo_rst;
u_ddr_core : ddr_v6
generic map (
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
RST_ACT_LOW => 0
)
port map (
-- Memory interface ports
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_cs_n => ddr3_cs_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
phy_init_done => ddr_calib_done,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
scl => open,
sda => open,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
ui_clk => ddr_ui_clk,
ui_clk_sync_rst => ddr_ui_reset,
-- System Clock Ports
sys_clk => ddr_sys_clk_i,
clk_ref => ddr_ref_clk_i,
sys_rst => ddr_sys_reset_i
);
ddr_sys_clk_i <= ddr_sys_clk_p;
ddr_ref_clk_i <= ddr_sys_clk_p;
ddr_sys_reset_i <= ddr_core_rst;
memc_ui_rst <= ddr_ui_reset;
end Behavioral;
|
lgpl-3.0
|
05d35416561d79322298c056d4c379bb
| 0.497039 | 3.496453 | false | false | false | false |
z3774/sparcv8-monocycle
|
MUX_NPC_SRC.vhd
| 1 | 1,014 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_NPC_SRC is
Port (
pc : in STD_LOGIC_VECTOR (31 downto 0);
disp22 : in STD_LOGIC_VECTOR (31 downto 0);
disp30 : in STD_LOGIC_VECTOR (31 downto 0);
alurs : in STD_LOGIC_VECTOR (31 downto 0);
pc_src : in STD_LOGIC_VECTOR (1 downto 0);
pc_out : out STD_LOGIC_VECTOR (31 downto 0)
);
end MUX_NPC_SRC;
architecture Behavioral of MUX_NPC_SRC is
begin
process(pc,disp22,disp30,alurs,pc_src)
begin
case pc_src is
when "00" =>
pc_out <= alurs;
when "01" =>
pc_out <= disp30;
when "10" =>
pc_out <= disp22;
when "11" =>
pc_out <= pc;
when others =>
pc_out <= pc;
end case;
end process;
end Behavioral;
|
gpl-3.0
|
56b9d0029085093792c3941ce6a70f1c
| 0.662722 | 2.913793 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/peripheral/pio.vhd
| 2 | 3,926 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity PIO is
port (
reset_i : in std_logic;
ipl_en_i : in std_logic;
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
has_data_o : out std_logic;
cs_i : in std_logic;
rd_i : in std_logic;
wr_i : in std_logic;
port_a_o : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
port_c_o : out std_logic_vector(7 downto 0)
);
end entity;
architecture Behavior of PIO is
signal porta_r : std_logic_vector(7 downto 0);
signal portc_r : std_logic_vector(7 downto 0);
signal rd_cs_s : std_logic;
signal wr_cs_s : std_logic;
begin
-- Sinais de selecao de escrita e leitura
rd_cs_s <= '1' when cs_i = '1' and rd_i = '1' else '0';
wr_cs_s <= '1' when cs_i = '1' and wr_i = '1' else '0';
-- Portas de saida
process(reset_i, ipl_en_i, wr_cs_s)
variable portc_addr_v : integer range 0 to 7;
begin
if reset_i = '1' then
porta_r <= (others => ipl_en_i);
portc_r <= (7 => '0', others => '1'); -- beep silent
elsif falling_edge(wr_cs_s) then
if addr_i = "00" then
porta_r <= data_i;
elsif addr_i = "10" then
portc_r <= data_i;
elsif addr_i = "11" and data_i(7) = '0' then
portc_addr_v := to_integer(unsigned(data_i(3 downto 1)));
portc_r(portc_addr_v) <= data_i(0);
else
-- Ignora resto
end if;
end if;
end process;
-- Leitura
data_o <= porta_r when rd_cs_s = '1' and addr_i = "00" else
port_b_i when rd_cs_s = '1' and addr_i = "01" else
portc_r when rd_cs_s = '1' and addr_i = "10" else
(others => '0');
has_data_o <= '1' when rd_cs_s = '1' and addr_i /= "11" else '0';
-- I/O
port_a_o <= porta_r;
port_c_o <= portc_r;
end;
|
gpl-3.0
|
ec2924d86439b6981ae0984522505fc1
| 0.627356 | 3.148356 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/DDR_Blinker.vhd
| 1 | 5,938 |
----------------------------------------------------------------------------------
-- Company: ZITI
-- Engineer: wgao
--
-- Create Date: 16:38:03 06 Oct 2008
-- Design Name:
-- Module Name: DDR_Blink - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DDR_Blink is
port (
DDR_blinker : out std_logic;
DDR_Write : in std_logic;
DDR_Read : in std_logic;
DDR_Both : in std_logic;
ddr_Clock : in std_logic;
DDr_Rst_n : in std_logic
);
end entity DDR_Blink;
architecture Behavioral of DDR_Blink is
-- Blinking -_-_-_-_
constant C_BLINKER_MSB : integer := 15; -- 4; -- 15;
constant CBIT_SLOW_BLINKER : integer := 11; -- 2; -- 11;
signal DDR_blinker_i : std_logic;
signal Fast_blinker : std_logic_vector(C_BLINKER_MSB downto 0);
signal Fast_blinker_MSB_r1 : std_logic;
signal Blink_Pulse : std_logic;
signal Slow_blinker : std_logic_vector(CBIT_SLOW_BLINKER downto 0);
signal DDR_write_extension : std_logic;
signal DDR_write_extension_Cnt : std_logic_vector(1 downto 0);
signal DDR_read_extension : std_logic;
signal DDR_read_extension_Cnt : std_logic_vector(1 downto 0);
begin
--
Syn_DDR_Fast_blinker :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
Fast_blinker <= (others => '0');
Fast_blinker_MSB_r1 <= '0';
Blink_Pulse <= '0';
Slow_blinker <= (others => '0');
elsif ddr_Clock'event and ddr_Clock = '1' then
Fast_blinker <= Fast_blinker + '1';
Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB);
Blink_Pulse <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1;
Slow_blinker <= Slow_blinker + Blink_Pulse;
end if;
end process;
--
Syn_DDR_Write_Extenstion :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_write_extension_Cnt <= (others => '0');
DDR_write_extension <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_write_extension_Cnt is
when "00" =>
if DDR_Write = '1' then
DDR_write_extension_Cnt <= "01";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_write_extension_Cnt <= "11";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '0' then
DDR_write_extension_Cnt <= "10";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when others =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_write_extension_Cnt <= "00";
DDR_write_extension <= '0';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Read_Extenstion :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_read_extension_Cnt <= (others => '0');
DDR_read_extension <= '1';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_read_extension_Cnt is
when "00" =>
if DDR_Read = '1' then
DDR_read_extension_Cnt <= "01";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_read_extension_Cnt <= "11";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '0' then
DDR_read_extension_Cnt <= "10";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when others =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_read_extension_Cnt <= "00";
DDR_read_extension <= '1';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Working_blinker :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_Blinker_i <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
DDR_Blinker_i <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension;
-- DDR_Blinker_i <= Slow_blinker(CBIT_SLOW_BLINKER-2);
end if;
end process;
DDR_blinker <= DDR_blinker_i;
end architecture Behavioral;
|
lgpl-3.0
|
3825325ac3527942f03b6d700a1ed991
| 0.54547 | 3.557819 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_cntrl.vhd
| 1 | 16,736 |
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 00:53:40
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/controller/rank_cntrl.v
-- Component name : rank_cntrl
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
library UNISIM;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- use UNISIM.VCOMPONENTS.all;
-- This block is responsible for managing various rank level timing
-- parameters. For now, only Four Activate Window (FAW) and Write
-- To Read delay are implemented here.
--
-- Each rank machine generates its own inhbt_act_faw_r and inhbt_rd_r.
-- These per rank machines are driven into the bank machines. Each
-- bank machines selects the correct inhibits based on the rank
-- of its current request.
entity rank_cntrl is
generic (
TCQ : integer := 100;
BURST_MODE : string := "8";
ID : integer := 0;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
CL : integer := 5;
nFAW : integer := 30;
nREFRESH_BANK : integer := 8;
nRRD : integer := 4;
nWTR : integer := 4;
PERIODIC_RD_TIMER_DIV : integer := 20;
RANK_BM_BV_WIDTH : integer := 16;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
PHASE_DETECT : string := "OFF"; --Added to control periodic reads
REFRESH_TIMER_DIV : integer := 39
);
port (
-- Outputs
-- Inputs
-- ceiling logb2
inhbt_act_faw_r : out std_logic;
inhbt_rd_r : out std_logic;
wtr_inhbt_config_r : out std_logic;
refresh_request : out std_logic;
periodic_rd_request : out std_logic;
clk : in std_logic;
rst : in std_logic;
sending_row : in std_logic_vector(nBANK_MACHS - 1 downto 0);
act_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
sending_col : in std_logic_vector(nBANK_MACHS - 1 downto 0);
wr_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
app_ref_req : in std_logic;
dfi_init_complete : in std_logic;
rank_busy_r : in std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
refresh_tick : in std_logic;
insert_maint_r1 : in std_logic;
maint_zq_r : in std_logic;
maint_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
app_periodic_rd_req : in std_logic;
maint_prescaler_tick_r : in std_logic;
clear_periodic_rd_request : in std_logic;
rd_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0)
);
end entity rank_cntrl;
architecture trans of rank_cntrl is
component SRLC32E
generic (
INIT : bit_vector := X"00000000"
);
port (
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
function REDUCTION_NOR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return not tmp;
end function REDUCTION_NOR;
function f_ADD_RRD (nCK_PER_CLK: integer; nRRD : integer )
return integer is
begin
if (nCK_PER_CLK = 1) then
return (nRRD - 2);
else
return ( nRRD - 4);
end if ;
end function f_ADD_RRD;
function f_RRD_CLKS(nCK_PER_CLK: integer; nADD_RRD : integer )
return integer is
begin
if (nCK_PER_CLK = 1) then
return (nADD_RRD);
else
return (nADD_RRD/2 + (nADD_RRD mod 2));
end if ;
end function f_RRD_CLKS;
function f_FAW_CLKS(nCK_PER_CLK: integer; nFAW : integer )
return integer is
begin
if (nCK_PER_CLK = 1) then
return (nFAW);
else
return (nFAW/2 + (nFAW mod 2));
end if ;
end function f_FAW_CLKS;
function clogb2(size: integer) return integer is
variable tmp : integer range 0 to 24;
begin
tmp := 0;
for i in 23 downto 0 loop
if( size <= 2** i) then
tmp := i;
end if;
end loop;
return tmp;
end function clogb2;
function f_CASWR2CASRD (nWTR: integer; CL : integer ;BURST_MODE : string)
return integer is
begin
if (BURST_MODE = "4") then
return ( 2 + nWTR + CL );
else
return (4 + nWTR + CL);
end if;
end function f_CASWR2CASRD;
function f_CASWR2CASRD_CLKS(nCK_PER_CLK: integer; CASWR2CASRD : integer )
return integer is
begin
if (nCK_PER_CLK = 1) then
return (CASWR2CASRD);
else
return (CASWR2CASRD/2 + (CASWR2CASRD mod 2));
end if ;
end function f_CASWR2CASRD_CLKS;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
function CALC_RANK_BUSY (my_rank_busy: std_logic; rank_busy_r : std_logic_vector)
return std_logic is
variable tmp : std_logic;
begin
tmp := my_rank_busy;
for i in 0 to nBANK_MACHS - 1 loop
tmp := tmp or rank_busy_r((i * RANKS) + ID);
end loop;
return tmp;
end function CALC_RANK_BUSY;
constant nADD_RRD : integer := f_ADD_RRD(nCK_PER_CLK, nRRD);
constant nRRD_CLKS : integer := f_RRD_CLKS(nCK_PER_CLK,nADD_RRD);
constant ADD_RRD_CNTR_WIDTH : integer := clogb2(nRRD_CLKS + 1);
constant nFAW_CLKS : integer := f_FAW_CLKS(nCK_PER_CLK ,nFAW);
constant ONE : integer := 1;
constant CASWR2CASRD : integer := f_CASWR2CASRD(nWTR,CL,BURST_MODE );
constant CASWR2CASRD_CLKS : integer := f_CASWR2CASRD_CLKS(nCK_PER_CLK,CASWR2CASRD);
constant WTR_CNT_WIDTH : integer := clogb2(CASWR2CASRD_CLKS - 1);
constant TWO : integer := 2;
constant REFRESH_BANK_WIDTH : integer := clogb2(nREFRESH_BANK + 1);
constant PERIODIC_RD_TIMER_WIDTH : integer := clogb2(PERIODIC_RD_TIMER_DIV + 1);
signal act_this_rank : std_logic;
signal i : integer;
signal add_rrd_inhbt : std_logic := '0';
signal faw_cnt_ns,faw_cnt_r : std_logic_vector(2 downto 0);
signal periodic_rd_timer_r : std_logic_vector(PERIODIC_RD_TIMER_WIDTH-1 downto 0);
signal periodic_rd_timer_ns : std_logic_vector(PERIODIC_RD_TIMER_WIDTH-1 downto 0);
signal periodic_rd_request_ns : std_logic;
signal periodic_rd_request_r : std_logic;
signal add_rrd_r : std_logic_vector(ADD_RRD_CNTR_WIDTH-1 downto 0);
signal add_rrd_ns : std_logic_vector(ADD_RRD_CNTR_WIDTH-1 downto 0);
signal shift_depth : std_logic_vector(4 downto 0);
signal act_delayed : std_logic;
signal inhbt_act_faw_ns : std_logic;
signal write_this_rank : std_logic;
signal wtr_cnt_r : std_logic_vector(WTR_CNT_WIDTH-1 downto 0);
signal wtr_cnt_ns : std_logic_vector(WTR_CNT_WIDTH-1 downto 0);
signal inhbt_rd_ns : std_logic;
signal wtr_inhbt_config_ns : std_logic;
signal read_this_rank : std_logic;
signal read_this_rank_tmp : std_logic;
signal my_rank_busy : std_logic;
signal refresh_bank_r : std_logic_vector(REFRESH_BANK_WIDTH-1 downto 0);
signal refresh_bank_ns : std_logic_vector(REFRESH_BANK_WIDTH-1 downto 0);
signal my_refresh : std_logic;
signal periodic_rd_timer_one : std_logic;
signal int1 : std_logic_vector(2 downto 0);
begin
process (act_this_rank_r, sending_row)
variable act_this_rank_tmp : std_logic;
begin
act_this_rank_tmp := '0';
for i in 0 to nBANK_MACHS - 1 loop
act_this_rank_tmp := act_this_rank_tmp or (sending_row(i) and act_this_rank_r((i * RANKS) + ID));
end loop;
act_this_rank <= act_this_rank_tmp;
end process;
int0 : if (nADD_RRD > 0) generate
process (act_this_rank, add_rrd_r, rst)
begin
add_rrd_ns <= add_rrd_r;
if (rst = '1') then
add_rrd_ns <= (others => '0');
elsif (act_this_rank = '1') then
add_rrd_ns <= conv_std_logic_vector(nRRD_CLKS, ADD_RRD_CNTR_WIDTH);
elsif ((REDUCTION_OR(add_rrd_r)) = '1') then
add_rrd_ns <= add_rrd_r - '1';
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
add_rrd_r <= add_rrd_ns after (TCQ)*1 ps;
end if;
end process;
process (add_rrd_ns)
begin
add_rrd_inhbt <= REDUCTION_OR(add_rrd_ns);
end process;
end generate;
shift_depth <= conv_std_logic_vector(nFAW_CLKS, 5) - "00011";
SRLC32E0 : SRLC32E
generic map (
init => "00000000000000000000000000000000"
)
port map (
q => act_delayed,
q31 => open,
a => shift_depth,
ce => '1',
clk => clk,
d => act_this_rank
);
process (act_delayed, act_this_rank, add_rrd_inhbt, faw_cnt_r, rst)
variable faw_cnt_ns_tmp : std_logic_vector(2 downto 0);
begin
if (rst = '1') then
faw_cnt_ns_tmp := "000";
else
faw_cnt_ns_tmp := faw_cnt_r;
if (act_this_rank = '1') then
faw_cnt_ns_tmp := faw_cnt_r + "001";
end if;
if (act_delayed = '1') then
faw_cnt_ns_tmp := faw_cnt_ns_tmp - "001";
end if;
end if;
faw_cnt_ns <= faw_cnt_ns_tmp;
inhbt_act_faw_ns <= BOOLEAN_TO_STD_LOGIC(faw_cnt_ns_tmp = "100") or add_rrd_inhbt;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
faw_cnt_r <= faw_cnt_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
inhbt_act_faw_r <= inhbt_act_faw_ns after (TCQ)*1 ps;
end if;
end process;
process (sending_col, wr_this_rank_r)
variable write_this_rank_tmp : std_logic;
begin
write_this_rank_tmp := '0';
for i in 0 to nBANK_MACHS - 1 loop
write_this_rank_tmp := write_this_rank_tmp or (sending_col(i) and wr_this_rank_r((i * RANKS) + ID));
end loop;
write_this_rank <= write_this_rank_tmp;
end process;
process (rst, write_this_rank, wtr_cnt_r)
variable wtr_cnt_ns_tmp : std_logic_vector(WTR_CNT_WIDTH-1 downto 0);
begin
if (rst = '1') then
wtr_cnt_ns_tmp := (others => '0');
else
wtr_cnt_ns_tmp := wtr_cnt_r;
if (write_this_rank = '1') then
wtr_cnt_ns_tmp := conv_std_logic_vector(CASWR2CASRD_CLKS, WTR_CNT_WIDTH) - conv_std_logic_vector(2,WTR_CNT_WIDTH);
elsif ((REDUCTION_OR(wtr_cnt_r)) = '1') then
wtr_cnt_ns_tmp := wtr_cnt_r - conv_std_logic_vector(1, WTR_CNT_WIDTH);
end if;
end if;
wtr_cnt_ns <= wtr_cnt_ns_tmp;
end process;
inhbt_rd_ns <= REDUCTION_OR(wtr_cnt_ns);
wtr_inhbt_config_ns <= BOOLEAN_TO_STD_LOGIC(wtr_cnt_ns >= conv_std_logic_vector(2,WTR_CNT_WIDTH));
process (clk)
begin
if (clk'event and clk = '1') then
wtr_cnt_r <= wtr_cnt_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
inhbt_rd_r <= inhbt_rd_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
wtr_inhbt_config_r <= wtr_inhbt_config_ns after (TCQ)*1 ps;
end if;
end process;
process (rank_busy_r)
begin
my_rank_busy <= CALC_RANK_BUSY('0',rank_busy_r);
--my_rank_busy <= '0';
--for i in 0 to nBANK_MACHS - 1 loop
-- my_rank_busy <= my_rank_busy or rank_busy_r((i * RANKS) + ID);
--end loop;
end process;
my_refresh <= insert_maint_r1 and not(maint_zq_r) and BOOLEAN_TO_STD_LOGIC(maint_rank_r = conv_std_logic_vector(ID,RANK_WIDTH));
int1 <= my_refresh & refresh_tick & app_ref_req;
process (app_ref_req, dfi_init_complete, my_refresh, refresh_bank_r, refresh_tick,int1)
begin
if ((not(dfi_init_complete)) = '1') then
if (REFRESH_TIMER_DIV = 0) then
refresh_bank_ns <= conv_std_logic_vector(nREFRESH_BANK, REFRESH_BANK_WIDTH);
else
refresh_bank_ns <= ( others => '0' );
end if;
else
case int1 is
when "000" | "110" | "101" | "111" =>
refresh_bank_ns <= refresh_bank_r;
when "010" | "001" | "011" =>
if ( REDUCTION_OR(refresh_bank_r) = '1' ) then
refresh_bank_ns <= refresh_bank_r - '1';
else
refresh_bank_ns <= refresh_bank_r;
end if;
when "100" =>
refresh_bank_ns <= refresh_bank_r + '1';
when others =>
null;
end case;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
refresh_bank_r <= refresh_bank_ns after (TCQ)*1 ps;
end if;
end process;
refresh_request <= dfi_init_complete and
(REDUCTION_NOR(refresh_bank_r) or
(BOOLEAN_TO_STD_LOGIC(refresh_bank_r /= conv_std_logic_vector(nREFRESH_BANK, REFRESH_BANK_WIDTH)) and not(my_rank_busy)));
enable_periodic_reads : if ( not(PHASE_DETECT = "OFF") ) generate
process (rd_this_rank_r, sending_col)
variable read_this_rank_tmp : std_logic;
begin
read_this_rank_tmp := '0';
for i in 0 to nBANK_MACHS - 1 loop
read_this_rank_tmp := read_this_rank_tmp or (sending_col(i) and rd_this_rank_r((i * RANKS) + ID));
end loop;
read_this_rank <= read_this_rank_tmp;
end process;
process (dfi_init_complete, maint_prescaler_tick_r, periodic_rd_timer_r, read_this_rank)
begin
periodic_rd_timer_ns <= periodic_rd_timer_r;
if ((not(dfi_init_complete)) = '1') then
periodic_rd_timer_ns <= (others => '0' );
elsif (read_this_rank = '1') then
periodic_rd_timer_ns <= conv_std_logic_vector(PERIODIC_RD_TIMER_DIV, PERIODIC_RD_TIMER_WIDTH);
elsif ((REDUCTION_OR(periodic_rd_timer_r) and maint_prescaler_tick_r) = '1') then
periodic_rd_timer_ns <= periodic_rd_timer_r - '1';
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
periodic_rd_timer_r <= periodic_rd_timer_ns after (TCQ)*1 ps;
end if;
end process;
periodic_rd_timer_one <= maint_prescaler_tick_r and BOOLEAN_TO_STD_LOGIC((periodic_rd_timer_r = conv_std_logic_vector(1,PERIODIC_RD_TIMER_WIDTH)));
periodic_rd_request_ns <= not(rst) and
((app_periodic_rd_req and dfi_init_complete) or
(BOOLEAN_TO_STD_LOGIC(PERIODIC_RD_TIMER_DIV /= 0) and not(dfi_init_complete)) or
(not(read_this_rank or clear_periodic_rd_request) and
(periodic_rd_request_r or periodic_rd_timer_one)));
process (clk)
begin
if (clk'event and clk = '1') then
periodic_rd_request_r <= periodic_rd_request_ns after (TCQ)*1 ps;
end if;
end process;
periodic_rd_request <= dfi_init_complete and periodic_rd_request_r;
end generate;
disable_periodic_reads : if ( PHASE_DETECT = "OFF" ) generate
periodic_rd_request <= '0';
end generate;
end architecture trans;
|
lgpl-3.0
|
c2103329148d9c352367a49eb0a20e61
| 0.548697 | 3.410638 | false | false | false | false |
VectorBlox/risc-v
|
ip/orca/hdl/axi_master.vhd
| 1 | 10,331 |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.utils.all;
use work.rv_components.all;
use work.constants_pkg.all;
-------------------------------------------------------------------------------
-- AXI master from OIMM master.
-------------------------------------------------------------------------------
entity axi_master is
generic (
ADDRESS_WIDTH : positive;
DATA_WIDTH : positive;
ID_WIDTH : positive;
LOG2_BURSTLENGTH : positive;
MAX_OUTSTANDING_REQUESTS : natural;
REQUEST_REGISTER : request_register_type;
RETURN_REGISTER : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
aresetn : in std_logic;
master_idle : out std_logic;
--ORCA-internal memory-mapped slave
oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
oimm_burstlength_minus1 : in std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
oimm_byteenable : in std_logic_vector((DATA_WIDTH/8)-1 downto 0);
oimm_requestvalid : in std_logic;
oimm_readnotwrite : in std_logic;
oimm_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_writelast : in std_logic;
oimm_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_readdatavalid : out std_logic;
oimm_waitrequest : out std_logic;
--AXI memory-mapped master
AWID : out std_logic_vector(ID_WIDTH-1 downto 0);
AWADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
AWLEN : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
AWSIZE : out std_logic_vector(2 downto 0);
AWBURST : out std_logic_vector(1 downto 0);
AWLOCK : out std_logic_vector(1 downto 0);
AWCACHE : out std_logic_vector(3 downto 0);
AWPROT : out std_logic_vector(2 downto 0);
AWVALID : out std_logic;
AWREADY : in std_logic;
WID : out std_logic_vector(ID_WIDTH-1 downto 0);
WSTRB : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
WVALID : out std_logic;
WLAST : out std_logic;
WDATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
WREADY : in std_logic;
BID : in std_logic_vector(ID_WIDTH-1 downto 0);
BRESP : in std_logic_vector(1 downto 0);
BVALID : in std_logic;
BREADY : out std_logic;
ARID : out std_logic_vector(ID_WIDTH-1 downto 0);
ARADDR : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
ARLEN : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
ARSIZE : out std_logic_vector(2 downto 0);
ARBURST : out std_logic_vector(1 downto 0);
ARLOCK : out std_logic_vector(1 downto 0);
ARCACHE : out std_logic_vector(3 downto 0);
ARPROT : out std_logic_vector(2 downto 0);
ARVALID : out std_logic;
ARREADY : in std_logic;
RID : in std_logic_vector(ID_WIDTH-1 downto 0);
RDATA : in std_logic_vector(DATA_WIDTH-1 downto 0);
RRESP : in std_logic_vector(1 downto 0);
RLAST : in std_logic;
RVALID : in std_logic;
RREADY : out std_logic
);
end entity axi_master;
architecture rtl of axi_master is
constant BURST_INCR : std_logic_vector(1 downto 0) := "01";
constant CACHE_VAL : std_logic_vector(3 downto 0) := "0011";
constant PROT_VAL : std_logic_vector(2 downto 0) := "000";
constant LOCK_VAL : std_logic_vector(1 downto 0) := "00";
signal register_idle : std_logic;
signal throttler_idle : std_logic;
signal registered_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal registered_oimm_burstlength_minus1 : std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
signal registered_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal registered_oimm_requestvalid : std_logic;
signal registered_oimm_readnotwrite : std_logic;
signal registered_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal registered_oimm_writelast : std_logic;
signal unregistered_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal unregistered_oimm_readdatavalid : std_logic;
signal unregistered_oimm_waitrequest : std_logic;
signal unthrottled_oimm_readcomplete : std_logic;
signal unthrottled_oimm_writecomplete : std_logic;
signal unthrottled_oimm_waitrequest : std_logic;
signal throttled_oimm_requestvalid : std_logic;
signal AWVALID_signal : std_logic;
signal WVALID_signal : std_logic;
signal aw_sending : std_logic;
signal aw_sent : std_logic;
signal w_sending : std_logic;
signal w_sent : std_logic;
begin
master_idle <= register_idle and throttler_idle;
-----------------------------------------------------------------------------
-- Optional OIMM register
-----------------------------------------------------------------------------
optional_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
LOG2_BURSTLENGTH => LOG2_BURSTLENGTH,
REQUEST_REGISTER => REQUEST_REGISTER,
RETURN_REGISTER => RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => oimm_address,
slave_oimm_burstlength_minus1 => oimm_burstlength_minus1,
slave_oimm_byteenable => oimm_byteenable,
slave_oimm_requestvalid => oimm_requestvalid,
slave_oimm_readnotwrite => oimm_readnotwrite,
slave_oimm_writedata => oimm_writedata,
slave_oimm_writelast => oimm_writelast,
slave_oimm_readdata => oimm_readdata,
slave_oimm_readdatavalid => oimm_readdatavalid,
slave_oimm_waitrequest => oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => registered_oimm_address,
master_oimm_burstlength_minus1 => registered_oimm_burstlength_minus1,
master_oimm_byteenable => registered_oimm_byteenable,
master_oimm_requestvalid => registered_oimm_requestvalid,
master_oimm_readnotwrite => registered_oimm_readnotwrite,
master_oimm_writedata => registered_oimm_writedata,
master_oimm_writelast => registered_oimm_writelast,
master_oimm_readdata => unregistered_oimm_readdata,
master_oimm_readdatavalid => unregistered_oimm_readdatavalid,
master_oimm_waitrequest => unregistered_oimm_waitrequest
);
-----------------------------------------------------------------------------
-- Optional OIMM request throttler
-----------------------------------------------------------------------------
request_throttler : oimm_throttler
generic map (
MAX_OUTSTANDING_REQUESTS => MAX_OUTSTANDING_REQUESTS,
READ_WRITE_FENCE => true --AXI lacks intra-channel ordering
)
port map (
clk => clk,
reset => reset,
throttler_idle => throttler_idle,
--ORCA-internal memory-mapped slave
slave_oimm_requestvalid => registered_oimm_requestvalid,
slave_oimm_readnotwrite => registered_oimm_readnotwrite,
slave_oimm_writelast => registered_oimm_writelast,
slave_oimm_waitrequest => unregistered_oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_requestvalid => throttled_oimm_requestvalid,
master_oimm_readcomplete => unthrottled_oimm_readcomplete,
master_oimm_writecomplete => unthrottled_oimm_writecomplete,
master_oimm_waitrequest => unthrottled_oimm_waitrequest
);
-----------------------------------------------------------------------------
-- OIMM to AXI logic
-----------------------------------------------------------------------------
unthrottled_oimm_readcomplete <= RVALID and RLAST;
unthrottled_oimm_writecomplete <= BVALID;
unregistered_oimm_readdata <= RDATA;
unregistered_oimm_readdatavalid <= RVALID;
unthrottled_oimm_waitrequest <= (not ARREADY) when registered_oimm_readnotwrite = '1' else
(((not AWREADY) and (not aw_sent) and (registered_oimm_writelast or w_sent)) or
((not WREADY) and (not w_sent)));
AWID <= (others => '0');
AWADDR <= registered_oimm_address;
AWLEN <= registered_oimm_burstlength_minus1;
AWSIZE <= std_logic_vector(to_unsigned(log2(DATA_WIDTH/8), 3));
AWBURST <= BURST_INCR;
AWLOCK <= LOCK_VAL;
AWCACHE <= CACHE_VAL;
AWPROT <= PROT_VAL;
AWVALID_signal <= (throttled_oimm_requestvalid and (not registered_oimm_readnotwrite)) and (not aw_sent);
AWVALID <= AWVALID_signal;
WID <= (others => '0');
WSTRB <= registered_oimm_byteenable;
WVALID_signal <= (throttled_oimm_requestvalid and (not registered_oimm_readnotwrite)) and (not w_sent);
WVALID <= WVALID_signal;
WLAST <= registered_oimm_writelast;
WDATA <= registered_oimm_writedata;
BREADY <= '1';
ARID <= (others => '0');
ARADDR <= registered_oimm_address;
ARLEN <= registered_oimm_burstlength_minus1;
ARSIZE <= std_logic_vector(to_unsigned(log2(DATA_WIDTH/8), 3));
ARBURST <= BURST_INCR;
ARLOCK <= LOCK_VAL;
ARCACHE <= CACHE_VAL;
ARPROT <= PROT_VAL;
ARVALID <= registered_oimm_readnotwrite and throttled_oimm_requestvalid;
RREADY <= '1';
aw_sending <= AWVALID_signal and AWREADY;
w_sending <= WVALID_signal and registered_oimm_writelast and WREADY;
process (clk) is
begin
if rising_edge(clk) then
if aw_sending = '1' then
if w_sent = '1' or w_sending = '1' then
aw_sent <= '0';
w_sent <= '0';
else
aw_sent <= '1';
end if;
end if;
if w_sending = '1' then
if aw_sent = '1' or aw_sending = '1' then
w_sent <= '0';
aw_sent <= '0';
else
w_sent <= '1';
end if;
end if;
if aresetn = '0' then
aw_sent <= '0';
w_sent <= '0';
end if;
end if;
end process;
end architecture;
|
bsd-3-clause
|
15cde96bde6f0790b9d5a8f24b129508
| 0.589294 | 4.037124 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/peripheral/exp_slot.vhd
| 2 | 3,703 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.and_reduce;
entity exp_slot is
port(
reset_i : in std_logic;
ipl_en_i : in std_logic;
addr_i : in std_logic_vector(15 downto 0);
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
has_data_o : out std_logic;
sltsl_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
expsltsl_n_o : out std_logic_vector(3 downto 0)
);
end entity;
architecture rtl of exp_slot is
signal ffff_s : std_logic;
signal exp_reg_s : std_logic_vector(7 downto 0);
signal exp_sel_s : std_logic_vector(1 downto 0);
signal exp_wr_s : std_logic;
signal exp_rd_s : std_logic;
begin
--
ffff_s <= and_reduce(addr_i);
exp_wr_s <= not (sltsl_n_i or wr_n_i or not ffff_s);
exp_rd_s <= not (sltsl_n_i or rd_n_i or not ffff_s);
process(reset_i, ipl_en_i, exp_wr_s)
begin
if reset_i = '1' then
if ipl_en_i = '1' then
exp_reg_s <= X"FF";
else
exp_reg_s <= X"00";
end if;
elsif falling_edge(exp_wr_s) then
exp_reg_s <= data_i;
end if;
end process;
-- Read
has_data_o <= exp_rd_s;
data_o <= (not exp_reg_s) when exp_rd_s = '1' else
(others => '1');
-- subslot mux
with addr_i(15 downto 14) select exp_sel_s <=
exp_reg_s(1 downto 0) when "00",
exp_reg_s(3 downto 2) when "01",
exp_reg_s(5 downto 4) when "10",
exp_reg_s(7 downto 6) when others;
-- Demux 2-to-4
expsltsl_n_o <= "1111" when ffff_s = '1' or sltsl_n_i = '1' else
"1110" when sltsl_n_i = '0' and exp_sel_s = "00" else
"1101" when sltsl_n_i = '0' and exp_sel_s = "01" else
"1011" when sltsl_n_i = '0' and exp_sel_s = "10" else
"0111";
end architecture;
|
gpl-3.0
|
0126ac21f1a0cbaaa07954cf5c73c0c0
| 0.655685 | 3.164957 | false | false | false | false |
z3774/sparcv8-monocycle
|
MUX.vhd
| 1 | 827 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX is
Port (
crs2 : in STD_LOGIC_VECTOR (31 downto 0);
immSE : in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
ope2 : out STD_LOGIC_VECTOR (31 downto 0)
);
end MUX;
architecture Behavioral of MUX is
begin
process (crs2, immSE, i)
begin
case i is
when '0' => ope2 <= crs2;
when '1' => ope2 <= immSE;
when others => ope2 <= (others =>'0');
end case;
end process;
end Behavioral;
|
gpl-3.0
|
8835ffb47b0465098fe34eb9ae8afdda
| 0.634825 | 3.361789 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-de2/de2_top.vhd
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-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
--
-- Terasic DE2 top-level
--
-- altera message_off 10540 10541
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.msx_pack.all;
-- Generic top-level entity for Altera DE2 board
entity de2_top is
generic (
per_opll_g : boolean := true;
per_jt51_g : boolean := true
);
port (
-- Clocks
clk50_i : in std_logic;
clk27_i : in std_logic;
clk_ext_i : in std_logic;
-- Switches
sw_i : in std_logic_vector(17 downto 0);
-- Buttons
key_n_i : in std_logic_vector( 3 downto 0);
-- 7 segment displays
display0_o : out std_logic_vector( 6 downto 0) := (others => '1');
display1_o : out std_logic_vector( 6 downto 0) := (others => '1');
display2_o : out std_logic_vector( 6 downto 0) := (others => '1');
display3_o : out std_logic_vector( 6 downto 0) := (others => '1');
display4_o : out std_logic_vector( 6 downto 0) := (others => '1');
display5_o : out std_logic_vector( 6 downto 0) := (others => '1');
display6_o : out std_logic_vector( 6 downto 0) := (others => '1');
display7_o : out std_logic_vector( 6 downto 0) := (others => '1');
-- Red LEDs
ledr_o : out std_logic_vector(17 downto 0) := (others => '0');
-- Green LEDs
ledg_o : out std_logic_vector( 8 downto 0) := (others => '0');
-- Serial
uart_rx_i : in std_logic;
uart_tx_o : out std_logic := '1';
-- IRDA
irda_rx_i : in std_logic;
irda_tx_o : out std_logic := '0';
-- SRAM
sram_addr_o : out std_logic_vector(17 downto 0) := (others => '0');
sram_data_io : inout std_logic_vector(15 downto 0) := (others => '0');
sram_ce_n_o : out std_logic := '1';
sram_oe_n_o : out std_logic := '1';
sram_we_n_o : out std_logic := '1';
sram_ub_n_o : out std_logic := '1';
sram_lb_n_o : out std_logic := '1';
-- SDRAM
dram_cke_o : out std_logic := '1';
dram_clk_o : out std_logic := '1';
dram_addr_o : out std_logic_vector(11 downto 0) := (others => '0');
dram_data_io : inout std_logic_vector(15 downto 0) := (others => '0');
dram_cas_n_o : out std_logic := '1';
dram_ras_n_o : out std_logic := '1';
dram_cs_n_o : out std_logic := '1';
dram_we_n_o : out std_logic := '1';
dram_ba_o : out std_logic_vector( 1 downto 0) := "11";
dram_ldqm_o : out std_logic := '1';
dram_udqm_o : out std_logic := '1';
-- Flash
fl_rst_n_o : out std_logic := '1';
fl_addr_o : out std_logic_vector(21 downto 0) := (others => '0');
fl_data_io : inout std_logic_vector( 7 downto 0) := (others => 'Z');
fl_ce_n_o : out std_logic := '1';
fl_oe_n_o : out std_logic := '1';
fl_we_n_o : out std_logic := '1';
-- ISP1362 Interface
otg_addr_o : out std_logic_vector( 1 downto 0) := (others => '0');
otg_data_io : inout std_logic_vector(15 downto 0) := (others => 'Z');
otg_cs_n_o : out std_logic := '1';
otg_rd_n_o : out std_logic := '1';
otg_wr_n_o : out std_logic := '1';
otg_rst_n_o : out std_logic := '1';
otg_fspeed_o : out std_logic := 'Z';
otg_lspeed_o : out std_logic := 'Z';
otg_int0_i : in std_logic;
otg_int1_i : in std_logic;
otg_dreq0_i : in std_logic;
otg_dreq1_i : in std_logic;
otg_dack0_n_o : out std_logic := '1';
otg_dack1_n_o : out std_logic := '1';
-- LCD Module 16X2
lcd_on_o : out std_logic := '0';
lcd_blon_o : out std_logic := '0';
lcd_data_io : inout std_logic_vector(7 downto 0) := (others => '0');
lcd_rw_o : out std_logic := '1'; -- 0=Write
lcd_en_o : out std_logic := '1';
lcd_rs_o : out std_logic := '1'; -- 0=Command
-- SD card (SPI mode)
sd_miso_i : in std_logic;
sd_mosi_o : out std_logic := '1';
sd_cs_n_o : out std_logic := '1';
sd_sclk_o : out std_logic := '1';
-- I2C
i2c_sclk_io : inout std_logic := '1';
i2c_sdat_io : inout std_logic := '1';
-- PS/2 Keyboard
ps2_clk_io : inout std_logic := '1';
ps2_dat_io : inout std_logic := '1';
-- VGA
vga_clk_o : out std_logic := '0';
vga_r_o : out std_logic_vector( 9 downto 0) := (others => '0');
vga_g_o : out std_logic_vector( 9 downto 0) := (others => '0');
vga_b_o : out std_logic_vector( 9 downto 0) := (others => '0');
vga_hsync_n_o : out std_logic := '1';
vga_vsync_n_o : out std_logic := '1';
vga_blank_n_o : out std_logic := '1';
vga_sync_o : out std_logic := '0';
-- Ethernet Interface
enet_clk_o : out std_logic := '0';
enet_data_io : inout std_logic_vector(15 downto 0) := (others => 'Z');
enet_cmd_o : out std_logic := '0'; -- 0=Command
enet_cs_n_o : out std_logic := '1';
enet_wr_n_o : out std_logic := '1';
enet_rd_n_o : out std_logic := '1';
enet_rst_n_o : out std_logic := '1';
enet_int_i : in std_logic;
-- Audio
aud_xck_o : out std_logic := '0';
aud_bclk_o : out std_logic := '0';
aud_adclrck_o : out std_logic := '0';
aud_adcdat_i : in std_logic;
aud_daclrck_o : out std_logic := '0';
aud_dacdat_o : out std_logic := '0';
-- TV Decoder
td_data_i : in std_logic_vector(7 downto 0);
td_hsync_n_i : in std_logic;
td_vsync_n_i : in std_logic;
td_reset_n_o : out std_logic := '1';
-- GPIO
gpio0_io : inout std_logic_vector(35 downto 0) := (others => 'Z');
gpio1_io : inout std_logic_vector(35 downto 0) := (others => 'Z')
);
end entity;
architecture behavior of de2_top is
-- Resets
signal pll_locked_s : std_logic;
signal por_s : std_logic;
signal reset_s : std_logic;
signal soft_por_s : std_logic;
signal soft_reset_k_s : std_logic;
signal soft_reset_s_s : std_logic;
signal soft_rst_cnt_s : unsigned(7 downto 0) := X"FF";
-- Clocks
signal clock_master_s : std_logic;
signal clock_sdram_s : std_logic;
signal clock_audio_s : std_logic;
signal clock_vdp_s : std_logic;
signal clock_cpu_s : std_logic;
signal clock_psg_en_s : std_logic;
signal clock_3m_s : std_logic;
signal clock_16m_s : std_logic;
signal clock_8m_s : std_logic;
signal turbo_on_s : std_logic;
-- RAM
signal ram_addr_s : std_logic_vector(22 downto 0); -- 8MB
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_ce_s : std_logic;
signal ram_oe_s : std_logic;
signal ram_we_s : std_logic;
-- VRAM memory
signal vram_addr_s : std_logic_vector(13 downto 0); -- 16K
signal vram_data_from_s : std_logic_vector( 7 downto 0);
signal vram_data_to_s : std_logic_vector( 7 downto 0);
signal vram_ce_s : std_logic;
signal vram_oe_s : std_logic;
signal vram_we_s : std_logic;
-- Audio
signal audio_scc_s : signed(14 downto 0);
signal audio_psg_s : unsigned(7 downto 0);
signal beep_s : std_logic;
signal ear_s : std_logic;
signal audio_l_s : signed(15 downto 0);
signal audio_r_s : signed(15 downto 0);
signal volumes_s : volumes_t;
-- Video
signal rgb_r_s : std_logic_vector( 3 downto 0);
signal rgb_g_s : std_logic_vector( 3 downto 0);
signal rgb_b_s : std_logic_vector( 3 downto 0);
signal rgb_hsync_n_s : std_logic;
signal rgb_vsync_n_s : std_logic;
signal ntsc_pal_s : std_logic;
signal vga_en_s : std_logic;
-- Keyboard
signal rows_s : std_logic_vector( 3 downto 0);
signal cols_s : std_logic_vector( 7 downto 0);
signal caps_en_s : std_logic;
signal extra_keys_s : std_logic_vector( 3 downto 0);
signal keyb_valid_s : std_logic;
signal keyb_data_s : std_logic_vector( 7 downto 0);
signal keymap_addr_s : std_logic_vector( 8 downto 0);
signal keymap_data_s : std_logic_vector( 7 downto 0);
signal keymap_we_s : std_logic;
-- Joystick (Minimig Standard)
alias J0_UP : std_logic is gpio1_io(34); -- Pin 1
alias J0_DOWN : std_logic is gpio1_io(32); -- Pin 2
alias J0_LEFT : std_logic is gpio1_io(30); -- Pin 3
alias J0_RIGHT : std_logic is gpio1_io(28); -- Pin 4
alias J0_MMB : std_logic is gpio1_io(26); -- Pin 5
alias J0_BTN : std_logic is gpio1_io(35); -- Pin 6
alias J0_BTN2 : std_logic is gpio1_io(29); -- Pin 9
alias J1_UP : std_logic is gpio1_io(24);
alias J1_DOWN : std_logic is gpio1_io(22);
alias J1_LEFT : std_logic is gpio1_io(20);
alias J1_RIGHT : std_logic is gpio1_io(23);
alias J1_MMB : std_logic is gpio1_io(27);
alias J1_BTN : std_logic is gpio1_io(25);
alias J1_BTN2 : std_logic is gpio1_io(21);
-- SD
signal sd_cs_n_s : std_logic;
-- Bus
signal bus_addr_s : std_logic_vector(15 downto 0);
signal bus_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal bus_data_to_s : std_logic_vector( 7 downto 0);
signal bus_rd_n_s : std_logic;
signal bus_wr_n_s : std_logic;
signal bus_m1_n_s : std_logic;
signal bus_iorq_n_s : std_logic;
signal bus_mreq_n_s : std_logic;
signal bus_sltsl1_n_s : std_logic;
signal bus_sltsl2_n_s : std_logic;
signal bus_int_n_s : std_logic;
-- JT51
signal jt51_cs_n_s : std_logic := '1';
signal jt51_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal jt51_hd_s : std_logic := '0';
signal jt51_left_s : signed(15 downto 0) := (others => '0');
signal jt51_right_s : signed(15 downto 0) := (others => '0');
-- OPLL
signal opll_cs_n_s : std_logic := '1';
signal opll_mo_s : signed(12 downto 0) := (others => '0');
signal opll_ro_s : signed(12 downto 0) := (others => '0');
-- Serial interface
signal serial_cs_s : std_logic := '0';
signal serial_data_from_s: std_logic_vector( 7 downto 0) := (others => '1');
signal serial_hd_s : std_logic := '0';
-- Debug
signal D_display_s : std_logic_vector(15 downto 0);
begin
-- PLL
pll_1: entity work.pll1
port map (
inclk0 => clk50_i,
c0 => clock_master_s, -- 21.428571 MHz (6x NTSC)
c1 => clock_sdram_s, -- 85.714286
c2 => dram_clk_o, -- 85.714286 90°
locked => pll_locked_s
);
pll_2: entity work.pll2
port map (
inclk0 => clk27_i,
c0 => clock_audio_s, -- 24.000000 MHz
c1 => clock_16m_s -- 16 MHz
);
-- Clocks
clks: entity work.clocks
port map (
clock_i => clock_master_s,
por_i => not pll_locked_s,
turbo_on_i => turbo_on_s,
clock_vdp_o => clock_vdp_s,
clock_5m_en_o => open,
clock_cpu_o => clock_cpu_s,
clock_psg_en_o => clock_psg_en_s,
clock_3m_o => clock_3m_s
);
-- The MSX1
the_msx: entity work.msx
generic map (
hw_id_g => 2,
hw_txt_g => "DE-2 Board",
hw_version_g => actual_version,
video_opt_g => 1, -- dblscan configurable
ramsize_g => 8192
)
port map (
-- Clocks
clock_i => clock_master_s,
clock_vdp_i => clock_vdp_s,
clock_cpu_i => clock_cpu_s,
clock_psg_en_i => clock_psg_en_s,
-- Turbo
turbo_on_k_i => extra_keys_s(3), -- F11
turbo_on_o => turbo_on_s,
-- Resets
reset_i => reset_s,
por_i => por_s,
softreset_o => soft_reset_s_s,
-- Options
opt_nextor_i => '1',
opt_mr_type_i => sw_i(2 downto 1),
opt_vga_on_i => '1',
-- RAM
ram_addr_o => ram_addr_s,
ram_data_i => ram_data_from_s,
ram_data_o => ram_data_to_s,
ram_ce_o => ram_ce_s,
ram_we_o => ram_we_s,
ram_oe_o => ram_oe_s,
-- ROM
rom_addr_o => open,
rom_data_i => ram_data_from_s,
rom_ce_o => open,
rom_oe_o => open,
-- External bus
bus_addr_o => bus_addr_s,
bus_data_i => bus_data_from_s,
bus_data_o => bus_data_to_s,
bus_rd_n_o => bus_rd_n_s,
bus_wr_n_o => bus_wr_n_s,
bus_m1_n_o => bus_m1_n_s,
bus_iorq_n_o => bus_iorq_n_s,
bus_mreq_n_o => bus_mreq_n_s,
bus_sltsl1_n_o => bus_sltsl1_n_s,
bus_sltsl2_n_o => bus_sltsl2_n_s,
bus_wait_n_i => '1',
bus_nmi_n_i => '1',
bus_int_n_i => bus_int_n_s,
-- VDP RAM
vram_addr_o => vram_addr_s,
vram_data_i => vram_data_from_s,
vram_data_o => vram_data_to_s,
vram_ce_o => vram_ce_s,
vram_oe_o => vram_oe_s,
vram_we_o => vram_we_s,
-- Keyboard
rows_o => rows_s,
cols_i => cols_s,
caps_en_o => caps_en_s,
keyb_valid_i => keyb_valid_s,
keyb_data_i => keyb_data_s,
keymap_addr_o => keymap_addr_s,
keymap_data_o => keymap_data_s,
keymap_we_o => keymap_we_s,
-- Audio
audio_scc_o => audio_scc_s,
audio_psg_o => audio_psg_s,
beep_o => beep_s,
volumes_o => volumes_s,
-- K7
k7_motor_o => open,
k7_audio_o => open,
k7_audio_i => ear_s,
-- Joystick
joy1_up_i => J0_UP,
joy1_down_i => J0_DOWN,
joy1_left_i => J0_LEFT,
joy1_right_i => J0_RIGHT,
joy1_btn1_i => J0_BTN,
joy1_btn1_o => J0_BTN,
joy1_btn2_i => J0_BTN2,
joy1_btn2_o => J0_BTN2,
joy1_out_o => open,
joy2_up_i => J1_UP,
joy2_down_i => J1_DOWN,
joy2_left_i => J1_LEFT,
joy2_right_i => J1_RIGHT,
joy2_btn1_i => J1_BTN,
joy2_btn1_o => J1_BTN,
joy2_btn2_i => J1_BTN2,
joy2_btn2_o => J1_BTN2,
joy2_out_o => open,
-- Video
rgb_r_o => rgb_r_s,
rgb_g_o => rgb_g_s,
rgb_b_o => rgb_b_s,
hsync_n_o => rgb_hsync_n_s,
vsync_n_o => rgb_vsync_n_s,
ntsc_pal_o => ntsc_pal_s,
vga_on_k_i => extra_keys_s(2), -- Print Screen
scanline_on_k_i=> extra_keys_s(1), -- Scroll Lock
vga_en_o => vga_en_s,
-- SPI/SD
flspi_cs_n_o => open,
spi_cs_n_o => sd_cs_n_s,
spi_sclk_o => sd_sclk_o,
spi_mosi_o => sd_mosi_o,
spi_miso_i => sd_miso_i,
sd_pres_n_i => '0',
sd_wp_i => '0',
-- DEBUG
D_wait_o => open,
D_slots_o => open,
D_ipl_en_o => open
);
-- Keyboard PS/2
keyb: entity work.keyboard
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
-- MSX
rows_coded_i => rows_s,
cols_o => cols_s,
keymap_addr_i => keymap_addr_s,
keymap_data_i => keymap_data_s,
keymap_we_i => keymap_we_s,
-- LEDs
led_caps_i => caps_en_s,
-- PS/2 interface
ps2_clk_io => ps2_clk_io,
ps2_data_io => ps2_dat_io,
-- Direct Access
keyb_valid_o => keyb_valid_s,
keyb_data_o => keyb_data_s,
--
reset_o => soft_reset_k_s,
por_o => soft_por_s,
reload_core_o => open,
extra_keys_o => extra_keys_s
);
-- VRAM
vram: entity work.spram
generic map (
addr_width_g => 14,
data_width_g => 8
)
port map (
clk_i => clock_master_s,
we_i => vram_we_s,
addr_i => vram_addr_s,
data_i => vram_data_to_s,
data_o => vram_data_from_s
);
-- sram_addr_o <= "0000" & vram_addr_s;
-- sram_data_io <= "ZZZZZZZZ" & vram_data_to_s when vram_we_s = '1' else
-- (others => 'Z');
-- vram_data_from_s <= sram_data_io( 7 downto 0);
-- sram_ub_n_o <= '1';
-- sram_lb_n_o <= '0';
-- sram_ce_n_o <= not vram_ce_s;
-- sram_oe_n_o <= not vram_oe_s;
-- sram_we_n_o <= not vram_we_s;
-- RAM
ram: entity work.ssdram
generic map (
freq_g => 86
)
port map (
clock_i => clock_sdram_s,
reset_i => reset_s,
refresh_i => '1',
-- Static RAM bus
addr_i => ram_addr_s,
data_i => ram_data_to_s,
data_o => ram_data_from_s,
cs_i => ram_ce_s,
oe_i => ram_oe_s,
we_i => ram_we_s,
-- SD-RAM ports
mem_cke_o => dram_cke_o,
mem_cs_n_o => dram_cs_n_o,
mem_ras_n_o => dram_ras_n_o,
mem_cas_n_o => dram_cas_n_o,
mem_we_n_o => dram_we_n_o,
mem_udq_o => dram_udqm_o,
mem_ldq_o => dram_ldqm_o,
mem_ba_o => dram_ba_o,
mem_addr_o => dram_addr_o,
mem_data_io => dram_data_io
);
-- Audio
mixer: entity work.mixers
port map (
clock_i => clock_master_s,
reset_i => reset_s,
volumes_i => volumes_s,
beep_i => beep_s,
ear_i => ear_s,
audio_scc_i => audio_scc_s,
audio_psg_i => audio_psg_s,
jt51_left_i => jt51_left_s,
jt51_right_i => jt51_right_s,
opll_mo_i => opll_mo_s,
opll_ro_i => opll_ro_s,
audio_mix_l_o => audio_l_s,
audio_mix_r_o => audio_r_s
);
codec: entity work.WM8731
port map (
clock_i => clock_audio_s,
reset_i => reset_s,
k7_audio_o => ear_s,
audio_l_i => audio_l_s,
audio_r_i => audio_r_s,
i2s_xck_o => aud_xck_o,
i2s_bclk_o => aud_bclk_o,
i2s_adclrck_o => aud_adclrck_o,
i2s_adcdat_i => aud_adcdat_i,
i2s_daclrck_o => aud_daclrck_o,
i2s_dacdat_o => aud_dacdat_o,
i2c_sda_io => i2c_sdat_io,
i2c_scl_io => i2c_sclk_io
);
-- Glue logic
-- Resets
por_s <= '1' when pll_locked_s = '0' or soft_por_s = '1' or key_n_i(3) = '0' else '0';
reset_s <= '1' when soft_rst_cnt_s = X"00" or por_s = '1' or key_n_i(0) = '0' else '0';
process(clock_master_s)
begin
if rising_edge(clock_master_s) then
if reset_s = '1' or por_s = '1' then
soft_rst_cnt_s <= X"FF";
elsif (soft_reset_k_s = '1' or soft_reset_s_s = '1') and soft_rst_cnt_s /= X"00" then
soft_rst_cnt_s <= soft_rst_cnt_s - 1;
end if;
end if;
end process;
-- SD
sd_cs_n_o <= sd_cs_n_s;
-- VGA Output
vga_r_o <= rgb_r_s & "000000";
vga_g_o <= rgb_g_s & "000000";
vga_b_o <= rgb_b_s & "000000";
vga_hsync_n_o <= rgb_hsync_n_s;
vga_vsync_n_o <= rgb_vsync_n_s;
vga_blank_n_o <= '1';
vga_clk_o <= clock_master_s;
-- Peripheral BUS control
bus_data_from_s <= jt51_data_from_s when jt51_hd_s = '1' else
serial_data_from_s when serial_hd_s = '1' else
(others => '1');
bus_int_n_s <= '1';
ptjt: if per_jt51_g generate
-- JT51 tests
jt51_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0010000" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x20 - 0x21
jt51: entity work.jt51_wrapper
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
addr_i => bus_addr_s(0),
cs_n_i => jt51_cs_n_s,
wr_n_i => bus_wr_n_s,
rd_n_i => bus_rd_n_s,
data_i => bus_data_to_s,
data_o => jt51_data_from_s,
has_data_o => jt51_hd_s,
ct1_o => open,
ct2_o => open,
irq_n_o => open,
p1_o => open,
-- Low resolution output (same as real chip)
sample_o => open,
left_o => open,
right_o => open,
-- Full resolution output
xleft_o => jt51_left_s,
xright_o => jt51_right_s,
-- unsigned outputs for sigma delta converters, full resolution
dacleft_o => open,
dacright_o => open
);
end generate;
popll: if per_opll_g generate
-- OPLL tests
opll_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0111110" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x7C - 0x7D
opll1 : entity work.OPLL
port map (
clock_i => clock_master_s,
clock_en_i => clock_psg_en_s,
reset_i => reset_s,
data_i => bus_data_to_s,
addr_i => bus_addr_s(0),
cs_n => opll_cs_n_s,
we_n => bus_wr_n_s,
melody_o => opll_mo_s,
rythm_o => opll_ro_s
);
end generate;
-- Tests UART
serial_cs_s <= '1' when bus_addr_s(7 downto 3) = "11001" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '0'; -- 0xC8 - 0xCF
serial: entity work.uart
port map (
clock_i => clock_16m_s,
reset_i => reset_s,
addr_i => bus_addr_s(2 downto 0),
data_i => bus_data_to_s,
data_o => serial_data_from_s,
has_data_o => serial_hd_s,
cs_i => serial_cs_s,
rd_i => not bus_rd_n_s,
wr_i => not bus_wr_n_s,
int_n_o => open,
--
rxd_i => uart_rx_i,
txd_o => uart_tx_o,
dsr_n_i => '0',
rts_n_o => open,
cts_n_i => '0',
dtr_n_o => open,
dcd_i => '0',
ri_n_i => '1'
);
-- DEBUG
D_display_s <= bus_addr_s;
ledg_o(7) <= turbo_on_s;
ledg_o(6) <= vga_en_s;
ledg_o(5) <= ntsc_pal_s;
ledg_o(4) <= not jt51_cs_n_s;
ledg_o(0) <= not sd_cs_n_s;
ledr_o(15 downto 0) <= std_logic_vector(jt51_left_s);
ld3: entity work.seg7
port map(
D => D_display_s(15 downto 12),
Q => display3_o
);
ld2: entity work.seg7
port map(
D => D_display_s(11 downto 8),
Q => display2_o
);
ld1: entity work.seg7
port map(
D => D_display_s(7 downto 4),
Q => display1_o
);
ld0: entity work.seg7
port map(
D => D_display_s(3 downto 0),
Q => display0_o
);
end architecture;
|
gpl-3.0
|
29d0ac6597957feb7e8e36d8ea33491c
| 0.544529 | 2.293399 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/YM2149.vhd
| 2 | 17,662 |
--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- by FBLabs: renamed signals and fixed port_a and port_b directions
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity YM2149 is
port (
clock_i : in std_logic;
clock_en_i : in std_logic;
reset_i : in std_logic;
sel_n_i : in std_logic; -- 1 = AY-3-8912 compatibility
ayymmode_i : in std_logic; -- 0 = YM, 1 = AY
-- data bus
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
-- control
a9_l_i : in std_logic;
a8_i : in std_logic;
bdir_i : in std_logic;
bc1_i : in std_logic;
bc2_i : in std_logic;
-- I/O ports
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
-- audio channels out
audio_ch_a_o : out std_logic_vector(7 downto 0);
audio_ch_b_o : out std_logic_vector(7 downto 0);
audio_ch_c_o : out std_logic_vector(7 downto 0);
audio_ch_mix_o : out unsigned(7 downto 0) -- mixed audio
);
end;
architecture RTL of YM2149 is
-- signals
type array_16x8_t is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12_t is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : unsigned(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal busctrl_addr_s : std_logic;
signal busctrl_we_s : std_logic;
signal busctrl_re_s : std_logic;
signal reg_addr_q : std_logic_vector(7 downto 0);
signal regs_q : array_16x8_t := (7 => (others => '1'), others => (others => '0'));
signal env_reset : std_logic;
signal noise_gen_cnt : unsigned(4 downto 0) := (others => '0');
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12_t := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0) := (others => '0');
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal A : std_logic_vector(4 downto 0);
signal B : std_logic_vector(4 downto 0);
signal C : std_logic_vector(4 downto 0);
-- signal vol_table_in : std_logic_vector(11 downto 0);
-- signal vol_table_out : std_logic_vector(9 downto 0);
type volTableType32 is array (0 to 31) of unsigned(7 downto 0);
type volTableType16 is array (0 to 15) of unsigned(7 downto 0);
constant volTableAy : volTableType16 :=(
x"00", x"03", x"04", x"06",
x"0a", x"0f", x"15", x"22",
x"28", x"41", x"5b", x"72",
x"90", x"b5", x"d7", x"ff"
);
constant volTableYm : volTableType32 :=(
x"00", x"01", x"01", x"02", x"02", x"03", x"03", x"04",
x"06", x"07", x"09", x"0a", x"0c", x"0e", x"11", x"13",
x"17", x"1b", x"20", x"25", x"2c", x"35", x"3e", x"47",
x"54", x"66", x"77", x"88", x"a1", x"c0", x"e0", x"ff"
);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
-- CPU Bus
process (bdir_i, bc1_i, bc2_i, a8_i, a9_l_i, reg_addr_q)
variable cs_v : std_logic;
variable sel_v : std_logic_vector(2 downto 0);
begin
busctrl_addr_s <= '0';
busctrl_re_s <= '0';
busctrl_we_s <= '0';
cs_v := '0';
if a9_l_i = '0' and a8_i = '1' and reg_addr_q(7 downto 4) = "0000" then
cs_v := '1';
end if;
sel_v := bdir_i & bc2_i & bc1_i;
case sel_v is
when "000" => null;
when "001" => busctrl_addr_s <= '1';
when "010" => null; -- 00
when "011" => busctrl_re_s <= cs_v; -- 01
when "100" => busctrl_addr_s <= '1';
when "101" => null;
when "110" => busctrl_we_s <= cs_v; -- 10
when "111" => busctrl_addr_s <= '1'; -- 11
when others => null;
end case;
end process;
-- latch addr
process(reset_i, busctrl_addr_s)
begin
if reset_i = '1' then
reg_addr_q <= (others => '0');
elsif falling_edge(busctrl_addr_s) then
reg_addr_q <= data_i;
end if;
end process;
-- latch register
process(reset_i, busctrl_we_s, reg_addr_q)
begin
if reset_i = '1' then
regs_q <= (7 => (others => '1'), others => (others => '0'));
elsif falling_edge(busctrl_we_s) then
case reg_addr_q(3 downto 0) is
when x"0" => regs_q(0) <= data_i;
when x"1" => regs_q(1) <= data_i;
when x"2" => regs_q(2) <= data_i;
when x"3" => regs_q(3) <= data_i;
when x"4" => regs_q(4) <= data_i;
when x"5" => regs_q(5) <= data_i;
when x"6" => regs_q(6) <= data_i;
when x"7" => regs_q(7) <= data_i;
when x"8" => regs_q(8) <= data_i;
when x"9" => regs_q(9) <= data_i;
when x"A" => regs_q(10) <= data_i;
when x"B" => regs_q(11) <= data_i;
when x"C" => regs_q(12) <= data_i;
when x"D" => regs_q(13) <= data_i;
when x"E" => regs_q(14) <= data_i;
when x"F" => regs_q(15) <= data_i;
when others => null;
end case;
end if;
env_reset <= '0';
if busctrl_we_s = '1' and reg_addr_q(3 downto 0) = x"D" then
env_reset <= '1';
end if;
end process;
-- read register
process(busctrl_re_s, reg_addr_q, regs_q, port_a_i)
begin
data_o <= (others => '0');
if busctrl_re_s = '1' then
case reg_addr_q(3 downto 0) is
when x"0" => data_o <= regs_q(0);
when x"1" => data_o <= "0000" & regs_q(1)(3 downto 0);
when x"2" => data_o <= regs_q(2);
when x"3" => data_o <= "0000" & regs_q(3)(3 downto 0);
when x"4" => data_o <= regs_q(4);
when x"5" => data_o <= "0000" & regs_q(5)(3 downto 0);
when x"6" => data_o <= "000" & regs_q(6)(4 downto 0);
when x"7" => data_o <= regs_q(7);
when x"8" => data_o <= "000" & regs_q(8)(4 downto 0);
when x"9" => data_o <= "000" & regs_q(9)(4 downto 0);
when x"A" => data_o <= "000" & regs_q(10)(4 downto 0);
when x"B" => data_o <= regs_q(11);
when x"C" => data_o <= regs_q(12);
when x"D" => data_o <= "0000" & regs_q(13)(3 downto 0);
when x"E" =>
data_o <= port_a_i;
when x"F" =>
data_o <= regs_q(15);
when others => null;
end case;
end if;
end process;
port_b_o <= regs_q(15);
-- p_divider : process
process(clock_i, clock_en_i)
begin
if rising_edge(clock_i) and clock_en_i = '1' then
ena_div <= '0';
ena_div_noise <= '0';
if cnt_div = "0000" then
cnt_div <= (not sel_n_i) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if noise_div = '1' then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- p_noise_gen : process
process(clock_i)
variable noise_gen_comp : unsigned(4 downto 0) := (others => '0');
variable poly17_zero : std_logic;
begin
if rising_edge(clock_i) then
if regs_q(6)(4 downto 0) = "00000" then
noise_gen_comp := "00000";
else
noise_gen_comp := unsigned( regs_q(6)(4 downto 0) ) - 1;
end if;
poly17_zero := '0';
if poly17 = "00000000000000000" then
poly17_zero := '1';
end if;
if clock_en_i = '1' then
if ena_div_noise = '1' then -- divider ena
if noise_gen_cnt >= noise_gen_comp then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= noise_gen_cnt + 1;
end if;
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
--p_tone_gens : process
process(clock_i)
variable tone_gen_freq : array_3x12_t := (others => (others => '0'));
variable tone_gen_comp : array_3x12_t := (others => (others => '0'));
begin
if rising_edge(clock_i) then
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := regs_q(1)(3 downto 0) & regs_q(0);
tone_gen_freq(2) := regs_q(3)(3 downto 0) & regs_q(2);
tone_gen_freq(3) := regs_q(5)(3 downto 0) & regs_q(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := std_logic_vector( unsigned(tone_gen_freq(i)) - 1 );
end if;
end loop;
if clock_en_i = '1' then
for i in 1 to 3 loop
if ena_div = '1' then -- divider ena
if tone_gen_cnt(i) >= tone_gen_comp(i) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= std_logic_vector( unsigned(tone_gen_cnt(i)) + 1 );
end if;
end if;
end loop;
end if;
end if;
end process;
--p_envelope_freq : process
process(clock_i)
variable env_gen_freq : std_logic_vector(15 downto 0) := (others => '0');
variable env_gen_comp : std_logic_vector(15 downto 0) := (others => '0');
begin
if rising_edge(clock_i) then
env_gen_freq := regs_q(12) & regs_q(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := std_logic_vector( unsigned(env_gen_freq) - 1 );
end if;
if clock_en_i = '1' then
env_ena <= '0';
if ena_div = '1' then -- divider ena
if env_gen_cnt >= env_gen_comp then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= std_logic_vector( unsigned( env_gen_cnt ) + 1 );
end if;
end if;
end if;
end if;
end process;
--p_envelope_shape : process(env_reset, CLK)
process(clock_i)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if rising_edge(clock_i) then
if env_reset = '1' then
-- load initial state
if (regs_q(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
else
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if clock_en_i = '1' then
if env_ena = '1' then
if env_hold = '0' then
if env_inc = '1' then
env_vol <= std_logic_vector( unsigned( env_vol ) + "00001");
else
env_vol <= std_logic_vector( unsigned( env_vol ) + "11111");
end if;
end if;
-- envelope shape control.
if (regs_q(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then
env_hold <= '1';
end if;
else
if is_top then
env_hold <= '1';
end if;
end if;
else
if (regs_q(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (regs_q(13)(1) = '1') then -- alt
if is_bot then
env_hold <= '1';
end if;
else
if is_bot_p1 then
env_hold <= '1';
end if;
end if;
else
if (regs_q(13)(1) = '1') then -- alt
if is_top then
env_hold <= '1';
end if;
else
if is_top_m1 then
env_hold <= '1';
end if;
end if;
end if;
elsif (regs_q(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then
env_hold <= '1';
end if;
if is_bot then
env_hold <= '0';
env_inc <= '1';
end if;
else
if is_top_m1 then
env_hold <= '1';
end if;
if is_top then
env_hold <= '0';
env_inc <= '0';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
--p_chan_mixer_table : process
process(clock_i)
variable chan_mixed : std_logic_vector(2 downto 0);
begin
if rising_edge(clock_i) then
if clock_en_i = '1' then
chan_mixed(0) := (regs_q(7)(0) or tone_gen_op(1)) and (regs_q(7)(3) or noise_gen_op);
chan_mixed(1) := (regs_q(7)(1) or tone_gen_op(2)) and (regs_q(7)(4) or noise_gen_op);
chan_mixed(2) := (regs_q(7)(2) or tone_gen_op(3)) and (regs_q(7)(5) or noise_gen_op);
A <= "00000";
B <= "00000";
C <= "00000";
if (chan_mixed(0) = '1') then
if (regs_q(8)(4) = '0') then
A <= regs_q(8)(3 downto 0) & "1";
else
A <= env_vol(4 downto 0);
end if;
end if;
if (chan_mixed(1) = '1') then
if (regs_q(9)(4) = '0') then
B <= regs_q(9)(3 downto 0) & "1";
else
B <= env_vol(4 downto 0);
end if;
end if;
if (chan_mixed(2) = '1') then
if (regs_q(10)(4) = '0') then
C <= regs_q(10)(3 downto 0) & "1";
else
C <= env_vol(4 downto 0);
end if;
end if;
end if;
end if;
end process;
process(clock_i)
variable out_audio_mixed : unsigned(9 downto 0);
begin
if rising_edge(clock_i) then
if reset_i = '1' then
audio_ch_mix_o <= x"00";
audio_ch_a_o <= x"00";
audio_ch_b_o <= x"00";
audio_ch_c_o <= x"00";
else
if ayymmode_i = '0' then
out_audio_mixed := ("00" & volTableYm( to_integer( unsigned( A )))) +
("00" & volTableYm( to_integer( unsigned( B )))) +
("00" & volTableYm( to_integer( unsigned( C ))));
audio_ch_mix_o <= out_audio_mixed(9 downto 2);
audio_ch_a_o <= std_logic_vector( volTableYm( to_integer( unsigned( A ) ) ) );
audio_ch_b_o <= std_logic_vector( volTableYm( to_integer( unsigned( B ) ) ) );
audio_ch_c_o <= std_logic_vector( volTableYm( to_integer( unsigned( C ) ) ) );
else
out_audio_mixed := ( "00" & volTableAy( to_integer( unsigned( A(4 downto 1) )))) +
( "00" & volTableAy( to_integer( unsigned( B(4 downto 1) )))) +
( "00" & volTableAy( to_integer( unsigned( C(4 downto 1) ))));
audio_ch_mix_o <= out_audio_mixed(9 downto 2);
audio_ch_a_o <= std_logic_vector( volTableAy( to_integer( unsigned( A(4 downto 1) ) ) ) );
audio_ch_b_o <= std_logic_vector( volTableAy( to_integer( unsigned( B(4 downto 1) ) ) ) );
audio_ch_c_o <= std_logic_vector( volTableAy( to_integer( unsigned( C(4 downto 1) ) ) ) );
end if;
end if;
end if;
end process;
end architecture RTL;
|
gpl-3.0
|
89ebd0ab6aa1ff6856a8fb388b276b8b
| 0.535557 | 2.700612 | false | false | false | false |
peteg944/music-fpga
|
LED_Matrix_FPGA_Nexys 3/uart_rx.vhd
| 4 | 6,141 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity uart_rx is
generic (
log2_oversampling : integer := 4);
port (
RST : in std_logic;
RDCLK : in std_logic;
CLKOSX : in std_logic;
RXD : in std_logic;
RDADDR : in std_logic_vector(8 downto 0);
RDDATA : out std_logic_vector(47 downto 0);
FRAMESEL : out std_logic);
end uart_rx;
architecture rtl of uart_rx is
type STATE_TYPE is (st0_idle, st1_read_start_bit, st2_read_data_bits, st3_read_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal WREN : std_logic;
signal WRRST : std_logic;
signal WRDATA : std_logic_vector(7 downto 0);
--signal WRCOUNT : std_logic_vector(10 downto 0);
--signal RDCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVCTREN : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal RXDATA : std_logic;
signal NEXT_WRDATA : std_logic_vector(7 downto 0);
signal we_red : std_logic_vector(1 downto 0);
signal we_green : std_logic_vector(1 downto 0);
signal we_blue : std_logic_vector(1 downto 0);
signal rdaddr_ext : std_logic_vector(9 downto 0);
signal rd_msb : std_logic;
signal rgb_ctr : std_logic_vector(1 downto 0);
signal wr_addr : std_logic_vector(10 downto 0);
signal wr_addr_short : std_logic_vector(9 downto 0);
signal wr_inc : std_logic;
begin
i_gen : for i in 1 downto 0 generate
-- RAM for red color
ram_red : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_red(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+7 downto i*24));
-- RAM for green color
ram_green : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_green(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+15 downto i*24+8));
-- RAM for blue color
ram_blue : entity work.bram
generic map (
addr_res => 10,
d_res => 8)
port map (
RCLK => RDCLK,
WCLK => CLKOSX,
WE => we_blue(i),
ADDRI => wr_addr_short,
ADDRO => rdaddr_ext,
DI => WRDATA,
DO => RDDATA(i*24+23 downto i*24+16));
end generate i_gen;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
WRDATA <= (others => '0');
RXDATA <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
WRDATA <= NEXT_WRDATA;
RXDATA <= RXD;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, RXDATA, WRDATA, DIVCTR, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_WRDATA <= WRDATA;
DIVCTREN <= '1';
BYTECTRINC <= '0';
WREN <= '0';
WRRST <= '0';
case STATE is
when st0_idle =>
if (RXDATA = '0') then
NEXT_STATE <= st1_read_start_bit;
else
DIVCTREN <= '0';
end if;
when st1_read_start_bit =>
if DIVCTR(log2_oversampling-1) = '1' then
NEXT_STATE <= st2_read_data_bits;
BYTECTRINC <= '1';
DIVCTREN <= '0';
end if;
when st2_read_data_bits =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_WRDATA(conv_integer(BYTECTR)) <= RXDATA;
if (BYTECTR = "111") then
NEXT_STATE <= st3_read_stop_bit;
else
BYTECTRINC <= '1';
end if;
end if;
when st3_read_stop_bit =>
if (DIVCTR = 2**log2_oversampling-1) then
NEXT_STATE <= st0_idle;
if WRDATA = 1 then
WREN <= '0';
WRRST <= RXDATA;
else
WREN <= RXDATA;
WRRST <= '0';
end if;
end if;
end case;
end process fsm_proc;
-- Clock divide counter
div_proc : process (CLKOSX)
begin
if rising_edge(CLKOSX) then
if DIVCTREN = '1' then
DIVCTR <= DIVCTR + 1;
else
DIVCTR <= (others => '0');
end if;
end if;
end process div_proc;
-- Byte counter
byte_proc : process (CLKOSX, RST)
begin
if RST = '1' then
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process byte_proc;
-- RGB color select
we_red(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(0) <= not wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
we_red(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "00")) else '0';
we_green(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "01")) else '0';
we_blue(1) <= wr_addr(9) when ((WREN = '1') and (rgb_ctr = "10")) else '0';
-- RAM control signals
rgb_proc : process (CLKOSX, RST)
begin
if RST = '1' then
rgb_ctr <= (others => '0');
wr_addr <= (others => '0');
elsif rising_edge(CLKOSX) then
if WRRST = '1' then
rgb_ctr <= (others => '0');
wr_addr(9 downto 0) <= (others => '0');
elsif WREN = '1' then
if rgb_ctr = "10" then
rgb_ctr <= (others => '0');
wr_addr <= wr_addr + 1;
else
rgb_ctr <= rgb_ctr + 1;
end if;
end if;
end if;
end process rgb_proc;
-- Clock domain crossing
rd_proc : process (RDCLK)
begin
if rising_edge(RDCLK) then
rd_msb <= not wr_addr(10);
FRAMESEL <= rd_msb;
end if;
end process rd_proc;
rdaddr_ext <= rd_msb & RDADDR;
wr_addr_short <= wr_addr(10) & wr_addr(8 downto 0);
end rtl;
|
mit
|
2132733eda68f153953372e29b8406f4
| 0.539326 | 3.230405 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd
| 1 | 17,554 |
------------------------------------------------------------------------------
-- Title : Wishbone FMC130m_4ch Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-29-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top Module with records for the FMC516 ADC board interface from
-- Curtis Wright.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-29-10 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_generic_pkg.all;
-- FMC ADC package
use work.fmc_adc_pkg.all;
entity xwb_fmc130m_4ch is
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_adc_clk_period_values : t_clk_values_array := default_adc_clk_period_values;
g_use_clk_chains : t_clk_use_chain := default_clk_use_chain;
g_with_bufio_clk_chains : t_clk_use_bufio_chain := default_clk_use_bufio_chain;
g_with_bufr_clk_chains : t_clk_use_bufr_chain := default_clk_use_bufr_chain;
g_use_data_chains : t_data_use_chain := default_data_use_chain;
g_map_clk_data_chains : t_map_clk_data_chain := default_map_clk_data_chain;
g_ref_clk : t_ref_adc_clk := default_ref_adc_clk;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic;
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc0_of_i : in std_logic; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic;
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc1_of_i : in std_logic; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic;
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc2_of_i : in std_logic; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0);
fmc_adc3_of_i : in std_logic; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic;
fmc_pg_m2c_i : in std_logic;
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic;
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic;
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic;
fmc_fpga_clk_n_i : in std_logic;
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic;
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_rst_n_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o : out std_logic;
trig_hw_i : in std_logic := '0';
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_pll_status_o : out std_logic;
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end xwb_fmc130m_4ch;
architecture rtl of xwb_fmc130m_4ch is
signal wbs_adr_int : std_logic_vector(c_num_adc_channels*c_wbs_adr4_width-1 downto 0);
signal wbs_dat_int : std_logic_vector(c_num_adc_channels*c_wbs_dat16_width-1 downto 0);
signal wbs_cyc_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_stb_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_we_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_sel_int : std_logic_vector(c_num_adc_channels*c_wbs_sel16_width-1 downto 0);
signal wbs_ack_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_stall_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_err_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_rty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
begin
cmp_wb_fmc130m_4ch : wb_fmc130m_4ch
generic map (
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device => g_fpga_device,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_adc_clk_period_values => g_adc_clk_period_values,
g_use_clk_chains => g_use_clk_chains,
g_with_bufio_clk_chains => g_with_bufio_clk_chains,
g_with_bufr_clk_chains => g_with_bufr_clk_chains,
g_use_data_chains => g_use_data_chains,
g_map_clk_data_chains => g_map_clk_data_chains,
g_ref_clk => g_ref_clk,
g_packet_size => g_packet_size,
g_sim => g_sim
)
port map
(
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o => fmc_adc_pga_o,
fmc_adc_shdn_o => fmc_adc_shdn_o,
fmc_adc_dith_o => fmc_adc_dith_o,
fmc_adc_rand_o => fmc_adc_rand_o,
-- ADC0 LTC2208
fmc_adc0_clk_i => fmc_adc0_clk_i,
fmc_adc0_data_i => fmc_adc0_data_i,
fmc_adc0_of_i => fmc_adc0_of_i,
-- ADC1 LTC2208
fmc_adc1_clk_i => fmc_adc1_clk_i,
fmc_adc1_data_i => fmc_adc1_data_i,
fmc_adc1_of_i => fmc_adc1_of_i,
-- ADC2 LTC2208
fmc_adc2_clk_i => fmc_adc2_clk_i,
fmc_adc2_data_i => fmc_adc2_data_i,
fmc_adc2_of_i => fmc_adc2_of_i,
-- ADC3 LTC2208
fmc_adc3_clk_i => fmc_adc3_clk_i,
fmc_adc3_data_i => fmc_adc3_data_i,
fmc_adc3_of_i => fmc_adc3_of_i,
-- FMC General Status
fmc_prsnt_i => fmc_prsnt_i,
fmc_pg_m2c_i => fmc_pg_m2c_i,
--fmc_clk_dir_i : in std_logic, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o => fmc_trig_dir_o,
fmc_trig_term_o => fmc_trig_term_o,
fmc_trig_val_p_b => fmc_trig_val_p_b,
fmc_trig_val_n_b => fmc_trig_val_n_b,
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-- EEPROM
eeprom_scl_pad_b => eeprom_scl_pad_b,
eeprom_sda_pad_b => eeprom_sda_pad_b,
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b => lm75_scl_pad_b,
lm75_sda_pad_b => lm75_sda_pad_b,
fmc_lm75_temp_alarm_i => fmc_lm75_temp_alarm_i,
-- FMC LEDs
fmc_led1_o => fmc_led1_o,
fmc_led2_o => fmc_led2_o,
fmc_led3_o => fmc_led3_o,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => adc_clk_o,
adc_clk2x_o => adc_clk2x_o,
adc_rst_n_o => adc_rst_n_o,
adc_data_o => adc_data_o,
adc_data_valid_o => adc_data_valid_o,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => trig_hw_o,
trig_hw_i => trig_hw_i,
-- General board status
fmc_mmcm_lock_o => fmc_mmcm_lock_o,
fmc_pll_status_o => fmc_pll_status_o,
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_adr_o => wbs_adr_int,
wbs_dat_o => wbs_dat_int,
wbs_cyc_o => wbs_cyc_int,
wbs_stb_o => wbs_stb_int,
wbs_we_o => wbs_we_int,
wbs_sel_o => wbs_sel_int,
wbs_ack_i => wbs_ack_int,
wbs_stall_i => wbs_stall_int,
wbs_err_i => wbs_err_int,
wbs_rty_i => wbs_rty_int,
adc_dly_debug_o => adc_dly_debug_o,
fifo_debug_valid_o => fifo_debug_valid_o,
fifo_debug_full_o => fifo_debug_full_o,
fifo_debug_empty_o => fifo_debug_empty_o
);
gen_wbs_interfaces : for i in 0 to c_num_adc_channels-1 generate
gen_wbs_interfaces_ch : if g_use_data_chains(i) = '1' generate
wbs_ack_int(i) <= wbs_source_i(i).ack;
wbs_stall_int(i) <= wbs_source_i(i).stall;
wbs_err_int(i) <= wbs_source_i(i).err;
wbs_rty_int(i) <= wbs_source_i(i).rty;
wbs_source_o(i).adr <= wbs_adr_int(c_wbs_adr4_width*(i+1)-1 downto
c_wbs_adr4_width*i);
wbs_source_o(i).dat <= wbs_dat_int(c_wbs_dat16_width*(i+1)-1 downto
c_wbs_dat16_width*i);
wbs_source_o(i).sel <= wbs_sel_int(c_wbs_sel16_width*(i+1)-1 downto
c_wbs_sel16_width*i);
wbs_source_o(i).cyc <= wbs_cyc_int(i);
wbs_source_o(i).stb <= wbs_stb_int(i);
wbs_source_o(i).we <= wbs_we_int(i);
end generate;
end generate;
end rtl;
|
lgpl-3.0
|
03a7e6e8715b928b5393ff7860be594c
| 0.397288 | 3.956277 | false | false | false | false |
freecores/camellia-vhdl
|
pipelining/f.vhd
| 1 | 4,338 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: F function
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity F is
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end F;
architecture RTL of F is
-- S-BOX
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX2 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX3 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX4 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
signal y : STD_LOGIC_VECTOR (0 to 63);
signal y1, y2, y3, y4, y5, y6, y7, y8 : STD_LOGIC_VECTOR (0 to 7);
signal so1, so2, so3, so4, so5, so6, so7, so8 : STD_LOGIC_VECTOR (0 to 7);
signal pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8 : STD_LOGIC_VECTOR (0 to 7);
signal pb1, pb2, pb3, pb4, pb5, pb6, pb7, pb8 : STD_LOGIC_VECTOR (0 to 7);
begin
y <= x xor k;
y8 <= y(56 to 63);
y7 <= y(48 to 55);
y6 <= y(40 to 47);
y5 <= y(32 to 39);
y4 <= y(24 to 31);
y3 <= y(16 to 23);
y2 <= y(8 to 15);
y1 <= y(0 to 7);
-- S-FUNCTION
S1 : SBOX1
port map(clk, y8, y1, so8, so1);
S2 : SBOX2
port map(clk, y5, y2, so5, so2);
S3 : SBOX3
port map(clk, y6, y3, so6, so3);
S4 : SBOX4
port map(clk, y7, y4, so7, so4);
-- P-FUNCTION
pa8 <= so8 xor pa2;
pa7 <= so7 xor pa1;
pa6 <= so6 xor pa4;
pa5 <= so5 xor pa3;
pa4 <= so4 xor so5;
pa3 <= so3 xor so8;
pa2 <= so2 xor so7;
pa1 <= so1 xor so6;
pb8 <= pa8 xor pb3;
pb7 <= pa7 xor pb2;
pb6 <= pa6 xor pb1;
pb5 <= pa5 xor pb4;
pb4 <= pa4 xor pa7;
pb3 <= pa3 xor pa6;
pb2 <= pa2 xor pa5;
pb1 <= pa1 xor pa8;
z <= pb5 & pb6 & pb7 & pb8 & pb1 & pb2 & pb3 & pb4;
end RTL;
|
gpl-3.0
|
a4b4f25be5ae3e27b859b6d5313afc69
| 0.501844 | 3.464856 | false | false | false | false |
z3774/sparcv8-monocycle
|
SEU.vhd
| 1 | 778 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SEU is
Port (
imm13 : in STD_LOGIC_VECTOR (12 downto 0);
sign_ext : out STD_LOGIC_VECTOR (31 downto 0)
);
end SEU;
architecture Behavioral of SEU is
begin
process(imm13)
begin
if(imm13(12) = '0') then
sign_ext(31 downto 13) <= (others=>'0');
sign_ext(12 downto 0) <= imm13;
else
sign_ext(31 downto 13) <= (others=>'1');
sign_ext(12 downto 0) <= imm13;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
9f7559996d5f6068a3d665178e06c4fb
| 0.686375 | 3.188525 | false | false | false | false |
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