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lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd
| 1 | 16,066 |
-------------------------------------------------------------------------------------
-- FILE NAME : ads62p49_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - ads62p49_ctrl
-- architecture - ads62p49_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the ADS62P49 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity ads62p49_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
adc_reset : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end ads62p49_ctrl;
architecture ads62p49_ctrl_syn of ads62p49_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component ads62p49_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000077";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000076";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0000076";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal reset : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(15 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(15 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
gen_serial_clk : if (g_sim = 0) generate
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the rising edge of SCLK.
-- therefore we make sure the external clock is slightly
-- after the internal clock.
serial_clk <= clk_div(clk_div'length-1);
sclk_ext <= serial_clk;
end if;
end process;
end generate;
-- Do not divide clock. Improve simulation speed.
gen_serial_clk_sim : if (g_sim = 1) generate
serial_clk <= clk;
end generate;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
reset <= '1';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
reset <= out_reg(1);
else
reset <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & reset & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(7 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(7 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= sh_counter_gen;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= init_data;
-- Stop when update instruction is reveived (= last instruction)
if (init_data(15 downto 8) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
ads62p49_init_mem_inst : ads62p49_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
adc_reset <= reset;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end ads62p49_ctrl_syn;
|
lgpl-3.0
|
6c665f7f65f2f9a9dea6b07a6643dc5d
| 0.47585 | 3.66469 | false | false | false | false |
freecores/camellia-vhdl
|
pipelining/sbox3.vhd
| 1 | 2,421 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX3
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SBOX3 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX3;
architecture RTL of SBOX3 is
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
begin
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
s1_clk <= clk;
s1_addra <= addra;
s1_addrb <= addrb;
douta <= s1_douta(7) & s1_douta(0 to 6);
doutb <= s1_doutb(7) & s1_doutb(0 to 6);
end RTL;
|
gpl-3.0
|
87831e3498c099273d226652791d703e
| 0.587361 | 3.668182 | false | false | false | false |
VectorBlox/risc-v
|
ip/ready_delayer/hdl/ready_delayer.vhd
| 1 | 8,658 |
-- ready_delayer.vhd
-- Copyright (C) 2018 VectorBlox Computing, Inc.
-------------------------------------------------------------------------------
-- This component delays ready/valid pairs in an AXI-compatible way
-------------------------------------------------------------------------------
-- synthesis library ready_delayer_lib
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ready_delayer is
generic (
READY_VALID_PAIRS : positive range 1 to 8 := 1;
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
valid0_in : in std_logic;
ready0_in : in std_logic;
valid0_out : out std_logic;
ready0_out : out std_logic;
valid1_in : in std_logic;
ready1_in : in std_logic;
valid1_out : out std_logic;
ready1_out : out std_logic;
valid2_in : in std_logic;
ready2_in : in std_logic;
valid2_out : out std_logic;
ready2_out : out std_logic;
valid3_in : in std_logic;
ready3_in : in std_logic;
valid3_out : out std_logic;
ready3_out : out std_logic;
valid4_in : in std_logic;
ready4_in : in std_logic;
valid4_out : out std_logic;
ready4_out : out std_logic;
valid5_in : in std_logic;
ready5_in : in std_logic;
valid5_out : out std_logic;
ready5_out : out std_logic;
valid6_in : in std_logic;
ready6_in : in std_logic;
valid6_out : out std_logic;
ready6_out : out std_logic;
valid7_in : in std_logic;
ready7_in : in std_logic;
valid7_out : out std_logic;
ready7_out : out std_logic
);
end;
architecture rtl of ready_delayer is
constant LOG2_MAX_READY_VALID_PAIRS : positive := 3;
constant MAX_READY_VALID_PAIRS : positive := 2**LOG2_MAX_READY_VALID_PAIRS;
constant LOG2_REGISTERS : positive := LOG2_MAX_READY_VALID_PAIRS;
signal axi_write_register : unsigned(LOG2_REGISTERS-1 downto 0);
signal axi_read_register : unsigned(LOG2_REGISTERS-1 downto 0);
constant DELAY_MASK_BITS : positive range 1 to 31 := 16;
constant DONT_DELAY : std_logic_vector(DELAY_MASK_BITS-1 downto 0) := (others => '0');
subtype delay_mask_type is std_logic_vector(DELAY_MASK_BITS-1 downto 0);
type delay_mask_vector is array (natural range <>) of delay_mask_type;
signal delay_mask : delay_mask_vector(MAX_READY_VALID_PAIRS-1 downto 0);
signal random_delay : std_logic_vector(MAX_READY_VALID_PAIRS-1 downto 0);
signal counter : unsigned(DELAY_MASK_BITS-1 downto 0);
signal lfsr32 : std_logic_vector(31 downto 0);
signal delay_channel : std_logic_vector(MAX_READY_VALID_PAIRS-1 downto 0);
signal valid_in : std_logic_vector(MAX_READY_VALID_PAIRS-1 downto 0);
signal ready_in : std_logic_vector(MAX_READY_VALID_PAIRS-1 downto 0);
signal valid_out : std_logic_vector(MAX_READY_VALID_PAIRS-1 downto 0);
signal ready_out : std_logic_vector(MAX_READY_VALID_PAIRS-1 downto 0);
signal S_AXI_AWREADY_signal : std_logic;
signal S_AXI_WREADY_signal : std_logic;
signal S_AXI_BVALID_signal : std_logic;
signal S_AXI_ARREADY_signal : std_logic;
signal S_AXI_RVALID_signal : std_logic;
begin
S_AXI_AWREADY <= S_AXI_AWREADY_signal;
S_AXI_WREADY <= S_AXI_WREADY_signal;
S_AXI_BVALID <= S_AXI_BVALID_signal;
S_AXI_ARREADY <= S_AXI_ARREADY_signal;
S_AXI_RVALID <= S_AXI_RVALID_signal;
--Half throughput (not checking for BREADY/RREADY) but makes timing better
S_AXI_AWREADY_signal <= S_AXI_WVALID and (not S_AXI_BVALID_signal);
S_AXI_WREADY_signal <= S_AXI_AWVALID and (not S_AXI_BVALID_signal);
S_AXI_ARREADY_signal <= (not S_AXI_RVALID_signal);
S_AXI_BRESP <= (others => '0');
S_AXI_RRESP <= (others => '0');
axi_write_register <= unsigned(S_AXI_AWADDR(LOG2_REGISTERS+1 downto 2));
axi_read_register <= unsigned(S_AXI_ARADDR(LOG2_REGISTERS+1 downto 2));
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_RREADY = '1' then
S_AXI_RVALID_signal <= '0';
end if;
if S_AXI_BREADY = '1' then
S_AXI_BVALID_signal <= '0';
end if;
if S_AXI_ARVALID = '1' and S_AXI_ARREADY_signal = '1' then
S_AXI_RVALID_signal <= '1';
S_AXI_RDATA <= (others => '0');
S_AXI_RDATA(DELAY_MASK_BITS-1 downto 0) <= delay_mask(to_integer(axi_read_register));
S_AXI_RDATA(31) <= random_delay(to_integer(axi_read_register));
end if;
if S_AXI_AWVALID = '1' and S_AXI_AWREADY_signal = '1' and S_AXI_WVALID = '1' and S_AXI_WREADY_signal = '1' then
S_AXI_BVALID_signal <= '1';
delay_mask(to_integer(axi_write_register)) <= S_AXI_WDATA(DELAY_MASK_BITS-1 downto 0);
random_delay(to_integer(axi_write_register)) <= S_AXI_WDATA(31);
end if;
if S_AXI_ARESETN = '0' then
delay_mask <= (others => (others => '0'));
random_delay <= (others => '0');
S_AXI_RVALID_signal <= '0';
S_AXI_BVALID_signal <= '0';
end if;
end if;
end process;
process (S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
counter <= counter + to_unsigned(1, counter'length);
--taps = 31, 29, 25, 24
lfsr32(lfsr32'left-1 downto 0) <= lfsr32(lfsr32'left downto 1);
lfsr32(lfsr32'left) <= lfsr32(0);
lfsr32(lfsr32'left-2) <= lfsr32(lfsr32'left-1) xor lfsr32(0);
lfsr32(lfsr32'left-6) <= lfsr32(lfsr32'left-5) xor lfsr32(0);
lfsr32(lfsr32'left-8) <= lfsr32(lfsr32'left-7) xor lfsr32(0);
delay_channel <= (others => '1');
for ichannel in MAX_READY_VALID_PAIRS-1 downto 0 loop
if random_delay(ichannel) = '1' then
if (lfsr32(DELAY_MASK_BITS-1 downto 0) and delay_mask(ichannel)) = DONT_DELAY then
delay_channel(ichannel) <= '0';
end if;
else
if (std_logic_vector(counter) and delay_mask(ichannel)) = DONT_DELAY then
delay_channel(ichannel) <= '0';
end if;
end if;
--Illegal to deassert valid in mid-transaction
if valid_out(ichannel) = '1' and ready_in(ichannel) = '0' then
delay_channel(ichannel) <= '0';
end if;
end loop; -- ichannel
if S_AXI_ARESETN = '0' then
counter <= to_unsigned(0, counter'length);
lfsr32 <= (others => '1');
end if;
end if;
end process;
channel_gen : for gchannel in MAX_READY_VALID_PAIRS-1 downto 0 generate
valid_out(gchannel) <= valid_in(gchannel) and (not delay_channel(gchannel));
ready_out(gchannel) <= ready_in(gchannel) and (not delay_channel(gchannel));
end generate channel_gen;
valid_in(0) <= valid0_in;
ready_in(0) <= ready0_in;
valid0_out <= valid_out(0);
ready0_out <= ready_out(0);
valid_in(1) <= valid1_in;
ready_in(1) <= ready1_in;
valid1_out <= valid_out(1);
ready1_out <= ready_out(1);
valid_in(2) <= valid2_in;
ready_in(2) <= ready2_in;
valid2_out <= valid_out(2);
ready2_out <= ready_out(2);
valid_in(3) <= valid3_in;
ready_in(3) <= ready3_in;
valid3_out <= valid_out(3);
ready3_out <= ready_out(3);
valid_in(4) <= valid4_in;
ready_in(4) <= ready4_in;
valid4_out <= valid_out(4);
ready4_out <= ready_out(4);
valid_in(5) <= valid5_in;
ready_in(5) <= ready5_in;
valid5_out <= valid_out(5);
ready5_out <= ready_out(5);
valid_in(6) <= valid6_in;
ready_in(6) <= ready6_in;
valid6_out <= valid_out(6);
ready6_out <= ready_out(6);
valid_in(7) <= valid7_in;
ready_in(7) <= ready7_in;
valid7_out <= valid_out(7);
ready7_out <= ready_out(7);
end rtl;
|
bsd-3-clause
|
b7e82932b967910e6602b48c17da7216
| 0.59806 | 3 | false | false | false | false |
rodrigosurita/new-crpuf
|
vhdl/src/resources.vhd
| 1 | 950 |
library ieee;
use ieee.std_logic_1164.all;
PACKAGE resources IS
constant base_tempo : time:= 100 ns ;--500; --individuos
constant matriz_i : natural := 3 ; -- linhas (impar)
constant matriz_j : natural := 3 ; -- colunas
constant number_of_vector: integer:= 16 ;--500; --quantidade de estimulos
constant individuos: integer:= 1000 ;--500; --individuos
constant response_file_rpuf1: string := "./data/PUF_Response/CRPUF1_response_PUF_"&integer'image(matriz_i)&"x"&integer'image(matriz_j)&"_bits_"&integer'image(individuos)&"_pufs.txt";
constant response_file_rpuf2: string := "./data/PUF_Response/CRPUF2_response_PUF_"&integer'image(matriz_i)&"x"&integer'image(matriz_j)&"_bits_"&integer'image(individuos)&"_pufs.txt";
constant response_file_raw: string := "./data/PUF_Response/RAW_response_PUF_"&integer'image(matriz_i)&"x"&integer'image(matriz_j)&"_bits_"&integer'image(individuos)&"_pufs.txt";
END resources;
|
gpl-2.0
|
296313a12abd26a48746f1894e5484f1
| 0.697895 | 3.220339 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-multicore2/pll2.vhd
| 2 | 16,200 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll2.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll2 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END pll2;
ARCHITECTURE SYN OF pll2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 125,
clk0_duty_cycle => 50,
clk0_multiply_by => 63,
clk0_phase_shift => "0",
clk1_divide_by => 25,
clk1_duty_cycle => 50,
clk1_multiply_by => 63,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll2",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.200001"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "126.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "126.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "63"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
230dd48f8359a2e8e7d60de087902dfc
| 0.700247 | 3.328539 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/col_mach.vhd
| 1 | 25,407 |
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 00:53:18
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/controller/col_mach.v
-- Component name : col_mach
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
library UNISIM;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use UNISIM.VCOMPONENTS.all;
-- The column machine manages the dq bus. Since there is a single DQ
-- bus, and the column part of the DRAM is tightly coupled to this DQ
-- bus, conceptually, the DQ bus and all of the column hardware in
-- a multi rank DRAM array are managed as a single unit.
--
--
-- The column machine does not "enforce" the column timing directly.
-- It generates information and sends it to the bank machines. If the
-- bank machines incorrectly make a request, the column machine will
-- simply overwrite the existing request with the new request even
-- if this would result in a timing or protocol violation.
--
-- The column machine
-- hosts the block that controls read and write data transfer
-- to and from the dq bus.
--
-- And if configured, there is provision for tracking the address
-- of a command as it moves through the column pipeline. This
-- address will be logged for detected ECC errors.
entity col_mach is
generic (
TCQ : integer := 100;
BANK_WIDTH : integer := 3;
BURST_MODE : string := "8";
COL_WIDTH : integer := 12;
CS_WIDTH : integer := 4;
DATA_BUF_ADDR_WIDTH : integer := 8;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DELAY_WR_DATA_CNTRL : integer := 0;
DQS_WIDTH : integer := 8;
DRAM_TYPE : string := "DDR3";
EARLY_WR_DATA_ADDR : string := "OFF";
ECC : string := "OFF";
MC_ERR_ADDR_WIDTH : integer := 31;
nCK_PER_CLK : integer := 2;
nPHY_WRLAT : integer := 0;
nRD_EN2CNFG_WR : integer := 6;
nWR_EN2CNFG_RD : integer := 4;
nWR_EN2CNFG_WR : integer := 4;
RANK_WIDTH : integer := 2;
ROW_WIDTH : integer := 16
);
port (
-- Outputs
-- Inputs
dq_busy_data : out std_logic; -- = 1'b0;
-- The following generates a column command disable based mostly on the type
-- of DRAM and the fabric to DRAM CK ratio.
-- This generates a data offset based on fabric clock to DRAM CK ratio and
-- the size bit. Note that this is different that the dq_busy_data signal
-- generated above.
wr_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
dfi_wrdata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
wr_data_en : out std_logic;
wr_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_en : out std_logic_vector(DQS_WIDTH - 1 downto 0);
inhbt_wr_config : out std_logic;
inhbt_rd_config : out std_logic;
rd_rmw : out std_logic;
ecc_err_addr : out std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
ecc_status_valid : out std_logic;
wr_ecc_buf : out std_logic;
rd_data_end : out std_logic;
rd_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rd_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
rd_data_en : out std_logic;
clk : in std_logic;
rst : in std_logic;
sent_col : in std_logic;
col_size : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
col_wr_data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
dfi_rddata_valid : in std_logic;
col_periodic_rd : in std_logic;
col_data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col_rmw : in std_logic;
col_ra : in std_logic_vector(RANK_WIDTH - 1 downto 0);
col_ba : in std_logic_vector(BANK_WIDTH - 1 downto 0);
col_row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
col_a : in std_logic_vector(ROW_WIDTH - 1 downto 0)
);
end entity col_mach;
architecture trans of col_mach is
component RAM32M
generic (
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
DOC : out std_logic_vector (1 downto 0);
DOD : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector(4 downto 0);
ADDRB : in std_logic_vector(4 downto 0);
ADDRC : in std_logic_vector(4 downto 0);
ADDRD : in std_logic_vector(4 downto 0);
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
DIC : in std_logic_vector (1 downto 0);
DID : in std_logic_vector (1 downto 0);
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
function nCOPY (A : in std_logic; B : in integer) return std_logic_vector is
variable tmp : std_logic_vector(B - 1 downto 0);
begin
for i in 0 to B - 1 loop
tmp(i) := A;
end loop;
return tmp;
end function nCOPY;
function clogb2(size: integer) return integer is
variable tmp : integer := 1;
variable tmp_size : std_logic_vector (31 downto 0);
begin
tmp_size := std_logic_vector(TO_UNSIGNED((size - 1),32));
while ( to_integer(UNSIGNED(tmp_size)) > 1 ) loop
tmp_size := std_logic_vector(UNSIGNED(tmp_size) srl 1);
tmp := tmp + 1;
end loop;
return tmp;
--for i in 23 downto 0 loop
-- if( size <= 2** i) then
-- tmp := i;
-- end if;
--end loop;
--return tmp;
end function clogb2;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
function f_FIFO_WIDTH (DATA_BUF_ADDR_WIDTH: integer; DATA_BUF_OFFSET_WIDTH : integer ;MC_ERR_LINE_WIDTH : integer; ECC : string)
return integer is
begin
if (ECC = "OFF") then
return ( 1 + 1 + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH );
else
return (1 + 1 + DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + 1 + MC_ERR_LINE_WIDTH);
end if;
end function f_FIFO_WIDTH;
function f_RAM_CNT (FULL_RAM_CNT: integer; REMAINDER : integer )
return integer is
begin
if (REMAINDER = 0) then
return ( FULL_RAM_CNT );
else
return ( FULL_RAM_CNT + 1);
end if;
end function f_RAM_CNT;
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
constant ONE : integer := 1;
constant nRD_EN2CNFG_WR_LOCAL : integer := nRD_EN2CNFG_WR - 2;
constant nWR_EN2CNFG_WR_LOCAL : integer := nWR_EN2CNFG_WR - 2;
constant WR_WAIT_CNT_WIDTH : integer := clogb2(nRD_EN2CNFG_WR_LOCAL + 1);
constant nWR_EN2CNFG_RD_LOCAL : integer := nWR_EN2CNFG_RD - 2;
constant RD_WAIT_CNT_WIDTH : integer := clogb2(nWR_EN2CNFG_RD_LOCAL + 1);
constant MC_ERR_LINE_WIDTH : integer := MC_ERR_ADDR_WIDTH - DATA_BUF_OFFSET_WIDTH;
constant FIFO_WIDTH : integer := f_FIFO_WIDTH(DATA_BUF_ADDR_WIDTH ,DATA_BUF_OFFSET_WIDTH ,MC_ERR_LINE_WIDTH,ECC );
constant FULL_RAM_CNT : integer := (FIFO_WIDTH / 6);
constant REMAINDER : integer := FIFO_WIDTH mod 6;
constant RAM_CNT : integer := f_RAM_CNT(FULL_RAM_CNT ,REMAINDER ) ;
constant RAM_WIDTH : integer := (RAM_CNT * 6);
signal ecc_err_addr_ns : std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
signal offset_r : std_logic_vector(1 downto 0) := "00";
signal offset_ns : std_logic_vector(1 downto 0) := "00";
signal data_end : std_logic;
signal offset_r1 : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0) := (others => '0' );
signal sent_col_r1 : std_logic;
signal wrdata_en : std_logic;
signal read_data_valid : std_logic;
signal cnfg_wr_wait_r : std_logic_vector(WR_WAIT_CNT_WIDTH - 1 downto 0);
signal cnfg_wr_wait_ns : std_logic_vector(WR_WAIT_CNT_WIDTH - 1 downto 0);
signal cnfg_rd_wait_r : std_logic_vector(RD_WAIT_CNT_WIDTH - 1 downto 0);
signal cnfg_rd_wait_ns : std_logic_vector(RD_WAIT_CNT_WIDTH - 1 downto 0);
signal inhbt_wr_config_ns : std_logic;
signal inhbt_wr_config_r : std_logic;
signal inhbt_rd_config_ns : std_logic;
signal inhbt_rd_config_r : std_logic;
signal col_a_full : std_logic_vector(11 downto 0);
signal col_a_extracted : std_logic_vector(COL_WIDTH - 1 downto 0);
signal granted_col_d_r : std_logic_vector(1 downto 0);
signal granted_col_d_ns : std_logic_vector(1 downto 0);
signal col_wr_data_buf_addr_r : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal ecc_line : std_logic_vector(MC_ERR_LINE_WIDTH downto 0);
signal rd_data_en_ns : std_logic;
signal real_fifo_data : std_logic_vector(FIFO_WIDTH - 1 downto 0);
signal fifo_in_data : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_in_data_r : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_out_data : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_out_data_ns : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal fifo_out_data_r : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal rd_data_end_ns : std_logic;
signal periodic_rd : std_logic;
signal rd_data_addr_ns : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal rd_data_offset_ns : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
signal ecc_status_valid_ns : std_logic;
signal wr_ecc_buf_ns : std_logic;
signal head_ns,head_r : std_logic_vector(4 downto 0);
signal head_r1 : std_logic_vector(4 downto 0);
signal tail_ns,tail_r : std_logic_vector(4 downto 0);
signal int8 : std_logic;
-- Declare intermediate signals for referenced outputs
signal rd_rmw_int3 : std_logic;
signal rd_data_end_int1 : std_logic;
signal rd_data_addr_int0 : std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
signal rd_data_offset_int2 : std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
--this signal is defined to initialize the dq_busy_data with a value of 0. for conditions where none of the generate block is triggered.
signal dq_busy_data_temp : std_logic := '0';
begin
-- Drive referenced outputs
rd_rmw <= rd_rmw_int3;
rd_data_end <= rd_data_end_int1;
rd_data_addr <= rd_data_addr_int0;
rd_data_offset <= rd_data_offset_int2;
dq_busy_data <= dq_busy_data_temp ;
int4 : if ((nCK_PER_CLK = 1) and ((BURST_MODE = "8") or (DRAM_TYPE = "DDR3"))) generate
granted_col_d_ns <= (sent_col & granted_col_d_r(1));
process (clk)
begin
if (clk'event and clk = '1') then
granted_col_d_r <= granted_col_d_ns after (TCQ)*1 ps;
end if;
end process;
process (granted_col_d_r, sent_col)
begin
dq_busy_data_temp <= sent_col or REDUCTION_OR(granted_col_d_r);
end process;
end generate;
int5 : if (((nCK_PER_CLK = 2) and ((BURST_MODE = "8") or (DRAM_TYPE = "DDR3"))) or ((nCK_PER_CLK = 1) and ((BURST_MODE = "4") or (DRAM_TYPE = "DDR2")))) generate
process (sent_col)
begin
dq_busy_data_temp <= sent_col;
end process;
end generate;
data_valid_1_1 : if (DATA_BUF_OFFSET_WIDTH = 2) generate
process (col_size, offset_r, rst, sent_col)
begin
if (rst = '1') then
offset_ns <= (others => '0');
else
offset_ns <= offset_r;
if (sent_col = '1') then
offset_ns <= "01";
elsif ((REDUCTION_OR(offset_r)) = '1' and (offset_r /= (col_size & '1'))) then
offset_ns <= offset_r + '1';
else
offset_ns <= "00";
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
offset_r <= offset_ns after (TCQ)*1 ps;
end if;
end process;
data_end <= BOOLEAN_TO_STD_LOGIC(offset_r = "11") when (col_size = '1') else
offset_r(0);
end generate;
--
data_valid_2_1 : if (not(DATA_BUF_OFFSET_WIDTH = 2)) generate
-- int8 <= '0' when (rst = '1') else
-- sent_col and col_size;
process (col_size, rst, sent_col)
begin
if (rst = '1') then
offset_ns(0) <= '0';
else
offset_ns(0) <= sent_col and col_size;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
offset_r(0) <= offset_ns(0) after (TCQ)*1 ps;
end if;
end process;
data_end <= offset_r(0) when (col_size = '1') else
'1';
end generate;
offset_pipe : if ((nPHY_WRLAT = 1) or (DELAY_WR_DATA_CNTRL = 1)) generate
process (clk)
begin
if (clk'event and clk = '1') then
offset_r1 <= offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0) after (TCQ)*1 ps;
end if;
end process;
end generate;
wr_data_offset <= offset_r1(DATA_BUF_OFFSET_WIDTH - 1 downto 0) when (DELAY_WR_DATA_CNTRL = 1) else
offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0) when (EARLY_WR_DATA_ADDR = "OFF") else
offset_ns(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
process (clk)
begin
if (clk'event and clk = '1') then
sent_col_r1 <= sent_col after (TCQ)*1 ps;
end if;
end process;
wrdata_en <= ((sent_col or REDUCTION_OR(offset_r)) and io_config(RANK_WIDTH)) when (nPHY_WRLAT = 0) else
((sent_col_r1 or REDUCTION_OR(offset_r1)) and io_config(RANK_WIDTH));
dfi_wrdata_en <= nCOPY(wrdata_en,DQS_WIDTH);
-- BAD
wr_data_en <= ((sent_col_r1 or REDUCTION_OR(offset_r1)) and io_config(RANK_WIDTH)) when (DELAY_WR_DATA_CNTRL = 1) else
((sent_col or REDUCTION_OR(offset_r)) and io_config(RANK_WIDTH));
delay_wr_data_cntrl_eq_1 : if (DELAY_WR_DATA_CNTRL = 1) generate
process (clk)
begin
if (clk'event and clk = '1') then
col_wr_data_buf_addr_r <= col_wr_data_buf_addr after (TCQ)*1 ps;
end if;
end process;
wr_data_addr <= col_wr_data_buf_addr_r;
end generate;
int11 : if (not(DELAY_WR_DATA_CNTRL = 1)) generate
wr_data_addr <= col_wr_data_buf_addr;
end generate;
read_data_valid <= (sent_col or REDUCTION_OR(offset_r)) and not(io_config(RANK_WIDTH));
process (read_data_valid)
begin
for i in dfi_rddata_en'range loop
dfi_rddata_en(i) <= read_data_valid;
end loop;
end process;
process (cnfg_wr_wait_r, read_data_valid, rst, wrdata_en)
variable cnfg_wr_wait_ns_tmp : std_logic_vector(WR_WAIT_CNT_WIDTH - 1 downto 0);
begin
if (rst = '1') then
cnfg_wr_wait_ns_tmp := (others => '0' );
else
cnfg_wr_wait_ns_tmp := cnfg_wr_wait_r;
if (wrdata_en = '1') then
cnfg_wr_wait_ns_tmp := std_logic_vector(TO_UNSIGNED(nWR_EN2CNFG_WR_LOCAL, WR_WAIT_CNT_WIDTH));
elsif (read_data_valid = '1') then
cnfg_wr_wait_ns_tmp := std_logic_vector(TO_UNSIGNED(nRD_EN2CNFG_WR_LOCAL, WR_WAIT_CNT_WIDTH));
elsif ((REDUCTION_OR(cnfg_wr_wait_r)) = '1') then
cnfg_wr_wait_ns_tmp := cnfg_wr_wait_r - '1';
end if;
end if;
cnfg_wr_wait_ns <= cnfg_wr_wait_ns_tmp;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
cnfg_wr_wait_r <= cnfg_wr_wait_ns after (TCQ)*1 ps;
end if;
end process;
process (cnfg_rd_wait_r, rst, wrdata_en)
variable cnfg_rd_wait_ns_tmp : std_logic_vector(RD_WAIT_CNT_WIDTH - 1 downto 0);
begin
if (rst = '1') then
cnfg_rd_wait_ns_tmp := (others => '0' );
else
cnfg_rd_wait_ns_tmp := cnfg_rd_wait_r;
if (wrdata_en = '1') then
cnfg_rd_wait_ns_tmp := std_logic_vector(TO_UNSIGNED(nWR_EN2CNFG_RD_LOCAL, RD_WAIT_CNT_WIDTH));
elsif ((REDUCTION_OR(cnfg_rd_wait_r)) = '1') then
cnfg_rd_wait_ns_tmp := cnfg_rd_wait_r - '1';
end if;
end if;
cnfg_rd_wait_ns <= cnfg_rd_wait_ns_tmp;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
cnfg_rd_wait_r <= cnfg_rd_wait_ns after (TCQ)*1 ps;
end if;
end process;
inhbt_wr_config_ns <= BOOLEAN_TO_STD_LOGIC(cnfg_wr_wait_ns /= nCOPY('0', WR_WAIT_CNT_WIDTH));
process (clk)
begin
if (clk'event and clk = '1') then
inhbt_wr_config_r <= inhbt_wr_config_ns after (TCQ)*1 ps;
end if;
end process;
inhbt_wr_config <= sent_col or wrdata_en or inhbt_wr_config_r;
inhbt_rd_config_ns <= BOOLEAN_TO_STD_LOGIC(cnfg_rd_wait_ns /= nCOPY('0',RD_WAIT_CNT_WIDTH));
process (clk)
begin
if (clk'event and clk = '1') then
inhbt_rd_config_r <= inhbt_rd_config_ns after (TCQ)*1 ps;
end if;
end process;
inhbt_rd_config <= sent_col or wrdata_en or inhbt_rd_config_r;
COL_SEL_0_13 : if ( ROW_WIDTH <= 13 ) generate
col_a_full <= ('0' & col_a(11) & col_a(9 downto 0));
end generate;
COL_SEL : if ( ROW_WIDTH > 13 ) generate
col_a_full <= (col_a(13) & col_a(11) & col_a(9 downto 0));
end generate;
col_a_extracted <= col_a_full(COL_WIDTH - 1 downto 0);
int12 : if (CS_WIDTH = 1) generate
ecc_line <= (col_rmw & col_ba & col_row & col_a_extracted);
end generate;
int13 : if (not(CS_WIDTH = 1)) generate
ecc_line <= (col_rmw & col_ra & col_ba & col_row & col_a_extracted);
end generate;
int14 : if (ECC = "OFF") generate
real_fifo_data <= (data_end & col_periodic_rd & col_data_buf_addr & offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0));
end generate;
int15 : if (not(ECC = "OFF")) generate
real_fifo_data <= (data_end & col_periodic_rd & col_data_buf_addr & offset_r(DATA_BUF_OFFSET_WIDTH - 1 downto 0) & ecc_line);
end generate;
int16 : if (REMAINDER = 0) generate
fifo_in_data <= ( real_fifo_data);
end generate;
int17 : if (not(REMAINDER = 0)) generate
fifo_in_data <= nCOPY('0',6-REMAINDER) & real_fifo_data;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
fifo_in_data_r <= fifo_in_data after (TCQ)*1 ps;
end if;
end process;
head_ns <= (others => '0' ) when (rst = '1') else
(head_r + "00001") when (read_data_valid = '1') else
head_r;
process (clk)
begin
if (clk'event and clk = '1') then
head_r <= head_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
head_r1 <= head_r after (TCQ)*1 ps;
end if;
end process;
tail_ns <= (others => '0' ) when (rst = '1') else
(tail_r + "00001") when (dfi_rddata_valid = '1') else
tail_r;
process (clk)
begin
if (clk'event and clk = '1') then
tail_r <= tail_ns after (TCQ)*1 ps;
end if;
end process;
fifo_ram : for i in 0 to RAM_CNT - 1 generate
RAM32M0 : RAM32M
generic map (
init_a => "0000000000000000000000000000000000000000000000000000000000000000",
init_b => "0000000000000000000000000000000000000000000000000000000000000000",
init_c => "0000000000000000000000000000000000000000000000000000000000000000",
init_d => "0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
doa => fifo_out_data_ns((i * 6) + 6 - 1 downto (i * 6) + 4),
dob => fifo_out_data_ns((i * 6) + 4 - 1 downto (i * 6) + 2),
doc => fifo_out_data_ns((i * 6) + 2 - 1 downto (i * 6) + 0),
dod => open,
dia => fifo_in_data_r((i * 6) + 6 - 1 downto (i * 6) + 4),
dib => fifo_in_data_r((i * 6) + 4 - 1 downto (i * 6) + 2),
dic => fifo_in_data_r((i * 6) + 2 - 1 downto (i * 6) + 0),
did => "00",
addra => tail_ns,
addrb => tail_ns,
addrc => tail_ns,
addrd => head_r1,
we => '1',
wclk => clk
);
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
fifo_out_data_r <= fifo_out_data_ns after (TCQ)*1 ps;
end if;
end process;
-- When ECC is ON, most of the FIFO output is delayed
-- by one state.
int18 : if (ECC = "OFF") generate
process (dfi_rddata_valid, fifo_out_data_r,periodic_rd)
begin
rd_data_offset_int2 <= fifo_out_data_r(DATA_BUF_OFFSET_WIDTH-1 downto 0);
rd_data_addr_int0 <= fifo_out_data_r(DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH -1 downto DATA_BUF_OFFSET_WIDTH );
periodic_rd <= fifo_out_data_r(DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH );
rd_data_end_int1 <= fifo_out_data_r(DATA_BUF_ADDR_WIDTH + DATA_BUF_OFFSET_WIDTH + 1 );
ecc_err_addr <= (others => '0' );
rd_data_en <= dfi_rddata_valid and not(periodic_rd);
ecc_status_valid <= '0';
wr_ecc_buf <= '0';
end process;
rd_rmw_int3 <= '0';
end generate;
int19 : if (not(ECC = "OFF")) generate
rd_data_end_ns <= fifo_out_data_r( DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + DATA_BUF_ADDR_WIDTH + 2);
periodic_rd <= fifo_out_data_r( DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + DATA_BUF_ADDR_WIDTH + 1);
rd_data_addr_ns <= fifo_out_data_r( DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + DATA_BUF_ADDR_WIDTH downto DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH + 1);
rd_data_offset_ns <= fifo_out_data_r(DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH downto MC_ERR_LINE_WIDTH + 1);
rd_rmw_int3 <= fifo_out_data_r(MC_ERR_LINE_WIDTH);
ecc_err_addr_ns(DATA_BUF_OFFSET_WIDTH + MC_ERR_LINE_WIDTH - 1 downto DATA_BUF_OFFSET_WIDTH) <= fifo_out_data_r(MC_ERR_LINE_WIDTH - 1 downto 0);
ecc_err_addr_ns(DATA_BUF_OFFSET_WIDTH - 1 downto 0) <= rd_data_offset_ns;
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_end_int1 <= rd_data_end_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_addr_int0 <= rd_data_addr_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_offset_int2 <= rd_data_offset_ns after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
ecc_err_addr <= ecc_err_addr_ns after (TCQ)*1 ps;
end if;
end process;
rd_data_en_ns <= dfi_rddata_valid and not((periodic_rd or rd_rmw_int3));
process (clk)
begin
if (clk'event and clk = '1') then
rd_data_en <= rd_data_en_ns;
end if;
end process;
ecc_status_valid_ns <= dfi_rddata_valid and not(periodic_rd);
process (clk)
begin
if (clk'event and clk = '1') then
ecc_status_valid <= ecc_status_valid_ns after (TCQ)*1 ps;
end if;
end process;
wr_ecc_buf_ns <= dfi_rddata_valid and not(periodic_rd) and rd_rmw_int3;
process (clk)
begin
if (clk'event and clk = '1') then
wr_ecc_buf <= wr_ecc_buf_ns after (TCQ)*1 ps;
end if;
end process;
end generate;
end architecture trans;
|
lgpl-3.0
|
b153bd1ff263f18cebed75c3b19d747e
| 0.55528 | 3.330319 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_control_io.vhd
| 1 | 55,739 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Application: MIG
-- \ \ Filename: phy_control_io.vhd
-- / / Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- /___/ /\ Date Created: Aug 03 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Instantiates IOB blocks for output-only control/address signals to DRAM.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_control_io.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_control_io.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_control_io is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
BANK_WIDTH : integer := 2; -- # of bank bits
RANK_WIDTH : integer := 1; -- log2(CS_WIDTH)
nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
CS_WIDTH : integer := 1; -- # of DRAM ranks
CKE_WIDTH : integer := 1; -- # of DRAM ranks
ROW_WIDTH : integer := 14; -- DRAM address bus width
WRLVL : string := "OFF"; -- Enable write leveling
nCWL : integer := 5; -- Write Latency
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
REG_CTRL : string := "ON"; -- "ON" for registered DIMM
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG"; -- May be assigned unique name
-- when mult IP cores in design
DDR2_EARLY_CS : integer := 0 -- set = 1 for >200 MHz DDR2 UDIMM designs
-- for early launch of CS
);
port (
clk_mem : in std_logic;-- full rate core clock
clk : in std_logic;-- half rate core clock
rst : in std_logic;-- half rate core clk reset
mc_data_sel : in std_logic;-- =1 for MC control, =0 for PHY
dfi_address0 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_address1 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
dfi_bank0 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_bank1 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
dfi_cas_n0 : in std_logic;
dfi_cas_n1 : in std_logic;
dfi_cke0 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
dfi_cke1 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
dfi_cs_n0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_cs_n1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_odt0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_odt1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
dfi_ras_n0 : in std_logic;
dfi_ras_n1 : in std_logic;
dfi_reset_n : in std_logic;
dfi_we_n0 : in std_logic;
dfi_we_n1 : in std_logic;
-- DFI address/control
phy_address0 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_address1 : in std_logic_vector(ROW_WIDTH - 1 downto 0);
phy_bank0 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_bank1 : in std_logic_vector(BANK_WIDTH - 1 downto 0);
phy_cas_n0 : in std_logic;
phy_cas_n1 : in std_logic;
phy_cke0 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cke1 : in std_logic_vector(CKE_WIDTH - 1 downto 0);
phy_cs_n0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_cs_n1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_odt0 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_odt1 : in std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
phy_ras_n0 : in std_logic;
phy_ras_n1 : in std_logic;
phy_reset_n : in std_logic;
phy_we_n0 : in std_logic;
phy_we_n1 : in std_logic;
-- DDR3-side address/control
ddr_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH - 1 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_cke : out std_logic_vector(CKE_WIDTH - 1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_odt : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_parity : out std_logic;
ddr_reset_n : out std_logic
);
end phy_control_io;
architecture arch_phy_control_io of phy_control_io is
function CALC_SINGLE_RANK_CS return integer is
begin
if ((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (CS_WIDTH = 1) and (nCS_PER_RANK = 2)) then
return 1;
else
return 0;
end if;
end function CALC_SINGLE_RANK_CS;
function CALC_HIGH_PERFORMANCE_MODE return boolean is
begin
if (IODELAY_HP_MODE = "OFF") then
return FALSE;
else
return TRUE;
end if;
end function CALC_HIGH_PERFORMANCE_MODE;
function XOR_BR (val : std_logic_vector) return std_logic is
variable rtn : std_logic := '0';
begin
for index in val'range loop
rtn := rtn xor val(index);
end loop;
return(rtn);
end function XOR_BR;
-- Set performance mode for IODELAY (power vs. performance tradeoff)
-- COMMENTED, 022009, RICHC. This is temporary pending IR 509123
constant HIGH_PERFORMANCE_MODE : boolean := CALC_HIGH_PERFORMANCE_MODE;
-- local parameter for the single rank DDR3 dimm case. This parameter will be
-- set when the number of chip selects is == 2 for a single rank registered
-- dimm.
constant SINGLE_RANK_CS_REG : integer := CALC_SINGLE_RANK_CS;
signal mux_addr0 : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal mux_addr1 : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal mux_ba0 : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal mux_ba1 : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal mux_cas_n0 : std_logic;
signal mux_cas_n1 : std_logic;
signal mux_cke0 : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal mux_cke1 : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal mux_cs_n0 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_n1 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d1 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d2 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d3 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_cs_d4 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_ioconfig : std_logic_vector(0 downto 0);
signal mux_ioconfig_en : std_logic;
signal mux_odt0 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_odt1 : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal mux_ras_n0 : std_logic;
signal mux_ras_n1 : std_logic;
signal mux_reset_n : std_logic;
signal mux_we_n0 : std_logic;
signal mux_we_n1 : std_logic;
signal oce_temp : std_logic;
signal parity0 : std_logic;
signal parity1 : std_logic;
signal rst_delayed : std_logic_vector(3 downto 0);
signal addr_odelay : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal addr_oq : std_logic_vector(ROW_WIDTH - 1 downto 0);
signal ba_odelay : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal ba_oq : std_logic_vector(BANK_WIDTH - 1 downto 0);
signal cas_n_odelay : std_logic;
signal cas_n_oq : std_logic;
signal cke_odelay : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal cke_oq : std_logic_vector(CKE_WIDTH - 1 downto 0);
signal cs_n_odelay : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal cs_n_oq : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal odt_odelay : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal odt_oq : std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
signal parity_odelay : std_logic;
signal parity_oq : std_logic;
signal reset_n_oq : std_logic;
signal ras_n_odelay : std_logic;
signal ras_n_oq : std_logic;
signal rst_cke_odt : std_logic;
signal rst_r : std_logic;
signal oce_hack_r : std_logic;
signal oce_hack_r1 : std_logic;
signal oce_hack_r2 : std_logic;
signal oce_hack_r3 : std_logic;
signal oce_hack_r4 : std_logic;
signal oce_hack_r5 : std_logic;
-- synthesis syn_keep = 1
signal we_n_odelay : std_logic;
signal we_n_oq : std_logic;
attribute IODELAY_GROUP : string;
begin
-- XST attributes for local reset tree RST_R - prohibit equivalent
-- register removal on RST_R to prevent "sharing" w/ other local reset trees
-- synthesis attribute shreg_extract of rst_r is "no";
-- synthesis attribute equivalent_register_removal of rst_r is "no"
--***************************************************************************
-- Reset pipelining - register reset signals to prevent large (and long)
-- fanouts during physical compilation of the design. Create one local reset
-- for most control/address OSERDES blocks - note that user may need to
-- change this if control/address are more "spread out" through FPGA
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
rst_r <= rst after (TCQ)*1 ps;
end if;
end process;
--***************************************************************************
-- Generate delayed version of global reset.
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
rst_delayed(0) <= rst after (TCQ)*1 ps;
rst_delayed(1) <= rst_delayed(0) after (TCQ)*1 ps;
rst_delayed(2) <= rst_delayed(1) after (TCQ)*1 ps;
rst_delayed(3) <= rst_delayed(2) after (TCQ)*1 ps;
end if;
end process;
-- Drive ODT and CKE OSERDES with these resets in order to ensure that
-- they remain low until after DDR_RESET_N is deasserted. This is done for
-- simulation reasons only, as some memory models will issue an error if
-- ODT/CKE are asserted prior to deassertion of RESET_N
rst_cke_odt <= rst_delayed(3);
--***************************************************************************
-- The following logic is only required to support DDR2 simulation, and is
-- done to prevent glitching on the ODT and CKE signals after "power-up".
-- Certain models will flag glitches on these lines as errors.
-- To fix this, the OCE for OSERDES is used to prevent glitches. However,
-- this may lead to setup time issues when running this design through
-- ISE - because the OCE setup is w/r/t to CLK (i.e. the "fast" clock).
-- It can be problematic to meet timing - therefore this path should be
-- marked as a false path (TIG) because it will be asserted long before
-- the OSERDES outputs need to be valid. This logic is disabled for the
-- DDR3 case because it is not required
-- LOGIC DESCRIPTION:
-- Generating OCE for DDR2 ODT & CKE. The output of the OSERDES model toggles
-- when it comes out of reset. This causes issues in simulation. Controlling
-- it OCE until there is a library fix. OCE will be asserted after 10 clks
-- after reset de-assertion
process (clk)
begin
if (clk'event and clk = '1') then
oce_hack_r <= not(rst_delayed(3)) after TCQ*1 ps;
oce_hack_r1 <= oce_hack_r after TCQ*1 ps;
oce_hack_r2 <= oce_hack_r1 after TCQ*1 ps;
oce_hack_r3 <= oce_hack_r2 after TCQ*1 ps;
oce_hack_r4 <= oce_hack_r3 after TCQ*1 ps;
oce_hack_r5 <= oce_hack_r4 after TCQ*1 ps;
end if;
end process;
-- Only use for DDR2. For DDR3, drive to constant high
oce_temp <= oce_hack_r5 when (DRAM_TYPE = "DDR2") else
'1';
--***************************************************************************
-- MUX to choose from either PHY or controller for DRAM control
-- NOTE: May need to add pipeline register to meet timing
--***************************************************************************
mux_addr0 <= dfi_address0 when (mc_data_sel = '1') else
phy_address0;
mux_addr1 <= dfi_address1 when (mc_data_sel = '1') else
phy_address1;
mux_ba0 <= dfi_bank0 when (mc_data_sel = '1') else
phy_bank0;
mux_ba1 <= dfi_bank1 when (mc_data_sel = '1') else
phy_bank1;
mux_cas_n0 <= dfi_cas_n0 when (mc_data_sel = '1') else
phy_cas_n0;
mux_cas_n1 <= dfi_cas_n1 when (mc_data_sel = '1') else
phy_cas_n1;
mux_cke0 <= dfi_cke0 when (mc_data_sel = '1') else
phy_cke0;
mux_cke1 <= dfi_cke1 when (mc_data_sel = '1') else
phy_cke1;
mux_odt0 <= dfi_odt0 when (mc_data_sel = '1') else
phy_odt0;
mux_odt1 <= dfi_odt1 when (mc_data_sel = '1') else
phy_odt1;
mux_ras_n0 <= dfi_ras_n0 when (mc_data_sel = '1') else
phy_ras_n0;
mux_ras_n1 <= dfi_ras_n1 when (mc_data_sel = '1') else
phy_ras_n1;
mux_reset_n <= dfi_reset_n when (mc_data_sel = '1') else
phy_reset_n;
mux_we_n0 <= dfi_we_n0 when (mc_data_sel = '1') else
phy_we_n0;
mux_we_n1 <= dfi_we_n1 when (mc_data_sel = '1') else
phy_we_n1;
--***************************************************************************
-- assigning chip select values.
-- For DDR3 Registered dimm's the chip select pins are toggled in a unique
-- way to differentiate between register programming and regular DIMM access.
-- For a single rank registered dimm with two chip selects the chip select
-- will be toggled in the following manner:
-- cs[0] =0, cs[1] = 0 the access is to the registered chip. On the
-- remaining combinations the access is to the DIMM. The SINGLE_RANK_CS_REG
-- parameter will be set for the above configurations and the chip select
-- pins will be toggled as per the DDR3 registered DIMM requirements. The
-- phy takes care of the register programming, and handles the chip
-- select's correctly for calibration and initialization. But the controller
-- does not know about this mode, the controller cs[1] bits will be tied to
-- 1'b1; All the controller access will be to the DIMM and none to the
-- register chip. Rest of the DDR3 register dimm configurations are
-- handled well by the controller.
--***************************************************************************
gen_single_rank : if (SINGLE_RANK_CS_REG = 1) generate
process (mc_data_sel, dfi_cs_n0(0), dfi_cs_n1(0), phy_cs_n0(0), phy_cs_n1(0), phy_cs_n0(1), phy_cs_n1(1))
begin
if (mc_data_sel = '1') then
mux_cs_n0(0) <= dfi_cs_n0(0);
mux_cs_n1(0) <= dfi_cs_n1(0);
mux_cs_n0(1) <= '1';
mux_cs_n1(1) <= '1';
else
mux_cs_n0(0) <= phy_cs_n0(0);
mux_cs_n1(0) <= phy_cs_n1(0);
mux_cs_n0(1) <= phy_cs_n0(1);
mux_cs_n1(1) <= phy_cs_n1(1);
end if;
end process;
end generate;
gen_mult_rank : if (SINGLE_RANK_CS_REG /= 1) generate
process (mc_data_sel, dfi_cs_n0, dfi_cs_n1, phy_cs_n0, phy_cs_n1)
begin
if (mc_data_sel = '1') then
mux_cs_n0 <= dfi_cs_n0;
mux_cs_n1 <= dfi_cs_n1;
else
mux_cs_n0 <= phy_cs_n0;
mux_cs_n1 <= phy_cs_n1;
end if;
end process;
end generate;
-- for DDR2 UDIMM designs the CS has to be launched early.
-- Setting the OSERDES input based on the DDR2_EARLY_CS parameter.
-- when this paramter is CS will be launched half a cycle early.
-- Launching half a cycle early will cause simulation issues.
-- Using synthesis options to control the assignment
process (mux_cs_n0,mux_cs_n1)
begin
if(DDR2_EARLY_CS = 1) then
mux_cs_d1 <= mux_cs_n0;
mux_cs_d2 <= mux_cs_n1;
mux_cs_d3 <= mux_cs_n1;
mux_cs_d4 <= mux_cs_n0;
else
mux_cs_d1 <= mux_cs_n0;
mux_cs_d2 <= mux_cs_n0;
mux_cs_d3 <= mux_cs_n1;
mux_cs_d4 <= mux_cs_n1;
end if; -- else: !if(DDR2_EARLY_CS == 1)
-- For simulation override the assignment for
-- synthesis do not override
-- synthesis translate_off
mux_cs_d1 <= mux_cs_n0;
mux_cs_d2 <= mux_cs_n0;
mux_cs_d3 <= mux_cs_n1;
mux_cs_d4 <= mux_cs_n1;
-- synthesis translate_on
end process;
-- parity for reg dimm. Have to check the timing impact.
-- Generate only for DDR3 RDIMM.
-- registring with negedge. Half cycle path.
gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
parity0 <= (XOR_BR(mux_addr0 & mux_ba0 & mux_cas_n0 & mux_ras_n0 & mux_we_n0));
process (clk)
begin
if (clk'event and clk = '1') then
parity1 <= (XOR_BR(mux_addr1 & mux_ba1 & mux_cas_n1 & mux_ras_n1 & mux_we_n1)) after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
process (clk)
begin
if (clk'event and clk = '1') then
parity0 <= '0' after (TCQ)*1 ps;
parity1 <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
--*****************************************************************
-- DDR3 reset: Note that this output is generated with an ODDR clocked
-- by the internal div-by-2 clock. It can be generated using the same
-- OSERDES structure as for the other control/address signals. However
-- there are no specific setup/hold requirements on reset_n w/r/t CK.
-- In addition, this an ODDR was used to prevent any glitching on reset_n
-- during startup. This was done for simulation considerations only -
-- the glitch causes warnings with the Denali DDR3 model (but will not
-- cause any issues in hardware).
--*****************************************************************
u_out_reset_n : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
Q => reset_n_oq,
C => clk,
CE => '1',
D1 => mux_reset_n,
D2 => mux_reset_n,
R => rst_r,
S => '0'
);
u_reset_n_obuf : OBUF
port map (
I => reset_n_oq,
O => ddr_reset_n
);
--*****************************************************************
-- Note on generation of Control/Address signals - there are
-- several possible configurations that affect the configuration
-- of the OSERDES and possible ODELAY for each output (this will
-- also affect the CK/CK# outputs as well
-- 1. DDR3, write-leveling: This is the simplest case. Use
-- OSERDES without the ODELAY. Initially clock/control/address
-- will be offset coming out of FPGA from DQ/DQS, but DQ/DQS
-- will be adjusted so that DQS-CK alignment is established
-- 2. DDR2 or DDR3 (no write-leveling): Both DQS and DQ will use
-- ODELAY to delay output of OSERDES. To match this,
-- CK/control/address must also delay their outputs using ODELAY
-- (with delay = 0)
--*****************************************************************
--*****************************************************************
-- RAS: = 1 at reset
--*****************************************************************
gen_ras_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
--*******************************************************
-- CASE1: DDR3, write-leveling
--*******************************************************
u_ras_n_obuf : OBUF
port map (
I => ras_n_oq,
O => ddr_ras_n
);
end generate;
gen_ras_n_nowrlvl: if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_ras_n : label is IODELAY_GRP;
begin
--*******************************************************
-- CASE2: DDR3, no write-leveling
--*******************************************************
u_ras_n_obuf : OBUF
port map (
I => ras_n_odelay,
O => ddr_ras_n
);
u_iodelay_ras_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => ras_n_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => ras_n_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_ras_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => ras_n_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_ras_n0,
D2 => mux_ras_n0,
D3 => mux_ras_n1,
D4 => mux_ras_n1,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
--*******************************************************
-- CAS: = 1 at reset
--*******************************************************
gen_cas_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_cas_n_obuf : OBUF
port map (
I => cas_n_oq,
O => ddr_cas_n
);
end generate;
gen_cas_n_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_cas_n : label is IODELAY_GRP;
begin
u_cas_n_obuf : OBUF
port map (
I => cas_n_odelay,
O => ddr_cas_n
);
u_iodelay_cas_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => cas_n_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => cas_n_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_cas_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => cas_n_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_cas_n0,
D2 => mux_cas_n0,
D3 => mux_cas_n1,
D4 => mux_cas_n1,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
--*******************************************************
-- WE: = 1 at reset
--*******************************************************
gen_we_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_we_n_obuf : OBUF
port map (
I => we_n_oq,
O => ddr_we_n
);
end generate;
gen_we_n_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_we_n : label is IODELAY_GRP;
begin
u_we_n_obuf : OBUF
port map (
I => we_n_odelay,
O => ddr_we_n
);
u_iodelay_we_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => we_n_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => we_n_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_we_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => we_n_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_we_n0,
D2 => mux_we_n0,
D3 => mux_we_n1,
D4 => mux_we_n1,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
--*******************************************************
-- CKE: = 0 at reset
--*******************************************************
gen_cke: for cke_i in 0 to (CKE_WIDTH-1) generate
gen_cke_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_cke_obuf : OBUF
port map (
I => cke_oq(cke_i),
O => ddr_cke(cke_i)
);
end generate;
gen_cke_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_cke : label is IODELAY_GRP;
begin
u_cke_obuf : OBUF
port map (
I => cke_odelay(cke_i),
O => ddr_cke(cke_i)
);
u_iodelay_cke : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => cke_odelay(cke_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => cke_oq(cke_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_cke : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => cke_oq(cke_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_cke0(cke_i),
D2 => mux_cke0(cke_i),
D3 => mux_cke1(cke_i),
D4 => mux_cke1(cke_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => oce_temp,
-- Connect SHIFTIN1, SHIFTIN2 to 0 for simulation purposes
-- (for all other OSERDES used in design, these are no-connects):
-- ensures that CKE outputs are not X at start of simulation
-- Certain DDR2 memory models may require that CK/CK# be valid
-- throughout simulation
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => rst_cke_odt,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*******************************************************
-- chip select = 1 at reset
--*******************************************************
gen_cs_n: for cs_i in 0 to (CS_WIDTH*nCS_PER_RANK - 1) generate
gen_cs_n_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_cs_n_obuf : OBUF
port map (
I => cs_n_oq(cs_i),
O => ddr_cs_n(cs_i)
);
end generate;
gen_cs_n_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_cs_n : label is IODELAY_GRP;
begin
u_cs_n_obuf : OBUF
port map (
I => cs_n_odelay(cs_i),
O => ddr_cs_n(cs_i)
);
u_iodelay_cs_n : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => cs_n_odelay(cs_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => cs_n_oq(cs_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_cs_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => cs_n_oq(cs_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_cs_d1(cs_i),
D2 => mux_cs_d2(cs_i),
D3 => mux_cs_d3(cs_i),
D4 => mux_cs_d4(cs_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*******************************************************
-- address = X at reset
--*******************************************************
gen_addr: for addr_i in 0 to (ROW_WIDTH - 1) generate
gen_addr_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_addr_obuf : OBUF
port map (
I => addr_oq(addr_i),
O => ddr_addr(addr_i)
);
end generate;
gen_addr_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_addr : label is IODELAY_GRP;
begin
u_addr_obuf : OBUF
port map (
I => addr_odelay(addr_i),
O => ddr_addr(addr_i)
);
u_iodelay_addr : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => addr_odelay(addr_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => addr_oq(addr_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_addr : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => addr_oq(addr_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_addr0(addr_i),
D2 => mux_addr0(addr_i),
D3 => mux_addr1(addr_i),
D4 => mux_addr1(addr_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*******************************************************
-- bank address = X at reset
--*******************************************************
gen_ba: for ba_i in 0 to (BANK_WIDTH - 1) generate
gen_ba_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_ba_obuf : OBUF
port map (
I => ba_oq(ba_i),
O => ddr_ba(ba_i)
);
end generate;
gen_ba_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_ba : label is IODELAY_GRP;
begin
u_ba_obuf : OBUF
port map (
I => ba_odelay(ba_i),
O => ddr_ba(ba_i)
);
u_iodelay_ba : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => ba_odelay(ba_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => ba_oq(ba_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_ba : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => ba_oq(ba_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_ba0(ba_i),
D2 => mux_ba0(ba_i),
D3 => mux_ba1(ba_i),
D4 => mux_ba1(ba_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*****************************************************************
-- ODT control = 0 at reset
--*****************************************************************
gen_odt : for odt_i in 0 to (CS_WIDTH*nCS_PER_RANK - 1) generate
gen_odt_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_odt_obuf : OBUF
port map (
I => odt_oq(odt_i),
O => ddr_odt(odt_i)
);
end generate;
gen_odt_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_odt : label is IODELAY_GRP;
begin
u_odt_obuf : OBUF
port map (
I => odt_odelay(odt_i),
O => ddr_odt(odt_i)
);
u_iodelay_odt : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => odt_odelay(odt_i),
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => odt_oq(odt_i),
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_odt : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0', -- 0 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => odt_oq(odt_i),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => mux_odt0(odt_i),
D2 => mux_odt0(odt_i),
D3 => mux_odt1(odt_i),
D4 => mux_odt1(odt_i),
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => oce_temp,
-- Connect SHIFTIN1, SHIFTIN2 to 0 for simulation purposes
-- (for all other OSERDES used in design, these are no-connects):
-- ensures that ODT outputs are not X at start of simulation
-- Certain DDR2 memory models may require that CK/CK# be valid
-- throughout simulation
SHIFTIN1 => '0',
SHIFTIN2 => '0',
RST => rst_cke_odt,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end generate;
--*********************************************************************
-- Parity for reg dimm. Parity output one cycle after the cs assertion
--*********************************************************************
gen_parity_wrlvl : if ((DRAM_TYPE = "DDR3") and (WRLVL = "ON")) generate
u_parity_obuf : OBUF
port map (
I => parity_oq,
O => ddr_parity
);
end generate;
gen_parity_nowrlvl : if (not(DRAM_TYPE = "DDR3") or not(WRLVL = "ON")) generate
attribute IODELAY_GROUP of u_iodelay_parity : label is IODELAY_GRP;
begin
u_parity_obuf : OBUF
port map (
I => parity_odelay,
O => ddr_parity
);
u_iodelay_parity : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "O",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 0,
ODELAY_TYPE => "FIXED",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ,
SIGNAL_PATTERN => "DATA"
)
port map (
DATAOUT => parity_odelay,
C => '0',
CE => '0',
DATAIN => 'Z',
IDATAIN => 'Z',
INC => '0',
ODATAIN => parity_oq,
RST => '0',
T => 'Z',
CNTVALUEIN => "ZZZZZ",
CNTVALUEOUT => open,
CLKIN => 'Z',
CINVCTRL => '0'
);
end generate;
u_out_parity : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1', -- 1 at reset
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => parity_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => parity1,
D2 => parity1,
D3 => parity0,
D4 => parity0,
D5 => 'Z',
D6 => 'Z',
ODV => '0',
OCE => '1',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst_r,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
end arch_phy_control_io;
|
lgpl-3.0
|
495627a66a7ce8cc16c4c16491f96ae9
| 0.405425 | 4.174268 | false | false | false | false |
amerc/TCP3
|
ipcore_dir/RxTstFIFO2K/simulation/RxTstFIFO2K_dverif.vhd
| 2 | 5,516 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.RxTstFIFO2K_pkg.ALL;
ENTITY RxTstFIFO2K_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF RxTstFIFO2K_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:RxTstFIFO2K_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
mit
|
f34c2904dab9f412671849a55fbe5923
| 0.576867 | 4.101115 | false | false | false | false |
VectorBlox/risc-v
|
ip/orca/hdl/branch_unit.vhd
| 1 | 8,587 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.constants_pkg.all;
use work.utils.all;
--use IEEE.std_logic_arith.all;
entity branch_unit is
generic (
REGISTER_SIZE : positive range 32 to 32;
SIGN_EXTENSION_SIZE : positive;
BTB_ENTRIES : natural;
ENABLE_EXCEPTIONS : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
to_branch_valid : in std_logic;
from_branch_illegal : out std_logic;
rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
current_pc : in unsigned(REGISTER_SIZE-1 downto 0);
predicted_pc : in unsigned(REGISTER_SIZE-1 downto 0);
instruction : in std_logic_vector(31 downto 0);
sign_extension : in std_logic_vector(SIGN_EXTENSION_SIZE-1 downto 0);
from_branch_valid : out std_logic;
from_branch_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
to_branch_ready : in std_logic;
target_misaligned : out std_logic;
to_pc_correction_data : out unsigned(REGISTER_SIZE-1 downto 0);
to_pc_correction_source_pc : out unsigned(REGISTER_SIZE-1 downto 0);
to_pc_correction_valid : out std_logic;
from_pc_correction_ready : in std_logic
);
end entity branch_unit;
architecture rtl of branch_unit is
--These signals must be one bit larger than a register
signal op1 : signed(REGISTER_SIZE downto 0);
signal op2 : signed(REGISTER_SIZE downto 0);
signal sub : signed(REGISTER_SIZE downto 0);
signal msb_mask : std_logic;
signal jal_imm : unsigned(REGISTER_SIZE-1 downto 0);
signal jalr_imm : unsigned(REGISTER_SIZE-1 downto 0);
signal b_imm : unsigned(REGISTER_SIZE-1 downto 0);
signal branch_target : unsigned(REGISTER_SIZE-1 downto 0);
signal nbranch_target : unsigned(REGISTER_SIZE-1 downto 0);
signal jalr_target : unsigned(REGISTER_SIZE-1 downto 0);
signal jal_target : unsigned(REGISTER_SIZE-1 downto 0);
signal target_pc : unsigned(REGISTER_SIZE-1 downto 0);
signal lt_flag : std_logic;
signal eq_flag : std_logic;
signal take_if_branch : std_logic;
alias opcode : std_logic_vector(6 downto 0) is instruction(INSTR_OPCODE'range);
alias func3 : std_logic_vector(2 downto 0) is instruction(INSTR_FUNC3'range);
signal jal_select : std_logic;
signal jalr_select : std_logic;
signal branch_select : std_logic;
begin
--Decode instruction to select submodule. All paths must decode to exactly
--one submodule.
--ASSUMES only JAL_OP | JALR_OP | BRANCH_OP for opcode.
process (opcode, func3) is
begin
jal_select <= '0';
jalr_select <= '0';
branch_select <= '0';
from_branch_illegal <= '0';
case opcode(3 downto 2) is
when "11" => --JAL_OP(3 downto 2)
jal_select <= '1';
when "01" => --JALR_OP(3 downto 2)
if ENABLE_EXCEPTIONS then
if func3 = JALR_FUNC3 then
jalr_select <= '1';
else
from_branch_illegal <= '1';
end if;
else
jalr_select <= '1';
end if;
when "00" => --BRANCH_OP(3 downto 2)
if ENABLE_EXCEPTIONS then
if func3(2 downto 1) = "01" then
from_branch_illegal <= '1';
else
branch_select <= '1';
end if;
else
branch_select <= '1';
end if;
when others =>
if ENABLE_EXCEPTIONS then
from_branch_illegal <= '1';
else
--Undefined; pick JAL for easy decoding
jal_select <= '1';
end if;
end case;
end process;
with func3 select
msb_mask <=
'0' when BLTU_FUNC3,
'0' when BGEU_FUNC3,
'1' when others;
op1 <= signed((msb_mask and rs1_data(rs1_data'left)) & rs1_data);
op2 <= signed((msb_mask and rs2_data(rs2_data'left)) & rs2_data);
sub <= op1 - op2;
eq_flag <= '1' when rs1_data = rs2_data else '0';
lt_flag <= sub(sub'left);
with func3 select
take_if_branch <=
(not lt_flag) or eq_flag when BGEU_FUNC3,
lt_flag when BLTU_FUNC3,
(not lt_flag) or eq_flag when BGE_FUNC3,
lt_flag when BLT_FUNC3,
not eq_flag when BNE_FUNC3,
eq_flag when others;
b_imm <= unsigned(sign_extension(REGISTER_SIZE-13 downto 0) &
instruction(7) & instruction(30 downto 25) &instruction(11 downto 8) & "0");
jalr_imm <= unsigned(sign_extension(REGISTER_SIZE-12-1 downto 0) &
instruction(31 downto 21) & "0");
jal_imm <= unsigned(RESIZE(signed(instruction(31) & instruction(19 downto 12) & instruction(20) &
instruction(30 downto 21)&"0"), REGISTER_SIZE));
no_predictor_gen : if BTB_ENTRIES = 0 generate
signal mispredict : std_logic;
begin
--If there's no branch predictor, any taken branch/jump is a mispredict, and
--there's no need to use PC+4 (nbranch_target) as a correction
target_pc <=
jal_target when jal_select = '1' else
jalr_target when jalr_select = '1' else
branch_target;
mispredict <= (take_if_branch and branch_select) or jal_select or jalr_select;
process(clk)
begin
if rising_edge(clk) then
if from_pc_correction_ready = '1' then
to_pc_correction_valid <= '0';
end if;
if to_branch_ready = '1' then
if to_branch_valid = '1' then
to_pc_correction_data <= target_pc;
to_pc_correction_source_pc <= current_pc;
if mispredict = '1' then
to_pc_correction_valid <= '1';
end if;
end if;
end if;
if reset = '1' then
to_pc_correction_valid <= '0';
end if;
end if;
end process;
end generate no_predictor_gen;
has_predictor_gen : if BTB_ENTRIES > 0 generate
signal previously_targeted_pc : unsigned(REGISTER_SIZE-1 downto 0);
signal previously_predicted_pc : unsigned(REGISTER_SIZE-1 downto 0);
signal to_pc_correction_valid_if_mispredicted : std_logic;
signal was_mispredicted : std_logic;
begin
target_pc <=
jalr_target when jalr_select = '1' else
jal_target when jal_select = '1' else
branch_target when branch_select = '1' and take_if_branch = '1' else
nbranch_target;
process(clk)
begin
if rising_edge(clk) then
if from_pc_correction_ready = '1' then
to_pc_correction_valid_if_mispredicted <= '0';
end if;
if to_branch_ready = '1' then
if to_branch_valid = '1' then
previously_targeted_pc <= target_pc;
to_pc_correction_source_pc <= current_pc;
previously_predicted_pc <= predicted_pc;
to_pc_correction_valid_if_mispredicted <= '1';
end if;
end if;
if reset = '1' then
to_pc_correction_valid_if_mispredicted <= '0';
end if;
end if;
end process;
to_pc_correction_data <= previously_targeted_pc;
--Note that computing mispredict during the execute cycle (as is done in
--the no BTB generate) is more readable/consistent. The latter part of the
--mispredict calculation was moved to the next cycle only because there is
--a long combinational path and it can be the critical path in
--implementations that don't do register retiming.
was_mispredicted <= '1' when previously_targeted_pc /= previously_predicted_pc else '0';
to_pc_correction_valid <= to_pc_correction_valid_if_mispredicted and was_mispredicted;
end generate has_predictor_gen;
branch_target <= b_imm + current_pc;
nbranch_target <= to_unsigned(4, REGISTER_SIZE) + current_pc;
jalr_target <= jalr_imm + unsigned(rs1_data);
jal_target <= jal_imm + current_pc;
process(clk)
begin
if rising_edge(clk) then
from_branch_valid <= '0';
if to_branch_ready = '1' then
from_branch_data <= std_logic_vector(nbranch_target);
if target_pc(1 downto 0) = "00" then
from_branch_valid <= to_branch_valid and (jal_select or jalr_select) ;
end if;
end if;
if reset = '1' then
from_branch_valid <= '0';
end if;
end if;
end process;
target_misaligned <= to_branch_valid when target_pc(1 downto 0) /= "00" else '0';
end architecture;
|
bsd-3-clause
|
d4149829ebc2362036d94174f74d796f
| 0.599744 | 3.595896 | false | false | false | false |
z3774/sparcv8-monocycle
|
PSR_MOD.vhd
| 1 | 1,824 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PSR_MOD is
Port (
alurs : in STD_LOGIC_VECTOR (31 downto 0);
ope1 : in STD_LOGIC;
ope2 : in STD_LOGIC;
aluop : in STD_LOGIC_VECTOR (5 downto 0);
nzvc : out std_logic_vector(3 downto 0)
);
end PSR_MOD;
architecture Behavioral of PSR_MOD is
begin
process(alurs,ope1,ope2,aluop)
begin
--ADDcc ADDXcc
if (aluop = "100001" or aluop = "100011") then
nzvc(3) <= alurs(31);
if(alurs = X"00000000")then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= (ope1 and ope2 and (not alurs(31))) or ((ope1) and (not ope2) and alurs(31));
nzvc(0) <= (ope1 and ope2) or ((not alurs(31)) and (ope1 or ope2));
--SUBcc SUBXcc
elsif (aluop = "100101" or aluop = "100111") then
nzvc(3) <= alurs(31);
if(alurs = X"00000000")then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= ((ope1 and (not ope2) and (not alurs(31))) or ((not ope1) and ope2 and alurs(31)));
nzvc(0) <= ((not ope1) and ope2) or (alurs(31) and ((not ope1) or ope2));
--ANDcc ANDNcc ORcc ORNcc XORcc XNORcc
elsif(aluop = "101001" or aluop = "101011" or aluop = "101101" or aluop = "101111" or aluop = "110001" or aluop = "110011")then
nzvc(3) <= alurs(31);
if(alurs = X"00000000") then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= '0';
nzvc(0) <= '0';
-- --RESTO DE OPERACIONES
-- else
-- nzvc <= "0000";
end if;
end process;
end Behavioral;
|
gpl-3.0
|
8cc912bf622131c12c555ddd2ce4289f
| 0.603618 | 2.832298 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/hdmi/hdmi.vhd
| 2 | 10,846 |
-------------------------------------------------------------------[13.08.2016]
-- HDMI
-------------------------------------------------------------------------------
-- Engineer: MVV <[email protected]>
--
-- (c) 2016 Alexey Spirkov
-- I am happy for anyone to use this for non-commercial use.
-- If my verilog/vhdl/c files are used commercially or otherwise sold,
-- please contact me for explicit permission at me _at_ alsp.net.
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
-- Recommended params:
-- N=0x1800 CTS=0x6FD1 (28.625MHz pixel clock -> 48KHz audio clock)
-- N=0x1000 CTS=0x6FD1 (28.625MHz pixel clock -> 32KHz audio clock)
-- N=0x1000 CTS=0x6978 (27MHz pixel clock -> 32KHz audio clock)
-- N=0x1800 CTS=0x6978 (27MHz pixel clock -> 48KHz audio clock)
-- N=0x1800 CTS=0x6270 (25.2MHz pixel clock -> 48KHz audio clock)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hdmi is
generic (
FREQ : integer; -- pixel clock frequency
FS : integer; -- audio sample rate - should be 32000, 41000 or 48000
CTS : integer; -- CTS = Freq(pixclk) * N / (128 * Fs)
N : integer -- N = 128 * Fs /1000, 128 * Fs /1500 <= N <= 128 * Fs /300 (Check HDMI spec 7.2 for details)
);
port (
I_CLK_VGA : in std_logic;
I_CLK_TMDS : in std_logic;
I_HSYNC : in std_logic;
I_VSYNC : in std_logic;
I_BLANK : in std_logic;
I_RED : in std_logic_vector( 7 downto 0);
I_GREEN : in std_logic_vector( 7 downto 0);
I_BLUE : in std_logic_vector( 7 downto 0);
I_AUDIO_PCM_L : in std_logic_vector(15 downto 0);
I_AUDIO_PCM_R : in std_logic_vector(15 downto 0);
O_TMDS : out std_logic_vector( 7 downto 0)
);
end entity;
architecture rtl of hdmi is
component hdmidataencoder
generic (
FREQ: integer;
FS: integer;
CTS: integer;
N: integer);
port (
i_pixclk : in std_logic;
i_hSync : in std_logic;
i_vSync : in std_logic;
i_blank : in std_logic;
i_audioL : in std_logic_vector(15 downto 0);
i_audioR : in std_logic_vector(15 downto 0);
o_d0 : out std_logic_vector(3 downto 0);
o_d1 : out std_logic_vector(3 downto 0);
o_d2 : out std_logic_vector(3 downto 0);
o_data : out std_logic);
end component;
signal red : std_logic_vector(9 downto 0);
signal green : std_logic_vector(9 downto 0);
signal blue : std_logic_vector(9 downto 0);
signal enc0out : std_logic_vector(9 downto 0);
signal enc1out : std_logic_vector(9 downto 0);
signal enc2out : std_logic_vector(9 downto 0);
signal tx_in : std_logic_vector(29 downto 0);
signal tmds_d : std_logic_vector(2 downto 0);
signal data : std_logic;
signal dataPacket0 : std_logic_vector(3 downto 0);
signal dataPacket1 : std_logic_vector(3 downto 0);
signal dataPacket2 : std_logic_vector(3 downto 0);
signal delayLineIn : std_logic_vector(39 downto 0);
signal delayLineOut : std_logic_vector(39 downto 0);
signal ROut : std_logic_vector(7 downto 0);
signal GOut : std_logic_vector(7 downto 0);
signal BOut : std_logic_vector(7 downto 0);
signal hSyncOut : std_logic;
signal vSyncOut : std_logic;
signal vdeOut : std_logic;
signal dataOut : std_logic;
signal vhSyncOut : std_logic_vector(1 downto 0);
signal prevBlank : std_logic;
signal prevData : std_logic;
signal dataPacket0Out : std_logic_vector(3 downto 0);
signal dataPacket1Out : std_logic_vector(3 downto 0);
signal dataPacket2Out : std_logic_vector(3 downto 0);
signal ctl0 : std_logic;
signal ctl1 : std_logic;
signal ctl2 : std_logic;
signal ctl3 : std_logic;
signal ctl_10 : std_logic_vector(1 downto 0);
signal ctl_32 : std_logic_vector(1 downto 0);
-- states
type count_state is (
videoData,
videoDataPreamble,
videoDataGuardBand,
dataIslandPreamble,
dataIslandPreGuard,
dataIslandPostGuard,
dataIsland,
controlData
);
signal state: count_state;
signal clockCounter: integer range 0 to 2047;
signal mod5 : std_logic_vector(2 downto 0);
signal shift_r, shift_g, shift_b : std_logic_vector(9 downto 0);
type t_q_pipe is array(0 to 10) of std_logic_vector(39 downto 0);
signal q_pipe : t_q_pipe;
begin
-- data should be delayed for 11 clocks to allow preamble and guard band generation
-- delay line inputs
delayLineIn(39 downto 32) <= I_RED;
delayLineIn(31 downto 24) <= I_GREEN;
delayLineIn(23 downto 16) <= I_BLUE;
delayLineIn(15) <= I_HSYNC;
delayLineIn(14) <= I_VSYNC;
delayLineIn(13) <= not I_BLANK;
delayLineIn(12) <= data;
delayLineIn(11 downto 8) <= dataPacket0;
delayLineIn(7 downto 4) <= dataPacket1;
delayLineIn(3 downto 0) <= dataPacket2;
-- delay line outputs
ROut <= delayLineOut(39 downto 32);
GOut <= delayLineOut(31 downto 24);
BOut <= delayLineOut(23 downto 16);
hSyncOut <= delayLineOut(15);
vSyncOut <= delayLineOut(14);
vdeOut <= delayLineOut(13);
dataOut <= delayLineOut(12);
dataPacket0Out <= delayLineOut(11 downto 8);
dataPacket1Out <= delayLineOut(7 downto 4);
dataPacket2Out <= delayLineOut(3 downto 0);
vhSyncOut <= vSyncOut & hSyncOut;
ctl_10 <= ctl1&ctl0;
ctl_32 <= ctl3&ctl2;
FSA: process(I_CLK_VGA) is
begin
if(rising_edge(I_CLK_VGA)) then
if(prevBlank = '0' and i_BLANK = '1') then
state <= controlData;
clockCounter <= 0;
else
case state is
when controlData =>
if prevData = '0' and data = '1' then -- ok - data stared - needs data preamble
state <= dataIslandPreamble;
ctl0 <= '1';
ctl1 <= '0';
ctl2 <= '1';
ctl3 <= '0';
clockCounter <= 0;
elsif prevBlank = '1' and I_BLANK = '0' then -- ok blank os out - start generation video preamble
state <= videoDataPreamble;
ctl0 <= '1';
ctl1 <= '0';
ctl2 <= '0';
ctl3 <= '0';
clockCounter <= 0;
end if;
when dataIslandPreamble => -- data island preable needed for 8 clocks
if clockCounter = 8 then
state <= dataIslandPreGuard;
ctl0 <= '0';
ctl1 <= '0';
ctl2 <= '0';
ctl3 <= '0';
clockCounter <= 0;
else
clockCounter <= clockCounter + 1;
end if;
when dataIslandPreGuard => -- data island preguard needed for 2 clocks
if clockCounter = 1 then
state <= dataIsland;
clockCounter <= 0;
else
clockCounter <= clockCounter + 1;
end if;
when dataIsland =>
if clockCounter = 11 then -- ok we at the end of data island - post guard is needed
state <= dataIslandPostGuard;
clockCounter <= 0;
elsif prevBlank = '1' and I_BLANK = '0' then -- something fails - no data were detected but blank os out
state <= videoDataPreamble;
ctl0 <= '1';
ctl1 <= '0';
ctl2 <= '0';
ctl3 <= '0';
clockCounter <= 0;
elsif data = '0' then -- start count and count only when data is over
clockCounter <= clockCounter + 1;
end if;
when dataIslandPostGuard => -- data island postguard needed for 2 clocks
if clockCounter = 1 then
state <= controlData;
clockCounter <= 0;
else
clockCounter <= clockCounter + 1;
end if;
when videoDataPreamble => -- video data preable needed for 8 clocks
if clockCounter = 8 then
state <= videoDataGuardBand;
ctl0 <= '0';
ctl1 <= '0';
ctl2 <= '0';
ctl3 <= '0';
clockCounter <= 0;
else
clockCounter <= clockCounter + 1;
end if;
when videoDataGuardBand => -- video data guard needed for 2 clocks
if clockCounter = 1 then
state <= videoData;
clockCounter <= 0;
else
clockCounter <= clockCounter + 1;
end if;
when videoData =>
if clockCounter = 11 then -- ok we at the end of video data - just switch to control
state <= controlData;
clockCounter <= 0;
elsif I_BLANK = '1' then -- start count and count only when video is over
clockCounter <= clockCounter + 1;
end if;
end case;
end if;
prevBlank <= I_BLANK;
prevData <= data;
end if;
end process;
blueout: blue <=
"1010001110" when (state = dataIslandPreGuard or state = dataIslandPostGuard) and vhSyncOut = "00" else
"1001110001" when (state = dataIslandPreGuard or state = dataIslandPostGuard) and vhSyncOut = "01" else
"0101100011" when (state = dataIslandPreGuard or state = dataIslandPostGuard) and vhSyncOut = "10" else
"1011000011" when (state = dataIslandPreGuard or state = dataIslandPostGuard) and vhSyncOut = "11" else
"1011001100" when state = videoDataGuardBand else
enc0out;
greenout: green <=
"0100110011" when state = videoDataGuardBand else
"0100110011" when state = dataIslandPreGuard or state = dataIslandPostGuard else
enc1out;
redout: red <=
"1011001100" when state = videoDataGuardBand else
"0100110011" when state = dataIslandPreGuard or state = dataIslandPostGuard else
enc2out;
process_pipe : process(I_CLK_VGA)
begin
if (rising_edge(I_CLK_VGA)) then
q_pipe <= delayLineIn & q_pipe(0 to q_pipe'length-2);
end if;
end process process_pipe;
delayLineOut <= q_pipe(q_pipe'length-1);
dataenc: hdmidataencoder
generic map (
FREQ => FREQ,
FS => FS,
CTS => CTS,
N => N)
port map(
i_pixclk => I_CLK_VGA,
i_blank => I_BLANK,
i_hSync => I_HSYNC,
i_vSync => I_VSYNC,
i_audioL => I_AUDIO_PCM_L,
i_audioR => I_AUDIO_PCM_R,
o_d0 => dataPacket0,
o_d1 => dataPacket1,
o_d2 => dataPacket2,
o_data => data
);
enc0: entity work.encoder
port map (
CLK => I_CLK_VGA,
DATA => BOut,
C => vhSyncOut,
VDE => vdeOut,
ADE => dataOut,
AUX => dataPacket0Out,
ENCODED => enc0out);
enc1: entity work.encoder
port map (
CLK => I_CLK_VGA,
DATA => GOut,
C => ctl_10,
VDE => vdeOut,
ADE => dataOut,
AUX => dataPacket1Out,
ENCODED => enc1out);
enc2: entity work.encoder
port map (
CLK => I_CLK_VGA,
DATA => ROut,
C => ctl_32,
VDE => vdeOut,
ADE => dataOut,
AUX => dataPacket2Out,
ENCODED => enc2out);
-- HDMI data serialiser
-- Outputs the encoded video data as serial data across the HDMI bus
ddio_inst: entity work.altddio_out1
port map (
datain_h => shift_r(0) & not(shift_r(0)) & shift_g(0) & not(shift_g(0)) & shift_b(0) & not(shift_b(0)) & I_CLK_VGA & not(I_CLK_VGA),
datain_l => shift_r(1) & not(shift_r(1)) & shift_g(1) & not(shift_g(1)) & shift_b(1) & not(shift_b(1)) & I_CLK_VGA & not(I_CLK_VGA),
outclock => I_CLK_TMDS,
dataout => O_TMDS);
process (I_CLK_TMDS)
begin
if I_CLK_TMDS'event and I_CLK_TMDS = '1' then
if mod5(2) = '1' then
mod5 <= "000";
shift_r <= red;
shift_g <= green;
shift_b <= blue;
else
mod5 <= mod5 + "001";
shift_r <= "00" & shift_r(9 downto 2);
shift_g <= "00" & shift_g(9 downto 2);
shift_b <= "00" & shift_b(9 downto 2);
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
b29405727cdc64a8f6e056be2de0fd70
| 0.630371 | 2.971507 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/hdmi2/hdmi_out_xilinx.vhd
| 2 | 3,872 |
--
-- Copyright (c) 2015 Davor Jadrijevic
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-- OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-- SUCH DAMAGE.
--
-- $Id$
--
-- vendor-independent module for simulating differential HDMI output
-- this module tested on scarab and it works :)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
entity hdmi_out_xilinx is
port (
clock_pixel_i : in std_logic; -- x1
clock_tdms_i : in std_logic; -- x5
red_i : in std_logic_vector(9 downto 0);
green_i : in std_logic_vector(9 downto 0);
blue_i : in std_logic_vector(9 downto 0);
tmds_out_p : out std_logic_vector(3 downto 0);
tmds_out_n : out std_logic_vector(3 downto 0)
);
end entity;
architecture Behavioral of hdmi_out_xilinx is
signal mod5 : std_logic_vector(2 downto 0);
signal shift_r, shift_g, shift_b : std_logic_vector(9 downto 0);
type a_output_bits is array (0 to 3) of std_logic_vector(1 downto 0);
signal output_bits : a_output_bits := (others => (others => '0'));
-- The signals from the DDR outputs to the output buffers
signal serial_outputs : std_logic_vector(3 downto 0);
begin
process (clock_tdms_i)
begin
if rising_edge(clock_tdms_i) then
if mod5(2) = '1' then
mod5 <= "000";
shift_r <= red_i;
shift_g <= green_i;
shift_b <= blue_i;
else
mod5 <= mod5 + "001";
shift_r <= "00" & shift_r(9 downto 2);
shift_g <= "00" & shift_g(9 downto 2);
shift_b <= "00" & shift_b(9 downto 2);
end if;
end if;
end process;
output_bits(3) <= clock_pixel_i & not clock_pixel_i;
output_bits(2) <= shift_r(1 downto 0);
output_bits(1) <= shift_g(1 downto 0);
output_bits(0) <= shift_b(1 downto 0);
g1: for i in 0 to 3 generate
--------------------------------------------------------
-- Convert the TMDS codes into a serial stream, two bits
-- at a time using a DDR register
--------------------------------------------------------
to_serial: ODDR2
generic map (
DDR_ALIGNMENT => "C0",
INIT => '0',
SRTYPE => "ASYNC"
)
port map (
C0 => clock_tdms_i,
C1 => not clock_tdms_i,
CE => '1',
R => '0',
S => '0',
D0 => output_bits(i)(0),
D1 => output_bits(i)(1),
Q => serial_outputs(i)
);
end generate;
-- vendor-specific differential output buffering for HDMI clock and video
hdmis: for i in 0 to 3 generate
tmds_video: obufds
--generic map(IOSTANDARD => "DEFAULT")
port map(
i => serial_outputs(i),
o => tmds_out_p(i),
ob => tmds_out_n(i)
);
end generate;
end Behavioral;
|
gpl-3.0
|
01caf5530d46ccbd454d2433a9639aa7
| 0.651085 | 3.253782 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdlvl.vhd
| 1 | 132,115 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version:
-- \ \ Application: MIG
-- / / Filename: phy_rdlvl.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created:
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Read leveling calibration logic
-- NOTES:
-- 1. DQ per-bit deskew is not yet supported
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_rdlvl.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_rdlvl.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_rdlvl is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3333; -- Internal clock period (in ps)
REFCLK_FREQ : integer := 300; -- IODELAY Reference Clock freq (MHz)
DQ_WIDTH : integer := 64; -- # of DQ (data)
DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
DQS_WIDTH : integer := 8; -- # of DQS (strobe)
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
PD_TAP_REQ : integer := 10; -- # of IODELAY taps reserved for PD
nCL : integer := 5; -- Read CAS latency (in clk cyc)
SIM_CAL_OPTION : string := "NONE"; -- Skip various calibration steps
REG_CTRL : string := "ON"; -- "ON" for registered DIMM
DEBUG_PORT : string := "OFF" -- Enable debug port
);
port (
clk : in std_logic;
rst : in std_logic;
-- Calibration status, control signals
rdlvl_start : in std_logic_vector(1 downto 0);
rdlvl_clkdiv_start : in std_logic;
rdlvl_rd_active : in std_logic;
rdlvl_done : out std_logic_vector(1 downto 0);
rdlvl_clkdiv_done : out std_logic;
rdlvl_err : out std_logic_vector(1 downto 0);
rdlvl_prech_req : out std_logic;
prech_done : in std_logic;
-- Captured data in resync clock domain
rd_data_rise0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_rise1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
-- Stage 1 calibration outputs
dlyce_cpt : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dlyinc_cpt : out std_logic;
dlyce_rsync : out std_logic_vector(3 downto 0);
dlyinc_rsync : out std_logic;
dlyval_dq : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dlyval_dqs : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
-- Stage 2 calibration inputs/outputs
rd_bitslip_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdly_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_active_dly : out std_logic_vector(4 downto 0);
rdlvl_pat_resume : in std_logic; -- resume pattern cal
rdlvl_pat_err : out std_logic; -- error during pattern cal
rdlvl_pat_err_cnt : out std_logic_vector(DQS_CNT_WIDTH - 1 downto 0); -- erroring DQS group
-- Resynchronization clock (clkinv_inv) calibration outputs
rd_clkdiv_inv : out std_logic_vector(DQS_WIDTH - 1 downto 0);
-- Debug Port
dbg_cpt_first_edge_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_rd_bitslip_cnt : out std_logic_vector(3*DQS_WIDTH - 1 downto 0);
dbg_rd_clkdiv_inv : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dbg_rd_clkdly_cnt : out std_logic_vector(2*DQS_WIDTH - 1 downto 0);
dbg_rd_active_dly : out std_logic_vector(4 downto 0);
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_rsync : in std_logic;
dbg_idel_down_rsync : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_idel_rsync : in std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
dbg_sel_all_idel_rsync : in std_logic;
dbg_phy_rdlvl : out std_logic_vector(255 downto 0)
);
end entity phy_rdlvl;
architecture arch of phy_rdlvl is
-- Function to 'and' all the bits of a signal
function AND_BR(inp_sig: std_logic_vector)
return std_logic is
variable return_var : std_logic := '1';
begin
for index in inp_sig'range loop
return_var := return_var and inp_sig(index);
end loop;
return return_var;
end function;
-- Function to 'OR' all the bits of a signal
function OR_BR(inp_sig: std_logic_vector(DQS_WIDTH-1 downto 0))
return std_logic is
variable return_var : std_logic := '0';
begin
for index in inp_sig'range loop
return_var := return_var or inp_sig(index);
end loop;
return return_var;
end function;
-- function calc_cnt_idel_dec_cpt (second_edge_taps_r, first_edge_taps_r: std_logic_vector) return std_logic_vector is
-- variable tmp : std_logic_vector (5 downto 0);
-- begin
-- tmp := std_logic_vector(unsigned(second_edge_taps_r - first_edge_taps_r) srl 1);
-- tmp := tmp + '1';
-- return tmp;
-- end function;
function calc_cnt_idel_dec_cpt (second_edge_taps_r, first_edge_taps_r: std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector (6 downto 0);
begin
tmp := std_logic_vector(to_unsigned(to_integer(signed('0' & second_edge_taps_r)) -
to_integer(signed('0' & first_edge_taps_r)), 7) srl 1) + '1';
return tmp(5 downto 0);
end function;
function add_vectors (opd1, opd2: std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector (5 downto 0);
begin
tmp := opd1 + ('0' & opd2);
return tmp(4 downto 0);
end function;
function subtract_vectors (opd1, opd2: std_logic_vector) return std_logic_vector is
variable tmp : std_logic_vector (5 downto 0);
begin
tmp := opd1 - ('0' & opd2);
return tmp(4 downto 0);
end function;
-- minimum time (in IDELAY taps) for which capture data must be stable for
-- algorithm to consider a valid data eye to be found. The read leveling
-- logic will ignore any window found smaller than this value. Limitations
-- on how small this number can be is determined by: (1) the algorithmic
-- limitation of how many taps wide the data eye can be (3 taps), and (2)
-- how wide regions of "instability" that occur around the edges of the
-- read valid window can be (i.e. need to be able to filter out "false"
-- windows that occur for a short # of taps around the edges of the true
-- data window, although with multi-sampling during read leveling, this is
-- not as much a concern) - the larger the value, the more protection
-- against "false" windows
function MIN_EYE_SIZE_CALC return integer is
begin
if (DRAM_TYPE = "DDR3") then
return 3;
else
return 6;
end if;
end function;
constant MIN_EYE_SIZE : integer := MIN_EYE_SIZE_CALC;
-- # of clock cycles to wait after changing IDELAY value or read data MUX
-- to allow both IDELAY chain to settle, and for delayed input to
-- propagate thru ISERDES
constant PIPE_WAIT_CNT : integer := 16;
-- Length of calibration sequence (in # of words)
constant CAL_PAT_LEN : integer := 8;
-- Read data shift register length
constant RD_SHIFT_LEN : integer := CAL_PAT_LEN / (2*nCK_PER_CLK);
-- Amount to shift by if one edge found (= 0.5*(bit_period)). Limit to 31
constant IODELAY_TAP_RES : integer := 1000000 / (REFCLK_FREQ * 64);
--Function to compare two vectors and return value if both vectors have true values (either 0s or 1s)
function ADVANCE_COMP(
input_a : std_logic_vector;
input_b : std_logic_vector
) return std_logic is
variable temp : std_logic_vector(RD_SHIFT_LEN-1 downto 0 ) := (others => '1');
begin
for i in input_a'range loop
if(((input_a(i) = '0') and (input_b(i) = '0')) or ((input_a(i) = '1') and (input_b(i) = '1'))) then
temp(i) := '1' ;
else
temp(i) := '0' ;
end if ;
end loop;
if((AND_BR(temp)) = '1' ) then
return '1' ;
else
return '0';
end if ;
end;
function CACL_TBY4_TAPS return integer is
begin
if ( ((CLK_PERIOD/nCK_PER_CLK/4) / IODELAY_TAP_RES) > 31) then
return (31);
else
return ((CLK_PERIOD/nCK_PER_CLK/4) / IODELAY_TAP_RES);
end if;
end function;
constant TBY4_TAPS : integer := CACL_TBY4_TAPS;
-- Maximum amount to wait after read issued until read data returned
constant MAX_RD_DLY_CNT : integer := 32;
-- # of cycles to wait after changing RDEN count value
constant RDEN_WAIT_CNT : integer := 8;
-- used during read enable calibration - difference between what the
-- calibration logic measured read enable delay to be, and what it needs
-- to set the value of the read active delay control to be
constant RDEN_DELAY_OFFSET : integer := 5;
-- # of read data samples to examine when detecting whether an edge has
-- occured during stage 1 calibration. Width of local param must be
-- changed as appropriate. Note that there are two counters used, each
-- counter can be changed independently of the other - they are used in
-- cascade to create a larger counter
constant DETECT_EDGE_SAMPLE_CNT0 : std_logic_vector(11 downto 0) := X"FFF";
constant DETECT_EDGE_SAMPLE_CNT1 : std_logic_vector(11 downto 0) := X"001";
-- # of taps in IDELAY chain. When the phase detector taps are reserved
-- before the start of calibration, reduce half that amount from the
-- total available taps.
constant IODELAY_TAP_LEN : integer := 32 - (PD_TAP_REQ/2);
-- Half the PD taps
constant PD_HALF_TAP : integer := (PD_TAP_REQ/2);
-- Type declarations for multi-dimensional arrays
type type_6 is array (0 to DQS_WIDTH-1) of std_logic_vector(4 downto 0);
type type_5 is array (3 downto 0) of std_logic_vector(RD_SHIFT_LEN - 1 downto 0);
type type_3 is array (DQS_WIDTH-1 downto 0) of std_logic_vector(4 downto 0);
type type_4 is array (DRAM_WIDTH-1 downto 0) of std_logic_vector(RD_SHIFT_LEN-1 downto 0);
constant CAL1_IDLE : std_logic_vector(4 downto 0) := "00000";
constant CAL1_NEW_DQS_WAIT : std_logic_vector(4 downto 0) := "00001";
constant CAL1_IDEL_STORE_FIRST : std_logic_vector(4 downto 0) := "00010";
constant CAL1_DETECT_EDGE : std_logic_vector(4 downto 0) := "00011";
constant CAL1_IDEL_STORE_OLD : std_logic_vector(4 downto 0) := "00100";
constant CAL1_IDEL_INC_CPT : std_logic_vector(4 downto 0) := "00101";
constant CAL1_IDEL_INC_CPT_WAIT : std_logic_vector(4 downto 0) := "00110";
constant CAL1_CALC_IDEL : std_logic_vector(4 downto 0) := "00111";
constant CAL1_IDEL_DEC_CPT : std_logic_vector(4 downto 0) := "01000";
constant CAL1_NEXT_DQS : std_logic_vector(4 downto 0) := "01001";
constant CAL1_DONE : std_logic_vector(4 downto 0) := "01010";
constant CAL1_RST_CPT : std_logic_vector(4 downto 0) := "01011";
constant CAL1_DETECT_EDGE_DQ : std_logic_vector(4 downto 0) := "01100";
constant CAL1_IDEL_INC_DQ : std_logic_vector(4 downto 0) := "01101";
constant CAL1_IDEL_INC_DQ_WAIT : std_logic_vector(4 downto 0) := "01110";
constant CAL1_CALC_IDEL_DQ : std_logic_vector(4 downto 0) := "01111";
constant CAL1_IDEL_INC_DQ_CPT : std_logic_vector(4 downto 0) := "10000";
constant CAL1_IDEL_INC_PD_CPT : std_logic_vector(4 downto 0) := "10001";
constant CAL1_IDEL_PD_ADJ : std_logic_vector(4 downto 0) := "10010";
constant CAL1_SKIP_RDLVL_INC_IDEL : std_logic_vector(4 downto 0) := "11111"; -- Only for simulation
constant CAL2_IDLE : std_logic_vector(2 downto 0) := "000";
constant CAL2_READ_WAIT : std_logic_vector(2 downto 0) := "001";
constant CAL2_DETECT_MATCH : std_logic_vector(2 downto 0) := "010";
constant CAL2_BITSLIP_WAIT : std_logic_vector(2 downto 0) := "011";
constant CAL2_NEXT_DQS : std_logic_vector(2 downto 0) := "100";
constant CAL2_DONE : std_logic_vector(2 downto 0) := "101";
constant CAL2_ERROR_TO : std_logic_vector(2 downto 0) := "110";
constant CAL_CLKDIV_IDLE : std_logic_vector(3 downto 0) := "0000";
constant CAL_CLKDIV_NEW_DQS_WAIT : std_logic_vector(3 downto 0) := "0001";
constant CAL_CLKDIV_IDEL_STORE_REF : std_logic_vector(3 downto 0) := "0010";
constant CAL_CLKDIV_DETECT_EDGE : std_logic_vector(3 downto 0) := "0011";
constant CAL_CLKDIV_IDEL_INCDEC_RSYNC : std_logic_vector(3 downto 0) := "0100";
constant CAL_CLKDIV_IDEL_INCDEC_RSYNC_WAIT : std_logic_vector(3 downto 0) := "0101";
constant CAL_CLKDIV_IDEL_SET_MIDPT_RSYNC : std_logic_vector(3 downto 0) := "0110";
constant CAL_CLKDIV_NEXT_CHECK : std_logic_vector(3 downto 0) := "0111";
constant CAL_CLKDIV_NEXT_DQS : std_logic_vector(3 downto 0) := "1000";
constant CAL_CLKDIV_DONE : std_logic_vector(3 downto 0) := "1001";
signal cal_clkdiv_clkdiv_inv_r : std_logic;
signal cal_clkdiv_cnt_clkdiv_r : std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
signal cal_clkdiv_dlyce_rsync_r : std_logic;
signal cal_clkdiv_dlyinc_rsync_r : std_logic;
signal cal_clkdiv_idel_rsync_inc_r : std_logic;
signal cal_clkdiv_prech_req_r : std_logic;
signal cal_clkdiv_store_sr_req_r : std_logic;
signal cal_clkdiv_state_r : std_logic_vector(3 downto 0);
signal cal1_cnt_cpt_r : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
signal cal1_dlyce_cpt_r : std_logic;
signal cal1_dlyinc_cpt_r : std_logic;
signal cal1_dq_tap_cnt_r : std_logic_vector(4 downto 0);
signal cal1_dq_taps_inc_r : std_logic;
signal cal1_prech_req_r : std_logic;
signal cal1_found_edge : std_logic;
signal cal1_state_r : std_logic_vector(4 downto 0);
signal cal1_store_sr_req_r : std_logic;
signal cal2_clkdly_cnt_r : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal cal2_cnt_bitslip_r : std_logic_vector(1 downto 0);
signal cal2_cnt_rd_dly_r : std_logic_vector(4 downto 0);
signal cal2_cnt_rden_r : std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
signal cal2_deskew_err_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal cal2_dly_cnt_delta_r : type_3;
signal cal2_done_r : std_logic;
signal cal2_done_r1 : std_logic;
signal cal2_done_r2 : std_logic;
signal cal2_done_r3 : std_logic;
signal cal2_dly_cnt_r : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal cal2_en_dqs_skew_r : std_logic;
signal cal2_max_cnt_rd_dly_r : std_logic_vector(4 downto 0);
signal cal2_prech_req_r : std_logic;
signal cal2_rd_active_dly_r : std_logic_vector(4 downto 0);
signal cal2_rd_bitslip_cnt_r : std_logic_vector(2*DQS_WIDTH - 1 downto 0);
signal cal2_state_r : std_logic_vector(2 downto 0);
signal clkdiv_inv_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal cnt_eye_size_r : std_logic_vector(2 downto 0);
signal cnt_idel_dec_cpt_r : std_logic_vector(5 downto 0);
signal cnt_idel_inc_cpt_r : std_logic_vector(4 downto 0);
signal cnt_idel_skip_idel_r : std_logic_vector(4 downto 0);
signal cnt_pipe_wait_r : std_logic_vector(3 downto 0);
signal cnt_rden_wait_r : std_logic_vector(2 downto 0);
signal cnt_shift_r : std_logic_vector(3 downto 0);
signal detect_edge_cnt0_r : std_logic_vector(11 downto 0);
signal detect_edge_cnt1_en_r : std_logic;
signal detect_edge_cnt1_r : std_logic_vector(11 downto 0);
signal detect_edge_done_r : std_logic;
signal detect_edge_start_r : std_logic;
signal dlyce_or : std_logic;
signal dlyval_dq_reg_r : std_logic_vector(5*DQS_WIDTH - 1 downto 0);
signal first_edge_taps_r : std_logic_vector(4 downto 0);
signal found_edge_r : std_logic;
signal found_edge_latched_r : std_logic;
signal found_edge_valid_r : std_logic;
signal found_dq_edge_r : std_logic;
signal found_first_edge_r : std_logic;
signal found_jitter_latched_r : std_logic;
signal found_second_edge_r : std_logic;
signal found_stable_eye_r : std_logic;
signal found_two_edge_r : std_logic;
signal idel_tap_cnt_cpt_r : std_logic_vector(4 downto 0);
signal idel_tap_delta_rsync_r : std_logic_vector(4 downto 0);
signal idel_tap_limit_cpt_r : std_logic;
signal idel_tap_limit_dq_r : std_logic;
signal last_tap_jitter_r : std_logic;
signal min_rsync_marg_r : std_logic_vector(4 downto 0);
signal mux_rd_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal mux_rd_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal mux_rd_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal mux_rd_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal new_cnt_clkdiv_r : std_logic;
signal new_cnt_cpt_r : std_logic;
signal old_sr_fall0_r : type_4;
signal old_sr_fall1_r : type_4;
signal old_sr_rise0_r : type_4;
signal old_sr_rise1_r : type_4;
signal old_sr_valid_r : std_logic;
signal pat_data_match_r : std_logic;
signal pat_fall0 : type_5;
signal pat_fall1 : type_5;
signal pat_match_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_fall0_and_r : std_logic;
signal pat_match_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_fall1_and_r : std_logic;
signal pat_match_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_rise0_and_r : std_logic;
signal pat_match_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal pat_match_rise1_and_r : std_logic;
signal pat_rise0 : type_5;
signal pat_rise1 : type_5;
signal pipe_wait : std_logic;
signal pol_min_rsync_marg_r : std_logic;
signal prev_found_edge_r : std_logic;
signal prev_found_edge_valid_r : std_logic;
signal prev_match_fall0_and_r : std_logic;
signal prev_match_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_fall1_and_r : std_logic;
signal prev_match_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_rise0_and_r : std_logic;
signal prev_match_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_rise1_and_r : std_logic;
signal prev_match_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal prev_match_valid_r : std_logic;
signal prev_match_valid_r1 : std_logic;
signal prev_sr_fall0_r : type_4;
signal prev_sr_fall1_r : type_4;
signal prev_sr_rise0_r : type_4;
signal prev_sr_rise1_r : type_4;
signal rd_mux_sel_r : std_logic_vector(DQS_CNT_WIDTH - 1 downto 0);
signal rd_active_posedge_r : std_logic;
signal rd_active_r : std_logic;
signal rden_wait_r : std_logic;
signal right_edge_taps_r : std_logic_vector(4 downto 0);
signal second_edge_taps_r : std_logic_vector(4 downto 0);
signal second_edge_dq_taps_r : std_logic_vector(4 downto 0);
signal sr_fall0_r : type_4;
signal sr_fall1_r : type_4;
signal sr_rise0_r : type_4;
signal sr_rise1_r : type_4;
signal sr_match_fall0_and_r : std_logic;
signal sr_match_fall0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal sr_match_fall1_and_r : std_logic;
signal sr_match_fall1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal sr_match_valid_r : std_logic;
signal sr_match_valid_r1 : std_logic;
signal sr_match_rise0_and_r : std_logic;
signal sr_match_rise0_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal sr_match_rise1_and_r : std_logic;
signal sr_match_rise1_r : std_logic_vector(DRAM_WIDTH - 1 downto 0);
signal store_sr_done_r : std_logic;
signal store_sr_r : std_logic;
signal store_sr_req : std_logic;
signal sr_valid_r : std_logic;
signal tby4_r : std_logic_vector(5 downto 0);
signal dbg_phy_clk : std_logic;
-- Debug
signal dbg_cpt_first_edge_taps : type_6;
signal dbg_cpt_second_edge_taps : type_6;
-- Declare intermediate signals for referenced outputs
signal rdlvl_clkdiv_done_1 : std_logic;
signal rdlvl_done_1 : std_logic_vector(1 downto 0);
signal rdlvl_err_2 : std_logic_vector(1 downto 0);
-- Declare intermediate signals for referenced outputs
signal rd_mux_sel_r_index : std_logic_vector(1 downto 0);
begin
-- Drive referenced outputs
rdlvl_done <= rdlvl_done_1;
rdlvl_err <= rdlvl_err_2;
rdlvl_clkdiv_done <= rdlvl_clkdiv_done_1;
--***************************************************************************
-- Debug
--***************************************************************************
dbg_phy_rdlvl(1 downto 0) <= rdlvl_start(1 downto 0);
dbg_phy_rdlvl(2) <= found_edge_r;
dbg_phy_rdlvl(3) <= pat_data_match_r;
dbg_phy_rdlvl(6 downto 4) <= cal2_state_r(2 downto 0);
dbg_phy_rdlvl(8 downto 7) <= cal2_cnt_bitslip_r(1 downto 0);
dbg_phy_rdlvl(13 downto 9) <= cal1_state_r(4 downto 0);
dbg_phy_rdlvl(20 downto 14) <= ('0' & cnt_idel_dec_cpt_r);
dbg_phy_rdlvl(21) <= found_first_edge_r;
dbg_phy_rdlvl(22) <= found_second_edge_r;
dbg_phy_rdlvl(23) <= old_sr_valid_r;
dbg_phy_rdlvl(24) <= store_sr_r;
dbg_phy_rdlvl(32 downto 25) <= (sr_fall1_r(0)(1 downto 0) & sr_rise1_r(0)(1 downto 0) &
sr_fall0_r(0)(1 downto 0) & sr_rise0_r(0)(1 downto 0));
dbg_phy_rdlvl(40 downto 33) <= (old_sr_fall1_r(0)(1 downto 0) & old_sr_rise1_r(0)(1 downto 0) &
old_sr_fall0_r(0)(1 downto 0) & old_sr_rise0_r(0)(1 downto 0));
dbg_phy_rdlvl(41) <= sr_valid_r;
dbg_phy_rdlvl(42) <= found_stable_eye_r;
dbg_phy_rdlvl(47 downto 43) <= idel_tap_cnt_cpt_r;
dbg_phy_rdlvl(48) <= idel_tap_limit_cpt_r;
dbg_phy_rdlvl(53 downto 49) <= first_edge_taps_r;
dbg_phy_rdlvl(58 downto 54) <= second_edge_taps_r;
dbg_phy_rdlvl(64 downto 59) <= tby4_r;
dbg_phy_rdlvl(67 downto 65) <= cnt_eye_size_r;
dbg_phy_rdlvl(72 downto 68) <= cal1_dq_tap_cnt_r;
dbg_phy_rdlvl(73) <= found_dq_edge_r;
dbg_phy_rdlvl(74) <= found_edge_valid_r;
gen_72width: if (DQS_CNT_WIDTH < 5) generate
dbg_phy_rdlvl(75+DQS_CNT_WIDTH-1 downto 75) <= cal1_cnt_cpt_r;
dbg_phy_rdlvl(78 downto 75+DQS_CNT_WIDTH) <= (others => '0');
dbg_phy_rdlvl(79+DQS_CNT_WIDTH-1 downto 79) <= cal2_cnt_rden_r;
dbg_phy_rdlvl(82 downto 79+DQS_CNT_WIDTH) <= (others => '0');
end generate;
gen_144width: if (DQS_CNT_WIDTH = 5) generate
dbg_phy_rdlvl(78 downto 75) <= cal1_cnt_cpt_r(DQS_CNT_WIDTH-2 downto 0);
dbg_phy_rdlvl(82 downto 79) <= cal2_cnt_rden_r(DQS_CNT_WIDTH-2 downto 0);
end generate;
dbg_phy_rdlvl(83) <= cal1_dlyce_cpt_r;
dbg_phy_rdlvl(84) <= cal1_dlyinc_cpt_r;
dbg_phy_rdlvl(85) <= found_edge_r;
dbg_phy_rdlvl(86) <= found_first_edge_r;
dbg_phy_rdlvl(91 downto 87) <= right_edge_taps_r;
dbg_phy_rdlvl(96 downto 92) <= second_edge_dq_taps_r;
dbg_phy_rdlvl(102 downto 97) <= tby4_r;
dbg_phy_rdlvl(103) <= cal_clkdiv_clkdiv_inv_r;
dbg_phy_rdlvl(104) <= cal_clkdiv_dlyce_rsync_r;
dbg_phy_rdlvl(105) <= cal_clkdiv_dlyinc_rsync_r;
dbg_phy_rdlvl(106) <= cal_clkdiv_idel_rsync_inc_r;
dbg_phy_rdlvl(107) <= pol_min_rsync_marg_r;
dbg_phy_rdlvl(111 downto 108) <= cal_clkdiv_state_r;
gen_dbg_cal_clkdiv_cnt_clkdiv_r_lt4: if (DQS_CNT_WIDTH < 4) generate
dbg_phy_rdlvl(112+DQS_CNT_WIDTH-1 downto 112) <= cal_clkdiv_cnt_clkdiv_r;
dbg_phy_rdlvl(115 downto 112+DQS_CNT_WIDTH) <= (others => '0');
end generate;
gen_dbg_cal_clkdiv_cnt_clkdiv_r_ge4: if (DQS_CNT_WIDTH >= 4) generate
dbg_phy_rdlvl(115 downto 112) <= cal_clkdiv_cnt_clkdiv_r(3 downto 0);
end generate;
dbg_phy_rdlvl(120 downto 116) <= idel_tap_delta_rsync_r;
dbg_phy_rdlvl(125 downto 121) <= min_rsync_marg_r;
gen_dbg_clkdiv_inv_r_lt9: if (DQS_WIDTH < 9) generate
dbg_phy_rdlvl(126+DQS_WIDTH-1 downto 126) <= clkdiv_inv_r;
dbg_phy_rdlvl(134 downto 126+DQS_WIDTH) <= (others => '0');
end generate;
gen_dbg_clkdiv_inv_r_ge9: if (DQS_WIDTH >= 9) generate
dbg_phy_rdlvl(134 downto 126) <= clkdiv_inv_r(8 downto 0);
end generate;
dbg_phy_rdlvl(135) <= rdlvl_clkdiv_start;
dbg_phy_rdlvl(136) <= rdlvl_clkdiv_done_1;
dbg_phy_rdlvl(255 downto 137) <= (others => '0');
--***************************************************************************
-- Debug output
--***************************************************************************
-- Record first and second edges found during CPT calibration
gen_dbg_cpt_edge : for ce_i in 0 to (DQS_WIDTH-1) generate
dbg_cpt_first_edge_cnt((5*ce_i)+4 downto (5*ce_i)) <= dbg_cpt_first_edge_taps(ce_i);
dbg_cpt_second_edge_cnt((5*ce_i)+4 downto (5*ce_i)) <= dbg_cpt_second_edge_taps(ce_i);
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
dbg_cpt_first_edge_taps(ce_i) <= (others => '0') after (TCQ)*1 ps;
dbg_cpt_second_edge_taps(ce_i) <= (others => '0') after (TCQ)*1 ps;
else
-- Record tap counts of first and second edge edges during
-- CPT calibration for each DQS group. If neither edge has
-- been found, then those taps will remain 0
if ((cal1_state_r = CAL1_CALC_IDEL) or (cal1_state_r = CAL1_RST_CPT)) then
if (found_first_edge_r = '1' and (TO_INTEGER(unsigned(cal1_cnt_cpt_r)) = ce_i)) then
dbg_cpt_first_edge_taps(ce_i) <= first_edge_taps_r after (TCQ)*1 ps;
end if;
if (found_second_edge_r = '1' and (TO_INTEGER(unsigned(cal1_cnt_cpt_r)) = ce_i)) then
dbg_cpt_second_edge_taps(ce_i) <= second_edge_taps_r after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
dbg_rd_active_dly <= cal2_rd_active_dly_r after (TCQ)*1 ps;
dbg_rd_clkdly_cnt <= cal2_clkdly_cnt_r after (TCQ)*1 ps;
end if;
end process;
-- cal2_rd_bitslip_cnt_r is only 2*DQS_WIDTH (2 bits per DQS group), but
-- is expanded to 3 bits per DQS group to maintain width compatibility with
-- previous definition of dbg_rd_bitslip_cnt (not a huge issue, should
-- align these eventually - minimize impact on debug designs)
gen_dbg_rd_bitslip : for d_i in 0 to DQS_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
dbg_rd_bitslip_cnt(3*d_i+1 downto 3*d_i) <= cal2_rd_bitslip_cnt_r(2*d_i+1 downto 2*d_i) after (TCQ)*1 ps;
dbg_rd_bitslip_cnt(3*d_i+2) <= '0' after (TCQ)*1 ps;
end if;
end process;
end generate;
--***************************************************************************
-- Data mux to route appropriate bit to calibration logic - i.e. calibration
-- is done sequentially, one bit (or DQS group) at a time
--***************************************************************************
rd_mux_sel_r_index <= rdlvl_clkdiv_done_1 & rdlvl_done_1(0);
process (clk)
begin
if (clk'event and clk = '1') then
--(* full_case, parallel_case *)
case (rd_mux_sel_r_index) is
when "00" =>
rd_mux_sel_r <= cal1_cnt_cpt_r after (TCQ)*1 ps;
when "01" =>
rd_mux_sel_r <= cal_clkdiv_cnt_clkdiv_r after (TCQ)*1 ps;
when "10" =>
rd_mux_sel_r <= cal2_cnt_rden_r after (TCQ)*1 ps; -- don't care
when "11" =>
rd_mux_sel_r <= cal2_cnt_rden_r after (TCQ)*1 ps;
when others =>
null;
end case;
end if;
end process;
-- Register outputs for improved timing.
-- NOTE: Will need to change when per-bit DQ deskew is supported.
-- Currenly all bits in DQS group are checked in aggregate
gen_mux_rd : for mux_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
mux_rd_rise0_r(mux_i) <= rd_data_rise0(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
mux_rd_fall0_r(mux_i) <= rd_data_fall0(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
mux_rd_rise1_r(mux_i) <= rd_data_rise1(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
mux_rd_fall1_r(mux_i) <= rd_data_fall1(DRAM_WIDTH*to_integer(unsigned(rd_mux_sel_r)) + mux_i) after (TCQ)*1 ps;
end if;
end process;
end generate;
--***************************************************************************
-- Demultiplexor to control IODELAY tap values
--***************************************************************************
-- Capture clock
process (clk)
begin
if (clk'event and clk = '1') then
dlyce_cpt <= (others => '0') after (TCQ)*1 ps;
dlyinc_cpt <= '0' after (TCQ)*1 ps;
if (cal1_dlyce_cpt_r = '1') then
if ((SIM_CAL_OPTION = "NONE") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) then
-- Change only specified DQS group's capture clock
dlyce_cpt(to_integer(unsigned(rd_mux_sel_r))) <= '1' after (TCQ)*1 ps;
dlyinc_cpt <= cal1_dlyinc_cpt_r after (TCQ)*1 ps;
elsif ((SIM_CAL_OPTION = "FAST_CAL") or (SIM_CAL_OPTION = "SKIP_CAL")) then
-- if simulating, and "shortcuts" for calibration enabled, apply
-- results to all other elements (i.e. assume delay on all
-- bits/bytes is same). Also do the same if skipping calibration
-- (the logic will still increment IODELAY to the "hardcoded" value)
dlyce_cpt <= (others => '1') after (TCQ)*1 ps;
dlyinc_cpt <= cal1_dlyinc_cpt_r after (TCQ)*1 ps;
end if;
elsif (DEBUG_PORT = "ON") then
-- simultaneously inc/dec all CPT idelays
if ((dbg_idel_up_all or dbg_idel_down_all or dbg_sel_all_idel_cpt) = '1') then
dlyce_cpt <= (others => (dbg_idel_up_all or dbg_idel_down_all or dbg_idel_up_cpt or dbg_idel_down_cpt)) after (TCQ)*1 ps;
dlyinc_cpt <= dbg_idel_up_all or dbg_idel_up_cpt after (TCQ)*1 ps;
else
-- select specific cpt clock for adjustment
if (to_integer(unsigned(dbg_sel_idel_cpt)) < DQS_WIDTH) then
dlyce_cpt(to_integer(unsigned(dbg_sel_idel_cpt))) <= dbg_idel_up_cpt or dbg_idel_down_cpt after (TCQ)*1 ps;
end if;
dlyinc_cpt <= dbg_idel_up_cpt after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Resync clock
process (clk)
begin
if (clk'event and clk = '1') then
dlyce_rsync <= (others => '0') after (TCQ)*1 ps;
dlyinc_rsync <= '0' after (TCQ)*1 ps;
if (cal_clkdiv_dlyce_rsync_r = '1') then
-- When shifting RSYNC, shift all BUFR IODELAYs. This is allowed
-- because only one DQS-group's data is being checked at any one
-- time, and at the end of calibration, all of the BUFR IODELAYs
-- will be reset to the starting tap value
dlyce_rsync <= (others => '1') after (TCQ)*1 ps;
dlyinc_rsync <= cal_clkdiv_dlyinc_rsync_r after (TCQ)*1 ps;
elsif (DEBUG_PORT = "ON") then
-- simultaneously inc/dec all RSYNC idelays
if ((dbg_idel_up_all or dbg_idel_down_all or dbg_sel_all_idel_rsync) = '1') then
dlyce_rsync <= (others => (dbg_idel_up_all or dbg_idel_down_all or dbg_idel_up_rsync or dbg_idel_down_rsync)) after (TCQ)*1 ps;
dlyinc_rsync <= dbg_idel_up_all or dbg_idel_up_rsync after (TCQ)*1 ps;
else
-- select specific rsync clock for adjustment
if (to_integer(unsigned(dbg_sel_idel_rsync)) < 4) then
dlyce_rsync(to_integer(unsigned(dbg_sel_idel_rsync))) <= (dbg_idel_up_rsync or dbg_idel_down_rsync) after (TCQ)*1 ps;
end if;
dlyinc_rsync <= dbg_idel_up_rsync after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- DQ parallel load tap values
-- Currently no debug port option to change DQ taps
-- NOTE: This values are not initially assigned after reset - until
-- a particular byte is being calibrated, the IDELAY dlyval values from
-- this module will be X's in simulation - this will be okay - those
-- IDELAYs won't be used until the byte is calibrated
process (clk)
begin
if (clk'event and clk = '1') then
-- If read leveling is not complete, calibration logic has complete
-- control of loading of DQ IDELAY taps
if ((SIM_CAL_OPTION = "NONE") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) then
-- Load all IDELAY value for all bits in that byte with the same
-- value. Eventually this will be changed to accomodate different
-- tap counts across the bits in a DQS group (i.e. "per-bit" cal)
for i in 0 to 4 loop
dlyval_dq_reg_r(5*to_integer(unsigned(cal1_cnt_cpt_r))+ i) <= cal1_dq_tap_cnt_r(i) after (TCQ)*1 ps;
end loop;
elsif (SIM_CAL_OPTION = "FAST_CAL") then
-- For simulation purposes, to reduce time associated with
-- calibration, calibrate only one DQS group, and load all IODELAY
-- values for all DQS groups with same value
for idx in 0 to (DQS_WIDTH-1) loop
dlyval_dq_reg_r(5*idx+4 downto 5*idx) <= cal1_dq_tap_cnt_r after (TCQ)*1 ps;
end loop;
elsif (SIM_CAL_OPTION = "SKIP_CAL") then
-- If skipping calibration altogether (only for simulation), set
-- all the DQ IDELAY delay values to 0
dlyval_dq_reg_r <= (others => '0') after (TCQ)*1 ps;
end if;
end if;
end process;
-- Register for timing (help with logic placement) - we're gonna need
-- all the help we can get
-- dlyval_dqs is assigned the value of dq taps. It is used in the PD module.
-- Changes will be made to this assignment when perbit deskew is done.
process (clk)
begin
if (clk'event and clk = '1') then
dlyval_dq <= dlyval_dq_reg_r after (TCQ)*1 ps;
dlyval_dqs <= dlyval_dq_reg_r after (TCQ)*1 ps;
end if;
end process;
--***************************************************************************
-- Generate signal used to delay calibration state machine - used when:
-- (1) IDELAY value changed
-- (2) RD_MUX_SEL value changed
-- Use when a delay is necessary to give the change time to propagate
-- through the data pipeline (through IDELAY and ISERDES, and fabric
-- pipeline stages)
--***************************************************************************
-- combine requests to modify any of the IDELAYs into one
dlyce_or <= '1' when (cal1_state_r = CAL1_IDEL_INC_DQ) else
(cal1_dlyce_cpt_r or new_cnt_cpt_r or
cal_clkdiv_dlyce_rsync_r or new_cnt_clkdiv_r);
-- NOTE: Can later recode to avoid combinational path, but be careful about
-- timing effect on main state logic
pipe_wait <= '1' when (to_integer(unsigned(cnt_pipe_wait_r)) /= (PIPE_WAIT_CNT-1)) else dlyce_or;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cnt_pipe_wait_r <= "0000" after (TCQ)*1 ps;
elsif (dlyce_or = '1') then
cnt_pipe_wait_r <= "0000" after (TCQ)*1 ps;
elsif (to_integer(unsigned(cnt_pipe_wait_r)) /= (PIPE_WAIT_CNT-1)) then
cnt_pipe_wait_r <= cnt_pipe_wait_r + "0001" after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- generate request to PHY_INIT logic to issue precharged. Required when
-- calibration can take a long time (during which there are only constant
-- reads present on this bus). In this case need to issue perioidic
-- precharges to avoid tRAS violation. This signal must meet the following
-- requirements: (1) only transition from 0->1 when prech is first needed,
-- (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rdlvl_prech_req <= '0' after (TCQ)*1 ps;
else
-- Combine requests from all stages here
rdlvl_prech_req <= cal1_prech_req_r or cal2_prech_req_r or
cal_clkdiv_prech_req_r after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
-- NOTE: Written using discrete flops, but SRL can be used if the matching
-- logic does the comparison sequentially, rather than parallel
--***************************************************************************
gen_sr : for rd_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
sr_rise0_r(rd_i) <= sr_rise0_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_rise0_r(rd_i) after (TCQ)*1 ps;
sr_fall0_r(rd_i) <= sr_fall0_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_fall0_r(rd_i) after (TCQ)*1 ps;
sr_rise1_r(rd_i) <= sr_rise1_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_rise1_r(rd_i) after (TCQ)*1 ps;
sr_fall1_r(rd_i) <= sr_fall1_r(rd_i)(RD_SHIFT_LEN - 2 downto 0) & mux_rd_fall1_r(rd_i) after (TCQ)*1 ps;
end if;
end process;
end generate;
--***************************************************************************
-- First stage calibration: Capture clock
--***************************************************************************
--*****************************************************************
-- Free-running counter to keep track of when to do parallel load of
-- data from memory
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cnt_shift_r <= (others => '0') after (TCQ)*1 ps;
sr_valid_r <= '0' after (TCQ)*1 ps;
else
if (to_integer(unsigned(cnt_shift_r)) = (RD_SHIFT_LEN-1)) then
sr_valid_r <= '1' after (TCQ)*1 ps;
cnt_shift_r <= (others => '0') after (TCQ)*1 ps;
else
sr_valid_r <= '0' after (TCQ)*1 ps;
cnt_shift_r <= cnt_shift_r + "0001" after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
--*****************************************************************
-- Logic to determine when either edge of the data eye encountered
-- Pre- and post-IDELAY update data pattern is compared, if they
-- differ, than an edge has been encountered. Currently no attempt
-- made to determine if the data pattern itself is "correct", only
-- whether it changes after incrementing the IDELAY (possible
-- future enhancement)
--*****************************************************************
store_sr_req <= cal1_store_sr_req_r or cal_clkdiv_store_sr_req_r;
-- Simple handshaking - when calib state machines want the OLD SR
-- value to get loaded, it requests for it to be loaded. One the
-- next sr_valid_r pulse, it does get loaded, and store_sr_done_r
-- is then pulsed asserted to indicate this, and we all go on our
-- merry way
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
store_sr_done_r <= '0' after (TCQ)*1 ps;
store_sr_r <= '0' after (TCQ)*1 ps;
else
store_sr_done_r <= sr_valid_r and store_sr_r;
if (store_sr_req = '1') then
store_sr_r <= '1' after (TCQ)*1 ps;
elsif ((sr_valid_r and store_sr_r) = '1') then
store_sr_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Determine if the comparison logic is putting out a valid
-- output - as soon as a request is made to load in a new value
-- for the OLD_SR shift register, the valid pipe is cleared. It
-- then gets asserted once the new value gets loaded into the
-- OLD_SR register
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
sr_match_valid_r <= '0' after (TCQ)*1 ps;
sr_match_valid_r1 <= '0' after (TCQ)*1 ps;
old_sr_valid_r <= '0' after (TCQ)*1 ps;
else
-- Flag to indicate whether data in OLD_SR register is valid
if (store_sr_req = '1') then
old_sr_valid_r <= '0' after (TCQ)*1 ps;
elsif (store_sr_done_r = '1') then
-- Immediately flush valid pipe to prevent any logic from
-- acting on compare results using previous OLD_SR data
old_sr_valid_r <= '1' after (TCQ)*1 ps;
end if;
if (store_sr_req = '1') then
sr_match_valid_r <= '0' after (TCQ)*1 ps;
sr_match_valid_r1 <= '0' after (TCQ)*1 ps;
else
sr_match_valid_r <= old_sr_valid_r and sr_valid_r after (TCQ)*1 ps;
sr_match_valid_r1 <= sr_match_valid_r after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Create valid qualifier for previous sample compare - might not
-- be needed - check previous sample compare timing
process(clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
prev_match_valid_r <= '0' after (TCQ)*1 ps;
prev_match_valid_r1 <= '0' after (TCQ)*1 ps;
else
prev_match_valid_r <= sr_valid_r after (TCQ)*1 ps;
prev_match_valid_r1 <= prev_match_valid_r after (TCQ)*1 ps;
end if;
end if;
end process;
-- Transfer current data to old data, prior to incrementing IDELAY
gen_old_sr : for z in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (sr_valid_r = '1') then
-- Load last sample (i.e. from current sampling interval)
prev_sr_rise0_r(z) <= sr_rise0_r(z) after (TCQ)*1 ps;
prev_sr_fall0_r(z) <= sr_fall0_r(z) after (TCQ)*1 ps;
prev_sr_rise1_r(z) <= sr_rise1_r(z) after (TCQ)*1 ps;
prev_sr_fall1_r(z) <= sr_fall1_r(z) after (TCQ)*1 ps;
end if;
if ((sr_valid_r and store_sr_r) = '1') then
old_sr_rise0_r(z) <= sr_rise0_r(z) after (TCQ)*1 ps;
old_sr_fall0_r(z) <= sr_fall0_r(z) after (TCQ)*1 ps;
old_sr_rise1_r(z) <= sr_rise1_r(z) after (TCQ)*1 ps;
old_sr_fall1_r(z) <= sr_fall1_r(z) after (TCQ)*1 ps;
end if;
end if;
end process;
end generate;
--*******************************************************
-- Match determination occurs over 3 cycles - pipelined for better timing
--*******************************************************
-- CYCLE1: Compare all bits in DQS grp, generate separate term for each
-- bit for each cycle of training seq. For example, if training seq = 4
-- words, and there are 8-bits per DQS group, then there is total of
-- 8*4 = 32 terms generated in this cycle
gen_sr_match : for sh_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (sr_valid_r = '1') then
-- Structure HDL such that X on data bus will result in a mismatch
-- This is required for memory models that can drive the bus with
-- X's to model uncertainty regions (e.g. Denali)
-- Check current sample vs. sample from last IODELAY tap
--if (sr_rise0_r(sh_i) = old_sr_rise0_r(sh_i)) then
if (ADVANCE_COMP(sr_rise0_r(sh_i),old_sr_rise0_r(sh_i)) = '1') then
sr_match_rise0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_rise0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall0_r(sh_i) = old_sr_fall0_r(sh_i)) then
if (ADVANCE_COMP(sr_fall0_r(sh_i),old_sr_fall0_r(sh_i)) = '1') then
sr_match_fall0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_fall0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_rise1_r(sh_i) = old_sr_rise1_r(sh_i)) then
if (ADVANCE_COMP(sr_rise1_r(sh_i),old_sr_rise1_r(sh_i)) = '1') then
sr_match_rise1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_rise1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall1_r(sh_i) = old_sr_fall1_r(sh_i)) then
if (ADVANCE_COMP(sr_fall1_r(sh_i),old_sr_fall1_r(sh_i)) = '1') then
sr_match_fall1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
sr_match_fall1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
-- Check current sample vs. sample from current IODELAY tap
--if (sr_rise0_r(sh_i) = prev_sr_rise0_r(sh_i)) then
if (ADVANCE_COMP(sr_rise0_r(sh_i),prev_sr_rise0_r(sh_i)) = '1') then
prev_match_rise0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_rise0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall0_r(sh_i) = prev_sr_fall0_r(sh_i)) then
if (ADVANCE_COMP(sr_fall0_r(sh_i),prev_sr_fall0_r(sh_i)) = '1') then
prev_match_fall0_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_fall0_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_rise1_r(sh_i) = prev_sr_rise1_r(sh_i)) then
if (ADVANCE_COMP(sr_rise1_r(sh_i),prev_sr_rise1_r(sh_i)) = '1') then
prev_match_rise1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_rise1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
--if (sr_fall1_r(sh_i) = prev_sr_fall1_r(sh_i)) then
if (ADVANCE_COMP(sr_fall1_r(sh_i),prev_sr_fall1_r(sh_i)) = '1') then
prev_match_fall1_r(sh_i) <= '1' after (TCQ)*1 ps;
else
prev_match_fall1_r(sh_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
end generate;
-- CYCLE 2: Logical AND match terms from all bits in DQS group together
process (clk)
begin
if (clk'event and clk = '1') then
-- Check current sample vs. sample from last IODELAY tap
sr_match_rise0_and_r <= AND_BR(sr_match_rise0_r) after (TCQ)*1 ps;
sr_match_fall0_and_r <= AND_BR(sr_match_fall0_r) after (TCQ)*1 ps;
sr_match_rise1_and_r <= AND_BR(sr_match_rise1_r) after (TCQ)*1 ps;
sr_match_fall1_and_r <= AND_BR(sr_match_fall1_r) after (TCQ)*1 ps;
-- Check current sample vs. sample from current IODELAY tap
prev_match_rise0_and_r <= AND_BR(prev_match_rise0_r) after (TCQ)*1 ps;
prev_match_fall0_and_r <= AND_BR(prev_match_fall0_r) after (TCQ)*1 ps;
prev_match_rise1_and_r <= AND_BR(prev_match_rise1_r) after (TCQ)*1 ps;
prev_match_fall1_and_r <= AND_BR(prev_match_fall1_r) after (TCQ)*1 ps;
end if;
end process;
-- CYCLE 3: During the third cycle of compare, the comparison output
-- over all the cycles of the training sequence is output
process (clk)
begin
if (clk'event and clk = '1') then
-- Found edge only asserted if OLD_SR shift register contents are valid
-- and a match has not occurred - since we're using this shift register
-- scheme, we need to qualify the match with the valid signals because
-- the "old" and "current" shift register contents can't be compared on
-- every clock cycle, only when the shift register is "fully loaded"
found_edge_r <= ((not(sr_match_rise0_and_r) or not(sr_match_fall0_and_r) or
not(sr_match_rise1_and_r) or not(sr_match_fall1_and_r)) and
(sr_match_valid_r1)) after (TCQ)*1 ps;
found_edge_valid_r <= sr_match_valid_r1 after (TCQ)*1 ps;
prev_found_edge_r <= ((not(prev_match_rise0_and_r) or not(prev_match_fall0_and_r) or
not(prev_match_rise1_and_r) or not(prev_match_fall1_and_r)) and
(prev_match_valid_r1)) after (TCQ)*1 ps;
prev_found_edge_valid_r <= prev_match_valid_r1 after (TCQ)*1 ps;
end if;
end process;
--*******************************************************
-- Counters for tracking # of samples compared
-- For each comparision point (i.e. to determine if an edge has
-- occurred after each IODELAY increment when read leveling),
-- multiple samples are compared in order to average out the effects
-- of jitter. If any one of these samples is different than the "old"
-- sample corresponding to the previous IODELAY value, then an edge
-- is declared to be detected.
--*******************************************************
-- Two counters are used to keep track of # of samples compared, in
-- order to make it easier to meeting timing on these paths
-- First counter counts the number of samples directly
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_cnt0_r <= (others => '0') after (TCQ)*1 ps;
else
if (detect_edge_start_r = '1') then
detect_edge_cnt0_r <= (others => '0') after (TCQ)*1 ps;
elsif (found_edge_valid_r = '1') then
detect_edge_cnt0_r <= detect_edge_cnt0_r + '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_cnt1_en_r <= '0' after (TCQ)*1 ps;
else
if (((SIM_CAL_OPTION = "FAST_CAL") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) and (detect_edge_cnt0_r = X"001")) then
-- Bypass multi-sampling for stage 1 when simulating with
-- either fast calibration option, or with multi-sampling
-- disabled
detect_edge_cnt1_en_r <= '1' after (TCQ)*1 ps;
elsif (detect_edge_cnt0_r = DETECT_EDGE_SAMPLE_CNT0) then
detect_edge_cnt1_en_r <= '1' after (TCQ)*1 ps;
else
detect_edge_cnt1_en_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
-- Counter #2
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_cnt1_r <= (others => '0') after (TCQ)*1 ps;
else
if (detect_edge_start_r = '1') then
detect_edge_cnt1_r <= (others => '0') after (TCQ)*1 ps;
elsif (detect_edge_cnt1_en_r = '1') then
detect_edge_cnt1_r <= detect_edge_cnt1_r + '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
detect_edge_done_r <= '0' after (TCQ)*1 ps;
else
if (detect_edge_start_r = '1') then
detect_edge_done_r <= '0' after (TCQ)*1 ps;
elsif (((SIM_CAL_OPTION = "FAST_CAL") or (SIM_CAL_OPTION = "FAST_WIN_DETECT")) and (detect_edge_cnt1_r = X"001")) then
-- Bypass multi-sampling for stage 1 when simulating with
-- either fast calibration option, or with multi-sampling
-- disabled
detect_edge_done_r <= '1' after (TCQ)*1 ps;
elsif (detect_edge_cnt1_r = DETECT_EDGE_SAMPLE_CNT1) then
detect_edge_done_r <= '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
--*****************************************************************
-- Keep track of how long we've been in the same data eye
-- (i.e. over how many taps we have not yet found an eye)
--*****************************************************************
-- An actual edge occurs when either: (1) difference in read data between
-- current IODELAY tap and previous IODELAY tap (yes, this is confusing,
-- since this condition is represented by found_edge_latched_r), (2) if
-- the previous IODELAY tap read data was jittering (in which case it
-- doesn't matter what the current IODELAY tap sample looks like)
cal1_found_edge <= found_edge_latched_r or last_tap_jitter_r;
process (clk)
begin
if (clk'event and clk = '1') then
-- Reset to 0 every time we begin processing a new DQS group
if ((cal1_state_r = CAL1_IDLE) or (cal1_state_r = CAL1_NEXT_DQS)) then
cnt_eye_size_r <= "000" after (TCQ)*1 ps;
found_stable_eye_r <= '0' after (TCQ)*1 ps;
last_tap_jitter_r <= '0' after (TCQ)*1 ps;
found_edge_latched_r <= '0' after (TCQ)*1 ps;
found_jitter_latched_r <= '0' after (TCQ)*1 ps;
elsif (not(cal1_state_r = CAL1_DETECT_EDGE)) then
-- Reset "latched" signals before looking for an edge
found_edge_latched_r <= '0' after (TCQ)*1 ps;
found_jitter_latched_r <= '0' after (TCQ)*1 ps;
elsif (cal1_state_r = CAL1_DETECT_EDGE) then
if (not(detect_edge_done_r = '1')) then
-- While sampling:
-- Latch if we've found an edge (i.e. difference between current
-- and previous IODELAY tap), and/or jitter (difference between
-- current and previous sample - on the same IODELAY tap). It is
-- possible to find an edge, and not jitter, but not vice versa
if (found_edge_r = '1') then
found_edge_latched_r <= '1' after (TCQ)*1 ps;
end if;
if (prev_found_edge_r = '1') then
found_jitter_latched_r <= '1' after (TCQ)*1 ps;
end if;
else
-- Once the sample interval is over, it's time for housekeeping:
-- If jitter found during current tap, record for future compares
last_tap_jitter_r <= found_jitter_latched_r after (TCQ)*1 ps;
-- If we found an edge, or if the previous IODELAY tap had jitter
-- then reset stable window counter to 0 - obviously we're not in
-- the data valid window. Note that we care about whether jitter
-- occurred during the previous tap because it's possible to not
-- find an edge (in terms of how it's determined in found_edge_r)
-- even though jitter occured during the previous tap.
if (cal1_found_edge = '1') then
cnt_eye_size_r <= "000" after (TCQ)*1 ps;
found_stable_eye_r <= '0' after (TCQ)*1 ps;
else
-- Otherwise, everytime we look for an edge, and don't find
-- one, increment counter until minimum eye size encountered -
-- note this counter does not track the eye size, but only if
-- it exceeded minimum size
if (to_integer(unsigned(cnt_eye_size_r)) = (MIN_EYE_SIZE-1)) then
found_stable_eye_r <= '1' after (TCQ)*1 ps;
else
found_stable_eye_r <= '0' after (TCQ)*1 ps;
cnt_eye_size_r <= cnt_eye_size_r + '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end if;
end process;
--*****************************************************************
-- keep track of edge tap counts found, and current capture clock
-- tap count
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
idel_tap_cnt_cpt_r <= (others => '0') after (TCQ)*1 ps;
idel_tap_limit_cpt_r <= '0' after (TCQ)*1 ps;
else
if (new_cnt_cpt_r = '1') then
idel_tap_cnt_cpt_r <= "00000" after (TCQ)*1 ps;
idel_tap_limit_cpt_r <= '0' after (TCQ)*1 ps;
elsif (cal1_dlyce_cpt_r = '1') then
if (cal1_dlyinc_cpt_r = '1') then
idel_tap_cnt_cpt_r <= idel_tap_cnt_cpt_r + '1' after (TCQ)*1 ps;
else
-- Assert if tap limit has been reached
idel_tap_cnt_cpt_r <= idel_tap_cnt_cpt_r - '1' after (TCQ)*1 ps;
end if;
if ((to_integer(unsigned(idel_tap_cnt_cpt_r)) = (IODELAY_TAP_LEN-2)) and (cal1_dlyinc_cpt_r = '1')) then
idel_tap_limit_cpt_r <= '1' after (TCQ)*1 ps;
else
idel_tap_limit_cpt_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end process;
--*****************************************************************
-- keep track of when DQ tap limit is reached
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
idel_tap_limit_dq_r <= '0' after (TCQ)*1 ps;
else
if (new_cnt_cpt_r = '1') then
idel_tap_limit_dq_r <= '0' after (TCQ)*1 ps;
elsif (to_integer(unsigned(cal1_dq_tap_cnt_r)) = (IODELAY_TAP_LEN-1)) then
idel_tap_limit_dq_r <= '1' after (TCQ)*1 ps;
end if;
end if;
end if;
end process;
--*****************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal1_cnt_cpt_r <= (others => '0') after (TCQ)*1 ps;
cal1_dlyce_cpt_r <= '0' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
cal1_dq_taps_inc_r <= '0' after (TCQ)*1 ps;
cal1_prech_req_r <= '0' after (TCQ)*1 ps;
cal1_store_sr_req_r <= '0' after (TCQ)*1 ps;
cal1_state_r <= CAL1_IDLE after (TCQ)*1 ps;
cnt_idel_dec_cpt_r <= "XXXXXX" after (TCQ)*1 ps;
cnt_idel_inc_cpt_r <= "XXXXX" after (TCQ)*1 ps;
cnt_idel_skip_idel_r<= "XXXXX" after (TCQ)*1 ps;
detect_edge_start_r <= '0' after (TCQ)*1 ps;
found_dq_edge_r <= '0' after (TCQ)*1 ps;
found_two_edge_r <= '0' after (TCQ)*1 ps;
found_first_edge_r <= '0' after (TCQ)*1 ps;
found_second_edge_r <= '0' after (TCQ)*1 ps;
first_edge_taps_r <= "XXXXX" after (TCQ)*1 ps;
new_cnt_cpt_r <= '0' after (TCQ)*1 ps;
rdlvl_done_1(0) <= '0' after (TCQ)*1 ps;
rdlvl_err_2(0) <= '0' after (TCQ)*1 ps;
right_edge_taps_r <= "XXXXX" after (TCQ)*1 ps;
second_edge_taps_r <= "XXXXX" after (TCQ)*1 ps;
second_edge_dq_taps_r <= "XXXXX" after (TCQ)*1 ps;
else
-- default (inactive) states for all "pulse" outputs
cal1_prech_req_r <= '0' after (TCQ)*1 ps;
cal1_dlyce_cpt_r <= '0' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
cal1_store_sr_req_r <= '0' after (TCQ)*1 ps;
detect_edge_start_r <= '0' after (TCQ)*1 ps;
new_cnt_cpt_r <= '0' after (TCQ)*1 ps;
case (cal1_state_r) is
when CAL1_IDLE =>
if ((rdlvl_start(0)) = '1') then
if (SIM_CAL_OPTION = "SKIP_CAL") then
-- "Hardcoded" calibration option
cnt_idel_skip_idel_r <= std_logic_vector(to_unsigned(TBY4_TAPS, 5)) after (TCQ)*1 ps;
cal1_state_r <= CAL1_SKIP_RDLVL_INC_IDEL after (TCQ)*1 ps;
else
new_cnt_cpt_r <= '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Wait for various MUXes associated with a new DQS group to
-- change - also gives time for the read data shift register
-- to load with the updated data for the new DQS group
when CAL1_NEW_DQS_WAIT =>
if (pipe_wait = '0') then
cal1_state_r <= CAL1_IDEL_STORE_FIRST after (TCQ)*1 ps;
end if;
-- When first starting calibration for a DQS group, save the
-- current value of the read data shift register, and use this
-- as a reference. Note that for the first iteration of the
-- edge detection loop, we will in effect be checking for an edge
-- at IODELAY taps = 0 - normally, we are comparing the read data
-- for IODELAY taps = N, with the read data for IODELAY taps = N-1
-- An edge can only be found at IODELAY taps = 0 if the read data
-- is changing during this time (possible due to jitter)
when CAL1_IDEL_STORE_FIRST =>
cal1_store_sr_req_r <= '1' after (TCQ)*1 ps;
detect_edge_start_r <= '1' after (TCQ)*1 ps;
if (store_sr_done_r = '1') then
if (cal1_dq_taps_inc_r = '1') then -- if using dq taps
cal1_state_r <= CAL1_DETECT_EDGE_DQ after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_DETECT_EDGE after (TCQ)*1 ps;
end if;
end if;
-- Check for presence of data eye edge
when CAL1_DETECT_EDGE =>
if (detect_edge_done_r = '1') then
if (cal1_found_edge = '1') then
-- Sticky bit - asserted after we encounter an edge, although
-- the current edge may not be considered the "first edge" this
-- just means we found at least one edge
found_first_edge_r <= '1' after (TCQ)*1 ps;
-- For use during "low-frequency" edge detection:
-- Prevent underflow if we find an edge right away - at any
-- rate, if we do, and later we don't find a second edge by
-- using DQ taps, then we're running at a very low
-- frequency, and we really don't care about whether the
-- first edge found is a "left" or "right" edge - we have
-- more margin to absorb any inaccuracy
if (found_first_edge_r = '0') then
if (idel_tap_cnt_cpt_r = "00000") then
right_edge_taps_r <= "00000" after (TCQ)*1 ps;
else
right_edge_taps_r <= (idel_tap_cnt_cpt_r - '1') after (TCQ)*1 ps;
end if;
end if;
-- Both edges of data valid window found:
-- If we've found a second edge after a region of stability
-- then we must have just passed the second ("right" edge of
-- the window. Record this second_edge_taps = current tap-1,
-- because we're one past the actual second edge tap, where
-- the edge taps represent the extremes of the data valid
-- window (i.e. smallest & largest taps where data still valid
if ((found_first_edge_r and found_stable_eye_r) = '1') then
found_second_edge_r <= '1' after (TCQ)*1 ps;
second_edge_taps_r <= idel_tap_cnt_cpt_r - '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_CALC_IDEL after (TCQ)*1 ps;
else
-- Otherwise, an edge was found (just not the "second" edge)
-- then record current tap count - this may be the "left"
-- edge of the current data valid window
first_edge_taps_r <= idel_tap_cnt_cpt_r after (TCQ)*1 ps;
-- If we haven't run out of taps, then keep incrementing
if (idel_tap_limit_cpt_r = '0') then
cal1_state_r <= CAL1_IDEL_STORE_OLD after (TCQ)*1 ps;
else
-- If we ran out of taps moving the capture clock, and we
-- haven't found second edge, then try to find edges by
-- moving the DQ IODELAY taps
cal1_state_r <= CAL1_RST_CPT after (TCQ)*1 ps;
-- Using this counter to reset the CPT taps to zero
-- taps + any PD taps
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN-1), 6)) after (TCQ)*1 ps;
end if;
end if;
else
-- Otherwise, if we haven't found an edge....
if (idel_tap_limit_cpt_r = '0') then
-- If we still have taps left to use, then keep incrementing
cal1_state_r <= CAL1_IDEL_STORE_OLD after (TCQ)*1 ps;
else
-- If we ran out of taps moving the capture clock, and we
-- haven't found even one or second edge, then try to find
-- edges by moving the DQ IODELAY taps
cal1_state_r <= CAL1_RST_CPT after (TCQ)*1 ps;
-- Using this counter to reset the CPT taps to zero
-- taps + any PD taps
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN-1), 6)) after (TCQ)*1 ps;
end if;
end if;
end if;
-- Store the current read data into the read data shift register
-- before incrementing the tap count and doing this again
when CAL1_IDEL_STORE_OLD =>
cal1_store_sr_req_r <= '1' after (TCQ)*1 ps;
if (store_sr_done_r = '1') then
if (cal1_dq_taps_inc_r = '1') then -- if using dq taps
cal1_state_r <= CAL1_IDEL_INC_DQ after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_IDEL_INC_CPT after (TCQ)*1 ps;
end if;
end if;
-- Increment IDELAY for both capture and resync clocks
when CAL1_IDEL_INC_CPT =>
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_IDEL_INC_CPT_WAIT after (TCQ)*1 ps;
-- Wait for IDELAY for both capture and resync clocks, and internal
-- nodes within ISERDES to settle, before checking again for an edge
when CAL1_IDEL_INC_CPT_WAIT =>
detect_edge_start_r <= '1' after (TCQ)*1 ps;
if (pipe_wait = '0') then
cal1_state_r <= CAL1_DETECT_EDGE after (TCQ)*1 ps;
end if;
-- Calculate final value of IDELAY. At this point, one or both
-- edges of data eye have been found, and/or all taps have been
-- exhausted looking for the edges
-- NOTE: We're calculating the amount to decrement by, not the
-- absolute setting for DQ IDELAY
when CAL1_CALC_IDEL =>
--*******************************************************
-- Now take care of IDELAY for capture clock:
-- Explanation of calculations:
-- 1. If 2 edges found, final IDELAY value =
-- TAPS = FE_TAPS + ((SE_TAPS-FE_TAPS)/2)
-- 2. If 1 edge found, final IDELAY value is either:
-- TAPS = FE_TAPS - TBY4_TAPS, or
-- TAPS = FE_TAPS + TBY4_TAPS
-- Depending on which is achievable without overflow
-- (and with bias toward having fewer taps)
-- 3. If no edges found, then final IDELAY value is:
-- TAPS = 15
-- This is the best we can do with the information we
-- have it guarantees we have at least 15 taps of
-- margin on either side of calibration point
-- How the final IDELAY tap is reached:
-- 1. If 2 edges found, current tap count = SE_TAPS + 1
-- * Decrement by [(SE_TAPS-FE_TAPS)/2] + 1
-- 2. If 1 edge found, current tap count = 31
-- * Decrement by 31 - FE_TAPS - TBY4, or
-- * Decrement by 31 - FE_TAPS + TBY4
-- 3. If no edges found
-- * Decrement by 16
--*******************************************************
-- CASE1: If 2 edges found.
-- Only CASE1 will be true. Due to the low frequency fixes
-- the SM will not transition to this state when two edges are not
-- found.
if (found_second_edge_r = '1') then
-- SYNTHESIS_NOTE: May want to pipeline this operation
-- over multiple cycles for better timing. If so, need
-- to add delay state in CAL1 state machine
cnt_idel_dec_cpt_r <= calc_cnt_idel_dec_cpt(second_edge_taps_r,first_edge_taps_r) after (TCQ)*1 ps;
-- CASE 2: 1 edge found
-- NOTE: Need to later add logic to prevent decrementing below 0
elsif (found_first_edge_r = '1') then
if ( to_integer(unsigned(first_edge_taps_r)) >= (IODELAY_TAP_LEN/2) and
((to_integer(unsigned(first_edge_taps_r)) + TBY4_TAPS) < (IODELAY_TAP_LEN - 1)) ) then
-- final IDELAY value = [FIRST_EDGE_TAPS-CLK_MEM_PERIOD/2]
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned(((IODELAY_TAP_LEN-1) -
to_integer(unsigned(first_edge_taps_r)) - TBY4_TAPS), 6)) after (TCQ)*1 ps;
else
-- final IDELAY value = [FIRST_EDGE_TAPS+CLK_MEM_PERIOD/2]
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned(((IODELAY_TAP_LEN-1) -
to_integer(unsigned(first_edge_taps_r)) + TBY4_TAPS), 6)) after (TCQ)*1 ps;
end if;
else
-- CASE 3: No edges found, decrement by half tap length
cnt_idel_dec_cpt_r <= std_logic_vector(to_unsigned(IODELAY_TAP_LEN/2, 6)) after (TCQ)*1 ps;
end if;
-- Now use the value we just calculated to decrement CPT taps
-- to the desired calibration point
cal1_state_r <= CAL1_IDEL_DEC_CPT after (TCQ)*1 ps;
-- decrement capture clock IDELAY for final adjustment - center
-- capture clock in middle of data eye. This adjustment will occur
-- only when both the edges are found usign CPT taps. Must do this
-- incrementally to avoid clock glitching (since CPT drives clock
-- divider within each ISERDES)
when CAL1_IDEL_DEC_CPT =>
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
-- once adjustment is complete, we're done with calibration for
-- this DQS, repeat for next DQS
cnt_idel_dec_cpt_r <= cnt_idel_dec_cpt_r - "000001" after (TCQ)*1 ps;
if ((cnt_idel_dec_cpt_r) = "1") then
cal1_state_r <= CAL1_IDEL_PD_ADJ after (TCQ)*1 ps;
end if;
-- Determine whether we're done, or have more DQS's to calibrate
-- Also request precharge after every byte, as appropriate
when CAL1_NEXT_DQS =>
cal1_prech_req_r <= '1' after (TCQ)*1 ps;
-- Prepare for another iteration with next DQS group
found_dq_edge_r <= '0' after (TCQ)*1 ps;
found_two_edge_r <= '0' after (TCQ)*1 ps;
found_first_edge_r <= '0' after (TCQ)*1 ps;
found_second_edge_r<= '0' after (TCQ)*1 ps;
cal1_dq_taps_inc_r <= '0' after (TCQ)*1 ps;
-- Wait until precharge that occurs in between calibration of
-- DQS groups is finished
if (prech_done = '1') then
if ((to_integer(unsigned(cal1_cnt_cpt_r)) >= (DQS_WIDTH-1)) or (SIM_CAL_OPTION = "FAST_CAL")) then
cal1_state_r <= CAL1_DONE after (TCQ)*1 ps;
else
-- Process next DQS group
new_cnt_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
cal1_cnt_cpt_r <= cal1_cnt_cpt_r + '1' after (TCQ)*1 ps;
cal1_state_r <= CAL1_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
when CAL1_RST_CPT =>
cal1_dq_taps_inc_r <= '1' after (TCQ)*1 ps;
-- If we never found even one edge by varying CPT taps, then
-- as an approximation set first edge tap indicators to 31. This
-- will be used later in the low-frequency portion of calibration
if (found_first_edge_r = '0') then
first_edge_taps_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN- 1), 5)) after (TCQ)*1 ps;
right_edge_taps_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN- 1), 5)) after (TCQ)*1 ps;
end if;
if ((cnt_idel_dec_cpt_r) = "000000") then
-- once the decerement is done. Go back to the CAL1_NEW_DQS_WAIT
-- state to load the correct data for comparison and to start
-- with DQ taps.
cal1_state_r <= CAL1_NEW_DQS_WAIT after (TCQ)*1 ps;
-- Start with a DQ tap value of 0
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
else
-- decrement both CPT taps to initial value.
-- DQ IODELAY taps will be used to find the edges
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '0' after (TCQ)*1 ps;
cnt_idel_dec_cpt_r <= cnt_idel_dec_cpt_r - "000001" after (TCQ)*1 ps;
end if;
-- When two edges are not found using CPT taps, finding edges
-- using DQ taps.
when CAL1_DETECT_EDGE_DQ =>
if (detect_edge_done_r = '1') then
-- when using DQ taps make sure the window size is atleast 10.
-- DQ taps used only in low frequency designs.
if (((found_edge_r)) = '1' and ((found_first_edge_r = '0') or (tby4_r > "000101"))) then
-- Sticky bit - asserted after we encounter first edge
-- If we've found a second edge(using dq taps) after a region
-- of stability ( using tby4_r count) then this must be the
-- second ("using dq taps") edge of the window
found_dq_edge_r <= '1' after (TCQ)*1 ps;
found_two_edge_r <= found_first_edge_r after (TCQ)*1 ps;
cal1_state_r <= CAL1_CALC_IDEL_DQ after (TCQ)*1 ps;
-- Recording the dq taps when an edge is found. Account for
-- the case when an edge is found at DQ IODELAY = 0 taps -
-- possible because of jitter
if (not(cal1_dq_tap_cnt_r = "00000")) then
second_edge_dq_taps_r <= (cal1_dq_tap_cnt_r - '1') after (TCQ)*1 ps;
else
second_edge_dq_taps_r <= "00000" after (TCQ)*1 ps;
end if;
else
-- No more DQ taps to increment - set left edge tap distance
-- to 31 as an approximation, and move on to figuring out
-- what needs to be done to center (or approximately center)
-- sampling point in middle of read window
if (idel_tap_limit_dq_r = '1') then
cal1_state_r <= CAL1_CALC_IDEL_DQ after (TCQ)*1 ps;
second_edge_dq_taps_r <= std_logic_vector(to_unsigned((IODELAY_TAP_LEN- 1), 5)) after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_IDEL_STORE_OLD after (TCQ)*1 ps;
end if;
end if;
end if;
when CAL1_IDEL_INC_DQ =>
cal1_dq_tap_cnt_r <= cal1_dq_tap_cnt_r + "00001" after (TCQ)*1 ps;
cal1_state_r <= CAL1_IDEL_INC_DQ_WAIT after (TCQ)*1 ps;
-- Wait for IDELAY for DQ, and internal nodes within ISERDES
-- to settle, before checking again for an edge
when CAL1_IDEL_INC_DQ_WAIT =>
detect_edge_start_r <= '1' after (TCQ)*1 ps;
if (pipe_wait = '0') then
cal1_state_r <= CAL1_DETECT_EDGE_DQ after (TCQ)*1 ps;
end if;
when CAL1_CALC_IDEL_DQ =>
cal1_state_r <= CAL1_IDEL_INC_DQ_CPT after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= "00000" after (TCQ)*1 ps;
cnt_idel_inc_cpt_r <= "00000" after (TCQ)*1 ps;
--------------------------------------------------------------
-- Determine whether to move DQ or CPT IODELAY taps to best
-- position sampling point in data valid window. In general,
-- we want to avoid setting DQ IODELAY taps to a nonzero value
-- in order to avoid adding IODELAY pattern-dependent jitter.
--------------------------------------------------------------
-- At this point, we have the following products of calibration:
-- 1. right_edge_taps_r: distance in IODELAY taps from start
-- position to right margin of current data valid window.
-- Measured using CPT IODELAY.
-- 2. first_edge_taps_r: distance in IODELAY taps from start
-- position to start of left edge of next data valid window.
-- Note that {first_edge_taps_r - right_edge_taps_r} = width
-- of the uncertainty or noise region between consecutive
-- data eyes. Measured using CPT IODELAY.
-- 3. second_edge_dq_taps_r: distance in IODELAY taps from left
-- edge of current data valid window. Measured using DQ
-- IODELAY.
-- 4. tby4_r: half the width of the eye as calculated by
-- {second_edge_dq_taps_r + first_edge_taps_r}
-- ------------------------------------------------------------
-- If two edges are found (one each from moving CPT, and DQ
-- IODELAYs), then the following cases are considered for setting
-- final DQ and CPT delays (in the following order):
-- 1. second_edge_dq_taps_r <= tby4_r:
-- * incr. CPT taps by {second_edge_dq_taps_r - tby4_r}
-- this means that there is more taps available to the right
-- of the starting position
-- 2. first_edge_taps_r + tby4_r <= 31 taps (IODELAY length)
-- * incr CPT taps by {tby4_r}
-- this means we have enough CPT taps available to us to
-- position the sampling point in the middle of the next
-- sampling window. Alternately, we could have instead
-- positioned ourselves in the middle of the current window
-- by using DQ taps, but if possible avoid using DQ taps
-- because of pattern-dependent jitter
-- 3. otherwise, our only recourse is to move DQ taps in order
-- to center the sampling point in the middle of the current
-- data valid window
-- * set DQ taps to {tby4_r - right_edge_taps_r}
-- ------------------------------------------------------------
-- Note that the case where only one edge is found, either using
-- CPT or DQ IODELAY taps is a subset of the above 3 cases, which
-- can be approximated by setting either right_edge_taps_r = 31,
-- or second_edge_dq_taps_r = 31. This doesn't result in an exact
-- centering, but this will only occur at an extremely low
-- frequency, and exact centering is not required
-- ------------------------------------------------------------
if (('0' & second_edge_dq_taps_r) <= tby4_r) then
cnt_idel_inc_cpt_r <= subtract_vectors(tby4_r, second_edge_dq_taps_r) after (TCQ)*1 ps;
elsif ((('0' & first_edge_taps_r) + tby4_r) <= std_logic_vector(to_unsigned(IODELAY_TAP_LEN - 1, 6))) then
cnt_idel_inc_cpt_r <= add_vectors(tby4_r, first_edge_taps_r) after (TCQ)*1 ps;
else
cal1_dq_tap_cnt_r <= subtract_vectors(tby4_r, right_edge_taps_r) after (TCQ)*1 ps;
end if;
-- increment capture clock IDELAY for final adjustment - center
-- capture clock in middle of data eye. This state transition will
-- occur when only one edge or no edge is found using CPT taps
when CAL1_IDEL_INC_DQ_CPT =>
if (cnt_idel_inc_cpt_r = "00000") then
-- once adjustment is complete, we're done with calibration for
-- this DQS, repeat for next DQS.
cal1_state_r <= CAL1_IDEL_PD_ADJ after (TCQ)*1 ps;
else
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cnt_idel_inc_cpt_r <= cnt_idel_inc_cpt_r - '1' after (TCQ)*1 ps;
end if;
when CAL1_IDEL_PD_ADJ =>
-- If CPT is < than half the required PD taps then move the
-- CPT taps the DQ taps togather
if (to_integer(unsigned(idel_tap_cnt_cpt_r)) < PD_HALF_TAP) then
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dq_tap_cnt_r <= cal1_dq_tap_cnt_r + "00001" after (TCQ)*1 ps;
else
cal1_state_r <= CAL1_NEXT_DQS after (TCQ)*1 ps;
end if;
-- Done with this stage of calibration
-- if used, allow DEBUG_PORT to control taps
when CAL1_DONE =>
rdlvl_done_1(0) <= '1' after (TCQ)*1 ps;
-- Used for simulation only - hardcode IDELAY values for all rdlvl
-- associated IODELAYs - kind of a cheesy way of providing for
-- simulation, but I don't feel like modifying PHY_DQ_IOB to add
-- extra parameters just for simulation. This part shouldn't get
-- synthesized.
when CAL1_SKIP_RDLVL_INC_IDEL =>
cal1_dlyce_cpt_r <= '1' after (TCQ)*1 ps;
cal1_dlyinc_cpt_r <= '1' after (TCQ)*1 ps;
cnt_idel_skip_idel_r <= cnt_idel_skip_idel_r - '1' after (TCQ)*1 ps;
if (cnt_idel_skip_idel_r = "00001") then
cal1_state_r <= CAL1_DONE after (TCQ)*1 ps;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
--***************************************************************************
-- Calculates the window size during calibration.
-- Value is used only when two edges are not found using the CPT taps.
-- cal1_dq_tap_cnt_r deceremented by 1 to account for the correct window.
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (cal1_dq_tap_cnt_r > "00000") then
tby4_r <= std_logic_vector(unsigned(('0' & cal1_dq_tap_cnt_r) + ('0' & right_edge_taps_r) - 1) srl 1) after (TCQ)*1 ps;
else
tby4_r <= std_logic_vector(unsigned(('0' & cal1_dq_tap_cnt_r) + ('0' & right_edge_taps_r)) srl 1) after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- Stage 2 calibration: Read Enable
-- Read enable calibration determines the "round-trip" time (in # of CLK
-- cycles) between when a read command is issued by the controller, and
-- when the corresponding read data is synchronized by into the CLK domain
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
rd_active_r <= rdlvl_rd_active after (TCQ)*1 ps;
rd_active_posedge_r <= rdlvl_rd_active and not(rd_active_r) after (TCQ)*1 ps;
end if;
end process;
--*****************************************************************
-- Expected data pattern when properly aligned through bitslip
-- Based on pattern of ({rise,fall}) =
-- 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
-- Examining only the LSb of each DQS group, pattern is =
-- bit3: 1, 0, 1, 0, 0, 1, 1, 0
-- bit2: 1, 0, 0, 1, 1, 0, 0, 1
-- bit1: 1, 0, 1, 0, 0, 1, 0, 1
-- bit0: 1, 0, 0, 1, 1, 0, 1, 0
-- Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
-- and the actual training pattern contents change
--*****************************************************************
pat_rise0(3) <= "10";
pat_fall0(3) <= "01";
pat_rise1(3) <= "11";
pat_fall1(3) <= "00";
pat_rise0(2) <= "11";
pat_fall0(2) <= "00";
pat_rise1(2) <= "00";
pat_fall1(2) <= "11";
pat_rise0(1) <= "10";
pat_fall0(1) <= "01";
pat_rise1(1) <= "10";
pat_fall1(1) <= "01";
pat_rise0(0) <= "11";
pat_fall0(0) <= "00";
pat_rise1(0) <= "01";
pat_fall1(0) <= "10";
--*****************************************************************
-- Do not need to look at sr_valid_r - the pattern can occur anywhere
-- during the shift of the data shift register - as long as the order
-- of the bits in the training sequence is correct. Each bit of each
-- byte is compared to expected pattern - this is not strictly required.
-- This was done to prevent (and "drastically decrease") the chance that
-- invalid data clocked in when the DQ bus is tri-state (along with a
-- combination of the correct data) will resemble the expected data
-- pattern. A better fix for this is to change the training pattern and/or
-- make the pattern longer.
--*****************************************************************
gen_pat_match : for pt_i in 0 to DRAM_WIDTH-1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (sr_rise0_r(pt_i) = pat_rise0(pt_i mod 4)) then
pat_match_rise0_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_rise0_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
if (sr_fall0_r(pt_i) = pat_fall0(pt_i mod 4)) then
pat_match_fall0_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_fall0_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
if (sr_rise1_r(pt_i) = pat_rise1(pt_i mod 4)) then
pat_match_rise1_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_rise1_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
if (sr_fall1_r(pt_i) = pat_fall1(pt_i mod 4)) then
pat_match_fall1_r(pt_i) <= '1' after (TCQ)*1 ps;
else
pat_match_fall1_r(pt_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
pat_match_rise0_and_r <= AND_BR(pat_match_rise0_r) after (TCQ)*1 ps;
pat_match_fall0_and_r <= AND_BR(pat_match_fall0_r) after (TCQ)*1 ps;
pat_match_rise1_and_r <= AND_BR(pat_match_rise1_r) after (TCQ)*1 ps;
pat_match_fall1_and_r <= AND_BR(pat_match_fall1_r) after (TCQ)*1 ps;
pat_data_match_r <= (pat_match_rise0_and_r and pat_match_fall0_and_r and
pat_match_rise1_and_r and pat_match_fall1_and_r) after (TCQ)*1 ps;
end if;
end process;
-- Generic counter to force wait after either bitslip value or
-- CNT_RDEN is changed - allows time for old contents of read pipe
-- to flush out
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rden_wait_r <= '0' after (TCQ)*1 ps;
cnt_rden_wait_r <= (others => '0') after (TCQ)*1 ps;
else
if (to_integer(unsigned(cal2_state_r)) /= CAL2_READ_WAIT) then
rden_wait_r <= '1' after (TCQ)*1 ps;
cnt_rden_wait_r <= (others => '0') after (TCQ)*1 ps;
else
cnt_rden_wait_r <= cnt_rden_wait_r + '1' after (TCQ)*1 ps;
if (cnt_rden_wait_r = std_logic_vector(to_unsigned(RDEN_WAIT_CNT - 1, 3))) then
rden_wait_r <= '0' after (TCQ)*1 ps;
end if;
end if;
end if;
end if;
end process;
-- Register output for timing purposes
process (clk)
begin
if (clk'event and clk = '1') then
rd_bitslip_cnt <= cal2_rd_bitslip_cnt_r after (TCQ)*1 ps;
rd_active_dly <= cal2_rd_active_dly_r after (TCQ)*1 ps;
end if;
end process;
--*****************************************************************
-- Calibration state machine for determining polarity of ISERDES
-- CLKDIV invert control on a per-DQS group basis
-- This stage is used to choose the best phase of the resync clock
-- (on a per-DQS group basis) - "best phase" meaning the phase that
-- results in the largest possible margin in the CLK-to-RSYNC clock
-- domain transfer within the ISERDES.
-- NOTE: This stage actually takes place after stage 1 calibration.
-- For the time being, the signal naming convention associated with
-- this stage will be known as "cal_clkdiv". However, it really is
-- another stage of calibration - should be stage 2, and what is
-- currently stage 2 (rd_active_dly calibration) should be changed
-- to stage 3.
--*****************************************************************
rd_clkdiv_inv <= clkdiv_inv_r;
dbg_rd_clkdiv_inv <= clkdiv_inv_r;
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal_clkdiv_clkdiv_inv_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_cnt_clkdiv_r <= (others => '0') after (TCQ)*1 ps;
cal_clkdiv_dlyce_rsync_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_dlyinc_rsync_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_idel_rsync_inc_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_prech_req_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_IDLE after (TCQ)*1 ps;
cal_clkdiv_store_sr_req_r <= '0' after (TCQ)*1 ps;
clkdiv_inv_r <= (others => '0') after (TCQ)*1 ps;
idel_tap_delta_rsync_r <= "00000" after (TCQ)*1 ps;
min_rsync_marg_r <= "XXXXX" after (TCQ)*1 ps;
new_cnt_clkdiv_r <= '0' after (TCQ)*1 ps;
pol_min_rsync_marg_r <= '0' after (TCQ)*1 ps;
rdlvl_clkdiv_done_1 <= '0' after (TCQ)*1 ps;
else
-- default (inactive) states for all "pulse" outputs
cal_clkdiv_dlyce_rsync_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_prech_req_r <= '0' after (TCQ)*1 ps;
cal_clkdiv_store_sr_req_r <= '0' after (TCQ)*1 ps;
new_cnt_clkdiv_r <= '0' after (TCQ)*1 ps;
case (cal_clkdiv_state_r) is
when CAL_CLKDIV_IDLE =>
if (rdlvl_clkdiv_start = '1') then
if (SIM_CAL_OPTION = "SKIP_CAL") then
-- "Hardcoded" calibration option - for all DQS groups
-- do not invert rsync clock
clkdiv_inv_r <= (others => '0') after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_DONE after (TCQ)*1 ps;
else
new_cnt_clkdiv_r <= '1' after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Wait for various MUXes associated with a new DQS group to
-- change - also gives time for the read data shift register
-- to load with the updated data for the new DQS group
when CAL_CLKDIV_NEW_DQS_WAIT =>
-- Reset smallest recorded margin
min_rsync_marg_r <= "10000" after (TCQ)*1 ps;
pol_min_rsync_marg_r <= '0' after (TCQ)*1 ps;
if (pipe_wait = '0') then
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_STORE_REF after (TCQ)*1 ps;
end if;
-- For a given polarity of the rsync clock, save the initial data
-- value and use this as a reference to decide when an "edge" has
-- been encountered as the rsync clock is shifted
when CAL_CLKDIV_IDEL_STORE_REF =>
cal_clkdiv_store_sr_req_r <= '1' after (TCQ)*1 ps;
if (store_sr_done_r = '1') then
cal_clkdiv_state_r <= CAL_CLKDIV_DETECT_EDGE after (TCQ)*1 ps;
end if;
-- Check for presence of cpt-rsync clock synchronization "edge"
-- This occurs when the captured data sequence changes as the RSYNC
-- clock is shifted
when CAL_CLKDIV_DETECT_EDGE =>
if (found_edge_valid_r = '1') then
-- If an edge found, or we've run out of taps looking for an
-- edge, then:
-- (1) If the current margin found is the smallest, then
-- record it, as well as whether the CLKDIV was inverted
-- or not when this margin was measured
-- (2) Reverse the direction of IDEL_RSYNC_INC and/or invert
-- CLKDIV. We only invert CLKDIV if we just finished
-- incrementing the RSYNC IODELAY with CLKDIV not inverted
-- (3) Restore the original RSYNC clock delay in preparation
-- for either further measurements with the current DQS
-- group, or with the next DQS group
if ((idel_tap_delta_rsync_r = "01111") or (found_edge_r = '1')) then
-- record the margin if it's the smallest found so far
if (idel_tap_delta_rsync_r < min_rsync_marg_r) then
min_rsync_marg_r <= idel_tap_delta_rsync_r after (TCQ)*1 ps;
pol_min_rsync_marg_r <= cal_clkdiv_clkdiv_inv_r after (TCQ)*1 ps;
end if;
-- Reverse direction of RSYNC inc/dec
cal_clkdiv_idel_rsync_inc_r <= not(cal_clkdiv_idel_rsync_inc_r) after (TCQ)*1 ps;
-- Check whether to also invert CLKDIV (see above comments)
if (cal_clkdiv_idel_rsync_inc_r = '1') then
cal_clkdiv_clkdiv_inv_r <= not(cal_clkdiv_clkdiv_inv_r) after (TCQ)*1 ps;
clkdiv_inv_r(to_integer(unsigned(cal_clkdiv_cnt_clkdiv_r))) <= not(cal_clkdiv_clkdiv_inv_r) after (TCQ)*1 ps;
end if;
-- Proceed to restoring original RSYNC clock delay
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_SET_MIDPT_RSYNC after (TCQ)*1 ps;
else
-- Otherwise, increment or decrement RSYNC phase, keep
-- looking for an edge
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_INCDEC_RSYNC after (TCQ)*1 ps;
end if;
end if;
-- Increment or decrement RSYNC IODELAY by 1
when CAL_CLKDIV_IDEL_INCDEC_RSYNC =>
cal_clkdiv_dlyce_rsync_r <= '1' after (TCQ)*1 ps;
cal_clkdiv_dlyinc_rsync_r <= cal_clkdiv_idel_rsync_inc_r after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_INCDEC_RSYNC_WAIT after (TCQ)*1 ps;
idel_tap_delta_rsync_r <= idel_tap_delta_rsync_r + '1' after (TCQ)*1 ps;
-- Wait for RSYNC IODELAY, internal nodes within ISERDES, and
-- comparison logic shift register to settle, before checking again
-- for an edge
when CAL_CLKDIV_IDEL_INCDEC_RSYNC_WAIT =>
if (pipe_wait = '0') then
cal_clkdiv_state_r <= CAL_CLKDIV_DETECT_EDGE after (TCQ)*1 ps;
end if;
-- Restore RSYNC IODELAY to starting value
when CAL_CLKDIV_IDEL_SET_MIDPT_RSYNC =>
-- Check case if we found an edge at starting tap (possible if
-- we start at or near (near enough for jitter to affect us)
-- the transfer point between the CLK and RSYNC clock domains
if (idel_tap_delta_rsync_r = "00000") then
cal_clkdiv_state_r <= CAL_CLKDIV_NEXT_CHECK after (TCQ)*1 ps;
else
cal_clkdiv_dlyce_rsync_r <= '1' after (TCQ)*1 ps;
-- inc/dec the RSYNC IODELAY in the opposite directionas
-- the just-finished search. This is a bit confusing, but note
-- that after finishing the search, we always invert
-- IDEL_RSYNC_INC prior to arriving at this state
cal_clkdiv_dlyinc_rsync_r <= cal_clkdiv_idel_rsync_inc_r after (TCQ)*1 ps;
idel_tap_delta_rsync_r <= idel_tap_delta_rsync_r - '1' after (TCQ)*1 ps;
if (idel_tap_delta_rsync_r = "00001") then
cal_clkdiv_state_r <= CAL_CLKDIV_NEXT_CHECK after (TCQ)*1 ps;
end if;
end if;
-- Determine where to go next:
-- (1) start looking for an edge in the other direction (CLKDIV
-- polarity unchanged)
-- (2) change CLKDIV polarity, resample and record a reference
-- data value, and start looking for an edge
-- (3) if we've searched all 4 possibilities (CLKDIV inverted,
-- not inverted, RSYNC shifted in left and right directions)
-- then decide which clock polarity is best to use for CLKDIV
-- and proceed to next DQS
-- NOTE: When we're comparing the current "state" (using both
-- IDEL_RSYNC_INC and CLKDIV_INV) we are comparing what the
-- next value of these signals will be, not what they were
-- for the phase of edge detection just finished. Therefore
-- IDEL_RSYNC_INC=0 and CLKDIV_INV=1 means we are about to
-- decrement RSYNC with CLKDIV inverted (or in other words,
-- we just searched with incrementing RSYNC, and CLKDIV not
-- inverted)
when CAL_CLKDIV_NEXT_CHECK =>
-- Wait for any residual change effects (CLKDIV inversion, RSYNC
-- IODELAY inc/dec) from previous state to finish
if (pipe_wait = '0') then
if ((cal_clkdiv_idel_rsync_inc_r = '0') and (cal_clkdiv_clkdiv_inv_r = '0')) then
-- If we've searched all 4 possibilities, then decide which
-- is the "best" clock polarity (which is to say, whichever
-- polarity which DID NOT result in the minimum margin found)
-- to use and proceed to next DQS
if (SIM_CAL_OPTION = "FAST_CAL") then
-- if simulating, and "shortcuts" for calibration enabled,
-- apply results to all other elements (i.e. assume delay
-- on all bits/bytes is same)
clkdiv_inv_r <= (others => not(pol_min_rsync_marg_r)) after (TCQ)*1 ps;
else
-- Otherwise, apply result only to current DQS group
clkdiv_inv_r(to_integer(unsigned(cal_clkdiv_cnt_clkdiv_r))) <= not(pol_min_rsync_marg_r) after (TCQ)*1 ps;
end if;
cal_clkdiv_state_r <= CAL_CLKDIV_NEXT_DQS after (TCQ)*1 ps;
elsif ((cal_clkdiv_idel_rsync_inc_r = '0') and (cal_clkdiv_clkdiv_inv_r = '1')) then
-- If we've finished searching with CLKDIV not inverted
-- Now store a new reference value for edge-detection
-- comparison purposes and begin looking for an edge
cal_clkdiv_state_r <= CAL_CLKDIV_IDEL_STORE_REF after (TCQ)*1 ps;
else
-- Otherwise, we've just finished checking by decrementing
-- RSYNC. Now look for an edge by incrementing RSYNC
-- (keep the CLKDIV polarity unchanged)
cal_clkdiv_state_r <= CAL_CLKDIV_DETECT_EDGE after (TCQ)*1 ps;
end if;
end if;
-- Determine whether we're done, or have more DQS's to calibrate
-- Also request precharge after every byte
when CAL_CLKDIV_NEXT_DQS =>
cal_clkdiv_prech_req_r <= '1' after (TCQ)*1 ps;
-- Wait until precharge that occurs in between calibration of
-- DQS groups is finished
if (prech_done = '1') then
if (((to_integer(unsigned(cal_clkdiv_cnt_clkdiv_r))) >= DQS_WIDTH-1) or (SIM_CAL_OPTION = "FAST_CAL")) then
-- If FAST_CAL enabled, only cal first DQS group - the results
-- (aka CLKDIV invert) have been applied to all DQS groups
cal_clkdiv_state_r <= CAL_CLKDIV_DONE after (TCQ)*1 ps;
else
-- Otherwise increment DQS group counter and keep going
new_cnt_clkdiv_r <= '1' after (TCQ)*1 ps;
cal_clkdiv_cnt_clkdiv_r <= cal_clkdiv_cnt_clkdiv_r + '1' after (TCQ)*1 ps;
cal_clkdiv_state_r <= CAL_CLKDIV_NEW_DQS_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Done with this stage of calibration
when CAL_CLKDIV_DONE =>
rdlvl_clkdiv_done_1 <= '1' after (TCQ)*1 ps;
when others =>
null;
end case;
end if;
end if;
end process;
--*****************************************************************
-- Stage 2 state machine
--*****************************************************************
-- when calibrating, check to see which clock cycle (after the read is
-- issued) does the expected data pattern arrive. Record this result
-- NOTES:
-- 1. An error condition can occur due to two reasons:
-- a. If the matching logic waits a long enough amount of time
-- and the expected data pattern is not received (longer than
-- the theoretical maximum time that the data can take, factoring
-- in CAS latency, prop delays, etc.), then flag an error.
-- However, the error may be "recoverable" in that the write
-- logic is still calibrating itself (in this case part of the
-- write calibration is intertwined with the this stage of read
-- calibration - write logic writes a pattern to the memory, then
-- relies on rdlvl to find that pattern - if it doesn't, wrlvl
-- changes its timing and tries again. By design, if the write path
-- timing is incorrect, the rdlvl logic will never find the
-- pattern). Because of this, there is a mechanism to restart
-- this stage of rdlvl if an "error" is found.
-- b. If the delay between different DQS groups is too large.
-- There will be a maximum "skew" between different DQS groups
-- based on routing, clock skew, etc.
-- NOTE: Can add error checking here in case valid data not found on any
-- of the available pipeline stages
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal2_cnt_bitslip_r <= (others => '0') after (TCQ)*1 ps;
cal2_cnt_rd_dly_r <= (others => '0') after (TCQ)*1 ps;
cal2_cnt_rden_r <= (others => '0') after (TCQ)*1 ps;
cal2_done_r <= '0' after (TCQ)*1 ps;
cal2_en_dqs_skew_r <= '0' after (TCQ)*1 ps;
cal2_max_cnt_rd_dly_r <= (others => '0') after (TCQ)*1 ps;
cal2_prech_req_r <= '0' after (TCQ)*1 ps;
cal2_rd_bitslip_cnt_r <= (others => '0') after (TCQ)*1 ps;
cal2_state_r <= CAL2_IDLE after (TCQ)*1 ps;
rdlvl_pat_err <= '0' after (TCQ)*1 ps;
else
cal2_prech_req_r <= '0' after (TCQ)*1 ps;
case (cal2_state_r) is
when CAL2_IDLE =>
if ((rdlvl_start(1)) = '1') then
if ((SIM_CAL_OPTION = "SKIP_CAL") and (REG_CTRL = "ON")) then
-- If skip rdlvl, then proceed to end. Also hardcode bitslip
-- values based on CAS latency
cal2_state_r <= CAL2_DONE after (TCQ)*1 ps;
for idx in 0 to (DQS_WIDTH-1) loop
case nCL is
when 3 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 4 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 5 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 6 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 7 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 8 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 9 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 10 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 11 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when others =>
null;
end case;
end loop;
elsif (SIM_CAL_OPTION = "SKIP_CAL") then
-- If skip rdlvl, then proceed to end. Also hardcode bitslip
-- values based on CAS latency
cal2_state_r <= CAL2_DONE after (TCQ)*1 ps;
for idx in 0 to (DQS_WIDTH-1) loop
case nCL is
when 3 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 4 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 5 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 6 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 7 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 8 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 9 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when 10 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "01" after (TCQ)*1 ps;
when 11 =>
cal2_rd_bitslip_cnt_r(2*idx+1 downto 2*idx) <= "11" after (TCQ)*1 ps;
when others =>
null;
end case;
end loop;
else
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
end if;
end if;
-- General wait state to wait for read pipe contents to settle
-- either after bitslip is changed
when CAL2_READ_WAIT =>
-- Reset read delay counter after bitslip is changed - with every
-- new bitslip setting, we need to remeasure the read delay
cal2_cnt_rd_dly_r <= "00000" after (TCQ)*1 ps;
-- Wait for rising edge of synchronized rd_active signal from
-- controller, then starts counting clock cycles until the correct
-- pattern is returned from memory. Also make sure that we've
-- waited long enough after incrementing CNT_RDEN to allow data
-- to change, and ISERDES pipeline to flush out
if ((rd_active_posedge_r = '1') and (not(rden_wait_r)) = '1') then
cal2_state_r <= CAL2_DETECT_MATCH after (TCQ)*1 ps;
end if;
-- Wait until either a match is found, or until enough cycles
-- have passed that there could not possibly be a match
when CAL2_DETECT_MATCH =>
-- Increment delay counter for every cycle we're in this state
cal2_cnt_rd_dly_r <= cal2_cnt_rd_dly_r + '1' after (TCQ)*1 ps;
if (pat_data_match_r = '1') then
-- If found data match, then move on to next DQS group
cal2_state_r <= CAL2_NEXT_DQS after (TCQ)*1 ps;
elsif (to_integer(unsigned(cal2_cnt_rd_dly_r)) = MAX_RD_DLY_CNT-1) then
if (cal2_cnt_bitslip_r /= "11") then
-- If we've waited enough cycles for worst possible "round-trip"
-- delay, then try next bitslip setting, and repeat this process
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
cal2_cnt_bitslip_r <= cal2_cnt_bitslip_r + "01" after (TCQ)*1 ps;
-- Update bitslip count for current DQS group
if (SIM_CAL_OPTION = "FAST_CAL") then
-- Increment bitslip count - for simulation, update bitslip
-- count for all DQS groups with same value
loop_sim_bitslip: for i in 0 to DQS_WIDTH-1 loop
cal2_rd_bitslip_cnt_r((2*i)+1 downto 2*i) <= cal2_rd_bitslip_cnt_r((2*i)+1 downto 2*i) + '1' after (TCQ)*1 ps;
end loop;
else
-- Otherwise, increment only for current DQS group
if ( cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))) = '1' ) then
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+0) <= '0' after (TCQ)*1 ps;
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+1) <=
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+1) xor '1' after (TCQ)*1 ps;
else
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+0) <= '1' after (TCQ)*1 ps;
end if;
end if;
else
-- Otherwise, if we've already exhausted all bitslip settings
-- and still haven't found a match, the boat has **possibly **
-- sunk (may be an error due to write calibration still
-- figuring out its own timing)
cal2_state_r <= CAL2_ERROR_TO after (TCQ)*1 ps;
end if;
end if;
-- Final processing for current DQS group. Move on to next group
-- Determine read enable delay between current DQS and DQS[0]
when CAL2_NEXT_DQS =>
-- At this point, we've just found the correct pattern for the
-- current DQS group. Now check to see how long it took for the
-- pattern to return. Record the current delay time, as well as
-- the maximum time required across all the bytes
if (cal2_cnt_rd_dly_r > cal2_max_cnt_rd_dly_r) then
cal2_max_cnt_rd_dly_r <= cal2_cnt_rd_dly_r after (TCQ)*1 ps;
end if;
if (SIM_CAL_OPTION = "FAST_CAL") then
-- For simulation, update count for all DQS groups
for j in 0 to DQS_WIDTH - 1 loop
cal2_dly_cnt_r(5*j+4 downto 5*j) <= cal2_cnt_rd_dly_r after (TCQ)*1 ps;
end loop;
else
for idx in 0 to 4 loop
cal2_dly_cnt_r(5*to_integer(unsigned(cal2_cnt_rden_r))+idx) <= cal2_cnt_rd_dly_r(idx) after (TCQ)*1 ps;
end loop;
end if;
-- Request bank/row precharge, and wait for its completion. Always
-- precharge after each DQS group to avoid tRAS(max) violation
cal2_prech_req_r <= '1' after (TCQ)*1 ps;
if (prech_done = '1') then
if (((DQS_WIDTH = 1) or (SIM_CAL_OPTION = "FAST_CAL")) or (to_integer(unsigned(cal2_cnt_rden_r)) >= (DQS_WIDTH-1))) then
-- If either FAST_CAL is enabled and first DQS group is
-- finished, or if the last DQS group was just finished,
-- then indicate that we can switch to final values for
-- byte skews, and signal end of stage 2 calibration
cal2_en_dqs_skew_r <= '1' after (TCQ)*1 ps;
cal2_state_r <= CAL2_DONE after (TCQ)*1 ps;
else
-- Continue to next DQS group
cal2_cnt_rden_r <= cal2_cnt_rden_r + '1' after (TCQ)*1 ps;
cal2_cnt_bitslip_r <= "00" after (TCQ)*1 ps;
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
end if;
end if;
-- Finished with read enable calibration
when CAL2_DONE =>
cal2_done_r <= '1' after (TCQ)*1 ps;
-- Error detected due to timeout from waiting for expected data pat
-- Also assert error in this case, but also allow opportunity for
-- external control logic to resume the calibration at this point
when CAL2_ERROR_TO =>
-- Assert error even though error might be temporary (until write
-- calibration logic asserts RDLVL_PAT_RESUME
rdlvl_pat_err <= '1' after (TCQ)*1 ps;
-- Wait for resume signal from write calibration logic
if (rdlvl_pat_resume = '1') then
-- Similarly, reset bitslip control for current DQS group to 0
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+1) <= '0' after (TCQ)*1 ps;
cal2_rd_bitslip_cnt_r(2*to_integer(unsigned(cal2_cnt_rden_r))+0) <= '0' after (TCQ)*1 ps;
cal2_cnt_bitslip_r <= (others => '0') after (TCQ)*1 ps;
cal2_state_r <= CAL2_READ_WAIT after (TCQ)*1 ps;
rdlvl_pat_err <= '0' after (TCQ)*1 ps;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- Display which DQS group failed when timeout error occurs during pattern
-- calibration. NOTE: Only valid when rdlvl_pat_err = 1
rdlvl_pat_err_cnt <= cal2_cnt_rden_r;
-- Final output: determine amount to delay rd_active signal by
process (clk)
begin
if (clk'event and clk = '1') then
if (SIM_CAL_OPTION = "SKIP_CAL") then
-- Hardcoded option (for simulation only). The results are very
-- specific for a testbench w/o additional net delays using a Micron
-- memory model. Any other configuration may not work.
case nCL is
when 5 =>
cal2_rd_active_dly_r <= "01010" after (TCQ)*1 ps;
when 6 =>
cal2_rd_active_dly_r <= "01010" after (TCQ)*1 ps;
when 7 =>
cal2_rd_active_dly_r <= "01011" after (TCQ)*1 ps;
when 8 =>
cal2_rd_active_dly_r <= "01011" after (TCQ)*1 ps;
when 9 =>
cal2_rd_active_dly_r <= "01100" after (TCQ)*1 ps;
when 10 =>
cal2_rd_active_dly_r <= "01100" after (TCQ)*1 ps;
when 11 =>
cal2_rd_active_dly_r <= "01101" after (TCQ)*1 ps;
when others =>
null;
end case;
elsif (rdlvl_done_1(1) = '0') then
-- Before calibration is complete, set RD_ACTIVE to minimum delay
cal2_rd_active_dly_r <= (others => '0') after (TCQ)*1 ps;
else
-- Set RD_ACTIVE based on maximum DQS group delay
cal2_rd_active_dly_r <= cal2_max_cnt_rd_dly_r - std_logic_vector(to_unsigned(RDEN_DELAY_OFFSET, 5)) after (TCQ)*1 ps;
end if;
end if;
end process;
gen_dly : for dqs_i in 0 to DQS_WIDTH-1 generate
-- Determine difference between delay for each DQS group, and the
-- DQS group with the maximum delay
process (clk)
begin
if (clk'event and clk = '1') then
cal2_dly_cnt_delta_r(dqs_i) <= cal2_max_cnt_rd_dly_r - cal2_dly_cnt_r(5*dqs_i+4 downto 5*dqs_i) after (TCQ)*1 ps;
end if;
end process;
-- Delay those DQS groups with less than the maximum delay
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "00" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
elsif (cal2_en_dqs_skew_r = '0') then
-- While calibrating, do not skew individual bytes
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "00" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
else
-- Once done calibrating, go ahead and skew individual bytes
case cal2_dly_cnt_delta_r(dqs_i) is
when "00000" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "00" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
when "00001" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "01" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
when "00010" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "10" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
when "00011" =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "11" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '0' after (TCQ)*1 ps;
-- If there's more than 3 cycles of skew between different
-- then flag error
when others =>
cal2_clkdly_cnt_r(2*dqs_i+1 downto 2*dqs_i) <= "XX" after (TCQ)*1 ps;
cal2_deskew_err_r(dqs_i) <= '1' after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
rd_clkdly_cnt <= cal2_clkdly_cnt_r after (TCQ)*1 ps;
end if;
end process;
-- Assert when non-recoverable error occurs during stage 2 cal
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rdlvl_err_2(1) <= '0' after (TCQ)*1 ps;
else
-- Combine errors from each of the individual DQS group deskews
rdlvl_err_2(1) <= or_br(cal2_deskew_err_r) after (TCQ)*1 ps;
end if;
end if;
end process;
-- Delay assertion of RDLVL_DONE for stage 2 by a few cycles after
-- we've reached CAL2_DONE to account for fact that the proper deskew
-- delays still need to be calculated, and driven to the individual
-- DQ/DQS delay blocks. It's not an exact science, the # of delay cycles
-- is sufficient. Feel free to add more delay if the calculation or FSM
-- logic is later changed.
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cal2_done_r1 <= '0' after (TCQ)*1 ps;
cal2_done_r2 <= '0' after (TCQ)*1 ps;
cal2_done_r3 <= '0' after (TCQ)*1 ps;
rdlvl_done_1(1) <= '0' after (TCQ)*1 ps;
else
cal2_done_r1 <= cal2_done_r after (TCQ)*1 ps;
cal2_done_r2 <= cal2_done_r1 after (TCQ)*1 ps;
cal2_done_r3 <= cal2_done_r2 after (TCQ)*1 ps;
rdlvl_done_1(1) <= cal2_done_r3 after (TCQ)*1 ps;
end if;
end if;
end process;
end architecture arch;
|
lgpl-3.0
|
99cf7d5406e501727d0e209bc7cf4931
| 0.512864 | 3.787375 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/tx_Mem_Reader.vhd
| 1 | 30,792 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: tx_Mem_Reader - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
--
-- Revision 1.00 - first release. 20.03.2008
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
entity tx_Mem_Reader is
port (
-- DDR Read Interface
DDR_rdc_sof : out std_logic;
DDR_rdc_eof : out std_logic;
DDR_rdc_v : out std_logic;
DDR_rdc_Shift : out std_logic;
DDR_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : in std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : out std_logic;
DDR_FIFO_Empty : in std_logic;
DDR_FIFO_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone Read interface
wb_rdc_sof : out std_logic;
wb_rdc_v : out std_logic;
wb_rdc_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wb_rdc_full : in std_logic;
-- Wisbbone Buffer read port
wb_FIFO_re : out std_logic;
wb_FIFO_empty : in std_logic;
wb_FIFO_qout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register Read interface
Regs_RdAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Read Command interface
RdNumber : in std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One : in std_logic;
RdNumber_eq_Two : in std_logic;
StartAddr : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord : in std_logic;
is_CplD : in std_logic;
BAR_value : in std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req : in std_logic;
RdCmd_Ack : out std_logic;
-- Output port of the memory buffer
mbuf_Din : out std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
mbuf_WE : out std_logic;
mbuf_Full : in std_logic;
mbuf_aFull : in std_logic;
-- Common ports
Tx_TimeOut : out std_logic;
Tx_wb_TimeOut : out std_logic;
mReader_Rst_n : in std_logic;
user_clk : in std_logic
);
end tx_Mem_Reader;
architecture Behavioral of tx_Mem_Reader is
type mReaderStates is (St_mR_Idle, -- Memory reader Idle
St_mR_CmdLatch, -- Capture the read command
St_mR_Transfer, -- Acknowlege the command request
St_mR_wb_A, -- Wishbone access state A
St_mR_DDR_A, -- DDR access state A
St_mR_DDR_C, -- DDR access state C
St_mR_Last -- Last word is reached
);
-- State variables
signal TxMReader_State : mReaderStates;
-- DDR Read Interface
signal DDR_rdc_sof_i : std_logic;
signal DDR_rdc_eof_i : std_logic;
signal DDR_rdc_v_i : std_logic;
signal DDR_rdc_Shift_i : std_logic;
signal DDR_rdc_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register read address
signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdEn : std_logic;
signal Regs_Hit : std_logic;
signal Regs_Write_mbuf_r1 : std_logic;
signal Regs_Write_mbuf_r2 : std_logic;
signal Regs_Write_mbuf_r3 : std_logic;
-- DDR FIFO read enable
signal DDR_FIFO_RdEn_i : std_logic;
signal DDR_FIFO_RdEn_Mask : std_logic;
signal DDR_FIFO_Hit : std_logic;
signal DDR_FIFO_Write_mbuf_r1 : std_logic;
signal DDR_FIFO_Write_mbuf_r2 : std_logic;
signal DDR_FIFO_Write_mbuf_r3 : std_logic;
signal DDR_FIFO_RdQout_swap : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
signal wb_rdc_sof_i : std_logic;
signal wb_rdc_v_i : std_logic;
signal wb_rdc_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_rdc_full_i : std_logic;
signal wb_FIFO_Hit : std_logic;
signal wb_FIFO_Write_mbuf : std_logic;
signal wb_FIFO_Write_mbuf_r1 : std_logic;
signal wb_FIFO_Write_mbuf_r2 : std_logic;
signal wb_FIFO_re_i : std_logic;
signal wb_FIFO_RdEn_Mask_rise : std_logic;
signal wb_FIFO_RdEn_Mask_rise_r1 : std_logic;
signal wb_FIFO_RdEn_Mask_rise_r2 : std_logic;
signal wb_FIFO_RdEn_Mask_rise_r3 : std_logic;
signal wb_FIFO_RdEn_Mask : std_logic;
signal wb_FIFO_RdEn_Mask_r1 : std_logic;
signal wb_FIFO_RdEn_Mask_r2 : std_logic;
signal wb_FIFO_Rd_1Dw : std_logic;
signal wb_FIFO_qout_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_FIFO_qout_shift : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wb_FIFO_qout_swapped : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Memory data outputs
signal wb_FIFO_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_RdQout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal mbuf_Din_wire_OR : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Output port of the memory buffer
signal mbuf_Din_i : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_WE_i : std_logic;
signal mbuf_Full_i : std_logic;
signal mbuf_aFull_i : std_logic;
signal mbuf_aFull_r1 : std_logic;
-- Read command request and acknowledge
signal RdCmd_Req_i : std_logic;
signal RdCmd_Ack_i : std_logic;
signal Shift_1st_QWord_k : std_logic;
signal is_CplD_k : std_logic;
signal may_be_MWr_k : std_logic;
signal TRem_n_last_QWord : std_logic;
signal regs_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal regs_Rd_Cntr_eq_One : std_logic;
signal regs_Rd_Cntr_eq_Two : std_logic;
signal DDR_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal DDR_Rd_Cntr_eq_One : std_logic;
signal wb_FIFO_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal wb_FIFO_Rd_Cntr_eq_Two : std_logic;
signal Address_var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Address_step : std_logic_vector(4-1 downto 0);
signal TxTLP_eof_n : std_logic;
signal TxTLP_eof_n_r1 : std_logic;
-- signal TxTLP_eof_n_r2 : std_logic;
signal TimeOut_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal TO_Cnt_Rst : std_logic;
signal Tx_TimeOut_i : std_logic;
signal Tx_wb_TimeOut_i : std_logic := '0';
begin
-- read command REQ + ACK
RdCmd_Req_i <= RdCmd_Req;
RdCmd_Ack <= RdCmd_Ack_i;
-- Time out signal out
Tx_TimeOut <= Tx_TimeOut_i;
Tx_wb_TimeOut <= Tx_wb_TimeOut_i;
------------------------------------------------------------
--- Memory read control
------------------------------------------------------------
-- Wishbone Buffer read
wb_FIFO_re <= wb_FIFO_re_i;
wb_rdc_sof <= wb_rdc_sof_i;
wb_rdc_v <= wb_rdc_v_i;
wb_rdc_din <= wb_rdc_din_i;
wb_rdc_full_i <= wb_rdc_full;
-- DDR FIFO Read
DDR_rdc_sof <= DDR_rdc_sof_i;
DDR_rdc_eof <= DDR_rdc_eof_i;
DDR_rdc_v <= DDR_rdc_v_i;
DDR_rdc_Shift <= DDR_rdc_Shift_i;
DDR_rdc_din <= DDR_rdc_din_i;
DDR_FIFO_RdQout_swap <= (DDR_FIFO_RdQout(C_DBUS_WIDTH/2-1 downto 0) &
DDR_FIFO_RdQout(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2));
DDR_FIFO_RdEn <= DDR_FIFO_RdEn_i;
-- Register address for read
Regs_RdAddr <= Regs_RdAddr_i;
-- Memory buffer write port
--ported from TRN to AXI, swap DWORDs
mbuf_Din <= mbuf_Din_i(C_DBUS_WIDTH*9/8-1 downto C_DBUS_WIDTH)
& mbuf_Din_i(31 downto 0)
& mbuf_Din_i(63 downto 32);
mbuf_WE <= mbuf_WE_i;
mbuf_Full_i <= mbuf_Full;
mbuf_aFull_i <= mbuf_aFull;
--
Regs_RdAddr_i <= Address_var(C_EP_AWIDTH-1 downto 0);
-----------------------------------------------------
-- Synchronous Delay: mbuf_aFull
--
Synchron_Delay_mbuf_aFull :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
mbuf_aFull_r1 <= mbuf_aFull_i or mbuf_Full_i;
end if;
end process;
-- ---------------------------------------------------
-- State Machine: Tx Memory read control
--
mR_FSM_Control :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
DDR_rdc_sof_i <= '0';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '0';
DDR_rdc_Shift_i <= '0';
DDR_rdc_din_i <= (others => '0');
wb_rdc_sof_i <= '0';
wb_rdc_v_i <= '0';
wb_rdc_din_i <= (others => '0');
wb_FIFO_Hit <= '0';
wb_FIFO_re_i <= '0';
wb_FIFO_RdEn_Mask <= '0';
DDR_FIFO_Hit <= '0';
DDR_FIFO_RdEn_i <= '0';
DDR_FIFO_RdEn_Mask <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
regs_Rd_Counter <= (others => '0');
DDR_Rd_Counter <= (others => '0');
DDR_Rd_Cntr_eq_One <= '0';
wb_FIFO_Rd_Counter <= (others => '0');
wb_FIFO_Rd_Cntr_eq_Two <= '0';
regs_Rd_Cntr_eq_One <= '0';
regs_Rd_Cntr_eq_Two <= '0';
Shift_1st_QWord_k <= '0';
is_CplD_k <= '0';
may_be_MWr_k <= '0';
TRem_n_last_QWord <= '0';
Address_var <= (others => '1');
TxTLP_eof_n <= '1';
TO_Cnt_Rst <= '1';
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
elsif user_clk'event and user_clk = '1' then
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '0' then
TxMReader_State <= St_mR_Idle;
wb_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
TxTLP_eof_n <= '1';
Address_var <= (others => '1');
RdCmd_Ack_i <= '0';
is_CplD_k <= '0';
may_be_MWr_k <= '0';
else
RdCmd_Ack_i <= '1';
Shift_1st_QWord_k <= Shift_1st_QWord;
TRem_n_last_QWord <= Shift_1st_QWord xor RdNumber(0);
is_CplD_k <= is_CplD;
may_be_MWr_k <= not is_CplD;
TxTLP_eof_n <= '1';
if BAR_value(C_ENCODE_BAR_NUMBER-1 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
wb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '1';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_DDR_A;
elsif BAR_value(C_ENCODE_BAR_NUMBER-1 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
wb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '1';
Regs_RdEn <= '1';
if Shift_1st_QWord = '1' then
Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0) - "100";
else
Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0);
end if;
TxMReader_State <= St_mR_CmdLatch;
elsif BAR_value(C_ENCODE_BAR_NUMBER-1 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
wb_FIFO_Hit <= '1';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_wb_A;
else
wb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_CmdLatch;
end if;
end if;
when St_mR_DDR_A =>
DDR_rdc_sof_i <= '1';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '1';
DDR_rdc_Shift_i <= Shift_1st_QWord_k;
DDR_rdc_din_i <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_TLP_FLD_WIDTH_OF_LENG+2+32)
& RdNumber & "00"
& StartAddr(C_DBUS_WIDTH-1-32 downto 0);
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '1';
TxMReader_State <= St_mR_DDR_C; -- St_mR_DDR_B;
when St_mR_wb_A =>
wb_rdc_sof_i <= '1';
wb_rdc_v_i <= '1';
wb_rdc_din_i <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_TLP_FLD_WIDTH_OF_LENG+2+32)
& RdNumber & "00"
& StartAddr(C_DBUS_WIDTH-1-32 downto 0);
Regs_RdEn <= '0';
wb_FIFO_re_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '1';
if wb_rdc_full_i = '0' then
TxMReader_State <= St_mR_DDR_C;
else
TxMReader_State <= St_mR_wb_A;
end if;
when St_mR_DDR_C =>
DDR_rdc_sof_i <= '0';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '0';
DDR_rdc_din_i <= DDR_rdc_din_i;
wb_rdc_sof_i <= '0';
wb_rdc_v_i <= '0';
wb_rdc_din_i <= wb_rdc_din_i;
RdCmd_Ack_i <= '0';
TxTLP_eof_n <= '1';
if DDR_FIFO_Hit = '1' and DDR_FIFO_Empty = '1' and Tx_TimeOut_i = '0' then
TxMReader_State <= St_mR_DDR_C;
elsif wb_FIFO_Hit = '1' and wb_FIFO_empty = '1' and Tx_wb_TimeOut_i = '0' then
TxMReader_State <= St_mR_DDR_C;
else
TxMReader_State <= St_mR_CmdLatch;
end if;
when St_mR_CmdLatch =>
RdCmd_Ack_i <= '0';
if regs_Rd_Cntr_eq_One = '1' then
Regs_RdEn <= '0';
Address_var <= Address_var;
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif regs_Rd_Cntr_eq_Two = '1' then
if Shift_1st_QWord_k = '1' then
TxMReader_State <= St_mR_Transfer;
Regs_RdEn <= Regs_RdEn; -- '1';
TxTLP_eof_n <= '1';
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
else
TxMReader_State <= St_mR_Last;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
end if;
else
Regs_RdEn <= Regs_RdEn;
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
TxTLP_eof_n <= '1';
TxMReader_State <= St_mR_Transfer;
end if;
when St_mR_Transfer =>
RdCmd_Ack_i <= '0';
if DDR_FIFO_Hit = '1' and DDR_FIFO_RdEn_Mask = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif wb_FIFO_Hit = '1' and wb_FIFO_RdEn_Mask = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif wb_FIFO_Hit = '0' and regs_Rd_Cntr_eq_One = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif wb_FIFO_Hit = '0' and regs_Rd_Cntr_eq_Two = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif mbuf_aFull_r1 = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= TxTLP_eof_n;
TxMReader_State <= St_mR_Transfer;
else
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
Regs_RdEn <= Regs_Hit;
TxTLP_eof_n <= TxTLP_eof_n;
TxMReader_State <= St_mR_Transfer;
end if;
when St_mR_Last =>
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= (not DDR_FIFO_Hit) and (not wb_FIFO_Hit);
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
when others =>
Address_var <= Address_var;
wb_FIFO_Hit <= '0';
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
end case;
case TxMReader_State is
when St_mR_Idle =>
TO_Cnt_Rst <= '1';
when others =>
TO_Cnt_Rst <= '0';
end case;
case TxMReader_State is
when St_mR_Idle =>
DDR_FIFO_RdEn_i <= '0';
DDR_FIFO_RdEn_Mask <= '0';
when others =>
if DDR_Rd_Cntr_eq_One = '1'
and (DDR_FIFO_Empty = '0' or Tx_TimeOut_i = '1')
and DDR_FIFO_RdEn_i = '1'
then
DDR_FIFO_RdEn_Mask <= '1';
DDR_FIFO_RdEn_i <= '0';
else
DDR_FIFO_RdEn_Mask <= DDR_FIFO_RdEn_Mask;
DDR_FIFO_RdEn_i <= DDR_FIFO_Hit
and not mbuf_aFull_r1
and not DDR_FIFO_RdEn_Mask;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
wb_FIFO_re_i <= '0';
wb_FIFO_RdEn_Mask <= '0';
when others =>
if wb_FIFO_Rd_Cntr_eq_Two = '1'
and (wb_FIFO_empty = '0' or Tx_wb_TimeOut_i = '1')
and wb_FIFO_re_i = '1'
then
wb_FIFO_RdEn_Mask <= '1';
wb_FIFO_re_i <= '0';
else
wb_FIFO_RdEn_Mask <= wb_FIFO_RdEn_Mask;
wb_FIFO_re_i <= wb_FIFO_Hit
and not mbuf_aFull_r1
and not wb_FIFO_RdEn_Mask;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
/= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
regs_Rd_Counter <= RdNumber;
regs_Rd_Cntr_eq_One <= RdNumber_eq_One;
regs_Rd_Cntr_eq_Two <= RdNumber_eq_Two;
else
regs_Rd_Counter <= (others => '0');
regs_Rd_Cntr_eq_One <= '0';
regs_Rd_Cntr_eq_Two <= '0';
end if;
when St_mR_CmdLatch =>
if DDR_FIFO_Hit = '0' then
if Shift_1st_QWord_k = '1' then
regs_Rd_Counter <= regs_Rd_Counter - '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
else
regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
end if;
else
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end if;
when St_mR_Transfer =>
if DDR_FIFO_Hit = '0'
and mbuf_aFull_r1 = '0'
then
regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
else
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end if;
when others =>
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
if RdNumber(0) = '1' then
DDR_Rd_Counter <= RdNumber + '1';
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
elsif Shift_1st_QWord = '1' then
DDR_Rd_Counter <= RdNumber + "10";
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
else
DDR_Rd_Counter <= RdNumber;
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One or RdNumber_eq_Two;
end if;
else
DDR_Rd_Counter <= (others => '0');
DDR_Rd_Cntr_eq_One <= '0';
end if;
when others =>
if ((DDR_FIFO_Empty = '0' or Tx_TimeOut_i = '1') and DDR_FIFO_RdEn_i = '1')
then
DDR_Rd_Counter <= DDR_Rd_Counter - "10"; -- '1';
if DDR_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
DDR_Rd_Cntr_eq_One <= '1';
else
DDR_Rd_Cntr_eq_One <= '0';
end if;
else
DDR_Rd_Counter <= DDR_Rd_Counter;
DDR_Rd_Cntr_eq_One <= DDR_Rd_Cntr_eq_One;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i = '1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
if RdNumber_eq_One = '1' then
wb_FIFO_Rd_Counter <= RdNumber + '1';
wb_FIFO_Rd_Cntr_eq_Two <= '1';
wb_FIFO_Rd_1Dw <= '1';
else
wb_FIFO_Rd_Counter <= RdNumber;
wb_FIFO_Rd_Cntr_eq_Two <= RdNumber_eq_Two; -- or RdNumber_eq_One;
wb_FIFO_Rd_1Dw <= '0';
end if;
else
wb_FIFO_Rd_Counter <= (others => '0');
wb_FIFO_Rd_Cntr_eq_Two <= '0';
wb_FIFO_Rd_1Dw <= '0';
end if;
when others =>
wb_FIFO_Rd_1Dw <= wb_FIFO_Rd_1Dw;
if (wb_FIFO_empty = '0' or Tx_wb_TimeOut_i = '1') and wb_FIFO_re_i = '1'
then
wb_FIFO_Rd_Counter <= wb_FIFO_Rd_Counter - "10"; -- '1';
if wb_FIFO_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
wb_FIFO_Rd_Cntr_eq_Two <= '1';
else
wb_FIFO_Rd_Cntr_eq_Two <= '0';
end if;
else
wb_FIFO_Rd_Counter <= wb_FIFO_Rd_Counter;
wb_FIFO_Rd_Cntr_eq_Two <= wb_FIFO_Rd_Cntr_eq_Two;
end if;
end case;
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: mbuf_writes
--
Synchron_Delay_mbuf_writes :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
Regs_Write_mbuf_r1 <= Regs_RdEn;
Regs_Write_mbuf_r2 <= Regs_Write_mbuf_r1;
Regs_Write_mbuf_r3 <= Regs_Write_mbuf_r2;
DDR_FIFO_Write_mbuf_r1 <= DDR_FIFO_RdEn_i and (not DDR_FIFO_Empty or Tx_TimeOut_i);
DDR_FIFO_Write_mbuf_r2 <= DDR_FIFO_Write_mbuf_r1;
DDR_FIFO_Write_mbuf_r3 <= DDR_FIFO_Write_mbuf_r2;
wb_FIFO_Write_mbuf <= wb_FIFO_re_i and (not wb_FIFO_empty or Tx_wb_TimeOut_i);
wb_FIFO_Write_mbuf_r1 <= wb_FIFO_Write_mbuf;
wb_FIFO_Write_mbuf_r2 <= wb_FIFO_Write_mbuf_r1;
wb_FIFO_RdEn_Mask_r1 <= wb_FIFO_RdEn_Mask;
wb_FIFO_RdEn_Mask_r2 <= wb_FIFO_RdEn_Mask_r1;
end if;
end process;
--------------------------------------------------------------------------
-- Wires to be OR'ed to build mbuf_Din
--------------------------------------------------------------------------
wb_FIFO_Dout_wire <= wb_FIFO_qout_r1 when (wb_FIFO_Hit = '1' and Shift_1st_QWord_k = '0')
else wb_FIFO_qout_shift when (wb_FIFO_Hit = '1' and Shift_1st_QWord_k = '1')
else (others => '0');
DDR_Dout_wire <= DDR_FIFO_RdQout_swap when DDR_FIFO_Hit = '1' else (others => '0');
Regs_RdQout_wire <= Regs_RdQout --watch out!
when Regs_Hit = '1' else (others => '0');
mbuf_Din_wire_OR <= wb_FIFO_Dout_wire or DDR_Dout_wire or Regs_RdQout_wire;
-----------------------------------------------------
-- Synchronous Delay: mbuf_WE
--
Synchron_Delay_mbuf_WE :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
mbuf_WE_i <= DDR_FIFO_Write_mbuf_r1
or Regs_Write_mbuf_r2
or (wb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k and wb_FIFO_RdEn_Mask_rise_r1));
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: TxTLP_eof_n
--
Synchron_Delay_TxTLP_eof_n :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
TxTLP_eof_n_r1 <= TxTLP_eof_n;
-- TxTLP_eof_n_r2 <= TxTLP_eof_n_r1;
end if;
end process;
wb_FIFO_qout_swapped <= wb_FIFO_qout(C_DBUS_WIDTH/2-1 downto 0) & wb_FIFO_qout(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
-----------------------------------------------------
-- Synchronous Delay: wb_FIFO_qout
--
Synchron_Delay_wb_FIFO_qout :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
wb_FIFO_RdEn_Mask_rise <= wb_FIFO_RdEn_Mask and not wb_FIFO_RdEn_Mask_r1;
wb_FIFO_RdEn_Mask_rise_r1 <= wb_FIFO_RdEn_Mask_rise;
wb_FIFO_RdEn_Mask_rise_r2 <= wb_FIFO_RdEn_Mask_rise_r1;
wb_FIFO_qout_r1 <= wb_FIFO_qout_swapped;
wb_FIFO_qout_shift <= wb_FIFO_qout_r1(C_DBUS_WIDTH/2-1 downto 0)
& wb_FIFO_qout_swapped(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: mbuf_Din
--
Synchron_Delay_mbuf_Din :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
mbuf_Din_i <= (C_DBUS_WIDTH => '1', others => '0');
elsif user_clk'event and user_clk = '1' then
if Tx_TimeOut_i = '1' and DDR_FIFO_Hit = '1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (others => '1');
elsif Tx_wb_TimeOut_i = '1' and wb_FIFO_Hit = '1' and is_CplD_k = '1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (others => '1');
elsif Tx_wb_TimeOut_i = '1' and wb_FIFO_Hit = '1' and may_be_MWr_k = '1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (others => '1');
else
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= Endian_Invert_64(mbuf_Din_wire_OR);
end if;
if DDR_FIFO_Hit = '1' then
mbuf_Din_i(C_DBUS_WIDTH) <= not DDR_FIFO_RdEn_Mask;
mbuf_Din_i(70) <= TRem_n_last_QWord;
elsif wb_FIFO_Hit = '1' then
if Shift_1st_QWord_k = '1' and wb_FIFO_Rd_1Dw = '0' then
mbuf_Din_i(C_DBUS_WIDTH) <= not wb_FIFO_RdEn_Mask_r2;
else
mbuf_Din_i(C_DBUS_WIDTH) <= not wb_FIFO_RdEn_Mask_r1;
end if;
mbuf_Din_i(70) <= TRem_n_last_QWord;
else
mbuf_Din_i(C_DBUS_WIDTH) <= TxTLP_eof_n_r1;
mbuf_Din_i(70) <= TRem_n_last_QWord;
end if;
end if;
end process;
-----------------------------------------------------
-- Synchronous: Time-out counter
--
Synchron_TimeOut_Counter :
process (user_clk, TO_Cnt_Rst)
begin
if TO_Cnt_Rst = '1' then
TimeOut_Counter <= (others => '0');
elsif user_clk'event and user_clk = '1' then
TimeOut_Counter(21 downto 0) <= TimeOut_Counter(21 downto 0) + '1';
end if;
end process;
-----------------------------------------------------
-- Synchronous: Tx_TimeOut
--
SynchOUT_Tx_TimeOut :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
Tx_TimeOut_i <= '0';
elsif user_clk'event and user_clk = '1' then
if TimeOut_Counter(21 downto 6) = X"FFFF" and DDR_FIFO_Hit = '1' then
Tx_TimeOut_i <= '1';
else
Tx_TimeOut_i <= Tx_TimeOut_i;
end if;
end if;
end process;
-----------------------------------------------------
-- Synchronous: Tx_wb_TimeOut
--
SynchOUT_Tx_wb_TimeOut :
process (user_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
Tx_wb_TimeOut_i <= '0';
elsif user_clk'event and user_clk = '1' then
if TimeOut_Counter(21 downto 6) = X"FFFF" and wb_FIFO_Hit = '1' then
Tx_wb_TimeOut_i <= '1';
else
Tx_wb_TimeOut_i <= Tx_wb_TimeOut_i;
end if;
end if;
end process;
end architecture Behavioral;
|
lgpl-3.0
|
b49ae9b04c861db6bca073493b1892d1
| 0.491167 | 3.230721 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd
| 1 | 4,646 |
------------------------------------------------------------------------------
-- Title : RF channels Swapping
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This core controls the swapping mechanism for ONE pair of
-- channels. It is possible swapping channels inputs @ clk_in_ext
-- frequency or stay fixed at direct/inverted/off position.
--
-- MODE: 00 turned off 01 direct 10 inverted 11 Swapping
--
-- CTRL: b1b0d1d0
-- This core was developed to Sirus Synchrotron Light Source.
-- The BPM RFFE uses HSWA2-30DR+ switches and are controlled by
-- arrangement of bits in CTRL.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-18 1.0 jose.berkenbrock Created
-- 2012-10-20 1.1 daniel.tavares
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rf_ch_swap is
generic
(
g_direct : std_logic_vector(7 downto 0) := "10100101";
g_inverted : std_logic_vector(7 downto 0) := "01011010"
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_swap_i : in std_logic;
mode_i : in std_logic_vector(1 downto 0);
ctrl_o : out std_logic_vector(7 downto 0));
end rf_ch_swap;
architecture rtl of rf_ch_swap is
--signal s_mode : std_logic_vector(1 downto 0);
signal ctrl : std_logic_vector(7 downto 0);
--signal ctrl_aux : std_logic_vector(7 downto 0);
--signal ctrl_old : std_logic_vector(7 downto 0);
--signal s_bit : std_logic;
begin
--------------------------------
-- Input Register
--------------------------------
-- p_reg_mode : process(rst_i, clk_i)
-- begin
-- if rst_i = '1' then
-- s_mode <= (others => '0');
-- elsif rising_edge(clk_i) then
-- s_mode <= mode_i;
-- else s_mode <= s_mode;
-- end if;
-- end process p_reg_mode;
--------------------------------
-- Swapping Process
--------------------------------
p_swap : process(clk_i,rst_i)
begin
---------------------------------------------------------------
-- if rst_i = '1' then
-- s_bit <= '0';
-- ctrl_aux <= "10100101";
-- ctrl <= "10100101";
-- elsif rising_edge(clk_i) then
-- s_bit <= not s_bit;
-- else s_bit <= s_bit;
-- end if;
---------------------------------------------------------------
if rst_i = '1' then
--ctrl_old <= "10100101"; -- initialize in direct channels
--s_bit <= '0';
ctrl <= "00000000";
elsif rising_edge(clk_i) then
if mode_i = "11" then -- crossed Swapping
-- ctrl <= not ctrl;
if en_swap_i = '0' then
ctrl <= g_direct;
else
ctrl <= g_inverted;
end if;
elsif mode_i = "10" then -- inverted
ctrl <= g_inverted;
elsif mode_i = "01" then -- direct
ctrl <= g_direct;
else
ctrl <= (others=>'0'); -- Swapping off
end if;
--ctrl_old <= ctrl;
end if;
-- ctrl <= "10100101" when s_bit = '1' else "01011010";
-- with s_bit select
-- ctrl <= "10100101" when '0',
-- "01011010" when others;
---------------------------------------------------------------
end process p_swap;
---------------------------------------------------------------
-- with s_bit select
-- ctrl_aux <= "10100101" when '0',
-- "01011010" when '1';
-- ctrl_aux when others;
--
-- with s_mode select
-- ctrl <= "00000000" when "00",
-- "10100101" when "01",
-- "01011010" when "10",
-- ctrl_aux when "11";
-- ctrl when others;
--------------------------------
-- Output Register
--------------------------------
p_reg_ctrl : process(rst_i, clk_i)
begin
if rst_i = '1' then
ctrl_o <= (others => '0'); -- rst_i = 1 => Swapping off
-- ctrl_old <= "00000000";
elsif rising_edge(clk_i) then
ctrl_o <= ctrl;
-- ctrl_old <= ctrl;
end if;
end process p_reg_ctrl;
end rtl;
|
lgpl-3.0
|
3b41c3a9796543bd61d5a1dc835d44a4
| 0.433706 | 3.927303 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/memc_ui_top.vhd
| 1 | 49,683 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc_ui_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:18:11 $
-- \ \ / \ Date Created : Mon Jun 23 2008
-- \___\/\___\
--
-- Device : Virtex-6
-- Design Name : DDR2 SDRAM & DDR3 SDRAM
-- Purpose :
-- Top level memory interface block. Instantiates a clock and
-- reset generator, the memory controller, the phy and the
-- user interface blocks.
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use unisim.vcomponents.all;
entity memc_ui_top is
generic(
REFCLK_FREQ : real := 200.0;
-- DDR2 SDRAM:
-- # = 200 for all design frequencies
-- DDR3 SDRAM:
-- # = 200 for all design frequencies of
-- -1 speed grade devices
-- = 200 when design frequency < 480 MHz
-- for -2 and -3 speed grade devices
-- = 300 when design frequency >= 480 MHz
-- for -2 and -3 speed grade devices
SIM_BYPASS_INIT_CAL : string := "OFF";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Skip memory init &
-- calibration sequence
-- # = "FAST" - Skip memory init & use
-- abbreviated calib sequence
IODELAY_GRP : string := "IODELAY_MIG";
--to phy_top
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric clock.
-- # = 2, 1.
DRAM_TYPE : string := "DDR3";
-- SDRAM type. # = "DDR3", "DDR2".
nCS_PER_RANK : integer := 1;
-- # of unique CS outputs per Rank for
-- phy.
DQ_CNT_WIDTH : integer := 6;
-- # = ceil(log2(DQ_WIDTH)).
DQS_CNT_WIDTH : integer := 3;
-- # = ceil(log2(DQS_WIDTH)).
RANK_WIDTH : integer := 1;
-- # = ceil(log2(RANKS)).
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
CK_WIDTH : integer := 1;
-- # of CK/CK# outputs to memory.
CKE_WIDTH : integer := 1;
-- # of CKE outputs to memory.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
DM_WIDTH : integer := 8;
-- # of Data Mask bits.
USE_DM_PORT : integer := 1;
-- # = 1, When Data Mask option is enabled
-- = 0, When Data Mask option is disbaled
-- When Data Mask option is disbaled in
-- MIG Controller Options page, the logic
-- related to Data Mask should not get
-- synthesized
DQ_WIDTH : integer := 64;
-- # of Data (DQ) bits.
DRAM_WIDTH : integer := 8;
-- # of DQ bits per DQS.
DQS_WIDTH : integer := 8;
-- # of DQS/DQS# bits.
ROW_WIDTH : integer := 14;
-- # of memory Row Address bits.
AL : string := "0";
-- DDR3 SDRAM:
-- Additive Latency (Mode Register 1).
-- # = "0", "CL-1", "CL-2".
-- DDR2 SDRAM:
-- Additive Latency (Extended Mode Register).
BURST_MODE : string := "4";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
BURST_TYPE : string := "SEQ";
-- DDR3 SDRAM: Burst Type (Mode Register 0).
-- DDR2 SDRAM: Burst Type (Mode Register).
-- # = "SEQ" - (Sequential),
-- = "INT" - (Interleaved).
IBUF_LPWR_MODE : string := "OFF";
-- to phy_top
IODELAY_HP_MODE : string := "ON";
-- to phy_top
nAL : integer := 0;
-- # Additive Latency in number of clock
-- cycles.
CL : integer := 6;
-- DDR3 SDRAM: CAS Latency (Mode Register 0).
-- DDR2 SDRAM: CAS Latency (Mode Register).
CWL : integer := 5;
-- DDR3 SDRAM: CAS Write Latency (Mode Register 2).
-- DDR2 SDRAM: Can be ignored
DATA_BUF_ADDR_WIDTH : integer := 4;
DATA_BUF_OFFSET_WIDTH : integer := 1;
-- # = 0,1.
--DELAY_WR_DATA_CNTRL : integer := 0; --This parameter is made as MC's constant
-- # = 0,1.
BM_CNT_WIDTH : integer := 2;
-- # = ceil(log2(nBANK_MACHS)).
ADDR_CMD_MODE : string := "1T" ;
-- # = "2T", "1T".
nBANK_MACHS : integer := 4;
-- # = 2,3,4,5,6,7,8.
ORDERING : string := "STRICT";
-- # = "NORM", "STRICT".
RANKS : integer := 1;
-- # of Ranks.
WRLVL : string := "ON";
-- # = "ON" - DDR3 SDRAM
-- = "OFF" - DDR2 SDRAM.
PHASE_DETECT : string := "ON";
-- # = "ON", "OFF".
CAL_WIDTH : string := "HALF";
-- # = "HALF", "FULL".
RTT_NOM : string := "60";
-- DDR3 SDRAM:
-- RTT_NOM (ODT) (Mode Register 1).
-- # = "DISABLED" - RTT_NOM disabled,
-- = "120" - RZQ/2,
-- = "60" - RZQ/4,
-- = "40" - RZQ/6.
-- DDR2 SDRAM:
-- RTT (Nominal) (Extended Mode Register).
-- # = "DISABLED" - RTT disabled,
-- = "150" - 150 Ohms,
-- = "75" - 75 Ohms,
-- = "50" - 50 Ohms.
RTT_WR : string := "OFF";
-- DDR3 SDRAM:
-- RTT_WR (ODT) (Mode Register 2).
-- # = "OFF" - Dynamic ODT off,
-- = "120" - RZQ/2,
-- = "60" - RZQ/4,
-- DDR2 SDRAM:
-- Can be ignored. Always set to "OFF".
OUTPUT_DRV : string := "HIGH";
-- DDR3 SDRAM:
-- Output Drive Strength (Mode Register 1).
-- # = "HIGH" - RZQ/7,
-- = "LOW" - RZQ/6.
-- DDR2 SDRAM:
-- Output Drive Strength (Extended Mode Register).
-- # = "HIGH" - FULL,
-- = "LOW" - REDUCED.
REG_CTRL : string := "OFF";
-- # = "ON" - RDIMMs,
-- = "OFF" - Components, SODIMMs, UDIMMs.
nDQS_COL0 : integer :=6;
-- Number of DQS groups in I/O column #1.
nDQS_COL1 : integer := 2;
-- Number of DQS groups in I/O column #2.
nDQS_COL2 : integer := 0;
-- Number of DQS groups in I/O column #3.
nDQS_COL3 : integer := 0;
-- Number of DQS groups in I/O column #4.
DQS_LOC_COL0 : std_logic_vector(23 downto 0) := X"020100";
-- DQS groups in column #1.
DQS_LOC_COL1 : std_logic_vector(39 downto 0) := X"0706050403";
-- DQS groups in column #2.
DQS_LOC_COL2 : std_logic_vector(0 downto 0) := "0";
-- DQS groups in column #3.
DQS_LOC_COL3 : std_logic_vector(0 downto 0) := "0";
-- DQS groups in column #4.
tCK : integer := 2500;
-- memory tCK paramter.
-- # = Clock Period.
tFAW : integer := 45000;
-- memory tRAW paramter.
tPRDI : integer := 1000000;
-- memory tPRDI paramter.
tRRD : integer := 7500;
-- memory tRRD paramter.
tRAS : integer := 36000;
-- memory tRAS paramter.
tRCD : integer := 13500;
-- memory tRCD paramter.
tREFI : integer := 7800000;
-- memory tREFI paramter.
tRFC : integer := 160000;
-- memory tRFC paramter.
tRP : integer := 13500;
-- memory tRP paramter.
tRTP : integer := 7500;
-- memory tRTP paramter.
tWTR : integer := 7500;
-- memory tWTR paramter.
tZQI : integer := 128000000;
-- memory tZQI paramter.
tZQCS : integer := 64;
-- memory tZQCS paramter.
SLOT_0_CONFIG : std_logic_vector(7 downto 0) := X"01";
-- Mapping of Ranks.
SLOT_1_CONFIG : std_logic_vector(7 downto 0) := X"00";
-- Mapping of Ranks.
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
ADDR_WIDTH : integer := 28;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
STARVE_LIMIT : integer := 2;
-- # = 2,3,4.
TCQ : integer := 100;
ECC : string := "OFF";
DATA_WIDTH : integer := 64;
-- # = DQ_WIDTH + ECC_WIDTH, if ECC="ON";
-- = DQ_WIDTH, if ECC="OFF".
ECC_TEST : string := "OFF";
PAYLOAD_WIDTH : integer := 64;
-- UI_INTFC Parameters
APP_DATA_WIDTH : integer := 64*4;
-- (PAYLOAD_WIDTH * 4)
APP_MASK_WIDTH : integer := 64/2
-- (APP_DATA_WIDTH / 8)
);
port(
clk : in std_logic;
clk_mem : in std_logic;
clk_rd_base : in std_logic;
rst : in std_logic;
ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
ddr_cas_n : out std_logic;
ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
ddr_odt : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
ddr_ras_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_parity : out std_logic;
ddr_we_n : out std_logic;
ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
pd_PSEN : out std_logic;
pd_PSINCDEC : out std_logic;
pd_PSDONE : in std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
phy_init_done : out std_logic;
app_ecc_multiple_err : out std_logic_vector(3 downto 0);
app_rd_data : out std_logic_vector(APP_DATA_WIDTH-1 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_hi_pri : in std_logic;
app_sz : in std_logic;
app_wdf_data : in std_logic_vector(APP_DATA_WIDTH-1 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(APP_MASK_WIDTH-1 downto 0);
app_wdf_wren : in std_logic;
app_correct_en : in std_logic;
dbg_wr_dqs_tap_set : in std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_wr_dq_tap_set : in std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_wr_tap_set_en : in std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
dbg_wl_dqs_inverted : out std_logic_vector(DQS_WIDTH-1 downto 0);
dbg_wr_calib_clk_delay : out std_logic_vector(2*DQS_WIDTH-1 downto 0);
dbg_wl_odelay_dqs_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_wl_odelay_dq_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_rd_bitslip_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
dbg_rd_clkdly_cnt : out std_logic_vector(2*DQS_WIDTH-1 downto 0);
dbg_rd_active_dly : out std_logic_vector(4 downto 0);
dbg_pd_off : in std_logic;
dbg_pd_maintain_off : in std_logic;
dbg_pd_maintain_0_only : in std_logic;
dbg_inc_cpt : in std_logic;
dbg_dec_cpt : in std_logic;
dbg_inc_rd_dqs : in std_logic;
dbg_dec_rd_dqs : in std_logic;
dbg_inc_dec_sel : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_inc_rd_fps : in std_logic;
dbg_dec_rd_fps : in std_logic;
dbg_dqs_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_dq_tap_cnt : out std_logic_vector(5*DQS_WIDTH-1 downto 0);
dbg_rddata : out std_logic_vector(4*DQ_WIDTH-1 downto 0)
);
end entity memc_ui_top;
architecture arch_memc_ui_top of memc_ui_top is
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of arch_memc_ui_top : ARCHITECTURE IS
"mig_v3_92_ddr3_V6, Coregen 14.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of arch_memc_ui_top : ARCHITECTURE IS "ddr3_V6,mig_v3_92,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=2500, MEMORY_TYPE=SODIMM, MEMORY_PART=mt4jsf12864hz-1g4, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, BURST_MODE=4, BURST_TYPE=SEQ, OUTPUT_DRV=HIGH, RTT_NOM=60, REFCLK_FREQ=200, MMCM_ADV_BANDWIDTH=OPTIMIZED, CLKFBOUT_MULT_F=6, CLKOUT_DIVIDE=3, DEBUG_PORT=OFF, IODELAY_HP_MODE=ON, INTERNAL_VREF=0, DCI_INOUTS=1, CLASS_ADDR=I, INPUT_CLK_TYPE=SINGLE_ENDED}";
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
function ECCWIDTH return integer is
begin
if(ECC = "OFF") then
return 0;
else
if(DATA_WIDTH <= 4) then
return 4;
elsif(DATA_WIDTH <= 10) then
return 5;
elsif(DATA_WIDTH <= 26) then
return 6;
elsif(DATA_WIDTH <= 57) then
return 7;
elsif(DATA_WIDTH <= 120) then
return 8;
elsif(DATA_WIDTH <= 247) then
return 9;
else
return 10;
end if;
end if;
end function;
constant nPHY_WRLAT : integer := 0;
constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
+ COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
constant ECC_WIDTH : integer := ECCWIDTH;
-- constant PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
constant DLC0_zeros : std_logic_vector(143 downto 23+1) := (others => '0');
constant DLC1_zeros : std_logic_vector(143 downto 39+1) := (others => '0');
constant DLC2_zeros : std_logic_vector(143 downto 0+1) := (others => '0');
constant DLC3_zeros : std_logic_vector(143 downto 0+1) := (others => '0');
constant DQS_LOC_COL0_i : std_logic_vector(143 downto 0) := (DLC0_zeros & DQS_LOC_COL0);
constant DQS_LOC_COL1_i : std_logic_vector(143 downto 0) := (DLC1_zeros & DQS_LOC_COL1);
constant DQS_LOC_COL2_i : std_logic_vector(143 downto 0) := (DLC2_zeros & DQS_LOC_COL2);
constant DQS_LOC_COL3_i : std_logic_vector(143 downto 0) := (DLC3_zeros & DQS_LOC_COL3);
component mem_intfc
generic (
TCQ : integer;
PAYLOAD_WIDTH : integer;
ADDR_CMD_MODE : string;
AL : string;
BANK_WIDTH : integer;
BM_CNT_WIDTH : integer;
BURST_MODE : string;
BURST_TYPE : string;
CK_WIDTH : integer;
CKE_WIDTH : integer;
CL : integer;
COL_WIDTH : integer;
CS_WIDTH : integer;
CWL : integer;
DATA_WIDTH : integer;
DATA_BUF_ADDR_WIDTH : integer;
DATA_BUF_OFFSET_WIDTH : integer;
DM_WIDTH : integer;
DQ_CNT_WIDTH : integer;
DQ_WIDTH : integer;
DQS_CNT_WIDTH : integer;
DQS_WIDTH : integer;
DRAM_TYPE : string;
DRAM_WIDTH : integer;
ECC : string;
ECC_WIDTH : integer;
MC_ERR_ADDR_WIDTH : integer;
nAL : integer;
nBANK_MACHS : integer;
nCK_PER_CLK : integer;
nCS_PER_RANK : integer;
ORDERING : string;
PHASE_DETECT : string;
IBUF_LPWR_MODE : string;
IODELAY_HP_MODE : string;
IODELAY_GRP : string;
OUTPUT_DRV : string;
REG_CTRL : string;
RTT_NOM : string;
RTT_WR : string;
STARVE_LIMIT : integer;
tCK : integer;
tFAW : integer;
tPRDI : integer;
tRAS : integer;
tRCD : integer;
tREFI : integer;
tRFC : integer;
tRP : integer;
tRRD : integer;
tRTP : integer;
tWTR : integer;
tZQI : integer;
tZQCS : integer;
WRLVL : string;
DEBUG_PORT : string;
CAL_WIDTH : string;
RANK_WIDTH : integer;
RANKS : integer;
ROW_WIDTH : integer;
SLOT_0_CONFIG : std_logic_vector(7 downto 0);
SLOT_1_CONFIG : std_logic_vector(7 downto 0);
SIM_BYPASS_INIT_CAL : string;
REFCLK_FREQ : real;
nDQS_COL0 : integer;
nDQS_COL1 : integer;
nDQS_COL2 : integer;
nDQS_COL3 : integer;
DQS_LOC_COL0 : std_logic_vector (143 downto 0);
DQS_LOC_COL1 : std_logic_vector (143 downto 0);
DQS_LOC_COL2 : std_logic_vector (143 downto 0);
DQS_LOC_COL3 : std_logic_vector (143 downto 0);
USE_DM_PORT : integer
);
port (
wr_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
wr_data_en : out std_logic;
wr_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rd_data_offset : out std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
rd_data_en : out std_logic;
rd_data_addr : out std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
ddr_we_n : out std_logic;
ddr_parity : out std_logic;
ddr_reset_n : out std_logic;
ddr_ras_n : out std_logic;
ddr_odt : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_dm : out std_logic_vector(DM_WIDTH - 1 downto 0);
ddr_cs_n : out std_logic_vector(CS_WIDTH * nCS_PER_RANK - 1 downto 0);
ddr_cke : out std_logic_vector(CKE_WIDTH - 1 downto 0);
ddr_ck : out std_logic_vector(CK_WIDTH - 1 downto 0);
ddr_ck_n : out std_logic_vector(CK_WIDTH - 1 downto 0);
ddr_cas_n : out std_logic;
ddr_ba : out std_logic_vector(BANK_WIDTH - 1 downto 0);
ddr_addr : out std_logic_vector(ROW_WIDTH - 1 downto 0);
dbg_wr_dqs_tap_set : in std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_wr_dq_tap_set : in std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_wr_tap_set_en : in std_logic;
dbg_wrlvl_start : out std_logic;
dbg_wrlvl_done : out std_logic;
dbg_wrlvl_err : out std_logic;
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
dbg_rd_active_dly : out std_logic_vector( 4 downto 0);
dbg_wl_dqs_inverted : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dbg_wr_calib_clk_delay : out std_logic_vector(2 * DQS_WIDTH - 1 downto 0);
dbg_wl_odelay_dqs_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_wl_odelay_dq_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_tap_cnt_during_wrlvl : out std_logic_vector(4 downto 0);
dbg_wl_edge_detect_valid : out std_logic;
dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH - 1 downto 0);
dbg_rdlvl_start : out std_logic_vector(1 downto 0);
dbg_rdlvl_done : out std_logic_vector(1 downto 0);
dbg_rdlvl_err : out std_logic_vector(1 downto 0);
dbg_cpt_first_edge_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_cpt_second_edge_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_rd_bitslip_cnt : out std_logic_vector(3 * DQS_WIDTH - 1 downto 0);
dbg_rd_clkdly_cnt : out std_logic_vector(2 * DQS_WIDTH - 1 downto 0);
dbg_rddata : out std_logic_vector(4 * DQ_WIDTH - 1 downto 0);
dbg_idel_up_all : in std_logic;
dbg_idel_down_all : in std_logic;
dbg_idel_up_cpt : in std_logic;
dbg_idel_down_cpt : in std_logic;
dbg_idel_up_rsync : in std_logic;
dbg_idel_down_rsync : in std_logic;
dbg_sel_all_idel_cpt : in std_logic;
dbg_sel_all_idel_rsync : in std_logic;
dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_sel_idel_rsync : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_cpt_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_rsync_tap_cnt : out std_logic_vector(19 downto 0);
dbg_dqs_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_dq_tap_cnt : out std_logic_vector(5 * DQS_WIDTH - 1 downto 0);
dbg_pd_off : in std_logic;
dbg_pd_maintain_off : in std_logic;
dbg_pd_maintain_0_only : in std_logic;
dbg_pd_inc_cpt : in std_logic;
dbg_pd_dec_cpt : in std_logic;
dbg_pd_inc_dqs : in std_logic;
dbg_pd_dec_dqs : in std_logic;
dbg_pd_disab_hyst : in std_logic;
dbg_pd_disab_hyst_0 : in std_logic;
dbg_pd_msb_sel : in std_logic_vector(3 downto 0);
dbg_pd_byte_sel : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
dbg_inc_rd_fps : in std_logic;
dbg_dec_rd_fps : in std_logic;
dbg_phy_pd : out std_logic_vector(255 downto 0);
dbg_phy_read : out std_logic_vector(255 downto 0);
dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
dbg_phy_top : out std_logic_vector(255 downto 0);
accept : out std_logic;
accept_ns : out std_logic;
rd_data : out std_logic_vector((4 * PAYLOAD_WIDTH) - 1 downto 0);
pd_PSEN : out std_logic;
pd_PSINCDEC : out std_logic;
rd_data_end : out std_logic;
dfi_init_complete : out std_logic;
ecc_single : out std_logic_vector(3 downto 0);
ecc_multiple : out std_logic_vector(3 downto 0);
ecc_err_addr : out std_logic_vector(MC_ERR_ADDR_WIDTH - 1 downto 0);
ddr_dqs : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dq : inout std_logic_vector(DQ_WIDTH - 1 downto 0);
use_addr : in std_logic;
size : in std_logic;
rst : in std_logic;
row : in std_logic_vector(ROW_WIDTH - 1 downto 0);
rank : in std_logic_vector(RANK_WIDTH - 1 downto 0);
hi_priority : in std_logic;
data_buf_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
col : in std_logic_vector(COL_WIDTH - 1 downto 0);
cmd : in std_logic_vector(2 downto 0);
clk_mem : in std_logic;
clk : in std_logic;
clk_rd_base : in std_logic;
bank : in std_logic_vector(BANK_WIDTH - 1 downto 0);
wr_data : in std_logic_vector((4 * PAYLOAD_WIDTH) - 1 downto 0);
wr_data_mask : in std_logic_vector((4 * (DATA_WIDTH / 8)) - 1 downto 0);
pd_PSDONE : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
correct_en : in std_logic;
raw_not_ecc : in std_logic_vector(3 downto 0)
);
end component mem_intfc;
component ui_top
generic (
TCQ : integer;
APP_DATA_WIDTH : integer;
APP_MASK_WIDTH : integer;
BANK_WIDTH : integer;
COL_WIDTH : integer;
CWL : integer;
ECC : string;
ECC_TEST : string;
ORDERING : string;
RANKS : integer;
RANK_WIDTH : integer;
ROW_WIDTH : integer;
MEM_ADDR_ORDER : string
);
port (
wr_data_mask : out std_logic_vector(APP_MASK_WIDTH - 1 downto 0);
wr_data : out std_logic_vector(APP_DATA_WIDTH - 1 downto 0);
use_addr : out std_logic;
size : out std_logic;
row : out std_logic_vector(ROW_WIDTH - 1 downto 0);
raw_not_ecc : out std_logic_vector(3 downto 0);
rank : out std_logic_vector(RANK_WIDTH - 1 downto 0);
hi_priority : out std_logic;
data_buf_addr : out std_logic_vector(3 downto 0);
col : out std_logic_vector(COL_WIDTH - 1 downto 0);
cmd : out std_logic_vector(2 downto 0);
bank : out std_logic_vector(BANK_WIDTH - 1 downto 0);
app_wdf_rdy : out std_logic;
app_rdy : out std_logic;
app_rd_data_valid : out std_logic;
app_rd_data_end : out std_logic;
app_rd_data : out std_logic_vector(APP_DATA_WIDTH - 1 downto 0);
app_ecc_multiple_err : out std_logic_vector(3 downto 0);
correct_en : out std_logic;
wr_data_offset : in std_logic;
wr_data_en : in std_logic;
wr_data_addr : in std_logic_vector(3 downto 0);
rst : in std_logic;
rd_data_offset : in std_logic;
rd_data_end : in std_logic;
rd_data_en : in std_logic;
rd_data_addr : in std_logic_vector(3 downto 0);
rd_data : in std_logic_vector(APP_DATA_WIDTH - 1 downto 0);
ecc_multiple : in std_logic_vector(3 downto 0);
clk : in std_logic;
app_wdf_wren : in std_logic;
app_wdf_mask : in std_logic_vector(APP_MASK_WIDTH - 1 downto 0);
app_wdf_end : in std_logic;
app_wdf_data : in std_logic_vector(APP_DATA_WIDTH - 1 downto 0);
app_sz : in std_logic;
app_raw_not_ecc : in std_logic_vector(3 downto 0);
app_hi_pri : in std_logic;
app_en : in std_logic;
app_cmd : in std_logic_vector(2 downto 0);
app_addr : in std_logic_vector(RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH - 1 downto 0);
accept_ns : in std_logic;
accept : in std_logic;
app_correct_en : in std_logic
);
end component ui_top;
signal correct_en : std_logic;
signal raw_not_ecc : std_logic_vector(3 downto 0);
signal ecc_single : std_logic_vector(3 downto 0);
signal ecc_multiple : std_logic_vector(3 downto 0);
signal ecc_err_addr : std_logic_vector(MC_ERR_ADDR_WIDTH-1 downto 0);
signal app_raw_not_ecc : std_logic_vector(3 downto 0);
signal wr_data_offset : std_logic_vector(DATA_BUF_OFFSET_WIDTH-1 downto 0);
signal wr_data_en : std_logic;
signal wr_data_addr : std_logic_vector(DATA_BUF_ADDR_WIDTH-1 downto 0);
signal rd_data_offset : std_logic_vector(DATA_BUF_OFFSET_WIDTH-1 downto 0);
signal rd_data_en : std_logic;
signal rd_data_addr : std_logic_vector(DATA_BUF_ADDR_WIDTH-1 downto 0);
signal accept : std_logic;
signal accept_ns : std_logic;
signal rd_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
signal rd_data_end : std_logic;
signal use_addr : std_logic;
signal size : std_logic;
signal row : std_logic_vector(ROW_WIDTH-1 downto 0);
signal rank : std_logic_vector(RANK_WIDTH-1 downto 0);
signal hi_priority : std_logic;
signal data_buf_addr : std_logic_vector(DATA_BUF_ADDR_WIDTH-1 downto 0);
signal col : std_logic_vector(COL_WIDTH-1 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal bank : std_logic_vector(BANK_WIDTH-1 downto 0);
signal wr_data : std_logic_vector((4*PAYLOAD_WIDTH)-1 downto 0);
signal wr_data_mask : std_logic_vector((4*(PAYLOAD_WIDTH/8))-1 downto 0);
begin
u_mem_intfc : mem_intfc
generic map(
TCQ => TCQ,
ADDR_CMD_MODE => ADDR_CMD_MODE,
AL => AL,
BANK_WIDTH => BANK_WIDTH,
BM_CNT_WIDTH => BM_CNT_WIDTH,
BURST_MODE => BURST_MODE,
BURST_TYPE => BURST_TYPE,
CK_WIDTH => CK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
CL => CL,
COL_WIDTH => COL_WIDTH,
CS_WIDTH => CS_WIDTH,
CWL => CWL,
DATA_WIDTH => DATA_WIDTH,
DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
DATA_BUF_OFFSET_WIDTH => DATA_BUF_OFFSET_WIDTH,
--DELAY_WR_DATA_CNTRL => DELAY_WR_DATA_CNTRL,
DM_WIDTH => DM_WIDTH,
DQ_CNT_WIDTH => DQ_CNT_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DQS_CNT_WIDTH => DQS_CNT_WIDTH,
DQS_WIDTH => DQS_WIDTH,
DRAM_TYPE => DRAM_TYPE,
DRAM_WIDTH => DRAM_WIDTH,
ECC => ECC,
PAYLOAD_WIDTH => PAYLOAD_WIDTH,
ECC_WIDTH => ECC_WIDTH,
MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
nAL => nAL,
nBANK_MACHS => nBANK_MACHS,
nCK_PER_CLK => nCK_PER_CLK,
nCS_PER_RANK => nCS_PER_RANK,
ORDERING => ORDERING,
PHASE_DETECT => PHASE_DETECT,
IBUF_LPWR_MODE => IBUF_LPWR_MODE,
IODELAY_HP_MODE => IODELAY_HP_MODE,
IODELAY_GRP => IODELAY_GRP,
OUTPUT_DRV => OUTPUT_DRV,
REG_CTRL => REG_CTRL,
RTT_NOM => RTT_NOM,
RTT_WR => RTT_WR,
STARVE_LIMIT => STARVE_LIMIT,
tCK => tCK,
tFAW => tFAW,
tPRDI => tPRDI,
tRAS => tRAS,
tRCD => tRCD,
tREFI => tREFI,
tRFC => tRFC,
tRP => tRP,
tRRD => tRRD,
tRTP => tRTP,
tWTR => tWTR,
tZQI => tZQI,
tZQCS => tZQCS,
WRLVL => WRLVL,
DEBUG_PORT => DEBUG_PORT,
CAL_WIDTH => CAL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
ROW_WIDTH => ROW_WIDTH,
SLOT_0_CONFIG => SLOT_0_CONFIG,
SLOT_1_CONFIG => SLOT_1_CONFIG,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
REFCLK_FREQ => REFCLK_FREQ,
nDQS_COL0 => nDQS_COL0,
nDQS_COL1 => nDQS_COL1,
nDQS_COL2 => nDQS_COL2,
nDQS_COL3 => nDQS_COL3,
DQS_LOC_COL0 => DQS_LOC_COL0_i,
DQS_LOC_COL1 => DQS_LOC_COL1_i,
DQS_LOC_COL2 => DQS_LOC_COL2_i,
DQS_LOC_COL3 => DQS_LOC_COL3_i,
USE_DM_PORT => USE_DM_PORT
)
port map(
wr_data_offset => wr_data_offset,
wr_data_en => wr_data_en,
wr_data_addr => wr_data_addr,
rd_data_offset => rd_data_offset,
rd_data_en => rd_data_en,
rd_data_addr => rd_data_addr,
ddr_we_n => ddr_we_n,
ddr_parity => ddr_parity,
ddr_reset_n => ddr_reset_n,
ddr_ras_n => ddr_ras_n,
ddr_odt => ddr_odt,
ddr_dm => ddr_dm,
ddr_cs_n => ddr_cs_n,
ddr_cke => ddr_cke,
ddr_ck => ddr_ck,
ddr_ck_n => ddr_ck_n,
ddr_cas_n => ddr_cas_n,
ddr_ba => ddr_ba,
ddr_addr => ddr_addr,
dbg_wr_dqs_tap_set => dbg_wr_dqs_tap_set,
dbg_wr_dq_tap_set => dbg_wr_dq_tap_set,
dbg_wr_tap_set_en => dbg_wr_tap_set_en,
dbg_wrlvl_start => dbg_wrlvl_start,
dbg_wrlvl_done => dbg_wrlvl_done,
dbg_wrlvl_err => dbg_wrlvl_err,
dbg_wl_dqs_inverted => dbg_wl_dqs_inverted,
dbg_wr_calib_clk_delay => dbg_wr_calib_clk_delay,
dbg_wl_odelay_dqs_tap_cnt => dbg_wl_odelay_dqs_tap_cnt,
dbg_wl_odelay_dq_tap_cnt => dbg_wl_odelay_dq_tap_cnt,
dbg_tap_cnt_during_wrlvl => open,
dbg_wl_edge_detect_valid => open,
dbg_rd_data_edge_detect => open,
dbg_rdlvl_start => dbg_rdlvl_start,
dbg_rdlvl_done => dbg_rdlvl_done,
dbg_rdlvl_err => dbg_rdlvl_err,
dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
dbg_rd_bitslip_cnt => dbg_rd_bitslip_cnt,
dbg_rd_clkdly_cnt => dbg_rd_clkdly_cnt,
dbg_rd_active_dly => dbg_rd_active_dly,
dbg_rddata => dbg_rddata,
-- Currently CPT clock IODELAY taps must be moved on per-DQS group
-- basis-only - i.e. all CPT clocks cannot be moved simultaneously
-- If desired to change this, rewire dbg_idel_*_all, and
-- dbg_sel_idel_*_* accordingly. Also no support for changing DQS
-- and CPT taps via phase detector. Note: can change CPT taps via
-- dbg_idel_*_cpt, but PD must off when this happens
dbg_idel_up_all => '0',
dbg_idel_down_all => '0',
dbg_idel_up_cpt => dbg_inc_cpt,
dbg_idel_down_cpt => dbg_dec_cpt,
dbg_idel_up_rsync => '0',
dbg_idel_down_rsync => '0',
dbg_sel_idel_cpt => dbg_inc_dec_sel,
dbg_sel_all_idel_cpt => '0',
dbg_sel_idel_rsync => (others => '0'),
dbg_sel_all_idel_rsync => '0',
dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
dbg_rsync_tap_cnt => open,
dbg_dqs_tap_cnt => dbg_dqs_tap_cnt,
dbg_dq_tap_cnt => dbg_dq_tap_cnt,
dbg_pd_off => dbg_pd_off,
dbg_pd_maintain_off => dbg_pd_maintain_off,
dbg_pd_maintain_0_only => dbg_pd_maintain_0_only,
dbg_pd_inc_cpt => '0',
dbg_pd_dec_cpt => '0',
dbg_pd_inc_dqs => dbg_inc_rd_dqs,
dbg_pd_dec_dqs => dbg_dec_rd_dqs,
dbg_pd_disab_hyst => '0',
dbg_pd_disab_hyst_0 => '0',
dbg_pd_msb_sel => (others => '0'),
dbg_pd_byte_sel => dbg_inc_dec_sel,
dbg_inc_rd_fps => dbg_inc_rd_fps,
dbg_dec_rd_fps => dbg_dec_rd_fps,
dbg_phy_pd => open,
dbg_phy_read => open,
dbg_phy_rdlvl => open,
dbg_phy_top => open,
bank_mach_next => bank_mach_next,
accept => accept,
accept_ns => accept_ns,
rd_data => rd_data((PAYLOAD_WIDTH*4)-1 downto 0),
rd_data_end => rd_data_end,
pd_PSEN => pd_PSEN,
dfi_init_complete => phy_init_done,
pd_PSINCDEC => pd_PSINCDEC,
ecc_single => ecc_single,
ecc_multiple => ecc_multiple,
ecc_err_addr => ecc_err_addr,
ddr_dqs => ddr_dqs,
ddr_dqs_n => ddr_dqs_n,
ddr_dq => ddr_dq,
use_addr => use_addr,
size => size,
rst => rst,
row => row,
rank => rank,
hi_priority => '0',
data_buf_addr => data_buf_addr,
col => col,
cmd => cmd,
clk_mem => clk_mem,
clk => clk,
clk_rd_base => clk_rd_base,
bank => bank,
wr_data => wr_data,
wr_data_mask => wr_data_mask(4 * DATA_WIDTH / 8 - 1 downto 0),
pd_PSDONE => pd_PSDONE,
slot_0_present => SLOT_0_CONFIG,
slot_1_present => SLOT_1_CONFIG,
correct_en => correct_en,
raw_not_ecc => raw_not_ecc
);
u_ui_top : ui_top
generic map(
TCQ => TCQ,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
BANK_WIDTH => BANK_WIDTH,
COL_WIDTH => COL_WIDTH,
CWL => CWL,
ECC => ECC,
ECC_TEST => ECC_TEST,
ORDERING => ORDERING,
RANKS => RANKS,
RANK_WIDTH => RANK_WIDTH,
ROW_WIDTH => ROW_WIDTH,
MEM_ADDR_ORDER => MEM_ADDR_ORDER
)
port map(
wr_data_mask => wr_data_mask,
wr_data => wr_data(APP_DATA_WIDTH-1 downto 0),
use_addr => use_addr,
size => size,
row => row(ROW_WIDTH-1 downto 0),
rank => rank(RANK_WIDTH-1 downto 0),
hi_priority => hi_priority,
data_buf_addr => data_buf_addr(3 downto 0),
col => col,
cmd => cmd,
bank => bank,
app_wdf_rdy => app_wdf_rdy,
app_rdy => app_rdy,
app_rd_data_valid => app_rd_data_valid,
app_rd_data_end => app_rd_data_end,
app_rd_data => app_rd_data,
wr_data_offset => std_logic(wr_data_offset(DATA_BUF_OFFSET_WIDTH-1)),
wr_data_en => wr_data_en,
wr_data_addr => wr_data_addr(3 downto 0),
rst => rst,
rd_data_offset => std_logic(rd_data_offset(DATA_BUF_OFFSET_WIDTH-1)),
rd_data_end => rd_data_end,
rd_data_en => rd_data_en,
rd_data_addr => rd_data_addr(3 downto 0),
rd_data => rd_data(APP_DATA_WIDTH-1 downto 0),
clk => clk,
raw_not_ecc => raw_not_ecc,
app_ecc_multiple_err => app_ecc_multiple_err,
correct_en => correct_en,
ecc_multiple => ecc_multiple,
app_raw_not_ecc => app_raw_not_ecc,
app_correct_en => app_correct_en,
app_wdf_wren => app_wdf_wren,
app_wdf_mask => app_wdf_mask,
app_wdf_end => app_wdf_end,
app_wdf_data => app_wdf_data,
app_sz => app_sz,
app_hi_pri => app_hi_pri,
app_en => app_en,
app_cmd => app_cmd,
app_addr => app_addr,
accept_ns => accept_ns,
accept => accept
);
end arch_memc_ui_top;
|
lgpl-3.0
|
811da4754dbacb49a0428a3618975fe7
| 0.436467 | 4.052778 | false | false | false | false |
rodrigosurita/new-crpuf
|
vhdl/src/std_logic_textio.vhd
| 9 | 17,971 |
----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: STD_LOGIC_TEXTIO
--
-- Purpose: This package overloads the standard TEXTIO procedures
-- READ and WRITE.
--
-- Author: CRC, TS
--
----------------------------------------------------------------------------
use STD.textio.all;
library IEEE;
use IEEE.std_logic_1164.all;
package STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Read and Write procedures for STD_ULOGIC and STD_ULOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD: out BOOLEAN);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--
-- Read and Write procedures for Hex and Octal values.
-- The values appear in the file as a series of characters
-- between 0-F (Hex), or 0-7 (Octal) respectively.
--
-- Hex
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- Octal
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
package body STD_LOGIC_TEXTIO is
--synopsys synthesis_off
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', ERROR);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of character;
type MVL9_indexed_by_char is array (character) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (character) of MVL9plus;
constant MVL9_to_char: char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9: MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus: MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => ERROR);
-- Overloaded procedures.
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC; GOOD:out BOOLEAN) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
good := FALSE;
else
value := char_to_MVL9(c);
good := TRUE;
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR; GOOD:out BOOLEAN) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
read(l, s);
for i in integer range 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
good := FALSE;
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in integer range 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
good := TRUE;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC) is
variable c: character;
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := 'U';
assert FALSE report "READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
else
value := char_to_MVL9(c);
end if;
end READ;
procedure READ(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable m: STD_ULOGIC;
variable c: character;
variable s: string(1 to value'length-1);
variable mv: STD_ULOGIC_VECTOR(0 to value'length-1);
constant allU: STD_ULOGIC_VECTOR(0 to value'length-1)
:= (others => 'U');
begin
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
if (char_to_MVL9plus(c) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal.";
return;
end if;
read(l, s);
for i in integer range 1 to value'length-1 loop
if (char_to_MVL9plus(s(i)) = ERROR) then
value := allU;
assert FALSE report
"READ(STD_ULOGIC_VECTOR) Error: Character '" &
s(i) & "' read, expected STD_ULOGIC literal.";
return;
end if;
end loop;
mv(0) := char_to_MVL9(c);
for i in integer range 1 to value'length-1 loop
mv(i) := char_to_MVL9(s(i));
end loop;
value := mv;
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
write(l, MVL9_to_char(value), justified, field);
end WRITE;
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
READ(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end READ;
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
WRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end WRITE;
--
-- Hex Read and Write procedures.
--
--
-- Hex, and Octal Read and Write procedures for BIT_VECTOR
-- (these procedures are not exported, they are only used
-- by the STD_ULOGIC hex/octal reads and writes below.
--
--
procedure Char2QuadBits(C: Character;
RESULT: out Bit_Vector(3 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := x"0"; good := TRUE;
when '1' => result := x"1"; good := TRUE;
when '2' => result := x"2"; good := TRUE;
when '3' => result := x"3"; good := TRUE;
when '4' => result := x"4"; good := TRUE;
when '5' => result := x"5"; good := TRUE;
when '6' => result := x"6"; good := TRUE;
when '7' => result := x"7"; good := TRUE;
when '8' => result := x"8"; good := TRUE;
when '9' => result := x"9"; good := TRUE;
when 'A' => result := x"A"; good := TRUE;
when 'B' => result := x"B"; good := TRUE;
when 'C' => result := x"C"; good := TRUE;
when 'D' => result := x"D"; good := TRUE;
when 'E' => result := x"E"; good := TRUE;
when 'F' => result := x"F"; good := TRUE;
when 'a' => result := x"A"; good := TRUE;
when 'b' => result := x"B"; good := TRUE;
when 'c' => result := x"C"; good := TRUE;
when 'd' => result := x"D"; good := TRUE;
when 'e' => result := x"E"; good := TRUE;
when 'f' => result := x"F"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"HREAD Error: Read a '" & c &
"', expected a Hex character (0-F).";
end if;
good := FALSE;
end case;
end;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HREAD Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "HREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 4 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2QuadBits(c, bv(0 to 3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2QuadBits(s(i), bv(4*i to 4*i+3), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable quad: bit_vector(0 to 3);
constant ne: integer := value'length/4;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 4 /= 0 then
assert FALSE report
"HWRITE Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
for i in 0 to ne-1 loop
quad := bv(4*i to 4*i+3);
case quad is
when x"0" => s(i+1) := '0';
when x"1" => s(i+1) := '1';
when x"2" => s(i+1) := '2';
when x"3" => s(i+1) := '3';
when x"4" => s(i+1) := '4';
when x"5" => s(i+1) := '5';
when x"6" => s(i+1) := '6';
when x"7" => s(i+1) := '7';
when x"8" => s(i+1) := '8';
when x"9" => s(i+1) := '9';
when x"A" => s(i+1) := 'A';
when x"B" => s(i+1) := 'B';
when x"C" => s(i+1) := 'C';
when x"D" => s(i+1) := 'D';
when x"E" => s(i+1) := 'E';
when x"F" => s(i+1) := 'F';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end HWRITE;
procedure Char2TriBits(C: Character;
RESULT: out bit_vector(2 downto 0);
GOOD: out Boolean;
ISSUE_ERROR: in Boolean) is
begin
case c is
when '0' => result := o"0"; good := TRUE;
when '1' => result := o"1"; good := TRUE;
when '2' => result := o"2"; good := TRUE;
when '3' => result := o"3"; good := TRUE;
when '4' => result := o"4"; good := TRUE;
when '5' => result := o"5"; good := TRUE;
when '6' => result := o"6"; good := TRUE;
when '7' => result := o"7"; good := TRUE;
when others =>
if ISSUE_ERROR then
assert FALSE report
"OREAD Error: Read a '" & c &
"', expected an Octal character (0-7).";
end if;
good := FALSE;
end case;
end;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR) is
variable c: character;
variable ok: boolean;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OREAD Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, TRUE);
if not ok then
return;
end if;
read(L, s, ok);
if not ok then
assert FALSE
report "OREAD Error: Failed to read the STRING";
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, TRUE);
if not ok then
return;
end if;
end loop;
value := bv;
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out BIT_VECTOR;GOOD: out BOOLEAN) is
variable ok: boolean;
variable c: character;
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1);
variable s: string(1 to ne-1);
begin
if value'length mod 3 /= 0 then
good := FALSE;
return;
end if;
loop -- skip white space
read(l,c);
exit when ((c /= ' ') and (c /= CR) and (c /= HT));
end loop;
Char2TriBits(c, bv(0 to 2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
read(L, s, ok);
if not ok then
good := FALSE;
return;
end if;
for i in 1 to ne-1 loop
Char2TriBits(s(i), bv(3*i to 3*i+2), ok, FALSE);
if not ok then
good := FALSE;
return;
end if;
end loop;
good := TRUE;
value := bv;
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in BIT_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable tri: bit_vector(0 to 2);
constant ne: integer := value'length/3;
variable bv: bit_vector(0 to value'length-1) := value;
variable s: string(1 to ne);
begin
if value'length mod 3 /= 0 then
assert FALSE report
"OWRITE Error: Trying to read vector " &
"with an odd (non multiple of 3) length";
return;
end if;
for i in 0 to ne-1 loop
tri := bv(3*i to 3*i+2);
case tri is
when o"0" => s(i+1) := '0';
when o"1" => s(i+1) := '1';
when o"2" => s(i+1) := '2';
when o"3" => s(i+1) := '3';
when o"4" => s(i+1) := '4';
when o"5" => s(i+1) := '5';
when o"6" => s(i+1) := '6';
when o"7" => s(i+1) := '7';
end case;
end loop;
write(L, s, JUSTIFIED, FIELD);
end OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := To_X01(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end HWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
HREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end HREAD;
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
HWRITE(L, To_bitvector(VALUE), JUSTIFIED, FIELD);
end HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR;GOOD:out BOOLEAN) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := To_X01(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_ULOGIC_VECTOR) is
variable tmp: bit_vector(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := To_X01(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, To_bitvector(VALUE),JUSTIFIED, FIELD);
end OWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR; GOOD: out BOOLEAN) is
variable tmp: STD_ULOGIC_VECTOR(VALUE'length-1 downto 0);
begin
OREAD(L, tmp, GOOD);
VALUE := STD_LOGIC_VECTOR(tmp);
end OREAD;
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
begin
OWRITE(L, STD_ULOGIC_VECTOR(VALUE), JUSTIFIED, FIELD);
end OWRITE;
--synopsys synthesis_on
end STD_LOGIC_TEXTIO;
|
gpl-2.0
|
e3c31bf1d37aedc3d85e8f16498d2e00
| 0.61193 | 2.849374 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/vm2413/envelopegenerator.vhd
| 2 | 7,944 |
--
-- EnvelopeGenerator.vhd
-- The envelope generator module of VM2413
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- modified by t.hara
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity EnvelopeGenerator is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
am : in std_logic;
tl : in std_logic_vector(6 downto 0);
ar : in std_logic_vector(3 downto 0);
dr : in std_logic_vector(3 downto 0);
sl : in std_logic_vector(3 downto 0);
rr : in std_logic_vector(3 downto 0);
rks : in std_logic_vector(3 downto 0);
key : in std_logic;
egout : out std_logic_vector( 12 downto 0 ) -- ¬ 6bit
);
end entity;
architecture rtl of EnvelopeGenerator is
signal rslot : std_logic_vector( 4 downto 0 );
signal memin : egdata_type;
signal memout : egdata_type;
signal memwr : std_logic;
signal aridx : std_logic_vector( 21 downto 0 );
signal ardata : std_logic_vector( 12 downto 0 ); -- ¬ 6bit
begin
-- Attack e[u
u_attack_table: entity work.AttackTable
port map (
clk => clk,
clkena => clkena,
addr => aridx,
data => ardata
);
u_envelope_memory: entity work.EnvelopeMemory
port map (
clk => clk,
reset => reset,
waddr => slot,
wr => memwr,
wdata => memin,
raddr => rslot,
rdata => memout
);
-- EnvelopeMemory ÌvtFb`
process( reset, clk )
begin
if( reset = '1' )then
rslot <= (others => '0');
elsif( clk'event and clk='1' )then
if( clkena = '1' )then
if( stage = "10" )then
if( slot = "10001" )then
rslot <= (others => '0');
else
rslot <= slot + 1;
end if;
end if;
end if;
end if;
end process;
process( reset, clk )
variable lastkey : std_logic_vector(18-1 downto 0);
variable rm : std_logic_vector(4 downto 0);
variable egtmp : std_logic_vector(6 + 8 downto 0); -- ¬ 6bit
variable amphase : std_logic_vector(19 downto 0);
variable egphase : egphase_type;
variable egstate : egstate_type;
variable dphase : egphase_type;
variable ntable : std_logic_vector(17 downto 0);
begin
if( reset = '1' )then
rm := (others=>'0');
lastkey := (others=>'0');
memwr <= '0';
egstate := Finish;
egphase := (others=>'0');
ntable := (others => '1');
amphase(amphase'high downto amphase'high-4) := "00001";
amphase(amphase'high-5 downto 0) := (others=>'0');
elsif( clk'event and clk='1' )then
aridx <= egphase( 22-1 downto 0 );
if( clkena = '1' )then
ntable( 17 downto 1 ) := ntable( 16 downto 0 );
ntable( 0 ) := ntable( 17 ) xor ntable( 14 );
-- Amplitude oscillator ( -4.8dB to 0dB , 3.7Hz )
amphase := amphase + '1';
if amphase(amphase'high downto amphase'high-4) = "11111" then
amphase(amphase'high downto amphase'high-4) := "00001";
end if;
if stage = 0 then
egstate := memout.state;
egphase := memout.phase;
elsif stage = 1 then
-- Wait for AttackTable
elsif stage = 2 then
case egstate is
when Attack =>
rm := '0'&ar;
egtmp := ("00"&tl&"000000") + ("00"&ardata); -- J[uð`¢Ä㸷é
when Decay =>
rm := '0'&dr;
egtmp := ("00"&tl&"000000") + ("00"&egphase(22-1 downto 22-7-6));
when Release=>
rm := '0'&rr;
egtmp := ("00"&tl&"000000") + ("00"&egphase(22-1 downto 22-7-6));
when Finish =>
egtmp(egtmp'high downto egtmp'high -1) := "00";
egtmp(egtmp'high-2 downto 0) := (others=>'1');
when others => null;
end case;
-- SD and HH
if ntable(0)='1' and conv_integer(slot)/2 = 7 and rhythm = '1' then
egtmp := egtmp + "010000000000000";
end if;
-- Amplitude LFO
if am ='1' then
if (amphase(amphase'high) = '0') then
-- ãèÌê
egtmp := egtmp + ("00000"&(amphase(amphase'high-1 downto amphase'high-4-6)-'1'));
else
-- ºèÌê
egtmp := egtmp + ("00000"&("1111"-amphase(amphase'high-1 downto amphase'high-4-6)));
end if;
end if;
-- Generate output
if egtmp(egtmp'high downto egtmp'high-1) = "00" then -- ~b^
egout <= egtmp(egout'range);
else
egout <= (others=>'1');
end if;
if rm /= "00000" then
rm := rm + rks(3 downto 2);
if rm(rm'high)='1' then
rm(3 downto 0):="1111";
end if;
case egstate is
when Attack =>
dphase(dphase'high downto 5) := (others=>'0');
dphase(5 downto 0) := "110" * ('1'&rks(1 downto 0));
dphase := SHL( dphase, rm(3 downto 0) );
egphase := egphase - dphase(egphase'range);
when Decay | Release =>
dphase(dphase'high downto 3) := (others=>'0');
dphase(2 downto 0) := '1'&rks(1 downto 0);
dphase := SHL(dphase, rm(3 downto 0) - '1');
egphase := egphase + dphase(egphase'range);
when Finish =>
null;
when others => null;
end case;
end if;
case egstate is
when Attack =>
if egphase(egphase'high) = '1' then
egphase := (others=>'0');
egstate := Decay;
end if;
when Decay =>
if egphase(egphase'high downto egphase'high-4) >= '0'&sl then
egstate := Release;
end if;
when Release =>
if( egphase(egphase'high downto egphase'high-4) >= "01111" ) then
egstate:= Finish;
end if;
when Finish =>
egphase := (others => '1');
when others => null;
end case;
if lastkey(conv_integer(slot)) = '0' and key = '1' then
egphase(egphase'high):= '0';
egphase(egphase'high-1 downto 0) := (others =>'1');
egstate:= Attack;
elsif lastkey(conv_integer(slot)) = '1' and key = '0' and egstate /= Finish then
egstate:= Release;
end if;
lastkey(conv_integer(slot)) := key;
-- update phase and state memory
memin <= ( state => egstate, phase => egphase );
memwr <='1';
elsif stage = 3 then
-- wait for phase memory
memwr <='0';
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
5fb9e13d02ed5e8514159d51dbc45f05
| 0.586229 | 3.221411 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-de1/pll1.vhd
| 1 | 18,312 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll1 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll1;
ARCHITECTURE SYN OF pll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
gate_lock_counter : NATURAL;
gate_lock_signal : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
invalid_lock_multiplier : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
valid_lock_multiplier : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 7,
clk0_duty_cycle => 50,
clk0_multiply_by => 3,
clk0_phase_shift => "0",
clk1_divide_by => 7,
clk1_duty_cycle => 50,
clk1_multiply_by => 12,
clk1_phase_shift => "0",
clk2_divide_by => 7,
clk2_duty_cycle => 50,
clk2_multiply_by => 12,
clk2_phase_shift => "-1458",
compensate_clock => "CLK0",
gate_lock_counter => 65536,
gate_lock_signal => "YES",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
invalid_lock_multiplier => 5,
lpm_hint => "CBX_MODULE_PREFIX=pll1",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
valid_lock_multiplier => 1
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "7"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "7"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "7"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "21.428572"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "85.714287"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "85.714287"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "65536"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "12"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "12"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "21.42857100"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-45.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "7"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1458"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "65536"
-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
6c4d27dcab22b3b24630fd9811bed41f
| 0.700743 | 3.291157 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/7a200ffg1156/mbuf_128x72.vhd
| 1 | 27,460 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.49d
-- \ \ Application: netgen
-- / / Filename: mbuf_128x72.vhd
-- /___/ /\ Timestamp: Thu Feb 21 12:33:55 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.vhd
-- Device : 7a200tffg1156-2
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/7a200tffg1156c/tmp/_cg/mbuf_128x72.vhd
-- # of Entities : 2
-- Design Name : mbuf_128x72
-- Xilinx : /opt/Xilinx/14.4/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity reset_builtin1 is
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end reset_builtin1;
architecture STRUCTURE of reset_builtin1 is
signal wr_rst_reg_2 : STD_LOGIC;
signal wr_rst_reg_GND_25_o_MUX_1_o : STD_LOGIC;
signal wr_rst_fb : STD_LOGIC_VECTOR ( 4 downto 0 );
signal power_on_wr_rst : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NlwRenamedSignal_RD_RST_I : STD_LOGIC_VECTOR ( 0 downto 0 );
signal NlwRenamedSig_OI_n0013 : STD_LOGIC_VECTOR ( 5 downto 5 );
begin
WR_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
WR_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(1) <= NlwRenamedSignal_RD_RST_I(0);
RD_RST_I(0) <= NlwRenamedSignal_RD_RST_I(0);
INT_RST_I(1) <= NlwRenamedSig_OI_n0013(5);
INT_RST_I(0) <= NlwRenamedSig_OI_n0013(5);
XST_GND : GND
port map (
G => NlwRenamedSig_OI_n0013(5)
);
power_on_wr_rst_0 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(1),
Q => power_on_wr_rst(0)
);
power_on_wr_rst_1 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(2),
Q => power_on_wr_rst(1)
);
power_on_wr_rst_2 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(3),
Q => power_on_wr_rst(2)
);
power_on_wr_rst_3 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(4),
Q => power_on_wr_rst(3)
);
power_on_wr_rst_4 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => power_on_wr_rst(5),
Q => power_on_wr_rst(4)
);
power_on_wr_rst_5 : FD
generic map(
INIT => '1'
)
port map (
C => CLK,
D => NlwRenamedSig_OI_n0013(5),
Q => power_on_wr_rst(5)
);
wr_rst_reg : FDP
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_GND_25_o_MUX_1_o,
PRE => RST,
Q => wr_rst_reg_2
);
wr_rst_fb_0 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(1),
Q => wr_rst_fb(0)
);
wr_rst_fb_1 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(2),
Q => wr_rst_fb(1)
);
wr_rst_fb_2 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(3),
Q => wr_rst_fb(2)
);
wr_rst_fb_3 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_fb(4),
Q => wr_rst_fb(3)
);
wr_rst_fb_4 : FD
generic map(
INIT => '0'
)
port map (
C => CLK,
D => wr_rst_reg_2,
Q => wr_rst_fb(4)
);
RD_RST_I_0_1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => wr_rst_reg_2,
I1 => power_on_wr_rst(0),
O => NlwRenamedSignal_RD_RST_I(0)
);
Mmux_wr_rst_reg_GND_25_o_MUX_1_o11 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => wr_rst_fb(0),
I1 => wr_rst_reg_2,
O => wr_rst_reg_GND_25_o_MUX_1_o
);
end STRUCTURE;
-- synthesis translate_on
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity mbuf_128x72 is
port (
clk : in STD_LOGIC := 'X';
rst : in STD_LOGIC := 'X';
wr_en : in STD_LOGIC := 'X';
rd_en : in STD_LOGIC := 'X';
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 71 downto 0 );
dout : out STD_LOGIC_VECTOR ( 71 downto 0 )
);
end mbuf_128x72;
architecture STRUCTURE of mbuf_128x72 is
component reset_builtin1
port (
CLK : in STD_LOGIC := 'X';
WR_CLK : in STD_LOGIC := 'X';
RD_CLK : in STD_LOGIC := 'X';
INT_CLK : in STD_LOGIC := 'X';
RST : in STD_LOGIC := 'X';
WR_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
RD_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 );
INT_RST_I : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component;
signal N1 : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19 : STD_LOGIC;
signal NlwRenamedSig_OI_empty : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED : STD_LOGIC;
signal U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
empty <= NlwRenamedSig_OI_empty;
prog_full <= U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19;
XST_GND : GND
port map (
G => N1
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt : reset_builtin1
port map (
CLK => clk,
WR_CLK => N1,
RD_CLK => N1,
INT_CLK => N1,
RST => rst,
WR_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_WR_RST_I_1_UNCONNECTED,
WR_RST_I(0) => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RD_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_1_UNCONNECTED,
RD_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_RD_RST_I_0_UNCONNECTED,
INT_RST_I(1) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_1_UNCONNECTED,
INT_RST_I(0) => NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_rstbt_INT_RST_I_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1 : FIFO36E1
generic map(
ALMOST_EMPTY_OFFSET => X"0002",
ALMOST_FULL_OFFSET => X"0180",
DATA_WIDTH => 72,
DO_REG => 0,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
EN_SYN => TRUE,
FIFO_MODE => "FIFO36_72",
FIRST_WORD_FALL_THROUGH => FALSE,
INIT => X"000000000000000000",
SIM_DEVICE => "7SERIES",
SRVAL => X"000000000000000000"
)
port map (
ALMOSTEMPTY =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ALMOSTEMPTY_UNCONNECTED
,
ALMOSTFULL => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
DBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_DBITERR_UNCONNECTED,
EMPTY => NlwRenamedSig_OI_empty,
FULL => full,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
RDCLK => clk,
RDEN => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp,
RDERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDERR_UNCONNECTED,
REGCE => N1,
RST => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
RSTREG => N1,
SBITERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_SBITERR_UNCONNECTED,
WRCLK => clk,
WREN => wr_en,
WRERR =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRERR_UNCONNECTED,
DI(63) => din(67),
DI(62) => din(66),
DI(61) => din(65),
DI(60) => din(64),
DI(59) => din(63),
DI(58) => din(62),
DI(57) => din(61),
DI(56) => din(60),
DI(55) => din(59),
DI(54) => din(58),
DI(53) => din(57),
DI(52) => din(56),
DI(51) => din(55),
DI(50) => din(54),
DI(49) => din(53),
DI(48) => din(52),
DI(47) => din(51),
DI(46) => din(50),
DI(45) => din(49),
DI(44) => din(48),
DI(43) => din(47),
DI(42) => din(46),
DI(41) => din(45),
DI(40) => din(44),
DI(39) => din(43),
DI(38) => din(42),
DI(37) => din(41),
DI(36) => din(40),
DI(35) => din(39),
DI(34) => din(38),
DI(33) => din(37),
DI(32) => din(36),
DI(31) => din(31),
DI(30) => din(30),
DI(29) => din(29),
DI(28) => din(28),
DI(27) => din(27),
DI(26) => din(26),
DI(25) => din(25),
DI(24) => din(24),
DI(23) => din(23),
DI(22) => din(22),
DI(21) => din(21),
DI(20) => din(20),
DI(19) => din(19),
DI(18) => din(18),
DI(17) => din(17),
DI(16) => din(16),
DI(15) => din(15),
DI(14) => din(14),
DI(13) => din(13),
DI(12) => din(12),
DI(11) => din(11),
DI(10) => din(10),
DI(9) => din(9),
DI(8) => din(8),
DI(7) => din(7),
DI(6) => din(6),
DI(5) => din(5),
DI(4) => din(4),
DI(3) => din(3),
DI(2) => din(2),
DI(1) => din(1),
DI(0) => din(0),
DIP(7) => din(71),
DIP(6) => din(70),
DIP(5) => din(69),
DIP(4) => din(68),
DIP(3) => din(35),
DIP(2) => din(34),
DIP(1) => din(33),
DIP(0) => din(32),
DO(63) => dout(67),
DO(62) => dout(66),
DO(61) => dout(65),
DO(60) => dout(64),
DO(59) => dout(63),
DO(58) => dout(62),
DO(57) => dout(61),
DO(56) => dout(60),
DO(55) => dout(59),
DO(54) => dout(58),
DO(53) => dout(57),
DO(52) => dout(56),
DO(51) => dout(55),
DO(50) => dout(54),
DO(49) => dout(53),
DO(48) => dout(52),
DO(47) => dout(51),
DO(46) => dout(50),
DO(45) => dout(49),
DO(44) => dout(48),
DO(43) => dout(47),
DO(42) => dout(46),
DO(41) => dout(45),
DO(40) => dout(44),
DO(39) => dout(43),
DO(38) => dout(42),
DO(37) => dout(41),
DO(36) => dout(40),
DO(35) => dout(39),
DO(34) => dout(38),
DO(33) => dout(37),
DO(32) => dout(36),
DO(31) => dout(31),
DO(30) => dout(30),
DO(29) => dout(29),
DO(28) => dout(28),
DO(27) => dout(27),
DO(26) => dout(26),
DO(25) => dout(25),
DO(24) => dout(24),
DO(23) => dout(23),
DO(22) => dout(22),
DO(21) => dout(21),
DO(20) => dout(20),
DO(19) => dout(19),
DO(18) => dout(18),
DO(17) => dout(17),
DO(16) => dout(16),
DO(15) => dout(15),
DO(14) => dout(14),
DO(13) => dout(13),
DO(12) => dout(12),
DO(11) => dout(11),
DO(10) => dout(10),
DO(9) => dout(9),
DO(8) => dout(8),
DO(7) => dout(7),
DO(6) => dout(6),
DO(5) => dout(5),
DO(4) => dout(4),
DO(3) => dout(3),
DO(2) => dout(2),
DO(1) => dout(1),
DO(0) => dout(0),
DOP(7) => dout(71),
DOP(6) => dout(70),
DOP(5) => dout(69),
DOP(4) => dout(68),
DOP(3) => dout(35),
DOP(2) => dout(34),
DOP(1) => dout(33),
DOP(0) => dout(32),
ECCPARITY(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_ECCPARITY_0_UNCONNECTED
,
RDCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_12_UNCONNECTED
,
RDCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_11_UNCONNECTED
,
RDCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_10_UNCONNECTED
,
RDCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_9_UNCONNECTED
,
RDCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_8_UNCONNECTED
,
RDCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_7_UNCONNECTED
,
RDCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_6_UNCONNECTED
,
RDCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_5_UNCONNECTED
,
RDCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_4_UNCONNECTED
,
RDCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_3_UNCONNECTED
,
RDCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_2_UNCONNECTED
,
RDCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_1_UNCONNECTED
,
RDCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_RDCOUNT_0_UNCONNECTED
,
WRCOUNT(12) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_12_UNCONNECTED
,
WRCOUNT(11) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_11_UNCONNECTED
,
WRCOUNT(10) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_10_UNCONNECTED
,
WRCOUNT(9) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_9_UNCONNECTED
,
WRCOUNT(8) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_8_UNCONNECTED
,
WRCOUNT(7) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_7_UNCONNECTED
,
WRCOUNT(6) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_6_UNCONNECTED
,
WRCOUNT(5) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_5_UNCONNECTED
,
WRCOUNT(4) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_4_UNCONNECTED
,
WRCOUNT(3) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_3_UNCONNECTED
,
WRCOUNT(2) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_2_UNCONNECTED
,
WRCOUNT(1) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_1_UNCONNECTED
,
WRCOUNT(0) =>
NLW_U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_gf36e1_inst_sngfifo36e1_WRCOUNT_0_UNCONNECTED
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q : FDC
generic map(
INIT => '0'
)
port map (
C => clk,
CLR => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_wr_rst_i(0),
D => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_fifo,
Q => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_prog_full_q_19
);
U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => NlwRenamedSig_OI_empty,
I1 => rd_en,
O => U0_xst_fifo_generator_gconvfifo_rf_gbiv5_bi_v6_fifo_fblk_gextw_1_gnll_fifo_inst_extd_gonep_inst_prim_rden_tmp
);
end STRUCTURE;
-- synthesis translate_on
|
lgpl-3.0
|
2d01ceb4f8d8dffb4f2662793dae5371
| 0.652331 | 2.61873 | false | false | false | false |
huljar/klein-vhdl
|
sim/klein80_axis_tb.vhd
| 1 | 4,734 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:37:59 02/28/2017
-- Design Name:
-- Module Name: /home/julian/Projekt/Xilinx Projects/present-vhdl/src/present_tb.vhd
-- Project Name: present-vhdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: present_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.std_logic_textio.ALL;
USE work.util.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY klein80_axis_tb IS
END klein80_axis_tb;
ARCHITECTURE behavior OF klein80_axis_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT axi_stream_wrapper
GENERIC(
k : key_enum
);
PORT(
ACLK : IN std_logic;
ARESETN : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(31 downto 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TVALID : IN std_logic;
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TDATA : OUT std_logic_vector(31 downto 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TREADY : IN std_logic
);
END COMPONENT;
--Inputs
signal ACLK : std_logic := '0';
signal ARESETN : std_logic := '0';
signal S_AXIS_TDATA : std_logic_vector(31 downto 0) := (others => '0');
signal S_AXIS_TLAST : std_logic := '0';
signal S_AXIS_TVALID : std_logic := '0';
signal M_AXIS_TREADY : std_logic := '0';
--Outputs
signal S_AXIS_TREADY : std_logic;
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(31 downto 0);
signal M_AXIS_TLAST : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
-- Other signals
signal ciphertext : std_logic_vector(63 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: axi_stream_wrapper GENERIC MAP (
k => K_80
) PORT MAP (
ACLK => ACLK,
ARESETN => ARESETN,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TREADY => M_AXIS_TREADY
);
-- Clock process definitions
clk_process: process
begin
ACLK <= '0';
wait for clk_period/2;
ACLK <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable ct: line;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- write plaintext
ARESETN <= '1';
S_AXIS_TVALID <= '1';
S_AXIS_TDATA <= (others => '1');
wait for clk_period;
assert (S_AXIS_TREADY = '1') report "ERROR: axi slave is not ready!" severity error;
wait for clk_period*2;
-- write key
S_AXIS_TDATA <= x"12345678";
wait for clk_period;
S_AXIS_TDATA <= x"90ABCDEF";
wait for clk_period;
S_AXIS_TDATA <= x"12340000";
wait for clk_period;
S_AXIS_TDATA <= (others => '0');
S_AXIS_TVALID <= '0';
wait for clk_period;
assert (S_AXIS_TREADY = '0') report "ERROR: axi slave is still ready after reading data!" severity error;
-- wait for processing
wait for clk_period*18;
assert (M_AXIS_TVALID = '1') report "ERROR: axi master is not ready in time!" severity error;
-- read ciphertext
M_AXIS_TREADY <= '1';
wait for clk_period;
ciphertext(63 downto 32) <= M_AXIS_TDATA;
wait for clk_period;
ciphertext(31 downto 0) <= M_AXIS_TDATA;
wait for clk_period;
assert (M_AXIS_TVALID = '0') report "ERROR: axi master is still valid after writing all output!" severity error;
M_AXIS_TREADY <= '0';
-- print ciphertext
hwrite(ct, ciphertext);
report "Ciphertext is " & ct.all & " (expected value: 3F210F67CB23687A)";
deallocate(ct);
wait;
end process;
END;
|
mit
|
2732a75d7b274d546bf9485090823973
| 0.591888 | 3.681182 | false | false | false | false |
hoglet67/AtomBusMon
|
src/T80/T80_MCode.vhd
| 1 | 59,483 |
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0250
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
-- 0211 : Fixed IM 1
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0235 : Added IM 2 fix by Mike Johnson
-- 0238 : Added NoRead signal
-- 0238b: Fixed instruction timing for POP and DJNZ
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
-- 0242 : Fixed I/O instruction timing, cleanup
-- 0250 : Added R800 Multiplier by TobiFlex 2017.10.15
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80_MCode is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
Rot_Akku : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
LDHLSP : out std_logic;
ADDSPdd : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
I_MULUB : out std_logic;
I_MULU : out std_logic;
SetWZ : out std_logic_vector(1 downto 0);
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
R800_mode : in std_logic;
No_PC : out std_logic;
XYbit_undoc : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if Mode = 3 then
case cc is
when "000" => return F(Flag_Z) = '0'; -- NZ
when "001" => return F(Flag_Z) = '1'; -- Z
when "010" => return F(Flag_C) = '0'; -- NC
when "011" => return F(Flag_C) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(Flag_Z) = '0'; -- NZ
when "001" => return F(Flag_Z) = '1'; -- Z
when "010" => return F(Flag_C) = '0'; -- NC
when "011" => return F(Flag_C) = '1'; -- C
when "100" => return F(Flag_P) = '0'; -- PO
when "101" => return F(Flag_P) = '1'; -- PE
when "110" => return F(Flag_S) = '0'; -- P
when "111" => return F(Flag_S) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State, R800_mode)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
Save_ALU <= '0';
Rot_Akku <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
LDHLSP <= '0';
ADDSPdd <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
I_MULUB <= '0';
I_MULU <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
No_PC <= '0';
XYbit_undoc <= '0';
SetWZ <= "00";
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
SetWZ <= "10";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
SetWZ <= "10";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
SetWZ <= "10";
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
if Mode = 3 then
MCycles <= "010";
if MCycle = "010" then
LDSPHL <= '1';
end if;
else
TStates <= "110";
LDSPHL <= '1';
end if;
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
if Mode = 3 then
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 3 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 4 =>
Write <= '1';
when others => null;
end case;
else
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if Mode = 3 then
-- RETI
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
--I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
LDW <= '1';
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
if Mode = 3 then
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "110";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
when 3 => -- GB: interrupt is acknowledged on MCycle 3
LDZ <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 4 =>
Write <= '1';
when others => null;
end case;
else
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
--TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
--TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
end if;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
if Mode = 3 then
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
SetWZ <= "11";
when 2 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
else
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
No_PC <= '1';
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
SetWZ <= "11";
No_PC <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
end if;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
if Mode = 3 then
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when others =>
end case;
else
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
end if;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
if Mode = 3 then
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
when others =>
end case;
else
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
end if;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Rot_Akku <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
if Mode = 3 then
MCycles <= "100";
else
MCycles <= "011";
end if;
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
if Mode /= 3 then
LDW <= '1';
end if;
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
IORQ <= '1'; --TH must be earlier to be stable when address is generated
when 2 =>
Write <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
IORQ <= '1'; --TH must be earlier to be stable when address is generated
when 2 =>
Read_To_Acc <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
if Mode = 3 then
MCycles <= "100";
else
MCycles <= "011";
end if;
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
if Mode /= 3 then
LDW <= '1';
end if;
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
elsif Mode = 3 then
MCycles <= "011";
end if;
when others => null;
end case;
end if;
when "00011000" =>
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
No_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
else
No_PC <= '1';
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
else
No_PC <= '1';
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
else
No_PC <= '1';
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
else
No_PC <= '1';
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if Mode = 3 then -- STOP and skip next byte
MCycles <= "010";
I_DJNZ <= '1';
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
No_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
if Mode = 3 then
MCycles <= "110";
else
MCycles <= "101";
end if;
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
if Mode = 3 then
MCycles <= "110";
else
MCycles <= "101";
end if;
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
if Mode = 3 then
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Set_Addr_TO <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 4 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
else
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
--TStates <= "101";
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 3 =>
Inc_PC <= '1';
ADDSPdd <= '1';
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Inc_PC <= '1';
when 2 =>
LDHLSP <= '1';
Inc_PC <= '1';
when 3 =>
LDHLSP <= '1';
when others => null;
end case;
end case;
else
-- RET cc
if Mode = 3 then
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "010";
end if;
TStates <= "101";
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 4 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
else
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
if Mode = 3 then
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 3 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 4 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
else
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
end if;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
when "11010011" =>
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if Mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if Mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if Mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"| "11000010" |"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"| "11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"| "11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"| "11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010" |"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01110111"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
No_PC <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
No_PC <= '1';
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
No_PC <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01111110" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
No_PC <= '1';
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
SetWZ <= "11";
No_PC <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
No_PC <= '1';
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
SetWZ <= "11";
No_PC <= '1';
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD -- Read in M2, not M3! fixed by Sorgelig
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
Save_ALU <= '1';
No_PC <= '1';
when 3 =>
TStates <= "100";
I_RLD <= '1';
NoRead <= '1';
Set_Addr_To <= aXY;
when 4 =>
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD -- Read in M2, not M3! fixed by Sorgelig
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
Save_ALU <= '1';
No_PC <= '1';
when 3 =>
TStates <= "100";
I_RRD <= '1';
NoRead <= '1';
Set_Addr_To <= aXY;
when 4 =>
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI/RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
LDW <= '1';
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
SetWZ <= "01";
when 2 =>
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
SetWZ <= "01";
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
SetWZ <= "11";
IncDec_16(3) <= IR(3);
when 2 =>
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
SetWZ <= "11";
IncDec_16(3) <= IR(3);
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "11000001"|"11001001"|"11010001"|"11011001" =>
--R800 MULUB
if R800_mode = '1' then
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
NoRead <= '1';
I_MULUB <= '1';
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
Set_BusB_To(3) <= '0';
when 2 =>
NoRead <= '1';
I_MULU <= '1';
Set_BusA_To(2 downto 0) <= "100";
when others => null;
end case;
end if;
when "11000011"|"11110011" =>
--R800 MULUW
if R800_mode = '1' then
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
NoRead <= '1';
if DPAIR = "11" then
Set_BusB_To(3 downto 0) <= "1000";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
Set_BusA_To(2 downto 0) <= "100";
when 2 =>
TStates <= "101";
NoRead <= '1';
I_MULU <= '1';
Set_BusA_To(2 downto 0) <= "100";
when others => null;
end case;
end if;
end case;
end case;
if Mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if Mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
if not (IRB = "00110110" or ISet = "01") then
No_PC <= '1';
end if;
end if;
if MCycle = "111" then
if Mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
|
gpl-3.0
|
7d7a428fab5036e6a0b88de7c9cc2169
| 0.506851 | 3.012102 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/bank_common.vhd
| 1 | 27,092 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : bank_common.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Wed Jun 17 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
-- Common block for the bank machines. Bank_common computes various
-- items that cross all of the bank machines. These values are then
-- fed back to all of the bank machines. Most of these values have
-- to do with a row machine figuring out where it belongs in a queue.
entity bank_common is
generic (
TCQ : integer := 100;
BM_CNT_WIDTH : integer := 2;
LOW_IDLE_CNT : integer := 1;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
nOP_WAIT : integer := 0;
nRFC : integer := 44;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
CWL : integer := 5;
tZQCS : integer := 64
);
port (
accept_internal_r : out std_logic;
accept_ns : out std_logic;
-- Wire to user interface informing user that the request has been accepted.
accept : out std_logic;
-- periodic_rd_insert tells everyone to mux in the periodic read.
periodic_rd_insert : out std_logic;
-- periodic_rd_ack_r acknowledges that the read has been accepted
-- into the queue.
periodic_rd_ack_r : out std_logic;
-- accept_req tells all q entries that a request has been accepted.
accept_req : out std_logic;
-- Count how many non idle bank machines hit on the rank and bank.
rb_hit_busy_cnt : out std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
-- Count the number of idle bank machines.
idle_cnt : out std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
-- Count the number of bank machines in the ordering queue.
order_cnt : out std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
adv_order_q : out std_logic;
-- Figure out which bank machine is going to accept the next request.
bank_mach_next : out std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
op_exit_grant : out std_logic_vector(nBANK_MACHS - 1 downto 0);
low_idle_cnt_r : out std_logic; -- = 1'b0;
-- In support of open page mode, the following logic
-- keeps track of how many "idle" bank machines there
-- are. In this case, idle means a bank machine is on
-- the idle list, or is in the process of precharging and
-- will soon be idle.
-- This arbiter determines which bank machine should transition
-- from open page wait to precharge. Ideally, this process
-- would take the oldest waiter, but don't have any reasonable
-- way to implement that. Instead, just use simple round robin
-- arb with the small enhancement that the most recent bank machine
-- to enter open page wait is given lowest priority in the arbiter.
-- should be one bit set at most
-- Register some command information. This information will be used
-- by the bank machines to figure out if there is something behind it
-- in the queue that require hi priority.
was_wr : out std_logic;
was_priority : out std_logic;
-- DRAM maintenance (refresh and ZQ) controller
maint_wip_r : out std_logic;
maint_idle : out std_logic;
force_io_config_rd_r : out std_logic;
-- Idle when not (maintenance work in progress (wip), OR maintenance
-- starting tick).
-- Maintenance work in progress starts with maint_reg_r tick, terminated
-- with maint_end tick. maint_end tick is generated by the RFC ZQ timer below.
-- Keep track of which bank machines hit on the maintenance request
-- when the request is made. As bank machines complete, an assertion
-- of the bm_end signal clears the correspoding bit in the
-- maint_hit_busies_r vector. Eventually, all bits should clear and
-- the maintenance operation will proceed. ZQ hits on all
-- non idle banks. Refresh hits only on non idle banks with the same rank as
-- the refresh request.
-- Look to see if io_config is in read mode.
-- Queue is clear of requests conflicting with maintenance.
-- Force io_config to read mode for ZQ. This insures the DQ
-- bus is hi Z.
-- Ready to start sending maintenance commands.
-- block: maint_controller
-- Figure out how many maintenance commands to send, and send them.
insert_maint_r : out std_logic;
clk : in std_logic;
rst : in std_logic;
idle_ns : in std_logic_vector(nBANK_MACHS - 1 downto 0);
dfi_init_complete : in std_logic;
periodic_rd_r : in std_logic;
use_addr : in std_logic;
rb_hit_busy_r : in std_logic_vector(nBANK_MACHS - 1 downto 0);
idle_r : in std_logic_vector(nBANK_MACHS - 1 downto 0);
ordered_r : in std_logic_vector(nBANK_MACHS - 1 downto 0);
ordered_issued : in std_logic_vector(nBANK_MACHS - 1 downto 0);
head_r : in std_logic_vector(nBANK_MACHS - 1 downto 0);
end_rtp : in std_logic_vector(nBANK_MACHS - 1 downto 0);
passing_open_bank : in std_logic_vector(nBANK_MACHS - 1 downto 0);
op_exit_req : in std_logic_vector(nBANK_MACHS - 1 downto 0);
start_pre_wait : in std_logic_vector(nBANK_MACHS - 1 downto 0);
cmd : in std_logic_vector(2 downto 0);
hi_priority : in std_logic;
maint_req_r : in std_logic;
maint_zq_r : in std_logic;
maint_hit : in std_logic_vector(nBANK_MACHS - 1 downto 0);
bm_end : in std_logic_vector(nBANK_MACHS - 1 downto 0);
io_config_valid_r : in std_logic;
io_config : in std_logic_vector(RANK_WIDTH downto 0);
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0)
);
end entity bank_common;
architecture trans of bank_common is
function nCOPY (A : in std_logic; B : in integer) return std_logic_vector is
variable tmp : std_logic_vector(B - 1 downto 0);
begin
for i in 0 to B - 1 loop
tmp(i) := A;
end loop;
return tmp;
end function nCOPY;
function BOOLEAN_TO_STD_LOGIC(A : in BOOLEAN) return std_logic is
begin
if A = true then
return '1';
else
return '0';
end if;
end function BOOLEAN_TO_STD_LOGIC;
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
function REDUCTION_NOR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return (not tmp);
end function REDUCTION_NOR;
function fRFC_CLKS (nCK_PER_CLK: integer; nRFC : integer )
return integer is
begin
if (nCK_PER_CLK = 1) then
return (nRFC);
else
return ( nRFC/2 + (nRFC mod 2));
end if ;
end function fRFC_CLKS;
function fZQCS_CLKS (nCK_PER_CLK: integer; tZQCS : integer )
return integer is
begin
if (nCK_PER_CLK = 1) then
return (tZQCS);
else
return ( tZQCS/2 + (tZQCS mod 2));
end if ;
end function fZQCS_CLKS ;
function clogb2(size: integer) return integer is
variable tmp : integer range 0 to 24;
begin
tmp := 0;
for i in 23 downto 0 loop
if( size <= 2** i) then
tmp := i;
end if;
end loop;
return tmp;
end function clogb2;
function fRFC_ZQ_TIMER_WIDTH (nZQCS_CLKS: integer; nRFC_CLKS : integer)
return integer is
begin
if (nZQCS_CLKS > nRFC_CLKS) then
return (clogb2(nZQCS_CLKS + 1));
else
return ( clogb2(nRFC_CLKS + 1));
end if ;
end function fRFC_ZQ_TIMER_WIDTH;
function COND_ADD ( A: std_logic_vector; B : std_logic_vector; C : std_logic; D : std_logic)
return std_logic_vector is
variable tmp : std_logic_vector (BM_CNT_WIDTH downto 0);
begin
tmp :=conv_std_logic_vector( (conv_integer (A) - conv_integer (C)),BM_CNT_WIDTH+1);
for i in 0 to nBANK_MACHS - 1 loop
tmp := conv_std_logic_vector((conv_integer(tmp) + conv_integer( B(i))),BM_CNT_WIDTH+1);
end loop;
tmp := conv_std_logic_vector((conv_integer(tmp) + conv_integer(D)),BM_CNT_WIDTH+1);
return tmp;
end function COND_ADD;
constant ZERO : integer := 0;
constant ONE : integer := 1;
constant BM_CNT_ZERO : std_logic_vector(BM_CNT_WIDTH - 1 downto 0) := (others => '0');
constant BM_CNT_ONE : std_logic_vector(BM_CNT_WIDTH - 1 downto 0) := (others => '1');
constant nRFC_CLKS : integer := fRFC_CLKS(nCK_PER_CLK ,nRFC);
constant nZQCS_CLKS : integer := fRFC_CLKS(nCK_PER_CLK ,tZQCS);
constant RFC_ZQ_TIMER_WIDTH : integer := fRFC_ZQ_TIMER_WIDTH(nZQCS_CLKS ,nRFC_CLKS );
constant THREE : integer := 3;
component round_robin_arb
generic (
TCQ : integer := 100;
WIDTH : integer := 3
);
port (
grant_ns : out std_logic_vector(WIDTH - 1 downto 0);
grant_r : out std_logic_vector(WIDTH - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
req : in std_logic_vector(WIDTH - 1 downto 0);
disable_grant : in std_logic;
current_master : in std_logic_vector(WIDTH - 1 downto 0);
upd_last_master : in std_logic
);
end component;
signal accept_internal_ns : std_logic;
signal periodic_rd_ack_ns : std_logic;
signal accept_ns_lcl : std_logic;
signal accept_r : std_logic;
signal periodic_rd_ack_r_lcl : std_logic;
signal periodic_rd_insert_lcl : std_logic;
signal accept_req_lcl : std_logic;
signal i : integer;
signal next_int1 : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal maint_wip_r_lcl : std_logic;
signal maint_idle_lcl : std_logic;
signal start_maint : std_logic;
signal maint_end : std_logic;
signal insert_maint_r_lcl : std_logic;
signal rfc_zq_timer_r :std_logic_vector(RFC_ZQ_TIMER_WIDTH - 1 downto 0);
signal rfc_zq_timer_ns :std_logic_vector(RFC_ZQ_TIMER_WIDTH - 1 downto 0);
signal maint_wip_ns : std_logic;
signal clear_vector : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal maint_zq_hits : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal maint_hit_busies_ns : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal maint_hit_busies_r : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal io_config_rd : std_logic;
signal io_config_rd_r : std_logic;
signal io_config_rd_r1 : std_logic;
signal io_config_rd_delayed : std_logic;
signal maint_clear : std_logic;
signal maint_rdy : std_logic;
signal maint_rdy_r1 : std_logic;
signal force_io_config_rd_ns : std_logic;
signal force_io_config_rd_r_lcl : std_logic;
signal send_cnt_ns : std_logic_vector(RANK_WIDTH downto 0);
signal send_cnt_r : std_logic_vector(RANK_WIDTH downto 0);
signal present_count : std_logic_vector(RANK_WIDTH downto 0);
signal present : std_logic_vector(7 downto 0);
signal insert_maint_ns : std_logic;
-- Count up how many slots are occupied. This tells
-- us how many ZQ commands to send out.
-- For refresh, there is only a single command sent. For
-- ZQ, each rank present will receive a ZQ command. The counter
-- below counts down the number of ranks present.
-- Insert a maintenance command for start_maint, or when the sent count
-- is not zero.
-- block: generate_maint_cmds
-- RFC ZQ timer. Generates delay from refresh or ZQ command until
-- the end of the maintenance operation.
-- Compute values for RFC and ZQ periods.
signal rfc_zq_timer_ns_int7 : std_logic_vector(RFC_ZQ_TIMER_WIDTH - 1 downto 0);
-- Declare intermediate signals for referenced outputs
signal rb_hit_busy_cnt_int4 : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
signal idle_cnt_int0 : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
signal order_cnt_int3 : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
signal op_exit_grant_i : std_logic_vector(nBANK_MACHS - 1 downto 0);
signal tstA : std_logic;
begin
-- Drive referenced outputs
rb_hit_busy_cnt <= rb_hit_busy_cnt_int4;
idle_cnt <= idle_cnt_int0;
order_cnt <= order_cnt_int3;
op_exit_grant <= op_exit_grant_i;
accept_internal_ns <= dfi_init_complete and REDUCTION_OR(idle_ns);
process (clk)
begin
if (clk'event and clk = '1') then
accept_internal_r <= accept_internal_ns;
end if;
end process;
accept_ns_lcl <= accept_internal_ns and not(periodic_rd_ack_ns);
accept_ns <= accept_ns_lcl;
process (clk)
begin
if (clk'event and clk = '1') then
accept_r <= accept_ns_lcl after (TCQ)*1 ps;
end if;
end process;
accept <= accept_r;
periodic_rd_insert_lcl <= periodic_rd_r and not(periodic_rd_ack_r_lcl);
periodic_rd_insert <= periodic_rd_insert_lcl;
periodic_rd_ack_ns <= periodic_rd_insert_lcl and accept_internal_ns;
process (clk)
begin
if (clk'event and clk = '1') then
periodic_rd_ack_r_lcl <= periodic_rd_ack_ns after (TCQ)*1 ps;
end if;
end process;
periodic_rd_ack_r <= periodic_rd_ack_r_lcl;
accept_req_lcl <= periodic_rd_ack_r_lcl or (accept_r and use_addr);
accept_req <= accept_req_lcl;
process (rb_hit_busy_r)
variable rb_hit_busy_r_tmp : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
begin
rb_hit_busy_r_tmp := (others => '0');
for i in 0 to nBANK_MACHS - 1 loop
if ((rb_hit_busy_r(i)) = '1') then
rb_hit_busy_r_tmp := rb_hit_busy_r_tmp + '1';
end if;
end loop;
rb_hit_busy_cnt_int4 <= rb_hit_busy_r_tmp;
end process;
process (idle_r)
variable idle_cnt_int0_tmp : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
begin
idle_cnt_int0_tmp := (others => '0');
for i in 0 to nBANK_MACHS - 1 loop
if ((idle_r(i)) = '1') then
idle_cnt_int0_tmp := idle_cnt_int0_tmp + '1';
end if;
end loop;
idle_cnt_int0 <= idle_cnt_int0_tmp;
end process;
process (ordered_r)
variable order_cnt_int3_tmp : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
begin
order_cnt_int3_tmp := (others => '0');
for i in 0 to nBANK_MACHS - 1 loop
if ((ordered_r(i)) = '1') then
order_cnt_int3_tmp := order_cnt_int3_tmp + '1';
end if;
end loop;
order_cnt_int3 <= order_cnt_int3_tmp;
end process;
adv_order_q <= REDUCTION_OR(ordered_issued);
next_int1 <= idle_r and head_r;
process (next_int1)
variable bank_mach_next_tmp : std_logic_vector(BM_CNT_WIDTH - 1 downto 0);
begin
bank_mach_next_tmp := BM_CNT_ZERO;
for i in 0 to nBANK_MACHS - 1 loop
if ((next_int1(i)) = '1') then
bank_mach_next_tmp := conv_std_logic_vector(i, BM_CNT_WIDTH);
end if;
end loop;
bank_mach_next <= bank_mach_next_tmp;
end process;
op_mode_disabled : if (nOP_WAIT = 0) generate
op_exit_grant_i <= (others => '0');
low_idle_cnt_r <= '0';
end generate;
op_mode_enabled : if (not(nOP_WAIT = 0)) generate
signal idle_cnt_r : std_logic_vector(BM_CNT_WIDTH downto 0);
signal idle_cnt_ns : std_logic_vector(BM_CNT_WIDTH downto 0);
signal low_idle_cnt_ns : std_logic;
signal upd_last_master : std_logic;
begin
process (accept_req_lcl, idle_cnt_r, passing_open_bank, rst, start_pre_wait)
begin
if (rst = '1') then
idle_cnt_ns <= conv_std_logic_vector(nBANK_MACHS, BM_CNT_WIDTH+1);
else
idle_cnt_ns <= COND_ADD (idle_cnt_r,passing_open_bank,accept_req_lcl,(REDUCTION_OR(start_pre_wait)));
--idle_cnt_ns <= idle_cnt_r - ( accept_req_lcl);
--for i in 0 to nBANK_MACHS - 1 loop
-- idle_cnt_ns <= idle_cnt_ns + ( passing_open_bank(i));
--end loop;
--idle_cnt_ns <= idle_cnt_ns + ( REDUCTION_OR(start_pre_wait));
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
idle_cnt_r <= idle_cnt_ns after (TCQ)*1 ps;
end if;
end process;
process(idle_cnt_ns)
begin
if ( conv_integer(idle_cnt_ns) <= LOW_IDLE_CNT) then
low_idle_cnt_ns <= '1';
else
low_idle_cnt_ns <= '0';
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
low_idle_cnt_r <= low_idle_cnt_ns after (TCQ)*1 ps;
end if;
end process;
upd_last_master <= REDUCTION_OR(end_rtp);
op_arb0 : round_robin_arb
generic map (
TCQ => TCQ,
WIDTH => nBANK_MACHS
)
port map (
grant_ns => op_exit_grant_i(nBANK_MACHS - 1 downto 0),
grant_r => open,
upd_last_master => upd_last_master,
current_master => end_rtp(nBANK_MACHS - 1 downto 0),
clk => clk,
rst => rst,
req => op_exit_req(nBANK_MACHS - 1 downto 0),
disable_grant => '0'
);
end generate;
process (clk)
begin
if (clk'event and clk = '1') then
was_wr <= cmd(0) and not((periodic_rd_r and not(periodic_rd_ack_r_lcl))) after (TCQ)*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
was_priority <= hi_priority after (TCQ)*1 ps;
end if;
end process;
maint_wip_r <= maint_wip_r_lcl;
maint_idle <= maint_idle_lcl;
-- ok bad
maint_idle_lcl <= not(maint_req_r or maint_wip_r_lcl);
-- ok bad ok
maint_wip_ns <= not(rst) and not(maint_end) and (maint_wip_r_lcl or maint_req_r);
process (clk)
begin
if (clk'event and clk = '1') then
maint_wip_r_lcl <= maint_wip_ns after (TCQ)*1 ps;
end if;
end process;
clear_vector <= nCOPY(rst,nBANK_MACHS) or bm_end;
--
maint_zq_hits <= nCOPY(maint_idle_lcl,nBANK_MACHS) and (maint_hit or nCOPY(maint_zq_r,nBANK_MACHS)) and not(idle_ns);
maint_hit_busies_ns <= not(clear_vector) and (maint_hit_busies_r or maint_zq_hits);
process (clk)
begin
if (clk'event and clk = '1') then
maint_hit_busies_r <= maint_hit_busies_ns after (TCQ)*1 ps;
end if;
end process;
io_config_rd <= io_config_valid_r and not(io_config(RANK_WIDTH));
--Added to fix CR #528228
--Adding extra register stages to delay the maintainence
--commands from beign applied on the dfi interface bus.
--This is done to compensate the delays added to ODT logic
--in the mem_infc module.
process (clk)
begin
if (clk'event and clk = '1') then
io_config_rd_r <= io_config_rd;
io_config_rd_r1 <= io_config_rd_r;
end if;
end process;
io_config_rd_delayed <= io_config_rd_r1 when (CWL >= 7) else io_config_rd_r;
tstA <= REDUCTION_NOR(maint_hit_busies_ns);
maint_clear <= not(maint_idle_lcl) and REDUCTION_NOR(maint_hit_busies_ns);--
force_io_config_rd_ns <= maint_clear and maint_zq_r and not(io_config_rd) and not(force_io_config_rd_r_lcl);
process (clk)
begin
if (clk'event and clk = '1') then
force_io_config_rd_r_lcl <= force_io_config_rd_ns after (TCQ)*1 ps;
end if;
end process;
force_io_config_rd_r <= force_io_config_rd_r_lcl;
-- bac
maint_rdy <= maint_clear and (not(maint_zq_r) or io_config_rd_delayed);
process (clk)
begin
if (clk'event and clk = '1') then
maint_rdy_r1 <= maint_rdy after (TCQ)*1 ps;
end if;
end process;
start_maint <= maint_rdy and not(maint_rdy_r1);
insert_maint_r <= insert_maint_r_lcl;
present <= slot_0_present or slot_1_present;
process (present)
variable present_count_tmp : std_logic_vector(RANK_WIDTH downto 0);
begin
present_count_tmp := (others => '0');
for i in 0 to 7 loop
present_count_tmp := present_count_tmp + (nCOPY('0',RANK_WIDTH) & present(i));
end loop;
present_count <= present_count_tmp;
end process;
process (maint_zq_r, present_count, rst, send_cnt_r, start_maint)
variable send_cnt_ns_tmp : std_logic_vector(RANK_WIDTH downto 0);
variable tstAA : std_logic_vector(2 downto 0);
begin
if (rst = '1') then
send_cnt_ns_tmp := (others => '0');
else
send_cnt_ns_tmp := send_cnt_r;
if (start_maint = '1' and maint_zq_r = '1') then
send_cnt_ns_tmp := present_count;
tstAA := "001";
end if;
if ((REDUCTION_OR(send_cnt_ns_tmp)) = '1') then
send_cnt_ns_tmp := send_cnt_ns_tmp - '1';
tstAA := "010";
end if;
end if;
send_cnt_ns <= send_cnt_ns_tmp;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
send_cnt_r <= send_cnt_ns after (TCQ)*1 ps;
end if;
end process;
insert_maint_ns <= start_maint or REDUCTION_OR(send_cnt_r);
process (clk)
begin
if (clk'event and clk = '1') then
insert_maint_r_lcl <= insert_maint_ns after (TCQ)*1 ps;
end if;
end process;
rfc_zq_timer_ns_int7 <= conv_std_logic_vector(nZQCS_CLKS, RFC_ZQ_TIMER_WIDTH) when (maint_zq_r = '1') else
conv_std_logic_vector(nRFC_CLKS, RFC_ZQ_TIMER_WIDTH);
rfc_zq_timer:process (insert_maint_r_lcl,rfc_zq_timer_ns_int7, maint_zq_r, rfc_zq_timer_r, rst)
variable rfc_zq_timer_ns_tmp : std_logic_vector(RFC_ZQ_TIMER_WIDTH - 1 downto 0);
begin
rfc_zq_timer_ns_tmp := rfc_zq_timer_r;
if (rst = '1') then
rfc_zq_timer_ns_tmp := (others => '0');
elsif (insert_maint_r_lcl = '1') then
rfc_zq_timer_ns_tmp := rfc_zq_timer_ns_int7;
elsif ((REDUCTION_OR(rfc_zq_timer_r)) = '1') then
rfc_zq_timer_ns_tmp := rfc_zq_timer_r - '1';
end if;
rfc_zq_timer_ns <= rfc_zq_timer_ns_tmp;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
-- Based on rfc_zq_timer_r, figure out when to release any bank
-- machines waiting to send an activate. Need to add two to the end count.
-- One because the counter starts a state after the insert_refresh_r, and
-- one more because bm_end to insert_refresh_r is one state shorter
-- than bm_end to rts_row.
rfc_zq_timer_r <= rfc_zq_timer_ns after (TCQ)*1 ps;
end if;
end process;
maint_end <= BOOLEAN_TO_STD_LOGIC((conv_integer(rfc_zq_timer_r) = 3));
-- block: rfc_zq_timer
-- bank_common
end architecture trans;
|
lgpl-3.0
|
84fbeaaaacbe663db9d0a559366c3144
| 0.577883 | 3.583598 | false | false | false | false |
fortesit/MIPS-CPU-simulator
|
processor_core.vhd
| 1 | 10,372 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity processor_core is
port (
clk : in std_logic; --clock signal
rst : in std_logic; --reset signal
run : in std_logic; --trigger the miniSPIM to run
instaddr: out std_logic_vector(31 downto 0); --Instruction memory read address
inst : in std_logic_vector(31 downto 0); --Instruction memory data
memwen : out std_logic; --Memory write enable
memaddr : out std_logic_vector(31 downto 0); --Memory address
memdw : out std_logic_vector(31 downto 0); --Memory write data
memdr : in std_logic_vector(31 downto 0); --Memory read data
fin : out std_logic; --Indicate execution finish
PCout : out std_logic_vector(31 downto 0); --PC value when finish
regaddr : in std_logic_vector(4 downto 0); --Register read address (debug use only)
regdout : out std_logic_vector(31 downto 0) --register read data (debug user only)
);
end processor_core;
architecture arch_processor_core of processor_core is
-- Add the register table here
component regtable IS
PORT (
clk : in std_logic; --clock signal
rst : in std_logic; --reset signal
raddrA : in std_logic_vector(4 downto 0); --register read address 1
raddrB : in std_logic_vector(4 downto 0); --register read address 2
wen : in std_logic; --write enable
waddr : in std_logic_vector(4 downto 0); --register write address
din : in std_logic_vector(31 downto 0); --register write data
doutA : out std_logic_vector(31 downto 0); --register read data 1
doutB : out std_logic_vector(31 downto 0); --register read data 2
extaddr : in std_logic_vector(4 downto 0); --External register read address (debug use only)
extdout : out std_logic_vector(31 downto 0) --External register read datat (debug use only)
);
end component;
-- Add signals here
signal signExtended : std_logic_vector(31 downto 0);
signal controlCode : std_logic_vector(5 downto 0);
signal writeRegAddr : std_logic_vector(4 downto 0);
signal shiftLeft2 : std_logic_vector(31 downto 0);
signal WBdata : std_logic_vector(31 downto 0);
--PC related
signal PCtemp : std_logic_vector(31 downto 0);
signal run_temp : std_logic;
signal branchResult : std_logic;
--Connected to ALU
signal registerA : std_logic_vector(31 downto 0);
signal registerB : std_logic_vector(31 downto 0);
signal aluMultiplexed : std_logic_vector(31 downto 0);
signal ALUresult : std_logic_vector(31 downto 0);
signal funct : std_logic_vector(5 downto 0);
signal ALUcontrol : std_logic_vector(2 downto 0);
signal ALUzero : std_logic;
-- control signal
signal RegDst : std_logic;
signal Jump : std_logic;
signal Branch : std_logic;
signal MemRead : std_logic;
signal MemtoReg : std_logic;
signal ALUOp : std_logic_vector(3 downto 0);
signal MemWrite : std_logic;
signal ALUSrc : std_logic;
signal RegWrite : std_logic;
signal finSignal : std_logic;
begin
-- Processor Core Behaviour
--control unit
controlCode <= inst(31 downto 26);
RegDst <= '1' when controlCode = "000000" else -- 000000 = 0
'0';
Jump <= '1' when controlCode = "000010" else -- 000010 = 2
'0';
Branch <= '1' when controlCode = "000100" else -- 000100 = 8
'0';
MemRead <= '1' when controlCode = "100011" else -- 100011 = 35
'0';
MemToReg <= '1' when controlCode = "100011" else -- 100011 = 35
'0';
ALUOp <= "0111" when controlCode = "000000" else --0111 = 7, 000000 = 0, R-type
"0010" when controlCode = "001010" else --0010 = 2, 001010 = 10, slti
"0011" when controlCode = "001011" else --0011 = 3, 001011 = 11, sltiu
"0001" when controlCode = "000100" else --0001 = 1, 000100 = 4, beq
"0110" when controlCode = "000110" else --0110 = 6, 000110 = 6, lui
"0000" ;
MemWrite <= '1' when controlCode = "101011" else -- 101011 = 43
'0';
ALUSrc <= '0' when controlCode = "000000" --000000 = 0
or controlCode = "000100" --000100 = 4
or controlCode = "000010" else --000010 = 2
'1';
RegWrite <= '0' when controlCode = "000100" --000100 = 4
or controlCode = "000010" --000010 = 2
or controlCode = "101011" else --101011 = 43
'1';
--write register multiplexer
writeRegAddr <= inst(20 downto 16) when RegDst = '0' else
inst(15 downto 11);
--sign-extend
signExtended <= X"0000" & inst(15 downto 0) when inst(15) = '0' else
X"FFFF" & inst(15 downto 0);
--shift-left 2 (before address adder)
shiftLeft2 <= signExtended(29 downto 0) & "00";
--ALU multiplexer
aluMultiplexed <= registerB when ALUSrc = '0' else
signExtended;
--ALU control
funct <= inst(5 downto 0);
ALUcontrol <= "000" when ALUOp = "0111" and funct = "100000" else --add
"001" when ALUOp = "0111" and funct = "100010" else --sub
"010" when ALUOp = "0111" and funct = "101010" else --set less signed
"011" when ALUOp = "0111" and funct = "101011" else --set less unsigned
"100" when ALUOp = "0111" and funct = "100100" else --and
"101" when ALUOp = "0111" and funct = "100101" else --or
"110" when ALUOp = "0111" and funct = "000110" else --shift left extended value 16
"111" when ALUOp = "0111" and funct = "100111" else --nor
"000" when ALUOp = "0000" else --addi
"010" when ALUOp = "0010" else --slti
"011" when ALUOp = "0011" else --sltiu
"001" when ALUOp = "0001" else --beq
"000" when ALUOp = "0000" else --lw
"000" when ALUOp = "0110" else --lui
"000" when ALUOp = "0000"; --sw
--Register
registerTable: regtable
port map (
clk => clk,
rst => rst,
raddrA => inst(25 downto 21),
raddrB => inst(20 downto 16),
wen => RegWrite,
waddr => writeRegAddr,
din => WBdata,
doutA => registerA,
doutB => registerB,
extaddr => regaddr,
extdout => regdout
);
--PC_update
branchResult <= ALUzero and Branch;
process(clk, run, rst)
begin
if run = '1' then
run_temp <= '1';
end if;
if rst = '1' then
PCtemp <= X"00004000";
elsif run_temp = '1' and clk = '1' and clk'event then
if Jump = '1' then
PCtemp <= PCtemp(31 downto 28) & inst(25 downto 0) & "00";
elsif branchResult = '1' then
PCtemp <= std_logic_vector( unsigned(PCtemp) + 4 + unsigned(shiftLeft2) );
else
PCtemp <= std_logic_vector( unsigned(PCtemp) + 4 );
end if;
end if;
end process;
--write_register
process(memdr, ALUresult)
begin
if MemToReg = '1' then
WBdata <= memdr;
else
WBdata <= ALUresult;
end if;
end process;
--Processor core output
memwen <= MemWrite;
memdw <= registerB;
--get instruction from instruction memory
instaddr <= PCtemp;
--ALU
--detect not only ALUControl as it may got cases that input changes but do the same operation
memaddr <= ALUresult;
ALUresult <= std_logic_vector(signed(registerA) + signed(aluMultiplexed))
when ALUControl = "000" else
std_logic_vector(signed(registerA) - signed(aluMultiplexed))
when ALUControl = "001" else
X"00000001"
when ALUControl = "010" and signed(registerA) < signed(aluMultiplexed) else
X"00000001"
when ALUControl = "011" and unsigned(registerA) < unsigned(aluMultiplexed) else
registerA and aluMultiplexed
when ALUControl = "100" else
registerA or aluMultiplexed
when ALUControl = "101" else
aluMultiplexed(15 downto 0) & X"0000"
when ALUControl = "110" else
not registerA
when ALUControl = "111" else
X"00000000";
ALUzero <= '1' when ALUControl = "001" and registerA = aluMultiplexed else
'0';
fin <= finSignal;
finSignal <= '1' and run_temp
when (controlCode /= "000000" and
controlCode /= "001000" and
controlCode /= "100011" and
controlCode /= "101011" and
controlCode /= "001111" and
controlCode /= "000100" and
controlCode /= "001010" and
controlCode /= "001011" and
controlCode /= "000010") or
(PCtemp(1 downto 0) /= "00") or
(ALUresult (1 downto 0) /= "00" and (MemWrite = '1' or MemtoReg = '1')) or
inst(31 downto 0) = X"00000000"
else
'0';
process (finSignal)
begin
if finSignal = '1' then
PCout <= PCtemp;
end if;
end process;
end arch_processor_core;
|
mit
|
43ac79de5735a1dd94c5c3f1599b6bd8
| 0.515619 | 4.230016 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/i2s_transmitter.vhd
| 2 | 5,831 |
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- * Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- * Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written agreement from the author.
--
-- * License is granted for non-commercial use only. A fee may not be charged
-- for redistributions as source code or in synthesized/hardware form without
-- specific prior written agreement from the author.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2s_transmitter is
generic (
mclk_rate : positive := 24576000; -- sample_rate * word_length * 2 * x || x in [2,4,8,16,32...]?
sample_rate : positive := 96000;
preamble : integer := 0; -- 0=Left-justified, 1=I2S
word_length : positive := 16
);
port (
clock_i : in std_logic; -- 2x MCLK in
reset_i : in std_logic;
-- Parallel input
pcm_l_i : in std_logic_vector(word_length - 1 downto 0);
pcm_r_i : in std_logic_vector(word_length - 1 downto 0);
i2s_mclk_o : out std_logic; -- MCLK is generated at half of the CLK input
i2s_lrclk_o : out std_logic; -- LRCLK is equal to the sample rate and is synchronous to MCLK.
i2s_bclk_o : out std_logic;
i2s_d_o : out std_logic
);
end entity;
architecture rtl of i2s_transmitter is
constant ratio_mclk_fs : positive := (mclk_rate / sample_rate); -- 24 MHz / 96KHz = 256
constant lrdivider_top : positive := ratio_mclk_fs - 1;
constant bdivider_top : positive := (ratio_mclk_fs / 4 / (preamble + word_length) * 2) - 1;
constant nbits : positive := preamble + word_length;
subtype lrdivider_t is integer range 0 to lrdivider_top;
subtype bdivider_t is integer range 0 to bdivider_top;
subtype bitcount_t is integer range 0 to nbits;
signal lrdivider : lrdivider_t;
signal bdivider : bdivider_t;
signal bitcount : bitcount_t;
signal mclk_r : std_logic;
signal lrclk_r : std_logic;
signal bclk_r : std_logic;
-- Shift register is long enough for the number of data bits
-- plus the preamble, plus an extra bit on the right to register
-- the incoming data
signal shiftreg : std_logic_vector(nbits downto 0);
begin
i2s_mclk_o <= mclk_r;
i2s_lrclk_o <= lrclk_r;
i2s_bclk_o <= bclk_r;
i2s_d_o <= shiftreg(nbits); -- data goes out MSb first
process(reset_i, clock_i)
begin
if reset_i = '1' then
-- Preload down-counters for clock generation
lrdivider <= lrdivider_top;
bdivider <= bdivider_top;
bitcount <= nbits;
mclk_r <= '0';
lrclk_r <= '0';
bclk_r <= '0';
shiftreg <= (others => '0');
elsif rising_edge(clock_i) then
-- Generate MCLK at half input clock rate
mclk_r <= not mclk_r;
-- Generate LRCLK at rate specified by codec configuration
if lrdivider = 0 then
-- LRCLK divider has reached 0 - start again from the top
lrdivider <= lrdivider_top;
-- Generate LRCLK edge and sync the BCLK counter
lrclk_r <= not lrclk_r;
bclk_r <= '0';
bitcount <= nbits; -- 1 extra required for setup
bdivider <= bdivider_top;
-- Load shift register with output data padding preamble
-- with 0s. Load output buses with input word from the
-- previous timeslot.
shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
if lrclk_r = '0' then
-- Next channel to output is RIGHT. Load this into the
-- shift register at the start of a cycle, left justified
shiftreg(word_length downto 1) <= pcm_r_i;
else
-- Next channel is LEFT
shiftreg(word_length downto 1) <= pcm_l_i;
end if;
else
-- Decrement the LRCLK counter
lrdivider <= lrdivider - 1;
-- Generate BCLK at a suitable rate to fit the required number
-- of bits into each timeslot. Data is changed on the falling edge,
-- sampled on the rising edge
if bdivider = 0 then
-- If all bits have been output for this phase then
-- stop and wait to sync back up with LRCLK
if bitcount > 0 then
-- Reset
bdivider <= bdivider_top;
-- Toggle BCLK
bclk_r <= not bclk_r;
if bclk_r = '0' then
-- Rising edge - decrement bit counter
bitcount <= bitcount - 1;
else
-- Falling edge - shift out next bit
shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
end if;
end if;
else
-- Decrement the BCLK counter
bdivider <= bdivider - 1;
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
58a820a2f5a33baec68ff1c81308b727
| 0.67587 | 3.4979 | false | false | false | false |
VectorBlox/risc-v
|
ip/orca/hdl/cache_mux.vhd
| 1 | 24,104 |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
--This OIMM Mux can be configured with or without multiple read support. If
--MAX_OUTSTANDING_READS is 1, then it is the responsibility of the requester to
--not issue a read request while a current read request is pending but the
--readdatavalid signal has not been asserted. If turned on then the
--MAX_OUTSTANDING_READS generic sets the number of outstanding reads that can
--be in flight on any one interface; all reads on one interface must finish
--before reads on another interface can start. MAX_OUTSTANDING_READS should be
--set to a power of 2 minus 1 (1,3,7,15,etc.) normally as numbers between those
--will use the same amount of resources as the next highest power of 2 minus 1.
entity cache_mux is
generic (
ADDRESS_WIDTH : positive;
DATA_WIDTH : positive;
MAX_OUTSTANDING_READS : positive;
AUX_MEMORY_REGIONS : natural range 0 to 4;
AMR0_ADDR_BASE : std_logic_vector(31 downto 0);
AMR0_ADDR_LAST : std_logic_vector(31 downto 0);
UC_MEMORY_REGIONS : natural range 0 to 4;
UMR0_ADDR_BASE : std_logic_vector(31 downto 0);
UMR0_ADDR_LAST : std_logic_vector(31 downto 0);
CACHE_SIZE : natural;
CACHE_LINE_SIZE : positive range 16 to 256;
INTERNAL_REQUEST_REGISTER : request_register_type;
INTERNAL_RETURN_REGISTER : boolean;
UC_REQUEST_REGISTER : request_register_type;
UC_RETURN_REGISTER : boolean;
AUX_REQUEST_REGISTER : request_register_type;
AUX_RETURN_REGISTER : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
amr_base_addrs : in std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
amr_last_addrs : in std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
umr_base_addrs : in std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
umr_last_addrs : in std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
internal_register_idle : out std_logic;
external_registers_idle : out std_logic;
--ORCA-internal memory-mapped slave
oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
oimm_byteenable : in std_logic_vector((DATA_WIDTH/8)-1 downto 0) := (others => '1');
oimm_requestvalid : in std_logic;
oimm_readnotwrite : in std_logic := '1';
oimm_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '-');
oimm_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_readdatavalid : out std_logic;
oimm_waitrequest : out std_logic;
--Cache interface ORCA-internal memory-mapped master
cacheint_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
cacheint_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
cacheint_oimm_requestvalid : out std_logic;
cacheint_oimm_readnotwrite : out std_logic;
cacheint_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
cacheint_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
cacheint_oimm_readdatavalid : in std_logic;
cacheint_oimm_waitrequest : in std_logic;
--Uncached ORCA-internal memory-mapped master
uc_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
uc_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
uc_oimm_requestvalid : out std_logic;
uc_oimm_readnotwrite : out std_logic;
uc_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
uc_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
uc_oimm_readdatavalid : in std_logic;
uc_oimm_waitrequest : in std_logic;
--Tightly-coupled memory ORCA-internal memory-mapped master
aux_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
aux_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
aux_oimm_requestvalid : out std_logic;
aux_oimm_readnotwrite : out std_logic;
aux_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
aux_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
aux_oimm_readdatavalid : in std_logic;
aux_oimm_waitrequest : in std_logic
);
end entity cache_mux;
architecture rtl of cache_mux is
signal internal_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal internal_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal internal_oimm_requestvalid : std_logic;
signal internal_oimm_readnotwrite : std_logic;
signal internal_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_oimm_readdatavalid : std_logic;
signal internal_oimm_waitrequest : std_logic;
signal c_outstanding_reads : unsigned(log2(MAX_OUTSTANDING_READS+1)-1 downto 0);
signal uc_outstanding_reads : unsigned(log2(MAX_OUTSTANDING_READS+1)-1 downto 0);
signal aux_outstanding_reads : unsigned(log2(MAX_OUTSTANDING_READS+1)-1 downto 0);
signal c_zero_outstanding_reads : std_logic;
signal uc_zero_outstanding_reads : std_logic;
signal aux_zero_outstanding_reads : std_logic;
signal c_max_outstanding_reads : std_logic;
signal uc_max_outstanding_reads : std_logic;
signal aux_max_outstanding_reads : std_logic;
type address_vector is array (natural range <>) of unsigned(ADDRESS_WIDTH-1 downto 0);
signal amr_base_addr : address_vector(imax(AUX_MEMORY_REGIONS, 1)-1 downto 0);
signal amr_last_addr : address_vector(imax(AUX_MEMORY_REGIONS, 1)-1 downto 0);
signal amr_address_match : std_logic_vector(imax(AUX_MEMORY_REGIONS, 1)-1 downto 0);
signal umr_base_addr : address_vector(imax(UC_MEMORY_REGIONS, 1)-1 downto 0);
signal umr_last_addr : address_vector(imax(UC_MEMORY_REGIONS, 1)-1 downto 0);
signal umr_address_match : std_logic_vector(imax(UC_MEMORY_REGIONS, 1)-1 downto 0);
signal c_select : std_logic;
signal uc_select : std_logic;
signal aux_select : std_logic;
signal read_stall : std_logic;
signal internal_uc_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal internal_uc_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal internal_uc_oimm_requestvalid : std_logic;
signal internal_uc_oimm_readnotwrite : std_logic;
signal internal_uc_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_uc_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_uc_oimm_readdatavalid : std_logic;
signal internal_uc_oimm_waitrequest : std_logic;
signal uc_register_idle : std_logic;
signal internal_aux_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal internal_aux_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal internal_aux_oimm_requestvalid : std_logic;
signal internal_aux_oimm_readnotwrite : std_logic;
signal internal_aux_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_aux_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_aux_oimm_readdatavalid : std_logic;
signal internal_aux_oimm_waitrequest : std_logic;
signal aux_register_idle : std_logic;
begin
-----------------------------------------------------------------------------
-- Optional Internal OIMM Register
-----------------------------------------------------------------------------
internal_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
REQUEST_REGISTER => INTERNAL_REQUEST_REGISTER,
RETURN_REGISTER => INTERNAL_RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => internal_register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => oimm_address,
slave_oimm_byteenable => oimm_byteenable,
slave_oimm_requestvalid => oimm_requestvalid,
slave_oimm_readnotwrite => oimm_readnotwrite,
slave_oimm_writedata => oimm_writedata,
slave_oimm_readdata => oimm_readdata,
slave_oimm_readdatavalid => oimm_readdatavalid,
slave_oimm_waitrequest => oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => internal_oimm_address,
master_oimm_byteenable => internal_oimm_byteenable,
master_oimm_requestvalid => internal_oimm_requestvalid,
master_oimm_readnotwrite => internal_oimm_readnotwrite,
master_oimm_writedata => internal_oimm_writedata,
master_oimm_readdata => internal_oimm_readdata,
master_oimm_readdatavalid => internal_oimm_readdatavalid,
master_oimm_waitrequest => internal_oimm_waitrequest
);
cacheint_oimm_address <= internal_oimm_address;
cacheint_oimm_byteenable <= internal_oimm_byteenable;
cacheint_oimm_writedata <= internal_oimm_writedata;
internal_uc_oimm_address <= internal_oimm_address;
internal_uc_oimm_byteenable <= internal_oimm_byteenable;
internal_uc_oimm_writedata <= internal_oimm_writedata;
internal_aux_oimm_address <= internal_oimm_address;
internal_aux_oimm_byteenable <= internal_oimm_byteenable;
internal_aux_oimm_writedata <= internal_oimm_writedata;
amr_gen : for gregister in imax(AUX_MEMORY_REGIONS, 1)-1 downto 0 generate
amr_base_addr(gregister) <=
unsigned(amr_base_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
amr_last_addr(gregister) <=
unsigned(amr_last_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
amr_address_match(gregister) <=
'1' when ((unsigned(internal_oimm_address) >= amr_base_addr(gregister)) and
(unsigned(internal_oimm_address) <= amr_last_addr(gregister))) else
'0';
end generate amr_gen;
umr_gen : for gregister in imax(UC_MEMORY_REGIONS, 1)-1 downto 0 generate
umr_base_addr(gregister) <=
unsigned(umr_base_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
umr_last_addr(gregister) <=
unsigned(umr_last_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
umr_address_match(gregister) <=
'1' when ((unsigned(internal_oimm_address) >= umr_base_addr(gregister)) and
(unsigned(internal_oimm_address) <= umr_last_addr(gregister))) else
'0';
end generate umr_gen;
--Generate control signals depending on which interfaces are enabled and if
--the address ranges overalp. Cache has all unspecified addresses. If AUX
--and UC overlap use AUX.
no_aux_gen : if AUX_MEMORY_REGIONS = 0 generate
aux_select <= '0';
no_uc_gen : if UC_MEMORY_REGIONS = 0 generate
uc_select <= '0';
external_registers_idle <= '1';
no_c_gen : if CACHE_SIZE = 0 generate
c_select <= '0';
internal_oimm_readdata <= (others => '-');
internal_oimm_readdatavalid <= '0';
assert true report
"Error; Cache is disabled (CACHE_SIZE = 0), UC interface is disabled (UC_MEMORY_REGIONS = 0), and AUX interface is disabled (AUX_MEMORY_REGIONS = 0). At least one interface must be enabled."
severity failure;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
c_select <= '1';
internal_oimm_readdata <= cacheint_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid;
end generate has_c_gen;
end generate no_uc_gen;
has_uc_gen : if UC_MEMORY_REGIONS /= 0 generate
external_registers_idle <= uc_register_idle;
no_c_gen : if CACHE_SIZE = 0 generate
c_select <= '0';
uc_select <= '1';
internal_oimm_readdata <= internal_uc_oimm_readdata;
internal_oimm_readdatavalid <= internal_uc_oimm_readdatavalid;
assert not ((unsigned(UMR0_ADDR_BASE) /= to_unsigned(0, UMR0_ADDR_BASE'length)) or
(signed(UMR0_ADDR_LAST) /= to_signed(-1, UMR0_ADDR_LAST'length))) report
"Warning; Cache is disabled (CACHE_SIZE = 0) and AUX interface is disabled (AUX_MEMORY_REGIONS = 0) but UMR0 address range does not encompass the full address range. All accesses will go to UC interface, even those not in the UMR0 address range."
severity note;
assert UC_MEMORY_REGIONS = 1 report
"Warning; Cache is disabled (CACHE_SIZE = 0) and AUX interface is disabled (AUX_MEMORY_REGIONS = 0) but UC_MEMORY_REGIONS is greater than 1. Multiple UC_MEMORY_REGIONS are superflous in this configuration as all accesses will use the UC memory interface."
severity note;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
uc_select <= or_slv(umr_address_match);
c_select <= and_slv(not umr_address_match);
internal_oimm_readdata <= cacheint_oimm_readdata when cacheint_oimm_readdatavalid = '1' else
internal_uc_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid or internal_uc_oimm_readdatavalid;
end generate has_c_gen;
end generate has_uc_gen;
end generate no_aux_gen;
has_aux_gen : if AUX_MEMORY_REGIONS /= 0 generate
no_uc_gen : if UC_MEMORY_REGIONS = 0 generate
uc_select <= '0';
external_registers_idle <= aux_register_idle;
no_c_gen : if CACHE_SIZE = 0 generate
aux_select <= '1';
c_select <= '0';
internal_oimm_readdata <= internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= internal_aux_oimm_readdatavalid;
assert not ((unsigned(AMR0_ADDR_BASE) /= to_unsigned(0, AMR0_ADDR_BASE'length)) or
(signed(AMR0_ADDR_LAST) /= to_signed(-1, AMR0_ADDR_LAST'length))) report
"Warning; Cache is disabled (CACHE_SIZE = 0) and UC interface is disabled (UC_MEMORY_REGIONS = 0) but AMR0 address range does not encompass the full address range. All accesses will go to AUX interface, even those not in the AMR0 address range."
severity note;
assert AUX_MEMORY_REGIONS = 1 report
"Warning; Cache is disabled (CACHE_SIZE = 0) and UC interface is disabled (UC_MEMORY_REGIONS = 0) but AUX_MEMORY_REGIONS is greater than 1. Multiple AUX_MEMORY_REGIONS are superflous in this configuration as all accesses will use the AUX memory interface."
severity note;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
aux_select <= or_slv(amr_address_match);
c_select <= and_slv(not amr_address_match);
internal_oimm_readdata <= cacheint_oimm_readdata when cacheint_oimm_readdatavalid = '1' else
internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid or internal_aux_oimm_readdatavalid;
end generate has_c_gen;
end generate no_uc_gen;
has_uc_gen : if UC_MEMORY_REGIONS /= 0 generate
aux_select <= or_slv(amr_address_match);
external_registers_idle <= uc_register_idle and aux_register_idle;
no_c_gen : if CACHE_SIZE = 0 generate
uc_select <= and_slv(not amr_address_match);
c_select <= '0';
internal_oimm_readdata <= internal_uc_oimm_readdata when internal_uc_oimm_readdatavalid = '1' else
internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= internal_uc_oimm_readdatavalid or internal_aux_oimm_readdatavalid;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
uc_select <= and_slv(not amr_address_match) and or_slv(umr_address_match);
c_select <= and_slv(not amr_address_match) and and_slv(not umr_address_match);
internal_oimm_readdata <= cacheint_oimm_readdata when cacheint_oimm_readdatavalid = '1' else
internal_uc_oimm_readdata when internal_uc_oimm_readdatavalid = '1' else
internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid or
internal_uc_oimm_readdatavalid or
internal_aux_oimm_readdatavalid;
end generate has_c_gen;
end generate has_uc_gen;
end generate has_aux_gen;
read_stall <=
((c_select and (c_max_outstanding_reads or (not uc_zero_outstanding_reads) or (not aux_zero_outstanding_reads))) or
(uc_select and (uc_max_outstanding_reads or (not c_zero_outstanding_reads) or (not aux_zero_outstanding_reads))) or
(aux_select and (aux_max_outstanding_reads or (not c_zero_outstanding_reads) or (not uc_zero_outstanding_reads))))
when MAX_OUTSTANDING_READS > 1 else
'0';
internal_oimm_waitrequest <= read_stall or
((cacheint_oimm_waitrequest and c_select) or
(internal_uc_oimm_waitrequest and uc_select) or
(internal_aux_oimm_waitrequest and aux_select));
cacheint_oimm_requestvalid <= internal_oimm_requestvalid and (not read_stall) and c_select;
cacheint_oimm_readnotwrite <= internal_oimm_readnotwrite;
internal_uc_oimm_requestvalid <= internal_oimm_requestvalid and (not read_stall) and uc_select;
internal_uc_oimm_readnotwrite <= internal_oimm_readnotwrite;
internal_aux_oimm_requestvalid <= internal_oimm_requestvalid and (not read_stall) and aux_select;
internal_aux_oimm_readnotwrite <= internal_oimm_readnotwrite;
--Note that we could include the updated read count when
--internal_oimm_readdatavalid is '1' but as long as more than one read is
--supported we can get full throughput with MAX_OUTSTANDING_READS-1 in
--flight.
c_zero_outstanding_reads <= '1' when c_outstanding_reads = to_unsigned(0, c_outstanding_reads'length) else '0';
c_max_outstanding_reads <=
'1' when c_outstanding_reads = to_unsigned(MAX_OUTSTANDING_READS, c_outstanding_reads'length) else '0';
uc_zero_outstanding_reads <= '1' when uc_outstanding_reads = to_unsigned(0, uc_outstanding_reads'length) else '0';
uc_max_outstanding_reads <=
'1' when uc_outstanding_reads = to_unsigned(MAX_OUTSTANDING_READS, uc_outstanding_reads'length) else '0';
aux_zero_outstanding_reads <= '1' when aux_outstanding_reads = to_unsigned(0, aux_outstanding_reads'length) else '0';
aux_max_outstanding_reads <=
'1' when aux_outstanding_reads = to_unsigned(MAX_OUTSTANDING_READS, aux_outstanding_reads'length) else '0';
process(clk)
begin
if rising_edge(clk) then
if internal_oimm_readdatavalid = '1' then
--Subtract one unless a new request has been issued
if (internal_oimm_requestvalid = '0' or
internal_oimm_readnotwrite = '0' or
internal_oimm_waitrequest = '1') then
if c_outstanding_reads /= to_unsigned(0, c_outstanding_reads'length) then
c_outstanding_reads <= c_outstanding_reads - to_unsigned(1, c_outstanding_reads'length);
end if;
if uc_outstanding_reads /= to_unsigned(0, uc_outstanding_reads'length) then
uc_outstanding_reads <= uc_outstanding_reads - to_unsigned(1, uc_outstanding_reads'length);
end if;
if aux_outstanding_reads /= to_unsigned(0, aux_outstanding_reads'length) then
aux_outstanding_reads <= aux_outstanding_reads - to_unsigned(1, aux_outstanding_reads'length);
end if;
end if;
else
if (internal_oimm_requestvalid = '1' and
internal_oimm_readnotwrite = '1' and
internal_oimm_waitrequest = '0') then
if c_select = '1' then
c_outstanding_reads <= c_outstanding_reads + to_unsigned(1, c_outstanding_reads'length);
end if;
if uc_select = '1' then
uc_outstanding_reads <= uc_outstanding_reads + to_unsigned(1, uc_outstanding_reads'length);
end if;
if aux_select = '1' then
aux_outstanding_reads <= aux_outstanding_reads + to_unsigned(1, aux_outstanding_reads'length);
end if;
end if;
end if;
if reset = '1' then
c_outstanding_reads <= to_unsigned(0, c_outstanding_reads'length);
uc_outstanding_reads <= to_unsigned(0, uc_outstanding_reads'length);
aux_outstanding_reads <= to_unsigned(0, aux_outstanding_reads'length);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Optional UC OIMM Register
-----------------------------------------------------------------------------
uc_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
REQUEST_REGISTER => UC_REQUEST_REGISTER,
RETURN_REGISTER => UC_RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => uc_register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => internal_uc_oimm_address,
slave_oimm_byteenable => internal_uc_oimm_byteenable,
slave_oimm_requestvalid => internal_uc_oimm_requestvalid,
slave_oimm_readnotwrite => internal_uc_oimm_readnotwrite,
slave_oimm_writedata => internal_uc_oimm_writedata,
slave_oimm_readdata => internal_uc_oimm_readdata,
slave_oimm_readdatavalid => internal_uc_oimm_readdatavalid,
slave_oimm_waitrequest => internal_uc_oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => uc_oimm_address,
master_oimm_byteenable => uc_oimm_byteenable,
master_oimm_requestvalid => uc_oimm_requestvalid,
master_oimm_readnotwrite => uc_oimm_readnotwrite,
master_oimm_writedata => uc_oimm_writedata,
master_oimm_readdata => uc_oimm_readdata,
master_oimm_readdatavalid => uc_oimm_readdatavalid,
master_oimm_waitrequest => uc_oimm_waitrequest
);
-----------------------------------------------------------------------------
-- Optional AUX OIMM Register
-----------------------------------------------------------------------------
aux_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
REQUEST_REGISTER => AUX_REQUEST_REGISTER,
RETURN_REGISTER => AUX_RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => aux_register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => internal_aux_oimm_address,
slave_oimm_byteenable => internal_aux_oimm_byteenable,
slave_oimm_requestvalid => internal_aux_oimm_requestvalid,
slave_oimm_readnotwrite => internal_aux_oimm_readnotwrite,
slave_oimm_writedata => internal_aux_oimm_writedata,
slave_oimm_readdata => internal_aux_oimm_readdata,
slave_oimm_readdatavalid => internal_aux_oimm_readdatavalid,
slave_oimm_waitrequest => internal_aux_oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => aux_oimm_address,
master_oimm_byteenable => aux_oimm_byteenable,
master_oimm_requestvalid => aux_oimm_requestvalid,
master_oimm_readnotwrite => aux_oimm_readnotwrite,
master_oimm_writedata => aux_oimm_writedata,
master_oimm_readdata => aux_oimm_readdata,
master_oimm_readdatavalid => aux_oimm_readdatavalid,
master_oimm_waitrequest => aux_oimm_waitrequest
);
end architecture;
|
bsd-3-clause
|
adf777396ca7688b9ef125005b1fca94
| 0.648274 | 3.873373 | false | false | false | false |
z3774/sparcv8-monocycle
|
WM.vhd
| 1 | 3,624 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:10:56 10/28/2012
-- Design Name:
-- Module Name: WM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity WM is
Port (
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwp : in STD_LOGIC_VECTOR (1 downto 0);
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
ncwp : out STD_LOGIC_VECTOR (1 downto 0);
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
nrd : out STD_LOGIC_VECTOR (5 downto 0);
r7 : out STD_LOGIC_VECTOR(5 downto 0)
);
end WM;
architecture Behavioral of WM is
signal rs1Integer, rs2Integer, rdInteger: integer range 0 to 39;
signal auxR7 : std_logic_vector(6 downto 0);
signal cwpi : std_logic_vector(1 downto 0);
begin
auxR7 <= cwp * "10000";--OJO en lugar de "00" debe ir cwp
r7 <= auxR7(5 downto 0) + "001111";
process(rs1,rs2,rd,cwp,cwpi,op,op3)--,clk)
begin
--if(rising_edge(clk)) then
--SAVE --RESTORE
if( (op3 = "111100" or op3 = "111101") and op = "10") then
if(cwp = "00") then
cwpi <= "01";
ncwp <= "01";
elsif(cwp = "01") then
cwpi <= "00";
ncwp <= "00";
end if;
else
cwpi <= cwp;
ncwp <= cwp;
end if;
if(rd>="00000" and rd<="00111") then
--globals
rdInteger <= conv_integer(rd);
elsif(rd>="01000" and rd<="01111") then
--outputs
rdInteger <= conv_integer(rd) + (conv_integer(cwpi)*16);
elsif(rd>="10000" and rd<="10111") then
--locals
rdInteger <= conv_integer(rd) + (conv_integer(cwpi)*16);
elsif(rd>="11000" and rd<="11111") then
--inputs
rdInteger <= conv_integer(rd) - (conv_integer(cwpi)*16);
end if;
if(rs1>="00000" and rs1<="00111") then
--globals
rs1Integer <= conv_integer(rs1);
elsif(rs1>="01000" and rs1<="01111") then
--outputs
rs1Integer <= conv_integer(rs1) + (conv_integer(cwp)*16);
elsif(rs1>="10000" and rs1<="10111") then
--locals
rs1Integer <= conv_integer(rs1) + (conv_integer(cwp)*16);
elsif(rs1>="11000" and rs1<="11111") then
--inputs
rs1Integer <= conv_integer(rs1) - (conv_integer(cwp)*16);
end if;
if(rs2>="00000" and rs2<="00111") then
--globals
rs2Integer <= conv_integer(rs2);
elsif(rs2>="01000" and rs2<="01111") then
--outputs
rs2Integer <= conv_integer(rs2) + (conv_integer(cwp)*16);
elsif(rs2>="10000" and rs2<="10111") then
--locals
rs2Integer <= conv_integer(rs2) + (conv_integer(cwp)*16);
elsif(rs2>="11000" and rs2<="11111") then
--inputs
rs2Integer <= conv_integer(rs2) - (conv_integer(cwp)*16);
end if;
--end if;
end process;
nrs1 <= conv_std_logic_vector(rs1Integer, 6);
nrs2 <= conv_std_logic_vector(rs2Integer, 6);
nrd <= conv_std_logic_vector(rdInteger, 6);
end Behavioral;
|
gpl-3.0
|
4c33e27a604c43b10bdb9bc2a3ea3708
| 0.595199 | 2.910843 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_data_io.vhd
| 1 | 26,259 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_data_io.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Top-level for all data (DQ, DQS, DM) related IOB logic.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_data_io.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_data_io.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_data_io is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCK_PER_CLK : integer := 2; -- # of memory clocks per CLK
CLK_PERIOD : integer := 3000; -- Internal clock period (in ps)
DRAM_WIDTH : integer := 8; -- # of DQ per DQS
DM_WIDTH : integer := 9; -- # of DM (data mask)
DQ_WIDTH : integer := 72; -- # of DQ (data)
DQS_WIDTH : integer := 9; -- # of DQS (strobe)
DRAM_TYPE : string := "DDR3";
nCWL : integer := 5; -- Write CAS latency (in clk cyc)
WRLVL : string := "OFF"; -- Enable write leveling
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG"; -- May be assigned unique name
-- when mult IP cores in design
nDQS_COL0 : integer := 4; -- # DQS groups in I/O column #1
nDQS_COL1 : integer := 4; -- # DQS groups in I/O column #2
nDQS_COL2 : integer := 0; -- # DQS groups in I/O column #3
nDQS_COL3 : integer := 0; -- # DQS groups in I/O column #4
DQS_LOC_COL0 : std_logic_vector(143 downto 0) := X"000000000000000000000000000003020100";-- DQS grps in col #1
DQS_LOC_COL1 : std_logic_vector(143 downto 0) := X"000000000000000000000000000007060504";-- DQS grps in col #2
DQS_LOC_COL2 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";-- DQS grps in col #3
DQS_LOC_COL3 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";-- DQS grps in col #4
USE_DM_PORT : integer := 1 -- DM instantation enable
);
port (
clk_mem : in std_logic;
clk : in std_logic;
clk_cpt : in std_logic_vector(DQS_WIDTH - 1 downto 0);
clk_rsync : in std_logic_vector(3 downto 0);
rst : in std_logic;
rst_rsync : in std_logic_vector(3 downto 0);
-- IODELAY I/F
dlyval_dq : in std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dlyval_dqs : in std_logic_vector(5*DQS_WIDTH - 1 downto 0);
-- Write datapath I/F
inv_dqs : in std_logic_vector(DQS_WIDTH - 1 downto 0);
wr_calib_dly : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
dqs_oe_n : in std_logic_vector(4*DQS_WIDTH - 1 downto 0);
dq_oe_n : in std_logic_vector(4*DQS_WIDTH - 1 downto 0);
dqs_rst : in std_logic_vector((DQS_WIDTH * 4) - 1 downto 0);
dm_ce : in std_logic_vector(DQS_WIDTH - 1 downto 0);
mask_data_rise0 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_fall0 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_rise1 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
mask_data_fall1 : in std_logic_vector((DQ_WIDTH / 8) - 1 downto 0);
wr_data_rise0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_rise1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_fall0 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
wr_data_fall1 : in std_logic_vector(DQ_WIDTH - 1 downto 0);
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdly_cnt : in std_logic_vector(2*DQS_WIDTH - 1 downto 0);
rd_clkdiv_inv : in std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_data_rise0 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall0 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_rise1 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_data_fall1 : out std_logic_vector(DQ_WIDTH - 1 downto 0);
rd_dqs_rise0 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall0 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_rise1 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
rd_dqs_fall1 : out std_logic_vector(DQS_WIDTH - 1 downto 0);
-- DDR3 bus signals
ddr_dm : out std_logic_vector(DM_WIDTH - 1 downto 0);
ddr_dqs_p : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dqs_n : inout std_logic_vector(DQS_WIDTH - 1 downto 0);
ddr_dq : inout std_logic_vector(DQ_WIDTH - 1 downto 0);
-- Debug Port
dbg_dqs_tap_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0);
dbg_dq_tap_cnt : out std_logic_vector(5*DQS_WIDTH - 1 downto 0)
);
end phy_data_io;
architecture trans of phy_data_io is
-- ratio of # of physical DM outputs to bytes in data bus
-- may be different - e.g. if using x4 components
constant DM_TO_BYTE_RATIO : integer := DM_WIDTH / (DQ_WIDTH / 8);
signal clk_rsync_dqs : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal dq_tap_cnt : std_logic_vector(5*DQ_WIDTH - 1 downto 0);
signal rst_r : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rst_rsync_dqs : std_logic_vector(DQS_WIDTH - 1 downto 0);
signal rst_dqs_r : std_logic_vector(DQS_WIDTH-1 downto 0);
signal rst_dm_r : std_logic_vector(DM_WIDTH-1 downto 0);
signal rst_dq_r : std_logic_vector(DQ_WIDTH-1 downto 0);
------- phy_dqs_iob component --------
component phy_dqs_iob
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic; -- memory-rate clock
clk : in std_logic; -- internal (logic) clock
clk_cpt : in std_logic; -- read capture clock
clk_rsync : in std_logic; -- resynchronization (read) clock
rst : in std_logic; -- reset sync'ed to CLK
rst_rsync : in std_logic; -- reset sync'ed to RSYNC
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0); -- IODELAY (DQS) parallel load value
-- Write datapath I/F
dqs_oe_n : in std_logic_vector(3 downto 0); -- DQS output enable
dqs_rst : in std_logic_vector(3 downto 0); -- D4 input of OSERDES: 1- for normal, 0- for WL
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(1 downto 0);
rd_clkdly_cnt : in std_logic_vector(1 downto 0);
rd_clkdiv_inv : in std_logic;
rd_dqs_rise0 : out std_logic; -- DQS captured in clk_cpt domain
rd_dqs_fall0 : out std_logic; -- used by Phase Detector. Monitor DQS
rd_dqs_rise1 : out std_logic;
rd_dqs_fall1 : out std_logic;
-- DDR3 bus signals
ddr_dqs_p : inout std_logic;
ddr_dqs_n : inout std_logic;
-- Debug Port
dqs_tap_cnt : out std_logic_vector(4 downto 0)
);
end component;
------- phy_dq_iob component --------
component phy_dq_iob
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCWL : integer := 5; -- Write CAS latency (in clk cyc)
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
WRLVL : string := "ON"; -- "OFF" for "DDR3" component interface
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic;
clk : in std_logic;
rst : in std_logic;
clk_cpt : in std_logic;
clk_rsync : in std_logic;
rst_rsync : in std_logic;
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0);
-- Write datapath I/F
inv_dqs : in std_logic;
wr_calib_dly : in std_logic_vector(1 downto 0);
dq_oe_n : in std_logic_vector(3 downto 0);
wr_data_rise0 : in std_logic;
wr_data_fall0 : in std_logic;
wr_data_rise1 : in std_logic;
wr_data_fall1 : in std_logic;
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(1 downto 0);
rd_clkdly_cnt : in std_logic_vector(1 downto 0);
rd_clkdiv_inv : in std_logic;
rd_data_rise0 : out std_logic;
rd_data_fall0 : out std_logic;
rd_data_rise1 : out std_logic;
rd_data_fall1 : out std_logic;
-- DDR3 bus signals
ddr_dq : inout std_logic;
dq_tap_cnt : out std_logic_vector(4 downto 0)
);
end component;
------- phy_dm_iob component --------
component phy_dm_iob
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCWL : integer := 5; -- CAS Write Latency
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
WRLVL : string := "ON"; -- "OFF" for "DDR3" component interface
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic;
clk : in std_logic;
clk_rsync : in std_logic;
rst : in std_logic;
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0);
dm_ce : in std_logic;
inv_dqs : in std_logic;
wr_calib_dly : in std_logic_vector(1 downto 0);
mask_data_rise0 : in std_logic;
mask_data_fall0 : in std_logic;
mask_data_rise1 : in std_logic;
mask_data_fall1 : in std_logic;
ddr_dm : out std_logic
);
end component;
attribute max_fanout: string;
attribute max_fanout of rst_dqs_r : signal is "1";
attribute max_fanout of rst_dm_r : signal is "1";
attribute max_fanout of rst_dq_r : signal is "1";
attribute shreg_extract: string;
attribute shreg_extract of rst_dqs_r : signal is "no";
attribute shreg_extract of rst_dm_r : signal is "no";
attribute shreg_extract of rst_dq_r : signal is "no";
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of rst_dqs_r : signal is "no";
attribute equivalent_register_removal of rst_dm_r : signal is "no";
attribute equivalent_register_removal of rst_dq_r : signal is "no";
attribute syn_maxfan : integer;
attribute syn_maxfan of rst_dqs_r : signal is 1;
attribute syn_maxfan of rst_dm_r : signal is 1;
attribute syn_maxfan of rst_dq_r : signal is 1;
attribute syn_srlstyle : string;
attribute syn_srlstyle of rst_dqs_r : signal is "noextractff_srl";
attribute syn_srlstyle of rst_dm_r : signal is "noextractff_srl";
attribute syn_srlstyle of rst_dq_r : signal is "noextractff_srl";
attribute syn_preserve : boolean;
attribute syn_preserve of rst_dqs_r : signal is true;
attribute syn_preserve of rst_dm_r : signal is true;
attribute syn_preserve of rst_dq_r : signal is true;
begin
-- XST attributes for local reset tree RST_R - prohibit equivalent
-- register removal on RST_R to prevent "sharing" w/ other local reset trees
-- synthesis attribute shreg_extract of rst_r is "no";
-- synthesis attribute equivalent_register_removal of rst_r is "no"
--
--***************************************************************************
-- Steer correct CLK_RSYNC to each DQS/DQ/DM group - different DQS groups
-- can reside on different I/O columns - each I/O column will have its
-- own CLK_RSYNC
-- Also steer correct performance path clock to each DQS/DQ/DM group -
-- different DQS groups can reside on different I/O columns - inner I/O
-- column I/Os will use clk_wr_i, other column I/O's will use clk_wr_o
-- By convention, inner columns use DQS_COL0 and DQS_COL1, and outer
-- columns use DQS_COL2 and DQS_COL3.
--***************************************************************************
gen_c0 : if (nDQS_COL0 > 0) generate
gen_loop_c0 : for c0_i in 0 to nDQS_COL0 - 1 generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) <= clk_rsync(0);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL0(8*c0_i+7 downto 8*c0_i)))) <= rst_rsync(0);
end generate;
end generate;
gen_c1 : if (nDQS_COL1 > 0) generate
gen_loop_c1 : for c1_i in 0 to (nDQS_COL1 - 1) generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) <= clk_rsync(1);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL1(8*c1_i+7 downto 8*c1_i)))) <= rst_rsync(1);
end generate;
end generate;
gen_c2 : if (nDQS_COL2 > 0) generate
gen_loop_c2 : for c2_i in 0 to (nDQS_COL2 - 1) generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) <= clk_rsync(2);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL2(8*c2_i+7 downto 8*c2_i)))) <= rst_rsync(2);
end generate;
end generate;
gen_c3 : if (nDQS_COL3 > 0) generate
gen_loop_c3 : for c3_i in 0 to nDQS_COL3 - 1 generate
clk_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) <= clk_rsync(3);
rst_rsync_dqs(TO_INTEGER(unsigned(DQS_LOC_COL3(8*c3_i+7 downto 8*c3_i)))) <= rst_rsync(3);
end generate;
end generate;
--***************************************************************************
-- Reset pipelining - register reset signals to prevent large (and long)
-- fanouts during physical compilation of the design. Create one local reset
-- for every byte's worth of DQ/DM/DQS (this should be local since DQ/DM/DQS
-- are placed close together)
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_r <= (others => '1') after (TCQ)*1 ps;
else
rst_r <= (others => '0') after (TCQ)*1 ps;
end if;
end if;
end process;
--***************************************************************************
-- DQS instances
--***************************************************************************
gen_dqs : for dqs_i in 0 to DQS_WIDTH - 1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_dqs_r(dqs_i) <= '1' after (TCQ)*1 ps;
else
rst_dqs_r(dqs_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
u_phy_dqs_iob : phy_dqs_iob
generic map (
DRAM_TYPE => (DRAM_TYPE),
REFCLK_FREQ => (REFCLK_FREQ),
IBUF_LPWR_MODE => (IBUF_LPWR_MODE),
IODELAY_HP_MODE => (IODELAY_HP_MODE),
IODELAY_GRP => (IODELAY_GRP)
)
port map (
clk_mem => clk_mem,
clk => clk,
clk_cpt => clk_cpt(dqs_i),
clk_rsync => clk_rsync_dqs(dqs_i),
rst => rst_dqs_r(dqs_i),
rst_rsync => rst_rsync_dqs(dqs_i),
dlyval => dlyval_dqs(5*dqs_i+4 downto 5*dqs_i),
dqs_oe_n => dqs_oe_n(4*dqs_i+3 downto 4*dqs_i),
dqs_rst => dqs_rst(4*dqs_i+3 downto 4*dqs_i),
rd_bitslip_cnt => rd_bitslip_cnt(2*dqs_i+1 downto 2*dqs_i),
rd_clkdly_cnt => rd_clkdly_cnt(2*dqs_i+1 downto 2*dqs_i),
rd_clkdiv_inv => rd_clkdiv_inv(dqs_i),
rd_dqs_rise0 => rd_dqs_rise0(dqs_i),
rd_dqs_fall0 => rd_dqs_fall0(dqs_i),
rd_dqs_rise1 => rd_dqs_rise1(dqs_i),
rd_dqs_fall1 => rd_dqs_fall1(dqs_i),
ddr_dqs_p => ddr_dqs_p(dqs_i),
ddr_dqs_n => ddr_dqs_n(dqs_i),
dqs_tap_cnt => dbg_dqs_tap_cnt(5*dqs_i+4 downto 5*dqs_i)
);
end generate;
--***************************************************************************
-- DM instances
--***************************************************************************
gen_dm_inst: if (USE_DM_PORT /= 0) generate
gen_dm : for dm_i in 0 to DM_WIDTH - 1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_dm_r(dm_i) <= '1' after (TCQ)*1 ps;
else
rst_dm_r(dm_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
u_phy_dm_iob : phy_dm_iob
generic map (
TCQ => (TCQ),
nCWL => (nCWL),
DRAM_TYPE => (DRAM_TYPE),
WRLVL => (WRLVL),
REFCLK_FREQ => (REFCLK_FREQ),
IODELAY_HP_MODE => (IODELAY_HP_MODE),
IODELAY_GRP => (IODELAY_GRP)
)
port map (
clk_mem => clk_mem,
clk => clk,
clk_rsync => clk_rsync_dqs(dm_i),
rst => rst_dm_r(dm_i),
dlyval => dlyval_dq(5*dm_i+4 downto 5*dm_i),
dm_ce => dm_ce(dm_i),
inv_dqs => inv_dqs(dm_i),
wr_calib_dly => wr_calib_dly(2*dm_i+1 downto 2*dm_i),
mask_data_rise0 => mask_data_rise0(dm_i / DM_TO_BYTE_RATIO),
mask_data_fall0 => mask_data_fall0(dm_i / DM_TO_BYTE_RATIO),
mask_data_rise1 => mask_data_rise1(dm_i / DM_TO_BYTE_RATIO),
mask_data_fall1 => mask_data_fall1(dm_i / DM_TO_BYTE_RATIO),
ddr_dm => ddr_dm(dm_i)
);
end generate;
end generate;
--***************************************************************************
-- DQ IOB instances
--***************************************************************************
gen_dq : for dq_i in 0 to DQ_WIDTH - 1 generate
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
rst_dq_r(dq_i) <= '1' after (TCQ)*1 ps;
else
rst_dq_r(dq_i) <= '0' after (TCQ)*1 ps;
end if;
end if;
end process;
u_iob_dq : phy_dq_iob
generic map (
tcq => (TCQ),
ncwl => (nCWL),
dram_type => (DRAM_TYPE),
wrlvl => (WRLVL),
refclk_freq => (REFCLK_FREQ),
ibuf_lpwr_mode => (IBUF_LPWR_MODE),
iodelay_hp_mode => (IODELAY_HP_MODE),
iodelay_grp => (IODELAY_GRP)
)
port map (
clk_mem => clk_mem,
clk => clk,
rst => rst_dq_r(dq_i),
clk_cpt => clk_cpt(dq_i / DRAM_WIDTH),
clk_rsync => clk_rsync_dqs(dq_i / DRAM_WIDTH),
rst_rsync => rst_rsync_dqs(dq_i / DRAM_WIDTH),
dlyval => dlyval_dq(5 * (dq_i / DRAM_WIDTH) + 4 downto 5 * (dq_i / DRAM_WIDTH)),
inv_dqs => inv_dqs(dq_i / DRAM_WIDTH),
wr_calib_dly => wr_calib_dly(2 * (dq_i / DRAM_WIDTH) + 1 downto 2 * (dq_i / DRAM_WIDTH)),
dq_oe_n => dq_oe_n(4 * (dq_i / DRAM_WIDTH) + 3 downto 4 * (dq_i / DRAM_WIDTH)),
wr_data_rise0 => wr_data_rise0(dq_i),
wr_data_fall0 => wr_data_fall0(dq_i),
wr_data_rise1 => wr_data_rise1(dq_i),
wr_data_fall1 => wr_data_fall1(dq_i),
rd_bitslip_cnt => rd_bitslip_cnt(2 * (dq_i / DRAM_WIDTH) + 1 downto 2 * (dq_i / DRAM_WIDTH)),
rd_clkdly_cnt => rd_clkdly_cnt(2 * (dq_i / DRAM_WIDTH) + 1 downto 2 * (dq_i / DRAM_WIDTH)),
rd_clkdiv_inv => rd_clkdiv_inv(dq_i / DRAM_WIDTH),
rd_data_rise0 => rd_data_rise0(dq_i),
rd_data_fall0 => rd_data_fall0(dq_i),
rd_data_rise1 => rd_data_rise1(dq_i),
rd_data_fall1 => rd_data_fall1(dq_i),
ddr_dq => ddr_dq(dq_i),
dq_tap_cnt => dq_tap_cnt(5*dq_i+4 downto 5*dq_i)
);
end generate;
-- Only use one DQ IODELAY tap per DQS group, since all DQs in the same
-- DQS group have the same delay value (because calibration for both write
-- and read timing is done on a per-DQS group basis, not a per-bit basis)
gen_dbg: for dbg_i in 0 to (DQS_WIDTH - 1) generate
dbg_dq_tap_cnt(5*dbg_i+4 downto 5*dbg_i) <= dq_tap_cnt (5*DRAM_WIDTH*dbg_i + 4 downto 5*DRAM_WIDTH*dbg_i);
end generate;
end trans;
|
lgpl-3.0
|
438070962de9c8230543beee8e3cc3de
| 0.507635 | 3.64253 | false | false | false | false |
rodrigosurita/new-crpuf
|
vhdl/src/simulate.vhd
| 1 | 10,543 |
-- TODO
-- Define stability as global parameter
-- Joint For generate
library IEEE;
use IEEE.std_logic_1164.all;
use STD.textio.all;
use work.std_logic_textio.all;
use work.txt_util.all;
use work.resources.all;
use work.std_logic_arith.CONV_STD_LOGIC_VECTOR;
entity simulate is
end simulate;
architecture simulate_arch of simulate is
signal a: std_logic := '1';
signal c: std_logic ;
signal b: std_logic ;
signal input_data: std_logic_vector (1 to 2*matriz_i) ;
signal output_result: std_logic_vector (1 to matriz_i) ;
TYPE time_vector IS ARRAY (1 to 2* matriz_i * (matriz_j)) OF integer;
TYPE wire IS ARRAY ( 1 to matriz_i, 1 to matriz_j) OF std_logic;
signal x_wire: wire ;
signal y_wire: wire ;
signal w_wire: wire ;
signal atraso_vector: time_vector:=(others=>0);
--signals for setup output file print
signal listen_output: std_logic:='0' ;
signal enable_wr_file_output: std_logic:='0' ;
signal number_of_simulation: integer:=1 ;
signal timer_dog: time:=1 ns;
signal watch_dog: time:=now;
BEGIN -- circuits of signal_trace
linhas: for i in 1 to matriz_i generate
colunas: for j in 1 to matriz_j generate
w_wire (i,j) <= x_wire (i,j) xor y_wire (i,j);
end generate colunas;
end generate linhas;
-- Circuit Generate
for1:for j in 2 to matriz_j generate
for2:for i in 1 to matriz_i generate -- for i = 1->4
x_wire(i,j) <= w_wire ((i + (matriz_i/2)) mod (matriz_i) + 1,j-1) after (atraso_vector((2*i + (j * matriz_i)) + 1)) * 1 fs; -- wi+3
y_wire(i,j) <= w_wire ((i + ((matriz_i/2) - 1)) mod (matriz_i) + 1,j-1) after (atraso_vector((2*i + (j * matriz_i)) + 2)) * 1 fs; -- yi+3 = wi
end generate for2;
end generate for1;
-- Input/Output pins
--conecta o primeiro estagio aos pinos de entrada
entrada: for i in 1 to matriz_i generate
x_wire (i , 1) <= input_data (2*i-1) ;
y_wire (i , 1) <= input_data (2*i) ;
end generate entrada;
--conecta o ultimo estagio aos pinos observados como saida
saida: for i in 1 to matriz_i generate
output_result (i) <= w_wire (i , matriz_j);
end generate saida;
read_file: process -- read file_io.in (one time at start of simulation)
file my_delay_file : TEXT;-- open READ_MODE is "atrasos32bits.txt";--"atrasosDevadas.txt";
file my_stimulus_file : TEXT;-- open READ_MODE is "stimulus.txt";
variable delays_file: string( 1 to 20); -- support only 5 decimal digits
variable my_line : LINE;
variable my_input_line : LINE;
variable stimulus : STD_LOGIC_VECTOR (1 to 2*matriz_i);
variable intfromfile : integer;
variable mystring: string( 1 to 50*matriz_i*matriz_i*matriz_j); -- support only 2 decimal digits
variable string2: string( 1 to 20); -- support only 5 decimal digits
variable stimulus_string: string( 1 to 2 * matriz_i); -- support only 2 decimal digits
variable i: time:=100 ns;
variable x: integer:=1;
variable simulacao: integer:=1;
variable indice, next_indice, inteiro:integer:=0;
variable valorreal:real:=0.0;
variable indice_atraso_x, indice_atraso_y:integer:=0;
variable indice_i: natural;
variable deslocamento_nivel: integer;
variable temp: integer; -- a variavel acima so funciona com uma abaixo dela????
begin
listen_output <='0';
write(my_line, string'("Running and reading file"));
writeline(output, my_line);
file_open(my_delay_file,"./data/RPUF_delays/atrasos_RPUF_" & integer'image(matriz_i) & "x"&integer'image(matriz_j) & "_"&integer'image(individuos)&"_pufs_.txt",read_mode);
for x in 1 to individuos loop
str_read(my_delay_file, mystring); -- read
indice :=1;
-- disable print for output file
input_data <= conv_std_logic_vector(0, 2*matriz_i); -- define initial value for circuit input
for var in 1 to 2* matriz_i * (matriz_j) loop -- 2* matriz_i * (matriz_j-1)
next_indice:= str_nextchar (mystring, indice, ' ');
for var_zero in 1 to string2'length loop
string2 (var_zero):= '0';
end loop;
for var_str in 1 to next_indice-indice loop
string2 (string2'length - (next_indice-indice) +var_str):= mystring(indice + var_str-1);
end loop;
inteiro:=str_to_int(string2);
atraso_vector (var)<= inteiro;
indice:=next_indice+1;
end loop; -- end
number_of_simulation <=simulacao;
simulacao:=simulacao+1;
file_open(my_stimulus_file,"./data/Challenges/desafios_"& integer'image(number_of_vector)&"_C_"& integer'image(2*matriz_i) &"_bits.txt",read_mode);
watch_dog <= now ;
--file_open(my_stimulus_file,"vetores10bits.txt",read_mode);
enable_wr_file_output<='0';
-- disable print for output file
for x in 1 to number_of_vector loop -- Amount challenge lines must be determined
str_read(my_stimulus_file, stimulus_string); -- read
stimulus:= to_std_logic_vector(stimulus_string);
input_data <= stimulus;
timer_dog <= now ;
listen_output <='1';
wait for 0.9*base_tempo;
enable_wr_file_output <= '1';
wait for 0.1*base_tempo;
enable_wr_file_output <= '0';
end loop;
FILE_CLOSE(my_stimulus_file);
end loop;
FILE_CLOSE(my_delay_file);
write(my_line, string'("######## Finish simulation at "));
write(my_line, now);
writeline(output, my_line);
wait;
end process read_file;
prcs_and: process (output_result)
variable line_raw : LINE;
file raw_output_file : TEXT open WRITE_MODE is response_file_raw;
variable simulacao: integer:=0;
begin
if (listen_output = '1') then
if (simulacao/=number_of_simulation ) then -- Separa o resultado dos desafios com # numerodopuf
write(line_raw, string'("#"));
write(line_raw, number_of_simulation);
writeline(raw_output_file, line_raw);
end if;
simulacao:=number_of_simulation;
end if;
-- if (enable_wr_file_output = '1') then
write(line_raw, output_result);
write(line_raw, string'(" "));
write(line_raw, (now - watch_dog));
writeline(raw_output_file, line_raw);
-- end if;
end process prcs_and;
prcs_or: process (output_result,enable_wr_file_output)
variable my_line, my_line2,my_line3 : LINE;
variable line_flipflop : LINE;
variable line_ff_RPUF_2 : LINE;
file flipflop_output_file : TEXT open WRITE_MODE is response_file_rpuf1;--"APUF_32estagios.txt";
file ff_RPUF_2_output_file : TEXT open WRITE_MODE is response_file_rpuf2;
variable last_output_result: std_logic_vector (1 to matriz_i) := conv_std_logic_vector(0, matriz_i) ;
variable var_last_output_result: std_logic_vector (1 to matriz_i) := conv_std_logic_vector(0, matriz_i) ;
--variable flipflop: std_logic_vector (1 to (matriz_i*(matriz_i-1))/2) := conv_std_logic_vector(0, (matriz_i*(matriz_i-1))/2) ;
variable flipflop: std_logic_vector(1 to (matriz_i*(matriz_i-1))/2) := conv_std_logic_vector(0, (matriz_i*(matriz_i-1))/2);
variable ff_RPUF_2: std_logic_vector (1 to matriz_i*(matriz_i-1)) := conv_std_logic_vector(0, matriz_i*(matriz_i-1)) ;
variable simulacao: integer:=0;
variable aux: integer := 0;
variable aux1: integer := 0;
variable aux2: integer := 0;
begin
aux1 := 0;
aux2 := 0;
var_last_output_result:=output_result;
if (simulacao/=number_of_simulation ) then -- Separa o resultado dos desafios com #
write(line_flipflop, string'("#"));
write(line_flipflop, number_of_simulation);
writeline(flipflop_output_file, line_flipflop);
write(line_ff_RPUF_2, string'("#"));
write(line_ff_RPUF_2, number_of_simulation);
writeline(ff_RPUF_2_output_file, line_ff_RPUF_2);
end if;
simulacao:=number_of_simulation;
-- for i in 1 to matriz_i loop --
for i in 1 to matriz_i loop
--if (i=1) then --*12 23 34 45 56 67 71
for ii in i+1 to matriz_i loop
aux1 := aux1 + 1;
-- if last_output_result (i) /= var_last_output_result (i) then
if last_output_result (i) /= var_last_output_result (i) then
if output_result (i) = '1' then -- pega a borda de subida daquele sinal
flipflop(aux1):= var_last_output_result(ii);
end if;
end if;
-- end if;
end loop;
end loop;
for i in 1 to matriz_i loop
for ii in 1 to matriz_i loop
if ii /= i then
aux2:= aux2 + 1;
if last_output_result (i) /= var_last_output_result (i) then
if output_result (i) = '1' then
ff_RPUF_2(aux2):= var_last_output_result((ii));
end if;
end if;
end if;
end loop;
end loop;
-- end if;
-- write(my_line, i);
-- write(my_line, string'("-"));
-- end if;
-- end loop;
last_output_result := var_last_output_result;
-- else -- update
-- last_output_result := var_last_output_result;
if (listen_output = '1') then
if (enable_wr_file_output = '1') then
write(line_flipflop, flipflop);
writeline(flipflop_output_file, line_flipflop);
-- writeline(my_output_file, my_line);
write(line_ff_RPUF_2, ff_RPUF_2);
writeline(ff_RPUF_2_output_file, line_ff_RPUF_2);
end if;
end if;
end process prcs_or;
end architecture simulate_arch; -- end of simulate
|
gpl-2.0
|
2716aa859f756d33c13fad428a7bcae7
| 0.558949 | 3.36622 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd
| 1 | 6,555 |
-- Based on wb_fabric_pkg.vhd from Tomasz Wlostowski
-- Modified by Lucas Russo <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package wb_stream_pkg is
-- Must be at least 2 bits wide
constant c_wbs_address_width : integer := 4;
-- Must be at least 16 bits wide. Not a good solution, as streaming interfaces
-- might different widths. FIX ME!
constant c_wbs_data_width : integer := 64;
subtype t_wbs_address is
std_logic_vector(c_wbs_address_width-1 downto 0);
subtype t_wbs_data is
std_logic_vector(c_wbs_data_width-1 downto 0);
subtype t_wbs_byte_select is
std_logic_vector((c_wbs_data_width/8)-1 downto 0);
constant c_WBS_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WBS_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WBS_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WBS_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wbs_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
error : std_logic;
tag_me : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
type t_wbs_source_out is record
adr : t_wbs_address;
dat : t_wbs_data;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_byte_select;
end record;
subtype t_wbs_sink_in is t_wbs_source_out;
type t_wbs_source_in is record
ack : std_logic;
stall : std_logic;
err : std_logic;
rty : std_logic;
end record;
subtype t_wbs_sink_out is t_wbs_source_in;
--type t_wrf_oob is record
-- valid: std_logic;
-- oob_type : std_logic_vector(3 downto 0);
-- ts_r : std_logic_vector(27 downto 0);
-- ts_f : std_logic_vector(3 downto 0);
-- frame_id : std_logic_vector(15 downto 0);
-- port_id : std_logic_vector(5 downto 0);
--end record;
type t_wbs_source_in_array is array (natural range <>) of t_wbs_source_in;
type t_wbs_source_out_array is array (natural range <>) of t_wbs_source_out;
subtype t_wbs_sink_in_array is t_wbs_source_out_array;
subtype t_wbs_sink_out_array is t_wbs_source_in_array;
function f_marshall_wbs_status (stat : t_wbs_status_reg) return std_logic_vector;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg;
function f_packet_num_bits(packet_size : natural) return natural;
constant cc_dummy_wbs_addr : std_logic_vector(c_wbs_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_wbs_dat : std_logic_vector(c_wbs_data_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_wbs_sel : std_logic_vector(c_wbs_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_src_in : t_wbs_source_in :=
('0', '0', '0', '0');
constant cc_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
-- Components
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_o : out std_logic
);
end component;
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_i : in std_logic
);
end component;
end wb_stream_pkg;
package body wb_stream_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector
is
-- Wishbone bus data_width is at least 16 bits
variable tmp : std_logic_vector(c_wbs_data_width-1 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.error;
tmp(2) := stat.has_smac;
tmp(3) := stat.has_crc;
tmp(15 downto 8) := stat.match_class;
return tmp;
end;
function f_unmarshall_wbs_status(stat : std_logic_vector)
return t_wbs_status_reg
is
variable tmp : t_wbs_status_reg;
begin
tmp.is_hp := stat(0);
tmp.error := stat(1);
tmp.has_smac := stat(2);
tmp.has_crc := stat(3);
tmp.match_class := stat(15 downto 8);
return tmp;
end f_unmarshall_wbs_status;
function f_packet_num_bits(packet_size : natural)
return natural
is
-- Slightly different behaviour than the one located at wishbone_pkg.vhd
function f_ceil_log2(x : natural) return natural is
begin
if x <= 2
then return 1;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
begin
return f_ceil_log2(packet_size);
end f_packet_num_bits;
end wb_stream_pkg;
|
lgpl-3.0
|
176bcc4a8ae4627de41c6b16454e3947
| 0.557285 | 3.307265 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/vm2413/operator.vhd
| 2 | 5,318 |
--
-- Operator.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
--
-- modified by t.hara
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity Operator is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
WF : in std_logic;
FB : in std_logic_vector(2 downto 0);
noise : in std_logic;
pgout : in std_logic_vector( 17 downto 0 ); -- 9bit, 9bit
egout : in std_logic_vector( 12 downto 0 );
faddr : out integer range 0 to 9-1;
fdata : in SIGNED_LI_TYPE;
opout : out std_logic_vector( 13 downto 0 ) -- 8bit, 6bit
);
end entity;
architecture rtl of Operator is
signal addr : std_logic_vector( 17 downto 0 );
signal data : std_logic_vector( 13 downto 0 );
signal w_is_carrier : std_logic;
signal w_modula_m : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
signal w_modula_c : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
signal w_modula : std_logic_vector( LI_TYPE'high + 2 + 9 downto 0 );
signal ff_egout : std_logic_vector( 12 downto 0 );
begin
-- TCgiÎ\»j--------------------------------------------------
-- addr wèµ½XTCNÉ data ªoÄé
--
-- stage X 00 X 01 X 10 X 11 X 00
-- addr X mè
-- data X mè
-- opout X mè
--
u_sine_table : entity work.SineTable
port map(
clk => clk,
clkena => clkena,
wf => wf,
addr => addr,
data => data
);
w_is_carrier <= slot(0);
w_modula_m <= (others => '0') when( fb = "000" )else
shr( '0' & fdata.value & '0' & "000000000", "111" xor fb );
w_modula_c <= fdata.value & "00" & "000000000";
w_modula <= w_modula_c when( w_is_carrier = '1' )else
w_modula_m;
process( reset, clk )
variable opout_buf : std_logic_vector( 13 downto 0 ); -- ® 8bit, ¬ 6bit
begin
if( reset = '1' )then
opout <= (others => '0');
ff_egout <= (others => '0');
elsif( clk'event and clk='1' )then
if( clkena = '1' )then
if( stage = "00" )then
-- TCgÌQÆAhXiÊjðè·éXe[W
if( rhythm = '1' and ( slot = 14 or slot = 17 ))then -- HH or CYM
addr <= (not noise) & "01111111" & "000000000";
elsif( rhythm = '1' and slot = 15 )then -- SD
addr <= (not pgout(pgout'high)) & "01111111" & "000000000";
elsif( rhythm = '1' and slot = 16 )then -- TOM
addr <= pgout;
else
if( fdata.sign = '0' )then -- modula Í fdata ÌâÎlðVtgµ½l¾©çA±±ÅµÄé
addr <= pgout + w_modula(pgout'range);
else
addr <= pgout - w_modula(pgout'range);
end if;
end if;
elsif( stage = "01" )then
-- è³ê½QÆAhXª u_sine_table Ö³êéXe[W
elsif( stage = "10" )then
ff_egout <= egout;
-- tB[hobNÌAhXðßéXe[W
if( slot(0) = '1' )then
if( conv_integer(slot)/2 = 8 )then
faddr <= 0;
else
faddr <= conv_integer(slot)/2 + 1; -- ÌW
[^ÌAhXÈÌÅ +1
end if;
end if;
elsif( stage = "11" )then
-- SineTable ©çf[^ªoÄéXe[W
if ( ( '0' & ff_egout ) + ('0'& data(12 downto 0) ) ) < "10000000000000" then
opout_buf := data(13) & (ff_egout + data(12 downto 0) );
else
opout_buf := data(13) & "1111111111111";
end if;
opout <= opout_buf;
-- è³ê½tB[hobNAhXª FeedBackMemory Ö³êéXe[W
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
4469d0d09823a3f5c9abb8b0c7df7e2c
| 0.578789 | 2.819724 | false | false | false | false |
hoglet67/AtomBusMon
|
src/AVR8/Memory/XPM_Xilinx.vhd
| 2 | 1,648 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
library unisim;
use unisim.vcomponents.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XPM is
-- number of bits in the RAMB16_S18
constant ramb16_size : integer := 16384;
-- determine shape of memory
constant block_size : integer := ramb16_size / WIDTH;
constant block_bits : integer := f_log2(block_size);
constant num_blocks : integer := (SIZE + block_size - 1) / block_size;
type RAMBlDOut_Type is array(0 to num_blocks - 1) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
begin
RAM_Inst:for i in 0 to num_blocks - 1 generate
Ram : RAMB16_S18
generic map (
INIT => X"00000", -- Value of output RAM registers at startup
SRVAL => X"00000", -- Ouput value upon SSR assertion
WRITE_MODE => "WRITE_FIRST" -- WRITE_FIRST, READ_FIRST or NO_CHANGE
)
port map(
DO => RAMBlDOut(i),
ADDR => address(block_bits - 1 downto 0),
DI => din,
DIP => "11",
EN => ce,
SSR => '0',
CLK => cp2,
WE => '0'
);
end generate;
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto block_bits)));
end RTL;
|
gpl-3.0
|
1bdd2991a90c5fec837f9990f63616d1
| 0.594053 | 3.296 | false | false | false | false |
freecores/camellia-vhdl
|
pipelining/f_tb.vhd
| 1 | 2,599 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 09/25/2007
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module F
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity f_tb is
end f_tb;
ARCHITECTURE behavior of f_tb is
-- Component Declaration for the Unit Under Test (UUT)
component F
port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end component;
--Inputs
signal reset : STD_LOGIC;
signal clk : STD_LOGIC;
signal x : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
signal k : STD_LOGIC_VECTOR(0 to 63) := (others=>'0');
--Outputs
signal z : STD_LOGIC_VECTOR(0 to 63);
begin
-- Instantiate the Unit Under Test (UUT)
uut: F port map(
reset => reset,
clk => clk,
x => x,
k => k,
z => z
);
tb : process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
x <= X"abcdef1234567890";
k <= X"0987654321abcdef";
wait for 30 ns;
x <= X"0000000000000000";
k <= X"0000000000000000";
wait;
end process;
ck : process
begin
clk <= '0';
wait for 15 ns;
clk <= '1';
wait for 15 ns;
end process;
end;
|
gpl-3.0
|
5d2794be7fed5437af71b7ba7f8719e4
| 0.552135 | 4.067293 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd
| 1 | 27,453 |
------------------------------------------------------------------------------
-- Title : Wishbone FMC150 ADC interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with FMC150 ADC board from 4DSP.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-17 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_pkg.all;
-- Register Bank
use work.fmc150_wbgen2_pkg.all;
-- Reset Synch
use work.dbe_common_pkg.all;
entity wb_fmc150 is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Simulation Only ports
-----------------------------
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
sim_adc_data_valid : in std_logic;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- ADC output signals
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
-- Wishbone Streaming Interface Source
wbs_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
wbs_cyc_o : out std_logic;
wbs_stb_o : out std_logic;
wbs_we_o : out std_logic;
wbs_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
wbs_ack_i : in std_logic;
wbs_stall_i : in std_logic;
wbs_err_i : in std_logic;
wbs_rty_i : in std_logic
);
end wb_fmc150;
architecture rtl of wb_fmc150 is
-- Constants
constant c_counter_size : natural := f_packet_num_bits(g_packet_size);
constant c_num_channels : natural := 2;
constant c_num_adc_bits : natural := 16;
constant c_num_adc_data_msb : natural := c_num_channels*c_num_adc_bits-1;
-----------------------------------------------------------------------------------------------
-- IP / user logic interface signals
-----------------------------------------------------------------------------------------------
-- wb_fmc150 reg structure
signal regs_in : t_fmc150_out_registers;
signal regs_out : t_fmc150_in_registers;
-- Stream nterface structure
signal wbs_stream_out : t_wbs_source_out;
signal wbs_stream_in : t_wbs_source_in;
-- FMC 150 testbench signals
--signal cdce_pll_status : std_logic;
signal s_mmcm_adc_locked : std_logic;
signal s_adc_dout : std_logic_vector(c_num_channels*c_num_adc_bits-1 downto 0);
signal s_clk_adc : std_logic;
signal rst_n_adc : std_logic;
signal s_fmc150_rst : std_logic;
-- Streaming control signals
signal s_wbs_packet_counter : unsigned(c_counter_size-1 downto 0);
signal s_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal s_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal s_dvalid : std_logic;
signal s_sof : std_logic;
signal s_eof : std_logic;
signal s_error : std_logic;
signal s_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal s_dreq : std_logic;
-- Wishbone adapter structures
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
-- Components
-- Bank Register / Wishbone Interface
component wb_fmc150_port
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
--clk_100Mhz_i : in std_logic;
--clk_wb_i : in std_logic;
regs_i : in t_fmc150_in_registers;
regs_o : out t_fmc150_out_registers
);
end component;
-- Top FMC150 component
component fmc150_testbench
generic(
g_sim : integer := 0
);
port
(
rst : in std_logic;
clk_100Mhz : in std_logic;
clk_200Mhz : in std_logic;
adc_clk_ab_p : in std_logic;
adc_clk_ab_n : in std_logic;
-- Start Simulation Only!
sim_adc_clk_i : in std_logic;
sim_adc_clk2x_i : in std_logic;
-- End of Simulation Only!
adc_cha_p : in std_logic_vector(6 downto 0);
adc_cha_n : in std_logic_vector(6 downto 0);
adc_chb_p : in std_logic_vector(6 downto 0);
adc_chb_n : in std_logic_vector(6 downto 0);
-- Start Simulation Only!
sim_adc_cha_data_i : in std_logic_vector(13 downto 0);
sim_adc_chb_data_i : in std_logic_vector(13 downto 0);
-- End of Simulation Only!
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
--clk_to_fpga_p : in std_logic;
--clk_to_fpga_n : in std_logic;
--ext_trigger_p : in std_logic;
--ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
external_clock : in std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic;
adc_delay_update_i : in std_logic;
adc_str_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_cha_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_chb_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_str_cntvalueout_o : out std_logic_vector(4 downto 0);
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
mmcm_adc_locked_o : out std_logic
);
end component;
begin
-----------------------------------------------------------------------------------------------
-- BUS / IP interface
-----------------------------------------------------------------------------------------------
cmp_fmc150_testbench: fmc150_testbench
generic map(
g_sim => g_sim
)
port map
(
rst => s_fmc150_rst,
--clk_100Mhz => clk_100Mhz_i,
clk_100Mhz => clk_sys_i,
clk_200Mhz => clk_200Mhz_i,
adc_clk_ab_p => adc_clk_ab_p_i,
adc_clk_ab_n => adc_clk_ab_n_i,
-- Start Simulation Only!
sim_adc_clk_i => sim_adc_clk_i,
sim_adc_clk2x_i => sim_adc_clk2x_i,
-- End of Simulation Only!
adc_cha_p => adc_cha_p_i,
adc_cha_n => adc_cha_n_i,
adc_chb_p => adc_chb_p_i,
adc_chb_n => adc_chb_n_i,
-- Start Simulation Only!
sim_adc_cha_data_i => sim_adc_cha_data_i,
sim_adc_chb_data_i => sim_adc_chb_data_i,
-- End of Simulation Only!
dac_dclk_p => dac_dclk_p_o,
dac_dclk_n => dac_dclk_n_o,
dac_data_p => dac_data_p_o,
dac_data_n => dac_data_n_o,
dac_frame_p => dac_frame_p_o,
dac_frame_n => dac_frame_n_o,
txenable => txenable_o,
--clk_to_fpga_p => clk_to_fpga_p_i,
--clk_to_fpga_n => clk_to_fpga_n_i,
--ext_trigger_p => ext_trigger_p_i,
--ext_trigger_n => ext_trigger_n_i,
spi_sclk => spi_sclk_o,
spi_sdata => spi_sdata_o,
adc_n_en => adc_n_en_o,
adc_sdo => adc_sdo_i,
adc_reset => adc_reset_o,
cdce_n_en => cdce_n_en_o,
cdce_sdo => cdce_sdo_i,
cdce_n_reset => cdce_n_reset_o,
cdce_n_pd => cdce_n_pd_o,
ref_en => cdce_ref_en_o,
dac_n_en => dac_n_en_o,
dac_sdo => dac_sdo_i,
mon_n_en => mon_n_en_o,
mon_sdo => mon_sdo_i,
mon_n_reset => mon_n_reset_o,
mon_n_int => mon_n_int_i,
pll_status => cdce_pll_status_i, --cdce_pll_status,--regs_out.flgs_out_pll_status_i,
mmcm_adc_locked_o => s_mmcm_adc_locked,--regs_out.flgs_out_adc_clk_locked_i,
odata => regs_out.data_out_i,--s_odata,
busy => regs_out.flgs_out_spi_busy_i,--s_busy,
prsnt_m2c_l => prsnt_m2c_l_i,--regs_out.flgs_out_fmc_prst_i,--prsnt_m2c_l,
rd_n_wr => regs_in.flgs_in_spi_rw_o, --s_registers(FLAGS_IN_0)(FLAGS_IN_0_SPI_RW),
addr => regs_in.addr_o, --s_registers(ADDR)(15 downto 0),
idata => regs_in.data_in_o, --s_registers(DATAIN),
cdce72010_valid => regs_in.cs_cdce72010_o,--s_registers(CHIPSELECT)(CHIPSELECT_CDCE72010),
ads62p49_valid => regs_in.cs_ads62p49_o, --s_registers(CHIPSELECT)(CHIPSELECT_ADS62P49),
dac3283_valid => regs_in.cs_dac3283_o, --s_registers(CHIPSELECT)(CHIPSELECT_DAC3283),
amc7823_valid => regs_in.cs_amc7823_o, --s_registers(CHIPSELECT)(CHIPSELECT_AMC7823),
external_clock => regs_in.flgs_in_ext_clk_o, --s_registers(FLAGS_IN_0)(FLAGS_IN_0_EXTERNAL_CLOCK),
adc_delay_update_i => regs_in.flgs_pulse_o,--s_adc_delay_update,
adc_str_cntvaluein_i => regs_in.adc_dly_str_o,--s_registers(ADC_DELAY)(4 downto 0),
adc_cha_cntvaluein_i => regs_in.adc_dly_cha_o,--s_registers(ADC_DELAY)(12 downto 8),
adc_chb_cntvaluein_i => regs_in.adc_dly_chb_o,--s_registers(ADC_DELAY)(20 downto 16),
adc_str_cntvalueout_o => open,
adc_dout_o => s_adc_dout,
clk_adc_o => s_clk_adc
);
-- Export external signals to bus register bank
regs_out.flgs_out_pll_status_i <= cdce_pll_status_i;
regs_out.flgs_out_adc_clk_locked_i <= s_mmcm_adc_locked;
regs_out.flgs_out_fmc_prst_i <= prsnt_m2c_l_i;
-- Connect to output ports
adc_dout_o <= s_adc_dout;
clk_adc_o <= s_clk_adc;
-- Generate reset for fmc150_testbench module
s_fmc150_rst <= not rst_n_i;
--regs_out.flgs_out_pll_status_i <= cdce_pll_status;
regs_out.flgs_out_adc_clk_locked_i <= s_mmcm_adc_locked;
-- Pipelined <--> Classic cycles / Word <--> Byte address granularity
-- conversion
cmp_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,--wb_adr_i,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o
);
-- Decode only the LSB bits. In this case, at most, 5 LSB must be decoded
-- (if byte addresses) or 3 LSB (if word addressed). We have to consider
-- the biggest value in order not to mismatch register addresses.
-- See wb_fmc150_port.vhd for register bank addresses.
resized_addr(4 downto 0) <= wb_adr_i(4 downto 0);
resized_addr(c_wishbone_address_width-1 downto 5)
<= (others => '0');
-- Register Bank / Wishbone Interface
cmp_wb_fmc150_port : wb_fmc150_port
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
--clk_100Mhz_i => clk_100Mhz_i,
--clk_wb_i => clk_sys_i,
regs_i => regs_out,
regs_o => regs_in
);
-- Reset synchronization with ADC clock domain
cmp_reset_adc_synch : reset_synch
port map(
clk_i => s_clk_adc,
arst_n_i => rst_n_i,
rst_n_o => rst_n_adc
);
-- This stream source is in ADC clock domain
cmp_wb_source_if : xwb_stream_source
port map(
clk_i => s_clk_adc,
--rst_n_i => rst_n_i,
rst_n_i => rst_n_adc,
-- Wishbone Fabric Interface I/O
src_i => wbs_stream_in,
src_o => wbs_stream_out,
-- Decoded & buffered logic
addr_i => s_addr,
data_i => s_data,
dvalid_i => s_dvalid,
sof_i => s_sof,
eof_i => s_eof,
error_i => s_error,
-- For now, just pick the LSB bit of s_bytesel
bytesel_i => s_bytesel,
dreq_o => s_dreq
);
-- Write always to addr 0
s_addr <= (others => '0');
-- Simulation / Syntesis Only consructs. Is there a better way to do it?
s_data(c_num_adc_data_msb downto 0) <= s_adc_dout(c_num_adc_data_msb downto 0);
s_data(c_wbs_data_width downto c_num_adc_data_msb+1) <= (others => '0');
gen_stream_valid : if (g_sim = 0) generate
s_dvalid <= cdce_pll_status_i and s_mmcm_adc_locked;
end generate;
gen_stream_valid_sim : if (g_sim = 1) generate
s_dvalid <= sim_adc_data_valid;
end generate;
-- generate SOF and EOF signals
p_gen_sof_eof : process(s_clk_adc, rst_n_adc)
begin
if rst_n_adc = '0' then
--s_sof <= '0';
--s_eof <= '0';
s_wbs_packet_counter <= (others => '0');
elsif rising_edge(s_clk_adc) then
-- Increment counter if data is valid
if s_dvalid = '1' then
s_wbs_packet_counter <= s_wbs_packet_counter + 1;
end if;
end if;
end process;
-- Generate SOF and EOF signals based on counter
s_sof <= '1' when s_wbs_packet_counter = to_unsigned(0, c_counter_size) else '0';
s_eof <= '1' when s_wbs_packet_counter = g_packet_size-1 else '0';
s_error <= '0';
s_bytesel <= (others => '1');
wbs_adr_o <= wbs_stream_out.adr;
wbs_dat_o <= wbs_stream_out.dat;
wbs_cyc_o <= wbs_stream_out.cyc;
wbs_stb_o <= wbs_stream_out.stb;
wbs_we_o <= wbs_stream_out.we;
wbs_sel_o <= wbs_stream_out.sel;
wb_err_o <= '0';
wb_rty_o <= '0';
wbs_stream_in.ack <= wbs_ack_i;
wbs_stream_in.stall <= wbs_stall_i;
wbs_stream_in.err <= wbs_err_i;
wbs_stream_in.rty <= wbs_rty_i;
end rtl;
|
lgpl-3.0
|
5a10daab59421162f1d975bf6cda105f
| 0.376061 | 4.262888 | false | false | false | false |
z3774/sparcv8-monocycle
|
CU.vhd
| 1 | 14,617 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CU is
Port (
--clk : in STD_LOGIC;
op : in STD_LOGIC_VECTOR (1 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
en_dm : out STD_LOGIC;
we_dm : out STD_LOGIC;
pc_src: out STD_LOGIC_VECTOR (1 downto 0);
we_rf : out STD_LOGIC;
rf_src: out STD_LOGIC_VECTOR (1 downto 0);
rf_dtn: out STD_LOGIC
);
end CU;
architecture Behavioral of CU is
begin
process(op,op2,op3,cond,icc)--, clk)
begin
--if (rising_edge(clk)) then
-- OP = 10
case op is
when "00" =>
case op2 is
when "010" =>
case cond is
--BA 1
when "1000" =>
--1
aluop <= "000001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "10"; --pc+disp22
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BN 2
when "0000" =>
--0
aluop <= "000010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
-- BNE 3
when "1001" =>
aluop <= "000011";
en_dm <= '1';
we_dm <= '0';
--not Z
if(not(icc(2)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BE 4
when "0001" =>
aluop <= "000100";
en_dm <= '1';
we_dm <= '0';
--Z
if(icc(2) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BG 5
when "1010" =>
aluop <= "000101";
en_dm <= '1';
we_dm <= '0';
-- not(Z or (N xor V))
if((not(icc(2) or (icc(3) xor icc(1)))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BLE 6
when "0010" =>
aluop <= "000110";
en_dm <= '1';
we_dm <= '0';
--Z or (N xor V)
if((icc(2) or (icc(3) xor icc(1))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
-- BGE 7
when "1011" =>
aluop <= "000111";
en_dm <= '1';
we_dm <= '0';
--not (N xor V)
if((not(icc(3) xor icc(1))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BL 8
when "0011" =>
aluop <= "001000";
en_dm <= '1';
we_dm <= '0';
-- (N xor V)
if((icc(3) xor icc(1)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BGU 9
when "1100" =>
aluop <= "001001";
en_dm <= '1';
we_dm <= '0';
-- not(C or Z)
if((not(icc(0) or icc(2))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BLEU 10
when "0100" =>
aluop <= "001010";
en_dm <= '1';
we_dm <= '0';
-- (C or Z)
if((icc(0) or icc(2)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BCC 11
when "1101" =>
aluop <= "001011";
en_dm <= '1';
we_dm <= '0';
--not C
if(not(icc(0)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BCS 12
when "0101" =>
aluop <= "001100";
en_dm <= '1';
we_dm <= '0';
--C
if(icc(0) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BPOS 13
when "1110" =>
aluop <= "001101";
en_dm <= '1';
we_dm <= '0';
--not N
if(not(icc(3)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BNEG 14
when "0110" =>
aluop <= "001110";
en_dm <= '1';
we_dm <= '0';
--N
if(icc(3) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BVC 15
when "1111" =>
aluop <= "001111";
en_dm <= '1';
we_dm <= '0';
--not V
if(not(icc(1)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BVS 16
when "0111" =>
aluop <= "010000";
en_dm <= '1';
we_dm <= '0';
--V
if(icc(1) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0'; --
pc_src <= "11"; --pc --
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
end case;
when "100" =>
-- NOP 19
aluop <= "010011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
end case;
-- op = 01
when "01" =>
--CALL 0
aluop <= "000000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "01"; --pc+disp30
we_rf <= '1';
rf_src <= "10"; --pc
rf_dtn <= '1';
-- op = 10
when "10" =>
case op3 is
--ADD 32
when "000000" =>
aluop <= "100000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ADDcc
when "010000" =>
aluop <= "100001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ADDX
when "001000" =>
aluop <= "100010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ADDXcc
when "011000" =>
aluop <= "100011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUB 36
when "000100" =>
aluop <= "100100";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUBcc
when "010100" =>
aluop <= "100101";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUBX
when "001100" =>
aluop <= "100110";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUBXcc
when "011100" =>
aluop <= "100111";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--AND 40
when "000001" =>
aluop <= "101000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ANDcc
when "010001" =>
aluop <= "101001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ANDN
when "000101" =>
aluop <= "101010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ANDNcc
when "010101" =>
aluop <= "101011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--OR
when "000010" =>
aluop <= "101100";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ORcc
when "010010" =>
aluop <= "101101";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ORN
when "000110" =>
aluop <= "101110";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ORNcc
when "010110" =>
aluop <= "101111";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XOR
when "000011" =>
aluop <= "110000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XORcc
when "010011" =>
aluop <= "110001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XNOR
when "000111" =>
aluop <= "110010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XNORcc 51
when "010111" =>
aluop <= "110011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SAVE 57
when "111100" =>
aluop <= "111001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--RESTORE 58
when "111101" =>
aluop <= "111010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--JMPL 59
when "111000" =>
aluop <= "111011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "00"; --alurs
we_rf <= '1';
rf_src <= "10"; --pc
rf_dtn <= '0'; --nrd
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0';
end case;
-- OP = 11
when "11" =>
case op3 is
--LD 55
when "000000" =>
aluop <= "110111";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "00"; --dm
rf_dtn <= '0'; --nrd
--ST 56
when "000100" =>
aluop <= "111000";
en_dm <= '1';
we_dm <= '1';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0';
end case;
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0';
end case;
--end if; -- risingEdge
end process;
end Behavioral;
|
gpl-3.0
|
58c233576fe344515533a527683c4d41
| 0.31826 | 2.882469 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/video/framebuffer.vhd
| 2 | 11,107 |
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: framebuffer.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY framebuffer IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END framebuffer;
ARCHITECTURE SYN OF framebuffer IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clock0 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
address_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock1 : IN STD_LOGIC ;
data_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_b : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(3 DOWNTO 0);
q_b <= sub_wire1(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 60480,
numwords_b => 60480,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 16,
widthad_b => 16,
width_a => 4,
width_b => 4,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clock0 => clock_a,
wren_a => wren_a,
address_b => address_b,
clock1 => clock_b,
data_b => data_b,
wren_b => wren_b,
address_a => address_a,
data_a => data_a,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "241920"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "60480"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "60480"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 16 0 INPUT NODEFVAL "address_a[15..0]"
-- Retrieval info: USED_PORT: address_b 0 0 16 0 INPUT NODEFVAL "address_b[15..0]"
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
-- Retrieval info: USED_PORT: data_a 0 0 4 0 INPUT NODEFVAL "data_a[3..0]"
-- Retrieval info: USED_PORT: data_b 0 0 4 0 INPUT NODEFVAL "data_b[3..0]"
-- Retrieval info: USED_PORT: q_a 0 0 4 0 OUTPUT NODEFVAL "q_a[3..0]"
-- Retrieval info: USED_PORT: q_b 0 0 4 0 OUTPUT NODEFVAL "q_b[3..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @address_a 0 0 16 0 address_a 0 0 16 0
-- Retrieval info: CONNECT: @address_b 0 0 16 0 address_b 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 4 0 data_a 0 0 4 0
-- Retrieval info: CONNECT: @data_b 0 0 4 0 data_b 0 0 4 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: CONNECT: q_b 0 0 4 0 @q_b 0 0 4 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL framebuffer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL framebuffer.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL framebuffer.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL framebuffer.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL framebuffer_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
gpl-3.0
|
7cc06a4a8eea2b771685ae207cc21290
| 0.677951 | 3.260053 | false | false | false | false |
fbelavenuto/msx1fpga
|
synth/zxuno/ipcore_dir/pll1.vhd
| 4 | 6,574 |
-- file: pll1.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____21.429______0.000______50.0______309.742____193.725
-- CLK_OUT2____25.000______0.000______50.0______300.363____193.725
-- CLK_OUT3___125.000______0.000______50.0______211.658____193.725
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________50.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll1 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic
);
end pll1;
architecture xilinx of pll1 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll1,clk_wiz_v3_6,{component_name=pll1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 15,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 35,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 30,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 6,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
clkout3_buf : BUFG
port map
(O => CLK_OUT3,
I => clkout2);
end xilinx;
|
gpl-3.0
|
e87ff36abc4cec2f6d3caf6a270f628c
| 0.589443 | 4.070588 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/peripheral/memoryctl.vhd
| 2 | 8,549 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memoryctl is
generic (
ramsize_g : integer := 512 -- 512, 2048 or 8192
);
port (
cpu_addr_i : in std_logic_vector(15 downto 0);
use_rom_in_ram_i : in std_logic;
--
rom_cs_i : in std_logic;
extrom_cs_i : in std_logic;
xb2rom_cs_i : in std_logic;
nxt_rom_cs_i : in std_logic;
nxt_rom_page_i : in std_logic_vector( 2 downto 0);
ipl_cs_i : in std_logic;
ipl_rampage_i : in std_logic_vector( 8 downto 0);
mr_ram_cs_i : in std_logic;
mr_ram_addr_i : in std_logic_vector(19 downto 0); -- 1MB
ram_cs_i : in std_logic;
ram_page_i : in std_logic_vector( 7 downto 0);
--
ram_addr_o : out std_logic_vector(22 downto 0); -- Max 8MB
mapper_mask_o : out std_logic_vector( 7 downto 0)
);
end entity;
architecture Behavior of memoryctl is
begin
m512: if ramsize_g = 512 generate
-- RAM map
-- Address Range System Size A22-A14 IPL Pages range
-- 00 0000-01 FFFF NEXTOR 128K 0000 00xxx 000-007
-- 02 0000-03 FFFF Mapper RAM 128K 0000 01xxx 008-00F
-- 04 0000-07 FFFF SCC/Megaram 256K 0000 1xxxx 010-01F
-- OR
-- 04 0000-05 FFFF SCC/Megaram 128K 0000 10xxx 020-023
-- 06 0000-07 7FFF (empty) 96K 0000 11... 024-029
-- 07 8000-07 FFFF ROM 32K 0000 1111x 01E-01F
process (nxt_rom_cs_i, ipl_cs_i, cpu_addr_i, nxt_rom_page_i,
ram_page_i, ipl_rampage_i, ram_cs_i, mr_ram_addr_i,
use_rom_in_ram_i, mr_ram_cs_i, rom_cs_i)
begin
ram_addr_o <= (others => '0');
if nxt_rom_cs_i = '1' then -- Nextor
ram_addr_o <= "000000" & nxt_rom_page_i & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15 downto 14) = "01" then -- RAM 16K (IPL) ($4000-$7FFF)
ram_addr_o <= "000001111" & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15) = '1' then -- All RAM (IPL) ($8000-$FFFF)
ram_addr_o <= "0000" & ipl_rampage_i(4 downto 0) & cpu_addr_i(13 downto 0);
elsif mr_ram_cs_i = '1' then -- SCC/Megaram (only 128 or 256K)
if use_rom_in_ram_i = '1' then
ram_addr_o <= "000010" & mr_ram_addr_i(16 downto 0);
else
ram_addr_o <= "00001" & mr_ram_addr_i(17 downto 0);
end if;
elsif rom_cs_i = '1' and use_rom_in_ram_i = '1' then -- ROM
ram_addr_o <= "00001111" & cpu_addr_i(14 downto 0);
elsif ram_cs_i = '1' then -- Mapper (only 128K)
ram_addr_o <= "000001" & ram_page_i(2 downto 0) & cpu_addr_i(13 downto 0);
else
null;
end if;
end process;
mapper_mask_o <= "00000111"; -- 128K
end generate;
m2M: if ramsize_g = 2048 generate
-- RAM map
-- Address Range System Size A22-A14 IPL Pages range
-- 00 0000-00 7FFF ROM BIOS 32K 00 000000x 000-001
-- 00 8000-00 BFFF EXT ROM 16K 00 0000010 002-002
-- 00 C000-00 FFFF XBASIC2 ROM 16K 00 0000011 003-003
-- 01 0000-01 FFFF (empty) 64K 00 00001xx 004-007
-- 02 0000-03 FFFF Nextor ROM 128K 00 0001xxx 008-00F
-- 04 0000-07 FFFF (empty) 256K 00 001xxxx 010-01F
-- 08 0000-0F FFFF ESCCI 512K 00 01xxxxx 020-03F
-- 10 0000-1F FFFF RAM Mapper 1MB 00 1xxxxxx 040-07F
process (nxt_rom_cs_i, ipl_cs_i, cpu_addr_i, nxt_rom_page_i,
ram_page_i, ipl_rampage_i, ram_cs_i, mr_ram_addr_i,
use_rom_in_ram_i, mr_ram_cs_i, rom_cs_i, extrom_cs_i,
xb2rom_cs_i)
begin
ram_addr_o <= (others => '0');
if rom_cs_i = '1' then -- ROM
ram_addr_o <= "00000000" & cpu_addr_i(14 downto 0);
elsif extrom_cs_i = '1' then -- Extension ROM
ram_addr_o <= "000000010" & cpu_addr_i(13 downto 0);
elsif xb2rom_cs_i = '1' then -- XBASIC2 ROM
ram_addr_o <= "000000011" & cpu_addr_i(13 downto 0);
elsif nxt_rom_cs_i = '1' then -- Nextor
ram_addr_o <= "000001" & nxt_rom_page_i & cpu_addr_i(13 downto 0);
elsif mr_ram_cs_i = '1' then -- SCC/Megaram (only 512K)
ram_addr_o <= "0001" & mr_ram_addr_i(18 downto 0);
elsif ram_cs_i = '1' then -- Mapper (only 1MB)
ram_addr_o <= "001" & ram_page_i(5 downto 0) & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15 downto 14) = "01" then -- RAM 16K (IPL) ($4000-$7FFF)
ram_addr_o <= "001111111" & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15) = '1' then -- All RAM (IPL) ($8000-$FFFF)
ram_addr_o <= "00" & ipl_rampage_i(6 downto 0) & cpu_addr_i(13 downto 0);
else
null;
end if;
end process;
mapper_mask_o <= "00111111"; -- 1MB
end generate;
m8M: if ramsize_g = 8192 generate
-- RAM map
-- Address Range System Size A22-A14 IPL Pages range
-- 00 0000-00 7FFF ROM BIOS 32K 00 000000x 000-001
-- 00 8000-00 BFFF EXT ROM 16K 00 0000010 002-002
-- 00 C000-00 FFFF XBASIC2 ROM 16K 00 0000011 003-003
-- 01 0000-01 FFFF (empty) 64K 00 00001xx 004-007
-- 02 0000-03 FFFF Nextor ROM 128K 00 0001xxx 008-00F
-- 04 0000-07 FFFF (empty) 256K 00 001xxxx 010-01F
-- 08 0000-0F FFFF (empty) 512K 00 01xxxxx 020-03F
-- 10 0000-1F FFFF ESCCI 1MB 00 1xxxxxx 040-07F
-- 20 0000-3F FFFF (empty) 2MB 01 xxxxxxx 080-0FF
-- 40 0000-7F FFFF RAM Mapper 4MB 1x xxxxxxx 100-1FF
process (nxt_rom_cs_i, ipl_cs_i, cpu_addr_i, nxt_rom_page_i,
ram_page_i, ipl_rampage_i, ram_cs_i, mr_ram_addr_i,
mr_ram_cs_i, rom_cs_i, extrom_cs_i, xb2rom_cs_i)
begin
ram_addr_o <= (others => '0');
if rom_cs_i = '1' then -- ROM
ram_addr_o <= "00000000" & cpu_addr_i(14 downto 0);
elsif extrom_cs_i = '1' then -- Extension ROM
ram_addr_o <= "000000010" & cpu_addr_i(13 downto 0);
elsif xb2rom_cs_i = '1' then -- XBASIC2 ROM
ram_addr_o <= "000000011" & cpu_addr_i(13 downto 0);
elsif nxt_rom_cs_i = '1' then -- Nextor
ram_addr_o <= "000001" & nxt_rom_page_i & cpu_addr_i(13 downto 0);
elsif mr_ram_cs_i = '1' then -- SCC/Megaram
ram_addr_o <= "001" & mr_ram_addr_i;
elsif ram_cs_i = '1' then -- Mapper
ram_addr_o <= "1" & ram_page_i & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15 downto 14) = "01" then -- RAM 16K (IPL) ($4000-$7FFF)
ram_addr_o <= "111111111" & cpu_addr_i(13 downto 0);
elsif ipl_cs_i = '1' and cpu_addr_i(15) = '1' then -- All RAM (IPL) ($8000-$FFFF)
ram_addr_o <= ipl_rampage_i & cpu_addr_i(13 downto 0);
else
null;
end if;
end process;
mapper_mask_o <= "11111111"; -- 4MB
end generate;
end architecture;
|
gpl-3.0
|
1dae556539e23efcfc704a9f58df5832
| 0.610481 | 2.713968 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/video/vdp18/vdp18_palette.vhd
| 2 | 3,427 |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_palette.vhd,v 1.10 2016/11/09 10:47:01 fbelavenuto Exp $
--
-- Palette
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vdp18_palette is
port (
reset_i : in boolean;
clock_i : in std_logic;
we_i : in std_logic;
addr_wr_i : in std_logic_vector(0 to 3);
data_i : in std_logic_vector(0 to 15);
addr_rd_i : in std_logic_vector(0 to 3);
data_o : out std_logic_vector(0 to 15)
);
end entity;
architecture Memory of vdp18_palette is
type ram_t is array (natural range 15 downto 0) of std_logic_vector(15 downto 0);
signal ram_q : ram_t;
signal read_addr_q : unsigned(3 downto 0);
begin
process (reset_i, clock_i)
begin
if reset_i then
ram_q <= (
-- RB0G
0 => X"0000",
1 => X"0000",
2 => X"240C",
3 => X"570D",
4 => X"5E05",
5 => X"7F07",
6 => X"D405",
7 => X"4F0E",
8 => X"F505",
9 => X"F707",
10 => X"D50C",
11 => X"E80C",
12 => X"230B",
13 => X"CB09",
14 => X"CC0C",
15 => X"FF0F"
);
elsif rising_edge(clock_i) then
if we_i = '1' then
ram_q(to_integer(unsigned(addr_wr_i))) <= data_i;
end if;
read_addr_q <= unsigned(addr_rd_i);
end if;
end process;
data_o <= ram_q(to_integer(read_addr_q));
end architecture;
|
gpl-3.0
|
022b58373b49230e4eb25ed58badc85b
| 0.635833 | 3.454637 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/msx.vhd
| 2 | 26,732 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
-- Slots:
-- 0 = Primary: BIOS+BASIC
-- 1 = Expanded:
-- 1.0 = XBASIC2
-- 1.1 = External slot 1
-- 1.2 = External slot 2
-- 2 = ESCCI
-- 3 = Expanded:
-- 3.0 = ExtROM from $4000-$7FFF
-- 3.1 = RAM Mapper
-- 3.2 = Nextor from $4000-$BFFF
-- 3.3 = IPL
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.msx_pack.all;
entity msx is
generic (
hw_id_g : integer := 0;
hw_txt_g : string := "NONE";
hw_version_g : std_logic_vector(7 downto 0) := X"00";
video_opt_g : integer := 0; -- 0 = no dblscan, 1 = dblscan configurable, 2 = dblscan always enabled, 3 = no dblscan and external palette
ramsize_g : integer := 512; -- 512, 2048 or 8192
hw_hashwds_g : std_logic := '0' -- 0 = Software disk-change, 1 = Hardware disk-change
);
port (
-- Clocks
clock_i : in std_logic;
clock_vdp_i : in std_logic;
clock_cpu_i : in std_logic;
clock_psg_en_i : in std_logic;
-- Turbo
turbo_on_k_i : in std_logic;
turbo_on_o : out std_logic;
-- Resets
reset_i : in std_logic;
por_i : in std_logic;
softreset_o : out std_logic;
reload_o : out std_logic;
-- Options
opt_nextor_i : in std_logic;
opt_mr_type_i : in std_logic_vector(1 downto 0);
opt_vga_on_i : in std_logic := '0';
-- RAM
ram_addr_o : out std_logic_vector(22 downto 0); -- 8MB
ram_data_i : in std_logic_vector( 7 downto 0);
ram_data_o : out std_logic_vector( 7 downto 0);
ram_ce_o : out std_logic;
ram_oe_o : out std_logic;
ram_we_o : out std_logic;
-- ROM
rom_addr_o : out std_logic_vector(14 downto 0); -- 32K
rom_data_i : in std_logic_vector( 7 downto 0);
rom_ce_o : out std_logic;
rom_oe_o : out std_logic;
-- External bus
bus_addr_o : out std_logic_vector(15 downto 0);
bus_data_i : in std_logic_vector( 7 downto 0);
bus_data_o : out std_logic_vector( 7 downto 0);
bus_rd_n_o : out std_logic;
bus_wr_n_o : out std_logic;
bus_m1_n_o : out std_logic;
bus_iorq_n_o : out std_logic;
bus_mreq_n_o : out std_logic;
bus_sltsl1_n_o : out std_logic;
bus_sltsl2_n_o : out std_logic;
bus_wait_n_i : in std_logic;
bus_nmi_n_i : in std_logic;
bus_int_n_i : in std_logic;
-- VDP VRAM
vram_addr_o : out std_logic_vector(13 downto 0); -- 16K
vram_data_i : in std_logic_vector( 7 downto 0);
vram_data_o : out std_logic_vector( 7 downto 0);
vram_ce_o : out std_logic;
vram_oe_o : out std_logic;
vram_we_o : out std_logic;
-- Keyboard
rows_o : out std_logic_vector( 3 downto 0);
cols_i : in std_logic_vector( 7 downto 0) := (others => '1');
caps_en_o : out std_logic;
keyb_valid_i : in std_logic;
keyb_data_i : in std_logic_vector( 7 downto 0);
keymap_addr_o : out std_logic_vector( 8 downto 0);
keymap_data_o : out std_logic_vector( 7 downto 0);
keymap_we_o : out std_logic;
-- Audio
audio_scc_o : out signed(14 downto 0);
audio_psg_o : out unsigned( 7 downto 0);
beep_o : out std_logic;
volumes_o : out volumes_t;
-- K7
k7_motor_o : out std_logic;
k7_audio_o : out std_logic;
k7_audio_i : in std_logic;
-- Joystick
joy1_up_i : in std_logic;
joy1_down_i : in std_logic;
joy1_left_i : in std_logic;
joy1_right_i : in std_logic;
joy1_btn1_i : in std_logic;
joy1_btn1_o : out std_logic;
joy1_btn2_i : in std_logic;
joy1_btn2_o : out std_logic;
joy1_out_o : out std_logic;
joy2_up_i : in std_logic;
joy2_down_i : in std_logic;
joy2_left_i : in std_logic;
joy2_right_i : in std_logic;
joy2_btn1_i : in std_logic;
joy2_btn1_o : out std_logic;
joy2_btn2_i : in std_logic;
joy2_btn2_o : out std_logic;
joy2_out_o : out std_logic;
-- Video
cnt_hor_o : out std_logic_vector( 8 downto 0);
cnt_ver_o : out std_logic_vector( 7 downto 0);
rgb_r_o : out std_logic_vector( 3 downto 0);
rgb_g_o : out std_logic_vector( 3 downto 0);
rgb_b_o : out std_logic_vector( 3 downto 0);
hsync_n_o : out std_logic;
vsync_n_o : out std_logic;
ntsc_pal_o : out std_logic;
vga_on_k_i : in std_logic;
vga_en_o : out std_logic;
scanline_on_k_i: in std_logic;
scanline_en_o : out std_logic;
vertfreq_on_k_i: in std_logic := '0';
-- SPI/SD
flspi_cs_n_o : out std_logic;
spi2_cs_n_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := '0';
sd_pres_n_i : in std_logic := '0';
sd_wp_i : in std_logic := '0';
-- DEBUG
D_wait_o : out std_logic;
D_slots_o : out std_logic_vector( 7 downto 0);
D_ipl_en_o : out std_logic
);
end entity;
architecture Behavior of msx is
-- Turbo
signal turbo_on_s : std_logic;
-- Reset
signal reset_n_s : std_logic;
-- signal por_n_s : std_logic;
signal softreset_s : std_logic;
-- CPU signals
signal int_n_s : std_logic;
signal iorq_n_s : std_logic;
signal m1_n_s : std_logic;
signal wait_n_s : std_logic;
signal rd_n_s : std_logic;
signal wr_n_s : std_logic;
signal mreq_n_s : std_logic;
signal rfsh_n_s : std_logic;
signal cpu_addr_s : std_logic_vector(15 downto 0);
signal d_to_cpu_s : std_logic_vector( 7 downto 0);
signal d_from_cpu_s : std_logic_vector( 7 downto 0);
-- Bus and Wait
signal m1_wait_n_s : std_logic;
signal m1_wait_ff_s : std_logic_vector(1 downto 0);
signal vdp_int_n_s : std_logic;
signal nrd_s : std_logic;
signal nwr_s : std_logic;
signal niorq_s : std_logic;
signal vdp_wait_s : std_logic;
-- Address Decoder
signal io_access_s : std_logic;
signal io_read_s : std_logic;
signal io_write_s : std_logic;
-- Memory
signal prim_slot_n_s : std_logic_vector( 3 downto 0) := "1111";
signal pslot_s : std_logic_vector( 1 downto 0) := "00";
signal d_from_exp1_s : std_logic_vector( 7 downto 0);
signal slot1_exp_n_s : std_logic_vector( 3 downto 0) := "1111";
signal exp1_has_data_s : std_logic;
signal d_from_exp3_s : std_logic_vector( 7 downto 0);
signal slot3_exp_n_s : std_logic_vector( 3 downto 0) := "1111";
signal exp3_has_data_s : std_logic;
signal brom_cs_s : std_logic;
signal extrom_cs_s : std_logic;
signal xb2rom_cs_s : std_logic;
signal ram_cs_s : std_logic;
signal use_rom_in_ram_s : std_logic;
signal hw_memsize_s : std_logic_vector( 7 downto 0);
-- IPL
signal ipl_en_s : std_logic;
signal iplrom_addr_s : std_logic_vector(12 downto 0);
signal d_from_iplrom_s : std_logic_vector( 7 downto 0);
signal ipl_cs_s : std_logic;
signal iplrom_cs_s : std_logic;
signal iplram_cs_s : std_logic;
signal iplram_bw_s : std_logic;
signal ipl_rampage_s : std_logic_vector( 8 downto 0);
-- Mapper
signal mp_mask_s : std_logic_vector( 7 downto 0);
signal mp_invmask_s : std_logic_vector( 7 downto 0);
signal mp_page_s : std_logic_vector( 7 downto 0);
signal mp_bank0_s : std_logic_vector( 7 downto 0);
signal mp_bank1_s : std_logic_vector( 7 downto 0);
signal mp_bank2_s : std_logic_vector( 7 downto 0);
signal mp_bank3_s : std_logic_vector( 7 downto 0);
signal mp_cs_s : std_logic;
signal d_from_mp_s : std_logic_vector( 7 downto 0);
-- VDP18
signal d_from_vdp_s : std_logic_vector( 7 downto 0);
signal vdp_rd_n_s : std_logic;
signal vdp_wr_n_s : std_logic;
signal vga_en_s : std_logic;
signal scanline_en_s : std_logic;
signal ntsc_pal_s : std_logic := '0';
signal vertfreq_csw_s : std_logic;
signal vertfreq_d_s : std_logic;
-- PSG
signal psg_cs_s : std_logic;
signal psg_bdir_s : std_logic;
signal psg_bc1_s : std_logic;
signal d_from_psg_s : std_logic_vector( 7 downto 0);
signal psg_port_a_s : std_logic_vector( 7 downto 0) := (others => '1');
signal psg_port_b_s : std_logic_vector( 7 downto 0);
-- Joystick
alias joy_sel_a : std_logic is psg_port_b_s(6);
signal joy_sigs_s : std_logic_vector(5 downto 0);
-- PIO
signal d_from_pio_s : std_logic_vector( 7 downto 0);
signal pio_hd_s : std_logic;
signal pio_cs_s : std_logic;
signal pio_rd_s : std_logic;
signal pio_wr_s : std_logic;
signal pio_port_a_s : std_logic_vector( 7 downto 0);
signal pio_port_c_s : std_logic_vector( 7 downto 0);
alias pio_rows_coded_a : std_logic_vector( 3 downto 0) is pio_port_c_s(3 downto 0);
alias pio_motoron_a : std_logic is pio_port_c_s(4);
alias pio_k7out_a : std_logic is pio_port_c_s(5);
alias pio_caps_a : std_logic is pio_port_c_s(6);
alias pio_beep_a : std_logic is pio_port_c_s(7);
-- Switched I/O ports
signal swp_hd_s : std_logic;
signal d_from_swp_s : std_logic_vector( 7 downto 0);
-- SPI/SD
signal nextor_en_s : std_logic;
signal spi_cs_s : std_logic;
signal spi_hd_s : std_logic;
signal d_from_spi_s : std_logic_vector( 7 downto 0);
signal nxt_rom_page_s : std_logic_vector( 2 downto 0);
signal nxt_rom_cs_s : std_logic;
signal nxt_rom_wr_s : std_logic;
-- SCC/Megaram
signal mram_cs_s : std_logic;
signal d_from_mram_s : std_logic_vector( 7 downto 0);
signal mr_type_s : std_logic_vector( 1 downto 0);
signal mr_ram_addr_s : std_logic_vector(19 downto 0);
signal mr_ram_ce_s : std_logic;
signal mr_audio_s : signed(14 downto 0);
signal mr_audio_std_s : std_logic_vector(14 downto 0);
begin
-- CPU
cpu: entity work.T80a
generic map (
mode_g => 0
)
port map (
clock_i => clock_cpu_i,
clock_en_i => '1',
reset_n_i => reset_n_s,
address_o => cpu_addr_s,
data_i => d_to_cpu_s,
data_o => d_from_cpu_s,
wait_n_i => wait_n_s,
int_n_i => int_n_s,
nmi_n_i => bus_nmi_n_i,
m1_n_o => m1_n_s,
mreq_n_o => mreq_n_s,
iorq_n_o => iorq_n_s,
rd_n_o => rd_n_s,
wr_n_o => wr_n_s,
refresh_n_o => rfsh_n_s,
halt_n_o => open,
busrq_n_i => '1',
busak_n_o => open
);
-- IPL ROM
ipl: entity work.ipl_rom
port map (
clk => clock_i,
addr => iplrom_addr_s,
data => d_from_iplrom_s
);
-- VDP
vdp: entity work.vdp18_core
generic map (
video_opt_g => video_opt_g
)
port map (
clock_i => clock_i,
clk_en_10m7_i => clock_vdp_i,
por_i => por_i,
reset_i => reset_i,
csr_n_i => vdp_rd_n_s,
csw_n_i => vdp_wr_n_s,
mode_i => cpu_addr_s(1 downto 0),
int_n_o => vdp_int_n_s,
cd_i => d_from_cpu_s,
cd_o => d_from_vdp_s,
wait_o => vdp_wait_s,
vram_ce_o => vram_ce_o,
vram_oe_o => vram_oe_o,
vram_we_o => vram_we_o,
vram_a_o => vram_addr_o,
vram_d_o => vram_data_o,
vram_d_i => vram_data_i,
vga_en_i => vga_en_s,
scanline_en_i => scanline_en_s,
cnt_hor_o => cnt_hor_o,
cnt_ver_o => cnt_ver_o,
rgb_r_o => rgb_r_o,
rgb_g_o => rgb_g_o,
rgb_b_o => rgb_b_o,
hsync_n_o => hsync_n_o,
vsync_n_o => vsync_n_o,
ntsc_pal_i => ntsc_pal_s,
vertfreq_csw_o => vertfreq_csw_s,
vertfreq_d_o => vertfreq_d_s
);
-- PSG
psg: entity work.YM2149
port map (
clock_i => clock_i,
clock_en_i => clock_psg_en_i, -- clock enable 3.57 MHz
reset_i => reset_i,
sel_n_i => '0', -- no division (clock = 3.57)
ayymmode_i => '0',
-- data bus
data_i => d_from_cpu_s,
data_o => d_from_psg_s,
-- control
a9_l_i => '0',
a8_i => '1',
bdir_i => psg_bdir_s,
bc1_i => psg_bc1_s,
bc2_i => '1',
-- I/O ports
port_a_i => psg_port_a_s,
port_b_o => psg_port_b_s,
-- audio channels out
audio_ch_a_o => open,
audio_ch_b_o => open,
audio_ch_c_o => open,
audio_ch_mix_o => audio_psg_o
);
-- PIO (82C55)
pio: entity work.PIO
port map (
reset_i => reset_i,
ipl_en_i => ipl_en_s,
addr_i => cpu_addr_s(1 downto 0),
data_i => d_from_cpu_s,
data_o => d_from_pio_s,
has_data_o => pio_hd_s,
cs_i => pio_cs_s,
rd_i => pio_rd_s,
wr_i => pio_wr_s,
port_a_o => pio_port_a_s,
port_b_i => cols_i,
port_c_o => pio_port_c_s
);
-- Slot expander prim slot 1
exp1: entity work.exp_slot
port map (
reset_i => reset_i,
ipl_en_i => '0',
addr_i => cpu_addr_s,
data_i => d_from_cpu_s,
data_o => d_from_exp1_s,
has_data_o => exp1_has_data_s,
sltsl_n_i => prim_slot_n_s(1),
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
expsltsl_n_o => slot1_exp_n_s
);
-- Slot expander prim slot 3
exp3: entity work.exp_slot
port map (
reset_i => reset_i,
ipl_en_i => ipl_en_s,
addr_i => cpu_addr_s,
data_i => d_from_cpu_s,
data_o => d_from_exp3_s,
has_data_o => exp3_has_data_s,
sltsl_n_i => prim_slot_n_s(3),
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
expsltsl_n_o => slot3_exp_n_s
);
-- Memory configuration
hw_memsize_s(7) <= use_rom_in_ram_s;
hw_memsize_s(6 downto 3) <= "0000";
hw_memsize_s(2 downto 0) <= "000" when ramsize_g = 512 else
"010" when ramsize_g = 2048 else
"100";
-- Switched I/O ports
swiop: entity work.swioports
port map (
por_i => por_i,
reset_i => reset_i,
clock_i => clock_i,
clock_cpu_i => clock_cpu_i,
addr_i => cpu_addr_s(7 downto 0),
cs_i => niorq_s,
rd_i => nrd_s,
wr_i => nwr_s,
data_i => d_from_cpu_s,
data_o => d_from_swp_s,
has_data_o => swp_hd_s,
--
hw_id_i => std_logic_vector(to_unsigned(hw_id_g, 8)),
hw_txt_i => hw_txt_g,
hw_version_i => hw_version_g,
hw_memsize_i => hw_memsize_s,
hw_hashwds_i => hw_hashwds_g,
nextor_en_i => opt_nextor_i,
mr_type_i => opt_mr_type_i,
vga_on_i => opt_vga_on_i,
turbo_on_k_i => turbo_on_k_i,
vga_on_k_i => vga_on_k_i,
scanline_on_k_i=> scanline_on_k_i,
vertfreq_on_k_i=> vertfreq_on_k_i,
vertfreq_csw_i => vertfreq_csw_s,
vertfreq_d_i => vertfreq_d_s,
keyb_valid_i => keyb_valid_i,
keyb_data_i => keyb_data_i,
--
nextor_en_o => nextor_en_s,
mr_type_o => mr_type_s,
turbo_on_o => turbo_on_s,
reload_o => reload_o,
softreset_o => softreset_s,
vga_en_o => vga_en_s,
scanline_en_o => scanline_en_s,
ntsc_pal_o => ntsc_pal_s,
keymap_addr_o => keymap_addr_o,
keymap_data_o => keymap_data_o,
keymap_we_o => keymap_we_o,
volumes_o => volumes_o
);
-- SPI
spi: entity work.spi
port map (
clock_i => clock_cpu_i,
reset_i => reset_i,
addr_i => cpu_addr_s(0),
cs_i => spi_cs_s,
wr_i => nwr_s,
rd_i => nrd_s,
data_i => d_from_cpu_s,
data_o => d_from_spi_s,
has_data_o => spi_hd_s,
-- SD card interface
spi_cs_n_o(2) => flspi_cs_n_o,
spi_cs_n_o(1) => spi2_cs_n_o,
spi_cs_n_o(0) => spi_cs_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
sd_wp_i => sd_wp_i,
sd_pres_n_i => sd_pres_n_i
);
-- ROM Nextor control
nxt: entity work.romnextor
port map (
reset_i => reset_i,
clock_i => clock_cpu_i,
enable_i => nextor_en_s,
addr_i => cpu_addr_s,
data_i => d_from_cpu_s,
sltsl_n_i => slot3_exp_n_s(2),
rd_n_i => rd_n_s,
wr_n_i => wr_n_s,
--
rom_cs_o => nxt_rom_cs_s,
rom_wr_o => nxt_rom_wr_s,
rom_page_o => nxt_rom_page_s
);
-- ESCCI
escci: entity work.escci
port map (
clock_i => clock_i,
clock_en_i => clock_psg_en_i,
reset_i => reset_i,
--
addr_i => cpu_addr_s,
data_i => d_from_cpu_s,
data_o => d_from_mram_s,
cs_i => mram_cs_s,
rd_i => nrd_s,
wr_i => nwr_s,
--
ram_addr_o => mr_ram_addr_s,
ram_data_i => ram_data_i,
ram_ce_o => mr_ram_ce_s,
ram_oe_o => open,
ram_we_o => open,
--
map_type_i => mr_type_s, -- "-0" : SCC+, "01" : ASC8K, "11" : ASC16K
-- Audio Out
wave_o => audio_scc_o
);
-- Glue
softreset_o <= softreset_s;
-- por_n_s <= not por_i;
reset_n_s <= not reset_i;
nrd_s <= not rd_n_s;
nwr_s <= not wr_n_s;
niorq_s <= not iorq_n_s;
ipl_en_s <= not iplram_bw_s;
beep_o <= pio_beep_a;
rows_o <= pio_rows_coded_a;
caps_en_o <= not pio_caps_a;
turbo_on_o <= turbo_on_s;
-- K7 and Joystick
k7_motor_o <= pio_motoron_a;
k7_audio_o <= pio_k7out_a;
psg_port_a_s <= k7_audio_i & '0' & joy_sigs_s; -- bit 6: Keyboard layout (1=JIS, 0=ANSI)
joy_sigs_s <= joy1_btn2_i & joy1_btn1_i & joy1_right_i & joy1_left_i & joy1_down_i & joy1_up_i when joy_sel_a = '0' else
joy2_btn2_i & joy2_btn1_i & joy2_right_i & joy2_left_i & joy2_down_i & joy2_up_i;
joy1_btn1_o <= '0' when psg_port_b_s(0) = '0' else 'Z';
joy1_btn2_o <= '0' when psg_port_b_s(1) = '0' else 'Z';
joy2_btn1_o <= '0' when psg_port_b_s(2) = '0' else 'Z';
joy2_btn2_o <= '0' when psg_port_b_s(3) = '0' else 'Z';
joy1_out_o <= psg_port_b_s(4);
joy2_out_o <= psg_port_b_s(5);
-- M1 Wait-state
process (mreq_n_s, rfsh_n_s, clock_cpu_i)
begin
if mreq_n_s = '1' or rfsh_n_s = '0' then
m1_wait_ff_s <= "10";
elsif rising_edge(clock_cpu_i) then
if turbo_on_s = '0' then
m1_wait_ff_s(1) <= m1_n_s or m1_wait_ff_s(0);
m1_wait_ff_s(0) <= not (m1_n_s or m1_wait_ff_s(0));
else
m1_wait_ff_s <= "10";
end if;
end if;
end process;
m1_wait_n_s <= m1_wait_ff_s(1);
-- Address decoding
io_access_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' else '0';
io_read_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' and rd_n_s = '0' else '0';
io_write_s <= '1' when iorq_n_s = '0' and m1_n_s = '1' and wr_n_s = '0' else '0';
-- I/O
vdp_wr_n_s <= '0' when io_write_s = '1' and cpu_addr_s(7 downto 2) = "100110" else '1'; -- VDP write => 98-9B
vdp_rd_n_s <= '0' when io_read_s = '1' and cpu_addr_s(7 downto 2) = "100110" else '1'; -- VDP read => 98-9B
spi_cs_s <= '1' when io_access_s = '1' and cpu_addr_s(7 downto 1) = "1001111" else '0'; -- SPI => 9E-9F
psg_cs_s <= '1' when io_access_s = '1' and cpu_addr_s(7 downto 2) = "101000" else '0'; -- PSG => A0-A3
pio_cs_s <= '1' when io_access_s = '1' and cpu_addr_s(7 downto 2) = "101010" else '0'; -- PPI => A8-AB
mp_cs_s <= '1' when io_access_s = '1' and cpu_addr_s(7 downto 2) = "111111" else '0'; -- Mapper => FC-FF
-- PSG
psg_bc1_s <= '1' when psg_cs_s = '1' and cpu_addr_s(0) = '0' else '0';
psg_bdir_s <= '1' when psg_cs_s = '1' and wr_n_s = '0' else '0';
-- PIO
pio_rd_s <= not rd_n_s;
pio_wr_s <= not wr_n_s;
-- ESCCI
mram_cs_s <= '1' when prim_slot_n_s(2) = '0' else '0'; -- slot 2
-- MUX data CPU
d_to_cpu_s <=
-- Memory
d_from_iplrom_s when iplrom_cs_s = '1' else
ram_data_i when iplram_cs_s = '1' else
rom_data_i when brom_cs_s = '1' else
ram_data_i when extrom_cs_s = '1' else
ram_data_i when xb2rom_cs_s = '1' else
ram_data_i when ram_cs_s = '1' else
ram_data_i when nxt_rom_cs_s = '1' else
d_from_exp1_s when exp1_has_data_s = '1' else
d_from_exp3_s when exp3_has_data_s = '1' else
d_from_mram_s when mram_cs_s = '1' else
-- I/O
d_from_vdp_s when vdp_rd_n_s = '0' else
d_from_psg_s when psg_cs_s = '1' else
d_from_pio_s when pio_hd_s = '1' else
d_from_spi_s when spi_hd_s = '1' else
d_from_mp_s when mp_cs_s = '1' else
d_from_swp_s when swp_hd_s = '1' else
--
bus_data_i;
-- Slot control
with cpu_addr_s(15 downto 14) select pslot_s <=
pio_port_a_s(7 downto 6) when "11",
pio_port_a_s(5 downto 4) when "10",
pio_port_a_s(3 downto 2) when "01",
pio_port_a_s(1 downto 0) when others;
prim_slot_n_s(0) <= '0' when mreq_n_s = '0' and rfsh_n_s = '1' and pslot_s = "00" else '1';
prim_slot_n_s(1) <= '0' when mreq_n_s = '0' and rfsh_n_s = '1' and pslot_s = "01" else '1';
prim_slot_n_s(2) <= '0' when mreq_n_s = '0' and rfsh_n_s = '1' and pslot_s = "10" else '1';
prim_slot_n_s(3) <= '0' when mreq_n_s = '0' and rfsh_n_s = '1' and pslot_s = "11" else '1';
-- IPL
ipl_cs_s <= '1' when slot3_exp_n_s(3) = '0' else '0';
-- ROMs
iplrom_cs_s <= '1' when slot3_exp_n_s(3) = '0' and cpu_addr_s(15 downto 13) = "000" else '0'; -- 0000-1FFF
iplrom_addr_s <= cpu_addr_s(12 downto 0);
brom_cs_s <= '1' when prim_slot_n_s(0) = '0' and cpu_addr_s(15) = '0' else '0'; -- 0000-7FFF
extrom_cs_s <= '1' when slot3_exp_n_s(0) = '0' and cpu_addr_s(15 downto 14) = "01" else '0'; -- 4000-7FFF
xb2rom_cs_s <= '1' when slot1_exp_n_s(0) = '0' and cpu_addr_s(15 downto 14) = "01" else '0'; -- 4000-7FFF
-- Mapper
process(reset_i, clock_cpu_i)
begin
if reset_i = '1' then
mp_bank0_s <= "00000011";
mp_bank1_s <= "00000010";
mp_bank2_s <= "00000001";
mp_bank3_s <= "00000000";
elsif falling_edge(clock_cpu_i) then
if mp_cs_s = '1' and wr_n_s = '0' then
case cpu_addr_s(1 downto 0) is
when "00" => mp_bank0_s <= d_from_cpu_s;
when "01" => mp_bank1_s <= d_from_cpu_s;
when "10" => mp_bank2_s <= d_from_cpu_s;
when others => mp_bank3_s <= d_from_cpu_s;
end case;
end if;
end if;
end process;
mp_invmask_s <= not mp_mask_s;
-- Mapper read
d_from_mp_s <= mp_bank0_s or mp_invmask_s when cpu_addr_s(1 downto 0) = "00" else
mp_bank1_s or mp_invmask_s when cpu_addr_s(1 downto 0) = "01" else
mp_bank2_s or mp_invmask_s when cpu_addr_s(1 downto 0) = "10" else
mp_bank3_s or mp_invmask_s;
-- Mapper page
mp_page_s <= mp_bank0_s and mp_mask_s when cpu_addr_s(15 downto 14) = "00" else
mp_bank1_s and mp_mask_s when cpu_addr_s(15 downto 14) = "01" else
mp_bank2_s and mp_mask_s when cpu_addr_s(15 downto 14) = "10" else
mp_bank3_s and mp_mask_s;
-- RAM
ram_data_o <= d_from_cpu_s;
ram_ce_o <= ram_cs_s or iplram_cs_s or nxt_rom_cs_s or mr_ram_ce_s or
(use_rom_in_ram_s and brom_cs_s) or
(use_rom_in_ram_s and extrom_cs_s) or
(use_rom_in_ram_s and xb2rom_cs_s);
ram_oe_o <= not rd_n_s;
ram_we_o <= '1' when wr_n_s = '0' and (ram_cs_s = '1' or mr_ram_ce_s = '1') else
'1' when wr_n_s = '0' and iplram_cs_s = '1' and iplram_bw_s = '0' else
'1' when wr_n_s = '0' and nxt_rom_wr_s = '1' else -- Nextor extra RAM
'0';
ram_cs_s <= '1' when slot3_exp_n_s(1) = '0' else '0';
iplram_cs_s <= '1' when slot3_exp_n_s(3) = '0' and cpu_addr_s(15 downto 14) /= "00" else '0';
-- IPLRAM block write
process (por_i, clock_cpu_i)
begin
if por_i = '1' then
iplram_bw_s <= '0';
elsif falling_edge(clock_cpu_i) then
if pio_cs_s = '1' and wr_n_s = '0' then
iplram_bw_s <= '1';
end if;
end if;
end process;
use_rom_in_ram_s <= '1' when hw_id_g = 4 or hw_id_g = 5 or ramsize_g /= 512 else '0';
memctl: entity work.memoryctl
generic map (
ramsize_g => ramsize_g
)
port map (
cpu_addr_i => cpu_addr_s,
use_rom_in_ram_i => use_rom_in_ram_s,
--
rom_cs_i => brom_cs_s,
extrom_cs_i => extrom_cs_s,
xb2rom_cs_i => xb2rom_cs_s,
nxt_rom_cs_i => nxt_rom_cs_s,
nxt_rom_page_i => nxt_rom_page_s,
ipl_cs_i => ipl_cs_s,
ipl_rampage_i => ipl_rampage_s,
mr_ram_cs_i => mr_ram_ce_s,
mr_ram_addr_i => mr_ram_addr_s,
ram_cs_i => ram_cs_s,
ram_page_i => mp_page_s,
--
ram_addr_o => ram_addr_o,
mapper_mask_o => mp_mask_s
);
-- IPL rampage write
process (reset_i, clock_cpu_i)
begin
if reset_i = '1' then
ipl_rampage_s <= (others => '1');
elsif falling_edge(clock_cpu_i) then
if mreq_n_s = '0' and wr_n_s = '0' and ipl_cs_s = '1' and
(cpu_addr_s = X"3FFE" or cpu_addr_s = X"3FFF") then
if cpu_addr_s(0) = '0' then
ipl_rampage_s(7 downto 0) <= d_from_cpu_s;
else
ipl_rampage_s(8) <= d_from_cpu_s(0);
end if;
end if;
end if;
end process;
-- ROM
rom_addr_o <= cpu_addr_s(14 downto 0);
rom_ce_o <= brom_cs_s;
rom_oe_o <= not rd_n_s;
-- BUS
bus_addr_o <= cpu_addr_s;
bus_data_o <= d_from_cpu_s;
bus_rd_n_o <= rd_n_s;
bus_wr_n_o <= wr_n_s;
bus_m1_n_o <= m1_n_s;
bus_iorq_n_o <= iorq_n_s;
bus_mreq_n_o <= mreq_n_s;
bus_sltsl1_n_o <= slot1_exp_n_s(1);
bus_sltsl2_n_o <= slot1_exp_n_s(2);
wait_n_s <= m1_wait_n_s and bus_wait_n_i and not vdp_wait_s;
int_n_s <= bus_int_n_i and vdp_int_n_s;
vga_en_o <= vga_en_s;
scanline_en_o <= scanline_en_s;
-- Debug
D_slots_o <= pio_port_a_s;
D_wait_o <= vdp_wait_s;
D_ipl_en_o <= ipl_en_s;
end architecture;
|
gpl-3.0
|
e06b2f7c26cb1bab6397941e93d6eb2e
| 0.562584 | 2.182917 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/cpu/t80.vhd
| 2 | 40,338 |
--
-- Z80 compatible microprocessor core
--
-- Version : 0249
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
-- 0248 : add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--
-- 0249 : add undocumented XY-Flags for CPI/CPD by TobiFlex 22.07.2012
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal ALU_cpi_r : std_logic;
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal ALU_cpi : std_logic;
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
ALU_cpi => ALU_cpi,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_cpi => ALU_cpi_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
ALU_cpi_r <= '0';
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
ALU_cpi_r <= '0';
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_cpi_r <= ALU_cpi;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 and Auto_Wait_t1 = '0' then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusB <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if T_Res = '1' then
Auto_Wait_t1 <= '0';
else
Auto_Wait_t1 <= Auto_Wait or IORQ_i;
end if;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' and IntCycle = '0' then -- by Fabio: Fix IM2 timing
M1_n <= '1';
end if;
if MCycle = "001" and TState = 3 and Wait_n = '1' and IntCycle = '1' then -- by Fabio: Fix IM2 timing
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
gpl-3.0
|
7f52427b2955c6aa26264c3d9b51c204
| 0.399747 | 4.174912 | false | false | false | false |
VectorBlox/risc-v
|
ip/idram/src/idram_behav.vhd
| 1 | 2,845 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.idram_utils.all;
use work.idram_components.all;
entity idram_behav is
generic (
RAM_DEPTH : integer := 1024;
RAM_WIDTH : integer := 32;
WRITE_FIRST : boolean := false
);
port (
clk : in std_logic;
instr_address : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
instr_data_in : in std_logic_vector(RAM_WIDTH-1 downto 0);
instr_we : in std_logic;
instr_en : in std_logic;
instr_be : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
instr_readdata : out std_logic_vector(RAM_WIDTH-1 downto 0);
data_address : in std_logic_vector(log2(RAM_DEPTH)-1 downto 0);
data_data_in : in std_logic_vector(RAM_WIDTH-1 downto 0);
data_we : in std_logic;
data_en : in std_logic;
data_be : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
data_readdata : out std_logic_vector(RAM_WIDTH-1 downto 0)
);
end entity idram_behav;
architecture rtl of idram_behav is
type data_vector is array (natural range <>) of std_logic_vector(8-1 downto 0);
signal wren_a : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal wren_b : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal en_a : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal en_b : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal data_a : data_vector((RAM_WIDTH/8)-1 downto 0);
signal data_b : data_vector((RAM_WIDTH/8)-1 downto 0);
signal readdata_a : data_vector((RAM_WIDTH/8)-1 downto 0);
signal readdata_b : data_vector((RAM_WIDTH/8)-1 downto 0);
begin
idram_gen : for gbyte in (RAM_WIDTH/8)-1 downto 0 generate
wren_a(gbyte) <= instr_we and instr_be(gbyte);
wren_b(gbyte) <= data_we and data_be(gbyte);
en_a(gbyte) <= instr_en and instr_be(gbyte);
en_b(gbyte) <= data_en and data_be(gbyte);
data_a(gbyte) <= instr_data_in(((gbyte+1)*8)-1 downto gbyte*8);
data_b(gbyte) <= data_data_in(((gbyte+1)*8)-1 downto gbyte*8);
tdp_ram : component tdp_ram_behav
generic map (
RAM_DEPTH => RAM_DEPTH,
RAM_WIDTH => 8,
WRITE_FIRST => WRITE_FIRST
)
port map (
address_a => instr_address,
address_b => data_address,
clk => clk,
data_a => data_a(gbyte),
data_b => data_b(gbyte),
wren_a => wren_a(gbyte),
wren_b => wren_b(gbyte),
en_a => en_a(gbyte),
en_b => en_b(gbyte),
readdata_a => readdata_a(gbyte),
readdata_b => readdata_b(gbyte)
);
instr_readdata(((gbyte+1)*8)-1 downto gbyte*8) <= readdata_a(gbyte);
data_readdata(((gbyte+1)*8)-1 downto gbyte*8) <= readdata_b(gbyte);
end generate idram_gen;
end architecture rtl;
|
bsd-3-clause
|
05f02bcaae2cf5820c085bd938c995ca
| 0.595782 | 3.052575 | false | false | false | false |
peteg944/music-fpga
|
LED_Matrix_FPGA_Nexys 3/ipcore_dir/pll/simulation/timing/pll_tb.vhd
| 1 | 7,433 |
-- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
end test;
|
mit
|
dee501601a0188e154ca64daf33c2e7d
| 0.609848 | 4.232916 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/top/pcie/top_ml605.vhd
| 1 | 11,157 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library work;
use work.abb64Package.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic --Reset to PCIe core
);
end entity top;
architecture arch of top is
component bpm_pcie_ml605 is
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE"
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
---- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end component bpm_pcie_ml605;
-- WISHBONE SLAVE interface:
-- Single-Port RAM with Asynchronous Read
--
component WB_MEM is
generic(
AWIDTH : natural range 2 to 29 := 7;
DWIDTH : natural range 8 to 128 := 64
);
port(
CLK_I : in std_logic;
ACK_O : out std_logic;
ADR_I : in std_logic_vector(AWIDTH-1 downto 0);
DAT_I : in std_logic_vector(DWIDTH-1 downto 0);
DAT_O : out std_logic_vector(DWIDTH-1 downto 0);
STB_I : in std_logic;
WE_I : in std_logic
);
end component;
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal ddr_ui_clk : std_logic;
signal pll_clkin : std_logic;
signal pll_clkfbout : std_logic;
signal pll_clkout0 : std_logic;
signal pll_locked : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
signal wbone_mdin : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_mdout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wbone_we : std_logic;
signal wbone_sel : std_logic_vector(0 downto 0);
signal wbone_stb : std_logic;
signal wbone_ack : std_logic;
signal wbone_cyc : std_logic;
signal wbone_rst : std_logic;
begin
bpm_pcie : bpm_pcie_ml605
generic map(
SIMULATION => SIMULATION,
-- ****
-- PCIe core parameters
-- ****
pcieLanes => pcieLanes,
PL_FAST_TRAIN => PL_FAST_TRAIN,
PIPE_SIM_MODE => PIPE_SIM_MODE
)
port map(
--DDR3 memory pins
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cs_n => ddr3_cs_n,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
-- PCIe transceivers
pci_exp_rxp => pci_exp_rxp,
pci_exp_rxn => pci_exp_rxn,
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk_p => ddr_sys_clk_i,
sys_clk_p => sys_clk_p,
sys_clk_n => sys_clk_n,
sys_rst_n => sys_rst_n,
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst => ddr_sys_rst_i,
memc_ui_clk => ddr_ui_clk,
memc_ui_rst => open,
memc_cmd_rdy => open,
memc_cmd_en => '0',
memc_cmd_instr => (others => '0'),
memc_cmd_addr => (others => '0'),
memc_wr_en => '0',
memc_wr_end => '0',
memc_wr_mask => (others => '0'),
memc_wr_data => (others => '0'),
memc_wr_rdy => open,
memc_rd_data => open,
memc_rd_valid => open,
---- memory arbiter interface
memarb_acc_req => '0',
memarb_acc_gnt => open,
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I => wbone_clk,
RST_I => wbone_rst,
ACK_I => wbone_ack,
DAT_I => wbone_mdin,
ADDR_O => wbone_addr(28 downto 0),
DAT_O => wbone_mdout,
WE_O => wbone_we,
STB_O => wbone_stb,
SEL_O => wbone_sel(0),
CYC_O => wbone_cyc,
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o => wbone_rst
);
Wishbone_mem_large: if (SIMULATION = "TRUE") generate
wb_mem_sim :
wb_mem
generic map(
AWIDTH => 16,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(16-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
Wishbone_mem_sample: if (SIMULATION = "FALSE") generate
wb_mem_syn :
wb_mem
generic map(
AWIDTH => 7,
DWIDTH => 64
)
port map(
CLK_I => wbone_clk, --in std_logic;
ACK_O => wbone_ack, --out std_logic;
ADR_I => wbone_addr(7-1 downto 0), --in std_logic_vector(AWIDTH-1 downto 0);
DAT_I => wbone_mdout, --in std_logic_vector(DWIDTH-1 downto 0);
DAT_O => wbone_mdin, --out std_logic_vector(DWIDTH-1 downto 0);
STB_I => wbone_stb, --in std_logic;
WE_I => wbone_we --in std_logic
);
end generate;
--temporary clock assignment
wbone_clk <= ddr_ui_clk;
ddr_inclk_bufgds : IBUFGDS
generic map(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE
)
port map(
O => ddr_sys_clk_i,
I => ddr_sys_clk_p,
IB => ddr_sys_clk_n
);
ddr_sys_rst_i <= wbone_rst;
end architecture;
|
lgpl-3.0
|
33b2db02d711aca001e218a6995d04fb
| 0.562248 | 3.190449 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/testbench/others/rffe/bpm_swap_ctrl/rf_ch_swap_tb.vhd
| 1 | 3,269 |
------------------------------------------------------------------------------
-- Title : RF channels Swapping Testbench
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simulation of rf_ch_swap desing behavior.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-18 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rf_ch_swap_tb is
end rf_ch_swap_tb;
architecture behavior of rf_ch_swap_tb is
-- component Declaration for the Unit Under Test (UUT)
component rf_ch_swap
generic(
g_direct : std_logic_vector(7 downto 0) := "10100101";
g_inverted : std_logic_vector(7 downto 0) := "01011010");
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_swap_i : in std_logic;
mode_i : in std_logic_vector(1 downto 0);
ctrl_o : out std_logic_vector(7 downto 0));
end component;
--inputs
signal clk_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal en_swap_i : std_logic := '0';
signal mode_i : std_logic_vector(1 downto 0) := (others => '0');
--outputs
signal ctrl_o : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 8 ns;
constant en_period : time := 80 ns;
begin
-- instantiate the Unit Under Test (UUT)
uut: rf_ch_swap
port map (
clk_i => clk_i,
rst_i => rst_i,
en_swap_i => en_swap_i,
mode_i => mode_i,
ctrl_o => ctrl_o
);
-- Clock process definitions
p_clock :process
begin
clk_i <= '1';
wait for clk_period/2;
clk_i <= '0';
wait for clk_period/2;
end process;
p_enable :process
begin
en_swap_i <= '1';
wait for en_period/2;
en_swap_i <= '0';
wait for en_period/2;
end process;
-- Stimulus process
p_stim: process
begin
-- hold reset state for 16 ns.
rst_i <= '1';
wait for clk_period*2;
rst_i <= '0';
wait for clk_period*14;
-- insert stimulus here
rst_i <= '0';
mode_i <= "11";
wait for clk_period*44;
-- Another reset period
rst_i <= '1';
wait for clk_period*20;
-- insert stimulus here
rst_i <= '0';
mode_i <= "11";
wait for clk_period*22;
mode_i <= "01";
wait for clk_period*30;
mode_i <= "11";
wait for clk_period*22;
-- Another reset period
rst_i <= '1';
wait for clk_period*14;
-- insert stimulus here
rst_i <= '0';
wait for clk_period*44;
mode_i <= "10";
wait for clk_period*5;
wait;
end process;
end;
|
lgpl-3.0
|
beac70d4a6f02f2e2821aed4f494d33e
| 0.470174 | 3.814469 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd
| 1 | 8,664 |
-------------------------------------------------------------------------------------
-- FILE NAME : fmc150_stellar_cmd.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc150_stellar_cmd
-- architecture - fmc150_stellar_cmd_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity fmc150_stellar_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end entity fmc150_stellar_cmd;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture arch_fmc150_stellar_cmd of fmc150_stellar_cmd is
-----------------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
-----------------------------------------------------------------------------------
-- Dignal declarations
-----------------------------------------------------------------------------------
signal register_wr : std_logic;
signal register_rd : std_logic;
signal out_cmd_val_sig : std_logic;
signal in_reg_addr_sig : std_logic_vector(27 downto 0);
signal mbx_in_val_sig : std_logic;
signal mbx_received : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component;
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr,
inbusy => open,
pulseout => out_reg_val
);
p2p1: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_rd,
inbusy => open,
pulseout => in_reg_req
);
p2p2: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd,
rst => reset,
pulsein => in_reg_val,
inbusy => open,
pulseout => out_cmd_val_sig
);
p2p3: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => mbx_in_val,
inbusy => open,
pulseout => mbx_in_val_sig
);
-----------------------------------------------------------------------------------
-- Synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process (reset, clk_cmd)
begin
if (reset = '1') then
in_reg_addr_sig <= (others => '0');
register_rd <= '0';
mbx_received <= '0';
out_cmd <= (others => '0');
out_cmd_val <= '0';
elsif (clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig = '1' and mbx_in_val_sig = '1') then
mbx_received <= '1';
elsif( mbx_received = '1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig = '1') then
out_cmd(31 downto 0) <= in_reg;
out_cmd(59 downto 32) <= in_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_RD_ACK;
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= start_addr;
out_cmd(63 downto 60) <= (others=>'0');
else
out_cmd(63 downto 0) <= (others=>'0');
end if;
if (out_cmd_val_sig = '1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(reset, clk_cmd)
begin
if (reset = '1') then
out_reg_addr <= (others => '0');
out_reg <= (others => '0');
register_wr <= '0';
elsif(clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
out_reg_addr <= in_cmd(59 downto 32) - start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end architecture arch_fmc150_stellar_cmd;
|
lgpl-3.0
|
c194949ea2ef2911c37eb17a23ac7d2b
| 0.433518 | 4.024152 | false | false | false | false |
VectorBlox/risc-v
|
ip/orca/hdl/alu.vhd
| 1 | 29,702 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.utils.all;
use work.constants_pkg.all;
use work.constants_pkg.all;
entity arithmetic_unit is
generic (
REGISTER_SIZE : positive range 32 to 32;
SIGN_EXTENSION_SIZE : positive;
POWER_OPTIMIZED : boolean;
MULTIPLY_ENABLE : boolean;
DIVIDE_ENABLE : boolean;
SHIFTER_MAX_CYCLES : positive range 1 to 32;
ENABLE_EXCEPTIONS : boolean;
FAMILY : string
);
port (
clk : in std_logic;
to_alu_valid : in std_logic;
to_alu_rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
to_alu_rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
from_alu_ready : out std_logic;
from_alu_illegal : out std_logic;
vcp_source_valid : in std_logic;
vcp_select : in std_logic;
from_execute_ready : in std_logic;
instruction : in std_logic_vector(31 downto 0);
sign_extension : in std_logic_vector(SIGN_EXTENSION_SIZE-1 downto 0);
current_pc : in unsigned(REGISTER_SIZE-1 downto 0);
from_alu_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_alu_valid : out std_logic
);
end entity arithmetic_unit;
architecture rtl of arithmetic_unit is
constant SHIFTER_USE_MULTIPLIER : boolean := MULTIPLY_ENABLE;
alias func3 : std_logic_vector(2 downto 0) is instruction(INSTR_FUNC3'range);
alias func7 : std_logic_vector(6 downto 0) is instruction(INSTR_FUNC7'range);
alias opcode : std_logic_vector(6 downto 0) is instruction(INSTR_OPCODE'range);
signal data1 : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal data2 : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal source_valid : std_logic;
--Submodules: LUI, AUIPC, add/sub/logic, shift, mul, div
signal lui_select : std_logic;
signal auipc_select : std_logic;
signal addsub_logic_select : std_logic;
signal shift_select : std_logic;
signal from_shift_ready : std_logic;
signal from_shift_valid : std_logic;
signal mul_select : std_logic;
signal from_mul_ready : std_logic;
signal from_mul_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal from_mul_valid : std_logic;
signal div_select : std_logic;
signal from_div_ready : std_logic;
signal from_div_valid : std_logic;
signal from_div_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal from_base_alu_valid : std_logic;
signal from_base_alu_data : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal shift_amt : unsigned(log2(REGISTER_SIZE)-1 downto 0);
signal shift_value : signed(REGISTER_SIZE downto 0);
signal lshifted_result : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal rshifted_result : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal upper_immediate : signed(REGISTER_SIZE-1 downto 0);
signal mul_dest : std_logic_vector((REGISTER_SIZE+1)*2-1 downto 0);
signal mul_dest_shift_by_zero : std_logic;
signal mul_dest_valid : std_logic;
component shifter is
generic (
REGISTER_SIZE : positive range 32 to 32;
SHIFTER_MAX_CYCLES : positive range 1 to 32
);
port (
clk : in std_logic;
shift_amt : in unsigned(log2(REGISTER_SIZE)-1 downto 0);
shift_value : in signed(REGISTER_SIZE downto 0);
lshifted_result : out std_logic_vector(REGISTER_SIZE-1 downto 0);
rshifted_result : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_shift_valid : out std_logic;
shift_enable : in std_logic
);
end component shifter;
component divider is
generic (
REGISTER_SIZE : positive range 32 to 32
);
port (
clk : in std_logic;
div_enable : in std_logic;
div_unsigned : in std_logic;
rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
quotient : out std_logic_vector(REGISTER_SIZE-1 downto 0);
remainder : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_div_valid : out std_logic
);
end component;
--operand creation signals
alias not_immediate : std_logic is instruction(5);
signal immediate_value : signed(REGISTER_SIZE-1 downto 0);
signal shifter_multiply : signed(REGISTER_SIZE downto 0);
signal m_op1_mask : std_logic;
signal m_op2_mask : std_logic;
signal m_op1 : signed(REGISTER_SIZE downto 0);
signal m_op2 : signed(REGISTER_SIZE downto 0);
signal is_add : boolean;
signal op1 : signed(REGISTER_SIZE downto 0);
signal op2 : signed(REGISTER_SIZE downto 0);
signal op1_msb : std_logic;
signal op2_msb : std_logic;
signal addsub : signed(REGISTER_SIZE downto 0);
signal slt_result : std_logic_vector(REGISTER_SIZE-1 downto 0);
begin
--Decode instruction to select submodule. All paths must decode to exactly
--one submodule.
--ASSUMES only ALU_OP | VCP32_OP | VCP64_OP | ALUI_OP | LUI_OP | AUIPC_OP for opcode.
process (opcode, func3, func7, vcp_select) is
begin
lui_select <= '0';
auipc_select <= '0';
shift_select <= '0';
addsub_logic_select <= '0';
div_select <= '0';
mul_select <= '0';
from_alu_illegal <= '0';
--Top bit and bottom two bits are identical for all cases we care about
case opcode(5 downto 2) is
when "1101" => --LUI_OP(5 downto 2)
lui_select <= '1';
when "0101" => --AUIPC_OP(5 downto 2)
auipc_select <= '1';
when "0100" => --ALUI_OP(5 downto 2)
case func3 is
when SLL_FUNC3 =>
if ENABLE_EXCEPTIONS then
if func7 = SHIFT_LOGIC_FUNC7 then
shift_select <= '1';
else
from_alu_illegal <= '1';
end if;
else
shift_select <= '1';
end if;
when SR_FUNC3 =>
if ENABLE_EXCEPTIONS then
case func7 is
when SHIFT_LOGIC_FUNC7 | SHIFT_ARITH_FUNC7 =>
shift_select <= '1';
when others =>
from_alu_illegal <= '1';
end case;
else
shift_select <= '1';
end if;
when others =>
addsub_logic_select <= '1';
end case;
when others => --ALU_OP or from VCP
if (MULTIPLY_ENABLE and func3(2) = '0' and
func7(5) = MUL_FUNC7(5) and func7(0) = MUL_FUNC7(0) and
(vcp_select = '1' or (func7(6) = MUL_FUNC7(6) and func7(4 downto 1) = MUL_FUNC7(4 downto 1)))) then
mul_select <= '1';
elsif (ENABLE_EXCEPTIONS and func3(2) = '0' and
func7(5) = MUL_FUNC7(5) and func7(0) = MUL_FUNC7(0) and
(vcp_select = '1' or (func7(6) = MUL_FUNC7(6) and func7(4 downto 1) = MUL_FUNC7(4 downto 1)))) then
from_alu_illegal <= '1';
elsif (DIVIDE_ENABLE and func3(2) = '1' and
func7(5) = MUL_FUNC7(5) and func7(0) = MUL_FUNC7(0) and
(vcp_select = '1' or (func7(6) = MUL_FUNC7(6) and func7(4 downto 1) = MUL_FUNC7(4 downto 1)))) then
div_select <= '1';
elsif (ENABLE_EXCEPTIONS and func3(2) = '1' and
func7(5) = MUL_FUNC7(5) and func7(0) = MUL_FUNC7(0) and
(vcp_select = '1' or (func7(6) = MUL_FUNC7(6) and func7(4 downto 1) = MUL_FUNC7(4 downto 1)))) then
from_alu_illegal <= '1';
else
case func3 is
when SLL_FUNC3 =>
if ENABLE_EXCEPTIONS then
if func7 = SHIFT_LOGIC_FUNC7 then
shift_select <= '1';
else
if vcp_select = '1' then
shift_select <= '1';
else
from_alu_illegal <= '1';
end if;
end if;
else
shift_select <= '1';
end if;
when SR_FUNC3 =>
if ENABLE_EXCEPTIONS then
case func7 is
when SHIFT_LOGIC_FUNC7 | SHIFT_ARITH_FUNC7 =>
shift_select <= '1';
when others =>
if vcp_select = '1' then
shift_select <= '1';
else
from_alu_illegal <= '1';
end if;
end case;
else
shift_select <= '1';
end if;
when ADDSUB_FUNC3 =>
if ENABLE_EXCEPTIONS then
case func7 is
when ADDSUB_ADD_FUNC7 | ADDSUB_SUB_FUNC7 =>
addsub_logic_select <= '1';
when others =>
if vcp_select = '1' then
addsub_logic_select <= '1';
else
from_alu_illegal <= '1';
end if;
end case;
else
addsub_logic_select <= '1';
end if;
when others => --SLT_FUNC3 | SLTU_FUNC3 | XOR_FUNC3 | OR_FUNC3 | AND_FUNC3
if ENABLE_EXCEPTIONS then
if func7 = ALU_FUNC7 then
addsub_logic_select <= '1';
else
if vcp_select = '1' then
addsub_logic_select <= '1';
else
from_alu_illegal <= '1';
end if;
end if;
else
addsub_logic_select <= '1';
end if;
end case;
end if;
end case;
end process;
immediate_value <= signed(sign_extension(REGISTER_SIZE-OP_IMM_IMMEDIATE_SIZE-1 downto 0) &
instruction(31 downto 20));
data1 <= (others => '0') when source_valid = '0' and POWER_OPTIMIZED else
to_alu_rs1_data;
data2 <= (others => '0') when source_valid = '0' and POWER_OPTIMIZED else
to_alu_rs2_data when not_immediate = '1' else std_logic_vector(immediate_value);
shift_amt <= unsigned(data2(log2(REGISTER_SIZE)-1 downto 0)) when not SHIFTER_USE_MULTIPLIER else
unsigned(data2(log2(REGISTER_SIZE)-1 downto 0)) when func3(2) = '0'else
unsigned(-signed(data2(log2(REGISTER_SIZE)-1 downto 0)));
shift_value <= signed((instruction(30) and to_alu_rs1_data(to_alu_rs1_data'left)) & to_alu_rs1_data);
is_add <= func3 = ADDSUB_FUNC3 when instruction(5) = '0' else
func3 = ADDSUB_FUNC3 and instruction(30) = '0';
--Sign extend; only matters for SLT{I}/SLT{I}U
op1_msb <= data1(data1'left) when instruction(12) = '0' else '0';
op2_msb <= data2(data2'left) when instruction(12) = '0' else '0';
op1 <= signed(op1_msb & data1);
op2 <= signed(op2_msb & data2);
addsub <= op1 + op2 when is_add else op1 - op2;
m_op1_mask <= '0' when instruction(13 downto 12) = "11" else '1';
m_op2_mask <= not instruction(13);
m_op1 <= signed((m_op1_mask and to_alu_rs1_data(data1'left)) & data1);
m_op2 <= signed((m_op2_mask and to_alu_rs2_data(data2'left)) & data2);
source_valid <= vcp_source_valid when vcp_select = '1' else
to_alu_valid;
from_shift_ready <= from_shift_valid or (not shift_select);
shift_using_multiplier_gen : if SHIFTER_USE_MULTIPLIER generate
assert MULTIPLY_ENABLE report
"Error; multiplier must be enabled when SHIFTER_USE_MULTIPLIER is true"
severity failure;
shift_mul_gen : for gbit in shifter_multiply'left-1 downto 0 generate
shifter_multiply(gbit) <= '1' when std_logic_vector(shift_amt) = std_logic_vector(to_unsigned(gbit, shift_amt'length)) else '0';
end generate shift_mul_gen;
shifter_multiply(shifter_multiply'left) <= '0';
process(clk) is
begin
if rising_edge(clk) then
lshifted_result <= mul_dest(REGISTER_SIZE-1 downto 0);
rshifted_result <= mul_dest(REGISTER_SIZE*2-1 downto REGISTER_SIZE);
if mul_dest_shift_by_zero = '1' then
rshifted_result <= mul_dest(REGISTER_SIZE-1 downto 0);
end if;
from_shift_valid <= mul_dest_valid and shift_select;
if from_execute_ready = '1' then
from_shift_valid <= '0';
end if;
end if;
end process;
end generate shift_using_multiplier_gen;
shift_using_shifter_gen : if not SHIFTER_USE_MULTIPLIER generate
signal shift_enable : std_logic;
begin
shift_enable <= source_valid and shift_select;
sh : shifter
generic map (
REGiSTER_SIZE => REGISTER_SIZE,
SHIFTER_MAX_CYCLES => SHIFTER_MAX_CYCLES
)
port map (
clk => clk,
shift_amt => shift_amt,
shift_value => shift_value,
lshifted_result => lshifted_result,
rshifted_result => rshifted_result,
from_shift_valid => from_shift_valid,
shift_enable => shift_enable
);
end generate shift_using_shifter_gen;
slt_result(slt_result'left downto 1) <= (others => '0');
slt_result(0) <= addsub(addsub'left);
upper_immediate(31 downto 12) <= signed(instruction(31 downto 12));
upper_immediate(11 downto 0) <= (others => '0');
--Base ALU (Add/sub, logical ops, shifts)
with func3 select
from_base_alu_data <=
data1 and data2 when AND_FUNC3,
data1 or data2 when OR_FUNC3,
rshifted_result when SR_FUNC3,
data1 xor data2 when XOR_FUNC3,
slt_result when SLT_FUNC3 | SLTU_FUNC3,
lshifted_result when SLL_FUNC3,
std_logic_vector(addsub(REGISTER_SIZE-1 downto 0)) when others;
from_base_alu_valid <=
source_valid when addsub_logic_select = '1' else
from_shift_valid;
--Mux in and register final result
process(clk) is
begin
if rising_edge(clk) then
if lui_select = '1' then
from_alu_data <= std_logic_vector(upper_immediate);
from_alu_valid <= source_valid;
elsif auipc_select = '1' then
from_alu_data <= std_logic_vector(upper_immediate + signed(current_pc));
from_alu_valid <= source_valid;
elsif div_select = '1' then
from_alu_data <= from_div_data;
from_alu_valid <= from_div_valid;
elsif mul_select = '1' then
from_alu_data <= from_mul_data;
from_alu_valid <= from_mul_valid;
else
from_alu_data <= from_base_alu_data;
from_alu_valid <= from_base_alu_valid;
end if;
end if;
end process;
mul_gen : if MULTIPLY_ENABLE generate
signal mul_enable : std_logic;
signal mul_srca : signed(REGISTER_SIZE downto 0);
signal mul_srcb : signed(REGISTER_SIZE downto 0);
signal mul_src_valid : std_logic;
signal mul_a : signed(mul_srca'range);
signal mul_b : signed(mul_srcb'range);
signal mul_ab_shift_by_zero : std_logic;
signal mul_ab_valid : std_logic;
begin
mul_enable <= source_valid and (mul_select or shift_select) when SHIFTER_USE_MULTIPLIER else
source_valid and mul_select;
from_mul_ready <= mul_dest_valid or (not mul_select);
mul_srca <= m_op1 when instruction(25) = '1' or (not SHIFTER_USE_MULTIPLIER) else shifter_multiply;
mul_srcb <= m_op2 when instruction(25) = '1' or (not SHIFTER_USE_MULTIPLIER) else shift_value;
mul_src_valid <= source_valid;
lattice_mul_gen : if FAMILY = "LATTICE" generate
signal afix : unsigned(mul_a'length-2 downto 0);
signal bfix : unsigned(mul_b'length-2 downto 0);
signal abfix : unsigned(mul_a'length-2 downto 0);
signal mul_a_unsigned : unsigned(mul_a'length-2 downto 0);
signal mul_b_unsigned : unsigned(mul_b'length-2 downto 0);
signal mul_dest_unsigned : unsigned((mul_a_unsigned'length+mul_b_unsigned'length)-1 downto 0);
begin
afix <= unsigned(mul_a(mul_a'length-2 downto 0)) when mul_b(mul_b'left) = '1' else
to_unsigned(0, afix'length);
bfix <= unsigned(mul_b(mul_b'length-2 downto 0)) when mul_a(mul_a'left) = '1' else
to_unsigned(0, afix'length);
mul_a_unsigned <= unsigned(mul_a(mul_a'length-2 downto 0));
mul_b_unsigned <= unsigned(mul_b(mul_b'length-2 downto 0));
process(clk)
begin
if rising_edge(clk) then
-- The multiplication of the absolute value of the source operands.
mul_dest_unsigned <= mul_a_unsigned * mul_b_unsigned;
abfix <= afix + bfix;
end if;
end process;
mul_dest(mul_a_unsigned'length-1 downto 0) <=
std_logic_vector(mul_dest_unsigned(mul_a_unsigned'length-1 downto 0));
mul_dest(mul_dest_unsigned'left downto mul_a_unsigned'length) <=
std_logic_vector(mul_dest_unsigned(mul_dest_unsigned'left downto mul_a_unsigned'length) - abfix);
end generate lattice_mul_gen;
default_mul_gen : if FAMILY /= "LATTICE" generate
begin
process(clk)
begin
if rising_edge(clk) then
mul_dest <= std_logic_vector(mul_a * mul_b);
end if;
end process;
end generate default_mul_gen;
process(clk)
begin
if rising_edge(clk) then
--Register multiplier inputs
mul_a <= mul_srca;
mul_b <= mul_srcb;
if POWER_OPTIMIZED and mul_select = '0' and shift_select = '0' then
mul_a <= (others => '0');
mul_b <= (others => '0');
end if;
if shift_amt = to_unsigned(0, shift_amt'length) then
mul_ab_shift_by_zero <= '1';
else
mul_ab_shift_by_zero <= '0';
end if;
mul_ab_valid <= mul_src_valid;
--Register multiplier output
mul_dest_shift_by_zero <= mul_ab_shift_by_zero;
mul_dest_valid <= mul_ab_valid;
--If we don't want to pipeline multiple multiplies (as is the case when we are not using VCP)
--we only want mul_dest_valid to be high for one cycle
if from_execute_ready = '1' then
mul_ab_valid <= '0';
mul_dest_valid <= '0';
end if;
end if;
end process;
--MUL/MULH/MULHSU/MULHU select
from_mul_data <= mul_dest(REGISTER_SIZE-1 downto 0) when func3(1 downto 0) = MUL_FUNC3(1 downto 0) else
mul_dest(REGISTER_SIZE*2-1 downto REGISTER_SIZE);
from_mul_valid <= mul_dest_valid and mul_select;
end generate mul_gen;
no_mul_gen : if not MULTIPLY_ENABLE generate
mul_dest_valid <= '0';
mul_dest_shift_by_zero <= 'X';
mul_dest <= (others => 'X');
from_mul_ready <= '1';
from_mul_data <= (others => 'X');
from_mul_valid <= '0';
end generate no_mul_gen;
divide_gen : if DIVIDE_ENABLE generate
signal div_enable : std_logic;
signal quotient : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal remainder : std_logic_vector(REGISTER_SIZE-1 downto 0);
begin
div_enable <= source_valid and div_select;
div : divider
generic map (
REGISTER_SIZE => REGISTER_SIZE
)
port map (
clk => clk,
div_enable => div_enable,
div_unsigned => instruction(12),
rs1_data => to_alu_rs1_data,
rs2_data => to_alu_rs2_data,
quotient => quotient,
remainder => remainder,
from_div_valid => from_div_valid
);
from_div_data <=
quotient when func3(1) = '0' else
remainder;
from_div_ready <= from_div_valid or (not div_select);
end generate divide_gen;
no_divide_gen : if not DIVIDE_ENABLE generate
begin
from_div_ready <= '1';
from_div_data <= (others => 'X');
from_div_valid <= '0';
end generate;
from_alu_ready <= from_div_ready and from_mul_ready and from_shift_ready;
end architecture;
-------------------------------------------------------------------------------
-- Shifter
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.utils.all;
entity shifter is
generic (
REGISTER_SIZE : positive range 32 to 32;
SHIFTER_MAX_CYCLES : positive range 1 to 32
);
port (
clk : in std_logic;
shift_amt : in unsigned(log2(REGISTER_SIZE)-1 downto 0);
shift_value : in signed(REGISTER_SIZE downto 0);
lshifted_result : out std_logic_vector(REGISTER_SIZE-1 downto 0);
rshifted_result : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_shift_valid : out std_logic;
shift_enable : in std_logic
);
end entity shifter;
architecture rtl of shifter is
constant SHIFT_AMT_SIZE : natural := shift_amt'length;
signal left_tmp : signed(REGISTER_SIZE downto 0);
signal right_tmp : signed(REGISTER_SIZE downto 0);
begin
assert SHIFTER_MAX_CYCLES = 1 or SHIFTER_MAX_CYCLES = 8 or SHIFTER_MAX_CYCLES = 32 report "Bad SHIFTER_MAX_CYCLES Value" severity failure;
cycle1 : if SHIFTER_MAX_CYCLES = 1 generate
left_tmp <= SHIFT_LEFT(shift_value, to_integer(shift_amt));
right_tmp <= SHIFT_RIGHT(shift_value, to_integer(shift_amt));
from_shift_valid <= shift_enable;
end generate cycle1;
cycle4N : if SHIFTER_MAX_CYCLES = 8 generate
signal left_nxt : signed(REGISTER_SIZE downto 0);
signal right_nxt : signed(REGISTER_SIZE downto 0);
signal count : unsigned(SHIFT_AMT_SIZE downto 0);
signal count_next : unsigned(SHIFT_AMT_SIZE downto 0);
signal count_sub4 : unsigned(SHIFT_AMT_SIZE downto 0);
signal shift4 : std_logic;
type state_t is (IDLE, RUNNING, DONE);
signal state : state_t;
begin
count_sub4 <= count - 4;
shift4 <= not count_sub4(count_sub4'left);
count_next <= count_sub4 when shift4 = '1' else count-1;
left_nxt <= SHIFT_LEFT(left_tmp, 4) when shift4 = '1' else SHIFT_LEFT(left_tmp, 1);
right_nxt <= SHIFT_RIGHT(right_tmp, 4) when shift4 = '1' else SHIFT_RIGHT(right_tmp, 1);
process(clk)
begin
if rising_edge(clk) then
from_shift_valid <= '0';
if shift_enable = '1' then
case state is
when IDLE =>
left_tmp <= shift_value;
right_tmp <= shift_value;
count <= unsigned("0" & shift_amt);
if shift_amt /= 0 then
state <= RUNNING;
else
state <= IDLE;
from_shift_valid <= '1';
end if;
when RUNNING =>
left_tmp <= left_nxt;
right_tmp <= right_nxt;
count <= count_next;
if count = 1 or count = 4 then
from_shift_valid <= '1';
state <= DONE;
end if;
when Done =>
state <= IDLE;
when others =>
null;
end case;
else
state <= IDLE;
end if;
end if;
end process;
end generate cycle4N;
cycle1N : if SHIFTER_MAX_CYCLES = 32 generate
signal left_nxt : signed(REGISTER_SIZE downto 0);
signal right_nxt : signed(REGISTER_SIZE downto 0);
signal count : signed(SHIFT_AMT_SIZE-1 downto 0);
type state_t is (IDLE, RUNNING, DONE);
signal state : state_t;
begin
left_nxt <= SHIFT_LEFT(left_tmp, 1);
right_nxt <= SHIFT_RIGHT(right_tmp, 1);
process(clk)
begin
if rising_edge(clk) then
from_shift_valid <= '0';
if shift_enable = '1' then
case state is
when IDLE =>
left_tmp <= shift_value;
right_tmp <= shift_value;
count <= signed(shift_amt);
if shift_amt /= 0 then
state <= RUNNING;
else
state <= IDLE;
from_shift_valid <= '1';
end if;
when RUNNING =>
left_tmp <= left_nxt;
right_tmp <= right_nxt;
count <= count-1;
if count = 1 then
from_shift_valid <= '1';
state <= DONE;
end if;
when Done =>
state <= IDLE;
when others =>
null;
end case;
else
state <= IDLE;
end if;
end if;
end process;
end generate cycle1N;
rshifted_result <= std_logic_vector(right_tmp(REGISTER_SIZE-1 downto 0));
lshifted_result <= std_logic_vector(left_tmp(REGISTER_SIZE-1 downto 0));
end architecture rtl;
-------------------------------------------------------------------------------
-- Divider
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.utils.all;
entity divider is
generic (
REGISTER_SIZE : positive range 32 to 32
);
port (
clk : in std_logic;
div_enable : in std_logic;
div_unsigned : in std_logic;
rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
quotient : out std_logic_vector(REGISTER_SIZE-1 downto 0);
remainder : out std_logic_vector(REGISTER_SIZE-1 downto 0);
from_div_valid : out std_logic
);
end entity;
architecture rtl of divider is
type div_state is (IDLE, DIVIDING, DONE);
signal state : div_state;
signal count : natural range REGISTER_SIZE-1 downto 0;
signal numerator : unsigned(REGISTER_SIZE-1 downto 0);
signal denominator : unsigned(REGISTER_SIZE-1 downto 0);
signal div_neg_op1 : std_logic;
signal div_neg_op2 : std_logic;
signal div_neg_quotient : std_logic;
signal div_neg_remainder : std_logic;
signal div_by_zero : boolean;
signal div_overflow : boolean;
signal div_res : unsigned(REGISTER_SIZE-1 downto 0);
signal rem_res : unsigned(REGISTER_SIZE-1 downto 0);
signal min_signed : signed(REGISTER_SIZE-1 downto 0);
begin
div_neg_op1 <= not div_unsigned when signed(rs1_data) < 0 else '0';
div_neg_op2 <= not div_unsigned when signed(rs2_data) < 0 else '0';
min_signed(min_signed'left) <= '1';
min_signed(min_signed'left-1 downto 0) <= (others => '0');
div_by_zero <= unsigned(rs2_data) = to_unsigned(0, REGISTER_SIZE);
div_overflow <= (signed(rs1_data) = min_signed and
signed(rs2_data) = to_signed(-1, REGISTER_SIZE) and
div_unsigned = '0');
numerator <= unsigned(rs1_data) when div_neg_op1 = '0' else unsigned(-signed(rs1_data));
denominator <= unsigned(rs2_data) when div_neg_op2 = '0' else unsigned(-signed(rs2_data));
div_proc : process(clk)
variable D : unsigned(REGISTER_SIZE-1 downto 0);
variable N : unsigned(REGISTER_SIZE-1 downto 0);
variable R : unsigned(REGISTER_SIZE-1 downto 0);
variable Q : unsigned(REGISTER_SIZE-1 downto 0);
variable sub : unsigned(REGISTER_SIZE downto 0);
variable Q_lsb : std_logic;
begin
if rising_edge(clk) then
from_div_valid <= '0';
if div_enable = '1' then
case state is
when IDLE =>
div_neg_quotient <= div_neg_op2 xor div_neg_op1;
div_neg_remainder <= div_neg_op1;
D := denominator;
N := numerator;
R := (others => '0');
if div_by_zero then
Q := (others => '1');
R := unsigned(rs1_data);
from_div_valid <= '1';
div_neg_remainder <= '0';
div_neg_quotient <= '0';
elsif div_overflow then
Q := unsigned(min_signed);
from_div_valid <= '1';
div_neg_remainder <= '0';
div_neg_quotient <= '0';
else
state <= DIVIDING;
count <= Q'length - 1;
end if;
when DIVIDING =>
R(REGISTER_SIZE-1 downto 1) := R(REGISTER_SIZE-2 downto 0);
R(0) := N(N'left);
N := SHIFT_LEFT(N, 1);
Q_lsb := '0';
sub := ("0"&R)-("0"&D);
if sub(sub'left) = '0' then
R := sub(R'range);
Q_lsb := '1';
end if;
Q := Q(Q'left-1 downto 0) & Q_lsb;
if count /= 0 then
count <= count - 1;
else
from_div_valid <= '1';
state <= DONE;
end if;
when DONE =>
state <= IDLE;
end case;
div_res <= Q;
rem_res <= R;
else
state <= IDLE;
end if;
end if; -- clk
end process;
remainder <= std_logic_vector(rem_res) when div_neg_remainder = '0' else std_logic_vector(-signed(rem_res));
quotient <= std_logic_vector(div_res) when div_neg_quotient = '0' else std_logic_vector(-signed(div_res));
end architecture rtl;
|
bsd-3-clause
|
329d31909399af0cceec722bd8ddb56f
| 0.550434 | 3.665556 | false | false | false | false |
VectorBlox/risc-v
|
ip/orca/hdl/sys_call.vhd
| 1 | 31,459 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.utils.all;
use work.constants_pkg.all;
entity sys_call is
generic (
REGISTER_SIZE : positive range 32 to 32;
POWER_OPTIMIZED : boolean;
INTERRUPT_VECTOR : std_logic_vector(31 downto 0);
ENABLE_EXCEPTIONS : boolean;
ENABLE_EXT_INTERRUPTS : boolean;
NUM_EXT_INTERRUPTS : positive range 1 to 32;
VCP_ENABLE : vcp_type;
MULTIPLY_ENABLE : boolean;
AUX_MEMORY_REGIONS : natural range 0 to 4;
AMR0_ADDR_BASE : std_logic_vector(31 downto 0);
AMR0_ADDR_LAST : std_logic_vector(31 downto 0);
AMR0_READ_ONLY : boolean;
UC_MEMORY_REGIONS : natural range 0 to 4;
UMR0_ADDR_BASE : std_logic_vector(31 downto 0);
UMR0_ADDR_LAST : std_logic_vector(31 downto 0);
UMR0_READ_ONLY : boolean;
HAS_ICACHE : boolean;
HAS_DCACHE : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
global_interrupts : in std_logic_vector(NUM_EXT_INTERRUPTS-1 downto 0);
core_idle : in std_logic;
memory_idle : in std_logic;
program_counter : in unsigned(REGISTER_SIZE-1 downto 0);
to_syscall_valid : in std_logic;
from_syscall_illegal : out std_logic;
current_pc : in unsigned(REGISTER_SIZE-1 downto 0);
instruction : in std_logic_vector(31 downto 0);
rs1_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
rs2_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
from_syscall_ready : out std_logic;
from_branch_misaligned : in std_logic;
illegal_instruction : in std_logic;
from_lsu_addr_misalign : in std_logic;
from_lsu_address : in std_logic_vector(REGISTER_SIZE-1 downto 0);
from_syscall_valid : out std_logic;
from_syscall_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
to_pc_correction_data : out unsigned(REGISTER_SIZE-1 downto 0);
to_pc_correction_valid : out std_logic;
from_pc_correction_ready : in std_logic;
from_icache_control_ready : in std_logic;
to_icache_control_valid : buffer std_logic;
to_icache_control_command : out cache_control_command;
from_dcache_control_ready : in std_logic;
to_dcache_control_valid : buffer std_logic;
to_dcache_control_command : out cache_control_command;
to_cache_control_base : out std_logic_vector(REGISTER_SIZE-1 downto 0);
to_cache_control_last : out std_logic_vector(REGISTER_SIZE-1 downto 0);
amr_base_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
amr_last_addrs : out std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
umr_base_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
umr_last_addrs : out std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*REGISTER_SIZE)-1 downto 0);
pause_ifetch : out std_logic;
timer_value : in std_logic_vector(63 downto 0);
timer_interrupt : in std_logic;
vcp_writeback_en : in std_logic;
vcp_writeback_data : in std_logic_vector(REGISTER_SIZE-1 downto 0)
);
end entity sys_call;
architecture rtl of sys_call is
signal fence_select : std_logic;
signal fencei_select : std_logic;
signal cache_select : std_logic;
signal csr_select : std_logic;
signal ebreak_select : std_logic;
signal ecall_select : std_logic;
signal mret_select : std_logic;
-- CSR signals. These are initialized to zero so that if any bits are never
-- assigned, they act like constants.
signal mstatus : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mscratch : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mepc : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mcause : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mtval : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mtime : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mtimeh : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal meimask : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal meimask_full : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal meipend : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mcache : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal misa : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
signal mtvec : std_logic_vector(REGISTER_SIZE-1 downto 0) := (others => '0');
alias csr_number : std_logic_vector(CSR_ADDRESS'length-1 downto 0) is instruction(CSR_ADDRESS'range);
alias opcode : std_logic_vector(INSTR_OPCODE'length-1 downto 0) is instruction(INSTR_OPCODE'range);
alias func3 : std_logic_vector(INSTR_FUNC3'length-1 downto 0) is instruction(INSTR_FUNC3'range);
alias func7 : std_logic_vector(INSTR_FUNC7'length-1 downto 0) is instruction(INSTR_FUNC7'range);
alias imm : std_logic_vector(CSR_ZIMM'length-1 downto 0) is instruction(CSR_ZIMM'range);
alias rs1_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is instruction(REGISTER_RS1'range);
alias rd_select : std_logic_vector(REGISTER_NAME_SIZE-1 downto 0) is instruction(REGISTER_RD'range);
alias mcause_exc_code : std_logic_vector is mcause(CSR_MCAUSE_CODE'range);
alias bit_sel : std_logic_vector(REGISTER_SIZE-1 downto 0) is rs1_data;
signal csr_readdata : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal csr_writedata : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal last_csr_writedata : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal was_mret : std_logic;
signal was_illegal : std_logic;
signal fence_pc_correction_valid : std_logic;
signal next_fence_pc : unsigned(REGISTER_SIZE-1 downto 0);
signal fence_pending : std_logic;
signal interrupt_pending : std_logic;
signal interrupt_pc_correction_valid : std_logic;
--Uncached/Auxiliary memory region CSR signals. Will be assigned 0's if unused.
type csr_vector is array (natural range <>) of std_logic_vector(REGISTER_SIZE-1 downto 0);
signal mamr_base : csr_vector(3 downto 0);
signal mamr_last : csr_vector(3 downto 0);
signal mumr_base : csr_vector(3 downto 0);
signal mumr_last : csr_vector(3 downto 0);
signal amr_base_select : std_logic_vector(3 downto 0);
signal amr_last_select : std_logic_vector(3 downto 0);
signal umr_base_select : std_logic_vector(3 downto 0);
signal umr_last_select : std_logic_vector(3 downto 0);
signal amr_base_write : std_logic_vector(3 downto 0);
signal amr_last_write : std_logic_vector(3 downto 0);
signal umr_base_write : std_logic_vector(3 downto 0);
signal umr_last_write : std_logic_vector(3 downto 0);
begin
--Decode instruction to select submodule. All paths must decode to exactly
--one submodule.
--ASSUMES only SYSTEM_OP | MISC_MEM_OP for opcode.
process (opcode, func3, func7) is
begin
fence_select <= '0';
fencei_select <= '0';
cache_select <= '0';
csr_select <= '0';
ebreak_select <= '0';
ecall_select <= '0';
mret_select <= '0';
from_syscall_illegal <= '0';
if opcode(6) = SYSTEM_OP(6) then
if ENABLE_EXCEPTIONS then
case func3 is
when PRIV_FUNC3 =>
if rs1_select /= REGISTER_ZERO or rd_select /= REGISTER_ZERO then
from_syscall_illegal <= '1';
else
case csr_number is
when SYSTEM_ECALL =>
ecall_select <= '1';
when SYSTEM_EBREAK =>
ebreak_select <= '1';
when SYSTEM_MRET =>
mret_select <= '1';
when others =>
from_syscall_illegal <= '1';
end case;
end if;
when "100" =>
from_syscall_illegal <= '1';
when others =>
csr_select <= '1';
end case;
else
csr_select <= '1';
end if;
else
case func3 is
when FENCE_FUNC3 =>
fence_select <= '1';
when REGION_FUNC3 =>
case func7 is
when FENCE_I_FUNC7 | FENCE_RI_FUNC7 =>
fencei_select <= '1';
when FENCE_RD_FUNC7 =>
fence_select <= '1';
when CACHE_WRITEBACK_FUNC7 | CACHE_FLUSH_FUNC7 | CACHE_DISCARD_FUNC7 =>
if HAS_DCACHE then
cache_select <= '1';
else
fence_select <= '1';
end if;
when others =>
if ENABLE_EXCEPTIONS then
from_syscall_illegal <= '1';
else
fence_select <= '1';
end if;
end case;
when others =>
if ENABLE_EXCEPTIONS then
from_syscall_illegal <= '1';
else
fence_select <= '1';
end if;
end case;
end if;
end process;
mtime <= std_logic_vector(timer_value(REGISTER_SIZE-1 downto 0));
mtimeh <= std_logic_vector(timer_value(timer_value'left downto timer_value'left-REGISTER_SIZE+1));
misa(misa'left downto misa'left-1) <= "01";
misa(23) <= '0' when VCP_ENABLE = DISABLED else '1';
misa(8) <= '1'; --I
misa(12) <= '1' when MULTIPLY_ENABLE else '0';
with csr_number select
csr_readdata <=
misa when CSR_MISA,
mscratch when CSR_MSCRATCH,
mstatus when CSR_MSTATUS,
mepc when CSR_MEPC,
mcause when CSR_MCAUSE,
mtval when CSR_MTVAL,
meimask when CSR_MEIMASK,
meipend when CSR_MEIPEND,
mtime when CSR_MTIME,
mtimeh when CSR_MTIMEH,
mtime when CSR_UTIME,
mtimeh when CSR_UTIMEH,
mcache when CSR_MCACHE,
mtvec when CSR_MTVEC,
mamr_base(0) when CSR_MAMR0_BASE,
mamr_base(1) when CSR_MAMR1_BASE,
mamr_base(2) when CSR_MAMR2_BASE,
mamr_base(3) when CSR_MAMR3_BASE,
mamr_last(0) when CSR_MAMR0_LAST,
mamr_last(1) when CSR_MAMR1_LAST,
mamr_last(2) when CSR_MAMR2_LAST,
mamr_last(3) when CSR_MAMR3_LAST,
mumr_base(0) when CSR_MUMR0_BASE,
mumr_base(1) when CSR_MUMR1_BASE,
mumr_base(2) when CSR_MUMR2_BASE,
mumr_base(3) when CSR_MUMR3_BASE,
mumr_last(0) when CSR_MUMR0_LAST,
mumr_last(1) when CSR_MUMR1_LAST,
mumr_last(2) when CSR_MUMR2_LAST,
mumr_last(3) when CSR_MUMR3_LAST,
(others => '0') when others;
with func3 select
csr_writedata <=
csr_readdata(31 downto 5) & (csr_readdata(CSR_ZIMM'length-1 downto 0) and (not imm)) when CSRRCI_FUNC3,
csr_readdata(31 downto 5) & (csr_readdata(CSR_ZIMM'length-1 downto 0) or imm) when CSRRSI_FUNC3,
std_logic_vector(resize(unsigned(imm), csr_writedata'length)) when CSRRWI_FUNC3,
csr_readdata and (not rs1_data) when CSRRC_FUNC3,
csr_readdata or rs1_data when CSRRS_FUNC3,
rs1_data when others; --CSRRW_FUNC3,
--Currently all syscall instructions execute without backpressure
from_syscall_ready <= '1';
exceptions_gen : if ENABLE_EXCEPTIONS generate
process(clk)
begin
if rising_edge(clk) then
--Hold pc_correction causing signals until they have been processed
if from_pc_correction_ready = '1' then
was_mret <= '0';
was_illegal <= '0';
end if;
if(illegal_instruction = '1' or
from_lsu_addr_misalign = '1' or
from_branch_misaligned = '1' or
(to_syscall_valid = '1' and (ebreak_select = '1' or ecall_select = '1'))) then
--Handle Illegal Instructions
mstatus(CSR_MSTATUS_MIE) <= '0';
mstatus(CSR_MSTATUS_MPIE) <= mstatus(CSR_MSTATUS_MIE);
mcause(mcause'left) <= '0';
if from_branch_misaligned = '1' then
mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_FETCH_MISALIGN;
--according to the tests its legal to put zero in this register
mtval <= std_logic_vector(to_unsigned(0, mtval'length));
elsif illegal_instruction = '1' then
mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_ILLEGAL;
mtval <= instruction(mtval'range);
elsif from_lsu_addr_misalign = '1' then
mtval <= from_lsu_address;
mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_LOAD_MISALIGN;
if instruction(5) = '1' then
mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_STORE_MISALIGN;
end if;
else
if ebreak_select = '1' then
mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_EBREAK;
else
mcause(CSR_MCAUSE_CODE'range) <= CSR_MCAUSE_MECALL;
end if;
end if;
mepc <= std_logic_vector(current_pc);
was_illegal <= '1';
end if;
if to_syscall_valid = '1' then
if csr_select = '1' then
--CSR Read/Write
case csr_number is
when CSR_MTVEC =>
-- Only direct exceptions are available; zero lower two bits
mtvec(REGISTER_SIZE-1 downto 2) <= csr_writedata(REGISTER_SIZE-1 downto 2);
when CSR_MSTATUS =>
-- Only 2 bits are writeable.
mstatus(CSR_MSTATUS_MIE) <= csr_writedata(CSR_MSTATUS_MIE);
mstatus(CSR_MSTATUS_MPIE) <= csr_writedata(CSR_MSTATUS_MPIE);
when CSR_MEPC =>
mepc <= csr_writedata;
when CSR_MCAUSE =>
--MCAUSE is WLRL so only legal values need to be supported
mcause(mcause'left) <= csr_writedata(mcause'left);
mcause(CSR_MCAUSE_CODE'range) <= csr_writedata(CSR_MCAUSE_CODE'range);
when CSR_MTVAL =>
mtval <= csr_writedata;
when CSR_MEIMASK =>
meimask_full <= csr_writedata;
when CSR_MSCRATCH =>
mscratch <= csr_writedata;
when others => null;
end case;
end if;
if mret_select = '1' then
--MRET
mstatus(CSR_MSTATUS_MIE) <= mstatus(CSR_MSTATUS_MPIE);
mstatus(CSR_MSTATUS_MPIE) <= '0';
was_mret <= '1';
end if;
end if;
if from_pc_correction_ready = '1' then
interrupt_pc_correction_valid <= '0';
end if;
if interrupt_pending = '1' and core_idle = '1' then
interrupt_pc_correction_valid <= '1';
-- Latch in mepc the cycle before interrupt_pc_correction_valid goes high.
-- When interrupt_pc_correction_valid goes high, the next_pc of the instruction fetch will
-- be corrected to the interrupt reset vector.
mepc <= std_logic_vector(program_counter);
mstatus(CSR_MSTATUS_MIE) <= '0';
mstatus(CSR_MSTATUS_MPIE) <= '1';
mcause(mcause'left) <= '1';
mcause_exc_code <= CSR_MCAUSE_MEXT;
if timer_interrupt = '1' then
mcause_exc_code <= CSR_MCAUSE_MTIMER;
end if;
end if;
if reset = '1' then
was_mret <= '0';
was_illegal <= '0';
interrupt_pc_correction_valid <= '0';
mtvec(REGISTER_SIZE-1 downto 2) <= INTERRUPT_VECTOR(REGISTER_SIZE-1 downto 2);
mstatus(CSR_MSTATUS_MIE) <= '0';
mstatus(CSR_MSTATUS_MPIE) <= '0';
mepc <= (others => '0');
mcause(mcause'left) <= '0';
mcause_exc_code <= (others => '0');
meimask_full <= (others => '0');
end if;
mepc(1 downto 0) <= "00";
end if;
end process;
mtvec(1 downto 0) <= (others => '0');
mstatus(REGISTER_SIZE-1 downto CSR_MSTATUS_MPIE+1) <= (others => '0');
mstatus(CSR_MSTATUS_MPIE-1 downto CSR_MSTATUS_MIE+1) <= (others => '0');
mstatus(CSR_MSTATUS_MIE-1 downto 0) <= (others => '0');
mcause(mcause'left-1 downto CSR_MCAUSE_CODE'left+1) <= (others => '0');
end generate exceptions_gen;
no_exceptions_gen : if not ENABLE_EXCEPTIONS generate
mtvec <= (others => '0');
was_mret <= '0';
was_illegal <= '0';
interrupt_pc_correction_valid <= '0';
mstatus <= (others => '0');
mepc <= (others => '0');
mcause <= (others => '0');
end generate no_exceptions_gen;
memory_region_registers_gen : for gregister in 3 downto 0 generate
amr_gen : if (AUX_MEMORY_REGIONS > gregister) and ((UC_MEMORY_REGIONS /= 0) or HAS_ICACHE or HAS_DCACHE) generate
read_only_amr_gen : if gregister = 0 and AMR0_READ_ONLY generate
amr_base_select(gregister) <= '0';
amr_last_select(gregister) <= '0';
mamr_base(gregister) <= AMR0_ADDR_BASE;
mamr_last(gregister) <= AMR0_ADDR_LAST;
end generate read_only_amr_gen;
writeable_amr_gen : if gregister /= 0 or (not AMR0_READ_ONLY) generate
amr_base_select(gregister) <=
'1' when (csr_number(csr_number'left downto 3) = CSR_MAMR0_BASE(CSR_MAMR0_BASE'left downto 3) and
unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else
'0';
amr_last_select(gregister) <=
'1' when (csr_number(csr_number'left downto 3) = CSR_MAMR0_LAST(CSR_MAMR0_LAST'left downto 3) and
unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else
'0';
process(clk)
begin
if rising_edge(clk) then
--Don't write the new AMR until the pipeline and memory interface are
--flushed
if from_pc_correction_ready = '1' then
if (memory_idle = '1' and
(from_icache_control_ready = '1' or to_icache_control_valid = '0') and
(from_dcache_control_ready = '1' or to_dcache_control_valid = '0')) then
if amr_base_write(gregister) = '1' then
mamr_base(gregister) <= last_csr_writedata;
end if;
if amr_last_write(gregister) = '1' then
mamr_last(gregister) <= last_csr_writedata;
end if;
end if;
end if;
if reset = '1' then
if gregister = 0 then
mamr_base(gregister) <= AMR0_ADDR_BASE;
mamr_last(gregister) <= AMR0_ADDR_LAST;
else
mamr_base(gregister) <= (others => '1');
mamr_last(gregister) <= (others => '0');
end if;
end if;
end if;
end process;
end generate writeable_amr_gen;
end generate amr_gen;
no_amr_gen : if ((AUX_MEMORY_REGIONS <= gregister) or
((UC_MEMORY_REGIONS = 0) and (not HAS_ICACHE) and (not HAS_DCACHE))) generate
amr_base_select(gregister) <= '0';
amr_last_select(gregister) <= '0';
mamr_base(gregister) <= (others => '0');
mamr_last(gregister) <= (others => '0');
end generate no_amr_gen;
umr_gen : if (UC_MEMORY_REGIONS > gregister) and ((AUX_MEMORY_REGIONS /= 0) or HAS_ICACHE or HAS_DCACHE) generate
read_only_umr_gen : if gregister = 0 and UMR0_READ_ONLY generate
umr_base_select(gregister) <= '0';
umr_last_select(gregister) <= '0';
mumr_base(gregister) <= UMR0_ADDR_BASE;
mumr_last(gregister) <= UMR0_ADDR_LAST;
end generate read_only_umr_gen;
writeable_umr_gen : if gregister /= 0 or (not UMR0_READ_ONLY) generate
umr_base_select(gregister) <=
'1' when (csr_number(csr_number'left downto 3) = CSR_MUMR0_BASE(CSR_MUMR0_BASE'left downto 3) and
unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else
'0';
umr_last_select(gregister) <=
'1' when (csr_number(csr_number'left downto 3) = CSR_MUMR0_LAST(CSR_MUMR0_LAST'left downto 3) and
unsigned(csr_number(2 downto 0)) = to_unsigned(gregister, 3)) else
'0';
process(clk)
begin
if rising_edge(clk) then
--Don't write the new UMR until the pipeline and memory interface are
--flushed
if from_pc_correction_ready = '1' then
if (memory_idle = '1' and
(from_icache_control_ready = '1' or to_icache_control_valid = '0') and
(from_dcache_control_ready = '1' or to_dcache_control_valid = '0')) then
if umr_base_write(gregister) = '1' then
mumr_base(gregister) <= last_csr_writedata;
end if;
if umr_last_write(gregister) = '1' then
mumr_last(gregister) <= last_csr_writedata;
end if;
end if;
end if;
if reset = '1' then
if gregister = 0 then
mumr_base(gregister) <= UMR0_ADDR_BASE;
mumr_last(gregister) <= UMR0_ADDR_LAST;
else
mumr_base(gregister) <= (others => '1');
mumr_last(gregister) <= (others => '0');
end if;
end if;
end if;
end process;
end generate writeable_umr_gen;
end generate umr_gen;
no_umr_gen : if ((UC_MEMORY_REGIONS <= gregister) or
((AUX_MEMORY_REGIONS = 0) and (not HAS_ICACHE) and (not HAS_DCACHE))) generate
umr_base_select(gregister) <= '0';
umr_last_select(gregister) <= '0';
mumr_base(gregister) <= (others => '0');
mumr_last(gregister) <= (others => '0');
end generate no_umr_gen;
end generate memory_region_registers_gen;
amr_gen : for gregister in imax(AUX_MEMORY_REGIONS, 1)-1 downto 0 generate
amr_base_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mamr_base(gregister);
amr_last_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mamr_last(gregister);
end generate amr_gen;
umr_gen : for gregister in imax(UC_MEMORY_REGIONS, 1)-1 downto 0 generate
umr_base_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mumr_base(gregister);
umr_last_addrs(((gregister+1)*REGISTER_SIZE)-1 downto gregister*REGISTER_SIZE) <= mumr_last(gregister);
end generate umr_gen;
has_icache_gen : if HAS_ICACHE generate
mcache(CSR_MCACHE_IEXISTS) <= '1';
end generate has_icache_gen;
no_icache_gen : if not HAS_ICACHE generate
mcache(CSR_MCACHE_IEXISTS) <= '0';
end generate no_icache_gen;
has_dcache_gen : if HAS_DCACHE generate
mcache(CSR_MCACHE_DEXISTS) <= '1';
end generate has_dcache_gen;
no_dcache_gen : if not HAS_DCACHE generate
mcache(CSR_MCACHE_DEXISTS) <= '0';
end generate no_dcache_gen;
mcache(REGISTER_SIZE-1 downto CSR_MCACHE_DEXISTS+1) <= (others => '0');
process(clk)
begin
if rising_edge(clk) then
from_syscall_valid <= '0';
--Hold pc_correction causing signals until they have been processed
if from_pc_correction_ready = '1' then
fence_pc_correction_valid <= '0';
--On FENCE.I hold the PC correction until all pending writebacks have
--occurred and the ICache is flushed (from_icache_control_ready is
--hardwired to '1' when no ICache is present).
if (memory_idle = '1' and
(from_icache_control_ready = '1' or to_icache_control_valid = '0') and
(from_dcache_control_ready = '1' or to_dcache_control_valid = '0')) then
fence_pending <= '0';
amr_base_write <= (others => '0');
amr_last_write <= (others => '0');
umr_base_write <= (others => '0');
umr_last_write <= (others => '0');
end if;
end if;
if from_icache_control_ready = '1' then
to_icache_control_valid <= '0';
end if;
if from_dcache_control_ready = '1' then
to_dcache_control_valid <= '0';
end if;
if illegal_instruction = '0' and to_syscall_valid = '1' then
if csr_select = '1' then
--CSR Read/Write
from_syscall_valid <= '1';
from_syscall_data <= csr_readdata;
last_csr_writedata <= csr_writedata;
--Changing cacheability flushes the pipeline and clears the
--memory interface before resuming.
if or_slv(amr_base_select or amr_last_select or umr_base_select or umr_last_select) = '1' then
fence_pc_correction_valid <= '1';
fence_pending <= '1';
end if;
amr_base_write <= amr_base_select;
amr_last_write <= amr_last_select;
umr_base_write <= umr_base_select;
umr_last_write <= umr_last_select;
end if;
next_fence_pc <= unsigned(current_pc) + to_unsigned(4, next_fence_pc'length);
to_icache_control_command <= INVALIDATE;
to_dcache_control_command <= WRITEBACK;
to_cache_control_base <= rs1_data;
to_cache_control_last <= rs2_data;
if fencei_select = '1' then
--FENCE.I/FENCE.RI
fence_pc_correction_valid <= '1';
fence_pending <= '1';
to_icache_control_valid <= '1';
to_dcache_control_valid <= '1';
if func7(1) = '0' then
--FENCE.I does not take base/last parameters; applies to all of cache
to_cache_control_base <= (others => '0');
to_cache_control_last <= (others => '1');
end if;
--Unclear from the REGION draft spec if FENCE.RI should return a
--value or not, since it can't partially complete. Omitting for now
--as it doesn't seem useful.
end if;
if cache_select = '1' then
--CACHE control instructions
--A FENCE is implied by all cache control instructions.
fence_pc_correction_valid <= '1';
fence_pending <= '1';
--Cache control instructions must return a value > rs2 on completion,
--corresponding to the start of memory not affected. Since if all
--memory is affected it's valid to return 0, just return 0 for all
--these instructions.
from_syscall_valid <= '1';
from_syscall_data <= (others => '0');
to_dcache_control_valid <= '1';
case func7(1 downto 0) is
when "00" => --CACHE_WRITEBACK_FUNC7(1 downto 0)
to_dcache_control_command <= WRITEBACK;
when "01" => --CACHE_FLUSH_FUNC7(1 downto 0)
to_dcache_control_command <= FLUSH;
when others => --CACHE_DISCARD_FUNC7(1 downto 0) + don't care
--Currently INVALIDATE invalidates the entire cache which is not
--safe. Until region support is added just flush the cache which
--is always safe.
to_dcache_control_command <= FLUSH;
end case;
end if;
if fence_select = '1' then
--FENCE
--All interfaces are strictly ordered and when switching between
--interfaces (via AMR/UMR writes) a FENCE is performed, so FENCEs
--don't need to do anything.
--Unclear from the REGION draft spec if FENCE.RI should return a
--value or not, since it can't partially complete. Omitting for now
--as it doesn't seem useful.
null;
end if;
end if;
if VCP_ENABLE /= DISABLED and vcp_writeback_en = '1' then
-- To avoid having a 5 to one mux in execute, we add
-- the writebacks from the vcp here. Since the writebacks
-- are from vbx_get, which are sort of control/status
-- registers it could be construed that this is an
-- appropriate place for this logic
from_syscall_data <= vcp_writeback_data;
from_syscall_valid <= '1';
end if;
if reset = '1' then
from_syscall_valid <= '0';
fence_pc_correction_valid <= '0';
fence_pending <= '0';
to_icache_control_valid <= '0';
to_dcache_control_valid <= '0';
amr_base_write <= (others => '0');
amr_last_write <= (others => '0');
umr_base_write <= (others => '0');
umr_last_write <= (others => '0');
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- Handle Global Interrupts
--
-- If interrupt is pending and enabled, slip the pipeline. This is done by
-- sending the interrupt_pending signal to the instruction_fetch.
--
-- Once the pipeline is empty, then correct the PC.
--------------------------------------------------------------------------------
interrupts_gen : if ENABLE_EXT_INTERRUPTS generate
process(clk)
begin
if rising_edge(clk) then
meipend(NUM_EXT_INTERRUPTS-1 downto 0) <= global_interrupts;
end if;
end process;
meimask(NUM_EXT_INTERRUPTS-1 downto 0) <= meimask_full(NUM_EXT_INTERRUPTS-1 downto 0);
not_all_interrupts_gen : if NUM_EXT_INTERRUPTS < REGISTER_SIZE generate
meipend(REGISTER_SIZE-1 downto NUM_EXT_INTERRUPTS) <= (others => '0');
meimask(REGISTER_SIZE-1 downto NUM_EXT_INTERRUPTS) <= (others => '0');
end generate not_all_interrupts_gen;
end generate interrupts_gen;
no_interrupts_gen : if not ENABLE_EXT_INTERRUPTS generate
meipend <= (others => '0');
meimask <= (others => '0');
end generate no_interrupts_gen;
interrupt_pending <= mstatus(CSR_MSTATUS_MIE) when unsigned(meimask and meipend) /= 0 or timer_interrupt = '1' else '0';
pause_ifetch <= fence_pending or interrupt_pending;
-- There are several reasons that sys_calls might send a pc correction
-- global interrupt
-- illegal instruction
-- mret instruction
-- fence.i (flush pipeline, and start over)
to_pc_correction_valid <= fence_pc_correction_valid or was_mret or was_illegal or interrupt_pc_correction_valid;
to_pc_correction_data <=
next_fence_pc when fence_pc_correction_valid = '1' else
unsigned(mtvec) when (was_illegal = '1' or interrupt_pc_correction_valid = '1') else
unsigned(mepc) when was_mret = '1' else
(others => '-');
end architecture rtl;
|
bsd-3-clause
|
9ecd2604f6873d4f7618e1b98a6470d2
| 0.566928 | 3.749583 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/video/vdp18/vdp18_cpuio.vhd
| 2 | 19,580 |
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_cpuio.vhd,v 1.17 2006/06/18 10:47:01 arnim Exp $
--
-- CPU I/O Interface Module
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vdp18_pack.all;
entity vdp18_cpuio is
port (
clock_i : in std_logic;
clk_en_10m7_i : in boolean;
clk_en_acc_i : in boolean;
reset_i : in boolean;
rd_i : in boolean;
wr_i : in boolean;
mode_i : in std_logic_vector(0 to 1);
cd_i : in std_logic_vector(0 to 7);
cd_o : out std_logic_vector(0 to 7);
cd_oe_o : out std_logic;
wait_o : out std_logic;
access_type_i : in access_t;
opmode_o : out opmode_t;
vram_read_o : out boolean;
vram_write_o : out boolean;
vram_we_o : out std_logic;
vram_a_o : out std_logic_vector(0 to 13);
vram_d_o : out std_logic_vector(0 to 7);
vram_d_i : in std_logic_vector(0 to 7);
spr_coll_i : in boolean;
spr_5th_i : in boolean;
spr_5th_num_i : in std_logic_vector(0 to 4);
reg_ev_o : out boolean;
reg_16k_o : out boolean;
reg_blank_o : out boolean;
reg_size1_o : out boolean;
reg_mag1_o : out boolean;
reg_ntb_o : out std_logic_vector(0 to 3);
reg_ctb_o : out std_logic_vector(0 to 7);
reg_pgb_o : out std_logic_vector(0 to 2);
reg_satb_o : out std_logic_vector(0 to 6);
reg_spgb_o : out std_logic_vector(0 to 2);
reg_col1_o : out std_logic_vector(0 to 3);
reg_col0_o : out std_logic_vector(0 to 3);
palette_idx_o : out std_logic_vector(0 to 3);
palette_val_o : out std_logic_vector(0 to 15);
palette_wr_o : out std_logic;
irq_i : in boolean;
int_n_o : out std_logic;
vertfreq_csw_o : out std_logic;
vertfreq_d_o : out std_logic
);
end vdp18_cpuio;
architecture rtl of vdp18_cpuio is
type state_t is (ST_IDLE,
ST_RD_MODE0, ST_WR_MODE0,
ST_RD_MODE1,
ST_WR_MODE1_1ST, ST_WR_MODE1_1ST_IDLE,
ST_WR_MODE1_2ND_VREAD, ST_WR_MODE1_2ND_VWRITE,
ST_WR_MODE1_2ND_RWRITE,
ST_WR_PALETTE);
signal state_s, state_q : state_t;
signal buffer_q : std_logic_vector(0 to 7);
signal addr_q : unsigned(0 to 13);
signal incr_addr_s,
load_addr_s : boolean;
signal wrbuf_cpu_s : boolean;
signal sched_rdvram_s,
rdvram_sched_q,
rdvram_q : boolean;
signal abort_wrvram_s,
sched_wrvram_s,
wrvram_sched_q,
wrvram_q : boolean;
signal write_tmp_s : boolean;
signal tmp_q : std_logic_vector(0 to 7);
signal write_reg_s : boolean;
-- control register bits ----------------------------------------------------
type ctrl_reg_t is array (natural range 7 downto 0) of std_logic_vector(0 to 7);
signal ctrl_reg_q : ctrl_reg_t;
-- status register ----------------------------------------------------------
signal status_reg_s : std_logic_vector(0 to 7);
signal destr_rd_status_s : boolean;
signal sprite_5th_q : boolean;
signal sprite_5th_num_q : std_logic_vector(0 to 4);
signal sprite_coll_q : boolean;
signal int_n_q : std_logic;
type read_mux_t is (RDMUX_STATUS, RDMUX_READAHEAD);
signal read_mux_s : read_mux_t;
-- palette
signal palette_idx_s : unsigned(0 to 3);
signal incr_palidx_s : boolean;
signal palette_val_s : std_logic_vector(0 to 15);
signal write_pal_s : boolean;
signal wrpal_byte2_s : boolean;
signal wait_s : std_logic;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (clock_i, reset_i)
variable incr_addr_v : boolean;
variable write_pal_v : boolean;
begin
if reset_i then
state_q <= ST_IDLE;
buffer_q <= (others => '0');
addr_q <= (others => '0');
rdvram_sched_q <= false;
rdvram_q <= false;
wrvram_sched_q <= false;
wrvram_q <= false;
palette_idx_o <= (others => '0');
wrpal_byte2_s <= false;
write_pal_v := false;
elsif clock_i'event and clock_i = '1' then
-- default assignments
incr_addr_v := incr_addr_s;
if clk_en_10m7_i then
incr_palidx_s <= false;
-- update state vector ------------------------------------------------
state_q <= state_s;
-- buffer and flag control --------------------------------------------
if wrbuf_cpu_s then
-- write read-ahead buffer from CPU bus
buffer_q <= cd_i;
-- immediately stop read-ahead
rdvram_sched_q <= false;
rdvram_q <= false;
elsif clk_en_acc_i and rdvram_q and access_type_i = AC_CPU then
-- write read-ahead buffer from VRAM during CPU access slot
buffer_q <= vram_d_i;
-- stop scanning for CPU data
rdvram_q <= false;
-- increment read-ahead address
incr_addr_v := true;
end if;
if sched_rdvram_s then
-- immediately stop write-back
wrvram_sched_q <= false;
wrvram_q <= false;
-- schedule read-ahead
rdvram_sched_q <= true;
end if;
if sched_wrvram_s then
-- schedule write-back
wrvram_sched_q <= true;
end if;
if abort_wrvram_s then
-- stop scanning for write-back
wrvram_q <= false;
end if;
if rdvram_sched_q and clk_en_acc_i then
-- align scheduled read-ahead with access slot phase
rdvram_sched_q <= false;
rdvram_q <= true;
end if;
if wrvram_sched_q and clk_en_acc_i then
-- align scheduled write-back with access slot phase
wrvram_sched_q <= false;
wrvram_q <= true;
end if;
-- manage address -----------------------------------------------------
if load_addr_s then
addr_q(6 to 13) <= unsigned(tmp_q);
addr_q(0 to 5) <= unsigned(cd_i(2 to 7));
elsif incr_addr_v then
addr_q <= addr_q + 1;
end if;
-- palette
if write_pal_s then
if wrpal_byte2_s then
palette_val_s(8 to 15) <= cd_i;
incr_palidx_s <= true;
palette_idx_o <= std_logic_vector(palette_idx_s);
else
palette_val_s(0 to 7) <= cd_i;
end if;
end if;
if write_pal_v and not write_pal_s then
wrpal_byte2_s <= not wrpal_byte2_s;
end if;
write_pal_v := write_pal_s;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
vram_read_o <= rdvram_q;
vram_write_o <= wrvram_q;
-----------------------------------------------------------------------------
-- Process wback_ctrl
--
-- Purpose:
-- Write-back control.
--
wback_ctrl: process (clk_en_acc_i, access_type_i, wrvram_q)
begin
-- default assignments
abort_wrvram_s <= false;
incr_addr_s <= false;
vram_we_o <= '0';
if wrvram_q then
if access_type_i = AC_CPU then
-- signal write access to VRAM
vram_we_o <= '1';
if clk_en_acc_i then
-- clear write-back flag and increment address
abort_wrvram_s <= true;
incr_addr_s <= true;
end if;
end if;
end if;
end process wback_ctrl;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process reg_if
--
-- Purpose:
-- Implements the register interface.
--
reg_if: process (clock_i, reset_i)
variable reg_addr_v : unsigned(0 to 2);
variable incr_palidx_v : boolean := false;
begin
if reset_i then
tmp_q <= (others => '0');
ctrl_reg_q <= (others => (others => '0'));
sprite_coll_q <= false;
sprite_5th_q <= false;
sprite_5th_num_q <= (others => '0');
int_n_q <= '1';
-- p ragma translate_off
ctrl_reg_q(1) <= X"C0";
ctrl_reg_q(2) <= X"02";
ctrl_reg_q(3) <= X"2C";
ctrl_reg_q(7) <= X"F7";
-- p ragma translate_on
palette_idx_s <= X"0";
elsif clock_i'event and clock_i = '1' then
vertfreq_csw_o <= '0';
if clk_en_10m7_i then
-- Temporary register -------------------------------------------------
if write_tmp_s then
tmp_q <= cd_i;
end if;
-- Registers 0 to 7, 9 and 16 ---------------------------------------------------
if write_reg_s then
if cd_i(3 to 7) = "10000" then -- 16
palette_idx_s <= unsigned(tmp_q(4 to 7));
elsif cd_i(3 to 7) = "01001" then -- 9
vertfreq_d_o <= tmp_q(6);
vertfreq_csw_o <= '1';
else
reg_addr_v := unsigned(cd_i(5 to 7));
ctrl_reg_q(to_integer(reg_addr_v)) <= tmp_q;
end if;
end if;
if not incr_palidx_s and incr_palidx_v then
palette_idx_s <= palette_idx_s + 1;
end if;
incr_palidx_v := incr_palidx_s;
end if;
-- Fifth sprite handling ------------------------------------------------
if spr_5th_i and not sprite_5th_q then
sprite_5th_q <= true;
sprite_5th_num_q <= spr_5th_num_i;
elsif destr_rd_status_s then
sprite_5th_q <= false;
end if;
-- Sprite collision flag ------------------------------------------------
if spr_coll_i then
sprite_coll_q <= true;
elsif destr_rd_status_s then
sprite_coll_q <= false;
end if;
-- Interrupt ------------------------------------------------------------
if irq_i then
int_n_q <= '0';
elsif destr_rd_status_s then
int_n_q <= '1';
end if;
end if;
end process reg_if;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process access_ctrl
--
-- Purpose:
-- Implements the combinational logic for the CPU I/F FSM.
-- Decodes the CPU I/F FSM state and generates the control signals for the
-- register and VRAM logic.
--
access_ctrl: process (state_q, rd_i, wr_i, mode_i, cd_i, rdvram_q, wrvram_q)
type transfer_mode_t is (TM_NONE,
TM_RD_MODE0, TM_WR_MODE0,
TM_RD_MODE1, TM_WR_MODE1,
TM_WR_PALETTE);
variable transfer_mode_v : transfer_mode_t;
begin
-- default assignments
state_s <= state_q;
sched_rdvram_s <= false;
sched_wrvram_s <= false;
wrbuf_cpu_s <= false;
write_tmp_s <= false;
write_reg_s <= false;
load_addr_s <= false;
read_mux_s <= RDMUX_STATUS;
destr_rd_status_s <= false;
write_pal_s <= false;
wait_s <= '0';
-- determine transfer mode
transfer_mode_v := TM_NONE;
case mode_i is
when "00" =>
if rd_i then
transfer_mode_v := TM_RD_MODE0;
end if;
if wr_i then
if wrvram_q then
wait_s <= '1';
else
transfer_mode_v := TM_WR_MODE0;
end if;
end if;
when "01" =>
if rd_i then
transfer_mode_v := TM_RD_MODE1;
end if;
if wr_i then
transfer_mode_v := TM_WR_MODE1;
end if;
when "10" =>
if wr_i then
transfer_mode_v := TM_WR_PALETTE;
end if;
when others =>
null;
end case;
-- FSM state transitions
case state_q is
-- ST_IDLE: waiting for CPU access --------------------------------------
when ST_IDLE =>
case transfer_mode_v is
when TM_RD_MODE0 =>
state_s <= ST_RD_MODE0;
when TM_WR_MODE0 =>
state_s <= ST_WR_MODE0;
when TM_RD_MODE1 =>
state_s <= ST_RD_MODE1;
when TM_WR_MODE1 =>
state_s <= ST_WR_MODE1_1ST;
when TM_WR_PALETTE =>
state_s <= ST_WR_PALETTE;
when others =>
null;
end case;
-- ST_RD_MODE0: read from VRAM ------------------------------------------
when ST_RD_MODE0 =>
-- set read mux
read_mux_s <= RDMUX_READAHEAD;
if transfer_mode_v = TM_NONE then
-- CPU finished read access:
-- schedule new read-ahead and return to idle
state_s <= ST_IDLE;
sched_rdvram_s <= true;
end if;
-- ST_WR_MODE0: write to VRAM -------------------------------------------
when ST_WR_MODE0 =>
-- write data from CPU to write-back/read-ahead buffer
wrbuf_cpu_s <= true;
if transfer_mode_v = TM_NONE then
-- CPU finished write access:
-- schedule new write-back and return to idle
state_s <= ST_IDLE;
sched_wrvram_s <= true;
end if;
-- ST_RD_MODE1: read from status register -------------------------------
when ST_RD_MODE1 =>
-- set read mux
read_mux_s <= RDMUX_STATUS;
if transfer_mode_v = TM_NONE then
-- CPU finished read access:
-- destructive read of status register and return to IDLE
destr_rd_status_s <= true;
state_s <= ST_IDLE;
end if;
-- ST_WR_MODE1_1ST: save first byte -------------------------------------
when ST_WR_MODE1_1ST =>
-- update temp register
write_tmp_s <= true;
if transfer_mode_v = TM_NONE then
-- CPU finished write access:
-- become idle but remember that the first byte of a paired write
-- has been written
state_s <= ST_WR_MODE1_1ST_IDLE;
end if;
-- ST_WR_MODE1_1ST_IDLE: wait for next access ---------------------------
when ST_WR_MODE1_1ST_IDLE =>
-- determine type of next access
case transfer_mode_v is
when TM_RD_MODE0 =>
state_s <= ST_RD_MODE0;
when TM_WR_MODE0 =>
state_s <= ST_WR_MODE0;
when TM_RD_MODE1 =>
state_s <= ST_RD_MODE1;
when TM_WR_MODE1 =>
case cd_i(0 to 1) is
when "00" =>
state_s <= ST_WR_MODE1_2ND_VREAD;
when "01" =>
state_s <= ST_WR_MODE1_2ND_VWRITE;
when "10" | "11" =>
state_s <= ST_WR_MODE1_2ND_RWRITE;
when others =>
null;
end case;
when others =>
null;
end case;
-- ST_WR_MODE1_2ND_VREAD: write second byte of address, then read ahead -
when ST_WR_MODE1_2ND_VREAD =>
load_addr_s <= true;
if transfer_mode_v = TM_NONE then
-- CPU finished write access:
-- schedule new read-ahead and return to idle
sched_rdvram_s <= true;
state_s <= ST_IDLE;
end if;
-- ST_WR_MODE1_2ND_VWRITE: write second byte of address
when ST_WR_MODE1_2ND_VWRITE =>
load_addr_s <= true;
if transfer_mode_v = TM_NONE then
-- CPU finished write access:
-- return to idle
state_s <= ST_IDLE;
end if;
-- ST_WR_MODE1_2ND_RWRITE: write to register ----------------------------
when ST_WR_MODE1_2ND_RWRITE =>
write_reg_s <= true;
if transfer_mode_v = TM_NONE then
-- CPU finished write access:
-- return to idle
state_s <= ST_IDLE;
end if;
when ST_WR_PALETTE =>
write_pal_s <= true;
if transfer_mode_v = TM_NONE then
-- CPU finished write access:
-- prepare to second byte
state_s <= ST_IDLE;
end if;
when others =>
null;
end case;
end process access_ctrl;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process mode_decode
--
-- Purpose:
-- Decodes the display mode from the M1, M2, M3 bits.
--
mode_decode: process (ctrl_reg_q)
variable mode_v : std_logic_vector(0 to 2);
begin
mode_v := ctrl_reg_q(1)(3) & -- M1
ctrl_reg_q(1)(4) & -- M2
ctrl_reg_q(0)(6); -- M3
case mode_v is
when "000" =>
opmode_o <= OPMODE_GRAPH1;
when "001" =>
opmode_o <= OPMODE_GRAPH2;
when "010" =>
opmode_o <= OPMODE_MULTIC;
when "100" =>
opmode_o <= OPMODE_TEXTM;
when others =>
opmode_o <= OPMODE_TEXTM;
end case;
end process mode_decode;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Build status register
-----------------------------------------------------------------------------
status_reg_s <= not int_n_q &
to_std_logic_f(sprite_5th_q) &
to_std_logic_f(sprite_coll_q) &
sprite_5th_num_q;
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
vram_a_o <= std_logic_vector(addr_q);
vram_d_o <= buffer_q;
cd_o <= buffer_q when read_mux_s = RDMUX_READAHEAD else status_reg_s;
cd_oe_o <= '1' when rd_i else '0';
reg_ev_o <= to_boolean_f(ctrl_reg_q(0)(7));
reg_16k_o <= to_boolean_f(ctrl_reg_q(1)(0));
reg_blank_o <= not to_boolean_f(ctrl_reg_q(1)(1));
reg_size1_o <= to_boolean_f(ctrl_reg_q(1)(6));
reg_mag1_o <= to_boolean_f(ctrl_reg_q(1)(7));
reg_ntb_o <= ctrl_reg_q(2)(4 to 7);
reg_ctb_o <= ctrl_reg_q(3);
reg_pgb_o <= ctrl_reg_q(4)(5 to 7);
reg_satb_o <= ctrl_reg_q(5)(1 to 7);
reg_spgb_o <= ctrl_reg_q(6)(5 to 7);
reg_col1_o <= ctrl_reg_q(7)(0 to 3);
reg_col0_o <= ctrl_reg_q(7)(4 to 7);
int_n_o <= int_n_q or not ctrl_reg_q(1)(2);
palette_val_o <= palette_val_s;
palette_wr_o <= to_std_logic_f(incr_palidx_s) when palette_idx_s /= 0 else '0';
wait_o <= wait_s;
end rtl;
|
gpl-3.0
|
15975e1b4cc5cd35b020cee7c6b62ae9
| 0.5143 | 3.082494 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/vm2413/vm2413.vhd
| 2 | 7,612 |
--
-- VM2413.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package VM2413 is
subtype REGS_VECTOR_TYPE is std_logic_vector(23 downto 0);
type REGS_TYPE is record
INST : std_logic_vector(3 downto 0);
VOL : std_logic_vector(3 downto 0);
SUS : std_logic;
KEY : std_logic;
BLK : std_logic_vector(2 downto 0);
FNUM : std_logic_vector(8 downto 0);
end record;
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE;
subtype VOICE_VECTOR_TYPE is std_logic_vector(35 downto 0);
type VOICE_TYPE is record
AM, PM, EG, KR : std_logic;
ML : std_logic_vector(3 downto 0);
KL : std_logic_vector(1 downto 0);
TL : std_logic_vector(5 downto 0);
WF : std_logic;
FB : std_logic_vector(2 downto 0);
AR, DR, SL, RR : std_logic_vector(3 downto 0);
end record;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE;
-- Voice Parameter Types
-- subtype AM_TYPE is std_logic; -- AM switch - '0':off '1':3.70Hz
-- subtype PM_TYPE is std_logic; -- PM switch - '0':stop '1':6.06Hz
-- subtype EG_TYPE is std_logic; -- Envelope type - '0':release '1':sustine
-- subtype KR_TYPE is std_logic; -- Keyscale Rate
-- subtype ML_TYPE is std_logic_vector(3 downto 0); -- Multiple
-- subtype WF_TYPE is std_logic; -- WaveForm - '0':sine '1':half-sine
-- subtype FB_TYPE is std_logic_vector(2 downto 0); -- Feedback
-- subtype AR_TYPE is std_logic_vector(3 downto 0); -- Attack Rate
-- subtype DR_TYPE is std_logic_vector(3 downto 0); -- Decay Rate
-- subtype SL_TYPE is std_logic_vector(3 downto 0); -- Sustine Level
-- subtype RR_TYPE is std_logic_vector(3 downto 0); -- Release Rate
-- F-Number, Block and Rks(Rate and key-scale) types
-- subtype BLK_TYPE is std_logic_vector(2 downto 0); -- Block
-- subtype FNUM_TYPE is std_logic_vector(8 downto 0); -- F-Number
-- subtype RKS_TYPE is std_logic_vector(3 downto 0); -- Rate-KeyScale
-- 18 bits phase counter
-- subtype PHASE_TYPE is std_logic_vector (17 downto 0);
-- Phage generator's output
-- subtype PGOUT_TYPE is std_logic_vector (8 downto 0);
-- Final linear output of opll
subtype LI_TYPE is std_logic_vector (8 downto 0); -- Wave in Linear
-- Total Level and Envelope output
subtype DB_TYPE is std_logic_vector(6 downto 0); -- Wave in dB, Reso: 0.375dB
subtype SIGNED_LI_VECTOR_TYPE is std_logic_vector(LI_TYPE'high + 1 downto 0);
type SIGNED_LI_TYPE is record
sign : std_logic;
value : LI_TYPE;
end record;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE;
subtype SIGNED_DB_VECTOR_TYPE is std_logic_vector(DB_TYPE'high + 1 downto 0);
type SIGNED_DB_TYPE is record
sign : std_logic;
value : DB_TYPE;
end record;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE;
-- Envelope generator states
subtype EGSTATE_TYPE is std_logic_vector(1 downto 0);
constant Attack : EGSTATE_TYPE := "01";
constant Decay : EGSTATE_TYPE := "10";
constant Release : EGSTATE_TYPE := "11";
constant Finish : EGSTATE_TYPE := "00";
-- Envelope generator phase
subtype EGPHASE_TYPE is std_logic_vector(22 downto 0);
-- Envelope data (state and phase)
type EGDATA_TYPE is record
state : EGSTATE_TYPE;
phase : EGPHASE_TYPE;
end record;
subtype EGDATA_VECTOR_TYPE is std_logic_vector(EGSTATE_TYPE'high + EGPHASE_TYPE'high + 1 downto 0);
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE;
end VM2413;
package body VM2413 is
function CONV_REGS_VECTOR ( regs : REGS_TYPE ) return REGS_VECTOR_TYPE is
begin
return regs.INST & regs.VOL & "00" & regs.SUS & regs.KEY & regs.BLK & regs.FNUM;
end CONV_REGS_VECTOR;
function CONV_REGS ( vec : REGS_VECTOR_TYPE ) return REGS_TYPE is
begin
return (
INST=>vec(23 downto 20), VOL=>vec(19 downto 16),
SUS=>vec(13), KEY=>vec(12), BLK=>vec(11 downto 9), FNUM=>vec(8 downto 0)
);
end CONV_REGS;
function CONV_VOICE_VECTOR ( inst : VOICE_TYPE ) return VOICE_VECTOR_TYPE is
begin
return inst.AM & inst.PM & inst.EG & inst.KR &
inst.ML & inst.KL & inst.TL & inst.WF & inst.FB &
inst.AR & inst.DR & inst.SL & inst.RR;
end CONV_VOICE_VECTOR;
function CONV_VOICE ( inst_vec : VOICE_VECTOR_TYPE ) return VOICE_TYPE is
begin
return (
AM=>inst_vec(35), PM=>inst_vec(34), EG=>inst_vec(33), KR=>inst_vec(32),
ML=>inst_vec(31 downto 28), KL=>inst_vec(27 downto 26), TL=>inst_vec(25 downto 20),
WF=>inst_vec(19), FB=>inst_vec(18 downto 16),
AR=>inst_vec(15 downto 12), DR=>inst_vec(11 downto 8), SL=>inst_vec(7 downto 4), RR=>inst_vec(3 downto 0)
);
end CONV_VOICE;
function CONV_SIGNED_LI_VECTOR( li : SIGNED_LI_TYPE ) return SIGNED_LI_VECTOR_TYPE is
begin
return li.sign & li.value;
end;
function CONV_SIGNED_LI( vec : SIGNED_LI_VECTOR_TYPE ) return SIGNED_LI_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_SIGNED_DB_VECTOR( db : SIGNED_DB_TYPE ) return SIGNED_DB_VECTOR_TYPE is
begin
return db.sign & db.value;
end;
function CONV_SIGNED_DB( vec : SIGNED_DB_VECTOR_TYPE ) return SIGNED_DB_TYPE is
begin
return ( sign => vec(vec'high), value=>vec(vec'high-1 downto 0) );
end;
function CONV_EGDATA_VECTOR( data : EGDATA_TYPE ) return EGDATA_VECTOR_TYPE is
begin
return data.state & data.phase;
end;
function CONV_EGDATA( vec : EGDATA_VECTOR_TYPE ) return EGDATA_TYPE is
begin
return ( state => vec(vec'high downto EGPHASE_TYPE'high + 1),
phase => vec(EGPHASE_TYPE'range) );
end;
end VM2413;
|
gpl-3.0
|
d33baeac25e910957be235dd83a3058c
| 0.689963 | 3.407341 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd
| 1 | 3,528 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dbe_wishbone_pkg.all;
use work.wishbone_pkg.all;
entity xwb_dbe_periph is
generic(
-- NOT used!
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
-- NOT used!
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cntr_period : integer := 100000; -- 100MHz clock, ms granularity
g_num_leds : natural := 8;
g_num_buttons : natural := 8
);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- LEDs
led_out_o : out std_logic_vector(g_num_leds-1 downto 0);
led_in_i : in std_logic_vector(g_num_leds-1 downto 0);
led_oen_o : out std_logic_vector(g_num_leds-1 downto 0);
-- Buttons
button_out_o : out std_logic_vector(g_num_buttons-1 downto 0);
button_in_i : in std_logic_vector(g_num_buttons-1 downto 0);
button_oen_o : out std_logic_vector(g_num_buttons-1 downto 0);
-- Wishbone
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end xwb_dbe_periph;
architecture rtl of xwb_dbe_periph is
begin
cmp_wb_dbe_periph : wb_dbe_periph
generic map (
-- NOT used!
g_interface_mode => g_interface_mode,
-- NOT used!
g_address_granularity => g_address_granularity,
g_cntr_period => g_cntr_period,
g_num_leds => g_num_leds,
g_num_buttons => g_num_buttons
)
port map(
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
-- UART
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- LEDs
led_out_o => led_out_o,
led_in_i => led_in_i,
led_oen_o => led_oen_o,
-- Buttons
button_out_o => button_out_o,
button_in_i => button_in_i,
button_oen_o => button_oen_o,
-- Wishbone
wb_adr_i => slave_i.adr,
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_sel_i => slave_i.sel,
wb_we_i => slave_i.we,
wb_cyc_i => slave_i.cyc,
wb_stb_i => slave_i.stb,
wb_ack_o => slave_o.ack,
wb_err_o => slave_o.err,
wb_rty_o => slave_o.rty,
wb_stall_o => slave_o.stall
);
end rtl;
|
lgpl-3.0
|
dafdee48be0f79196642f04809bb6680
| 0.371032 | 4.160377 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dm_iob.vhd
| 1 | 23,232 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_dm_iob.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- This module places the data mask signals into the IOBs.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_dm_iob.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_dm_iob.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_dm_iob is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
nCWL : integer := 5; -- CAS Write Latency
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
WRLVL : string := "ON"; -- "OFF" for "DDR3" component interface
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic;
clk : in std_logic;
clk_rsync : in std_logic;
rst : in std_logic;
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0);
dm_ce : in std_logic;
inv_dqs : in std_logic;
wr_calib_dly : in std_logic_vector(1 downto 0);
mask_data_rise0 : in std_logic;
mask_data_fall0 : in std_logic;
mask_data_rise1 : in std_logic;
mask_data_fall1 : in std_logic;
ddr_dm : out std_logic
);
end phy_dm_iob;
architecture trans_phy_dm_iob of phy_dm_iob is
-- Set performance mode for IODELAY (power vs. performance tradeoff)
function CALC_HIGH_PERF_MODE return boolean is
begin
if (IODELAY_HP_MODE = "OFF") then
return FALSE;
elsif (IODELAY_HP_MODE = "ON") then
return TRUE;
else
return FALSE;
end if;
end function CALC_HIGH_PERF_MODE;
constant HIGH_PERFORMANCE_MODE : boolean := CALC_HIGH_PERF_MODE;
signal dm_odelay : std_logic;
signal dm_oq : std_logic;
signal mask_data_fall0_r1 : std_logic;
signal mask_data_fall0_r2 : std_logic;
signal mask_data_fall0_r3 : std_logic;
signal mask_data_fall0_r4 : std_logic;
signal mask_data_fall1_r1 : std_logic;
signal mask_data_fall1_r2 : std_logic;
signal mask_data_fall1_r3 : std_logic;
signal mask_data_fall1_r4 : std_logic;
signal mask_data_rise0_r1 : std_logic;
signal mask_data_rise0_r2 : std_logic;
signal mask_data_rise0_r3 : std_logic;
signal mask_data_rise0_r4 : std_logic;
signal mask_data_rise1_r1 : std_logic;
signal mask_data_rise1_r2 : std_logic;
signal mask_data_rise1_r3 : std_logic;
signal mask_data_rise1_r4 : std_logic;
signal out_d1 : std_logic;
signal out_d2 : std_logic;
signal out_d3 : std_logic;
signal out_d4 : std_logic;
signal xhdl1 : std_logic_vector(2 downto 0);
attribute IODELAY_GROUP : string;
attribute IODELAY_GROUP of u_odelay_dm : label is IODELAY_GRP;
begin
-- drive xhdl1 from wr_calib_dly(1 downto 0) and inv_dqs
xhdl1 <= wr_calib_dly(1 downto 0) & inv_dqs;
--***************************************************************************
-- Data Mask Bitslip
--***************************************************************************
-- dfi_wrdata_en0 - even clk cycles channel 0
-- dfi_wrdata_en1 - odd clk cycles channel 1
-- tphy_wrlat set to 0 clk cycle for CWL = 5,6,7,8
-- Valid dfi_wrdata* sent 1 clk cycle after dfi_wrdata_en* is asserted
-- mask_data_rise0 - first rising edge data mask (rise0)
-- mask_data_fall0 - first falling edge data mask (fall0)
-- mask_data_rise1 - second rising edge data mask (rise1)
-- mask_data_fall1 - second falling edge data mask (fall1)
process (clk)
begin
if (clk'event and clk = '1') then
if (DRAM_TYPE = "DDR3") then
mask_data_rise0_r1 <= dm_ce and mask_data_rise0 after (TCQ)*1 ps;
mask_data_fall0_r1 <= dm_ce and mask_data_fall0 after (TCQ)*1 ps;
mask_data_rise1_r1 <= dm_ce and mask_data_rise1 after (TCQ)*1 ps;
mask_data_fall1_r1 <= dm_ce and mask_data_fall1 after (TCQ)*1 ps;
else
mask_data_rise0_r1 <= mask_data_rise0 after (TCQ)*1 ps;
mask_data_fall0_r1 <= mask_data_fall0 after (TCQ)*1 ps;
mask_data_rise1_r1 <= mask_data_rise1 after (TCQ)*1 ps;
mask_data_fall1_r1 <= mask_data_fall1 after (TCQ)*1 ps;
end if;
mask_data_rise0_r2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
mask_data_fall0_r2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
mask_data_rise1_r2 <= mask_data_rise1_r1 after (TCQ)*1 ps;
mask_data_fall1_r2 <= mask_data_fall1_r1 after (TCQ)*1 ps;
mask_data_rise0_r3 <= mask_data_rise0_r2 after (TCQ)*1 ps;
mask_data_fall0_r3 <= mask_data_fall0_r2 after (TCQ)*1 ps;
mask_data_rise1_r3 <= mask_data_rise1_r2 after (TCQ)*1 ps;
mask_data_fall1_r3 <= mask_data_fall1_r2 after (TCQ)*1 ps;
mask_data_rise0_r4 <= mask_data_rise0_r3 after (TCQ)*1 ps;
mask_data_fall0_r4 <= mask_data_fall0_r3 after (TCQ)*1 ps;
mask_data_rise1_r4 <= mask_data_rise1_r3 after (TCQ)*1 ps;
mask_data_fall1_r4 <= mask_data_fall1_r3 after (TCQ)*1 ps;
end if;
end process;
-- Different nCWL values: 5, 6, 7, 8, 9
gen_dm_ddr3_write_lat : if (DRAM_TYPE = "DDR3") generate
gen_dm_ncwl5_odd : if ((nCWL = 5) or (nCWL = 7) or (nCWL = 9)) generate
process (clk)
begin
if (clk'event and clk = '1') then
if (WRLVL = "OFF") then
out_d1 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r1 after (TCQ)*1 ps;
else
-- write command sent by MC on channel1
-- D3,D4 inputs of the OCB used to send write command to DDR3
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl1) is
-- 0 clk_mem delay required as per write calibration
when "000" =>
out_d1 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0 after (TCQ)*1 ps;
-- DQS inverted during write leveling
when "001" =>
out_d1 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r1 after (TCQ)*1 ps;
-- 1 clk_mem delay required as per write cal
when "010" =>
out_d1 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 1 clk_mem delay required as per write cal
when "011" =>
out_d1 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r1 after (TCQ)*1 ps;
-- 2 clk_mem delay required as per write cal
when "100" =>
out_d1 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 2 clk_mem delay required as per write cal
when "101" =>
out_d1 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r2 after (TCQ)*1 ps;
-- 3 clk_mem delay required as per write cal
when "110" =>
out_d1 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 3 clk_mem delay required as per write cal
when "111" =>
out_d1 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r2 after (TCQ)*1 ps;
-- defaults to 0 clk_mem delay
when others =>
out_d1 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0 after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
gen_dm_ncwl_even : if ((nCWL = 6) or (nCWL = 8)) generate
process (clk)
begin
if (clk'event and clk = '1') then
if (WRLVL = "OFF") then
out_d1 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r1 after (TCQ)*1 ps;
else
-- write command sent by MC on channel1
-- D3,D4 inputs of the OCB used to send write command to DDR3
-- Shift bitslip logic by 1 or 2 clk_mem cycles
-- Write calibration currently supports only upto 2 clk_mem cycles
case (xhdl1) is
-- 0 clk_mem delay required as per write calibration
-- could not test 0011 case
when "000" =>
out_d1 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
when "001" =>
out_d1 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r1 after (TCQ)*1 ps;
-- 1 clk_mem delay required as per write cal
when "010" =>
out_d1 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0_r1 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 1 clk_mem delay required as per write cal
when "011" =>
out_d1 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r2 after (TCQ)*1 ps;
-- 2 clk_mem delay required as per write cal
when "100" =>
out_d1 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 2 clk_mem delay required as per write cal
when "101" =>
out_d1 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_rise0_r2 after (TCQ)*1 ps;
out_d4 <= mask_data_fall0_r2 after (TCQ)*1 ps;
-- 3 clk_mem delay required as per write cal
when "110" =>
out_d1 <= mask_data_fall0_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_fall1_r3 after (TCQ)*1 ps;
out_d4 <= mask_data_rise0_r2 after (TCQ)*1 ps;
-- DQS inverted during write leveling
-- 3 clk_mem delay required as per write cal
when "111" =>
out_d1 <= mask_data_rise0_r3 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r3 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r3 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r3 after (TCQ)*1 ps;
-- defaults to 0 clk_mem delay
when others =>
out_d1 <= mask_data_fall1_r2 after (TCQ)*1 ps;
out_d2 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_rise1_r1 after (TCQ)*1 ps;
end case;
end if;
end if;
end process;
end generate;
end generate;
gen_dm_lat_ddr2 : if (DRAM_TYPE = "DDR2") generate
gen_ddr2_ncwl2 : if (nCWL = 2) generate
process (mask_data_rise1_r1, mask_data_fall1_r1, mask_data_rise0, mask_data_fall0)
begin
out_d1 <= mask_data_rise1_r1;
out_d2 <= mask_data_fall1_r1;
out_d3 <= mask_data_rise0;
out_d4 <= mask_data_fall0;
end process;
end generate;
gen_ddr2_ncwl3 : if (nCWL = 3) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise0 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1 after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr2_ncwl4 : if (nCWL = 4) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise1_r1 ;
out_d2 <= mask_data_fall1_r1 ;
out_d3 <= mask_data_rise0 ;
out_d4 <= mask_data_fall0 ;
end if;
end process;
end generate;
gen_ddr2_ncwl5 : if (nCWL = 5) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise0_r1 after (TCQ)*1 ps;
out_d2 <= mask_data_fall0_r1 after (TCQ)*1 ps;
out_d3 <= mask_data_rise1_r1 after (TCQ)*1 ps;
out_d4 <= mask_data_fall1_r1 after (TCQ)*1 ps;
end if;
end process;
end generate;
gen_ddr2_ncwl6 : if (nCWL = 6) generate
process (clk)
begin
if (clk'event and clk = '1') then
out_d1 <= mask_data_rise1_r2;
out_d2 <= mask_data_fall1_r2;
out_d3 <= mask_data_rise0_r1;
out_d4 <= mask_data_fall0_r1;
end if;
end process;
end generate;
end generate;
--***************************************************************************
u_oserdes_dm : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '0',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => dm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => open,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => out_d1,
D2 => out_d2,
D3 => out_d3,
D4 => out_d4,
D5 => 'Z',
D6 => 'Z',
OCE => '1',
ODV => '0',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TFB => open,
TCE => '1',
WC => '0'
);
-- Output of OSERDES drives IODELAY (ODELAY)
u_odelay_dm : IODELAYE1
generic map (
cinvctrl_sel => FALSE,
delay_src => "O",
high_performance_mode => HIGH_PERFORMANCE_MODE,
idelay_type => "FIXED",
idelay_value => 0,
odelay_type => "VAR_LOADABLE",
odelay_value => 0,
refclk_frequency => REFCLK_FREQ,
signal_pattern => "DATA"
)
port map (
dataout => dm_odelay,
c => clk_rsync,
ce => '0',
datain => 'Z',
idatain => 'Z',
inc => '0',
odatain => dm_oq,
rst => '1',
t => 'Z',
cntvaluein => dlyval,
cntvalueout => open,
clkin => 'Z',
cinvctrl => '0'
);
-- Output of ODELAY drives OBUF
u_obuf_dm : OBUF
port map (
i => dm_odelay,
o => ddr_dm
);
end trans_phy_dm_iob;
|
lgpl-3.0
|
4dcad38d9356ecb228fa4a0d2939b4c4
| 0.471419 | 3.816032 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/mixeru.vhd
| 2 | 5,465 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.msx_pack.all;
entity mixeru is
port (
clock_i : in std_logic;
reset_i : in std_logic;
volumes_i : in volumes_t;
beep_i : in std_logic;
ear_i : in std_logic;
audio_scc_i : in signed(14 downto 0);
audio_psg_i : in unsigned(7 downto 0);
jt51_left_i : in signed(15 downto 0);
jt51_right_i : in signed(15 downto 0);
opll_mo_i : in signed(12 downto 0) := (others => '0');
opll_ro_i : in signed(12 downto 0) := (others => '0');
audio_mix_l_o : out unsigned(15 downto 0);
audio_mix_r_o : out unsigned(15 downto 0)
);
end mixeru;
-- 32767 0111111111111111
--
-- 1 0000000000000001
-- 0 0000000000000000
-- -1 1111111111111111
--
-- -32768 1000000000000000
architecture Behavioral of mixeru is
constant beep_con_c : unsigned(15 downto 0) := to_unsigned(16383, 16);
constant ear_con_c : unsigned(15 downto 0) := to_unsigned(16383, 16);
signal pcm_l_s : unsigned(15 downto 0);
signal pcm_r_s : unsigned(15 downto 0);
signal beep_con_s : unsigned(15 downto 0);
signal ear_con_s : unsigned(15 downto 0);
signal opll_sum_s : signed(12 downto 0);
signal beep_uns_s : unsigned(16 + volumes_i.beep'length downto 0);
signal ear_uns_s : unsigned(16 + volumes_i.ear'length downto 0);
signal psg_uns_s : unsigned(16 + volumes_i.psg'length downto 0);
signal scc_uns_s : unsigned(16 + volumes_i.scc'length downto 0);
signal opll_uns_s : unsigned(16 + volumes_i.opll'length downto 0);
signal jt51_l_uns_s : unsigned(16 + volumes_i.aux1'length downto 0);
signal jt51_r_uns_s : unsigned(16 + volumes_i.aux1'length downto 0);
begin
beep_con_s <= beep_con_c when beep_i = '1' else (others => '0');
ear_con_s <= ear_con_c when ear_i = '1' else (others => '0');
opll_sum_s <= opll_mo_i + opll_ro_i;
beep_uns_s <= beep_con_s * ('0' & unsigned(volumes_i.beep));
ear_uns_s <= ear_con_s * ('0' & unsigned(volumes_i.ear));
psg_uns_s <= ("00" & audio_psg_i & "000000") * ('0' & unsigned(volumes_i.psg));
scc_uns_s <= ('0' & not audio_scc_i(14) & unsigned(audio_scc_i (13 downto 0))) * ('0' & unsigned(volumes_i.scc));
opll_uns_s <= ('0' & not opll_sum_s(12) & unsigned(opll_sum_s (11 downto 0)) & "00") * ('0' & unsigned(volumes_i.opll));
jt51_l_uns_s <= ('0' & not jt51_left_i(15) & unsigned(jt51_left_i (14 downto 1))) * ('0' & unsigned(volumes_i.aux1));
jt51_r_uns_s <= ('0' & not jt51_right_i(15) & unsigned(jt51_right_i(14 downto 1))) * ('0' & unsigned(volumes_i.aux1));
pcm_l_s <= beep_uns_s(beep_uns_s'high downto beep_uns_s'high-15) +
ear_uns_s(ear_uns_s'high downto ear_uns_s'high-15) +
psg_uns_s(psg_uns_s'high downto psg_uns_s'high-15) +
scc_uns_s(scc_uns_s'high downto scc_uns_s'high-15) +
opll_uns_s(opll_uns_s'high downto opll_uns_s'high-15) +
jt51_l_uns_s(jt51_l_uns_s'high downto jt51_l_uns_s'high-15);
--
pcm_r_s <= beep_uns_s(beep_uns_s'high downto beep_uns_s'high-15) +
ear_uns_s(ear_uns_s'high downto ear_uns_s'high-15) +
psg_uns_s(psg_uns_s'high downto psg_uns_s'high-15) +
scc_uns_s(scc_uns_s'high downto scc_uns_s'high-15) +
opll_uns_s(opll_uns_s'high downto opll_uns_s'high-15) +
jt51_r_uns_s(jt51_r_uns_s'high downto jt51_r_uns_s'high-15);
audio_mix_l_o <= pcm_l_s;
audio_mix_r_o <= pcm_r_s;
end Behavioral;
|
gpl-3.0
|
a906fcb112f88641ddabafc2132346a2
| 0.644099 | 2.942919 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/shared/multiboot.vhd
| 2 | 9,053 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
-- Multiboot core
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity multiboot is
generic (
bit_g : integer := 4 -- 1 or 2 or 4
);
port(
reset_i : in std_logic;
clock_i : in std_logic;
start_i : in std_logic;
spi_addr_i : in std_logic_vector(23 downto 0) := X"000000"
);
end entity;
architecture Behavioral of multiboot is
----------------------------------------------------------------------------
-- ICAP configuration data codes
----------------------------------------------------------------------------
-- For custom data codes like the ones for reading back, take a look to:
-- [OPCODES] UG380 page 88 table 5-23
-- [CFG PACKETS] UG380 page 89 tables 5-{24, 25}
-- [CG REGISTERS] UG380 page 90 table 5-30
----------------------------------------------------------------------------
constant DUMMY_C : std_logic_vector(15 downto 0) := X"FFFF"; --
constant NOOP_C : std_logic_vector(15 downto 0) := X"2000"; --
constant NULL1_C : std_logic_vector(15 downto 0) := X"0000"; --
constant NULL2_C : std_logic_vector(15 downto 0) := X"1111"; --
constant SYNCH_C : std_logic_vector(15 downto 0) := X"AA99"; --
constant SYNCL_C : std_logic_vector(15 downto 0) := X"5566"; --
constant CMD_WR_GEN1_C : std_logic_vector(15 downto 0) := X"3261"; --
constant CMD_WR_GEN2_C : std_logic_vector(15 downto 0) := X"3281"; --
constant CMD_WR_CMD_C : std_logic_vector(15 downto 0) := X"30A1"; --
constant CMD_WR_MOD_C : std_logic_vector(15 downto 0) := X"3301"; --
constant CMD_IPROG_C : std_logic_vector(15 downto 0) := X"000E"; --
constant BIT1X_C : std_logic_vector(15 downto 0) := X"2100"; --
constant BIT2X_C : std_logic_vector(15 downto 0) := X"2900"; --
constant BIT4X_C : std_logic_vector(15 downto 0) := X"3100"; --
-- SPI commands
constant FASTREAD_C : std_logic_vector( 7 downto 0) := X"0B"; -- 1x
constant DUALREAD_C : std_logic_vector( 7 downto 0) := X"3B"; -- 2x
constant QUADREAD_C : std_logic_vector( 7 downto 0) := X"6B"; -- 4x
--
type states_t is (IDLE, SYNC_H, SYNC_L, GEN1_H, GEN1_L, GEN2_H, GEN2_L, NUL_H,
NUL_L, MOD_H, MOD_L, RBT_H, RBT_L, NOOP_0, NOOP_1, NOOP_2, NOOP_3);
signal state_s : states_t;
signal next_state_s : states_t;
signal icap_ce_r_s : std_logic;
signal icap_wr_r_s : std_logic;
signal icap_ce_s : std_logic;
signal icap_wr_s : std_logic;
signal icap_i_r_s : std_logic_vector(15 downto 0);
signal icap_i_s : std_logic_vector(15 downto 0);
signal modereg_s : std_logic_vector(15 downto 0);
signal spi_cmd_s : std_logic_vector( 7 downto 0);
begin
ICAP_SPARTAN6_inst : ICAP_SPARTAN6
port map (
CLK => clock_i, -- 1-bit input: Clock input
CE => icap_ce_s, -- 1-bit input: Active-Low ICAP Enable input
I => icap_i_s, -- 16-bit input: Configuration data input bus
WRITE => icap_wr_s -- 1-bit input: Read/Write control input
);
spi_cmd_s <= FASTREAD_C when bit_g = 1 else
DUALREAD_C when bit_g = 2 else
QUADREAD_C;
modereg_s <= BIT1X_C when bit_g = 1 else
BIT2X_C when bit_g = 2 else
BIT4X_C;
-- assign values
process(clock_i)
begin
if rising_edge(clock_i) then
-- First we order the bits according to UG380 Table2-5 page 37, as specified in page 126
icap_i_s(0) <= icap_i_r_s(7);
icap_i_s(1) <= icap_i_r_s(6);
icap_i_s(2) <= icap_i_r_s(5);
icap_i_s(3) <= icap_i_r_s(4);
icap_i_s(4) <= icap_i_r_s(3);
icap_i_s(5) <= icap_i_r_s(2);
icap_i_s(6) <= icap_i_r_s(1);
icap_i_s(7) <= icap_i_r_s(0);
icap_i_s(8) <= icap_i_r_s(15);
icap_i_s(9) <= icap_i_r_s(14);
icap_i_s(10) <= icap_i_r_s(13);
icap_i_s(11) <= icap_i_r_s(12);
icap_i_s(12) <= icap_i_r_s(11);
icap_i_s(13) <= icap_i_r_s(10);
icap_i_s(14) <= icap_i_r_s(9);
icap_i_s(15) <= icap_i_r_s(8);
icap_wr_s <= icap_wr_r_s;
icap_ce_s <= icap_ce_r_s;
end if;
end process;
-- next state
process(clock_i)
begin
if rising_edge(clock_i) then
if reset_i = '1' then
state_s <= IDLE;
else
state_s <= next_state_s;
end if;
end if;
end process;
-- FSM
process (state_s, start_i, spi_addr_i)
begin
case state_s is
when IDLE =>
if start_i = '1' then
next_state_s <= SYNC_H;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= SYNCH_C;
else
next_state_s <= IDLE;
icap_ce_r_s <= '1';
icap_wr_r_s <= '1';
icap_i_r_s <= DUMMY_C;
end if;
when SYNC_H =>
next_state_s <= SYNC_L;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= SYNCL_C;
when SYNC_L =>
next_state_s <= NUL_H;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= CMD_WR_CMD_C;
when NUL_H =>
next_state_s <= GEN1_H;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= NULL1_C;
when GEN1_H =>
next_state_s <= GEN1_L;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= CMD_WR_GEN1_C;
when GEN1_L =>
next_state_s <= GEN2_H;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= spi_addr_i(15 downto 0);
when GEN2_H =>
next_state_s <= GEN2_L;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= CMD_WR_GEN2_C;
when GEN2_L =>
next_state_s <= MOD_H;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= spi_cmd_s & spi_addr_i(23 downto 16);
when MOD_H =>
next_state_s <= MOD_L;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= CMD_WR_MOD_C;
when MOD_L =>
next_state_s <= NUL_L;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= modereg_s;
when NUL_L =>
next_state_s <= RBT_H;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= CMD_WR_CMD_C;
when RBT_H =>
next_state_s <= RBT_L;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= CMD_IPROG_C;
when RBT_L =>
next_state_s <= NOOP_0;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= NOOP_C;
when NOOP_0 =>
next_state_s <= NOOP_1;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= NOOP_C;
when NOOP_1 =>
next_state_s <= NOOP_2;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= NOOP_C;
when NOOP_2 =>
next_state_s <= NOOP_3;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= NOOP_C;
when NOOP_3 =>
next_state_s <= IDLE;
icap_ce_r_s <= '0';
icap_wr_r_s <= '0';
icap_i_r_s <= NULL2_C;
-- when others =>
-- next_state_s <= IDLE;
-- icap_ce_r_s <= '1';
-- icap_wr_r_s <= '1';
-- icap_i_r_s <= NULL2_C;
end case;
end process;
end architecture;
|
gpl-3.0
|
7dd9ea27dfadce0f9fd6ed4150bbf68c
| 0.54435 | 2.550859 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/hdmi/encoder.vhd
| 2 | 4,437 |
-------------------------------------------------------------------[01.11.2014]
-- Encoder
-------------------------------------------------------------------------------
-- Engineer: MVV <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder is
port (
CLK : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
C : in STD_LOGIC_VECTOR (1 downto 0);
VDE : in STD_LOGIC; -- Video Data Enable (VDE)
ADE : in STD_LOGIC; -- Audio/auxiliary Data Enable (ADE)
AUX : in STD_LOGIC_VECTOR (3 downto 0);
ENCODED : out STD_LOGIC_VECTOR (9 downto 0));
end encoder;
architecture rtl of encoder is
signal xored : STD_LOGIC_VECTOR (8 downto 0);
signal xnored : STD_LOGIC_VECTOR (8 downto 0);
signal ones : STD_LOGIC_VECTOR (3 downto 0);
signal data_word : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_inv : STD_LOGIC_VECTOR (8 downto 0);
signal data_word_disparity : STD_LOGIC_VECTOR (3 downto 0);
signal dc_bias : STD_LOGIC_VECTOR (3 downto 0) := (others => '0');
begin
-- Work our the two different encodings for the byte
xored(0) <= DATA(0);
xored(1) <= DATA(1) xor xored(0);
xored(2) <= DATA(2) xor xored(1);
xored(3) <= DATA(3) xor xored(2);
xored(4) <= DATA(4) xor xored(3);
xored(5) <= DATA(5) xor xored(4);
xored(6) <= DATA(6) xor xored(5);
xored(7) <= DATA(7) xor xored(6);
xored(8) <= '1';
xnored(0) <= DATA(0);
xnored(1) <= DATA(1) xnor xnored(0);
xnored(2) <= DATA(2) xnor xnored(1);
xnored(3) <= DATA(3) xnor xnored(2);
xnored(4) <= DATA(4) xnor xnored(3);
xnored(5) <= DATA(5) xnor xnored(4);
xnored(6) <= DATA(6) xnor xnored(5);
xnored(7) <= DATA(7) xnor xnored(6);
xnored(8) <= '0';
-- Count how many ones are set in data
ones <= "0000" + DATA(0) + DATA(1) + DATA(2) + DATA(3) + DATA(4) + DATA(5) + DATA(6) + DATA(7);
-- Decide which encoding to use
process (ones, DATA(0), xnored, xored)
begin
if ones > 4 or (ones = 4 and DATA(0) = '0') then
data_word <= xnored;
data_word_inv <= NOT(xnored);
else
data_word <= xored;
data_word_inv <= NOT(xored);
end if;
end process;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + data_word(0) + data_word(1) + data_word(2) + data_word(3) + data_word(4) + data_word(5) + data_word(6) + data_word(7);
-- Now work out what the output should be
process(CLK)
begin
if (CLK'event and CLK = '1') then
-- Video Data Coding
if VDE = '1' then
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if data_word(8) = '1' then
ENCODED <= "01" & data_word(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
else
ENCODED <= "10" & data_word_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
ENCODED <= '1' & data_word(8) & data_word_inv(7 downto 0);
dc_bias <= dc_bias + data_word(8) - data_word_disparity;
else
ENCODED <= '0' & data_word;
dc_bias <= dc_bias - data_word_inv(8) + data_word_disparity;
end if;
-- TERC4 Coding
elsif ADE = '1' then
case AUX is
when "0000" => ENCODED <= "1010011100";
when "0001" => ENCODED <= "1001100011";
when "0010" => ENCODED <= "1011100100";
when "0011" => ENCODED <= "1011100010";
when "0100" => ENCODED <= "0101110001";
when "0101" => ENCODED <= "0100011110";
when "0110" => ENCODED <= "0110001110";
when "0111" => ENCODED <= "0100111100";
when "1000" => ENCODED <= "1011001100";
when "1001" => ENCODED <= "0100111001";
when "1010" => ENCODED <= "0110011100";
when "1011" => ENCODED <= "1011000110";
when "1100" => ENCODED <= "1010001110";
when "1101" => ENCODED <= "1001110001";
when "1110" => ENCODED <= "0101100011";
when others => ENCODED <= "1011000011";
end case;
else
-- In the control periods, all values have and have balanced bit count
case C is
when "00" => ENCODED <= "1101010100";
when "01" => ENCODED <= "0010101011";
when "10" => ENCODED <= "0101010100";
when others => ENCODED <= "1010101011";
end case;
dc_bias <= (others => '0');
end if;
end if;
end process;
end rtl;
|
gpl-3.0
|
946e5af2119970f49f5502bb1e0cd323
| 0.566374 | 2.971869 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_dqs_iob.vhd
| 1 | 16,487 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_dqs_iob.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Instantiates I/O-related logic for DQS. Contains logic for both write
-- and read (phase detection) paths.
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_dqs_iob.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_dqs_iob.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_dqs_iob is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
DRAM_TYPE : string := "DDR3"; -- Memory I/F type: "DDR3", "DDR2"
REFCLK_FREQ : real := 300.0; -- IODELAY Reference Clock freq (MHz)
IBUF_LPWR_MODE : string := "OFF"; -- Input buffer low power mode
IODELAY_HP_MODE : string := "ON"; -- IODELAY High Performance Mode
IODELAY_GRP : string := "IODELAY_MIG" -- May be assigned unique name
-- when mult IP cores in design
);
port (
clk_mem : in std_logic; -- memory-rate clock
clk : in std_logic; -- internal (logic) clock
clk_cpt : in std_logic; -- read capture clock
clk_rsync : in std_logic; -- resynchronization (read) clock
rst : in std_logic; -- reset sync'ed to CLK
rst_rsync : in std_logic; -- reset sync'ed to RSYNC
-- IODELAY I/F
dlyval : in std_logic_vector(4 downto 0); -- IODELAY (DQS) parallel load value
-- Write datapath I/F
dqs_oe_n : in std_logic_vector(3 downto 0); -- DQS output enable
dqs_rst : in std_logic_vector(3 downto 0); -- D4 input of OSERDES: 1- for normal, 0- for WL
-- Read datapath I/F
rd_bitslip_cnt : in std_logic_vector(1 downto 0);
rd_clkdly_cnt : in std_logic_vector(1 downto 0);
rd_clkdiv_inv : in std_logic;
rd_dqs_rise0 : out std_logic; -- DQS captured in clk_cpt domain
rd_dqs_fall0 : out std_logic; -- used by Phase Detector. Monitor DQS
rd_dqs_rise1 : out std_logic;
rd_dqs_fall1 : out std_logic;
-- DDR3 bus signals
ddr_dqs_p : inout std_logic;
ddr_dqs_n : inout std_logic;
-- Debug Port
dqs_tap_cnt : out std_logic_vector(4 downto 0)
);
end phy_dqs_iob;
architecture trans_phy_dqs_iob of phy_dqs_iob is
-- Set performance mode for IODELAY (power vs. performance tradeoff)
function CALC_HIGH_PERF_MODE return boolean is
begin
if (IODELAY_HP_MODE = "OFF") then
return FALSE;
elsif (IODELAY_HP_MODE = "ON") then
return TRUE;
else
return FALSE;
end if;
end function CALC_HIGH_PERF_MODE;
-- Enable low power mode for input buffer
function CALC_IBUF_LOW_PWR return boolean is
begin
if (IBUF_LPWR_MODE = "OFF") then
return FALSE;
elsif (IBUF_LPWR_MODE = "ON") then
return TRUE;
else
return FALSE;
end if;
end function CALC_IBUF_LOW_PWR;
constant HIGH_PERFORMANCE_MODE : boolean := CALC_HIGH_PERF_MODE;
constant IBUF_LOW_PWR : boolean := CALC_IBUF_LOW_PWR;
signal dqs_ibuf_n : std_logic;
signal dqs_ibuf_p : std_logic;
signal dqs_n_iodelay : std_logic;
signal dqs_n_tfb : std_logic;
signal dqs_n_tq : std_logic;
signal dqs_p_iodelay : std_logic;
signal dqs_p_tfb : std_logic;
signal dqs_p_oq : std_logic;
signal dqs_p_tq : std_logic;
signal iserdes_clk : std_logic;
signal iserdes_clkb : std_logic;
signal iserdes_q : std_logic_vector(5 downto 0);
signal iserdes_q_mux : std_logic_vector(5 downto 0);
signal iserdes_q_neg_r : std_logic_vector(5 downto 0);
signal iserdes_q_r : std_logic_vector(5 downto 0);
signal rddata : std_logic_vector(3 downto 0);
------ rd_bitslip component -------
component rd_bitslip
generic (
TCQ : integer := 100
);
port (
clk : in std_logic;
bitslip_cnt : in std_logic_vector(1 downto 0);
clkdly_cnt : in std_logic_vector(1 downto 0);
din : in std_logic_vector(5 downto 0);
qout : out std_logic_vector(3 downto 0)
);
end component;
attribute IODELAY_GROUP : string;
attribute IODELAY_GROUP of u_iodelay_dqs_p_early : label is IODELAY_GRP;
begin
--***************************************************************************
-- Strobe Bidirectional I/O
--***************************************************************************
u_iobuf_dqs: IOBUFDS_DIFF_OUT
generic map (
IBUF_LOW_PWR => IBUF_LOW_PWR
)
port map (
o => dqs_ibuf_p,
ob => dqs_ibuf_n,
io => ddr_dqs_p,
iob => ddr_dqs_n,
i => dqs_p_iodelay,
tm => dqs_p_tq,
ts => dqs_n_tq
);
--***************************************************************************
-- Programmable Delay element - the "P"-side is used for both input and
-- output paths. The N-side is used for tri-state control of N-side I/O
-- buffer and can possibly be used as as an input (complement of P-side)
-- for the read phase detector
--***************************************************************************
u_iodelay_dqs_p_early : IODELAYE1
generic map (
CINVCTRL_SEL => FALSE,
DELAY_SRC => "IO",
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => 0,
ODELAY_TYPE => "VAR_LOADABLE",
ODELAY_VALUE => 0,
REFCLK_FREQUENCY => REFCLK_FREQ
)
port map (
DATAOUT => dqs_p_iodelay,
C => clk_rsync,
CE => '0',
DATAIN => '0',
IDATAIN => dqs_ibuf_p,
INC => '0',
ODATAIN => dqs_p_oq,
RST => '1',
T => dqs_p_tfb,
CNTVALUEIN => dlyval,
CNTVALUEOUT => dqs_tap_cnt,
CLKIN => 'Z',
CINVCTRL => '0'
);
--***************************************************************************
-- Write Path
--***************************************************************************
u_oserdes_dqs_p : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '0',
INIT_TQ => '1',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => dqs_p_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => dqs_p_tq,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => dqs_rst(0),
D2 => dqs_rst(1),
D3 => dqs_rst(2),
D4 => dqs_rst(3),
D5 => 'Z',
D6 => 'Z',
OCE => '1',
ODV => '0',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst,
T1 => dqs_oe_n(0),
T2 => dqs_oe_n(1),
T3 => dqs_oe_n(2),
T4 => dqs_oe_n(3),
TFB => dqs_p_tfb,
TCE => '1',
WC => '0'
);
u_oserdes_dqs_n : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 0,
INIT_OQ => '1',
INIT_TQ => '1',
INTERFACE_TYPE => "DEFAULT",
ODELAY_USED => 0,
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 4
)
port map (
OCBEXTEND => open,
OFB => open,
OQ => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TQ => dqs_n_tq,
CLK => clk_mem,
CLKDIV => clk,
CLKPERF => 'Z',
CLKPERFDELAY => 'Z',
D1 => '0',
D2 => '0',
D3 => '0',
D4 => '0',
D5 => 'Z',
D6 => 'Z',
OCE => '1',
ODV => '0',
SHIFTIN1 => 'Z',
SHIFTIN2 => 'Z',
RST => rst,
T1 => dqs_oe_n(0),
T2 => dqs_oe_n(1),
T3 => dqs_oe_n(2),
T4 => dqs_oe_n(3),
TFB => dqs_n_tfb,
TCE => '1',
WC => '0'
);
--***************************************************************************
-- Read Path
--***************************************************************************
-- Assign equally to avoid delta-delay issues in simulation
iserdes_clk <= clk_cpt;
iserdes_clkb <= not(clk_cpt);
u_iserdes_dqs_p : ISERDESE1
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 4,
DYN_CLKDIV_INV_EN => TRUE,
DYN_CLK_INV_EN => FALSE,
INIT_Q1 => '0',
INIT_Q2 => '0',
INIT_Q3 => '0',
INIT_Q4 => '0',
INTERFACE_TYPE => "MEMORY_DDR3",
NUM_CE => 2,
IOBDELAY => "IFD",
OFB_USED => FALSE,
SERDES_MODE => "MASTER",
SRVAL_Q1 => '0',
SRVAL_Q2 => '0',
SRVAL_Q3 => '0',
SRVAL_Q4 => '0'
)
port map (
O => open,
Q1 => iserdes_q(0),
Q2 => iserdes_q(1),
Q3 => iserdes_q(2),
Q4 => iserdes_q(3),
Q5 => iserdes_q(4),
Q6 => iserdes_q(5),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => '0',
CE1 => '1',
CE2 => '1',
CLK => iserdes_clk,
CLKB => iserdes_clkb,
CLKDIV => clk_rsync,
D => 'Z',
DDLY => dqs_p_iodelay,
DYNCLKDIVSEL => rd_clkdiv_inv,
DYNCLKSEL => '0',
OCLK => clk_mem, -- Not used, but connect to avoid DRC
OFB => '0',
RST => rst_rsync,
SHIFTIN1 => '0',
SHIFTIN2 => '0'
);
--*****************************************************************
-- Selectable registers on ISERDES data outputs depending on
-- whether DYNCLKDIVSEL is enabled or not
--*****************************************************************
-- Capture first using CLK_RSYNC falling edge domain, then transfer
-- to rising edge CLK_RSYNC. We could also attempt to transfer
-- directly from falling edge CLK_RSYNC domain (in ISERDES) to
-- rising edge CLK_RSYNC domain in fabric. This is allowed as long
-- as the half-cycle timing on these paths can be met.
process (clk_rsync)
begin
if (clk_rsync'event and clk_rsync = '0') then
iserdes_q_neg_r <= iserdes_q after (TCQ)*1 ps;
end if;
end process;
process (clk_rsync)
begin
if (clk_rsync'event and clk_rsync = '1') then
iserdes_q_r <= iserdes_q_neg_r after (TCQ)*1 ps;
end if;
end process;
iserdes_q_mux <= iserdes_q_r when (rd_clkdiv_inv = '1') else
iserdes_q;
--*****************************************************************
-- Read bitslip logic
--*****************************************************************
u_rd_bitslip_early: rd_bitslip
generic map(
TCQ => TCQ
)
port map(
clk => clk_rsync,
bitslip_cnt => rd_bitslip_cnt,
clkdly_cnt => rd_clkdly_cnt,
din => iserdes_q_mux,
qout => rddata
);
rd_dqs_rise0 <= rddata(3);
rd_dqs_fall0 <= rddata(2);
rd_dqs_rise1 <= rddata(1);
rd_dqs_fall1 <= rddata(0);
end trans_phy_dqs_iob;
|
lgpl-3.0
|
347722a5b4ae110b12259ca6033f096b
| 0.446412 | 4.178155 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ip_top/iodelay_ctrl.vhd
| 1 | 8,247 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: iodelay_ctrl.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:11 $
-- \ \ / \ Date Created: Wed Aug 16 2006
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- This module instantiates the IDELAYCTRL primitive, which continously
-- calibrates the IODELAY elements in the region to account for varying
-- environmental conditions. A 200MHz or 300MHz reference clock (depending
-- on the desired IODELAY tap resolution) must be supplied
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: iodelay_ctrl.vhd,v 1.1 2011/06/02 07:18:11 mishra Exp $
--**$Date: 2011/06/02 07:18:11 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/ip_top/iodelay_ctrl.vhd,v $
--******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity iodelay_ctrl is
generic (
TCQ : integer := 100; -- clk->out delay (sim only)
IODELAY_GRP : string := "IODELAY_MIG"; -- May be assigned unique name when
-- multiple IP cores used in design
INPUT_CLK_TYPE : string := "DIFFERENTIAL"; -- input clock type
-- "DIFFERENTIAL","SINGLE_ENDED"
RST_ACT_LOW : integer := 1 -- Reset input polarity
-- (0 = active high, 1 = active low)
);
port (
clk_ref_p : in std_logic;
clk_ref_n : in std_logic;
clk_ref : in std_logic;
sys_rst : in std_logic;
iodelay_ctrl_rdy : out std_logic
);
end entity iodelay_ctrl;
architecture syn of iodelay_ctrl is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on DCM lock status)
-- COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
constant RST_SYNC_NUM : integer := 15;
-- constant : integer := RST_SYNC_NUM = 25;
signal clk_ref_bufg : std_logic;
signal clk_ref_ibufg : std_logic;
signal rst_ref : std_logic;
signal rst_ref_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal rst_tmp_idelay : std_logic;
signal sys_rst_act_hi : std_logic;
attribute syn_maxfan : integer;
attribute IODELAY_GROUP : string;
attribute syn_maxfan of rst_ref_sync_r : signal is 10;
attribute IODELAY_GROUP of u_idelayctrl : label is IODELAY_GRP;
begin
--***************************************************************************
-- Possible inversion of system reset as appropriate
sys_rst_act_hi <= not (sys_rst) when(RST_ACT_LOW=1) else sys_rst;
--***************************************************************************
-- Input buffer for IDELAYCTRL reference clock - handle either a
-- differential or single-ended input
--***************************************************************************
diff_clk_ref: if (INPUT_CLK_TYPE = "DIFFERENTIAL") generate
u_ibufg_clk_ref : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE
)
port map (
I => clk_ref_p,
IB => clk_ref_n,
O => clk_ref_ibufg
);
end generate diff_clk_ref;
se_clk_ref: if (INPUT_CLK_TYPE = "SINGLE_ENDED") generate
-- u_ibufg_clk_ref : IBUFG
-- generic map (
-- IBUF_LOW_PWR => FALSE
-- )
-- port map (
-- I => clk_ref,
-- O => clk_ref_ibufg
-- );
clk_ref_ibufg <= clk_ref;
end generate se_clk_ref;
--***************************************************************************
-- Global clock buffer for IDELAY reference clock
--***************************************************************************
u_bufg_clk_ref : BUFG
port map (
O => clk_ref_bufg,
I => clk_ref_ibufg
);
--*****************************************************************
-- IDELAYCTRL reset
-- This assumes an external clock signal driving the IDELAYCTRL
-- blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
-- lock signal will need to be incorporated in this.
--*****************************************************************
-- Add PLL lock if PLL drives IDELAYCTRL in user design
rst_tmp_idelay <= sys_rst_act_hi;
process (clk_ref_bufg, rst_tmp_idelay)
begin
if (rst_tmp_idelay = '1') then
rst_ref_sync_r <= (others => '1') after (TCQ)*1 ps;
elsif (clk_ref_bufg'event and clk_ref_bufg = '1') then
rst_ref_sync_r <= std_logic_vector(unsigned(rst_ref_sync_r) sll 1) after (TCQ)*1 ps;
end if;
end process;
rst_ref <= rst_ref_sync_r(RST_SYNC_NUM-1);
--*****************************************************************
u_idelayctrl : IDELAYCTRL
port map (
RDY => iodelay_ctrl_rdy,
REFCLK => clk_ref_bufg,
RST => rst_ref
);
end architecture syn;
|
lgpl-3.0
|
4101d7b436e41c95696b885bcb5570a7
| 0.570996 | 4.255418 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/peripheral/keymap.vhd
| 2 | 10,961 |
--
-- keymap.vhd
-- keymap ROM tables for eseps2.vhd
-- Revision 1.00
--
-- Copyright (c) 2006 Kazuhiro Tsujikawa (ESE Artists' factory)
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- 2013.08.12 modified by KdL
-- Added RWIN and LWIN usable as alternatives to the space-bar.
--
-- 2015.05.20 - Brazilian ABNT2 keymap by Fabio Belavenuto
-- 2016.11 - Implemented Keymap change via software (SWIOPORTS)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity keymap is
port (
clock_i : in std_logic;
we_i : in std_logic;
addr_wr_i : in std_logic_vector(8 downto 0);
data_i : in std_logic_vector(7 downto 0);
addr_rd_i : in std_logic_vector(8 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end entity;
architecture RTL of keymap is
signal read_addr_q : unsigned(8 downto 0);
type ram_t is array (0 to 511) of std_logic_vector(7 downto 0);
signal ram_q : ram_t := (
--
-- bit 7 F 6 E 5 D 4 C 3 B 2 A 1 9 0 8
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 0 | 7 & | 6 ^ | 5 % | 4 $ | 3 # | 2 @ | 1 ! | 0 ) | 0
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 1 | ; : | ] } | [ { | \ | | = + | - _ | 9 ( | 8 * | 1
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 2 | B | A |DEAD | / ? | . > | , < | ` ~ | ' " | 2
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 3 | J | I | H | G | F | E | D | C | 3
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 4 | R | Q | P | O | N | M | L | K | 4
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 5 | Z | Y | X | W | V | U | T | S | 5
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 6 | F3 | F2 | F1 | Code|CapsL|Graph| Ctrl|Shift| 6
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 7 |Enter|Selec| BS | Stop| Tab | Esc | F5 | F4 | 7
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 8 |Right| Down| Up | Left| Del | Ins | Home|Space| 8
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 9 | [4] | [3] | [2] | [1] | [0] | [/] | [+] | [*] | 9
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- ROW 10| [.] | [,] | [-] | [9] | [8] | [7] | [6] | [5] | A
-- +-----+-----+-----+-----+-----+-----+-----+-----+
-- bit 7 F 6 E 5 D 4 C 3 B 2 A 1 9 0 8
--------------------------------------------
-- 108 Keys Brazilian keyboard: Scancode --
--------------------------------------------
-- F9 F5 F3 F1 F2 F12
X"FF", X"FF", X"FF", X"17", X"76", X"56", X"66", X"FF", -- 00..07
-- F10 F8 F6 F4 Tab '/"
X"FF", X"FF", X"FF", X"FF", X"07", X"37", X"02", X"FF", -- 08..0F
-- LAlt LShft LCtrl Q 1/!
X"FF", X"26", X"06", X"FF", X"16", X"64", X"10", X"FF", -- 10..17
-- Z S A W 2/@
X"FF", X"FF", X"75", X"05", X"62", X"45", X"20", X"FF", -- 18..1F
-- C X D E 4/$ 3/#
X"FF", X"03", X"55", X"13", X"23", X"40", X"30", X"FF", -- 20..27
-- Space V F T R 5/%
X"FF", X"08", X"35", X"33", X"15", X"74", X"50", X"FF", -- 28..2F
-- N B H G Y 6/¨
X"FF", X"34", X"72", X"53", X"43", X"65", X"60", X"FF", -- 30..37
-- M J U 7/& 8/*
X"FF", X"FF", X"24", X"73", X"25", X"70", X"01", X"FF", -- 38..3F
-- ,/< K I O 0/) 9/(
X"FF", X"22", X"04", X"63", X"44", X"00", X"11", X"FF", -- 40..47
-- ./> ;/: L Ç P -/_
X"FF", X"32", X"71", X"14", X"FF", X"54", X"21", X"FF", -- 48..4F
-- //? ~/^ ´/` =/+
X"FF", X"42", X"12", X"FF", X"52", X"31", X"FF", X"FF", -- 50..57
-- CapLk RShft Enter [/{ ]/}
X"36", X"06", X"77", X"51", X"FF", X"61", X"FF", X"FF", -- 58..5F
-- \/| BS
X"FF", X"14", X"FF", X"FF", X"FF", X"FF", X"57", X"FF", -- 60..67
-- [1] [4] [7] [.]
X"FF", X"49", X"FF", X"79", X"2A", X"7A", X"FF", X"FF", -- 68..6F
-- [0] [,] [2] [5] [6] [8] Esc NLock
X"39", X"6A", X"59", X"0A", X"1A", X"3A", X"27", X"FF", -- 70..77
-- F11 [+] [3] [-] [*] [9] ScrLk
X"FF", X"19", X"69", X"5A", X"09", X"4A", X"FF", X"FF", -- 78..7F
-- F7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 80..87
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 88..8F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 90..97
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 98..9F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A0..A7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A8..AF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B0..B7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B8..BF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C0..C7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C8..CF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D0..D7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D8..DF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E0..E7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E8..EF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0..F7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F8..FF
-------------------------------------------------
-- 108 Keys Brazilian keyboard: E0 + Scan Code --
-------------------------------------------------
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 00..07
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 08..0F
-- RAlt PrtSc RCtrl
X"FF", X"26", X"FF", X"FF", X"16", X"FF", X"FF", X"FF", -- 10..17
-- LWin
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"08", -- 18..1F (LWIN = $1F = SPACE)
-- RWin
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"08", -- 20..27 (RWIN = $27 = SPACE)
-- Menu
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 28..2F (MENU = $2F = 'M' key)
-- Power
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 30..37
-- Sleep
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 38..3F
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 40..47
-- [/]
X"FF", X"FF", X"29", X"FF", X"FF", X"FF", X"FF", X"FF", -- 48..4F
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 50..57
-- [Enter] Wake
X"FF", X"FF", X"77", X"FF", X"FF", X"FF", X"FF", X"FF", -- 58..5F
--
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 60..67
-- End Left Home
X"FF", X"47", X"FF", X"48", X"18", X"FF", X"FF", X"FF", -- 68..6F
-- Ins Supr Down Right Up
X"28", X"38", X"68", X"FF", X"78", X"58", X"FF", X"FF", -- 70..77
-- PDown PUp
X"FF", X"FF", X"46", X"FF", X"FF", X"67", X"FF", X"FF", -- 78..7F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 80..87
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 88..8F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 90..97
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- 98..9F
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A0..A7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- A8..AF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B0..B7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- B8..BF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C0..C7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- C8..CF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D0..D7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- D8..DF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E0..E7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- E8..EF
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", -- F0..F7
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF", X"FF" -- F8..FF
);
begin
process (clock_i)
begin
if rising_edge(clock_i) then
if we_i = '1' then
ram_q(to_integer(unsigned(addr_wr_i))) <= data_i;
end if;
read_addr_q <= unsigned(addr_rd_i);
end if;
end process;
data_o <= ram_q(to_integer(read_addr_q));
end RTL;
|
gpl-3.0
|
8f8f26cb4587e2b82cf69d31f83cae04
| 0.385472 | 2.606565 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-wxeda/pll1.vhd
| 1 | 18,080 |
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll1 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll1;
ARCHITECTURE SYN OF pll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 38,
clk0_duty_cycle => 50,
clk0_multiply_by => 17,
clk0_phase_shift => "0",
clk1_divide_by => 19,
clk1_duty_cycle => 50,
clk1_multiply_by => 34,
clk1_phase_shift => "0",
clk2_divide_by => 19,
clk2_duty_cycle => 50,
clk2_multiply_by => 34,
clk2_phase_shift => "-1455",
compensate_clock => "CLK0",
inclk0_input_frequency => 20833,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll1",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "38"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "38"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "38"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "21.473684"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "85.894737"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "85.894737"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "17"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "68"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "68"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "21.47727700"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "85.89473600"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "96.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-45.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "38"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "17"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "19"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "34"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "19"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "34"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1455"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
gpl-3.0
|
e0af03f21da8feba9ee23c4d6061b052
| 0.699834 | 3.283094 | false | false | false | false |
hoglet67/AtomBusMon
|
src/MOS6502CpuMon.vhd
| 1 | 5,850 |
-------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMon.vhd
-- /___/ /\ Timestamp : 03/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMon
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMon is
generic (
UseT65Core : boolean;
UseAlanDCore : boolean;
ClkMult : integer;
ClkDiv : integer;
ClkPer : real;
num_comparators : integer;
avr_prog_mem_size : integer
);
port (
clock : in std_logic;
-- 6502 Signals
Phi0 : in std_logic;
Phi1 : out std_logic;
Phi2 : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : in std_logic;
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Jumpers
fakeTube_n : in std_logic;
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Test connector signals
test : inout std_logic_vector(3 downto 0)
);
end MOS6502CpuMon;
architecture behavioral of MOS6502CpuMon is
signal clock_avr : std_logic;
signal Din : std_logic_vector(7 downto 0);
signal Dout : std_logic_vector(7 downto 0);
signal Rdy_latched : std_logic;
signal IRQ_n_sync : std_logic;
signal NMI_n_sync : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal R_W_n_int : std_logic;
signal Phi0_a : std_logic;
signal Phi0_b : std_logic;
signal Phi0_c : std_logic;
signal Phi0_d : std_logic;
signal cpu_clk : std_logic;
signal busmon_clk : std_logic;
begin
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
core : entity work.MOS6502CpuMonCore
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => '1',
cpu_clk => cpu_clk,
cpu_clken => '1',
IRQ_n => IRQ_n_sync,
NMI_n => NMI_n_sync,
Sync => Sync,
Addr => Addr_int,
R_W_n => R_W_n_int,
Din => Din,
Dout => Dout,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy_latched,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
test => test
);
sync_gen : process(cpu_clk)
begin
if rising_edge(cpu_clk) then
NMI_n_sync <= NMI_n;
IRQ_n_sync <= IRQ_n;
end if;
end process;
-- 6502: Sample Rdy on the rising edge of Phi0
rdy_6502: if UseT65Core generate
process(Phi0)
begin
if rising_edge(Phi0) then
Rdy_latched <= Rdy;
end if;
end process;
end generate;
-- 65C02: Sample Rdy on the falling edge of Phi0
rdy_65c02: if UseAlanDCore generate
process(Phi0)
begin
if falling_edge(Phi0) then
Rdy_latched <= Rdy;
end if;
end process;
end generate;
-- Sample Data on the falling edge of Phi0_a
data_latch : process(Phi0_a)
begin
if falling_edge(Phi0_a) then
if (fakeTube_n = '0' and Addr_int = x"FEE0") then
Din <= x"FE";
else
Din <= Data;
end if;
end if;
end process;
Data <= Dout when Phi0_c = '1' and R_W_n_int = '0' else (others => 'Z');
R_W_n <= R_W_n_int;
Addr <= Addr_int;
clk_gen : process(clock)
begin
if rising_edge(clock) then
Phi0_a <= Phi0;
Phi0_b <= Phi0_a;
Phi0_c <= Phi0_b;
Phi0_d <= Phi0_c;
end if;
end process;
Phi1 <= not Phi0_b;
Phi2 <= Phi0_b;
cpu_clk <= not Phi0_d;
busmon_clk <= Phi0_d;
end behavioral;
|
gpl-3.0
|
acc4ed8f851b27ced692420667c9a2fb
| 0.444444 | 3.709575 | false | false | false | false |
freecores/camellia-vhdl
|
looping/f.vhd
| 1 | 3,854 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 01/22/2008
-- Last Update: 01/22/2008
-- Project Name: camellia-vhdl
-- Description: Asynchronous F function
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity F is
port (
x : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 63);
z : out STD_LOGIC_VECTOR (0 to 63)
);
end F;
architecture RTL of F is
-- S-BOX
component SBOX1 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX2 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX3 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
component SBOX4 is
port (
data_in : IN STD_LOGIC_VECTOR(0 to 7);
data_out : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
signal y : STD_LOGIC_VECTOR (0 to 63);
signal y1, y2, y3, y4, y5, y6, y7, y8 : STD_LOGIC_VECTOR (0 to 7);
signal so1, so2, so3, so4, so5, so6, so7, so8 : STD_LOGIC_VECTOR (0 to 7);
signal pa1, pa2, pa3, pa4, pa5, pa6, pa7, pa8 : STD_LOGIC_VECTOR (0 to 7);
signal pb1, pb2, pb3, pb4, pb5, pb6, pb7, pb8 : STD_LOGIC_VECTOR (0 to 7);
begin
y <= x xor k;
y8 <= y(56 to 63);
y7 <= y(48 to 55);
y6 <= y(40 to 47);
y5 <= y(32 to 39);
y4 <= y(24 to 31);
y3 <= y(16 to 23);
y2 <= y(8 to 15);
y1 <= y(0 to 7);
-- S-FUNCTION
S1a : SBOX1
port map(y8, so8);
S1b : SBOX1
port map(y1, so1);
S2a : SBOX2
port map(y5, so5);
S2b : SBOX2
port map(y2, so2);
S3a : SBOX3
port map(y6, so6);
S3b : SBOX3
port map(y3, so3);
S4a : SBOX4
port map(y7, so7);
S4b : SBOX4
port map(y4, so4);
-- P-FUNCTION
pa8 <= so8 xor pa2;
pa7 <= so7 xor pa1;
pa6 <= so6 xor pa4;
pa5 <= so5 xor pa3;
pa4 <= so4 xor so5;
pa3 <= so3 xor so8;
pa2 <= so2 xor so7;
pa1 <= so1 xor so6;
pb8 <= pa8 xor pb3;
pb7 <= pa7 xor pb2;
pb6 <= pa6 xor pb1;
pb5 <= pa5 xor pb4;
pb4 <= pa4 xor pa7;
pb3 <= pa3 xor pa6;
pb2 <= pa2 xor pa5;
pb1 <= pa1 xor pa8;
z <= pb5 & pb6 & pb7 & pb8 & pb1 & pb2 & pb3 & pb4;
end RTL;
|
gpl-3.0
|
f59c70d537a8bfec6a8e9eb55cbd4ec1
| 0.510898 | 3.392606 | false | false | false | false |
RowdyRajan/GestureGloveCapstone
|
DE2Component.vhd
| 1 | 8,616 |
-- This is the top level file for Gesture Control Interface project for Group 2
-- Eric Smith, Chris Chmilar, Rajan Jassal
-- This file is a modified version of the top level file provided in lab 1
-- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port
(
-- Input ports and 50 MHz Clock
KEY : in std_logic_vector (0 downto 0);
SW : in std_logic_vector (0 downto 0);
CLOCK_50 : in std_logic;
-- Green leds on board
LEDG : out DE2_LED_GREEN;
-- LCD on board
LCD_BLON : out std_logic;
LCD_ON : out std_logic;
LCD_DATA : inout DE2_LCD_DATA_BUS;
LCD_RS : out std_logic;
LCD_EN : out std_logic;
LCD_RW : out std_logic;
-- SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic
);
end DE2Component;
architecture structure of DE2Component is
-- Declarations (optional)
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic -- WE_N
--character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
--character_lcd_0_external_interface_ON : out std_logic; -- ON
--character_lcd_0_external_interface_BLON : out std_logic; -- BLON
--character_lcd_0_external_interface_EN : out std_logic; -- EN
--character_lcd_0_external_interface_RS : out std_logic; -- RS
--character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N
--character_lcd_0_external_interface_DATA => LCD_DATA,
--character_lcd_0_external_interface_ON => LCD_ON,
--character_lcd_0_external_interface_BLON => LCD_BLON,
--character_lcd_0_external_interface_EN => LCD_EN,
--character_lcd_0_external_interface_RS => LCD_RS,
--character_lcd_0_external_interface_RW => LCD_RW
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
|
gpl-2.0
|
80182e04b876e16ad8e15537891d0b99
| 0.463324 | 3.797268 | false | false | false | false |
freecores/camellia-vhdl
|
pipelining/sbox4.vhd
| 1 | 2,415 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/14/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX4
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SBOX4 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX4;
architecture RTL of SBOX4 is
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
begin
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
s1_clk <= clk;
s1_addra <= addra(1 to 7) & addra(0);
s1_addrb <= addrb(1 to 7) & addrb(0);
douta <= s1_douta;
doutb <= s1_doutb;
end RTL;
|
gpl-3.0
|
6f7cf8e31a0a5f1830b78120bbc62888
| 0.587164 | 3.692661 | false | false | false | false |
hoglet67/AtomBusMon
|
src/SYS09/cpu09l.vhd
| 2 | 182,156 |
--===========================================================================--
-- --
-- Synthesizable 6809 instruction compatible VHDL CPU core --
-- --
--===========================================================================--
--
-- File name : cpu09l.vhd
--
-- Entity name : cpu09
--
-- Purpose : 6809 instruction compatible CPU core written in VHDL
-- with Last Instruction Cycle, bus available, bus status,
-- and instruction fetch signals.
-- Not cycle compatible with the original 6809 CPU
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : VMA (valid memory address) is hight whenever a valid memory
-- access is made by an instruction fetch, interrupt vector fetch
-- or a data read or write otherwise it is low indicating an idle
-- bus cycle.
-- IFETCH (instruction fetch output) is high whenever an
-- instruction byte is read i.e. the program counter is applied
-- to the address bus.
-- LIC (last instruction cycle output) is normally low
-- but goes high on the last cycle of an instruction.
-- BA (bus available output) is normally low but goes high while
-- waiting in a Sync instruction state or the CPU is halted
-- i.e. a DMA grant.
-- BS (bus status output) is normally low but goes high during an
-- interrupt or reset vector fetch or the processor is halted
-- i.e. a DMA grant.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version 0.1 - 26 June 2003 - John Kent
-- Added extra level in state stack
-- fixed some calls to the extended addressing state
--
-- Version 0.2 - 5 Sept 2003 - John Kent
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
-- Added/Fixed STY and STS instructions.
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
-- CMPX Loaded ACCA and ACCB - Now fixed
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
-- reversed clock edge
--
-- Version 1.1 - 29 November 2003 John kent
-- ACCA and ACCB indexed offsets are 2's complement.
-- ALU Right Mux now sign extends ACCA & ACCB offsets
-- Absolute Indirect addressing performed a read on the
-- second byte of the address rather than a fetch
-- so it formed an incorrect address. Now fixed.
--
-- Version 1.2 - 29 November 2003 John Kent
-- LEAX and LEAY affect the Z bit only
-- LEAS and LEAU do not affect any condition codes
-- added an extra ALU control for LEA.
--
-- Version 1.3 - 12 December 2003 John Kent
-- CWAI did not work, was missed a PUSH_ST on calling
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
-- finding this fault.
--
-- Version 1.4 - 12 December 2003 John Kent
-- Missing cc_ctrl assignment in otherwise case of
-- lea_state resulted in cc_ctrl being latched in
-- that state.
-- The otherwise statement should never be reached,
-- and has been fixed simply to resolve synthesis warnings.
--
-- Version 1.5 - 17 january 2004 John kent
-- The clear instruction used "alu_ld8" to control the ALU
-- rather than "alu_clr". This mean the Carry was not being
-- cleared correctly.
--
-- Version 1.6 - 24 January 2004 John Kent
-- Fixed problems in PSHU instruction
--
-- Version 1.7 - 25 January 2004 John Kent
-- removed redundant "alu_inx" and "alu_dex'
-- Removed "test_alu" and "test_cc"
-- STD instruction did not set condition codes
-- JMP direct was not decoded properly
-- CLR direct performed an unwanted read cycle
-- Bogus "latch_md" in Page2 indexed addressing
--
-- Version 1.8 - 27 January 2004 John Kent
-- CWAI in decode1_state should increment the PC.
-- ABX is supposed to be an unsigned addition.
-- Added extra ALU function
-- ASR8 slightly changed in the ALU.
--
-- Version 1.9 - 20 August 2005
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
-- rather than LSR16. There was a problem with single
-- operand instructions using the MD register which is
-- sign extended on the first 8 bit fetch.
--
-- Version 1.10 - 13 September 2005
-- TFR & EXG instructions did not work for the Condition Code Register
-- An extra case has been added to the ALU for the alu_tfr control
-- to assign the left ALU input (alu_left) to the condition code
-- outputs (cc_out).
--
-- Version 1.11 - 16 September 2005
-- JSR ,X should not predecrement S before calculating the jump address.
-- The reason is that JSR [0,S] needs S to point to the top of the stack
-- to fetch a valid vector address. The solution is to have the addressing
-- mode microcode called before decrementing S and then decrementing S in
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
-- pushed on the stack. This adds one extra bus cycle, but resolves the
-- addressing conflict. I've also removed the pre-decement S in
-- JSR EXTENDED as it also calls JSR_STATE.
--
-- Version 1.12 - 6th June 2006
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
-- This is different to the 6800. CLR should reset the V bit.
--
-- Version 1.13 - 7th July 2006
-- Disable NMI on reset until S Stack pointer has been loaded.
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
--
-- Version 1.14 - 11th July 2006
-- 1. Added new state to RTI called rti_entire_state.
-- This state tests the CC register after it has been loaded
-- from the stack. Previously the current CC was tested which
-- was incorrect. The Entire Flag should be set before the
-- interrupt stacks the CC.
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
-- which was an enumerated state, but not defined anywhere.
-- rti_state has been changed to rti_cc_state so that bogus interrupt
-- will perform an RTI after entering that state.
-- 3. Sync should generate an interrupt if the interrupt masks
-- are cleared. If the interrupt masks are set, then an interrupt
-- will cause the the PC to advance to the next instruction.
-- Note that I don't wait for an interrupt to be asserted for
-- three clock cycles.
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
-- the Multiply instruction replacing "alu_add16". This is similar
-- to "alu_add16" except it sets the Carry bit to B7 of the result
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
-- flags. The logic was re-arranged so that it adds md or zero so
-- that the Carry condition code is set on zero multiplicands.
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
-- and Zero Flags. It will also affect the Overflow (V) flag although
-- the operation is undefined. It's anyones guess what DAA does to V.
--
-- Version 1.15 - 25th Feb 2007 - John Kent
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
-- Changed sensitivity lists.
--
-- Version 1.16 - 5th February 2008 - John Kent
-- FIRQ interrupts should take priority over IRQ Interrupts.
-- This presumably means they should be tested for before IRQ
-- when they happen concurrently.
--
-- Version 1.17 - 18th February 2008 - John Kent
-- NMI in CWAI should mask IRQ and FIRQ interrupts
--
-- Version 1.18 - 21st February 2008 - John Kent
-- Removed default register settings in each case statement
-- and placed them at the beginning of the state sequencer.
-- Modified the SYNC instruction so that the interrupt vector(iv)
-- is not set unless an unmasked FIRQ or IRQ is received.
--
-- Version 1.19 - 25th February 2008 - John Kent
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
-- Enumerated separate states for MASKI and MASKIF states
-- Removed code on BSR/JSR in fetch cycle
--
-- Version 1.20 - 8th October 2011 - John Kent
-- added fetch output which should go high during the fetch cycle
--
-- Version 1.21 - 8th October 2011 - John Kent
-- added Last Instruction Cycle signal
-- replaced fetch with ifetch (instruction fetch) signal
-- added ba & bs (bus available & bus status) signals
--
-- Version 1.22 - 2011-10-29 John Kent
-- The halt state isn't correct.
-- The halt state is entered into from the fetch_state
-- It returned to the fetch state which may re-run an execute cycle
-- on the accumulator and it won't necessarily be the last instruction cycle
-- I've changed the halt state to return to the decode1_state
--
-- Version 1.23 - 2011-10-30 John Kent
-- sample halt in the change_state process if lic is high (last instruction cycle)
--
-- Version 1.24 - 2011-11-01 John Kent
-- Handle interrupts in change_state process
-- Sample interrupt inputs on last instruction cycle
-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process.
-- Generate fic (first instruction cycle) from lic (last instruction cycle)
-- and use it to complete the dual operand execute cycle before servicing
-- halt or interrupts requests.
-- rename lic to lic_out on the entity declaration so that lic can be tested internally.
-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle
-- integrated nmi_ctrl into change_state process
-- Reduces the microcode state stack to one entry (saved_state)
-- imm16_state jumps directly to the fetch_state
-- pull_return_lo states jumps directly to the fetch_state
-- duplicate andcc_state as cwai_state
-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state
--
-- Version 1.25 - 2011-11-27 John Kent
-- Changed the microcode for saving registers on an interrupt into a microcode subroutine.
-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3
-- call the interrupt microcode subroutine.
-- Added additional states for nmi, and irq for interrupt servicing.
-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags.
--
-- Version 1.26 - 2013-03-18 John Kent
-- pre-initialized cond_true variable to true in state sequencer
-- re-arranged change_state process slightly
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu09 is
port (
clk : in std_logic; -- E clock input (rising edge)
rst : in std_logic; -- reset input (active high)
vma : out std_logic; -- valid memory address (active high)
lic_out : out std_logic; -- last instruction cycle (active high)
ifetch : out std_logic; -- instruction fetch cycle (active high)
opfetch : out std_logic; -- opcode fetch (active high)
ba : out std_logic; -- bus available (high on sync wait or DMA grant)
bs : out std_logic; -- bus status (high on interrupt or reset vector fetch or DMA grant)
addr : out std_logic_vector(15 downto 0); -- address bus output
rw : out std_logic; -- read not write output
data_out : out std_logic_vector(7 downto 0); -- data bus output
data_in : in std_logic_vector(7 downto 0); -- data bus input
irq : in std_logic; -- interrupt request input (active high)
firq : in std_logic; -- fast interrupt request input (active high)
nmi : in std_logic; -- non maskable interrupt request input (active high)
halt : in std_logic; -- halt input (active high) grants DMA
hold : in std_logic; -- hold input (active high) extend bus cycle
Regs : out std_logic_vector(111 downto 0)
);
end cpu09;
architecture rtl of cpu09 is
constant EBIT : integer := 7;
constant FBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
--
-- Interrupt vector modifiers
--
constant RST_VEC : std_logic_vector(2 downto 0) := "111";
constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
type state_type is (-- Start off in Reset
reset_state,
-- Fetch Interrupt Vectors (including reset)
vect_lo_state, vect_hi_state, vect_idle_state,
-- Fetch Instruction Cycle
fetch_state,
-- Decode Instruction Cycles
decode1_state, decode2_state, decode3_state,
-- Calculate Effective Address
imm16_state,
indexed_state, index8_state, index16_state, index16_2_state,
pcrel8_state, pcrel16_state, pcrel16_2_state,
indexaddr_state, indexaddr2_state,
postincr1_state, postincr2_state,
indirect_state, indirect2_state, indirect3_state,
extended_state,
-- single ops
single_op_read_state,
single_op_exec_state,
single_op_write_state,
-- Dual op states
dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
dual_op_write8_state, dual_op_write16_state,
--
sync_state, halt_state, cwai_state,
--
andcc_state, orcc_state,
tfr_state,
exg_state, exg1_state, exg2_state,
lea_state,
-- Multiplication
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
-- Branches
lbranch_state, sbranch_state,
-- Jumps, Subroutine Calls and Returns
jsr_state, jmp_state,
push_return_hi_state, push_return_lo_state,
pull_return_hi_state, pull_return_lo_state,
-- Interrupt cycles
int_nmi_state, int_nmi1_state,
int_irq_state, int_irq1_state,
int_firq_state, int_firq1_state,
int_entire_state, int_fast_state,
int_pcl_state, int_pch_state,
int_upl_state, int_uph_state,
int_iyl_state, int_iyh_state,
int_ixl_state, int_ixh_state,
int_dp_state,
int_accb_state, int_acca_state,
int_cc_state,
int_cwai_state,
int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state,
-- Return From Interrupt
rti_cc_state, rti_entire_state,
rti_acca_state, rti_accb_state,
rti_dp_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_upl_state, rti_uph_state,
rti_pcl_state, rti_pch_state,
-- Push Registers using SP
pshs_state,
pshs_pcl_state, pshs_pch_state,
pshs_upl_state, pshs_uph_state,
pshs_iyl_state, pshs_iyh_state,
pshs_ixl_state, pshs_ixh_state,
pshs_dp_state,
pshs_acca_state, pshs_accb_state,
pshs_cc_state,
-- Pull Registers using SP
puls_state,
puls_cc_state,
puls_acca_state, puls_accb_state,
puls_dp_state,
puls_ixl_state, puls_ixh_state,
puls_iyl_state, puls_iyh_state,
puls_upl_state, puls_uph_state,
puls_pcl_state, puls_pch_state,
-- Push Registers using UP
pshu_state,
pshu_pcl_state, pshu_pch_state,
pshu_spl_state, pshu_sph_state,
pshu_iyl_state, pshu_iyh_state,
pshu_ixl_state, pshu_ixh_state,
pshu_dp_state,
pshu_acca_state, pshu_accb_state,
pshu_cc_state,
-- Pull Registers using UP
pulu_state,
pulu_cc_state,
pulu_acca_state, pulu_accb_state,
pulu_dp_state,
pulu_ixl_state, pulu_ixh_state,
pulu_iyl_state, pulu_iyh_state,
pulu_spl_state, pulu_sph_state,
pulu_pcl_state, pulu_pch_state );
type st_type is (reset_st, push_st, idle_st );
type iv_type is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv);
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type pre_type is (reset_pre, fetch_pre, latch_pre );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type left_type is (cc_left, acca_left, accb_left, dp_left,
ix_left, iy_left, up_left, sp_left,
accd_left, md_left, pc_left, ea_left );
type right_type is (ea_right, zero_right, one_right, two_right,
acca_right, accb_right, accd_right,
md_right, md_sign5_right, md_sign8_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_mul,
alu_asr8, alu_asl8, alu_lsr8,
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
alu_seif, alu_sei, alu_see, alu_cle,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
signal op_code: std_logic_vector(7 downto 0);
signal pre_code: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal dp: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal yreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal up: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(2 downto 0);
signal nmi_req: std_logic;
signal nmi_ack: std_logic;
signal nmi_enable: std_logic;
signal fic: std_logic; -- first instruction cycle
signal lic: std_logic; -- last instruction cycle
signal state: state_type;
signal next_state: state_type;
signal return_state: state_type;
signal saved_state: state_type;
signal st_ctrl: st_type;
signal iv_ctrl: iv_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal pre_ctrl: pre_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal iy_ctrl: iy_type;
signal cc_ctrl: cc_type;
signal dp_ctrl: dp_type;
signal sp_ctrl: sp_type;
signal up_ctrl: up_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
begin
Regs <= cc & dp & pc & sp & up & yreg & xreg & accb & acca;
----------------------------------
--
-- State machine stack
--
----------------------------------
--state_stack_proc: process( clk, hold, state_stack, st_ctrl,
-- return_state, fetch_state )
state_stack_proc: process( clk, st_ctrl, return_state )
begin
if clk'event and clk = '1' then
if hold = '0' then
case st_ctrl is
when reset_st =>
saved_state <= fetch_state;
when push_st =>
saved_state <= return_state;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Interrupt Vector control
--
----------------------------------
--
int_vec_proc: process( clk, iv_ctrl )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iv_ctrl is
when reset_iv =>
iv <= RST_VEC;
when nmi_iv =>
iv <= NMI_VEC;
when swi_iv =>
iv <= SWI_VEC;
when irq_iv =>
iv <= IRQ_VEC;
when firq_iv =>
iv <= FIRQ_VEC;
when swi2_iv =>
iv <= SWI2_VEC;
when swi3_iv =>
iv <= SWI3_VEC;
when others =>
null;
end case;
end if; -- hold
end if; -- clk
end process;
----------------------------------
--
-- Program Counter Control
--
----------------------------------
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
pc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pc_ctrl is
when reset_pc =>
pc <= (others=>'0');
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when incr_pc =>
pc <= pc + 1;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
ea_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold= '0' then
case ea_ctrl is
when reset_ea =>
ea <= (others=>'0');
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= dp;
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator A
--
--------------------------------
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
acca_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case acca_ctrl is
when reset_acca =>
acca <= (others=>'0');
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
accb_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case accb_ctrl is
when reset_accb =>
accb <= (others=>'0');
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
ix_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case ix_ctrl is
when reset_ix =>
xreg <= (others=>'0');
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Y Index register
--
--------------------------------
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
iy_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iy_ctrl is
when reset_iy =>
yreg <= (others=>'0');
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- S stack pointer
--
--------------------------------
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
sp_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case sp_ctrl is
when reset_sp =>
sp <= (others=>'0');
nmi_enable <= '0';
when load_sp =>
sp <= out_alu(15 downto 0);
nmi_enable <= '1';
when pull_hi_sp =>
sp(15 downto 8) <= data_in;
when pull_lo_sp =>
sp(7 downto 0) <= data_in;
nmi_enable <= '1';
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- U stack pointer
--
--------------------------------
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
up_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case up_ctrl is
when reset_up =>
up <= (others=>'0');
when load_up =>
up <= out_alu(15 downto 0);
when pull_hi_up =>
up(15 downto 8) <= data_in;
when pull_lo_up =>
up(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
md_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case md_ctrl is
when reset_md =>
md <= (others=>'0');
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md => -- sign extend md for branches
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
cc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case cc_ctrl is
when reset_cc =>
cc <= "11010000"; -- set EBIT, FBIT & IBIT
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Direct Page register
--
----------------------------------
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
dp_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case dp_ctrl is
when reset_dp =>
dp <= (others=>'0');
when load_dp =>
dp <= out_alu(7 downto 0);
when pull_dp =>
dp <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- op code register
--
----------------------------------
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
op_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00010010";
when fetch_op =>
op_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- pre byte op code register
--
----------------------------------
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
pre_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pre_ctrl is
when reset_pre =>
pre_code <= (others=>'0');
when fetch_pre =>
pre_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
--change_state: process( clk, rst, state, hold, next_state )
change_state: process( clk )
begin
if clk'event and clk = '1' then
if rst = '1' then
fic <= '0';
nmi_ack <= '0';
state <= reset_state;
elsif hold = '0' then
fic <= lic;
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
nmi_ack <= '0';
end if;
if (nmi_req = '1') and (nmi_ack = '0') and (state = int_nmimask_state) then
nmi_ack <= '1';
end if;
if lic = '1' then
if halt = '1' then
state <= halt_state;
-- service non maskable interrupts
elsif (nmi_req = '1') and (nmi_ack = '0') then
state <= int_nmi_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') then
if (cc(FBIT) = '0') then
state <= int_firq_state;
else
state <= fetch_state;
end if;
elsif (irq = '1') then
if (cc(IBIT) = '0') then
state <= int_irq_state;
else
state <= fetch_state;
end if;
else
state <= next_state;
end if; -- halt, nmi, firq, irq
else
state <= next_state;
end if; -- lic
end if; -- reset/hold
end if; -- clk
end process;
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
nmi_handler : process( rst, clk )
begin
if rst='1' then
nmi_req <= '0';
elsif clk'event and clk='0' then
if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
nmi_req <= '1';
else
if (nmi='0') and (nmi_ack='1') then
nmi_req <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
begin
ifetch <= '0';
vma <= '1';
case addr_ctrl is
when fetch_ad =>
addr <= pc;
rw <= '1';
ifetch <= '1';
when read_ad =>
addr <= ea;
rw <= '1';
when write_ad =>
addr <= ea;
rw <= '0';
when pushs_ad =>
addr <= sp;
rw <= '0';
when pulls_ad =>
addr <= sp;
rw <= '1';
when pushu_ad =>
addr <= up;
rw <= '0';
when pullu_ad =>
addr <= up;
rw <= '1';
when int_hi_ad =>
addr <= "111111111111" & iv & "0";
rw <= '1';
when int_lo_ad =>
addr <= "111111111111" & iv & "1";
rw <= '1';
when others =>
addr <= "1111111111111111";
rw <= '1';
vma <= '0';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
begin
case dout_ctrl is
when cc_dout => -- condition code register
data_out <= cc;
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when dp_dout => -- direct page register
data_out <= dp;
when ix_lo_dout => -- X index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- X index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- Y index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- Y index reg
data_out <= yreg(15 downto 8);
when up_lo_dout => -- U stack pointer
data_out <= up(7 downto 0);
when up_hi_dout => -- U stack pointer
data_out <= up(15 downto 8);
when sp_lo_dout => -- S stack pointer
data_out <= sp(7 downto 0);
when sp_hi_dout => -- S stack pointer
data_out <= sp(15 downto 8);
when md_lo_dout => -- alu output
data_out <= md(7 downto 0);
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
end case;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
begin
case left_ctrl is
when cc_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= cc;
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when dp_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= dp;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when up_left =>
left <= up;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux: process( right_ctrl, md, acca, accb, ea )
begin
case right_ctrl is
when ea_right =>
right <= ea;
when zero_right =>
right <= "0000000000000000";
when one_right =>
right <= "0000000000000001";
when two_right =>
right <= "0000000000000010";
when acca_right =>
if acca(7) = '0' then
right <= "00000000" & acca(7 downto 0);
else
right <= "11111111" & acca(7 downto 0);
end if;
when accb_right =>
if accb(7) = '0' then
right <= "00000000" & accb(7 downto 0);
else
right <= "11111111" & accb(7 downto 0);
end if;
when accd_right =>
right <= acca & accb;
when md_sign5_right =>
if md(4) = '0' then
right <= "00000000000" & md(4 downto 0);
else
right <= "11111111111" & md(4 downto 0);
end if;
when md_sign8_right =>
if md(7) = '0' then
right <= "00000000" & md(7 downto 0);
else
right <= "11111111" & md(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when alu_asr8 =>
carry_in := left(7);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
--
-- CBIT HBIT VHI VLO DAA
-- 0 0 0 0 66 (!VHI : hi_nybble>8)
-- 0 0 0 1 60
-- 0 0 1 1 00
-- 0 0 1 0 06 ( VHI : hi_nybble<=8)
--
-- 0 1 1 0 06
-- 0 1 1 1 06
-- 0 1 0 1 66
-- 0 1 0 0 66
--
-- 1 1 0 0 66
-- 1 1 0 1 66
-- 1 1 1 1 66
-- 1 1 1 0 66
--
-- 1 0 1 0 66
-- 1 0 1 1 60
-- 1 0 0 1 60
-- 1 0 0 0 66
--
-- 66 = (!VHI & !VLO) + (CBIT & HBIT) + (HBIT & !VHI) + (CBIT & !VLO)
-- = (CBIT & (HBIT + !VLO)) + (!VHI & (HBIT + !VLO))
-- = (!VLO & (CBIT + !VHI)) + (HBIT & (CBIT + !VHI))
-- 60 = (CBIT & !HBIT & VLO) + (!HBIT & !VHI & VLO)
-- = (!HBIT & VLO & (CBIT + !VHI))
-- 06 = (!CBIT & VHI & (!VLO + VHI)
-- 00 = (!CBIT & !HBIT & VHI & VLO)
--
if (cc(CBIT) = '0') then
-- CBIT=0
if( cc(HBIT) = '0' ) then
-- HBIT=0
if valid_lo then
-- lo <= 9 (no overflow in low nybble)
if valid_hi then
-- hi <= 9 (no overflow in either low or high nybble)
daa_reg := "00000000";
else
-- hi > 9 (overflow in high nybble only)
daa_reg := "01100000";
end if;
else
-- lo > 9 (overflow in low nybble)
--
-- since there is already an overflow in the low nybble
-- you need to make room in the high nybble for the low nybble carry
-- so compare the high nybble with 8 rather than 9
-- if the high nybble is 9 there will be an overflow on the high nybble
-- after the decimal adjust which means it will roll over to an invalid BCD digit
--
if( left(7 downto 4) <= 8 ) then
-- hi <= 8 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 8 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- HBIT=1 (overflow in low nybble)
if valid_hi then
-- hi <= 9 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- CBIT=1 (carry => overflow in high nybble)
if ( cc(HBIT) = '0' )then
-- HBIT=0 (half carry clear => may or may not be an overflow in the low nybble)
if valid_lo then
-- lo <=9 (overflow in high nybble only)
daa_reg := "01100000";
else
-- lo >9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
else
-- HBIT=1 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_adc | alu_mul =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_sbc =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_abx =>
out_alu <= left + ("00000000" & right(7 downto 0)) ;
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 =>
out_alu <= carry_in & left(15 downto 1); -- lsr16
when alu_lsr8 | alu_asr8 | alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_sex =>
if left(7) = '0' then
out_alu <= "00000000" & left(7 downto 0);
else
out_alu <= "11111111" & left(7 downto 0);
end if;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_mul =>
cc_out(CBIT) <= out_alu(7);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_andcc =>
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
when alu_orcc =>
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
when alu_tfr =>
cc_out(CBIT) <= left(CBIT);
when others =>
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 | alu_mul |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_lea =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_andcc =>
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
when alu_orcc =>
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
when alu_tfr =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_andcc =>
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
when alu_orcc =>
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
when alu_tfr =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_andcc =>
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
when alu_orcc =>
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
when alu_tfr =>
cc_out(IBIT) <= left(IBIT);
when alu_seif | alu_sei =>
cc_out(IBIT) <= '1';
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_andcc =>
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
when alu_orcc =>
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
when alu_tfr =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
-- 6809 Programming reference manual says
-- V not affected by ASR, LSR and ROR
-- This is different to the 6800
-- John Kent 6th June 2006
-- when alu_asr8 =>
-- cc_out(VBIT) <= left(0) xor left(7);
-- when alu_lsr8 | alu_lsr16 =>
-- cc_out(VBIT) <= left(0);
-- when alu_ror8 =>
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
--
-- 11th July 2006 - John Kent
-- What DAA does with V is anyones guess
-- It is undefined in the 6809 programming manual
--
when alu_daa =>
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
-- CLR resets V Bit
-- John Kent 6th June 2006
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
cc_out(VBIT) <= '0';
when alu_andcc =>
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
when alu_orcc =>
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
when alu_tfr =>
cc_out(VBIT) <= left(VBIT);
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
when alu_orcc =>
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
when alu_tfr =>
cc_out(FBIT) <= left(FBIT);
when alu_seif =>
cc_out(FBIT) <= '1';
when others =>
cc_out(FBIT) <= cc(FBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
when alu_orcc =>
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
when alu_tfr =>
cc_out(EBIT) <= left(EBIT);
when alu_see =>
cc_out(EBIT) <= '1';
when alu_cle =>
cc_out(EBIT) <= '0';
when others =>
cc_out(EBIT) <= cc(EBIT);
end case;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
process( state, saved_state,
op_code, pre_code,
cc, ea, md, iv, fic, halt,
nmi_req, firq, irq, lic )
variable cond_true : boolean; -- variable used to evaluate coditional branches
begin
cond_true := (1=1);
ba <= '0';
bs <= '0';
lic <= '0';
opfetch <= '0';
iv_ctrl <= latch_iv;
-- Registers preserved
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- ALU Idle
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
-- Bus idle
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
-- Next State Fetch
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
case state is
when reset_state => -- released from reset
-- reset the registers
iv_ctrl <= reset_iv;
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
cc_ctrl <= reset_cc;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
dp_ctrl <= reset_dp;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
up_ctrl <= reset_up;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
st_ctrl <= reset_st;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
bs <= '1';
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
bs <= '1';
next_state <= fetch_state;
when vect_idle_state =>
--
-- Last Instruction Cycle for SWI, SWI2 & SWI3
--
if op_code = "00111111" then
lic <= '1';
end if;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
--
when fetch_state =>
-- fetch the op code
opfetch <= '1';
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
-- Fetch op code
addr_ctrl <= fetch_ad;
-- Advance the PC to fetch next instruction byte
pc_ctrl <= incr_pc;
next_state <= decode1_state;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode1_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- direct single op (2 bytes)
-- 6809 => 6 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 md_lo=(ea) / pc=pc
-- 4 alu_left=md / md=alu_out / pc=pc
-- 5 (ea)=md_lo / pc=pc
--
-- Exception is JMP
-- 6809 => 3 cycles
-- cpu09 => 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 pc=ea
--
when "0000" =>
-- advance the PC
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "1110" => -- jmp
next_state <= jmp_state;
when "1111" => -- clr
next_state <= single_op_exec_state;
when others =>
next_state <= single_op_read_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
case op_code(3 downto 0) is
--
-- Page2 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0000" => -- page2
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode2_state;
--
-- Page3 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0001" => -- page3
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode3_state;
--
-- nop - No operation ( 1 byte )
-- 6809 => 2 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode
--
when "0010" => -- nop
lic <= '1';
next_state <= fetch_state;
--
-- sync - halt execution until an interrupt is received
-- interrupt may be NMI, IRQ or FIRQ
-- program execution continues if the
-- interrupt is asserted for 3 clock cycles
-- note that registers are not pushed onto the stack
-- CPU09 => Interrupts need only be asserted for one clock cycle
--
when "0011" => -- sync
next_state <= sync_state;
--
-- lbra -- long branch (3 bytes)
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 pc=pc+md
--
when "0110" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- lbsr - long branch to subroutine (3 bytes)
-- 6809 => 9 cycles
-- cpu09 => 6 cycles
-- 1 op=(pc) /pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
-- 5 (sp)=pc_hi / pc=pc
-- 6 pc=pc+md
--
when "0111" =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Decimal Adjust Accumulator
--
when "1001" => -- daa
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
lic <= '1';
next_state <= fetch_state;
--
-- OR Condition Codes
--
when "1010" => -- orcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= orcc_state;
--
-- AND Condition Codes
--
when "1100" => -- andcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= andcc_state;
--
-- Sign Extend
--
when "1101" => -- sex
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
lic <= '1';
next_state <= fetch_state;
--
-- Exchange Registers
--
when "1110" => -- exg
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= exg_state;
--
-- Transfer Registers
--
when "1111" => -- tfr
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= tfr_state;
when others =>
-- increment the pc
pc_ctrl <= incr_pc;
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Short branch conditional
-- 6809 => always 3 cycles
-- cpu09 => always = 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
-- 3 if cc tru pc=pc+md else pc=pc
--
when "0010" => -- branch conditional
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= sbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
--
-- lea - load effective address (2+ bytes)
-- 6809 => 4 cycles + addressing mode
-- cpu09 => 4 cycles + addressing mode
-- 1 op=(pc) / pc=pc+1
-- 2 md_lo=(pc) / pc=pc+1
-- 3 calculate ea
-- 4 ix/iy/sp/up = ea
--
case op_code(3 downto 0) is
when "0000" | -- leax
"0001" | -- leay
"0010" | -- leas
"0011" => -- leau
-- advance PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= lea_state;
next_state <= indexed_state;
--
-- pshs - push registers onto sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
-- 1 op=(pc) / pc=pc+1
-- 2 ea_lo=(pc) / pc=pc+1
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
-- 5 if ea(7) = 1 (sp)=pch
-- if ea(6 downto 0) != "0000000" then sp=sp-1
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
-- 7 if ea(6) = 1 (sp)=uph
-- if ea(5 downto 0) != "000000" then sp=sp-1
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
-- 9 if ea(5) = 1 (sp)=iyh
-- if ea(4 downto 0) != "00000" then sp=sp-1
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
-- 11 if ea(4) = 1 (sp)=ixh
-- if ea(3 downto 0) != "0000" then sp=sp-1
-- 12 if ea(3) = 1 (sp)=dp
-- if ea(2 downto 0) != "000" then sp=sp-1
-- 13 if ea(2) = 1 (sp)=accb
-- if ea(1 downto 0) != "00" then sp=sp-1
-- 14 if ea(1) = 1 (sp)=acca
-- if ea(0 downto 0) != "0" then sp=sp-1
-- 15 if ea(0) = 1 (sp)=cc
--
when "0100" => -- pshs
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshs_state;
--
-- puls - pull registers of sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0101" => -- puls
-- advance PC
pc_ctrl <= incr_pc;
next_state <= puls_state;
--
-- pshu - push registers onto up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0110" => -- pshu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshu_state;
--
-- pulu - pull registers of up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0111" => -- pulu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pulu_state;
--
-- rts - return from subroutine
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode op
-- 3 pc_hi = (sp) / sp=sp+1
-- 4 pc_lo = (sp) / sp=sp+1
--
when "1001" =>
next_state <= pull_return_hi_state;
--
-- ADD accb to index register
-- *** Note: this is an unsigned addition.
-- does not affect any condition codes
-- 6809 => 3 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
--
when "1010" => -- abx
lic <= '1';
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_abx;
ix_ctrl <= load_ix;
next_state <= fetch_state;
--
-- Return From Interrupt
--
when "1011" => -- rti
next_state <= rti_cc_state;
--
-- CWAI
--
when "1100" => -- cwai #$<cc_mask>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment pc
pc_ctrl <= incr_pc;
next_state <= cwai_state;
--
-- MUL Multiply
--
when "1101" => -- mul
next_state <= mul_state;
--
-- SWI Software Interrupt
--
when "1111" => -- swi
-- predecrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi_iv;
st_ctrl <= push_st;
return_state <= int_swimask_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = acca, dest = acca
-- Do not advance PC
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0100" => -- acca single op
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp (not defined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single Operand accb
-- source = accb, dest = accb
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0101" =>
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp (undefined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
-- increment the pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
-- increment PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= extended_state;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cmpx #
"1110" => -- ldx #
next_state <= imm16_state;
--
-- bsr offset - Branch to subroutine (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=pc+md
--
when "1101" => -- bsr
-- pre decrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
next_state <= dual_op_read16_state;
when "0111" => -- sta direct
next_state <= dual_op_write8_state;
--
-- jsr direct - Jump to subroutine in direct page (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=ea
--
when "1101" => -- jsr direct
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
when "1111" => -- stx direct
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- staa ,x
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- jsr ,x
-- DO NOT pre decrement SP
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= indexed_state;
when "1111" => -- stx ,x
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- staa >
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- jsr >extended
-- DO NOT pre decrement sp
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= extended_state;
when "1111" => -- stx >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldu #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
next_state <= dual_op_read16_state;
when "0111" => -- stab direct
next_state <= dual_op_write8_state;
when "1101" => -- std direct
next_state <= dual_op_write16_state;
when "1111" => -- stu direct
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- stab indexed
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- std indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1111" => -- stu indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- stab extended
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- std extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1111" => -- stu extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
--
-- not sure why I need this
--
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode prefix 2 instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode2_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- lbcc -- long branch conditional
-- 6809 => branch 6 cycles, no branch 5 cycles
-- cpu09 => always 5 cycles
-- 1 pre=(pc) / pc=pc+1
-- 2 op=(pc) / pc=pc+1
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 5 if cond pc=pc+md else pc=pc
--
when "0010" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi 2
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi2_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd #
"1100" | -- cmpy #
"1110" => -- ldy #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
next_state <= dual_op_read16_state;
when "1111" => -- sty <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd ,ind
"1100" | -- cmpy ,ind
"1110" => -- ldy ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sty ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sty >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef #
"1100" | -- undef #
"1110" => -- lds #
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef <
"1100" | -- undef <
"1110" => -- lds <
next_state <= dual_op_read16_state;
when "1111" => -- sts <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef ,ind
"1100" | -- undef ,ind
"1110" => -- lds ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sts ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef >
"1100" | -- undef >
"1110" => -- lds >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sts >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode3_state =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi3
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi3_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu #
"1100" | -- cmps #
"1110" => -- undef #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu <
"1100" | -- cmps <
"1110" => -- undef <
next_state <= dual_op_read16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu ,X
"1100" | -- cmps ,X
"1110" => -- undef ,X
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu >
"1100" | -- cmps >
"1110" => -- undef >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte
-- Direct
-- Extended
-- Indexed
-- read memory location
--
when single_op_read_state =>
-- read memory into md
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= single_op_exec_state;
when single_op_exec_state =>
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1011" => -- undefined
lic <= '1';
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
lic <= '1';
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- single operand 8 bit write
-- Write low 8 bits of ALU output
-- EA holds address
-- MD holds data
--
when single_op_write_state =>
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
lic <= '1';
next_state <= fetch_state;
--
-- here if ea holds address of low byte
-- read memory location
--
when dual_op_read8_state =>
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Here to read a 16 bit value into MD
-- pointed to by the EA register
-- The first byte is read
-- and the EA is incremented
--
when dual_op_read16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- read the high byte of the 16 bit data
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= dual_op_read16_2_state;
--
-- here to read the second byte
-- pointed to by EA into MD
--
when dual_op_read16_2_state =>
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit Write state
-- EA hold address of memory to write to
-- Advance the effective address in ALU
-- decode op_code to determine which
-- register to write
--
when dual_op_write16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- write the ALU hi byte at ea
addr_ctrl <= write_ad;
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_hi_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
else
case op_code(3 downto 0) is
when "1101" => -- std
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_hi_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
end if;
next_state <= dual_op_write8_state;
--
-- Dual operand 8 bit write
-- Write 8 bit accumulator
-- or low byte of 16 bit register
-- EA holds address
-- decode opcode to determine
-- which register to apply to the bus
-- Also set the condition codes here
--
when dual_op_write8_state =>
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "0111" => -- sta
dout_ctrl <= acca_dout;
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_lo_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
else
case op_code(3 downto 0) is
when "0111" => -- stb
dout_ctrl <= accb_dout;
when "1101" => -- std
dout_ctrl <= accb_dout; -- accb is low byte of accd
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_lo_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
end if;
-- write ALU low byte output
addr_ctrl <= write_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit immediate addressing mode
--
when imm16_state =>
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
lic <= '1';
next_state <= fetch_state;
--
-- md & ea holds 8 bit index offset
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
--
-- decode indexing mode
--
if md(7) = '0' then
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= md_sign5_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= saved_state;
else
case md(3 downto 0) is
when "0000" => -- ,R+
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
left_ctrl <= sp_left;
end case;
--
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr1_state;
when "0001" => -- ,R++
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr2_state;
when "0010" => -- ,-R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
next_state <= saved_state;
when "0011" => -- ,--R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= two_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0100" => -- ,R (zero offset)
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0101" => -- ACCB,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0110" => -- ACCA,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= acca_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0111" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1000" => -- offset8,R
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index8_state;
when "1001" => -- offset16,R
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index16_state;
when "1010" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
--
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1011" => -- ACCD,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accd_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1100" => -- offset8,PC
-- fetch 8 bit offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel8_state;
when "1101" => -- offset16,PC
-- fetch offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel16_state;
when "1110" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when others =>
-- when "1111" => -- [,address]
-- advance PC to pick up address
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= indexaddr_state;
end case;
end if;
-- load index register with ea plus one
when postincr1_state =>
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- load index register with ea plus two
when postincr2_state =>
-- increment register by two (address)
left_ctrl <= ea_left;
right_ctrl <= two_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- ea = index register + md (8 bit signed offset)
-- ea holds post byte
--
when index8_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- fetch low byte of 16 bit indexed offset
when index16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= index16_2_state;
-- ea = index register + md (16 bit offset)
-- ea holds post byte
when index16_2_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- pc relative with 8 bit signed offest
-- md holds signed offset
--
when pcrel8_state =>
-- ea = pc + signed md
left_ctrl <= pc_left;
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- pc relative addressing with 16 bit offset
-- pick up the low byte of the offset in md
-- advance the pc
when pcrel16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= pcrel16_2_state;
-- pc relative with16 bit signed offest
-- md holds signed offset
when pcrel16_2_state =>
-- ea = pc + md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= indexaddr2_state;
-- indexed to absolute address
-- md holds address
-- ea hold indexing mode byte
when indexaddr2_state =>
-- ea = md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- load md with high byte of indirect address
-- pointed to by ea
-- increment ea
--
when indirect_state =>
-- increment ea
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- fetch high byte
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= indirect2_state;
--
-- load md with low byte of indirect address
-- pointed to by ea
-- ea has previously been incremented
--
when indirect2_state =>
-- fetch high byte
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= indirect3_state;
--
-- complete idirect addressing
-- by loading ea with md
--
when indirect3_state =>
-- load ea with md
left_ctrl <= ea_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
next_state <= saved_state;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
-- return to previous state
next_state <= saved_state;
when lea_state => -- here on load effective address
-- load index register with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_lea;
case op_code(3 downto 0) is
when "0000" => -- leax
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
when "0001" => -- leay
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when "0010" => -- leas
sp_ctrl <= load_sp;
when "0011" => -- leau
up_ctrl <= load_up;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- jump to subroutine
-- sp=sp-1
-- call push_return_lo_state to save pc
-- return to jmp_state
--
when jsr_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- call push_return_state
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
--
-- Load pc with ea
-- (JMP)
--
when jmp_state =>
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
--
-- long branch or branch to subroutine
-- pick up next md byte
-- md_hi = md_lo
-- md_lo = (pc)
-- pc=pc+1
-- if a lbsr push return address
-- continue to sbranch_state
-- to evaluate conditional branches
--
when lbranch_state =>
pc_ctrl <= incr_pc;
-- fetch the next byte into md_lo
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
-- if lbsr - push return address
-- then continue on to short branch
if op_code = "00010111" then
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
else
next_state <= sbranch_state;
end if;
--
-- here to execute conditional branch
-- short conditional branch md = signed 8 bit offset
-- long branch md = 16 bit offset
--
when sbranch_state =>
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
-- Test condition for branch
if op_code(7 downto 4) = "0010" then -- conditional branch
case op_code(3 downto 0) is
when "0000" => -- bra
cond_true := (1 = 1);
when "0001" => -- brn
cond_true := (1 = 0);
when "0010" => -- bhi
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
when "0011" => -- bls
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
when "0100" => -- bcc/bhs
cond_true := (cc(CBIT) = '0');
when "0101" => -- bcs/blo
cond_true := (cc(CBIT) = '1');
when "0110" => -- bne
cond_true := (cc(ZBIT) = '0');
when "0111" => -- beq
cond_true := (cc(ZBIT) = '1');
when "1000" => -- bvc
cond_true := (cc(VBIT) = '0');
when "1001" => -- bvs
cond_true := (cc(VBIT) = '1');
when "1010" => -- bpl
cond_true := (cc(NBIT) = '0');
when "1011" => -- bmi
cond_true := (cc(NBIT) = '1');
when "1100" => -- bge
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
when "1101" => -- blt
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
when "1110" => -- bgt
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
when "1111" => -- ble
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
when others =>
null;
end case;
end if;
if cond_true then
pc_ctrl <= load_pc;
end if;
lic <= '1';
next_state <= fetch_state;
--
-- push return address onto the S stack
--
-- (sp) = pc_lo
-- sp = sp - 1
--
when push_return_lo_state =>
-- decrement the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write PC low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= push_return_hi_state;
--
-- push program counter hi byte onto the stack
-- (sp) = pc_hi
-- sp = sp
-- return to originating state
--
when push_return_hi_state =>
-- write pc hi bytes
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
next_state <= saved_state;
--
-- RTS pull return address from stack
--
when pull_return_hi_state =>
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= pull_return_lo_state;
when pull_return_lo_state =>
-- increment the SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
lic <= '1';
next_state <= fetch_state;
when andcc_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when orcc_state =>
-- OR CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_orcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when tfr_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
--
lic <= '1';
next_state <= fetch_state;
when exg_state =>
-- save destination register
case md(3 downto 0) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
ea_ctrl <= load_ea;
-- call tranfer microcode
next_state <= exg1_state;
when exg1_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
next_state <= exg2_state;
when exg2_state =>
-- restore destination
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- save as source register
case md(7 downto 4) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
when mul_state =>
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
md_ctrl <= load_md;
next_state <= mulea_state;
when mulea_state =>
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
ea_ctrl <= load_ea;
next_state <= muld_state;
when muld_state =>
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
next_state <= mul0_state;
when mul0_state =>
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(0) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul1_state;
when mul1_state =>
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(1) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul2_state;
when mul2_state =>
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(2) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul3_state;
when mul3_state =>
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(3) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul4_state;
when mul4_state =>
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(4) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul5_state;
when mul5_state =>
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(5) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul6_state;
when mul6_state =>
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(6) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul7_state;
when mul7_state =>
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(7) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pushs
-- ea holds post byte
--
when pshs_state =>
-- decrement sp if any registers to be pushed
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
-- idle address
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
if ea(7 downto 0) = "00000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
if ea(7) = '1' then
next_state <= pshs_pcl_state;
elsif ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshs_pch_state;
when pshs_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= pshs_uph_state;
when pshs_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
if ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshs_iyh_state;
when pshs_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write iy hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshs_ixh_state;
when pshs_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write dp
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '1' then
sp_ctrl <= load_sp;
else
sp_ctrl <= latch_sp;
end if;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_cc_state =>
-- idle sp
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULS
-- ea hold register mask
--
when puls_state =>
if ea(0) = '1' then
next_state <= puls_cc_state;
elsif ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
if ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
if ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
if ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
if ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= puls_ixl_state;
when puls_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
if ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= puls_iyl_state;
when puls_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
if ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= puls_upl_state;
when puls_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
if ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= puls_pcl_state;
when puls_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pshu
-- ea holds post byte
--
when pshu_state =>
-- decrement up if any registers to be pushed
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write idle bus
if ea(7) = '1' then
next_state <= pshu_pcl_state;
elsif ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
--
-- push PC onto U stack
--
when pshu_pcl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshu_pch_state;
when pshu_pch_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write pc hi
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_spl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write sp low
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_lo_dout;
next_state <= pshu_sph_state;
when pshu_sph_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write sp hi
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_hi_dout;
if ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_iyl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write iy low
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshu_iyh_state;
when pshu_iyh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write iy hi
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_ixl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write ix low
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshu_ixh_state;
when pshu_ixh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write ix hi
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_dp_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write dp
addr_ctrl <= pushu_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_accb_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write accb
addr_ctrl <= pushu_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_acca_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '0' then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write acca
addr_ctrl <= pushu_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_cc_state =>
-- idle up
-- write cc
addr_ctrl <= pushu_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULU
-- ea hold register mask
--
when pulu_state =>
-- idle UP
-- idle bus
if ea(0) = '1' then
next_state <= pulu_cc_state;
elsif ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_cc_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pullu_ad;
if ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_acca_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pullu_ad;
if ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_accb_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pullu_ad;
if ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_dp_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pullu_ad;
if ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_ixh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pullu_ad;
next_state <= pulu_ixl_state;
when pulu_ixl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pullu_ad;
if ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_iyh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pullu_ad;
next_state <= pulu_iyl_state;
when pulu_iyl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pullu_ad;
if ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_sph_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp hi
sp_ctrl <= pull_hi_sp;
addr_ctrl <= pullu_ad;
next_state <= pulu_spl_state;
when pulu_spl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp low
sp_ctrl <= pull_lo_sp;
addr_ctrl <= pullu_ad;
if ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_pch_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pullu_ad;
next_state <= pulu_pcl_state;
when pulu_pcl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pullu_ad;
lic <= '1';
next_state <= fetch_state;
--
-- pop the Condition codes
--
when rti_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
next_state <= rti_entire_state;
--
-- Added RTI cycle 11th July 2006 John Kent.
-- test the "Entire" Flag
-- that has just been popped off the stack
--
when rti_entire_state =>
--
-- The Entire flag must be recovered from the stack
-- before testing.
--
if cc(EBIT) = '1' then
next_state <= rti_acca_state;
else
next_state <= rti_pch_state;
end if;
when rti_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
next_state <= rti_accb_state;
when rti_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
next_state <= rti_dp_state;
when rti_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_iyh_state;
when rti_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_iyl_state;
when rti_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_uph_state;
when rti_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= rti_upl_state;
when rti_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
next_state <= rti_pch_state;
when rti_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- here on NMI interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_nmi_state =>
next_state <= int_nmi1_state;
-- Idle bus cycle
when int_nmi1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= nmi_iv;
st_ctrl <= push_st;
return_state <= int_nmimask_state;
next_state <= int_entire_state;
--
-- here on IRQ interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_irq_state =>
next_state <= int_irq1_state;
-- pre decrement the sp
-- Idle bus cycle
when int_irq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= irq_iv;
st_ctrl <= push_st;
return_state <= int_irqmask_state;
next_state <= int_entire_state;
--
-- here on FIRQ interrupt
-- Complete execution cycle of the last instruction
-- if it was a dual operand instruction
--
when int_firq_state =>
next_state <= int_firq1_state;
-- Idle bus cycle
when int_firq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= firq_iv;
st_ctrl <= push_st;
return_state <= int_firqmask_state;
next_state <= int_fast_state;
--
-- CWAI entry point
-- stack pointer already pre-decremented
-- mask condition codes
--
when cwai_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
st_ctrl <= push_st;
return_state <= int_cwai_state;
next_state <= int_entire_state;
--
-- wait here for an interrupt
--
when int_cwai_state =>
if (nmi_req = '1') then
iv_ctrl <= nmi_iv;
next_state <= int_nmimask_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') and (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
next_state <= int_firqmask_state;
elsif (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_irqmask_state;
else
next_state <= int_cwai_state;
end if;
--
-- State to mask I Flag and F Flag (NMI)
--
when int_nmimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (FIRQ)
--
when int_firqmask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (SWI)
--
when int_swimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag only (IRQ)
--
when int_irqmask_state =>
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
-- before stacking all registers
--
when int_entire_state =>
-- set entire flag
alu_ctrl <= alu_see;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
--
-- clear Entire Flag on FIRQ
-- before stacking all registers
--
when int_fast_state =>
-- clear entire flag
alu_ctrl <= alu_cle;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
when int_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
when int_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if cc(EBIT) = '1' then
next_state <= int_upl_state;
else
next_state <= int_cc_state;
end if;
when int_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write up low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= int_uph_state;
when int_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
next_state <= int_iyl_state;
when int_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= int_iyh_state;
when int_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
next_state <= int_ixl_state;
when int_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
when int_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_dp_state;
when int_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
next_state <= int_accb_state;
when int_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
next_state <= int_acca_state;
when int_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
next_state <= int_cc_state;
when int_cc_state =>
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
next_state <= saved_state;
--
-- According to the 6809 programming manual:
-- If an interrupt is received and is masked
-- or lasts for less than three cycles, the PC
-- will advance to the next instruction.
-- If an interrupt is unmasked and lasts
-- for more than three cycles, an interrupt
-- will be generated.
-- Note that I don't wait 3 clock cycles.
-- John Kent 11th July 2006
--
when sync_state =>
lic <= '1';
ba <= '1';
next_state <= sync_state;
when halt_state =>
--
-- 2011-10-30 John Kent
-- ba & bs should be high
ba <= '1';
bs <= '1';
if halt = '1' then
next_state <= halt_state;
else
next_state <= fetch_state;
end if;
end case;
--
-- Ver 1.23 2011-10-30 John Kent
-- First instruction cycle might be
-- fetch_state
-- halt_state
-- int_nmirq_state
-- int_firq_state
--
if fic = '1' then
--
case op_code(7 downto 6) is
when "10" => -- acca
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0011" =>
case pre_code is
when "00010000" => -- page 2 -- cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmpu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end case;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1100" =>
case pre_code is
when "00010000" => -- page 2 -- cmpy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmps
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- cmpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
end case;
when "1101" => -- bsr / jsr
null;
when "1110" => -- ldx
case pre_code is
when "00010000" => -- page 2 -- ldy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when others => -- page 1 -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
end case;
when "1111" => -- stx
case pre_code is
when "00010000" => -- page 2 -- sty
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when "11" => -- accb dual op
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when "1110" => -- ldu
case pre_code is
when "00010000" => -- page 2 -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
sp_ctrl <= load_sp;
when others => -- page 1 -- ldu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
up_ctrl <= load_up;
end case;
when "1111" =>
case pre_code is
when "00010000" => -- page 2 -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when others =>
null;
end case;
end if; -- first instruction cycle (fic)
lic_out <= lic;
end process;
end rtl;
|
gpl-3.0
|
62b57a22b39a5d8535fcead858bfa1ba
| 0.456334 | 3.635485 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/DMA_Calculate.vhd
| 1 | 33,957 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: DMA_Calculate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.20 - Taken out from the original version. 26.07.2007
--
-- Revision 1.10 - Msg inserted. 26.02.2007
--
-- Revision 1.00 - Created. 09.02.2007
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_Calculate is
port (
-- Downstream Registers from MWr Channel
DMA_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : in std_logic;
BDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : in std_logic;
Leng_Lo7b_True : in std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : out std_logic;
DMA_Snout_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Only for downstream channel
DMA_PA_Snout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : out std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Engine control signals
DMA_Start : in std_logic;
DMA_Start2 : in std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : out std_logic; -- No more block(s) of Max_Size
ThereIs_Snout : out std_logic; -- 1st packet before Body blocks
ThereIs_Body : out std_logic; -- Block(s) of Max_Size
ThereIs_Tail : out std_logic; -- Last packet with size less than Max_Size
ThereIs_Dex : out std_logic; -- Not the last descriptor
HA64bit : out std_logic; -- Host Address is 64-bit
Addr_Inc : out std_logic; -- Peripheral Address increase token
-- FSM indicators
State_Is_LoadParam : in std_logic;
State_Is_Snout : in std_logic;
State_Is_Body : in std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : in std_logic_vector(2 downto 0);
-- Common ports
dma_clk : in std_logic;
dma_reset : in std_logic
);
end entity DMA_Calculate;
architecture Behavioral of DMA_Calculate is
-- Significant bits from the MaXSiZe parameter
signal Max_TLP_Size : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal mxsz_left : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_mid : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_right : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Signals masked by MaxSize
signal DMA_Leng_Left_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Mid_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Right_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Alias
signal Lo_Leng_Left_Msk_is_True : std_logic;
signal Lo_Leng_Mid_Msk_is_True : std_logic;
signal Lo_Leng_Right_Msk_is_True : std_logic;
-- Masked values of HA and Length
signal DMA_HA_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Length_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Indicates whether the DMA_PA is already accepted
signal PA_is_taken : std_logic;
-- Calculation for the PA of the next DMA, if UPA bit = 0
signal DMA_PA_next : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_PA_current : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- eventual PA parameter for the current DMA transaction
signal DMA_PA_Loaded_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, only for better timing
signal Carry_PA_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Carry_PAx_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Leng_Hi_plus_PA_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
signal Leng_Hi_plus_PAx_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
-- DMA parameters from the register module
signal DMA_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- delay
signal State_Is_Snout_r1 : std_logic;
signal State_Is_Body_r1 : std_logic;
-- from control word
signal Dex_is_Last : std_logic;
signal Engine_Ends : std_logic;
-- Major FSM control signals
signal ThereIs_Snout_i : std_logic;
signal ThereIs_Body_i : std_logic;
signal ThereIs_Tail_i : std_logic;
signal Snout_Only : std_logic;
signal ThereIs_Dex_i : std_logic;
signal No_More_Bodies_i : std_logic;
-- Address/Length combination
signal ALc : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Compressed ALc
-- ALc_B bit means the ALc has carry in, making an extra Body block.
signal ALc_B : std_logic;
signal ALc_B_wire : std_logic;
-- ALc_T bit means the ALc has trailer, making a final Tail block.
signal ALc_T : std_logic;
signal ALc_T_wire : std_logic;
-- Compressed Length
-- Leng_Two bit means Length >= 2 Max_Size.
signal Leng_Two : std_logic;
-- Leng_One bit means Length >= 1 Max_Size.
signal Leng_One : std_logic;
-- Leng_nint bit means Length is not integral of Max_Sizes.
signal Leng_nint : std_logic;
signal Length_analysis : std_logic_vector(2 downto 0);
signal Snout_Body_Tail : std_logic_vector(2 downto 0);
-- Byte counter
signal DMA_Byte_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- !!! Elastic
signal Length_minus : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BC_Carry : std_logic_vector(CBIT_CARRY downto 0);
-- Remote & Local Address variable
signal DMA_HA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_Carry32 : std_logic_vector(C_DBUS_WIDTH/2 downto 0);
signal DMA_PA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- BDA parameter is buffered for FSM module
signal DMA_BDA_fsm_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal BDA_is_64b_fsm_i : std_logic;
-- Token bits out of Control word
signal HA64bit_i : std_logic;
signal Addr_Inc_i : std_logic;
signal use_PA : std_logic;
-- for better timing
signal HA_gap : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
--
signal DMA_Snout_Length_i : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Tail_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- for better timing
signal raw_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal DMA_PA_Snout_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_PA_Body_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_BAR_Number_i : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
begin
-- Partition indicators
No_More_Bodies <= No_More_Bodies_i;
ThereIs_Snout <= ThereIs_Snout_i;
ThereIs_Body <= ThereIs_Body_i;
ThereIs_Tail <= ThereIs_Tail_i;
ThereIs_Dex <= ThereIs_Dex_i;
HA64bit <= HA64bit_i;
Addr_Inc <= Addr_Inc_i;
--
DMA_PA_Loaded <= DMA_PA_Loaded_i;
DMA_PA_Var <= DMA_PA_Var_i;
DMA_HA_Var <= DMA_HA_Var_i;
DMA_BDA_fsm <= DMA_BDA_fsm_i;
BDA_is_64b_fsm <= BDA_is_64b_fsm_i;
-- Only for downstream channel
DMA_PA_Snout <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number <= DMA_BAR_Number_i;
-- different lengths
DMA_Snout_Length <= DMA_Snout_Length_i;
DMA_Body_Length <= Max_TLP_Size;
DMA_Tail_Length <= DMA_Tail_Length_i;
-- Register stubs
DMA_PA_i <= DMA_PA;
DMA_HA_i <= DMA_HA;
DMA_BDA_i <= DMA_BDA;
DMA_Length_i <= DMA_Length;
DMA_Control_i <= DMA_Control;
-- ---------------------------------------------------------------
-- Parameters should be captured by the start/start2 and be kept
-- in case Pause command comes.
--
Syn_Param_Capture :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Addr_Inc_i <= '0';
use_PA <= '0';
Dex_is_Last <= '0';
Engine_Ends <= '1';
DMA_BAR_Number_i <= (others => '0');
DMA_BDA_fsm_i <= (others => '0');
BDA_is_64b_fsm_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' or DMA_Start2 = '1' then
Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
DMA_BAR_Number_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_BAR_TOP downto CINT_BIT_DMA_CTRL_BAR_BOT);
DMA_BDA_fsm_i <= DMA_BDA_i;
BDA_is_64b_fsm_i <= BDA_is_64b;
else
Addr_Inc_i <= Addr_Inc_i;
use_PA <= use_PA;
Dex_is_Last <= Dex_is_Last;
Engine_Ends <= Engine_Ends;
DMA_BAR_Number_i <= DMA_BAR_Number_i;
DMA_BDA_fsm_i <= DMA_BDA_fsm_i;
BDA_is_64b_fsm_i <= BDA_is_64b_fsm_i;
end if;
end if;
end process;
-- Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
-- use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
-- Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
-- Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
-- use_Irpt_Done <= not DMA_Control_i(CINT_BIT_DMA_CTRL_EDI);
-- Means there is consecutive descriptor(s)
ThereIs_Dex_i <= not Dex_is_Last and not Engine_Ends;
-- ---------------------------------------------------------------
-- PA_i selection
--
Syn_Calc_DMA_PA :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_current <= (others => '0');
-- DMA_BAR_Number_i <= (Others=>'0');
PA_is_taken <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken = '0' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken = '0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '1' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken = '0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '0' then
DMA_PA_current(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_next;
PA_is_taken <= '1';
else
DMA_PA_current <= DMA_PA_current;
if DMA_Start = '0' and DMA_Start2 = '0' then
PA_is_taken <= '0';
else
PA_is_taken <= PA_is_taken;
end if;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- PA_next Calculation
--
Syn_Calc_DMA_PA_next :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_next <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken = '0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PA_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PA_Hi
+ Carry_PA_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
end if;
elsif DMA_Start2 = '1' and PA_is_taken = '0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PAx_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PAx_Hi
+ Carry_PAx_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_next;
end if;
else
DMA_PA_next <= DMA_PA_next;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PA_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PA_plus_Leng :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PA_plus_Leng <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PA_plus_Leng <= ('0'& DMA_PA_i(CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PAx_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PAx_plus_Leng :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PAx_plus_Leng <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PAx_plus_Leng <= ('0'& DMA_PA_next (CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PA_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PA_Hi :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PA_Hi <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PA_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_i(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PAx_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PAx_Hi :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PAx_Hi <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PAx_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_Leng_Left_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left;
DMA_Leng_Mid_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid;
DMA_Leng_Right_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_HA_Msk <= (DMA_HA_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_HA_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
DMA_Length_Msk <= (DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_Length_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
-- -----------------------------------------------------------------------------------------------------------------------------------
Lo_Leng_Left_Msk_is_True <= '0' when DMA_Leng_Left_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Mid_Msk_is_True <= '0' when DMA_Leng_Mid_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Right_Msk_is_True <= '0' when DMA_Leng_Right_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
-- ----------------------------------------------------------
-- Synchronous Register: Leng_Info(Compressed Length Information)
---
Syn_Calc_Parameter_Leng_Info :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Two <= '0';
Leng_One <= '0';
Leng_nint <= '0';
elsif dma_clk'event and dma_clk = '1' then
Leng_Two <= Leng_Hi19b_True or Lo_Leng_Left_Msk_is_True;
Leng_One <= Lo_Leng_Mid_Msk_is_True;
Leng_nint <= Leng_Lo7b_True or Lo_Leng_Right_Msk_is_True;
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
ALc_B_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
else '1';
ALc_T_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and ALc(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)
else '1';
-- -----------------------------------------------------------------------------------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Register: ALc (Address-Length combination)
---
Syn_Calc_Parameter_ALc :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
ALc <= (others => '0');
ALc_B <= '0';
ALc_T <= '0';
elsif dma_clk'event and dma_clk = '1' then
ALc <= DMA_Length_Msk + DMA_HA_Msk;
ALc_B <= ALc_B_wire;
ALc_T <= ALc_T_wire;
end if;
end process;
-- concatenation of the Length information
Length_analysis <= Leng_Two & Leng_One & Leng_nint;
-- -------------------------------------------
-- Analysis on the DMA division
-- truth-table expressions
--
Comb_S_B_T :
process (
Length_analysis
, ALc_B
, ALc_T
)
begin
case Length_analysis is
-- Zero-length DMA, nothing to send
when "000" =>
Snout_Body_Tail <= "000";
-- Length < Max_Size. Always Snout and never Body, Tail depends on ALc.
when "001" =>
Snout_Body_Tail <= '1' & '0' & (ALc_B and ALc_T);
-- Length = Max_Size. Division depends only on ALc-Tail.
when "010" =>
Snout_Body_Tail <= ALc_T & not ALc_T & ALc_T;
-- Length = (k+1) Max_Size, k>=1. Always Body. Snout and Tail depend on ALc-Tail.
-- Body = Leng_Two or not ALc_T
when "100" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
when "110" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
-- Length = (1+d) Max_Size, 0<d<1. Always Snout. Body and Tail copy ALc.
when "011" =>
Snout_Body_Tail <= '1' & ALc_B & ALc_T;
-- Length = (k+1+d) Max_Size, k>=1, 0<d<1. Always Snout and Body. Tail copies ALc-Tail.
-- Body = Leng_Two or ALc_B
when "101" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
when "111" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
-- dealt as zero-length DMA
when others =>
Snout_Body_Tail <= "000";
end case;
end process;
-- -----------------------------------------------
-- Synchronous Register:
-- ThereIs_Snout
-- ThereIs_Body
-- ThereIs_Tail
--
Syn_Calc_Parameters_SBT :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
ThereIs_Snout_i <= '0';
ThereIs_Body_i <= '0';
ThereIs_Tail_i <= '0';
Snout_Only <= '0';
elsif dma_clk'event and dma_clk = '1' then
ThereIs_Snout_i <= Snout_Body_Tail(2);
ThereIs_Body_i <= Snout_Body_Tail(1);
ThereIs_Tail_i <= Snout_Body_Tail(0);
Snout_Only <= ALc_T and not Snout_Body_Tail(0);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA_gap
--
Syn_Calc_HA_gap :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA_gap <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
HA_gap <= Max_TLP_Size - DMA_HA_Msk;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Snout_Carry
--
FSM_Calc_DMA_PA_Snout_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Snout_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Snout_Carry <= ('0'& DMA_PA_current(CBIT_CARRY-1 downto 0)) + HA_gap;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Body_Carry
--
FSM_Calc_DMA_PA_Body_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Body_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Body_Carry <= ('0'& DMA_PA_Var_i(CBIT_CARRY-1 downto 0)) + Max_TLP_Size;
end if;
end process;
-- ------------------------------------------------------------------
-- Synchronous Register: Length_minus
--
Sync_Calc_Length_minus :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Length_minus <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Length_minus <= DMA_Length_i - Max_TLP_Size;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_BC_Carry
--
FSM_Calc_DMA_BC_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_BC_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_BC_Carry <= ('0'& DMA_Byte_Counter(CBIT_CARRY-1 downto 0)) - Max_TLP_Size;
end if;
end process;
-- --------------------------------------------
-- Synchronous reg: DMA_Snout_Length
-- DMA_Tail_Length
--
FSM_Calc_DMA_Snout_Tail_Lengths :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Snout_Length_i <= (others => '0');
DMA_Tail_Length_i <= (others => '0');
raw_Tail_Length <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_Tail_Length_i(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= (raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
and mxsz_right(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
) & raw_Tail_Length( C_MAXSIZE_FLD_BIT_BOT-1 downto 0);
if State_Is_LoadParam = '1' then
raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= DMA_Length_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
+ DMA_HA_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
if Snout_Only = '1' then
DMA_Snout_Length_i <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto 2) &"00";
else
DMA_Snout_Length_i <= Max_TLP_Size - DMA_HA_Msk;
end if;
else
DMA_Snout_Length_i <= DMA_Snout_Length_i;
raw_Tail_Length <= raw_Tail_Length;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous Delays:
-- State_Is_Snout_r1
-- State_Is_Body_r1
--
Syn_Delay_State_is_x :
process (dma_clk)
begin
if dma_clk'event and dma_clk = '1' then
State_Is_Snout_r1 <= State_Is_Snout;
State_Is_Body_r1 <= State_Is_Body;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Carry32
--
FSM_Calc_DMA_HA_Carry32 :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Carry32 <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Carry32 <= '0' & DMA_HA_i(C_DBUS_WIDTH/2-1 downto 2) & "00"; -- temp
elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Carry32(C_DBUS_WIDTH/2 downto C_MAXSIZE_FLD_BIT_BOT) <= ('0'& DMA_HA_Var_i(C_DBUS_WIDTH/2-1 downto C_MAXSIZE_FLD_BIT_TOP+1) &
(DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right)
) + mxsz_mid;
else
DMA_HA_Carry32 <= DMA_HA_Carry32;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Var
--
FSM_Calc_DMA_HA_Var :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Var_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Var_i <= DMA_HA_i(C_DBUS_WIDTH-1 downto 2) & "00"; -- temp
elsif State_Is_Snout_r1 = '1' or State_Is_Body_r1 = '1' then
-- elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) <= DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
+ DMA_HA_Carry32(C_DBUS_WIDTH/2);
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_BOT) <= (DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
& (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right))
+ mxsz_mid;
DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) <= (others => '0'); -- MaxSize aligned
else
DMA_HA_Var_i <= DMA_HA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA64bit
--
FSM_Calc_HA64bit :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA64bit_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
HA64bit_i <= HA_is_64b;
elsif DMA_HA_Carry32(C_DBUS_WIDTH/2) = '1' then
HA64bit_i <= '1';
else
HA64bit_i <= HA64bit_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Var
--
FSM_Calc_DMA_PA_Var :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Var_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if Addr_Inc_i = '1' and ThereIs_Snout_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_current(CBIT_CARRY-1 downto 0)
+ HA_gap(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_current(C_DBUS_WIDTH-1 downto CBIT_CARRY);
else
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
end if;
elsif State_Is_Snout_r1 = '1' then
---- elsif State_Is_Snout = '1' then
if Addr_Inc_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Var_i(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Snout_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
elsif State_Is_Body_r1 = '1' then
---- elsif State_Is_Body = '1' then
if Addr_Inc_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Body_Carry(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Body_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Loaded_i
--
FSM_Calc_DMA_PA_Loaded_i :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Loaded_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_PA_Loaded_i <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
else
DMA_PA_Loaded_i <= DMA_PA_Loaded_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: DMA_Byte_Counter
---
FSM_Calc_DMA_Byte_Counter :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Byte_Counter <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if ALc_B = '0' and ALc_T = '1' then
DMA_Byte_Counter <= Length_minus;
else
DMA_Byte_Counter <= DMA_Length_i(C_DBUS_WIDTH-1 downto 2) & "00";
end if;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY)
- DMA_BC_Carry(CBIT_CARRY);
DMA_Byte_Counter(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT) <= DMA_BC_Carry(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT);
else
DMA_Byte_Counter <= DMA_Byte_Counter;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: No_More_Bodies
---
FSM_Calc_No_More_Bodies :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
No_More_Bodies_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
No_More_Bodies_i <= not ThereIs_Body_i;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
if DMA_Byte_Counter(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1) = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid) /= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
then
No_More_Bodies_i <= '1';
else
No_More_Bodies_i <= '0';
end if;
else
No_More_Bodies_i <= No_More_Bodies_i;
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: Param_Max_Cfg
--
Syn_Config_Param_Max_Cfg :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then -- 0x0080 Bytes
mxsz_left <= "111110"; -- 6 bits
mxsz_mid <= "000001"; -- 6 bits
mxsz_right <= "000000"; -- 6 bits
elsif dma_clk'event and dma_clk = '1' then
case Param_Max_Cfg is
when "000" => -- 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
when "001" => -- 0x0100 Bytes
mxsz_left <= "111100";
mxsz_mid <= "000010";
mxsz_right <= "000001";
when "010" => -- 0x0200 Bytes
mxsz_left <= "111000";
mxsz_mid <= "000100";
mxsz_right <= "000011";
when "011" => -- 0x0400 Bytes
mxsz_left <= "110000";
mxsz_mid <= "001000";
mxsz_right <= "000111";
when "100" => -- 0x0800 Bytes
mxsz_left <= "100000";
mxsz_mid <= "010000";
mxsz_right <= "001111";
when "101" => -- 0x1000 Bytes
mxsz_left <= "000000";
mxsz_mid <= "100000";
mxsz_right <= "011111";
when others => -- as 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
end case;
end if;
end process;
Max_TLP_Size <= mxsz_mid & CONV_STD_LOGIC_VECTOR(0, C_MAXSIZE_FLD_BIT_BOT);
end architecture Behavioral;
|
lgpl-3.0
|
bf11e79e16059be9293804ecdc840b82
| 0.527019 | 3.26196 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd
| 1 | 3,777 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.adc_pkg.all;
entity fmc150_adc_if is
generic (
g_sim : integer := 0
);
port
(
--clk_200MHz_i : in std_logic;
clk_100MHz_i : in std_logic;
rst_i : in std_logic;
cha_p_i : in std_logic_vector(6 downto 0);
cha_n_i : in std_logic_vector(6 downto 0);
chb_p_i : in std_logic_vector(6 downto 0);
chb_n_i : in std_logic_vector(6 downto 0);
str_p_i : in std_logic;
str_n_i : in std_logic;
cha_data_o : out std_logic_vector(13 downto 0);
chb_data_o : out std_logic_vector(13 downto 0);
clk_adc_i : in std_logic;
str_o : out std_logic;
delay_update_i : in std_logic;
str_cntvalue_i : in std_logic_vector(4 downto 0);
cha_cntvalue_i : in std_logic_vector(4 downto 0);
chb_cntvalue_i : in std_logic_vector(4 downto 0);
str_cntvalue_o : out std_logic_vector(4 downto 0)
);
end fmc150_adc_if;
architecture rtl of fmc150_adc_if is
--------------------------------------------------------------------
-- Signal declaration
--------------------------------------------------------------------
-- ADC data strobe
signal s_adc_str_dly : std_logic;
signal s_adc_str : std_logic;
-- ADC data streams on Single Data Rate (SDR)
signal s_adc_cha_sdr : std_logic_vector(13 downto 0);
signal s_adc_chb_sdr : std_logic_vector(13 downto 0);
begin
-- Synthesis Only!
gen_adc_clk : if (g_sim = 0) generate
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
end generate;
-- Simulation Only!
gen_adc_clk_sim : if (g_sim = 1) generate
s_adc_str_dly <= str_p_i and str_n_i;
end generate;
-- s_adc_str_dly is a regional clock driven by BUFR.
-- Must go through a BUFG before other components (BPM DDC)
-- ADC strobe must be routed on a global net
--cmp_adc_str_bufg: bufg
--port map
--(
-- i => s_adc_str_dly,
-- o => s_adc_str
--);
--str_o <= s_adc_str;
str_o <= s_adc_str_dly;
-- ADC channel A with adjustable delay
cmp_adc_cha: adc_channel_lvds_ddr
generic map
(
C_NBITS => 14,
C_DEFAULT_DELAY => 15
)
port map
(
clk_adc_i => s_adc_str_dly,--clk_adc_i,
clk_ctrl_i => clk_100MHz_i,
adc_p_i => cha_p_i,
adc_n_i => cha_n_i,
adc_data_o => cha_data_o,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => cha_cntvalue_i
);
-- ADC channel B with adjustable delay
cmp_adc_chb: adc_channel_lvds_ddr
generic map
(
C_NBITS => 14,
C_DEFAULT_DELAY => 15
)
port map
(
clk_adc_i => s_adc_str_dly,--clk_adc_i,
clk_ctrl_i => clk_100MHz_i,
adc_p_i => chb_p_i,
adc_n_i => chb_n_i,
adc_data_o => chb_data_o,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => chb_cntvalue_i
);
end rtl;
|
lgpl-3.0
|
5ec76ac0667f3ea9ae2ae237079a6b63
| 0.488218 | 3.301573 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/cpu/t80_pack.vhd
| 2 | 8,347 |
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
ALU_cpi : out std_logic;
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_cpi : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
|
gpl-3.0
|
5687f5cc5f60f74621a7a896ec95406c
| 0.531329 | 3.733005 | false | false | false | false |
z3774/sparcv8-monocycle
|
MUX_RF_DWR.vhd
| 1 | 936 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_RF_DWR is
Port (
data_dm : in STD_LOGIC_VECTOR (31 downto 0);
alurs : in STD_LOGIC_VECTOR (31 downto 0);
pc : in STD_LOGIC_VECTOR (31 downto 0);
rf_src : in STD_LOGIC_VECTOR (1 downto 0);
rf_data : out STD_LOGIC_VECTOR (31 downto 0)
);
end MUX_RF_DWR;
architecture Behavioral of MUX_RF_DWR is
begin
process(data_dm,alurs,pc,rf_src)
begin
case rf_src is
when "00" =>
rf_data <= data_dm;
when "01" =>
rf_data <= alurs;
when "10" =>
rf_data <= pc;
when others =>
rf_data <= (others =>'0');
end case;
end process;
end Behavioral;
|
gpl-3.0
|
f5b0c6db2a224294c061a2270df226c4
| 0.667735 | 2.962025 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/syn-wxedax/wxedax_top.vhd
| 1 | 23,231 |
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--library unisim;
--use unisim.vcomponents.all;
use work.msx_pack.all;
entity wxedax_top is
generic (
use_i2s_g : boolean := true;
per_opll_g : boolean := true;
per_jt51_g : boolean := false
);
port (
-- Clock (48MHz)
clock_48M_i : in std_logic;
-- SDRAM (W9864G6JH-6 = 4Mx16 = 8MB)
sdram_clock_o : out std_logic := '0';
sdram_cke_o : out std_logic := '0';
sdram_addr_o : out std_logic_vector(11 downto 0) := (others => '0');
sdram_dq_io : inout std_logic_vector(15 downto 0);
sdram_ba_o : out std_logic_vector( 1 downto 0) := (others => '0');
sdram_dqml_o : out std_logic;
sdram_dqmh_o : out std_logic;
sdram_cs_n_o : out std_logic := '1';
sdram_we_n_o : out std_logic := '1';
sdram_cas_n_o : out std_logic := '1';
sdram_ras_n_o : out std_logic := '1';
-- SPI FLASH (FPGA and Aux)
flashf_clk_o : out std_logic := '0';
flashf_data_i : in std_logic;
flashf_data_o : out std_logic := '0';
flashf_cs_n_o : out std_logic := '1';
-- flash2_clk_o : out std_logic := '0';
-- flash2_data_i : in std_logic;
-- flash2_data_o : out std_logic := '0';
flash2_cs_n_o : out std_logic := '1';
-- VGA 5:6:5
vga_r_o : out std_logic_vector(4 downto 0) := (others => '0');
vga_g_o : out std_logic_vector(5 downto 0) := (others => '0');
vga_b_o : out std_logic_vector(4 downto 0) := (others => '0');
vga_hs_o : out std_logic := '1';
vga_vs_o : out std_logic := '1';
-- -- UART
uart_tx_o : out std_logic := '1';
uart_rx_i : in std_logic;
-- Keys and Leds
keys_n_i : in std_logic_vector(4 downto 1);
leds_n_o : out std_logic_vector(3 downto 0) := (others => '1');
-- PS/2 Keyboard
ps2_clk_io : inout std_logic := 'Z';
ps2_dat_io : inout std_logic := 'Z';
-- ADC
adc_clock_o : out std_logic := '0';
adc_data_i : in std_logic;
adc_cs_n_o : out std_logic := '1';
-- Audio
i2s_mclk_o : out std_logic := '0';
i2s_bclk_o : out std_logic := '0';
i2s_lrclk_o : out std_logic := '0';
i2s_data_o : out std_logic := '0';
buzzer_o : out std_logic := '1';
-- SD Card
sd_cs_n_o : out std_logic := '1';
sd_sclk_o : out std_logic := '0';
sd_mosi_o : out std_logic := '0';
sd_miso_i : in std_logic;
sd_pres_n_i : in std_logic;
sd_wp_i : in std_logic;
-- Joystick SNES
pad_clk_o : out std_logic := '0';
pad_latch_o : out std_logic := '0';
pad_data_i : in std_logic;
-- Others
-- irda_o : out std_logic := '0';
gpio_io : inout std_logic_vector(1 downto 0) := (others => 'Z')
);
end;
architecture behavior of wxedax_top is
-- Resets
signal por_cnt_s : unsigned(7 downto 0) := (others => '1');
signal por_clock_s : std_logic;
signal por_s : std_logic;
signal reset_s : std_logic;
signal reset_n_s : std_logic;
signal soft_por_s : std_logic;
signal soft_reset_k_s : std_logic;
signal soft_reset_s_s : std_logic;
signal soft_rst_cnt_s : unsigned(7 downto 0) := X"FF";
signal reload_s : std_logic;
attribute clock_signal : string;
-- Clocks
signal clock_master_s : std_logic; attribute clock_signal of clock_master_s : signal is "yes";
signal clock_sdram_s : std_logic; attribute clock_signal of clock_sdram_s : signal is "yes";
signal clock_vdp_s : std_logic; attribute clock_signal of clock_vdp_s : signal is "yes";
signal clock_cpu_s : std_logic; attribute clock_signal of clock_cpu_s : signal is "yes";
signal clock_psg_en_s : std_logic;
signal clock_3m_s : std_logic; attribute clock_signal of clock_3m_s : signal is "yes";
signal turbo_on_s : std_logic;
signal clock_8m_s : std_logic; attribute clock_signal of clock_8m_s : signal is "yes";
-- RAM
signal ram_addr_s : std_logic_vector(22 downto 0); -- 8MB
signal ram_data_from_s : std_logic_vector( 7 downto 0);
signal ram_data_to_s : std_logic_vector( 7 downto 0);
signal ram_ce_s : std_logic;
signal ram_oe_s : std_logic;
signal ram_we_s : std_logic;
-- VRAM memory
signal vram_addr_s : std_logic_vector(13 downto 0); -- 16K
signal vram_do_s : std_logic_vector( 7 downto 0);
signal vram_di_s : std_logic_vector( 7 downto 0);
-- signal vram_ce_s : std_logic;
-- signal vram_oe_s : std_logic;
signal vram_we_s : std_logic;
-- Audio
signal audio_scc_s : signed(14 downto 0);
signal audio_psg_s : unsigned( 7 downto 0);
signal beep_s : std_logic;
signal tapein_s : std_logic_vector( 7 downto 0);
signal ear_s : std_logic;
signal audio_l_s : signed(15 downto 0);
signal audio_r_s : signed(15 downto 0);
signal volumes_s : volumes_t;
-- Video
signal rgb_r_s : std_logic_vector( 3 downto 0);
signal rgb_g_s : std_logic_vector( 3 downto 0);
signal rgb_b_s : std_logic_vector( 3 downto 0);
signal rgb_hsync_n_s : std_logic;
signal rgb_vsync_n_s : std_logic;
signal vga_en_s : std_logic;
signal ntsc_pal_s : std_logic;
-- Keyboard
signal rows_s : std_logic_vector( 3 downto 0);
signal cols_s : std_logic_vector( 7 downto 0);
signal caps_en_s : std_logic;
signal extra_keys_s : std_logic_vector( 3 downto 0);
signal keyb_valid_s : std_logic;
signal keyb_data_s : std_logic_vector( 7 downto 0);
signal keymap_addr_s : std_logic_vector( 8 downto 0);
signal keymap_data_s : std_logic_vector( 7 downto 0);
signal keymap_we_s : std_logic;
-- SPI
signal spi_mosi_s : std_logic;
signal spi_miso_s : std_logic;
signal spi_sclk_s : std_logic;
signal sdspi_cs_n_s : std_logic;
signal flspi_cs_n_s : std_logic;
-- SNES
signal but_a_s : std_logic;
signal but_b_s : std_logic;
signal but_x_s : std_logic;
signal but_y_s : std_logic;
signal but_start_s : std_logic;
signal but_sel_s : std_logic;
signal but_tl_s : std_logic;
signal but_tr_s : std_logic;
signal but_up_s : std_logic;
signal but_down_s : std_logic;
signal but_left_s : std_logic;
signal but_right_s : std_logic;
-- Bus
signal bus_addr_s : std_logic_vector(15 downto 0);
signal bus_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal bus_data_to_s : std_logic_vector( 7 downto 0);
signal bus_rd_n_s : std_logic;
signal bus_wr_n_s : std_logic;
signal bus_m1_n_s : std_logic;
signal bus_iorq_n_s : std_logic;
signal bus_mreq_n_s : std_logic;
signal bus_sltsl1_n_s : std_logic;
signal bus_sltsl2_n_s : std_logic;
signal bus_int_n_s : std_logic;
signal bus_wait_n_s : std_logic;
-- JT51
signal jt51_cs_n_s : std_logic := '1';
signal jt51_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal jt51_hd_s : std_logic := '0';
signal jt51_left_s : signed(15 downto 0) := (others => '0');
signal jt51_right_s : signed(15 downto 0) := (others => '0');
-- OPLL
signal opll_cs_n_s : std_logic := '1';
signal opll_mo_s : signed(12 downto 0) := (others => '0');
signal opll_ro_s : signed(12 downto 0) := (others => '0');
-- MIDI interface
signal midi_cs_n_s : std_logic := '1';
signal midi_data_from_s : std_logic_vector( 7 downto 0) := (others => '1');
signal midi_hd_s : std_logic := '0';
signal midi_int_n_s : std_logic := '1';
-- Serial interface
signal serial_cs_s : std_logic := '0';
signal serial_data_from_s: std_logic_vector( 7 downto 0) := (others => '1');
signal serial_hd_s : std_logic := '0';
begin
-- PLL
pll_1: entity work.pll1
port map (
CLK_IN1 => clock_48M_i,
CLK_OUT1 => clock_master_s, -- 21.429 MHz (6x NTSC)
CLK_OUT2 => clock_sdram_s, -- 85.716 MHz (4x master)
CLK_OUT3 => sdram_clock_o, -- 85.716 MHz -90°
CLK_OUT4 => clock_8m_s -- 8 MHz (for MIDI)
);
-- Clocks
clks: entity work.clocks
port map (
clock_i => clock_master_s, -- 21.429
por_i => por_clock_s,
turbo_on_i => turbo_on_s,
clock_vdp_o => clock_vdp_s,
clock_5m_en_o => open,
clock_cpu_o => clock_cpu_s,
clock_psg_en_o => clock_psg_en_s,
clock_3m_o => clock_3m_s -- 3571500
);
-- The MSX1
the_msx: entity work.msx
generic map (
hw_id_g => 4,
hw_txt_g => "WXEDAX Board",
hw_version_g => actual_version,
video_opt_g => 1, -- dblscan configurable
ramsize_g => 8192,
hw_hashwds_g => '1'
)
port map (
-- Clocks
clock_i => clock_master_s,
clock_vdp_i => clock_vdp_s,
clock_cpu_i => clock_cpu_s,
clock_psg_en_i => clock_psg_en_s,
-- Turbo
turbo_on_k_i => extra_keys_s(3), -- F11
turbo_on_o => turbo_on_s,
-- Resets
reset_i => reset_s,
por_i => por_s,
softreset_o => soft_reset_s_s,
reload_o => reload_s,
-- Options
opt_nextor_i => '1',
opt_mr_type_i => "00",
opt_vga_on_i => '1',
-- RAM
ram_addr_o => ram_addr_s,
ram_data_i => ram_data_from_s,
ram_data_o => ram_data_to_s,
ram_ce_o => ram_ce_s,
ram_we_o => ram_we_s,
ram_oe_o => ram_oe_s,
-- ROM
rom_addr_o => open,
rom_data_i => ram_data_from_s,
rom_ce_o => open,
rom_oe_o => open,
-- External bus
bus_addr_o => bus_addr_s,
bus_data_i => bus_data_from_s,
bus_data_o => bus_data_to_s,
bus_rd_n_o => bus_rd_n_s,
bus_wr_n_o => bus_wr_n_s,
bus_m1_n_o => bus_m1_n_s,
bus_iorq_n_o => bus_iorq_n_s,
bus_mreq_n_o => bus_mreq_n_s,
bus_sltsl1_n_o => bus_sltsl1_n_s,
bus_sltsl2_n_o => bus_sltsl2_n_s,
bus_wait_n_i => bus_wait_n_s,
bus_nmi_n_i => '1',
bus_int_n_i => bus_int_n_s,
-- VDP RAM
vram_addr_o => vram_addr_s,
vram_data_i => vram_do_s,
vram_data_o => vram_di_s,
vram_ce_o => open,--vram_ce_s,
vram_oe_o => open,--vram_oe_s,
vram_we_o => vram_we_s,
-- Keyboard
rows_o => rows_s,
cols_i => cols_s,
caps_en_o => caps_en_s,
keyb_valid_i => keyb_valid_s,
keyb_data_i => keyb_data_s,
keymap_addr_o => keymap_addr_s,
keymap_data_o => keymap_data_s,
keymap_we_o => keymap_we_s,
-- Audio
audio_scc_o => audio_scc_s,
audio_psg_o => audio_psg_s,
beep_o => beep_s,
volumes_o => volumes_s,
-- K7
k7_motor_o => open,
k7_audio_o => open,
k7_audio_i => ear_s,
-- Joystick
joy1_up_i => but_up_s,
joy1_down_i => but_down_s,
joy1_left_i => but_left_s,
joy1_right_i => but_right_s,
joy1_btn1_i => but_b_s,
joy1_btn1_o => open,
joy1_btn2_i => but_a_s,
joy1_btn2_o => open,
joy1_out_o => open,
joy2_up_i => '1',
joy2_down_i => '1',
joy2_left_i => '1',
joy2_right_i => '1',
joy2_btn1_i => '1',
joy2_btn1_o => open,
joy2_btn2_i => '1',
joy2_btn2_o => open,
joy2_out_o => open,
-- Video
rgb_r_o => rgb_r_s,
rgb_g_o => rgb_g_s,
rgb_b_o => rgb_b_s,
hsync_n_o => rgb_hsync_n_s,
vsync_n_o => rgb_vsync_n_s,
ntsc_pal_o => ntsc_pal_s,
vga_on_k_i => extra_keys_s(2), -- Print Screen
scanline_on_k_i=> extra_keys_s(1), -- Scroll Lock
vertfreq_on_k_i=> extra_keys_s(0), -- Pause
vga_en_o => vga_en_s,
-- SPI/SD
flspi_cs_n_o => flspi_cs_n_s,
spi_cs_n_o => sdspi_cs_n_s,
spi_sclk_o => spi_sclk_s,
spi_mosi_o => spi_mosi_s,
spi_miso_i => spi_miso_s,
sd_pres_n_i => sd_pres_n_i,
sd_wp_i => sd_wp_i,
-- DEBUG
D_wait_o => open,
D_slots_o => open,
D_ipl_en_o => open
);
-- RAM
ram: entity work.ssdram
generic map (
freq_g => 85
)
port map (
clock_i => clock_sdram_s,
reset_i => reset_s,
refresh_i => '1',
-- Static RAM bus
addr_i => ram_addr_s,
data_i => ram_data_to_s,
data_o => ram_data_from_s,
cs_i => ram_ce_s,
oe_i => ram_oe_s,
we_i => ram_we_s,
-- SD-RAM ports
mem_cke_o => sdram_cke_o,
mem_cs_n_o => sdram_cs_n_o,
mem_ras_n_o => sdram_ras_n_o,
mem_cas_n_o => sdram_cas_n_o,
mem_we_n_o => sdram_we_n_o,
mem_udq_o => sdram_dqmh_o,
mem_ldq_o => sdram_dqml_o,
mem_ba_o => sdram_ba_o,
mem_addr_o => sdram_addr_o,
mem_data_io => sdram_dq_io
);
-- VRAM
vram: entity work.spram
generic map (
addr_width_g => 14,
data_width_g => 8
)
port map (
clk_i => clock_master_s,
we_i => vram_we_s,
addr_i => vram_addr_s,
data_i => vram_di_s,
data_o => vram_do_s
);
-- Keyboard PS/2
keyb: entity work.keyboard
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
-- MSX
rows_coded_i => rows_s,
cols_o => cols_s,
keymap_addr_i => keymap_addr_s,
keymap_data_i => keymap_data_s,
keymap_we_i => keymap_we_s,
-- LEDs
led_caps_i => caps_en_s,
-- PS/2 interface
ps2_clk_io => ps2_clk_io,
ps2_data_io => ps2_dat_io,
-- Direct Access
keyb_valid_o => keyb_valid_s,
keyb_data_o => keyb_data_s,
--
reset_o => soft_reset_k_s,
por_o => soft_por_s,
reload_core_o => open,
extra_keys_o => extra_keys_s
);
-- Audio
mixer: entity work.mixers
port map (
clock_i => clock_master_s,
reset_i => reset_s,
volumes_i => volumes_s,
ear_i => ear_s,
beep_i => beep_s,
audio_scc_i => audio_scc_s,
audio_psg_i => audio_psg_s,
jt51_left_i => jt51_left_s,
jt51_right_i => jt51_right_s,
opll_mo_i => opll_mo_s,
opll_ro_i => opll_ro_s,
audio_mix_l_o => audio_l_s,
audio_mix_r_o => audio_r_s
);
ui2s: if use_i2s_g generate
-- I2S out
i2s : entity work.i2s_transmitter
generic map (
mclk_rate => 10714500, -- unusual values
sample_rate => 167414,
preamble => 0,
word_length => 16
)
port map (
clock_i => clock_master_s, -- 21.477 MHz (2xMCLK)
reset_i => reset_s,
-- Parallel input
pcm_l_i => std_logic_vector(audio_l_s),
pcm_r_i => std_logic_vector(audio_r_s),
i2s_mclk_o => i2s_mclk_o,
i2s_lrclk_o => i2s_lrclk_o,
i2s_bclk_o => i2s_bclk_o,
i2s_d_o => i2s_data_o
);
end generate;
nui2s: if not use_i2s_g generate
-- Left Channel
audiol : entity work.dac_dsm2v
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_master_s,
dac_i => audio_l_s,
dac_o => i2s_lrclk_o
);
-- Right Channel
audior : entity work.dac_dsm2v
generic map (
nbits_g => 16
)
port map (
reset_i => reset_s,
clock_i => clock_master_s,
dac_i => audio_r_s,
dac_o => i2s_bclk_o
);
end generate;
-- Tape In
tapein: entity work.tlc549
generic map (
frequency_g => 21,
sample_cycles_g => 28
)
port map (
clock_i => clock_master_s,
reset_i => reset_s,
clock_o => open,
data_o => tapein_s,
adc_data_i => adc_data_i,
adc_cs_n_o => adc_cs_n_o,
adc_clk_o => adc_clock_o
);
-- Multiboot
mb: entity work.multiboot
generic map (
bit_g => 2
)
port map (
reset_i => por_s,
clock_i => clock_vdp_s,
start_i => reload_s,
spi_addr_i => X"000000"
);
-----------------------------------------------------------------------------
-- SNES Gamepads
-----------------------------------------------------------------------------
snespads_b : entity work.snespad
generic map (
num_pads_g => 1,
reset_level_g => 1,
button_level_g => 0,
clocks_per_6us_g => 128 -- 6us = 128 ciclos de 21.477MHz
)
port map (
clk_i => clock_master_s,
reset_i => reset_s,
pad_clk_o => pad_clk_o,
pad_latch_o => pad_latch_o,
pad_data_i(0) => pad_data_i,
but_a_o(0) => but_a_s,
but_b_o(0) => but_b_s,
but_x_o(0) => but_x_s,
but_y_o(0) => but_y_s,
but_start_o(0) => but_start_s,
but_sel_o(0) => but_sel_s,
but_tl_o(0) => but_tl_s,
but_tr_o(0) => but_tr_s,
but_up_o(0) => but_up_s,
but_down_o(0) => but_down_s,
but_left_o(0) => but_left_s,
but_right_o(0) => but_right_s
);
-- Glue logic
-- Power-on counter
process (clock_master_s)
begin
if rising_edge(clock_master_s) then
if por_cnt_s /= 0 then
por_cnt_s <= por_cnt_s - 1;
end if;
end if;
end process;
por_clock_s <= '1' when por_cnt_s /= 0 else '0';
por_s <= '1' when por_cnt_s /= 0 or soft_por_s = '1' or keys_n_i(4) = '0' else '0';
reset_s <= '1' when soft_rst_cnt_s = X"00" or por_s = '1' or keys_n_i(1) = '0' else '0';
reset_n_s <= not reset_s;
process(clock_master_s)
begin
if rising_edge(clock_master_s) then
if reset_s = '1' or por_s = '1' then
soft_rst_cnt_s <= X"FF";
elsif (soft_reset_k_s = '1' or soft_reset_s_s = '1') and soft_rst_cnt_s /= X"00" then
soft_rst_cnt_s <= soft_rst_cnt_s - 1;
end if;
end if;
end process;
-- Audio
buzzer_o <= beep_s;
-- Tape In (via ADC)
process (clock_master_s)
constant HYST_C : integer := 20;
constant LEVEL_C : integer := 128;
variable tapein_v : std_logic_vector(8 downto 0);
begin
if rising_edge(clock_master_s) then
tapein_v := '0' & tapein_s;
if tapein_v < (LEVEL_C - HYST_C) then
ear_s <= '0';
elsif tapein_v > (LEVEL_C + HYST_C) then
ear_s <= '1';
end if;
end if;
end process;
-- VGA Output
vga_r_o <= rgb_r_s & '0';
vga_g_o <= rgb_g_s & "00";
vga_b_o <= rgb_b_s & '0';
vga_hs_o <= rgb_hsync_n_s;
vga_vs_o <= rgb_vsync_n_s;
-- SD and Flash
spi_miso_s <= sd_miso_i when sdspi_cs_n_s = '0' else flashf_data_i;
sd_mosi_o <= spi_mosi_s;
sd_sclk_o <= spi_sclk_s;
sd_cs_n_o <= sdspi_cs_n_s;
flashf_data_o <= spi_mosi_s;
flashf_clk_o <= spi_sclk_s;
flashf_cs_n_o <= flspi_cs_n_s;
-- Peripheral BUS control
bus_data_from_s <= jt51_data_from_s when jt51_hd_s = '1' else
midi_data_from_s when midi_hd_s = '1' else
serial_data_from_s when serial_hd_s = '1' else
(others => '1');
bus_wait_n_s <= '1';
bus_int_n_s <= midi_int_n_s;
ptjt: if per_jt51_g generate
-- JT51 tests
jt51_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0010000" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x20 - 0x21
jt51: entity work.jt51_wrapper
port map (
clock_i => clock_3m_s,
reset_i => reset_s,
addr_i => bus_addr_s(0),
cs_n_i => jt51_cs_n_s,
wr_n_i => bus_wr_n_s,
rd_n_i => bus_rd_n_s,
data_i => bus_data_to_s,
data_o => jt51_data_from_s,
has_data_o => jt51_hd_s,
ct1_o => open,
ct2_o => open,
irq_n_o => open,
p1_o => open,
-- Low resolution output (same as real chip)
sample_o => open,
left_o => open,
right_o => open,
-- Full resolution output
xleft_o => jt51_left_s,
xright_o => jt51_right_s,
-- unsigned outputs for sigma delta converters, full resolution
dacleft_o => open,
dacright_o => open
);
end generate;
popll: if per_opll_g generate
-- OPLL tests
opll_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0111110" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x7C - 0x7D
opll1 : entity work.opll
port map (
clock_i => clock_master_s,
clock_en_i => clock_psg_en_s,
reset_i => reset_s,
data_i => bus_data_to_s,
addr_i => bus_addr_s(0),
cs_n => opll_cs_n_s,
we_n => bus_wr_n_s,
melody_o => opll_mo_s,
rythm_o => opll_ro_s
);
end generate;
-- MIDI3
midi_cs_n_s <= '0' when bus_addr_s(7 downto 1) = "0111111" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '1'; -- 0x7E - 0x7F
-- MIDI interface
midi: entity work.midiIntf
port map (
clock_i => clock_8m_s,
reset_i => reset_s,
addr_i => bus_addr_s(0),
cs_n_i => midi_cs_n_s,
wr_n_i => bus_wr_n_s,
rd_n_i => bus_rd_n_s,
data_i => bus_data_to_s,
data_o => midi_data_from_s,
has_data_o => midi_hd_s,
-- Outs
int_n_o => midi_int_n_s,
wait_n_o => open,
tx_o => open
);
-- Tests UART
serial_cs_s <= '1' when bus_addr_s(7 downto 3) = "11001" and bus_iorq_n_s = '0' and bus_m1_n_s = '1' else '0'; -- 0xC8 - 0xCF
serial: entity work.uart
port map (
clock_i => clock_master_s, -- 21.429 MHz
reset_i => reset_s,
addr_i => bus_addr_s(2 downto 0),
data_i => bus_data_to_s,
data_o => serial_data_from_s,
has_data_o => serial_hd_s,
cs_i => serial_cs_s,
rd_i => not bus_rd_n_s,
wr_i => not bus_wr_n_s,
int_n_o => leds_n_o(1),
--
rxd_i => uart_rx_i,
txd_o => uart_tx_o,
cts_n_i => gpio_io(0),
rts_n_o => gpio_io(1),
dsr_n_i => '0',
dtr_n_o => open,
dcd_i => '0',
ri_i => '0'
);
-- DEBUG
leds_n_o(0) <= sdspi_cs_n_s;
-- leds_n_o(1) <= '1';
leds_n_o(2) <= '1';--not vga_en_s;
leds_n_o(3) <= '1';--not turbo_on_s;
end architecture;
|
gpl-3.0
|
1a98838590b5138f6f66d764ff0482e0
| 0.548233 | 2.2951 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/testbench/wishbone/system_test/dbe_bpm_simple_top.vhd
| 1 | 26,640 |
-- Simple DBE simple design
-- Created by Lucas Russo <[email protected]>
-- Date: 11/10/2012
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Memory core generator
use work.gencores_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone stream modules and interface
use work.wb_stream_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_simple_top is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
--clk100_i : in std_logic;
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Reset Button
-----------------------------------------
sys_rst_button_i : in std_logic;
-----------------------------------------
-- FMC150 pins
-----------------------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-----------------------------------------
-- UART pins
-----------------------------------------
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_simple_top;
architecture rtl of dbe_bpm_simple_top is
-- Top crossbar layout
-- Number of slaves
constant c_slaves : natural := 7; -- LED, Button, Dual-port memory, UART, DMA control port, FMC150
-- Number of masters
constant c_masters : natural := 4; -- LM32 master. Data + Instruction, DMA read+write master
constant c_dpram_size : natural := 16384; -- in 32-bit words (64KB)
-- Number of source/sink Wishbone stream components
constant c_sinks : natural := 1;
constant c_sources : natural := c_sinks;
-- GPIO num pins
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^27 clock cycles
--constant c_counter_width : natural := 27;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 64KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(c_xwb_dma_sdb, x"20000400"), -- DMA control port
3 => f_sdb_embed_device(c_xwb_fmc150_sdb, x"20000500"), -- FMC control port
4 => f_sdb_embed_device(c_xwb_uart_sdb, x"20000600"), -- UART control port
5 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000700"), -- GPIO LED
6 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000800") -- GPIO Button
--7 => f_sdb_embed_device(c_xwb_irqmngr_sdb, x"20000900") -- IRQ_MNGR
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"20000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- Wishbone Stream source/sinks arrays
signal wbs_src_i : t_wbs_source_in_array(c_sources-1 downto 0);
signal wbs_src_o : t_wbs_source_out_array(c_sources-1 downto 0);
-- Check the use of this kind of alias
alias wbs_sink_i is wbs_src_o;
alias wbs_sink_o is wbs_src_i;
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Clocks and resets signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- 200 Mhz clocck for iodelatctrl
signal clk_200mhz : std_logic;
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal s_leds : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- IRQ manager signals
--signal gpio_slave_irqmngr_o : t_wishbone_slave_out;
--signal gpio_slave_irqmngr_i : t_wishbone_slave_in;
-- LEDS, button and irq manager signals
--signal r_leds : std_logic_vector(7 downto 0);
--signal r_reset : std_logic;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- FMC150 signals
signal clk_adc : std_logic;
-- Chipscope control signals
signal CONTROL0 : std_logic_vector(35 downto 0);
signal CONTROL1 : std_logic_vector(35 downto 0);
-- Chipscope ILA 0 signals
signal TRIG_ILA0_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA0_3 : std_logic_vector(31 downto 0);
-- Chipscope ILA 1 signals
signal TRIG_ILA1_0 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_1 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_2 : std_logic_vector(31 downto 0);
signal TRIG_ILA1_3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon_1_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Controller 2 port
component chipscope_icon_2_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
-- Functions
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking!
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_200mhz, -- 200MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles have passed
cmp_reset : gc_reset
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0);
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn and not sys_rst_button_i;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupts 31 downto 1 disabled for now.
-- Interrupt '0' is DMA completion.
lm32_interrupt(31 downto 1) <= (others => '0');
-- A DMA controller is master 2+3, slave 2, and interrupt 0
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => lm32_interrupt(0)
);
-- Slave 0+1 is the RAM. Load a input file containing a simple led blink program!
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
--slave2_i => cc_dummy_slave_in, -- CYC always low
--slave2_o => open
);
-- Slave 3 is the FMC150 interface
cmp_xwb_fmc150 : xwb_fmc150
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
--g_packet_size => 32,
--g_sim => 0
)
port map(
rst_n_i => clk_sys_rstn,
clk_sys_i => clk_sys,
--clk_100Mhz_i : in std_logic;
clk_200Mhz_i => clk_200mhz,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => cbar_master_o(3),
wb_slv_o => cbar_master_i(3),
-----------------------------
-- Simulation Only ports!
-----------------------------
sim_adc_clk_i => '0',
sim_adc_clk2x_i => '0',
sim_adc_cha_data_i => f_zeros(14),
sim_adc_chb_data_i => f_zeros(14),
sim_adc_data_valid => '0',
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => adc_clk_ab_p_i,
adc_clk_ab_n_i => adc_clk_ab_n_i,
adc_cha_p_i => adc_cha_p_i,
adc_cha_n_i => adc_cha_n_i,
adc_chb_p_i => adc_chb_p_i,
adc_chb_n_i => adc_chb_n_i,
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o => dac_dclk_p_o,
dac_dclk_n_o => dac_dclk_n_o,
dac_data_p_o => dac_data_p_o,
dac_data_n_o => dac_data_n_o,
dac_frame_p_o => dac_frame_p_o,
dac_frame_n_o => dac_frame_n_o,
txenable_o => txenable_o,
--Clock/Trigger connection to FMC150
--clk_to_fpga_p_i : in std_logic;
--clk_to_fpga_n_i : in std_logic;
--ext_trigger_p_i : in std_logic;
--ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o => spi_sclk_o, -- Shared SPI clock line
spi_sdata_o => spi_sdata_o,-- Shared SPI data line
-- ADC specific signals
adc_n_en_o => adc_n_en_o, -- SPI chip select
adc_sdo_i => adc_sdo_i, -- SPI data out
adc_reset_o => adc_reset_o,-- SPI reset
-- CDCE specific signals
cdce_n_en_o => cdce_n_en_o, -- SPI chip select
cdce_sdo_i => cdce_sdo_i, -- SPI data out
cdce_n_reset_o => cdce_n_reset_o,
cdce_n_pd_o => cdce_n_pd_o,
cdce_ref_en_o => cdce_ref_en_o,
cdce_pll_status_i => cdce_pll_status_i,
-- DAC specific signals
dac_n_en_o => dac_n_en_o, -- SPI chip select
dac_sdo_i => dac_sdo_i, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => mon_n_en_o, -- SPI chip select
mon_sdo_i => mon_sdo_i, -- SPI data out
mon_n_reset_o => mon_n_reset_o,
mon_n_int_i => mon_n_int_i,
--FMC Present status
prsnt_m2c_l_i => prsnt_m2c_l_i,
-- ADC output signals
-- ADC data is interfaced through the wishbone stream interface (wbs_src_o)
adc_dout_o => open,
clk_adc_o => clk_adc,
-- Wishbone Streaming Interface Source
wbs_source_i => wbs_src_i(0),
wbs_source_o => wbs_src_o(0)
);
-- Slave 4 is the UART
cmp_uart : xwb_simple_uart
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE
)
port map (
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(4),
slave_o => cbar_master_i(4),
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o
);
-- Slave 5 is the example LED driver
cmp_leds : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_leds_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(5),
slave_o => cbar_master_i(5),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => s_leds,
--gpio_out_o => open,
gpio_in_i => s_leds,
gpio_oen_o => open
);
--leds_o <= x"55";
leds_o <= s_leds;
--p_test_leds : process (clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- if clk_sys_rstn = '0' then
-- s_counter <= (others => '0');
-- s_leds <= x"55";
-- else
-- if (s_counter = s_counter_full-1) then
-- s_counter <= (others => '0');
-- s_leds <= s_leds(c_leds_num_pins-2 downto 0) & s_leds(c_leds_num_pins-1);
-- else
-- s_counter <= s_counter + 1;
-- end if;
-- end if;
-- end if;
--end process;
-- Slave 1 is the example LED driver
--gpio_slave_led_i <= cbar_master_o(1);
--cbar_master_i(1) <= gpio_slave_led_o;
--leds_o <= not r_leds;
-- There is a tool called 'wbgen2' which can autogenerate a Wishbone
-- interface and C header file, but this is a simple example.
--gpio : process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- It is vitally important that for each occurance of
-- (cyc and stb and not stall) there is (ack or rty or err)
-- sometime later on the bus.
--
-- This is an easy solution for a device that never stalls:
-- gpio_slave_led_o.ack <= gpio_slave_led_i.cyc and gpio_slave_led_i.stb;
-- Detect a write to the register byte
-- if gpio_slave_led_i.cyc = '1' and gpio_slave_led_i.stb = '1' and
-- gpio_slave_led_i.we = '1' and gpio_slave_led_i.sel(0) = '1' then
-- Register 0x0 = LEDs, 0x4 = CPU reset
-- if gpio_slave_led_i.adr(2) = '0' then
-- r_leds <= gpio_slave_led_i.dat(7 downto 0);
-- else
-- r_reset <= gpio_slave_led_i.dat(0);
-- end if;
-- end if;
-- Read to the register byte
-- if gpio_slave_led_i.adr(2) = '0' then
-- gpio_slave_led_o.dat(31 downto 8) <= (others => '0');
-- gpio_slave_led_o.dat(7 downto 0) <= r_leds;
-- else
-- gpio_slave_led_o.dat(31 downto 2) <= (others => '0');
-- gpio_slave_led_o.dat(0) <= r_reset;
-- end if;
--end if;
--end process;
--gpio_slave_led_o.int <= '0';
--gpio_slave_led_o.err <= '0';
--gpio_slave_led_o.rty <= '0';
--gpio_slave_led_o.stall <= '0'; -- This simple example is always ready
-- Slave 6 is the example Button driver
cmp_buttons : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_buttons_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(6),
slave_o => cbar_master_i(6),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => open,
gpio_in_i => buttons_i,
gpio_oen_o => open
);
-- Xilinx Chipscope
cmp_chipscope_icon_0 : chipscope_icon_2_port
port map (
CONTROL0 => CONTROL0,
CONTROL1 => CONTROL1
);
cmp_chipscope_ila_0 : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys,
TRIG0 => TRIG_ILA0_0,
TRIG1 => TRIG_ILA0_1,
TRIG2 => TRIG_ILA0_2,
TRIG3 => TRIG_ILA0_3
);
-- FMC150 master output (slave input) control data
TRIG_ILA0_0 <= cbar_master_o(3).dat;
-- FMC150 master input (slave output) control data
TRIG_ILA0_1 <= cbar_master_i(3).dat;
-- FMC150 master control output (slave input) control signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA0_2(10 downto 0) <= cbar_master_o(3).cyc &
cbar_master_o(3).stb &
cbar_master_o(3).adr(3 downto 0) &
cbar_master_o(3).sel &
cbar_master_o(3).we;
TRIG_ILA0_2(31 downto 11) <= (others => '0');
-- FMC150 master control input (slave output) control signals
TRIG_ILA0_3(4 downto 0) <= cbar_master_i(3).ack &
cbar_master_i(3).err &
cbar_master_i(3).rty &
cbar_master_i(3).stall &
cbar_master_i(3).int;
TRIG_ILA0_3(31 downto 5) <= (others => '0');
cmp_chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL1,
CLK => clk_adc,
TRIG0 => TRIG_ILA1_0,
TRIG1 => TRIG_ILA1_1,
TRIG2 => TRIG_ILA1_2,
TRIG3 => TRIG_ILA1_3
);
-- FMC150 source output (sink input) stream data
TRIG_ILA1_0 <= wbs_src_o(0).dat;
-- FMC150 source input (sink output) stream data
--TRIG_ILA1_1 <= wbs_src_i(0).dat;
-- FMC150 source control output (sink input) stream signals
-- Partial decoding. Thus, only the LSB part of address matters to
-- a specific slave core
TRIG_ILA1_1(10 downto 0) <= wbs_src_o(0).cyc &
wbs_src_o(0).stb &
wbs_src_o(0).adr(3 downto 0) &
wbs_src_o(0).sel &
wbs_src_o(0).we;
TRIG_ILA1_1(31 downto 11) <= (others => '0');
-- FMC150 master control input (slave output) stream signals
TRIG_ILA1_2(3 downto 0) <= wbs_src_i(0).ack &
wbs_src_i(0).err &
wbs_src_i(0).rty &
wbs_src_i(0).stall;
TRIG_ILA1_2(31 downto 4) <= (others => '0');
end rtl;
|
lgpl-3.0
|
f19573dbf25e4e3daef8888445265487
| 0.463739 | 3.56388 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd
| 1 | 10,963 |
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
-- Modified by Lucas Russo <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity xwb_stream_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_i : in std_logic
);
end xwb_stream_sink;
architecture rtl of xwb_stream_sink is
-- FIFO ranges
constant c_data_lsb : natural := 0;
constant c_data_msb : natural := c_data_lsb + c_wbs_data_width - 1;
constant c_addr_lsb : natural := c_data_msb + 1;
constant c_addr_msb : natural := c_addr_lsb + c_wbs_address_width -1;
constant c_valid_bit : natural := c_addr_msb + 1;
constant c_sel_lsb : natural := c_valid_bit + 1;
constant c_sel_msb : natural := c_sel_lsb + (c_wbs_data_width/8) - 1;
constant c_eof_bit : natural := c_sel_msb + 1;
constant c_sof_bit : natural := c_eof_bit + 1;
alias c_logic_lsb is c_valid_bit;
alias c_logic_msb is c_sof_bit;
constant c_logic_width : integer := c_sof_bit - c_valid_bit + 1;
constant c_fifo_width : integer := c_sof_bit - c_data_lsb + 1;
constant c_fifo_depth : integer := 32;
constant c_logic_zeros : std_logic_vector(c_logic_msb downto c_logic_lsb)
:= std_logic_vector(to_unsigned(0, c_logic_width));
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_eof, pre_dvalid : std_logic;
signal pre_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal post_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal post_eof : std_logic;
signal post_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal snk_out : t_wbs_sink_out;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_i.cyc;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_i.cyc and not cyc_d0; -- sof
pre_eof <= not snk_i.cyc and cyc_d0; -- eof
--pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_bytesel <= snk_i.sel; -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(c_data_msb downto c_data_lsb) <= snk_i.dat;
fin(c_addr_msb downto c_addr_lsb) <= snk_i.adr;
fin(c_logic_msb downto c_logic_lsb) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
end if;
end if;
end process;
snk_o <= snk_out;
-- FIX. Review the comparison fin(c_logic_msb downto c_logic_lsb) /= c_logic_zeros
we <= '1' when fin(c_logic_msb downto c_logic_lsb) /= c_logic_zeros
and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid
);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
-- Output fifo registers only when valid
--p_post_regs : process(fout_reg, q_valid)
--begin
-- if q_valid = '1' then
-- post_data <= fout_reg(c_data_msb downto c_data_lsb);
-- post_addr <= fout_reg(c_addr_msb downto c_addr_lsb);
-- post_sof <= fout_reg(c_sof_bit); --and rd_d0; --and q_valid;
-- post_dvalid <= fout_reg(c_valid_bit);
-- post_eof <= fout_reg(c_eof_bit);-- and rd_d0;
-- post_bytesel <= fout_reg(c_sel_msb downto c_sel_lsb);
-- else
-- post_data <= (others => '0');
-- post_addr <= (others => '0');
-- post_sof <= '0';
-- post_dvalid <= '0';
-- post_eof <= '0';
-- post_bytesel <= (others => '0');
-- end if;
--end process;
post_sof <= fout_reg(c_sof_bit) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(c_valid_bit);
post_eof <= fout_reg(c_eof_bit);
post_bytesel <= fout_reg(c_sel_msb downto c_sel_lsb);
post_data <= fout_reg(c_data_msb downto c_data_lsb);
post_addr <= fout_reg(c_addr_msb downto c_addr_lsb);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = std_logic_vector(c_WBS_STATUS)) and (f_unmarshall_wbs_status(post_data).error = '1') else '0';
eof_o <= post_eof and rd_d0;
bytesel_o <= post_bytesel;
data_o <= post_data;
addr_o <= post_addr;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity wb_stream_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_dat_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
snk_adr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
snk_sel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_stream_sink;
architecture wrapper of wb_stream_sink is
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
signal snk_in : t_wbs_sink_in;
signal snk_out : t_wbs_sink_out;
begin -- wrapper
cmp_stream_sink_wrapper : xwb_stream_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
addr_o => addr_o,
data_o => data_o,
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
bytesel_o => bytesel_o,
dreq_i => dreq_i);
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.cyc <= snk_cyc_i;
snk_in.sel <= snk_sel_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
|
lgpl-3.0
|
f34ad114058c4e2dd684fcb5b98c453d
| 0.507799 | 3.266687 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/lowpass.vhd
| 2 | 11,517 |
--##############################################################################
--
-- lowpass
-- generic all-pole lowpass filter
--
-- This circuit simulates an analog ladder filter by replacing the integral
-- relations of the LC elements by digital accumulators.
--
--------------------------------------------------------------------------------
--
-- Versions / Authors
-- 1.1 Francois Corthay added additional w(0) AND w(filterOrder+1)
-- 1.0 Romain Cheviron first implementation
--
-- Provided under GNU LGPL licence: <http://www.gnu.org/copyleft/lesser.html>
--
-- by the electronics group of "HES-SO//Valais Wallis", in Switzerland:
-- <http://isi.hevs.ch/switzerland/robust-electronics.html>.
--
--------------------------------------------------------------------------------
--
-- Usage
-- Set the input signal bit number with the generic "inputBitNb".
--
-- Set the output signal bit number with the generic "outputBitNb". This
-- value must be greater or equal than "inputBitNb". The additional bits
-- are added as LSBs. They allow to increas the resolution as the bandwidth
-- is reduced.
--
-- Define the cutoff frequency with the generic "shiftBitNb". Every
-- increment in this value shifts the cutoff frequency down by an octave
-- (a factor of 2).
--
-- In order to define the filter function, the first lines of the
-- architecture have to be edited:
-- constant "filterOrder" obviously gives the filter order.
-- constant "coefficientBitNb" obviously gives the number of bits of
-- the coefficients.
-- constant "coefficient" give the time constants as unsigned numbers
-- ranging from 1 to (2**coefficientBitNb)-1. The relative values
-- of the coefficients give the shape of the transfer function.
-- The cutoff frequency is furthermore given by the "shiftBitNb"
-- generic.
-- constant "additionalInternalWBitNb" gives the number of additional
-- bits assigned to the internal signals corresponding to the state
-- variables of the analog filter. They are used to avoid overflows
-- on these signals.
-- The values for "shiftBitNb" and "constant additionalInternalWBitNb" can
-- be dertermined analytically, but a frequency sweep simulation allows to
-- set them iteratively.
--
-- The input samples are read from the signal "filterIn" at the rising edge
-- of "clock" when "en" is '1'.
--
-- With this, a new output sample is calculated and provided on
-- "filterOut". The output changes at the end of the iterative calculation
-- of the multiplication, which is roughly n clock periods after "en"
-- was '1'. The number of clock periods, n, is equal to the number of bits
-- of the coefficients. The output sample remains stable until the next
-- sample has been calculated.
--
-- The "reset" signal is active high.
--
--------------------------------------------------------------------------------
--
-- Synthesis results
--
-- A 3rd order filter with 16 bit input, 16 bit output and 4 bit shift
-- gives the following synthesis result on a Xilinx Spartan3-1000:
-- Number of Slice Flip Flops: 162 out of 15,360 1%
-- Number of 4 input LUTs: 282 out of 15,360 1%
-- Average Fanout of Non-Clock Nets: 2.73
--
-- A 6th order filter with 16 bit input, 16 bit output and 4 bit shift
-- gives the following synthesis result on a Xilinx Spartan3-1000:
-- Number of Slice Flip Flops: 333 out of 15,360 2%
-- Number of 4 input LUTs: 604 out of 15,360 3%
-- Average Fanout of Non-Clock Nets: 2.81
--
--##############################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY lowpass IS
GENERIC(
inputBitNb : positive := 16;
outputBitNb : positive := 16;
shiftBitNb : positive := 4
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
en : IN std_ulogic;
filterIn : IN signed (inputBitNb-1 DOWNTO 0);
filterOut : OUT signed (outputBitNb-1 DOWNTO 0)
);
END lowpass ;
--==============================================================================
ARCHITECTURE RTL OF lowpass IS
-- 3rd order Butterworth
--
-- constant filterOrder : natural := 3;
-- constant coefficientBitNb : natural := 8;
-- type unsigned_vector_c is array(1 to filterOrder)
-- of unsigned(coefficientBitNb-1 downto 0);
-- constant coefficient : unsigned_vector_c := (
-- to_unsigned(2**7, coefficientBitNb),
-- to_unsigned(2**6, coefficientBitNb),
-- to_unsigned(2**7, coefficientBitNb)
-- );
-- constant additionalInternalWBitNb: positive := 2;
-- 6th order Bessel
--
constant filterOrder : natural := 6;
constant coefficientBitNb : natural := 8;
type unsigned_vector_c is array(1 to filterOrder)
of unsigned(coefficientBitNb-1 downto 0);
constant coefficient : unsigned_vector_c := (
to_unsigned(215, coefficientBitNb),
to_unsigned( 88, coefficientBitNb),
to_unsigned( 81, coefficientBitNb),
to_unsigned( 61, coefficientBitNb),
to_unsigned( 38, coefficientBitNb),
to_unsigned( 13, coefficientBitNb)
);
constant additionalInternalWBitNb: positive := 4;
constant internalWBitNb: positive := filterOut'length + additionalInternalWBitNb;
signal inputSignalScaled : signed(internalWBitNb-1 downto 0);
constant internalAccumulatorBitNb : positive := internalWBitNb + shiftBitNb;
type signed_vector_accumulator is array(1 to filterOrder)
of signed(internalAccumulatorBitNb-1 downto 0);
type signed_vector_w is array(0 to filterOrder+1)
of signed(internalWBitNb-1 downto 0);
signal accumulator : signed_vector_accumulator;
signal w : signed_vector_w;
type unsigned_vector_coeffShiftReg is array(1 to filterOrder)
of unsigned(coefficientBitNb-1 downto 0);
signal coefficientShiftRegister: unsigned_vector_coeffShiftReg;
signal multiplicandBit: std_ulogic_vector(1 to filterOrder);
type signed_vector_multAcc is array(1 to filterOrder)
of signed(internalAccumulatorBitNb+coefficientBitNb-1 downto 0);
signal multiplicationAccumulator: signed_vector_multAcc;
signal cycleCounterShiftReg: unsigned(coefficientBitNb downto 0);
signal endOfCycle: std_ulogic;
signal calculating: std_ulogic;
signal wDebug : signed_vector_w;
BEGIN
------------------------------------------------------------------------------
-- Scale input signal to internal state variables size
inputSignalScaled <= SHIFT_LEFT(
RESIZE(filterIn, inputSignalScaled'length),
filterOut'length - filterIn'length
);
------------------------------------------------------------------------------
-- Accumulator chain
process(reset, clock)
begin
if reset = '1' then
accumulator <= (others => (others => '0'));
elsif rising_edge(clock) then
if en = '1' then
for index in 1 to filterOrder loop
accumulator(index) <= accumulator(index) + (
RESIZE(w(index-1), w(index)'length+1) -
RESIZE(w(index+1), w(index)'length+1)
);
end loop;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Multiplication sequence
-- Coefficient shift
process(reset, clock)
begin
if reset = '1' then
coefficientShiftregister <= (others => (others => '0'));
elsif rising_edge(clock) then
for index in 1 to filterOrder loop
if en = '1' then
coefficientShiftregister(index) <= coefficient(index);
else
coefficientShiftregister(index) <=
shift_right(coefficientShiftregister(index), 1);
end if;
end loop;
end if;
end process;
process(coefficientShiftregister)
begin
for index in 1 to filterOrder loop
multiplicandBit(index) <= coefficientShiftregister(index)(0);
end loop;
end process;
-- Multiplication accumulator
process(reset, clock)
begin
if reset = '1' then
multiplicationAccumulator <= (others => (others => '0'));
elsif rising_edge(clock) then
for index in 1 to filterOrder loop
if en = '1' then
multiplicationAccumulator(index) <= (others => '0');
elsif calculating = '1' then
if multiplicandBit(index) = '0' then
multiplicationAccumulator(index) <=
shift_right(multiplicationAccumulator(index), 1);
else
multiplicationAccumulator(index) <=
shift_right(multiplicationAccumulator(index), 1) +
shift_left(
resize(accumulator(index), multiplicationAccumulator(index)'length),
coefficientBitNb
);
end if;
end if;
end loop;
end if;
end process;
------------------------------------------------------------------------------
-- Analog filter state variables
process(multiplicationAccumulator, w, inputSignalScaled)
begin
for index in 1 to filterOrder loop
w(index) <= RESIZE(
SHIFT_RIGHT(
multiplicationAccumulator(index),
coefficientBitNb + shiftBitNb
),
w(index)'length
);
end loop;
-- w(0) combines input and w(1) for first accumulator
w(0) <= inputSignalScaled - w(1);
-- w(filterOrder+1) is a copy of w(filterOrder) for last accumulator
w(filterOrder+1) <= w(filterOrder);
end process;
------------------------------------------------------------------------------
-- Scale last state variables to output size and latch
process(reset, clock)
begin
if reset = '1' then
filterOut <= (others => '0');
elsif rising_edge(clock) then
if calculating = '0' then
filterOut <= RESIZE(w(w'high), filterOut'length);
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Multiplication cycle counter
process(reset, clock)
begin
if reset = '1' then
cycleCounterShiftReg <= (others => '0');
elsif rising_edge(clock) then
cycleCounterShiftReg <= shift_right(cycleCounterShiftReg, 1);
cycleCounterShiftReg(cycleCounterShiftReg'high) <= en;
end if;
end process;
endOfCycle <= cycleCounterShiftReg(0);
calculating <= '1' when cycleCounterShiftReg /= 0
else '0';
------------------------------------------------------------------------------
-- Debug information
process(reset, clock)
begin
if reset = '1' then
wDebug <= (others => (others => '0'));
elsif rising_edge(clock) then
for index in 1 to filterOrder loop
if calculating = '0' then
wDebug <= w;
end if;
end loop;
end if;
end process;
END ARCHITECTURE RTL;
|
gpl-3.0
|
31ff309521a8fdf63a492f9050c2c6df
| 0.566988 | 4.704657 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ui/ui_top.vhd
| 1 | 20,825 |
--LIBRARY xtek;
-- USE xtek.XHDL_std_logic.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
--*****************************************************************************
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ui_top.v
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created : Tue Jun 30 2009
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
-- Top level of simple user interface.
ENTITY ui_top IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
APP_MASK_WIDTH : INTEGER := 32;
BANK_WIDTH : INTEGER := 3;
COL_WIDTH : INTEGER := 12;
CWL : INTEGER := 5;
ECC : STRING := "OFF";
ECC_TEST : STRING := "OFF";
ORDERING : STRING := "NORM";
RANKS : INTEGER := 4;
RANK_WIDTH : INTEGER := 2;
ROW_WIDTH : INTEGER := 16;
MEM_ADDR_ORDER : STRING := "BANK_ROW_COLUMN"
);
PORT (
-- Outputs
-- Inputs
-- Beginning of automatic inputs (from unused autoinst inputs)
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_cmd0 of ui_cmd.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_cmd0 of ui_cmd.v, ...
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_rd_data0 of ui_rd_data.v
-- To ui_cmd0 of ui_cmd.v, ...
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- To ui_wr_data0 of ui_wr_data.v
-- End of automatics
-- Beginning of automatic outputs (from unused autoinst outputs)
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_rd_data0 of ui_rd_data.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_wr_data0 of ui_wr_data.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_wr_data0 of ui_wr_data.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_cmd0 of ui_cmd.v
-- From ui_wr_data0 of ui_wr_data.v
wr_data_mask : OUT STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0); -- From ui_wr_data0 of ui_wr_data.v
wr_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
use_addr : OUT STD_LOGIC;
size : OUT STD_LOGIC;
row : OUT STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0);
raw_not_ecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rank : OUT STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0);
hi_priority : OUT STD_LOGIC;
data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
col : OUT STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0);
cmd : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
bank : OUT STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0);
app_wdf_rdy : OUT STD_LOGIC;
app_rdy : OUT STD_LOGIC;
app_rd_data_valid : OUT STD_LOGIC;
app_rd_data_end : OUT STD_LOGIC;
app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
correct_en : OUT STD_LOGIC;
wr_data_offset : IN STD_LOGIC;
wr_data_en : IN STD_LOGIC;
wr_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
rd_data_offset : IN STD_LOGIC;
rd_data_end : IN STD_LOGIC;
rd_data_en : IN STD_LOGIC;
rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk : IN STD_LOGIC;
app_wdf_wren : IN STD_LOGIC;
app_wdf_mask : IN STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
app_wdf_end : IN STD_LOGIC;
app_wdf_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_sz : IN STD_LOGIC;
app_raw_not_ecc : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
app_hi_pri : IN STD_LOGIC;
app_en : IN STD_LOGIC;
app_cmd : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
app_addr : IN STD_LOGIC_VECTOR(RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH - 1 DOWNTO 0);
accept_ns : IN STD_LOGIC;
accept : IN STD_LOGIC;
app_correct_en : IN STD_LOGIC
);
END ENTITY ui_top;
ARCHITECTURE trans OF ui_top IS
constant ADDR_WIDTH :integer := RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
COMPONENT ui_cmd IS
GENERIC (
TCQ : INTEGER := 100;
ADDR_WIDTH : INTEGER := 33;
BANK_WIDTH : INTEGER := 3;
COL_WIDTH : INTEGER := 12;
RANK_WIDTH : INTEGER := 2;
ROW_WIDTH : INTEGER := 16;
RANKS : INTEGER := 4;
MEM_ADDR_ORDER : STRING := "BANK_ROW_COLUMN"
);
PORT (
app_rdy : OUT STD_LOGIC;
use_addr : OUT STD_LOGIC;
rank : OUT STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0);
bank : OUT STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0);
row : OUT STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0);
col : OUT STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0);
size : OUT STD_LOGIC;
cmd : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hi_priority : OUT STD_LOGIC;
rd_accepted : OUT STD_LOGIC;
wr_accepted : OUT STD_LOGIC;
data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
accept_ns : IN STD_LOGIC;
rd_buf_full : IN STD_LOGIC;
wr_req_16 : IN STD_LOGIC;
app_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
app_cmd : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
app_sz : IN STD_LOGIC;
app_hi_pri : IN STD_LOGIC;
app_en : IN STD_LOGIC;
wr_data_buf_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_buf_addr_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT ui_wr_data IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
APP_MASK_WIDTH : INTEGER := 32;
ECC : STRING := "OFF";
ECC_TEST : STRING := "OFF";
CWL : INTEGER := 5
);
PORT (
app_wdf_rdy : OUT STD_LOGIC;
wr_req_16 : OUT STD_LOGIC;
wr_data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
wr_data_mask : OUT STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
raw_not_ecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
app_wdf_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_wdf_mask : IN STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
app_raw_not_ecc : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
app_wdf_wren : IN STD_LOGIC;
app_wdf_end : IN STD_LOGIC;
wr_data_offset : IN STD_LOGIC;
wr_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
wr_data_en : IN STD_LOGIC;
wr_accepted : IN STD_LOGIC;
ram_init_done_r : IN STD_LOGIC;
ram_init_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT ui_rd_data IS
GENERIC (
TCQ : INTEGER := 100;
APP_DATA_WIDTH : INTEGER := 256;
ECC : STRING := "OFF";
ORDERING : STRING := "NORM"
);
PORT (
ram_init_done_r : OUT STD_LOGIC;
ram_init_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
app_rd_data_valid : OUT STD_LOGIC;
app_rd_data_end : OUT STD_LOGIC;
app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_buf_full : OUT STD_LOGIC;
rd_data_buf_addr_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rst : IN STD_LOGIC;
clk : IN STD_LOGIC;
rd_data_en : IN STD_LOGIC;
rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_data_offset : IN STD_LOGIC;
rd_data_end : IN STD_LOGIC;
rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rd_accepted : IN STD_LOGIC
);
END COMPONENT;
-- End of automatics
-- Beginning of automatic wires (for undeclared instantiated-module outputs)
SIGNAL ram_init_addr : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_rd_data0 of ui_rd_data.v
SIGNAL ram_init_done_r : STD_LOGIC; -- From ui_rd_data0 of ui_rd_data.v
SIGNAL rd_accepted : STD_LOGIC; -- From ui_cmd0 of ui_cmd.v
SIGNAL rd_buf_full : STD_LOGIC; -- From ui_rd_data0 of ui_rd_data.v
SIGNAL rd_data_buf_addr_r : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_rd_data0 of ui_rd_data.v
SIGNAL wr_accepted : STD_LOGIC; -- From ui_cmd0 of ui_cmd.v
SIGNAL wr_data_buf_addr : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_wr_data0 of ui_wr_data.v
SIGNAL wr_req_16 : STD_LOGIC; -- From ui_wr_data0 of ui_wr_data.v
-- Declare intermediate signals for referenced outputs
SIGNAL wr_data_mask_xhdl17 : STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0);
SIGNAL wr_data_xhdl16 : STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL use_addr_xhdl15 : STD_LOGIC;
SIGNAL size_xhdl14 : STD_LOGIC;
SIGNAL row_xhdl13 : STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0);
SIGNAL raw_not_ecc_xhdl12 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rank_xhdl11 : STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0);
SIGNAL hi_priority_xhdl10 : STD_LOGIC;
SIGNAL data_buf_addr_xhdl9 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL col_xhdl8 : STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0);
SIGNAL cmd_xhdl7 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bank_xhdl6 : STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0);
SIGNAL app_wdf_rdy_xhdl5 : STD_LOGIC;
SIGNAL app_rdy_xhdl4 : STD_LOGIC;
SIGNAL app_rd_data_valid_xhdl3 : STD_LOGIC;
SIGNAL app_rd_data_end_xhdl2 : STD_LOGIC;
SIGNAL app_rd_data_xhdl1 : STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0);
SIGNAL app_ecc_multiple_err_xhdl0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL rst_reg : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL rst_final : STD_LOGIC;
SIGNAL app_addr_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
ATTRIBUTE max_fanout : STRING;
ATTRIBUTE max_fanout OF rst_final : SIGNAL IS "10";
BEGIN
-- Drive referenced outputs
wr_data_mask <= wr_data_mask_xhdl17;
wr_data <= wr_data_xhdl16;
use_addr <= use_addr_xhdl15;
size <= size_xhdl14;
row <= row_xhdl13;
raw_not_ecc <= raw_not_ecc_xhdl12;
rank <= rank_xhdl11;
hi_priority <= hi_priority_xhdl10;
data_buf_addr <= data_buf_addr_xhdl9;
col <= col_xhdl8;
cmd <= cmd_xhdl7;
bank <= bank_xhdl6;
app_wdf_rdy <= app_wdf_rdy_xhdl5;
app_rdy <= app_rdy_xhdl4;
app_rd_data_valid <= app_rd_data_valid_xhdl3;
app_rd_data_end <= app_rd_data_end_xhdl2;
app_rd_data <= app_rd_data_xhdl1;
app_ecc_multiple_err <= app_ecc_multiple_err_xhdl0;
correct_en <= app_correct_en;
-- End of automatics
rank_add_correction1: IF ( RANKS > 1 ) GENERATE
app_addr_temp <= app_addr;
END GENERATE;
rank_add_correction2: IF ( RANKS = 1 ) GENERATE
app_addr_temp <= ('0' & app_addr ( ADDR_WIDTH - 2 DOWNTO 0));
END GENERATE;
-- Parameters
PROCESS (clk)
BEGIN
IF ( clk'EVENT AND clk = '1') THEN
rst_reg <= (rst_reg(8 DOWNTO 0) & rst);
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF ( clk'EVENT AND clk = '1') THEN
rst_final <= rst_reg(9);
END IF;
END PROCESS;
ui_cmd0 : ui_cmd
GENERIC MAP (
TCQ => TCQ,
ADDR_WIDTH => ADDR_WIDTH,
BANK_WIDTH => BANK_WIDTH,
COL_WIDTH => COL_WIDTH,
RANK_WIDTH => RANK_WIDTH,
ROW_WIDTH => ROW_WIDTH,
RANKS => RANKS,
MEM_ADDR_ORDER => MEM_ADDR_ORDER
)
PORT MAP (
-- Outputs
app_rdy => app_rdy_xhdl4,
use_addr => use_addr_xhdl15,
rank => rank_xhdl11(RANK_WIDTH - 1 DOWNTO 0),
bank => bank_xhdl6(BANK_WIDTH - 1 DOWNTO 0),
row => row_xhdl13(ROW_WIDTH - 1 DOWNTO 0),
col => col_xhdl8(COL_WIDTH - 1 DOWNTO 0),
size => size_xhdl14,
cmd => cmd_xhdl7(2 DOWNTO 0),
hi_priority => hi_priority_xhdl10,
rd_accepted => rd_accepted,
wr_accepted => wr_accepted,
data_buf_addr => data_buf_addr_xhdl9(3 DOWNTO 0),
-- Inputs
rst => rst_final,
clk => clk,
accept_ns => accept_ns,
rd_buf_full => rd_buf_full,
wr_req_16 => wr_req_16,
app_addr => app_addr_temp(ADDR_WIDTH - 1 DOWNTO 0),
app_cmd => app_cmd(2 DOWNTO 0),
app_sz => app_sz,
app_hi_pri => app_hi_pri,
app_en => app_en,
wr_data_buf_addr => wr_data_buf_addr(3 DOWNTO 0),
rd_data_buf_addr_r => rd_data_buf_addr_r(3 DOWNTO 0)
);
-- Parameters
ui_wr_data0 : ui_wr_data
GENERIC MAP (
TCQ => TCQ,
APP_DATA_WIDTH => APP_DATA_WIDTH,
APP_MASK_WIDTH => APP_MASK_WIDTH,
ECC => ECC,
ECC_TEST => ECC_TEST,
CWL => CWL
)
PORT MAP (
-- Outputs
app_wdf_rdy => app_wdf_rdy_xhdl5,
wr_req_16 => wr_req_16,
wr_data_buf_addr => wr_data_buf_addr(3 DOWNTO 0),
wr_data => wr_data_xhdl16(APP_DATA_WIDTH - 1 DOWNTO 0),
wr_data_mask => wr_data_mask_xhdl17(APP_MASK_WIDTH - 1 DOWNTO 0),
raw_not_ecc => raw_not_ecc_xhdl12(3 DOWNTO 0),
-- Inputs
rst => rst_final,
clk => clk,
app_wdf_data => app_wdf_data(APP_DATA_WIDTH - 1 DOWNTO 0),
app_wdf_mask => app_wdf_mask(APP_MASK_WIDTH - 1 DOWNTO 0),
app_raw_not_ecc => app_raw_not_ecc(3 DOWNTO 0),
app_wdf_wren => app_wdf_wren,
app_wdf_end => app_wdf_end,
wr_data_offset => wr_data_offset,
wr_data_addr => wr_data_addr(3 DOWNTO 0),
wr_data_en => wr_data_en,
wr_accepted => wr_accepted,
ram_init_done_r => ram_init_done_r,
ram_init_addr => ram_init_addr(3 DOWNTO 0)
);
-- Parameters
ui_rd_data0 : ui_rd_data
GENERIC MAP (
TCQ => TCQ,
APP_DATA_WIDTH => APP_DATA_WIDTH,
ECC => ECC,
ORDERING => ORDERING
)
PORT MAP (
-- Outputs
ram_init_done_r => ram_init_done_r,
ram_init_addr => ram_init_addr(3 DOWNTO 0),
app_rd_data_valid => app_rd_data_valid_xhdl3,
app_rd_data_end => app_rd_data_end_xhdl2,
app_rd_data => app_rd_data_xhdl1(APP_DATA_WIDTH - 1 DOWNTO 0),
app_ecc_multiple_err => app_ecc_multiple_err_xhdl0(3 DOWNTO 0),
rd_buf_full => rd_buf_full,
rd_data_buf_addr_r => rd_data_buf_addr_r(3 DOWNTO 0),
-- Inputs
rst => rst_final,
clk => clk,
rd_data_en => rd_data_en,
rd_data_addr => rd_data_addr(3 DOWNTO 0),
rd_data_offset => rd_data_offset,
rd_data_end => rd_data_end,
rd_data => rd_data(APP_DATA_WIDTH - 1 DOWNTO 0),
ecc_multiple => ecc_multiple(3 DOWNTO 0),
rd_accepted => rd_accepted
);
END ARCHITECTURE trans;
-- ui_top
|
lgpl-3.0
|
d0bfa1ccebea647b30d7de38566d1eac
| 0.507323 | 3.60856 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/sim/amc7823_init_mem.vhd
| 1 | 5,466 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file amc7823_init_mem.vhd when simulating
-- the core, amc7823_init_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY amc7823_init_mem IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END amc7823_init_mem;
ARCHITECTURE amc7823_init_mem_a OF amc7823_init_mem IS
-- synthesis translate_off
COMPONENT wrapped_amc7823_init_mem
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_amc7823_init_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "virtex6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/sim/amc7823_init_mem.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_amc7823_init_mem
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END amc7823_init_mem_a;
|
lgpl-3.0
|
747da997b9c14d250d3997a70ff05cd5
| 0.536407 | 3.926724 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/rx_MWr_Channel.vhd
| 1 | 26,723 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: rx_MWr_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.10 - x4 timing constraints met. 02.02.2007
--
-- Revision 1.04 - Timing improved. 17.01.2007
--
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_MWr_Transact is
port (
-- Transaction receive interface
m_axis_rx_tlast : in std_logic;
m_axis_rx_tdata : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
m_axis_rx_tkeep : in std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
m_axis_rx_terrfwd : in std_logic;
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tready : in std_logic; -- !!
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- SDRAM and Wishbone address page
sdram_pg : in std_logic_vector(31 downto 0);
wb_pg : in std_logic_vector(31 downto 0);
-- from pre-process module
MWr_Type : in std_logic_vector(1 downto 0);
-- Last_DW_of_TLP : IN std_logic;
Tlp_has_4KB : in std_logic;
-- Event Buffer write port
wb_FIFO_we : out std_logic;
wb_FIFO_wsof : out std_logic;
wb_FIFO_weof : out std_logic;
wb_FIFO_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : out std_logic;
Regs_WrMask : out std_logic_vector(2-1 downto 0);
Regs_WrAddr : out std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : out std_logic;
DDR_wr_eof : out std_logic;
DDR_wr_v : out std_logic;
DDR_wr_Shift : out std_logic;
DDR_wr_Mask : out std_logic_vector(2-1 downto 0);
DDR_wr_din : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : in std_logic;
-- Common ports
user_clk : in std_logic;
user_reset : in std_logic;
user_lnk_up : in std_logic
);
end entity rx_MWr_Transact;
architecture Behavioral of rx_MWr_Transact is
type RxMWrTrnStates is (ST_MWr_RESET
, ST_MWr_IDLE
-- , ST_MWr3_HEAD1
-- , ST_MWr4_HEAD1
, ST_MWr3_HEAD2
, ST_MWr4_HEAD2
-- , ST_MWr4_HEAD3
-- , ST_MWr_Last_HEAD
, ST_MWr4_1ST_DATA
, ST_MWr_1ST_DATA
, ST_MWr_1ST_DATA_THROTTLE
, ST_MWr_DATA
, ST_MWr_DATA_THROTTLE
-- , ST_MWr_LAST_DATA
);
-- State variables
signal RxMWrTrn_NextState : RxMWrTrnStates;
signal RxMWrTrn_State : RxMWrTrnStates;
-- trn_rx stubs
signal m_axis_rx_tdata_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tdata_hdrfix : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tkeep_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tkeep_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal m_axis_rx_tbar_hit_i : std_logic_vector (C_BAR_NUMBER-1 downto 0);
signal m_axis_rx_tbar_hit_r1 : std_logic_vector (C_BAR_NUMBER-1 downto 0);
signal m_axis_rx_tvalid_i : std_logic;
signal trn_rsof_n_i : std_logic;
signal in_packet_reg : std_logic;
signal m_axis_rx_tlast_i : std_logic;
signal m_axis_rx_tlast_r1 : std_logic;
-- packet RAM and packet FIFOs selection signals
signal FIFO_Space_Sel : std_logic;
signal DDR_Space_Sel : std_logic;
signal REGS_Space_Sel : std_logic;
-- DDR write port
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal ddr_wr_1st_mask_hi : std_logic;
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer write port
signal wb_FIFO_we_i : std_logic;
signal wb_FIFO_wsof_i : std_logic;
signal wb_FIFO_weof_i : std_logic;
signal wb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
signal Regs_WrEn_i : std_logic;
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal m_axis_rx_tready_i : std_logic;
signal trn_rx_throttle : std_logic;
signal trn_rx_throttle_r1 : std_logic;
-- 1st DW BE = "0000" means the TLP is of zero-length.
signal MWr_Has_4DW_Header : std_logic;
signal Tlp_is_Zero_Length : std_logic;
signal MWr_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
begin
-- Event Buffer write
wb_FIFO_we <= wb_FIFO_we_i;
wb_FIFO_wsof <= wb_FIFO_wsof_i;
wb_FIFO_weof <= wb_FIFO_weof_i;
wb_FIFO_din <= wb_FIFO_din_i;
-- DDR
DDR_wr_sof <= DDR_wr_sof_i;
DDR_wr_eof <= DDR_wr_eof_i;
DDR_wr_v <= DDR_wr_v_i;
DDR_wr_Shift <= DDR_wr_Shift_i;
DDR_wr_Mask <= DDR_wr_Mask_i;
DDR_wr_din <= DDR_wr_din_i;
-- Registers writing
Regs_WrEn <= Regs_WrEn_i;
Regs_WrMask <= Regs_WrMask_i;
Regs_WrAddr <= Regs_WrAddr_i;
Regs_WrDin <= Regs_WrDin_i; -- Mem_WrData;
-- TLP info stubs
m_axis_rx_tdata_i <= m_axis_rx_tdata;
m_axis_rx_tlast_i <= m_axis_rx_tlast;
m_axis_rx_tkeep_i <= m_axis_rx_tkeep;
m_axis_rx_tdata_hdrfix <= m_axis_rx_tdata_r1 when MWr_Has_4DW_Header = '1' else
(m_axis_rx_tdata_r1(31 downto 0) & m_axis_rx_tdata_r2(63 downto 32));
-- Output to the core as handshaking
m_axis_rx_tbar_hit_i <= m_axis_rx_tbar_hit;
-- Output to the core as handshaking
m_axis_rx_tvalid_i <= m_axis_rx_tvalid;
m_axis_rx_tready_i <= m_axis_rx_tready;
-- ( m_axis_rx_tvalid seems never deasserted during packet)
trn_rx_throttle <= not(m_axis_rx_tvalid_i) or not(m_axis_rx_tready_i);
-- -----------------------------------------------------
-- Delays: m_axis_rx_tdata_i, m_axis_rx_tbar_hit_i, m_axis_rx_tlast_i
-- -----------------------------------------------------
Sync_Delays_m_axis_rx_tdata_rbar_reof :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
trn_rx_throttle_r1 <= trn_rx_throttle;
m_axis_rx_tlast_r1 <= m_axis_rx_tlast_i;
m_axis_rx_tdata_r1 <= m_axis_rx_tdata_i;
m_axis_rx_tdata_r2 <= m_axis_rx_tdata_r1;
m_axis_rx_tkeep_r1 <= m_axis_rx_tkeep_i;
m_axis_rx_tbar_hit_r1 <= m_axis_rx_tbar_hit_i;
end if;
end process;
-- -----------------------------------------------------------------------
-- States synchronous
--
Syn_RxTrn_States :
process (user_clk, user_reset)
begin
if user_reset = '1' then
RxMWrTrn_State <= ST_MWr_RESET;
elsif user_clk'event and user_clk = '1' then
RxMWrTrn_State <= RxMWrTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates :
process (
RxMWrTrn_State
, MWr_Type
, trn_rx_throttle
, m_axis_rx_tlast_i
)
begin
case RxMWrTrn_State is
when ST_MWr_RESET =>
RxMWrTrn_NextState <= ST_MWr_IDLE;
when ST_MWr_IDLE =>
if trn_rx_throttle = '0' then
case MWr_Type is
when C_TLP_TYPE_IS_MWR_H3 =>
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
when C_TLP_TYPE_IS_MWR_H4 =>
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
when others =>
RxMWrTrn_NextState <= ST_MWr_IDLE;
end case; -- MWr_Type
else
RxMWrTrn_NextState <= ST_MWr_IDLE;
end if;
when ST_MWr3_HEAD2 =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
elsif m_axis_rx_tlast_i = '1' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_1ST_DATA; -- ST_MWr_Last_HEAD;
end if;
when ST_MWr4_HEAD2 =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
else
RxMWrTrn_NextState <= ST_MWr4_1ST_DATA; -- ST_MWr4_HEAD3;
end if;
when ST_MWr_1ST_DATA =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
elsif m_axis_rx_tlast_i = '1' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr4_1ST_DATA =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
elsif m_axis_rx_tlast_i = '1' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr_1ST_DATA_THROTTLE =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
elsif m_axis_rx_tlast_i = '1' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr_DATA =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_DATA_THROTTLE;
elsif m_axis_rx_tlast_i = '1' then
RxMWrTrn_NextState <= ST_MWr_IDLE;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr_DATA_THROTTLE =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_DATA_THROTTLE;
elsif m_axis_rx_tlast_i = '1' then
RxMWrTrn_NextState <= ST_MWr_IDLE;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when others =>
RxMWrTrn_NextState <= ST_MWr_RESET;
end case;
end process;
-- ----------------------------------------------
-- registers Write Enable
--
RxFSM_Output_Regs_Write_En :
process (user_clk, user_reset)
begin
if user_reset = '1' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxMWrTrn_State is
when ST_MWr3_HEAD2 =>
if REGS_Space_Sel = '1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrMask_i <= "01";
Regs_WrAddr_i <= m_axis_rx_tdata_i(C_EP_AWIDTH-1 downto 2) & "00";
Regs_WrDin_i <= Endian_Invert_64(m_axis_rx_tdata_i(63 downto 32) & X"00000000");
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end if;
when ST_MWr4_HEAD2 =>
if REGS_Space_Sel = '1' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= m_axis_rx_tdata_i(32+C_EP_AWIDTH-1 downto 32+2) &"00";
Regs_WrDin_i <= Endian_Invert_64(m_axis_rx_tdata_i);
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end if;
when ST_MWr_1ST_DATA =>
if REGS_Space_Sel = '1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrDin_i <= Endian_Invert_64 (m_axis_rx_tdata_i(31 downto 0) & m_axis_rx_tdata(63 downto 32));
if m_axis_rx_tlast_i = '1' then
Regs_WrMask_i <= '0' & (m_axis_rx_tkeep_i(3) and m_axis_rx_tkeep_i(0));
else
Regs_WrMask_i <= (others => '0');
end if;
if MWr_Has_4DW_Header = '1' then
Regs_WrAddr_i <= Regs_WrAddr_i;
else
Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
end if;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end if;
when ST_MWr4_1ST_DATA =>
if REGS_Space_Sel = '1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrDin_i <= Endian_Invert_64 (m_axis_rx_tdata_i(31 downto 0) & m_axis_rx_tdata(63 downto 32));
if m_axis_rx_tlast_i = '1' then
Regs_WrMask_i <= '0' & (m_axis_rx_tkeep_i(3) and m_axis_rx_tkeep_i(0));
else
Regs_WrMask_i <= (others => '0');
end if;
-- if MWr_Has_4DW_Header='1' then
Regs_WrAddr_i <= Regs_WrAddr_i;
-- else
-- Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
-- end if;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end if;
when ST_MWr_1ST_DATA_THROTTLE =>
if REGS_Space_Sel = '1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrDin_i <= Endian_Invert_64 (m_axis_rx_tdata_i(31 downto 0) & m_axis_rx_tdata(63 downto 32));
if m_axis_rx_tlast_i = '1' then
Regs_WrMask_i <= '0' & (m_axis_rx_tkeep_i(3) and m_axis_rx_tkeep_i(0));
else
Regs_WrMask_i <= (others => '0');
end if;
-- if MWr_Has_4DW_Header='1' then
Regs_WrAddr_i <= Regs_WrAddr_i;
-- else
-- Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
-- end if;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end if;
when ST_MWr_DATA =>
if REGS_Space_Sel = '1' then
Regs_WrEn_i <= not trn_rx_throttle; -- '1';
if m_axis_rx_tlast_i = '1' then
Regs_WrMask_i <= '0' & (m_axis_rx_tkeep_i(3) and m_axis_rx_tkeep_i(0));
else
Regs_WrMask_i <= (others => '0');
end if;
Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(8, C_EP_AWIDTH);
Regs_WrDin_i <= Endian_Invert_64 (m_axis_rx_tdata_i(31 downto 0) & m_axis_rx_tdata(63 downto 32));
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end if;
when ST_MWr_DATA_THROTTLE =>
if REGS_Space_Sel = '1' then
Regs_WrEn_i <= not trn_rx_throttle; -- '1';
if m_axis_rx_tlast_i = '1' then
Regs_WrMask_i <= '0' & (m_axis_rx_tkeep_i(3) and m_axis_rx_tkeep_i(0));
else
Regs_WrMask_i <= (others => '0');
end if;
Regs_WrAddr_i <= Regs_WrAddr_i; -- + CONV_STD_LOGIC_VECTOR(8, C_EP_AWIDTH);
Regs_WrDin_i <= Endian_Invert_64 (m_axis_rx_tdata_i(31 downto 0) & m_axis_rx_tdata(63 downto 32));
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end if;
when others =>
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (others => '0');
Regs_WrAddr_i <= (others => '1');
Regs_WrDin_i <= (others => '0');
end case;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: REGS_Space_Sel
--
Syn_Capture_REGS_Space_Sel :
process (user_clk, user_reset)
begin
if user_reset = '1' then
REGS_Space_Sel <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' then
REGS_Space_Sel <= (m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+3)
or m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+2)
or m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+1)
or m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+0))
and m_axis_rx_tbar_hit_i(CINT_REGS_SPACE_BAR);
else
REGS_Space_Sel <= REGS_Space_Sel;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MWr_Has_4DW_Header
-- : Tlp_is_Zero_Length
--
Syn_Capture_MWr_Has_4DW_Header :
process (user_clk, user_reset)
begin
if user_reset = '1' then
MWr_Has_4DW_Header <= '0';
Tlp_is_Zero_Length <= '0';
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' then
MWr_Has_4DW_Header <= m_axis_rx_tdata_i(C_TLP_FMT_BIT_BOT);
Tlp_is_Zero_Length <= not(m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+3)
or m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+2)
or m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+1)
or m_axis_rx_tdata_i(C_TLP_1ST_BE_BIT_BOT+0));
else
MWr_Has_4DW_Header <= MWr_Has_4DW_Header;
Tlp_is_Zero_Length <= Tlp_is_Zero_Length;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MWr_Leng_in_Bytes
--
Syn_Capture_MWr_Length_in_Bytes :
process (user_clk, user_reset)
begin
if user_reset = '1' then
MWr_Leng_in_Bytes <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if trn_rsof_n_i = '0' then
-- Assume no 4KB length for MWr
MWr_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 2) <=
Tlp_has_4KB & m_axis_rx_tdata_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
else
MWr_Leng_in_Bytes <= MWr_Leng_in_Bytes;
end if;
end if;
end process;
-- ----------------------------------------------
-- Synchronous outputs: DDR Space Select --
-- ----------------------------------------------
RxFSM_Output_DDR_Space_Selected :
process (user_clk, user_reset)
begin
if user_reset = '1' then
DDR_Space_Sel <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= (others => '0');
ddr_wr_1st_mask_hi <= '0';
elsif user_clk'event and user_clk = '1' then
case RxMWrTrn_State is
when ST_MWr3_HEAD2 =>
if m_axis_rx_tbar_hit_r1(CINT_DDR_SPACE_BAR) = '1'
and Tlp_is_Zero_Length = '0'
then
DDR_Space_Sel <= '1';
DDR_wr_sof_i <= '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= not trn_rx_throttle;
DDR_wr_Shift_i <= not m_axis_rx_tdata_i(2);
DDR_wr_Mask_i <= (others => '0');
ddr_wr_1st_mask_hi <= '1';
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & sdram_pg(31-C_DDR_PG_WIDTH downto 0) &
m_axis_rx_tdata_i(C_DDR_PG_WIDTH-1 downto 0);
else
DDR_Space_Sel <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= DDR_wr_din_i;
end if;
when ST_MWr4_HEAD2 =>
if m_axis_rx_tbar_hit_r1(CINT_DDR_SPACE_BAR) = '1'
and Tlp_is_Zero_Length = '0'
then
DDR_Space_Sel <= '1';
DDR_wr_sof_i <= '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= not trn_rx_throttle;
DDR_wr_Shift_i <= m_axis_rx_tdata_i(2+32);
DDR_wr_Mask_i <= (others => '0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & sdram_pg(31-C_DDR_PG_WIDTH downto 0) &
m_axis_rx_tdata_i(32+C_DDR_PG_WIDTH-1 downto 32);
else
DDR_Space_Sel <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= DDR_wr_din_i;
end if;
when ST_MWr4_1ST_DATA =>
DDR_Space_Sel <= DDR_Space_Sel;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= (others => '0');
when others =>
if m_axis_rx_tlast_r1 = '1' then
DDR_Space_Sel <= '0';
else
DDR_Space_Sel <= DDR_Space_Sel;
end if;
--write the last word unconditionally, otherwise we may lose it
--because RxMwTrn_State could switch from IDLE to St_MWR3_HEAD2 before
--trn_rx_throttle_r1 deasserts
if DDR_Space_Sel = '1' then
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= m_axis_rx_tlast_r1;
DDR_wr_v_i <= not(trn_rx_throttle_r1) or m_axis_rx_tlast_r1;
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= not(m_axis_rx_tkeep_r1(4)) & (not(m_axis_rx_tkeep_r1(0)) or ddr_wr_1st_mask_hi);
DDR_wr_din_i <= Endian_Invert_64 (m_axis_rx_tdata_r1(63 downto 32) & m_axis_rx_tdata_r1(31 downto 0));
else
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (others => '0');
DDR_wr_din_i <= Endian_Invert_64 (m_axis_rx_tdata_r1(63 downto 32) & m_axis_rx_tdata_r1(31 downto 0));
end if;
if DDR_wr_v_i = '1' then
ddr_wr_1st_mask_hi <= '0';
else
ddr_wr_1st_mask_hi <= ddr_wr_1st_mask_hi;
end if;
end case;
end if;
end process;
-- ----------------------------------------------
-- Synchronous outputs: WB FIFO Select --
-- ----------------------------------------------
RxFSM_Output_FIFO_Space_Selected :
process (user_clk, user_reset)
begin
if user_reset = '1' then
FIFO_Space_Sel <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_din_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
case RxMWrTrn_State is
when ST_MWr3_HEAD2 =>
if m_axis_rx_tbar_hit_r1(CINT_FIFO_SPACE_BAR) = '1'
and Tlp_is_Zero_Length = '0'
then
FIFO_Space_Sel <= '1';
wb_FIFO_we_i <= not trn_rx_throttle;
wb_FIFO_wsof_i <= '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_din_i <= MWr_Leng_in_Bytes(31 downto 0) & wb_pg(31-C_WB_PG_WIDTH downto 0) &
m_axis_rx_tdata_i(C_WB_PG_WIDTH-1 downto 0);
else
FIFO_Space_Sel <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
end if;
when ST_MWr_1ST_DATA =>
FIFO_Space_Sel <= FIFO_Space_Sel;
wb_FIFO_we_i <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_din_i <= wb_FIFO_din_i;
when ST_MWr4_HEAD2 =>
if m_axis_rx_tbar_hit_r1(CINT_FIFO_SPACE_BAR) = '1'
and Tlp_is_Zero_Length = '0'
then
FIFO_Space_Sel <= '1';
wb_FIFO_we_i <= not trn_rx_throttle;
wb_FIFO_wsof_i <= '1';
wb_FIFO_weof_i <= '0';
wb_FIFO_din_i <= MWr_Leng_in_Bytes(31 downto 0) & wb_pg(31-C_WB_PG_WIDTH downto 0) &
m_axis_rx_tdata_i(32+C_WB_PG_WIDTH-1 downto 32);
else
FIFO_Space_Sel <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
end if;
when ST_MWr4_1ST_DATA =>
FIFO_Space_Sel <= FIFO_Space_Sel;
wb_FIFO_we_i <= '0';
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_din_i <= wb_FIFO_din_i;
when others =>
if m_axis_rx_tlast_r1 = '1' and trn_rx_throttle_r1 = '0' then
FIFO_Space_Sel <= '0';
else
FIFO_Space_Sel <= FIFO_Space_Sel;
end if;
if FIFO_Space_Sel = '1' then
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= m_axis_rx_tlast_r1;
wb_FIFO_we_i <= not trn_rx_throttle_r1;
wb_FIFO_din_i <= Endian_Invert_64(m_axis_rx_tdata_hdrfix);
else
wb_FIFO_wsof_i <= '0';
wb_FIFO_weof_i <= '0';
wb_FIFO_we_i <= '0';
wb_FIFO_din_i <= wb_FIFO_din_i;
end if;
end case;
end if;
end process;
-- ---------------------------------
-- Regenerate trn_rsof_n signal as in old TRN core
--
TRN_rsof_n_make :
process (user_clk, user_reset)
begin
if user_reset = '1' then
in_packet_reg <= '0';
elsif rising_edge(user_clk) then
if (m_axis_rx_tvalid and m_axis_rx_tready) = '1' then
in_packet_reg <= not(m_axis_rx_tlast);
end if;
end if;
end process;
trn_rsof_n_i <= not(m_axis_rx_tvalid and not(in_packet_reg));
end architecture Behavioral;
|
lgpl-3.0
|
daf11291b88ebb4f6a3a7e0bfab674bb
| 0.493058 | 3.114569 | false | false | false | false |
fbelavenuto/msx1fpga
|
synth/zxuno_vga2m/ipcore_dir/pll1.vhd
| 1 | 6,021 |
-- file: pll1.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____21.512______0.000______50.0______338.146____247.402
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________50.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll1 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end pll1;
architecture xilinx of pll1 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll1,clk_wiz_v3_6,{component_name=pll1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 37,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 43,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1_unused,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
|
gpl-3.0
|
65e46734da56fb87d97fb8642410b180
| 0.602059 | 4.225263 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/ecc/ecc_buf.vhd
| 1 | 6,708 |
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 01:00:41
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_buf.v
-- Component name : ecc_buf
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
library UNISIM;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- use UNISIM.VCOMPONENTS.all;
entity ecc_buf is
generic (
TCQ : integer := 100;
PAYLOAD_WIDTH : integer := 64;
DATA_BUF_ADDR_WIDTH : integer := 4;
DATA_BUF_OFFSET_WIDTH : integer := 1;
DATA_WIDTH : integer := 64
);
port (
-- Outputs
-- Inputs
-- RMW architecture supports only 16 data buffer entries.
-- Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
-- assume the upper bits are used for tagging.
-- block: rd_buffer_ram
rd_merge_data : out std_logic_vector(4 * DATA_WIDTH - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
rd_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
rd_data_offset : in std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
wr_data_addr : in std_logic_vector(DATA_BUF_ADDR_WIDTH - 1 downto 0);
wr_data_offset : in std_logic_vector(DATA_BUF_OFFSET_WIDTH - 1 downto 0);
rd_data : in std_logic_vector(4 * PAYLOAD_WIDTH - 1 downto 0);
wr_ecc_buf : in std_logic
);
end entity ecc_buf;
architecture trans of ecc_buf is
component RAM32M
generic (
INIT_A : bit_vector(63 downto 0) := X"0000000000000000";
INIT_B : bit_vector(63 downto 0) := X"0000000000000000";
INIT_C : bit_vector(63 downto 0) := X"0000000000000000";
INIT_D : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
DOC : out std_logic_vector (1 downto 0);
DOD : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector(4 downto 0);
ADDRB : in std_logic_vector(4 downto 0);
ADDRC : in std_logic_vector(4 downto 0);
ADDRD : in std_logic_vector(4 downto 0);
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
DIC : in std_logic_vector (1 downto 0);
DID : in std_logic_vector (1 downto 0);
WCLK : in std_ulogic;
WE : in std_ulogic
);
end component;
function f_RAM_CNT (FULL_RAM_CNT: integer; REMAINDER : integer)
return integer is
begin
if (REMAINDER = 0) then
return FULL_RAM_CNT ;
else
return FULL_RAM_CNT + 1 ;
end if;
end f_RAM_CNT;
function nCOPY (A : in std_logic; B : in integer) return std_logic_vector is
variable tmp : std_logic_vector(B - 1 downto 0);
begin
for i in 0 to B - 1 loop
tmp(i) := A;
end loop;
return tmp;
end function nCOPY;
constant BUF_WIDTH : integer := 4 * DATA_WIDTH;
constant FULL_RAM_CNT : integer := (BUF_WIDTH / 6);
constant REMAINDER : integer := BUF_WIDTH mod 6;
constant RAM_CNT : integer := f_RAM_CNT(FULL_RAM_CNT ,REMAINDER );
constant RAM_WIDTH : integer := (RAM_CNT * 6);
signal buf_wr_addr : std_logic_vector(4 downto 0);
signal buf_rd_addr_r : std_logic_vector(4 downto 0);
signal payload : std_logic_vector(4 * DATA_WIDTH - 1 downto 0);
signal h : integer;
signal buf_out_data : std_logic_vector(RAM_WIDTH - 1 downto 0);
signal buf_in_data : std_logic_vector(RAM_WIDTH - 1 downto 0);
begin
int0 : if (DATA_BUF_ADDR_WIDTH >= 4) generate
process (clk)
begin
if (clk'event and clk = '1') then
buf_rd_addr_r <= (wr_data_addr(3 downto 0) & wr_data_offset) after (TCQ)*1 ps;
end if;
end process;
buf_wr_addr <= (rd_data_addr(3 downto 0) & rd_data_offset);
end generate;
int1 : if (not(DATA_BUF_ADDR_WIDTH >= 4)) generate
process (clk)
begin
if (clk'event and clk = '1') then
buf_rd_addr_r <= ( nCOPY('0',4 - DATA_BUF_ADDR_WIDTH) & wr_data_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0) & wr_data_offset) after (TCQ)*1 ps;
end if;
end process;
buf_wr_addr <= ( nCOPY('0',4 - DATA_BUF_ADDR_WIDTH) & rd_data_addr(DATA_BUF_ADDR_WIDTH - 1 downto 0) & rd_data_offset);
end generate;
process (rd_data)
begin
for h in 0 to 3 loop
payload((DATA_WIDTH*h)+DATA_WIDTH-1 downto h * DATA_WIDTH) <= rd_data((PAYLOAD_WIDTH*h)+DATA_WIDTH-1 downto h * PAYLOAD_WIDTH);
end loop;
end process;
int2 : if (REMAINDER = 0) generate
buf_in_data <= payload;
end generate;
int3 : if (not(REMAINDER = 0)) generate
buf_in_data <= nCOPY('0',6 - REMAINDER) & payload;
end generate;
rd_buffer_ram : for i in 0 to RAM_CNT - 1 generate
RAM32M0 : RAM32M
generic map (
INIT_A => "0000000000000000000000000000000000000000000000000000000000000000",
INIT_B => "0000000000000000000000000000000000000000000000000000000000000000",
INIT_C => "0000000000000000000000000000000000000000000000000000000000000000",
INIT_D => "0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => buf_out_data((i * 6) + 4 + 1 downto (i * 6) + 4),
DOB => buf_out_data((i * 6) + 2 + 1 downto (i * 6) + 2),
DOC => buf_out_data((i * 6) + 0 + 1 downto (i * 6) + 0),
DOD => open,
DIA => buf_in_data((i * 6) + 4 + 1 downto (i * 6) + 4),
DIB => buf_in_data((i * 6) + 2 + 1 downto (i * 6) + 2),
DIC => buf_in_data((i * 6) + 0 + 1 downto (i * 6) + 0),
DID => "00",
ADDRA => buf_rd_addr_r,
ADDRB => buf_rd_addr_r,
ADDRC => buf_rd_addr_r,
ADDRD => buf_wr_addr,
WE => wr_ecc_buf,
WCLK => clk
);
end generate;
rd_merge_data <= buf_out_data(4 * DATA_WIDTH - 1 downto 0);
end architecture trans;
|
lgpl-3.0
|
1f3f8da95266589062f2cba361348db9
| 0.538312 | 3.56051 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/video/vdp18/vdp18_paletas_3bit_pack.vhd
| 2 | 5,149 |
-------------------------------------------------------------------------------
--
-- Based on: $Id: vdp18_col_pack-p.vhd,v 1.3 2006/02/28 22:30:41 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package vdp18_paletas_3bit_pack is
constant r_c : natural := 0;
constant g_c : natural := 1;
constant b_c : natural := 2;
subtype rgb_val_t is natural range 0 to 7;
type rgb_triple_t is array (natural range 0 to 2) of rgb_val_t;
type rgb_table_t is array (natural range 0 to 15) of rgb_triple_t;
-- Original
constant paleta1_c : rgb_table_t := (
-- R G B
( 0, 0, 0), -- Transparent RGB
( 0, 0, 0), -- Black 000
( 1, 6, 2), -- Medium Green 162
( 2, 6, 3), -- Light Green 263
( 2, 2, 7), -- Dark Blue 227
( 3, 3, 7), -- Light Blue 337
( 6, 2, 2), -- Dark Red 622
( 2, 7, 7), -- Cyan 277
( 7, 2, 2), -- Medium Red 722
( 7, 3, 3), -- Light Red 733
( 6, 6, 2), -- Dark Yellow 662
( 7, 6, 4), -- Light Yellow 764
( 1, 5, 1), -- Dark Green 151
( 6, 2, 5), -- Magenta 625
( 3, 3, 3), -- Gray 333
( 7, 7, 7) -- White 777
);
-- MSXBT601
constant paleta2_c : rgb_table_t := (
-- R G B
( 0, 0, 0), -- Transparent RB0G
( 0, 0, 0), -- Black 0000
( 0, 6, 1), -- Medium Green 0106
( 2, 7, 3), -- Light Green 2307
( 2, 2, 7), -- Dark Blue 2702
( 3, 3, 7), -- Light Blue 3703
( 6, 2, 2), -- Dark Red 6202
( 1, 7, 7), -- Cyan 1707
( 7, 2, 2), -- Medium Red 7202
( 7, 3, 3), -- Light Red 7303
( 6, 6, 2), -- Dark Yellow 6206
( 6, 6, 3), -- Light Yellow 6306
( 0, 5, 1), -- Dark Green 0105
( 6, 3, 5), -- Magenta 6503
( 6, 6, 6), -- Gray 6606
( 7, 7, 7) -- White 7707
);
-- MSX1YUV
constant paleta3_c : rgb_table_t := (
-- R G B
( 0, 0, 0), -- Transparent RB0G
( 0, 0, 0), -- Black 0000
( 0, 6, 1), -- Medium Green 2205
( 2, 7, 3), -- Light Green 3306
( 2, 2, 7), -- Dark Blue 2602
( 3, 3, 7), -- Light Blue 3703
( 6, 2, 2), -- Dark Red 5203
( 1, 7, 7), -- Cyan 3706
( 7, 2, 2), -- Medium Red 6203
( 7, 3, 3), -- Light Red 7304
( 6, 6, 2), -- Dark Yellow 6305
( 6, 6, 3), -- Light Yellow 6406
( 0, 5, 1), -- Dark Green 2204
( 6, 3, 5), -- Magenta 5503
( 6, 6, 6), -- Gray 6606
( 7, 7, 7) -- White 7707
);
-- ZX Spectrum
constant paleta4_c : rgb_table_t := (
-- R G B
( 0, 0, 0), -- Transparent RB0G
( 0, 0, 0), -- Black 0000
( 0, 7, 0), -- Medium Green 0007
( 0, 7, 7), -- Light Green 0707
( 0, 0, 5), -- Dark Blue 0500
( 0, 0, 7), -- Light Blue 0700
( 5, 0, 0), -- Dark Red 5000
( 0, 5, 5), -- Cyan 0505
( 7, 0, 0), -- Medium Red 7000
( 7, 0, 7), -- Light Red 7700
( 5, 5, 0), -- Dark Yellow 5005
( 7, 7, 0), -- Light Yellow 7007
( 0, 5, 0), -- Dark Green 0005
( 5, 0, 5), -- Magenta 5500
( 5, 5, 5), -- Gray 5505
( 7, 7, 7) -- White 7707
);
-- FRS Cool Colors
constant paleta5_c : rgb_table_t := (
-- R G B
( 0, 0, 0), -- Transparent RB0G
( 0, 0, 0), -- Black 0000
( 2, 5, 3), -- Medium Green 2305
( 3, 6, 4), -- Light Green 3406
( 1, 2, 5), -- Dark Blue 1502
( 2, 3, 6), -- Light Blue 2603
( 5, 2, 1), -- Dark Red 5102
( 3, 5, 7), -- Cyan 3705
( 6, 3, 2), -- Medium Red 6203
( 7, 4, 2), -- Light Red 7204
( 7, 6, 2), -- Dark Yellow 7206
( 7, 7, 4), -- Light Yellow 7407
( 1, 4, 2), -- Dark Green 1204
( 5, 2, 4), -- Magenta 5402
( 5, 5, 5), -- Gray 5505
( 7, 7, 7) -- White 7707
);
end package;
|
gpl-3.0
|
e75ded64d3a7c63d46658ae0dab30497
| 0.336764 | 3.131995 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/video/vdp18/vdp18_pack-p.vhd
| 2 | 8,447 |
-------------------------------------------------------------------------------
--
-- $Id: vdp18_pack-p.vhd,v 1.14 2006/02/22 23:07:05 arnim Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package vdp18_pack is
-----------------------------------------------------------------------------
-- Subtype for horizontal/vertical counters/positions.
--
subtype hv_t is signed(0 to 8);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constants for first and last vertical line of NTSC and PAL mode.
--
constant hv_first_line_ntsc_c : hv_t := to_signed(-40, hv_t'length);
constant hv_last_line_ntsc_c : hv_t := to_signed(221, hv_t'length);
--
constant hv_first_line_pal_c : hv_t := to_signed(-65, hv_t'length);
constant hv_last_line_pal_c : hv_t := to_signed(247, hv_t'length);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constants for first and last horizontal pixel in text and graphics.
--
constant hv_first_pix_text_c : hv_t := to_signed(-102, hv_t'length); -- 342
constant hv_last_pix_text_c : hv_t := to_signed(239, hv_t'length);
--
constant hv_first_pix_graph_c : hv_t := to_signed(-86, hv_t'length); -- 342
constant hv_last_pix_graph_c : hv_t := to_signed(255, hv_t'length);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Miscellaneous constants for horizontal phases.
--
constant hv_vertical_inc_c : hv_t := to_signed(-32, hv_t'length);
constant hv_sprite_start_c : hv_t := to_signed(247, hv_t'length);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Operating modes of the VDP18 core.
--
type opmode_t is (OPMODE_GRAPH1, OPMODE_GRAPH2,
OPMODE_MULTIC, OPMODE_TEXTM);
--
constant opmode_graph1_c : std_logic_vector(0 to 2) := "000";
constant opmode_graph2_c : std_logic_vector(0 to 2) := "001";
constant opmode_multic_c : std_logic_vector(0 to 2) := "010";
constant opmode_textm_c : std_logic_vector(0 to 2) := "100";
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Access types.
--
type access_t is (-- pattern access
-- read Pattern Name Table
AC_PNT,
-- read Pattern Generator Table
AC_PGT,
-- read Pattern Color Table
AC_PCT,
-- sprite access
-- sprite test read (y coordinate)
AC_STST,
-- read Sprite Attribute Table/Y
AC_SATY,
-- read Sprite Attribute Table/X
AC_SATX,
-- read Sprite Attribute Table/N
AC_SATN,
-- read Sprite Attribute Table/C
AC_SATC,
-- read Sprite Pattern Table/high quadrant
AC_SPTH,
-- read Sprite Pattern Table/low quadrant
AC_SPTL,
--
-- CPU access
AC_CPU,
--
-- no access at all
AC_NONE
);
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function enum_to_vec_f
--
-- Purpose:
-- Translate access_t enumeration type to std_logic_vector.
--
function enum_to_vec_f(enum : in access_t) return
std_logic_vector;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_boolean_f
--
-- Purpose:
-- Converts a std_logic value to boolean.
--
function to_boolean_f(val : in std_logic) return boolean;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_std_logic_f
--
-- Purpose:
-- Converts a boolean value to std_logic.
--
function to_std_logic_f(val : in boolean) return std_logic;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function mod_6_f
--
-- Purpose:
-- Calculate the modulo of 6.
-- Only the positive part is considered.
--
function mod_6_f(val : in hv_t) return hv_t;
--
-----------------------------------------------------------------------------
end vdp18_pack;
package body vdp18_pack is
-----------------------------------------------------------------------------
-- Function enum_to_vec_f
--
-- Purpose:
-- Translate access_t enumeration type to std_logic_vector.
--
function enum_to_vec_f(enum : in access_t) return
std_logic_vector is
variable result_v : std_logic_vector(3 downto 0);
begin
case enum is
when AC_NONE =>
result_v := "0000";
when AC_PNT =>
result_v := "0001";
when AC_PGT =>
result_v := "0010";
when AC_PCT =>
result_v := "0011";
when AC_STST =>
result_v := "0100";
when AC_SATY =>
result_v := "0101";
when AC_SATX =>
result_v := "0110";
when AC_SATN =>
result_v := "0111";
when AC_SATC =>
result_v := "1000";
when AC_SPTL =>
result_v := "1001";
when AC_SPTH =>
result_v := "1010";
when AC_CPU =>
result_v := "1111";
when others =>
result_v := "UUUU";
end case;
return result_v;
end;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_boolean_f
--
-- Purpose:
-- Converts a std_logic value to boolean.
--
function to_boolean_f(val : in std_logic) return boolean is
variable result_v : boolean;
begin
case to_X01(val) is
when '1' =>
result_v := true;
when '0' =>
result_v := false;
when others =>
result_v := false;
end case;
return result_v;
end;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function to_std_logic_f
--
-- Purpose:
-- Converts a boolean value to std_logic.
--
function to_std_logic_f(val : in boolean) return std_logic is
variable result_v : std_logic;
begin
case val is
when true =>
result_v := '1';
when false =>
result_v := '0';
end case;
return result_v;
end;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function mod_6_f
--
-- Purpose:
-- Calculate the modulo of 6.
-- Only the positive part is considered.
--
function mod_6_f(val : in hv_t) return hv_t is
variable mod_v : natural;
variable result_v : hv_t;
begin
if val(0) = '0' then
result_v := (others => '0');
mod_v := 0;
for idx in 0 to 255 loop
if val = idx then
result_v := to_signed(mod_v, hv_t'length);
end if;
if mod_v < 5 then
mod_v := mod_v + 1;
else
mod_v := 0;
end if;
end loop;
else
result_v := (others => '-');
end if;
return result_v;
end;
--
-----------------------------------------------------------------------------
end vdp18_pack;
|
gpl-3.0
|
2fce4731c0bc6b4841b543fbbc1e826d
| 0.376347 | 4.679778 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd
| 1 | 15,903 |
-------------------------------------------------------------------------------------
-- FILE NAME : dac3283_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - dac3283_ctrl
-- architecture - dac3283_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the DAC3283 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity dac3283_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end dac3283_ctrl;
architecture dac3283_ctrl_syn of dac3283_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component dac3283_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector := x"0000020";
constant ADDR_MAX_WR : std_logic_vector := x"000001F";
constant ADDR_MAX_RD : std_logic_vector := x"000001F";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(15 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(15 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
gen_serial_clk : if (g_sim = 0) generate
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the rising edge of SCLK.
-- therefore we make sure the external clock is slightly
-- after the internal clock.
sclk_ext <= clk_div(clk_div'length-1);
serial_clk <= sclk_ext;
end if;
end process;
end generate;
-- Do not divide clock. Improve simulation speed.
gen_serial_clk_sim : if (g_sim = 1) generate
serial_clk <= clk;
end generate;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & '0' & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(4 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(4 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
-- Speedup simulation execution
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= sh_counter_gen;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus one data byte;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= '0' & "00" & init_data(12 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(12 downto 8) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= inst_rw & "00" & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
--data_read <= shift_reg(8 downto 1); -- at this stage already one bit has shifted in too much
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
dac3283_init_mem_inst : dac3283_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end dac3283_ctrl_syn;
|
lgpl-3.0
|
6b81ad4b426cfa7fb89832fe2767ea3e
| 0.476451 | 3.687225 | false | false | false | false |
hoglet67/AtomBusMon
|
src/BusMonCore.vhd
| 1 | 25,184 |
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : BusMonCore.vhd
-- /___/ /\ Timestamp : 30/05/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomBusMon
--Device: XC3S250E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
entity BusMonCore is
generic (
num_comparators : integer := 8;
reg_width : integer := 46;
fifo_width : integer := 72;
avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
avr_prog_mem_size : integer := 1024 * 8 -- Default is 8K, 6809 amd Z80 need 9K
);
port (
clock_avr : in std_logic;
busmon_clk : in std_logic;
busmon_clken : in std_logic;
cpu_clk : in std_logic;
cpu_clken : in std_logic;
-- CPU Signals
Addr : in std_logic_vector(15 downto 0);
Data : in std_logic_vector(7 downto 0);
Rd_n : in std_logic;
Wr_n : in std_logic;
RdIO_n : in std_logic;
WrIO_n : in std_logic;
Sync : in std_logic;
Rdy : out std_logic;
nRSTin : in std_logic;
nRSTout : out std_logic;
CountCycle : in std_logic;
-- CPU Registers
-- unused in pure bus monitor mode
Regs : in std_logic_vector(255 downto 0);
-- CPI Specific data
PdcData : in std_logic_vector(7 downto 0) := x"00";
-- CPU Memory Read/Write
-- unused in pure bus monitor mode
RdMemOut : out std_logic;
WrMemOut : out std_logic;
RdIOOut : out std_logic;
WrIOOut : out std_logic;
ExecOut : out std_logic;
AddrOut : out std_logic_vector(15 downto 0);
DataOut : out std_logic_vector(7 downto 0);
DataIn : in std_logic_vector(7 downto 0);
Done : in std_logic;
-- External Interrupt Control
int_ctrl : out std_logic_vector(7 downto 0) := x"00";
-- Single Step interface
SS_Single : out std_logic;
SS_Step : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- AVR Serial Port
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end BusMonCore;
architecture behavioral of BusMonCore is
signal cpu_reset_n : std_logic;
signal nrst_avr : std_logic;
signal nrst1 : std_logic;
signal nrst2 : std_logic;
signal nrst3 : std_logic;
-- debounce time is 2^17 / 16MHz = 8.192ms
signal nrst_counter : unsigned(17 downto 0);
signal dy_counter : std_logic_vector(31 downto 0);
signal dy_data : y2d_type ;
signal mux : std_logic_vector(7 downto 0);
signal muxsel : std_logic_vector(5 downto 0);
signal cmd_edge : std_logic;
signal cmd_edge1 : std_logic;
signal cmd_edge2 : std_logic;
signal cmd_ack : std_logic;
signal cmd_ack1 : std_logic;
signal cmd_ack2 : std_logic;
signal cmd : std_logic_vector(5 downto 0);
signal addr_sync : std_logic_vector(15 downto 0);
signal addr_inst : std_logic_vector(15 downto 0);
signal Addr1 : std_logic_vector(15 downto 0);
signal Data1 : std_logic_vector(7 downto 0);
signal ext_clk : std_logic;
signal timer0Count : std_logic_vector(23 downto 0);
signal timer1Count : std_logic_vector(23 downto 0);
signal cycleCount : std_logic_vector(23 downto 0);
signal instrCount : std_logic_vector(23 downto 0);
signal single : std_logic;
signal reset : std_logic;
signal step : std_logic;
signal bw_status : std_logic_vector(3 downto 0);
signal bw_status1 : std_logic_vector(3 downto 0);
signal auto_inc : std_logic;
signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
signal brkpt_enable : std_logic;
signal brkpt_active : std_logic;
signal brkpt_active1 : std_logic;
signal watch_active : std_logic;
signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_not_empty1 : std_logic;
signal fifo_not_empty2 : std_logic;
signal fifo_rd : std_logic;
signal fifo_rd_en : std_logic;
signal fifo_wr : std_logic;
signal fifo_wr_en : std_logic;
signal fifo_rst : std_logic;
signal memory_rd : std_logic;
signal memory_wr : std_logic;
signal io_rd : std_logic;
signal io_wr : std_logic;
signal exec : std_logic;
signal addr_dout_reg : std_logic_vector(23 downto 0);
signal din_reg : std_logic_vector(7 downto 0);
signal Rdy_int : std_logic;
signal unused_d6 : std_logic;
signal unused_d7 : std_logic;
signal last_done : std_logic;
signal cmd_done : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
signal dropped_counter : std_logic_vector(3 downto 0);
signal timer_mode : std_logic_vector(1 downto 0);
begin
inst_oho_dy1 : entity work.Oho_Dy1 port map (
dy_clock => clock_avr,
dy_rst_n => '1',
dy_data => dy_data,
dy_update => '1',
dy_frame => open,
dy_frameend => open,
dy_frameend_c => open,
dy_pwm => "1010",
dy_counter => dy_counter,
dy_sclk => tdin,
dy_ser => tcclk,
dy_rclk => tmosi
);
Inst_AVR8: entity work.AVR8
generic map(
CDATAMEMSIZE => avr_data_mem_size,
CPROGMEMSIZE => avr_prog_mem_size
)
port map(
clk16M => clock_avr,
nrst => nrst_avr,
portain => PdcData,
portaout => open,
-- Command Port
portbin(0) => '0',
portbin(1) => '0',
portbin(2) => '0',
portbin(3) => '0',
portbin(4) => '0',
portbin(5) => '0',
portbin(6) => '0',
portbin(7) => '0',
portbout(0) => cmd(0),
portbout(1) => cmd(1),
portbout(2) => cmd(2),
portbout(3) => cmd(3),
portbout(4) => cmd(4),
portbout(5) => cmd(5),
portbout(6) => cmd_edge,
portbout(7) => open,
-- Status Port
portdin(0) => '0',
portdin(1) => '0',
portdin(2) => '0',
portdin(3) => '0',
portdin(4) => '0',
portdin(5) => '0',
portdin(6) => cmd_ack2,
portdin(7) => fifo_not_empty2,
portdout(0) => muxsel(0),
portdout(1) => muxsel(1),
portdout(2) => muxsel(2),
portdout(3) => muxsel(3),
portdout(4) => muxsel(4),
portdout(5) => muxsel(5),
portdout(6) => unused_d6,
portdout(7) => unused_d7,
-- Mux Port
portein => mux,
porteout => open,
spi_mosio => open,
spi_scko => open,
spi_misoi => '0',
rxd => avr_RxD,
txd => avr_TxD
);
-- Syncronise signals crossing busmon_clk / clock_avr boundary
process (clock_avr)
begin
if rising_edge(clock_avr) then
fifo_not_empty1 <= not fifo_empty;
fifo_not_empty2 <= fifo_not_empty1;
cmd_ack1 <= cmd_ack;
cmd_ack2 <= cmd_ack1;
end if;
end process;
WatchEvents_inst : entity work.WatchEvents port map(
clk => busmon_clk,
srst => fifo_rst,
din => fifo_din,
wr_en => fifo_wr_en,
rd_en => fifo_rd_en,
dout => fifo_dout,
full => fifo_full,
empty => fifo_empty
);
fifo_wr_en <= fifo_wr and busmon_clken;
fifo_rd_en <= fifo_rd and busmon_clken;
-- The fifo is writen the cycle after the break point
-- Addr1 is the address bus delayed by 1 cycle
-- DataWr1 is the data being written delayed by 1 cycle
-- DataRd is the data being read, that is already one cycle late
-- bw_state1(1) is 1 for writes, and 0 for reads
fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
-- Implement a 4-bit saturating counter of the number of dropped events
process (busmon_clk)
begin
if rising_edge(busmon_clk) then
if busmon_clken = '1' then
if fifo_rst = '1' then
dropped_counter <= x"0";
elsif fifo_wr_en = '1' then
if fifo_full = '1' then
if dropped_counter /= x"F" then
dropped_counter <= dropped_counter + 1;
end if;
else
dropped_counter <= x"0";
end if;
end if;
end if;
end if;
end process;
led_trig0 <= trig(0);
led_trig1 <= trig(1);
led_bkpt <= brkpt_active;
nrst_avr <= not sw_reset_avr;
-- OHO DY1 Display for Testing
dy_data(0) <= hex & "0000" & Addr(3 downto 0);
dy_data(1) <= hex & "0000" & Addr(7 downto 4);
dy_data(2) <= hex & "0000" & "00" & sw_reset_avr & sw_reset_cpu;
mux <= addr_inst(7 downto 0) when muxsel = 0 else
addr_inst(15 downto 8) when muxsel = 1 else
din_reg when muxsel = 2 else
instrCount(23 downto 16) when muxsel = 3 else
instrCount(7 downto 0) when muxsel = 4 else
instrCount(15 downto 8) when muxsel = 5 else
fifo_dout(7 downto 0) when muxsel = 6 else
fifo_dout(15 downto 8) when muxsel = 7 else
fifo_dout(23 downto 16) when muxsel = 8 else
fifo_dout(31 downto 24) when muxsel = 9 else
fifo_dout(39 downto 32) when muxsel = 10 else
fifo_dout(47 downto 40) when muxsel = 11 else
fifo_dout(55 downto 48) when muxsel = 12 else
fifo_dout(63 downto 56) when muxsel = 13 else
fifo_dout(71 downto 64) when muxsel = 14 else
Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0))));
-- Combinatorial set of comparators to decode breakpoint/watch addresses
brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n, trig)
variable i : integer;
variable reg_addr : std_logic_vector(15 downto 0);
variable reg_mask : std_logic_vector(15 downto 0);
variable reg_mode_bmr : std_logic;
variable reg_mode_bmw : std_logic;
variable reg_mode_bir : std_logic;
variable reg_mode_biw : std_logic;
variable reg_mode_bx : std_logic;
variable reg_mode_wmr : std_logic;
variable reg_mode_wmw : std_logic;
variable reg_mode_wir : std_logic;
variable reg_mode_wiw : std_logic;
variable reg_mode_wx : std_logic;
variable reg_mode_all : std_logic_vector(9 downto 0);
variable bactive : std_logic;
variable wactive : std_logic;
variable status : std_logic_vector(3 downto 0);
variable trigval : std_logic;
begin
bactive := '0';
wactive := '0';
status := (others => '0');
if (brkpt_enable = '1') then
for i in 0 to num_comparators - 1 loop
reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
reg_mask := brkpt_reg(i * reg_width + 31 downto i * reg_width + 16);
reg_mode_bmr := brkpt_reg(i * reg_width + 32);
reg_mode_wmr := brkpt_reg(i * reg_width + 33);
reg_mode_bmw := brkpt_reg(i * reg_width + 34);
reg_mode_wmw := brkpt_reg(i * reg_width + 35);
reg_mode_bir := brkpt_reg(i * reg_width + 36);
reg_mode_wir := brkpt_reg(i * reg_width + 37);
reg_mode_biw := brkpt_reg(i * reg_width + 38);
reg_mode_wiw := brkpt_reg(i * reg_width + 39);
reg_mode_bx := brkpt_reg(i * reg_width + 40);
reg_mode_wx := brkpt_reg(i * reg_width + 41);
reg_mode_all := brkpt_reg(i * reg_width + 41 downto i * reg_width + 32);
trigval := brkpt_reg(i * reg_width + 42 + to_integer(unsigned(trig)));
if (trigval = '1' and ((Addr and reg_mask) = reg_addr or (reg_mode_all = "0000000000"))) then
if (Sync = '1') then
if (reg_mode_bx = '1') then
bactive := '1';
status := "1000";
elsif (reg_mode_wx = '1') then
wactive := '1';
status := "1001";
end if;
elsif (Rd_n = '0') then
if (reg_mode_bmr = '1') then
bactive := '1';
status := "0000";
elsif (reg_mode_wmr = '1') then
wactive := '1';
status := "0001";
end if;
elsif (Wr_n = '0') then
if (reg_mode_bmw = '1') then
bactive := '1';
status := "0010";
elsif (reg_mode_wmw = '1') then
wactive := '1';
status := "0011";
end if;
elsif (RdIO_n = '0') then
if (reg_mode_bir = '1') then
bactive := '1';
status := "0100";
elsif (reg_mode_wir = '1') then
wactive := '1';
status := "0101";
end if;
elsif (WrIO_n = '0') then
if (reg_mode_biw = '1') then
bactive := '1';
status := "0110";
elsif (reg_mode_wiw = '1') then
wactive := '1';
status := "0111";
end if;
end if;
end if;
end loop;
end if;
watch_active <= wactive;
brkpt_active <= bactive;
bw_status <= status;
end process;
-- CPU Control Commands
-- 00000x Enable/Disable single stepping
-- 00001x Enable/Disable breakpoints / watches
-- 00010x Load breakpoint / watch register
-- 00011x Reset CPU
-- 001000 Singe Step CPU
-- 001001 Read FIFO
-- 001010 Reset FIFO
-- 001011 Unused
-- 00110x Load address/data register
-- 00111x Unused
-- 010000 Read Memory
-- 010001 Read Memory and Auto Inc Address
-- 010010 Write Memory
-- 010011 Write Memory and Auto Inc Address
-- 010100 Read IO
-- 010101 Read IO and Auto Inc Address
-- 010110 Write IO
-- 010111 Write IO and Auto Inc Address
-- 011000 Execute 6502 instruction
-- 0111xx Unused
-- 011x1x Unused
-- 011xx1 Unused
-- 10xxxx Int Ctrl
-- 1100xx Timer Mode
-- 00 - count cpu cycles where clken = 1 and CountCycle = 1
-- 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
-- 10 - free running timer, using busmon_clk as the source
-- 11 - free running timer, using trig0 as the source
-- Use trig0 to drive a free running counter for absolute timings
ext_clk <= trig(0);
timer1Process: process (ext_clk)
begin
if rising_edge(ext_clk) then
timer1Count <= timer1Count + 1;
end if;
end process;
cpuProcess: process (busmon_clk)
begin
if rising_edge(busmon_clk) then
timer0Count <= timer0Count + 1;
if busmon_clken = '1' then
-- Cycle counter
if (cpu_reset_n = '0') then
cycleCount <= (others => '0');
elsif (CountCycle = '1' or timer_mode(0) = '1') then
cycleCount <= cycleCount + 1;
end if;
-- Command processing
cmd_edge1 <= cmd_edge;
cmd_edge2 <= cmd_edge1;
fifo_rd <= '0';
fifo_wr <= '0';
fifo_rst <= '0';
memory_rd <= '0';
memory_wr <= '0';
io_rd <= '0';
io_wr <= '0';
exec <= '0';
SS_Step <= '0';
if (cmd_edge2 /= cmd_edge1) then
if (cmd(5 downto 1) = "00000") then
single <= cmd(0);
end if;
if (cmd(5 downto 1) = "00001") then
brkpt_enable <= cmd(0);
end if;
if (cmd(5 downto 1) = "00010") then
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
end if;
if (cmd(5 downto 1) = "00110") then
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
end if;
if (cmd(5 downto 1) = "00011") then
reset <= cmd(0);
end if;
if (cmd(5 downto 0) = "01001") then
fifo_rd <= '1';
end if;
if (cmd(5 downto 0) = "01010") then
fifo_rst <= '1';
end if;
if (cmd(5 downto 1) = "01000") then
memory_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01001") then
memory_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01010") then
io_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01011") then
io_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 0) = "011000") then
exec <= '1';
end if;
if (cmd(5 downto 4) = "10") then
int_ctrl(to_integer(unsigned(cmd(3 downto 2))) * 2 + 1 downto to_integer(unsigned(cmd(3 downto 2))) * 2) <= cmd(1 downto 0);
end if;
if (cmd(5 downto 2) = "1100") then
timer_mode <= cmd(1 downto 0);
end if;
-- Acknowlege certain commands immediately
if cmd(5 downto 4) /= "01" then
cmd_ack <= not cmd_ack;
end if;
end if;
if cmd_done = '1' then
-- Acknowlege memory access commands when thet complete
cmd_ack <= not cmd_ack;
-- Auto increment the memory address reg the cycle after a rd/wr
if auto_inc = '1' then
addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
end if;
end if;
-- Single Stepping
if (brkpt_active = '1') then
single <= '1';
end if;
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
Rdy_int <= (not brkpt_active);
SS_Step <= (not brkpt_active);
else
Rdy_int <= (not Sync);
end if;
-- Latch instruction address for the whole cycle
if (Sync = '1') then
addr_inst <= Addr;
if timer_mode = "10" then
instrCount <= timer0Count;
elsif timer_mode = "11" then
instrCount <= timer1Count;
else
instrCount <= cycleCount;
end if;
end if;
-- Breakpoints and Watches written to the FIFO
brkpt_active1 <= brkpt_active;
bw_status1 <= bw_status;
if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then
fifo_wr <= '1';
Addr1 <= Addr;
end if;
end if;
end if;
end process;
dataProcess: process (cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
-- Latch the data bus for use in watches
Data1 <= Data;
-- Latch memory read in response to a read command
if (Done = '1') then
din_reg <= DataIn;
end if;
-- Delay the increnting of the address by one cycle
last_done <= Done;
if Done = '1' and last_done = '0' then
cmd_done <= '1';
else
cmd_done <= '0';
end if;
end if;
end if;
end process;
Rdy <= Rdy_int;
RdMemOut <= memory_rd;
WrMemOut <= memory_wr;
RdIOOut <= io_rd;
WrIOOut <= io_wr;
AddrOut <= addr_dout_reg(23 downto 8);
DataOut <= addr_dout_reg(7 downto 0);
SS_Single <= single;
ExecOut <= exec;
-- Reset Logic
-- Generate a short (~1ms @ 1MHz) power up reset pulse
--
-- This is in case FPGA configuration takes longer than
-- the length of the host system reset pulse.
--
-- Some 6502 cores (particularly the AlanD core) needs
-- reset to be asserted to start.
-- Debounce nRSTin using clock_avr as this is always 16MHz
-- nrst1 is the possibly glitchy input
-- nrst2 is the filtered output
process(clock_avr)
begin
if rising_edge(clock_avr) then
-- Syncronise nRSTin
nrst1 <= nRSTin and (not sw_reset_cpu);
-- De-glitch NRST
if nrst1 = '0' then
nrst_counter <= to_unsigned(0, nrst_counter'length);
nrst2 <= '0';
elsif nrst_counter(nrst_counter'high) = '0' then
nrst_counter <= nrst_counter + 1;
else
nrst2 <= '1';
end if;
end if;
end process;
process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
if reset_counter(reset_counter'high) = '0' then
reset_counter <= reset_counter + 1;
end if;
nrst3 <= nrst2 and reset_counter(reset_counter'high) and (not reset);
cpu_reset_n <= nrst3;
end if;
end if;
end process;
nRSTout <= cpu_reset_n;
end behavioral;
|
gpl-3.0
|
b2bb14e656e6f575c08558dc455fb252
| 0.449571 | 4.087648 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/v6abb64Package_efifo_elink.vhd
| 1 | 31,562 |
-- -------------------------------------------------------------
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- Nov 2008 --> 64-bit
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
package abb64Package is
-- Implemet a design with only one FIFO and only one BRAM Module: For Loopback Test!!
constant USE_LOOPBACK_TEST : boolean := false;
-- Declare constants
-- ----------------------------------------------------------------------
-- Address definitions
-- The 2 MSB's are for Addressing, i.e.
--
-- 0x0000 : Design ID
-- 0x0008 : Interrupt status
-- 0x0010 : Interrupt enable
-- 0x0018 : General error
-- 0x001C : DDR SDRAM address page
-- 0x0020 : General status
-- 0x0024 : Wishbone address page
-- 0x0028 : General control
-- 0x002C ~ 0x004C: DMA upstream registers
-- 0x0050 ~ 0x0070: DMA upstream registers
-- 0x0074 : MRd channel control
-- 0x0078 : CplD channel control
-- 0x007C : ICAP input/output
-- 0x0080 ~ 0x008C: Interrupt Generator (IG) registers
-- 0x4010 : TxFIFO write port
-- 0x4018 : W - TxFIFO Reset
-- : R - TxFIFO Vacancy status
-- 0x4020 : RxFIFO read port
-- 0x4028 : W - RxFIFO Reset
-- : R - RxFIFO Occupancy status
-- 0x8000 ~ 0xBFFF: BRAM space (BAR1)
-- Others : Reserved
------------------------------------------------------------------------
-- Global Constants
--
--- Data bus width
constant C_DBUS_WIDTH : integer := 64;
constant C_DATA_WIDTH : integer := C_DBUS_WIDTH;
--- Event Buffer: FIFO Data Count width
constant C_FIFO_DC_WIDTH : integer := 26;
--- Address width for endpoint device/peripheral
--
constant C_EP_AWIDTH : integer range 10 to 30 := 10;
--- Buffer width from the PCIe Core
constant C_TBUF_AWIDTH : integer := 6; -- 4; -- 5;
--- Width for Tx output Arbitration
constant C_ARBITRATE_WIDTH : integer := 4;
--- Number of BAR spaces
constant CINT_BAR_SPACES : integer := 6;
--- Max BAR number, 7
constant C_BAR_NUMBER : integer := 7;
--- Encoded BAR number takes 3 bits to represent 0~6. 7 means invalid or don't care
constant C_ENCODE_BAR_NUMBER : integer := 3;
--- Number of Channels, currently 4: Interrupt, PIO MRd, upstream DMA, downstream DMA
constant C_CHANNEL_NUMBER : integer := 4;
--- Data width of the channel buffers (FIFOs)
constant C_CHANNEL_BUF_WIDTH : integer := 128;
--- Higher 4 bits are for tag decoding
constant C_TAG_DECODE_BITS : integer := 4;
--- DDR SDRAM bank address pin number
constant C_DDR_BANK_AWIDTH : integer := 2;
--- DDR SDRAM address pin number
constant C_DDR_AWIDTH : integer := 13;
--- DDR SDRAM data pin number
constant C_DDR_DWIDTH : integer := 16;
--- DDR SDRAM module address width, dependent on total DDR memory capacity.
-- 128 Mb= 16MB : 24
-- 256 Mb= 32MB : 25
-- 512 Mb= 64MB : 26
-- 1024 Mb= 128MB : 27
-- 2048 Mb= 256MB : 28
-- 4096 Mb= 512MB : 29
-- 8192 Mb= 1024MB : 30
-- 16384 Mb= 2048MB : 31
-- 32768 Mb= 4096MB : 32
constant C_DDR_IAWIDTH : integer range 24 to 32 := 30;
--- Block RAM address bus width. Variation requires BRAM core regeneration.
constant C_PRAM_AWIDTH : integer range 8 to 29 := 29;
-- Wishbone endpoint address width
constant C_WB_AWIDTH : integer range 24 to 31 := 31;
-- DDR SDRAM page address width
constant C_DDR_PG_WIDTH : integer range 0 to 30 := 20;
-- Wishbone endpoint page address width
constant C_WB_PG_WIDTH : integer range 0 to 30 := 19;
--- Width for Interrupt generation counter
constant C_CNT_GINT_WIDTH : integer := 30;
--- Tag RAM data bus width, 1 bit for AInc information and 3 bits for BAR number
constant C_TAGRAM_DWIDTH : integer := 36;
--- Configuration command width, e.g. cfg_dcommand, cfg_lcommand.
constant C_CFG_COMMAND_DWIDTH : integer := 16;
--- Tag RAM address bus width, only 6 bits (of 8) are used for MRd from DMA Write Channel
constant C_TAGRAM_AWIDTH : integer := 6;
constant C_TAG_MAP_WIDTH : integer := 64; -- 2^C_TAGRAM_AWIDTH
-- TAG map are partitioned into sub-parts
constant C_SUB_TAG_MAP_WIDTH : integer := 8;
--- Address_Increment bit is put in tag RAM
constant CBIT_AINC_IN_TAGRAM : integer := C_TAGRAM_DWIDTH-1;
-- Bit range of BAR field in TAG ram
constant C_TAGBAR_BIT_TOP : integer := CBIT_AINC_IN_TAGRAM-1;
constant C_TAGBAR_BIT_BOT : integer := C_TAGBAR_BIT_TOP-C_ENCODE_BAR_NUMBER+1;
--- Feature Bits width
constant C_FEAT_BITS_WIDTH : integer := 8;
--- Channel lables
constant C_CHAN_INDEX_IRPT : integer := 3;
constant C_CHAN_INDEX_MRD : integer := 2;
constant C_CHAN_INDEX_DMA_DS : integer := 1;
constant C_CHAN_INDEX_DMA_US : integer := 0;
------------------------------------------------------------------------
-- Bit ranges
-- Bits range for Max_Read_Request_Size in cfg_dcommand
constant C_CFG_MRS_BIT_TOP : integer := 14;
constant C_CFG_MRS_BIT_BOT : integer := 12;
-- Bits range for Max_Payload_Size in cfg_dcommand
constant C_CFG_MPS_BIT_TOP : integer := 7;
constant C_CFG_MPS_BIT_BOT : integer := 5;
-- The bit in minimum Max_Read_Request_Size/Max_Payload_Size that is one
-- i.e. 0x80 Bytes = 0x20 DW = "000000100000"
constant CBIT_SENSE_OF_MAXSIZE : integer := 5;
-- ------------------------------------------------------------------------
--
-- Section for TLP headers' bit definition
-- ( not shown in user header file)
--
-- ------------------------------------------------------------------------
-- -- The bit in TLP header #0 that means whether the TLP comes with data
-- Constant CBIT_TLP_HAS_PAYLOAD : integer := 30;
-- -- The bit in TLP header #0 that means whether the TLP has 4-DW header
-- Constant CBIT_TLP_HAS_4DW_HEAD : integer := 29;
-- -- The bit in TLP header #0 that means Cpl/CplD
-- Constant C_TLP_CPLD_BIT : integer := 27;
-- The bit in TLP header #0 that means TLP Digest
constant C_TLP_TD_BIT : integer := 15;
-- The bit in TLP header #0 that means Error Poison
constant C_TLP_EP_BIT : integer := 14;
-- Bit range of Format field in TLP header #0
constant C_TLP_FMT_BIT_TOP : integer := 30; -- TLP has payload
constant C_TLP_FMT_BIT_BOT : integer := 29; -- TLP header has 4 DW
-- Bit range of Type field in TLP header #0
constant C_TLP_TYPE_BIT_TOP : integer := 28;
constant C_TLP_TYPE_BIT_BOT : integer := 24;
-- Bit range of TC field in TLP header #0
constant C_TLP_TC_BIT_TOP : integer := 22;
constant C_TLP_TC_BIT_BOT : integer := 20;
-- Bit range of Attribute field in TLP header #0
constant C_TLP_ATTR_BIT_TOP : integer := 13;
constant C_TLP_ATTR_BIT_BOT : integer := 12;
-- Bit range of Length field in TLP header #0
constant C_TLP_LENG_BIT_TOP : integer := 9;
constant C_TLP_LENG_BIT_BOT : integer := 0;
-- Bit range of Requester ID field in header #1 of non-Cpl/D TLP
constant C_TLP_REQID_BIT_TOP : integer := 31+32;
constant C_TLP_REQID_BIT_BOT : integer := 16+32;
-- Bit range of Tag field in header #1 of non-Cpl/D TLP
constant C_TLP_TAG_BIT_TOP : integer := 15+32;
constant C_TLP_TAG_BIT_BOT : integer := 8+32;
-- Bit range of Last BE field in TLP header #1
constant C_TLP_LAST_BE_BIT_TOP : integer := 7+32;
constant C_TLP_LAST_BE_BIT_BOT : integer := 4+32;
-- Bit range of 1st BE field in TLP header #1
constant C_TLP_1ST_BE_BIT_TOP : integer := 3+32;
constant C_TLP_1ST_BE_BIT_BOT : integer := 0+32;
-- Bit range of Completion Status field in Cpl/D TLP header #1
constant C_CPLD_CS_BIT_TOP : integer := 15+32;
constant C_CPLD_CS_BIT_BOT : integer := 13+32;
-- Bit range of Completion Byte Count field in Cpl/D TLP header #1
constant C_CPLD_BC_BIT_TOP : integer := 11+32;
constant C_CPLD_BC_BIT_BOT : integer := 0+32;
-- Bit range of Completer ID field in header#1 of Cpl/D TLP
constant C_CPLD_CPLT_ID_BIT_TOP : integer := C_TLP_REQID_BIT_TOP;
constant C_CPLD_CPLT_ID_BIT_BOT : integer := C_TLP_REQID_BIT_BOT;
-- Bit range of Requester ID field in header#2 of Cpl/D TLP
constant C_CPLD_REQID_BIT_TOP : integer := 31;
constant C_CPLD_REQID_BIT_BOT : integer := 16;
-- Bit range of Completion Tag field in Cpl/D TLP 3rd header
constant C_CPLD_TAG_BIT_TOP : integer := 15;
constant C_CPLD_TAG_BIT_BOT : integer := 8;
-- Bit range of Completion Lower Address field in Cpl/D TLP 3rd header
constant C_CPLD_LA_BIT_TOP : integer := 6;
constant C_CPLD_LA_BIT_BOT : integer := 0;
-- Bit range of Message Code field in Msg 2nd header
constant C_MSG_CODE_BIT_TOP : integer := 7+32;
constant C_MSG_CODE_BIT_BOT : integer := 0+32;
-- ----------------------------------------------------------------------
-- TLP field widths
-- For PCIe, the length field is 10 bits wide.
constant C_TLP_FLD_WIDTH_OF_LENG : integer := C_TLP_LENG_BIT_TOP-C_TLP_LENG_BIT_BOT+1;
------------------------------------------------------------------------
--- Tag width in TLP
constant C_TAG_WIDTH : integer := C_TLP_TAG_BIT_TOP-C_TLP_TAG_BIT_BOT+1;
------------------------------------------------------------------------
--- Width for Local ID
constant C_ID_WIDTH : integer := C_TLP_REQID_BIT_TOP-C_TLP_REQID_BIT_BOT+1;
------------------------------------------------------------------------
--- Width for Requester ID
constant C_REQID_WIDTH : integer := C_TLP_REQID_BIT_TOP-C_TLP_REQID_BIT_BOT+1;
-- ------------------------------------------------------------------------
-- Section for Channel Buffer bit definition, referenced to TLP header definition
-- ( not shown in user header file)
--
-- ------------------------------------------------------------------------
-- Bit range of Length field in Channel Buffer word
constant C_CHBUF_LENG_BIT_BOT : integer := 0;
constant C_CHBUF_LENG_BIT_TOP : integer := C_CHBUF_LENG_BIT_BOT+C_TLP_FLD_WIDTH_OF_LENG-1; -- 9
-- Bit range of Attribute field in Channel Buffer word
constant C_CHBUF_ATTR_BIT_BOT : integer := C_CHBUF_LENG_BIT_TOP+1; --10;
constant C_CHBUF_ATTR_BIT_TOP : integer := C_CHBUF_ATTR_BIT_BOT+C_TLP_ATTR_BIT_TOP-C_TLP_ATTR_BIT_BOT; --11;
-- The bit in Channel Buffer word that means Error Poison
constant C_CHBUF_EP_BIT : integer := C_CHBUF_ATTR_BIT_TOP+1; --12;
-- The bit in Channel Buffer word that means TLP Digest
constant C_CHBUF_TD_BIT : integer := C_CHBUF_EP_BIT+1; --13;
-- Bit range of TC field in Channel Buffer word
constant C_CHBUF_TC_BIT_BOT : integer := C_CHBUF_TD_BIT+1; --14;
constant C_CHBUF_TC_BIT_TOP : integer := C_CHBUF_TC_BIT_BOT+C_TLP_TC_BIT_TOP-C_TLP_TC_BIT_BOT; --16;
-- Bit range of Format field in Channel Buffer word
constant C_CHBUF_FMT_BIT_BOT : integer := C_CHBUF_TC_BIT_TOP+1; --17;
constant C_CHBUF_FMT_BIT_TOP : integer := C_CHBUF_FMT_BIT_BOT+C_TLP_FMT_BIT_TOP-C_TLP_FMT_BIT_BOT; --18;
-- Bit range of Tag field in Channel Buffer word except Cpl/D
constant C_CHBUF_TAG_BIT_BOT : integer := C_CHBUF_FMT_BIT_TOP+1; --19;
constant C_CHBUF_TAG_BIT_TOP : integer := C_CHBUF_TAG_BIT_BOT+C_TLP_TAG_BIT_TOP-C_TLP_TAG_BIT_BOT; --26;
-- Bit range of BAR Index field in upstream DMA Channel Buffer word
constant C_CHBUF_DMA_BAR_BIT_BOT : integer := C_CHBUF_TAG_BIT_TOP+1; --27;
constant C_CHBUF_DMA_BAR_BIT_TOP : integer := C_CHBUF_DMA_BAR_BIT_BOT+C_ENCODE_BAR_NUMBER-1; --29;
-- Bit range of Message Code field in Channel Buffer word for Msg
constant C_CHBUF_MSG_CODE_BIT_BOT : integer := C_CHBUF_TAG_BIT_TOP+1; --27;
constant C_CHBUF_MSG_CODE_BIT_TOP : integer := C_CHBUF_MSG_CODE_BIT_BOT+C_MSG_CODE_BIT_TOP-C_MSG_CODE_BIT_BOT; --34;
-- Bit range of remaining Byte Count field in Cpl/D Channel Buffer word
constant C_CHBUF_CPLD_BC_BIT_BOT : integer := C_CHBUF_FMT_BIT_TOP+1; --19;
constant C_CHBUF_CPLD_BC_BIT_TOP : integer := C_CHBUF_CPLD_BC_BIT_BOT+C_TLP_FLD_WIDTH_OF_LENG-1+2; --30;
-- Bit range of Completion Status field in Cpl/D Channel Buffer word
constant C_CHBUF_CPLD_CS_BIT_BOT : integer := C_CHBUF_CPLD_BC_BIT_TOP+1; --31;
constant C_CHBUF_CPLD_CS_BIT_TOP : integer := C_CHBUF_CPLD_CS_BIT_BOT+C_CPLD_CS_BIT_TOP-C_CPLD_CS_BIT_BOT; --33;
-- Bit range of Lower Address field in Cpl/D Channel Buffer word
constant C_CHBUF_CPLD_LA_BIT_BOT : integer := C_CHBUF_CPLD_CS_BIT_TOP+1; --34;
constant C_CHBUF_CPLD_LA_BIT_TOP : integer := C_CHBUF_CPLD_LA_BIT_BOT+C_CPLD_LA_BIT_TOP-C_CPLD_LA_BIT_BOT; --40;
-- Bit range of Tag field in Cpl/D Channel Buffer word
constant C_CHBUF_CPLD_TAG_BIT_BOT : integer := C_CHBUF_CPLD_LA_BIT_TOP+1; --41;
constant C_CHBUF_CPLD_TAG_BIT_TOP : integer := C_CHBUF_CPLD_TAG_BIT_BOT+C_CPLD_TAG_BIT_TOP-C_CPLD_TAG_BIT_BOT; --48;
-- Bit range of Requester ID field in Cpl/D Channel Buffer word
constant C_CHBUF_CPLD_REQID_BIT_BOT : integer := C_CHBUF_CPLD_TAG_BIT_TOP+1; --49;
constant C_CHBUF_CPLD_REQID_BIT_TOP : integer := C_CHBUF_CPLD_REQID_BIT_BOT+C_CPLD_REQID_BIT_TOP-C_CPLD_REQID_BIT_BOT; --64;
-- Bit range of BAR Index field in Cpl/D Channel Buffer word
constant C_CHBUF_CPLD_BAR_BIT_BOT : integer := C_CHBUF_CPLD_REQID_BIT_TOP+1; --65;
constant C_CHBUF_CPLD_BAR_BIT_TOP : integer := C_CHBUF_CPLD_BAR_BIT_BOT+C_ENCODE_BAR_NUMBER-1; --67;
-- Bit range of host address in Channel Buffer word
constant C_CHBUF_HA_BIT_BOT : integer := C_CHBUF_DMA_BAR_BIT_TOP+1; --30;
-- Constant C_CHBUF_HA_BIT_TOP : integer := C_CHBUF_HA_BIT_BOT+2*C_DBUS_WIDTH-1; --93;
constant C_CHBUF_HA_BIT_TOP : integer := C_CHBUF_HA_BIT_BOT+C_DBUS_WIDTH-1; --93;
-- The bit in Channel Buffer word that means whether this TLP is valid for output arbitration
-- (against channel buffer reset during arbitration)
constant C_CHBUF_QVALID_BIT : integer := C_CHBUF_HA_BIT_TOP+1; --94;
-- The bit in Channel Buffer word that means address increment
constant C_CHBUF_AINC_BIT : integer := C_CHBUF_QVALID_BIT+1; --95;
-- The bit in Channel Buffer word that means zero-length
constant C_CHBUF_0LENG_BIT : integer := C_CHBUF_AINC_BIT+1; --96;
-- Bit range of peripheral address in Channel Buffer word
constant C_CHBUF_PA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_EP_AWIDTH; --118;
constant C_CHBUF_PA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of BRAM address in Channel Buffer word
constant C_CHBUF_MA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_PRAM_AWIDTH-2; --97;
constant C_CHBUF_MA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of DDR address in Channel Buffer word
constant C_CHBUF_DDA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_DDR_IAWIDTH; --102;
constant C_CHBUF_DDA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of Wishbone address in Channel Buffer word
constant C_CHBUF_WB_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_WB_AWIDTH; --97;
constant C_CHBUF_WB_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
------------------------------------------------------------------------
-- The Relaxed Ordering bit constant in TLP
constant C_RELAXED_ORDERING : std_logic := '0';
-- The NO SNOOP bit constant in TLP
constant C_NO_SNOOP : std_logic := '0'; -- '1';
-- AK, 2007-11-07: SNOOP-bit corrupts DMA, if set on INTEL platform. Seems to be don't care on AMD
------------------------------------------------------------------------
-- TLP resolution concerning Format
constant C_FMT3_NO_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) := "00";
constant C_FMT3_WITH_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) := "10";
constant C_FMT4_NO_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) := "01";
constant C_FMT4_WITH_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) := "11";
-- TLP resolution concerning Type
constant C_TYPE_MEM_REQ : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "00000";
constant C_TYPE_IO_REQ : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "00010";
constant C_TYPE_MEM_REQ_LK : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "00001";
constant C_TYPE_COMPLETION : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "01010";
constant C_TYPE_COMPLETION_LK : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "01011";
constant C_TYPE_MSG_TO_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "10000";
constant C_TYPE_MSG_BY_ADDRESS : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "10001";
constant C_TYPE_MSG_BY_ID : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "10010";
constant C_TYPE_MSG_FROM_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "10011";
constant C_TYPE_MSG_LOCAL : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "10100";
constant C_TYPE_MSG_GATHER_TO_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := "10101";
-- Select this constant to test system response
constant C_TYPE_OF_MSG : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) := C_TYPE_MSG_LOCAL; -- C_TYPE_MSG_TO_ROOT;
------------------------------------------------------------------------
-- Lowest priority for Tx_Output_Arbitration module
constant C_LOWEST_PRIORITY : std_logic_vector (C_ARBITRATE_WIDTH-1 downto 0) := (0 => '1', others => '0');
------------------------------------------------------------------------
constant C_DECODE_BIT_TOP : integer := C_EP_AWIDTH-1; -- 9;
constant C_DECODE_BIT_BOT : integer := C_DECODE_BIT_TOP-1; -- 8;
------------------------------------------------------------------------
-- Current buffer descriptor length is 8 DW.
constant C_NEXT_BD_LENGTH : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
:= CONV_STD_LOGIC_VECTOR(8*4, C_TLP_FLD_WIDTH_OF_LENG+2);
-- Maximum 8 DW for the CplD carrying next BDA
constant C_NEXT_BD_LENG_MSB : integer := 3;
------------------------------------------------------------------------
-- To determine the max.size parameters, 6 bits are used.
constant C_MAXSIZE_FLD_BIT_TOP : integer := C_TLP_FLD_WIDTH_OF_LENG +2;
constant C_MAXSIZE_FLD_BIT_BOT : integer := 7;
------------------------------------------------------------------------
-- Time-out counter width
constant C_TOUT_WIDTH : integer := 32;
-- Bottom bit for determining time-out
constant CBIT_TOUT_BOT : integer := 16;
-- Time-out value
constant C_TIME_OUT_VALUE : std_logic_vector(C_TOUT_WIDTH-1 downto CBIT_TOUT_BOT) := (24 => '1', others => '0');
-- := (OTHERS=>'1' ); -- Maximum value (-1)
----------------------------------------------------------------------------------
constant C_REGS_BASE_ADDR : std_logic_vector(C_EP_AWIDTH-1 downto 0) := (C_DECODE_BIT_TOP => '0', C_DECODE_BIT_BOT => '0', others => '0');
----------------------------------------------------------------------------------
constant CINT_REGS_SPACE_BAR : integer := 0;
constant CINT_FIFO_SPACE_BAR : integer := 4;
constant CINT_DDR_SPACE_BAR : integer := 2;
------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- 1st word of MRd, for requesting the next descriptor
-- Constant C_MRD_HEAD0_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
-- := X"80000000";
constant C_TLP_HAS_NO_DATA : std_logic := '0';
------------------------------------------------------------------------
constant C_TLP_TYPE_IS_MRD_H3 : std_logic_vector(3 downto 0) := "1000";
constant C_TLP_TYPE_IS_MRDLK_H3 : std_logic_vector(3 downto 0) := "0100";
constant C_TLP_TYPE_IS_MRD_H4 : std_logic_vector(3 downto 0) := "0010";
constant C_TLP_TYPE_IS_MRDLK_H4 : std_logic_vector(3 downto 0) := "0001";
constant C_TLP_TYPE_IS_MWR_H3 : std_logic_vector(1 downto 0) := "10";
constant C_TLP_TYPE_IS_MWR_H4 : std_logic_vector(1 downto 0) := "01";
constant C_TLP_TYPE_IS_CPLD : std_logic_vector(3 downto 0) := "1000";
constant C_TLP_TYPE_IS_CPL : std_logic_vector(3 downto 0) := "0100";
constant C_TLP_TYPE_IS_CPLDLK : std_logic_vector(3 downto 0) := "0010";
constant C_TLP_TYPE_IS_CPLLK : std_logic_vector(3 downto 0) := "0001";
------------------------------------------------------------------------
-- Maximal number of Interrupts
constant C_NUM_OF_INTERRUPTS : integer := 16;
------------------------------------------------------------------------
-- Minimal register set
constant CINT_ADDR_VERSION : integer := 0;
constant CINT_ADDR_IRQ_STAT : integer := 2;
-- IRQ Enable. Write '1' turns on the interrupt, '0' masks.
constant CINT_ADDR_IRQ_EN : integer := 4;
constant CINT_ADDR_ERROR : integer := 6; -- unused
constant CINT_ADDR_SDRAM_PG : integer := 7;
constant CINT_ADDR_STATUS : integer := 8;
constant CINT_ADDR_WB_PG : integer := 9;
constant CINT_ADDR_CONTROL : integer := 10;
-- Upstream DMA channel Constants
constant CINT_ADDR_DMA_US_PAH : integer := 11;
constant CINT_ADDR_DMA_US_PAL : integer := 12;
constant CINT_ADDR_DMA_US_HAH : integer := 13;
constant CINT_ADDR_DMA_US_HAL : integer := 14;
constant CINT_ADDR_DMA_US_BDAH : integer := 15;
constant CINT_ADDR_DMA_US_BDAL : integer := 16;
constant CINT_ADDR_DMA_US_LENG : integer := 17;
constant CINT_ADDR_DMA_US_CTRL : integer := 18;
constant CINT_ADDR_DMA_US_STA : integer := 19;
-- Downstream DMA channel Constants
constant CINT_ADDR_DMA_DS_PAH : integer := 20;
constant CINT_ADDR_DMA_DS_PAL : integer := 21;
constant CINT_ADDR_DMA_DS_HAH : integer := 22;
constant CINT_ADDR_DMA_DS_HAL : integer := 23;
constant CINT_ADDR_DMA_DS_BDAH : integer := 24;
constant CINT_ADDR_DMA_DS_BDAL : integer := 25;
constant CINT_ADDR_DMA_DS_LENG : integer := 26;
constant CINT_ADDR_DMA_DS_CTRL : integer := 27;
constant CINT_ADDR_DMA_DS_STA : integer := 28;
-------- Address for MRd channel control
constant CINT_ADDR_MRD_CTRL : integer := 29;
-------- Address for Tx module control
constant CINT_ADDR_TX_CTRL : integer := 30;
-------- Address of Interrupt Generator Control (W)
constant CINT_ADDR_IG_CONTROL : integer := 32;
-------- Address of Interrupt Generator Latency (W+R)
constant CINT_ADDR_IG_LATENCY : integer := 33;
-------- Address of Interrupt Generator Assert Number (R)
constant CINT_ADDR_IG_NUM_ASSERT : integer := 34;
-------- Address of Interrupt Generator Deassert Number (R)
constant CINT_ADDR_IG_NUM_DEASSERT : integer := 35;
-------- Event Buffer FIFO status (R) + control (W)
constant CINT_ADDR_EB_STACON : integer := 36;
-------- Upstream DMA transferred byte count (R)
constant CINT_ADDR_US_TRANSF_BC : integer := 37;
-------- Downstream DMA transferred byte count (R)
constant CINT_ADDR_DS_TRANSF_BC : integer := 38;
------------------------------------------------------------------------
-- Number of registers
constant C_NUM_OF_ADDRESSES : integer := 39;
--
------------------------------------------------------------------------
-- ----------------------------------------------------------------------
-- Bit definitions of the Control register for DMA channels
--
constant CINT_BIT_DMA_CTRL_VALID : integer := 25;
constant CINT_BIT_DMA_CTRL_LAST : integer := 24;
constant CINT_BIT_DMA_CTRL_UPA : integer := 20;
constant CINT_BIT_DMA_CTRL_AINC : integer := 15;
constant CINT_BIT_DMA_CTRL_END : integer := 08;
-- Bit range of BAR field in DMA Control register
constant CINT_BIT_DMA_CTRL_BAR_TOP : integer := 18;
constant CINT_BIT_DMA_CTRL_BAR_BOT : integer := 16;
-- Default DMA Control register value
-- Constant C_DEF_DMA_CTRL_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
constant C_DEF_DMA_CTRL_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0) := (CINT_BIT_DMA_CTRL_VALID => '1',
CINT_BIT_DMA_CTRL_END => '1' , others => '0');
------------------------------------------------------------------------
constant C_CHANNEL_RST_BITS : std_logic_vector(C_FEAT_BITS_WIDTH-1 downto 0) := X"0A";
------------------------------------------------------------------------
constant C_HOST_ICLR_BITS : std_logic_vector(C_FEAT_BITS_WIDTH-1 downto 0) := X"F0";
----------------------------------------------------------------------------------
-- Initial MWr Tag for upstream DMA
constant C_TAG0_DMA_US_MWR : std_logic_vector(C_TAG_WIDTH-1 downto 0) := X"D0";
-- Initial MRd Tag for upstream DMA descriptor
constant C_TAG0_DMA_USB : std_logic_vector(C_TAG_WIDTH-1 downto 0) := X"E0";
-- Initial MRd Tag for downstream DMA descriptor
constant C_TAG0_DMA_DSB : std_logic_vector(C_TAG_WIDTH-1 downto 0) := X"C0";
-- Initial Msg Tag Hihger 4 bits for interrupt
constant C_MSG_TAG_HI : std_logic_vector(3 downto 0) := X"F";
-- Msg code for IntA (fixed by PCIe)
constant C_MSGCODE_INTA : std_logic_vector(7 downto 0) := X"20";
-- Msg code for #IntA (fixed by PCIe)
constant C_MSGCODE_INTA_N : std_logic_vector(7 downto 0) := X"24";
----------------------------------------------------------------------------------
-- DMA status bit definition
constant CINT_BIT_DMA_STAT_NALIGN : integer := 7;
constant CINT_BIT_DMA_STAT_TIMEOUT : integer := 4;
constant CINT_BIT_DMA_STAT_BDANULL : integer := 3;
constant CINT_BIT_DMA_STAT_BUSY : integer := 1;
constant CINT_BIT_DMA_STAT_DONE : integer := 0;
-- Bit definition in interrup status register (ISR)
constant CINT_BIT_US_DONE_IN_ISR : integer := 0;
constant CINT_BIT_DS_DONE_IN_ISR : integer := 1;
constant CINT_BIT_INTGEN_IN_ISR : integer := 2;
constant CINT_BIT_DGEN_IN_ISR : integer := 3;
constant CINT_BIT_USTOUT_IN_ISR : integer := 4;
constant CINT_BIT_DSTOUT_IN_ISR : integer := 5;
constant CINT_BIT_TX_DDR_TOUT_ISR : integer := 6;
constant CINT_BIT_TX_WB_TOUT_ISR : integer := 7;
-- The Time-out bits in System Error Register (SER)
constant CINT_BIT_TX_TOUT_IN_SER : integer := 18;
constant CINT_BIT_EB_TOUT_IN_SER : integer := 19;
constant CINT_BIT_EB_OVERWRITTEN : integer := 20;
-- Bit definition of msg routing method in General Control Register (GCR)
constant C_GCR_MSG_ROUT_BIT_BOT : integer := 0;
constant C_GCR_MSG_ROUT_BIT_TOP : integer := 2;
-- Bit definition of Data Generator available in global status register (GSR)
constant CINT_BIT_DG_AVAIL_IN_GSR : integer := 5;
-- Bit definition of DDR SDRAM ready for use in global status register (GSR)
constant CINT_BIT_DDR_RDY_GSR : integer := 7;
-- Bit range of link width in GSR
constant CINT_BIT_LWIDTH_IN_GSR_BOT : integer := 10; -- 16;
constant CINT_BIT_LWIDTH_IN_GSR_TOP : integer := 15; -- 21;
----------------------------------------------------------------------------------
-- Carry bit, only for better timing, used to divide 32-bit add into 2 stages
constant CBIT_CARRY : integer := 16;
----------------------------------------------------------------------------------
-- Zero and -1 constants for different dimensions
--
constant C_ALL_ZEROS : std_logic_vector(255 downto 0) := (others => '0');
constant C_ALL_ONES : std_logic_vector(255 downto 0) := (others => '1');
----------------------------------------------------------------------------------
-- Implement interrupt generator (IG)
constant IMP_INT_GENERATOR : boolean := false;
-- interrupt type: cfg(INTA or MSI) or MSI-X
constant USE_CFG_INTERRUPT : boolean := true;
------------------------------------------------------------------------------------
---- ------------ Author ID
constant AUTHOR_UNKNOWN : std_logic_vector(4-1 downto 0) := X"0";
constant AUTHOR_AKUGEL : std_logic_vector(4-1 downto 0) := X"1";
constant AUTHOR_WGAO : std_logic_vector(4-1 downto 0) := X"2";
----------------------------------------------------------------------------------
---- ------------ design ID ---------------------
---- design id now contains a version: upper 8 bits, a major revision: next 8 bits,
---- and author code: next 4 bits and a minor revision: lower 12 bits
---- keep the autor file seperate and don't submit to CVS
----
constant DESIGN_VERSION : std_logic_vector(8-1 downto 0) := X"01";
constant DESIGN_MAJOR_REVISION : std_logic_vector(8-1 downto 0) := X"04";
constant DESIGN_MINOR_REVISION : std_logic_vector(12-1 downto 0) := X"001";
constant C_DESIGN_ID : std_logic_vector(64-1 downto 0) := X"00000000"
& DESIGN_VERSION
& DESIGN_MAJOR_REVISION
& AUTHOR_WGAO
& DESIGN_MINOR_REVISION;
----------------------------------------------------------------------------------
-- Function to invert endian for 32-bit data
--
function Endian_Invert_32 (Word_in : std_logic_vector) return std_logic_vector;
function Endian_Invert_64 (Word_in : std_logic_vector(64-1 downto 0)) return std_logic_vector;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- revision log
-- 2007-05-30: AK - abbPackage added, address map changed
-- 2007-06-12: WGao - C_DEF_DMA_CTRL_WORD added,
-- DMA Control word bit definition added,
-- Function Endian_Invert_32 added.
-- CINT_ADDR_MRD_CTRL and CINT_ADDR_CPLD_CTRL changed,
-- CINT_ADDR_US_SAH and CINT_ADDR_DS_SAH removed.
-- 2007-07-16: AK - dma status bits added
end abb64Package;
package body abb64Package is
-- ------------------------------------------------------------------------------------------
-- Function to invert bytewise endian for 32-bit data
-- ------------------------------------------------------------------------------------------
function Endian_Invert_32 (Word_in : std_logic_vector) return std_logic_vector is
begin
return Word_in(7 downto 0)&Word_in(15 downto 8)&Word_in(23 downto 16)&Word_in(31 downto 24);
end Endian_Invert_32;
-- ------------------------------------------------------------------------------------------
-- Function to invert bytewise endian for 64-bit data
-- ------------------------------------------------------------------------------------------
function Endian_Invert_64 (Word_in : std_logic_vector(64-1 downto 0)) return std_logic_vector is
begin
return Word_in(39 downto 32)&Word_in(47 downto 40)&Word_in(55 downto 48)&Word_in(63 downto 56)
& Word_in(7 downto 0)&Word_in(15 downto 8)&Word_in(23 downto 16)&Word_in(31 downto 24);
end Endian_Invert_64;
end abb64Package;
|
lgpl-3.0
|
d056f043acd31a6f48633cab8034a9a5
| 0.576706 | 3.576025 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/pcie/common/wb_transact.vhd
| 1 | 12,914 |
----------------------------------------------------------------------------------
-- Company: Creotech
-- Engineer: abyszuk
--
-- Create Date:
-- Design Name:
-- Module Name: wb_transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library work;
use work.abb64Package.all;
use work.genram_pkg.all;
entity wb_transact is
generic (
C_ASYNFIFO_WIDTH : integer := 66
);
port (
-- PCIE user clk
user_clk : in std_logic;
-- Write port
wr_we : in std_logic;
wr_sof : in std_logic;
wr_eof : in std_logic;
wr_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
wr_full : out std_logic;
-- Read command port
rdc_sof : in std_logic;
rdc_v : in std_logic;
rdc_din : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
rdc_full : out std_logic;
rd_tout : in std_logic;
-- Read data port
rd_ren : in std_logic;
rd_empty : out std_logic;
rd_dout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Wishbone interface
wb_clk : in std_logic;
wb_rst : in std_logic;
addr_o : out std_logic_vector(28 downto 0);
dat_i : in std_logic_vector(63 downto 0);
dat_o : out std_logic_vector(63 downto 0);
we_o : out std_logic;
sel_o : out std_logic_vector(0 downto 0);
stb_o : out std_logic;
ack_i : in std_logic;
cyc_o : out std_logic;
--RESET from PCIe
rst : in std_logic
);
end entity wb_transact;
architecture Behavioral of wb_transact is
type wb_states is (st_RESET,
st_IDLE,
st_LA,
st_WR_LOAD,
st_WR_SEND,
st_RD
);
signal wb_state : wb_states := st_RESET;
signal wpipe_din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0) := (others => '0');
signal wpipe_wen : std_logic;
signal wpipe_afull : std_logic;
signal wpipe_full : std_logic;
signal wpipe_empty : std_logic;
signal wpipe_qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal wpipe_ren : std_logic;
signal wpipe_rd_en : std_logic;
signal wpipe_valid : std_logic;
signal wpipe_last : std_logic;
signal rpipec_din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0) := (others => '0');
signal rpipec_wen : std_logic;
signal rpipec_qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpipec_valid : std_logic;
signal rpipec_ren : std_logic;
signal rpipec_empty : std_logic;
signal rpipec_full : std_logic;
signal rpipec_afull : std_logic;
signal rpiped_din : std_logic_vector(63 downto 0) := (others => '0');
signal rpiped_qout : std_logic_vector(63 downto 0);
signal rpiped_full : std_logic;
signal rpiped_we : std_logic;
signal rpiped_afull : std_logic;
signal rpiped_empty : std_logic;
signal wb_addr : unsigned(addr_o'range);
signal wb_rd_cnt : unsigned(C_TLP_FLD_WIDTH_OF_LENG-2 downto 0);
signal wb_dat_o : std_logic_vector(dat_o'range);
signal wb_we : std_logic;
signal wb_sel : std_logic_vector(sel_o'range);
signal wb_stb : std_logic;
signal wb_cyc : std_logic;
signal rst_i : std_logic;
signal rst_rd_i : std_logic;
signal rst_n_i : std_logic;
signal rst_rd_n_i : std_logic;
begin
rst_i <= wb_rst or rst;
rst_rd_i <= rst_i or rd_tout;
rst_n_i <= not rst_i;
rst_rd_n_i <= not rst_rd_i;
--Wishbone interface FSM
WB_fsm :
process (wb_clk)
begin
if rising_edge(wb_clk) then
if rst_i = '1' then
wb_state <= st_RESET;
wb_cyc <= '0';
wb_we <= '0';
wb_stb <= '0';
wb_sel <= (others => '0');
wpipe_ren <= '0';
rpiped_we <= '0';
else
case wb_state is
when st_RESET =>
wb_state <= st_IDLE;
when st_IDLE =>
wb_stb <= '0';
wb_cyc <= '0';
wb_we <= '0';
wb_sel <= (others => '0');
rpiped_we <= '0';
if wpipe_empty = '0' then
wpipe_ren <= '1';
rpipec_ren <= '0';
wb_state <= st_LA;
elsif rpipec_empty = '0' then
wpipe_ren <= '0';
rpipec_ren <= '1';
wb_state <= st_LA;
else
wpipe_ren <= '0';
rpipec_ren <= '0';
wb_state <= st_IDLE;
end if;
when st_LA =>
wb_stb <= '0';
wb_cyc <= '0';
wpipe_ren <= '0';
if wpipe_valid = '1' then
if wpipe_qout(C_DBUS_WIDTH) = '1' then --sof
wb_addr <= unsigned(wpipe_qout(wb_addr'left+3 downto 3));
wb_state <= st_WR_LOAD;
else
wb_state <= st_IDLE;
end if;
elsif rpipec_valid = '1' then
wb_addr <= unsigned(rpipec_qout(wb_addr'left+3 downto 3));
wb_rd_cnt <= unsigned(rpipec_qout(C_TLP_FLD_WIDTH_OF_LENG+32+1 downto 32+3)); --omit lowest bit, QW counted
rpipec_ren <= '0';
wb_state <= st_RD;
else
wb_state <= st_LA;
end if;
when st_RD =>
wb_stb <= not(rpiped_afull);
wb_cyc <= '1';
wb_sel <= (others => '1');
wb_we <= '0';
if rd_tout = '1' then
wb_stb <= '0';
wb_cyc <= '0';
wb_state <= st_IDLE;
elsif wb_stb = '1' and ack_i = '1' then
rpiped_din <= dat_i;
rpiped_we <= '1';
wb_addr <= wb_addr + 1;
wb_rd_cnt <= wb_rd_cnt - 1;
if wb_rd_cnt <= 1 then
wb_stb <= '0';
wb_cyc <= '0';
wb_state <= st_IDLE;
else
wb_state <= st_RD;
end if;
else
rpiped_din <= rpiped_din;
rpiped_we <= '0';
wb_state <= st_RD;
end if;
when st_WR_LOAD =>
wb_cyc <= '1';
wb_we <= '1';
wb_sel <= (others => '1');
if wpipe_valid = '1' then
wpipe_ren <= '0';
wpipe_last <= wpipe_qout(C_DBUS_WIDTH+1);
wb_dat_o <= wpipe_qout(wb_dat_o'range);
wb_stb <= '1';
wb_state <= st_WR_SEND;
else
wpipe_ren <= '1';
wpipe_last <= wpipe_last;
wb_dat_o <= wb_dat_o;
wb_stb <= '0';
wb_state <= st_WR_LOAD;
end if;
when st_WR_SEND =>
wb_cyc <= '1';
wb_we <= '1';
wb_sel <= (others => '1');
if ack_i = '1' and wb_stb = '1' then
wb_stb <= '0';
if wpipe_last = '1' then
wpipe_ren <= '0';
wb_addr <= wb_addr;
wb_state <= st_IDLE;
else
wpipe_ren <= '1';
wb_addr <= wb_addr + 1;
wb_state <= st_WR_LOAD;
end if;
else
wb_stb <= '1';
wpipe_ren <= '0';
wb_addr <= wb_addr;
wb_state <= st_WR_SEND;
end if;
end case;
end if;
end if;
end process;
wr_full <= wpipe_afull;
rdc_full <= rpipec_afull;
stb_o <= wb_stb;
addr_o <= std_logic_vector(wb_addr);
cyc_o <= wb_cyc;
dat_o <= wb_dat_o;
sel_o <= wb_sel;
we_o <= wb_we;
wpipe_syn :
process (user_clk)
begin
if rising_edge(user_clk) then
wpipe_din <= (others => '0');
wpipe_din(C_DBUS_WIDTH-1 downto 0) <= wr_din;
wpipe_din(C_DBUS_WIDTH) <= wr_sof;
wpipe_din(C_DBUS_WIDTH+1) <= wr_eof;
wpipe_wen <= wr_we;
end if;
end process;
p_wpipe_valid :
process (wb_clk)
begin
if rising_edge(wb_clk) then
if wpipe_ren = '1' and wpipe_empty = '0' then
wpipe_valid <= '1';
else
wpipe_valid <= '0';
end if;
end if;
end process;
-- we access one word at a time, so stall read if we got valid data
wpipe_rd_en <= wpipe_ren and not(wpipe_valid);
wpipe_fifo :
generic_async_fifo
generic map (
g_data_width => C_ASYNFIFO_WIDTH,
g_size => 128,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => true,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_full_threshold => 120)
port map(
rst_n_i => rst_n_i,
clk_wr_i => user_clk,
d_i => wpipe_Din,
we_i => wpipe_wEn,
wr_empty_o => open,
wr_full_o => wpipe_Full,
wr_almost_empty_o => open,
wr_almost_full_o => wpipe_aFull,
wr_count_o => open,
clk_rd_i => wb_clk,
q_o => wpipe_qout,
rd_i => wpipe_rd_en,
rd_empty_o => wpipe_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
rpipe_syn :
process (user_clk)
begin
if rising_edge(user_clk) then
rpipec_din <= (others => '0');
rpipec_din(C_DBUS_WIDTH-1 downto 0) <= rdc_din;
rpipec_din(C_DBUS_WIDTH) <= rdc_v;
rpipec_din(C_DBUS_WIDTH+1) <= rdc_sof;
end if;
end process;
p_rpipec_valid :
process (wb_clk)
begin
if rising_edge(wb_clk) then
if rpipec_ren = '1' and rpipec_empty = '0' then
rpipec_valid <= '1';
else
rpipec_valid <= '0';
end if;
end if;
end process;
rpipec_wen <= rpipec_din(C_DBUS_WIDTH);
rpipec_fifo :
generic_async_fifo
generic map (
g_data_width => C_ASYNFIFO_WIDTH,
g_size => 32,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => true,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_full_threshold => 30)
port map(
rst_n_i => rst_rd_n_i,
clk_wr_i => user_clk,
d_i => rpipec_din,
we_i => rpipec_wen,
wr_empty_o => open,
wr_full_o => rpipec_full,
wr_almost_empty_o => open,
wr_almost_full_o => rpipec_afull,
wr_count_o => open,
clk_rd_i => wb_clk,
q_o => rpipec_qout,
rd_i => rpipec_ren,
rd_empty_o => rpipec_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
rpiped_fifo :
generic_async_fifo
generic map (
g_data_width => 64,
g_size => 128,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => false,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => false,
g_with_wr_empty => false,
g_with_wr_full => true,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => true,
g_with_wr_count => false,
g_almost_full_threshold => 124)
port map(
rst_n_i => rst_rd_n_i,
clk_wr_i => wb_clk,
d_i => rpiped_din,
we_i => rpiped_we,
wr_empty_o => open,
wr_full_o => rpiped_full,
wr_almost_empty_o => open,
wr_almost_full_o => rpiped_afull,
wr_count_o => open,
clk_rd_i => user_clk,
q_o => rpiped_qout,
rd_i => rd_ren,
rd_empty_o => rd_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open);
rd_dout <= rpiped_qout;
end architecture Behavioral;
|
lgpl-3.0
|
997a2910575af576264d618122539376
| 0.463451 | 3.336951 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/fmc_adc_common/fmc_adc_sync_chains.vhd
| 1 | 4,905 |
------------------------------------------------------------------------------
-- Title : Wishbone FMC516 ADC Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-18-03
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Synchronization between all data chains to a single clock
-- domain. The necessity of such module has to be better
-- understood, but so far, it does not appear necessary
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-18-03 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc_adc_pkg.all;
use work.genram_pkg.all;
entity fmc_adc_sync_chains is
--generic
--(
--)
port
(
sys_clk_i : std_logic;
sys_rst_n_i : std_logic;
-----------------------------
-- ADC Data Input signals. Each data chain is synchronous to its
-- own clock.
-----------------------------
adc_out_i : in t_adc_out_array(c_num_adc_channels-1 downto 0);
-- Reference clock for synchronization with all data chains
adc_refclk_i : in t_adc_clk_chain_glob;
-----------------------------
-- ADC output signals. Synchronous to a single clock
-----------------------------
adc_out_o : out t_adc_out_array(c_num_adc_channels-1 downto 0)
);
end fmc_adc_sync_chains;
architecture rtl of fmc_adc_sync_chains is
constant c_async_fifo_size : natural := 16;
signal adc_ref_clk : std_logic;
signal adc_ref_clk2x : std_logic;
signal adc_data_fifo_in : std_logic_vector(c_num_adc_bits*c_num_adc_channels-1 downto 0);
signal adc_data_fifo_out : std_logic_vector(c_num_adc_bits*c_num_adc_channels-1 downto 0);
-- FIFO signals
signal adc_fifo_wr : std_logic;
signal adc_fifo_rd : std_logic;
signal adc_fifo_full : std_logic;
signal adc_fifo_empty : std_logic;
signal adc_data_valid_out : std_logic;
begin
adc_ref_clk <= adc_refclk_i.adc_clk_bufg;
adc_ref_clk2x <= adc_refclk_i.adc_clk2x_bufg;
-- Merge FIFO data
gen_merge_adc_data_channel : for i in 0 to c_num_adc_channels-1 generate -- 0 to 3
gen_merge_adc_data_bits : for j in 0 to c_num_adc_bits-1 generate -- 0 to 15
adc_data_fifo_in(i*c_num_adc_bits + j)
<= adc_out_i(i).adc_data(j);
end generate;
end generate;
cmp_adc_data_sync_fifo : generic_sync_fifo
generic map(
g_data_width => c_num_adc_bits*c_num_adc_channels,
g_size => c_async_fifo_size
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => adc_ref_clk,
d_i => adc_data_fifo_in,
we_i => adc_fifo_wr,
q_o => adc_data_fifo_out,
rd_i => adc_fifo_rd,
full_o => adc_fifo_full,
empty_o => adc_fifo_empty
);
--Generate valid signal for adc_data_o.
p_gen_valid : process (adc_ref_clk)
begin
if rising_edge (adc_ref_clk) then
adc_data_valid_out <= adc_fifo_rd;
if adc_fifo_empty = '1' then
adc_data_valid_out <= '0';
end if;
end if;
end process;
adc_fifo_wr <= '1';
adc_fifo_rd <= '1';
-- Unmerge FIFO data
gen_unmerge_adc_data_channel : for i in 0 to c_num_adc_channels-1 generate -- 0 to 3
gen_unmerge_adc_data_bits : for j in 0 to c_num_adc_bits-1 generate -- 0 to 15
adc_out_o(i).adc_data(j) <= adc_data_fifo_out(i*c_num_adc_bits + j);
end generate;
adc_out_o(i).adc_clk <= adc_ref_clk;
adc_out_o(i).adc_clk2x <= adc_ref_clk2x;
adc_out_o(i).adc_data_valid <= adc_data_valid_out;
end generate;
end rtl;
|
lgpl-3.0
|
20e456aabb0115eabf0ef22a1c9cdd7a
| 0.449541 | 3.974878 | false | false | false | false |
peteg944/music-fpga
|
LED_Matrix_FPGA_Nexys 3/ipcore_dir/pll/simulation/pll_tb.vhd
| 1 | 6,667 |
-- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
end test;
|
mit
|
9b8b21e536e5f2bc3dd82114a13c79dd
| 0.60972 | 4.249203 | false | false | false | false |
hoglet67/AtomBusMon
|
src/Z80CpuMonALS.vhd
| 2 | 6,358 |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMonALS.vhd
-- /___/ /\ Timestamp : 29/09/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: Z80CpuMon
--Device: XC6SLX9
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Z80CpuMonALS is
generic (
num_comparators : integer := 8; -- default value for lx9core board
avr_prog_mem_size : integer := 1024 * 16 -- default value for lx9core board
);
port (
clock : in std_logic;
-- Z80 Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- Level Shifers Controls
OEC_n : out std_logic;
OEA1_n : out std_logic;
OEA2_n : out std_logic;
OED_n : out std_logic;
DIRD : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- ID/mode inputs
mode : in std_logic;
id : in std_logic_vector(3 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
-- Optional OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Optional Debugging signals
test : out std_logic_vector(9 downto 0)
);
end Z80CpuMonALS;
architecture behavioral of Z80CpuMonALS is
signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal M1_n_int : std_logic;
signal RD_n_int : std_logic;
signal WR_n_int : std_logic;
signal RFSH_n_int : std_logic;
signal HALT_n_int : std_logic;
signal BUSAK_n_int : std_logic;
signal tristate_n : std_logic;
signal tristate_ad_n: std_logic;
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
signal TState : std_logic_vector(2 downto 0);
begin
sw_reset_cpu <= not sw1;
sw_reset_avr <= not sw2;
led1 <= led_bkpt;
led2 <= led_trig0;
led3 <= led_trig1;
MREQ_n <= MREQ_n_int;
IORQ_n <= IORQ_n_int;
M1_n <= M1_n_int;
RD_n <= RD_n_int;
WR_n <= WR_n_int;
RFSH_n <= RFSH_n_int;
HALT_n <= HALT_n_int;
BUSAK_n <= BUSAK_n_int;
OEC_n <= not tristate_n;
OEA1_n <= not tristate_ad_n;
OEA2_n <= not tristate_ad_n;
OED_n <= not tristate_ad_n;
wrapper : entity work.Z80CpuMon
generic map (
ClkMult => 12,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock,
-- Z80 Signals
RESET_n => RESET_n,
CLK_n => CLK_n,
WAIT_n => WAIT_n,
INT_n => INT_n,
NMI_n => NMI_n,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n_int,
MREQ_n => MREQ_n_int,
IORQ_n => IORQ_n_int,
RD_n => RD_n_int,
WR_n => WR_n_int,
RFSH_n => RFSH_n_int,
HALT_n => HALT_n_int,
BUSAK_n => BUSAK_n_int,
Addr => Addr,
Data => Data,
-- Buffer Control Signals
DIRD => DIRD,
tristate_n => tristate_n,
tristate_ad_n => tristate_ad_n,
-- Mode jumper, tie low to generate NOPs when paused
mode => mode,
-- External trigger inputs
trig => trig,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 connected to test connector
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
-- Debugging signals
test1 => open,
test2 => TState(0),
test3 => TState(1),
test4 => TSTate(2)
);
-- Test outputs
test(0) <= M1_n_int;
test(1) <= RD_n_int;
test(2) <= WR_n_int;
test(3) <= MREQ_n_int;
test(4) <= IORQ_n_int;
test(5) <= WAIT_n;
test(6) <= CLK_n;
test(7) <= TState(2);
test(8) <= TState(1);
test(9) <= TState(0);
end behavioral;
|
gpl-3.0
|
d2a5459c679fd5d9f6f3406f18ef0b89
| 0.405945 | 3.729032 | false | true | false | false |
fbelavenuto/msx1fpga
|
src/audio/vm2413/controller.vhd
| 2 | 15,786 |
--
-- Controller.vhd
-- The core controller module of VM2413
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
-- [Description]
--
-- The Controller is the beginning module of the OPLL slot calculation.
-- It manages register accesses from I/O and sends proper voice parameters
-- to the succeding PhaseGenerator and EnvelopeGenerator modules.
-- The one cycle of the Controller consists of 4 stages as follows.
--
-- 1st stage:
-- * Prepare to read the register value for the current slot from RegisterMemory.
-- * Prepare to read the voice parameter for the current slot from VoiceMemory.
-- * Prepare to read the user-voice data from VoiceMemory.
--
-- 2nd stage:
-- * Wait for RegisterMemory and VoiceMemory
--
-- 3rd clock stage:
-- * Update register value if wr='1' and addr points the current OPLL channel.
-- * Update voice parameter if wr='1' and addr points the voice parameter area.
-- * Write register value to RegisterMemory.
-- * Write voice parameter to VoiceMemory.
--
-- 4th stage:
-- * Send voice and register parameters to PhaseGenerator and EnvelopeGenerator.
-- * Increment the number of the current slot.
--
-- Each stage is completed in one clock. Thus the Controller traverses all 18 opll
-- slots in 72 clocks.
--
--
-- modified by t.hara
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.vm2413.all;
entity controller is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
wr : in std_logic;
addr : in std_logic_vector( 7 downto 0 );
data : in std_logic_vector( 7 downto 0 );
-- output parameters for phasegenerator and envelopegenerator
am : out std_logic;
pm : out std_logic;
wf : out std_logic;
ml : out std_logic_vector(3 downto 0);
tl : out std_logic_vector(6 downto 0);
fb : out std_logic_vector(2 downto 0);
ar : out std_logic_vector(3 downto 0);
dr : out std_logic_vector(3 downto 0);
sl : out std_logic_vector(3 downto 0);
rr : out std_logic_vector(3 downto 0);
blk : out std_logic_vector(2 downto 0);
fnum : out std_logic_vector(8 downto 0);
rks : out std_logic_vector(3 downto 0);
key : out std_logic;
rhythm : out std_logic
-- slot_out : out slot_id
);
end controller;
architecture rtl of controller is
-- the array which caches instrument number of each channel.
type inst_array is array ( 0 to 9-1) of integer range 0 to 15;
signal inst_cache : inst_array;
attribute ram_style : string;
attribute ram_style of inst_cache : signal is "block";
type kl_array is array (0 to 15) of std_logic_vector(5 downto 0);
constant kl_table : kl_array := (
"000000", "011000", "100000", "100101",
"101000", "101011", "101101", "101111",
"110000", "110010", "110011", "110100",
"110101", "110110", "110111", "111000"
); -- 0.75db/step, 6db/oct
-- signals for the read-only access ports of voicememory module.
signal slot_voice_addr : integer range 0 to 37;
signal slot_voice_data : voice_type;
-- signals for the read-write access ports of voicememory module.
signal user_voice_wr : std_logic;
signal user_voice_addr : integer range 0 to 37;
signal user_voice_rdata : voice_type;
signal user_voice_wdata : voice_type;
-- signals for the registermemory module.
signal regs_wr : std_logic;
signal regs_addr : std_logic_vector( 3 downto 0 );
signal regs_rdata : std_logic_vector( 23 downto 0 );
signal regs_wdata : std_logic_vector( 23 downto 0 );
signal rflag : std_logic_vector( 7 downto 0 );
signal w_channel : std_logic_vector( 3 downto 0 );
-- signal w_is_carrier : std_logic;
begin -- rtl
-- ���W�X�^�ݒ��l���ێ����邽�߂̃�����
u_register_memory : entity work.RegisterMemory
port map (
clk => clk,
reset => reset,
addr => regs_addr,
wr => regs_wr,
idata => regs_wdata,
odata => regs_rdata
);
vmem : entity work.VoiceMemory
port map (
clk, reset, user_voice_wdata, user_voice_wr, user_voice_addr, slot_voice_addr,
user_voice_rdata, slot_voice_data );
-- ���W�X�^�A�h���X���b�` (���P�X�e�[�W)
process( reset, clk )
begin
if( reset = '1' )then
regs_addr <= (others => '0');
elsif( clk'event and clk = '1' )then
if clkena='1' then
if( stage = "00" )then
regs_addr <= slot( 4 downto 1 );
else
-- hold
end if;
end if;
end if;
end process;
-- ���݂̃X���b�g�̉��F�f�[�^�ǂݏo���A�h���X���b�` (���P�X�e�[�W)
process( reset, clk )
begin
if( reset = '1' )then
slot_voice_addr <= 0;
elsif( clk'event and clk = '1' )then
if clkena='1' then
if( stage = "00" )then
if( rflag(5) = '1' and w_channel >= "0110" )then
-- ���Y�����[�h�� ch6 �ȍ~
slot_voice_addr <= conv_integer(slot) - 12 + 32;
else
slot_voice_addr <= inst_cache(conv_integer(slot)/2) * 2 + conv_integer(slot) mod 2;
end if;
else
-- hold
end if;
end if;
end if;
end process;
w_channel <= slot( 4 downto 1 );
-- w_is_carrier <= slot( 0 );
process (clk, reset)
variable kflag : std_logic;
variable tll : std_logic_vector(7 downto 0);
variable kll : std_logic_vector(7 downto 0);
variable regs_tmp : std_logic_vector(23 downto 0);
variable user_voice_tmp : voice_type;
variable fb_buf : std_logic_vector(2 downto 0);
variable wf_buf : std_logic;
variable extra_mode : std_logic;
variable vindex : integer range 0 to 37;
begin -- process
if(reset = '1') then
key <= '0';
rhythm <= '0';
tll := (others=>'0');
kll := (others=>'0');
kflag := '0';
rflag <= (others=>'0');
user_voice_wr <= '0';
user_voice_addr <= 0;
regs_wr <='0';
ar <= (others=>'0');
dr <= (others=>'0');
sl <= (others=>'0');
rr <= (others=>'0');
tl <= (others=>'0');
fb <= (others=>'0');
wf <= '0';
ml <= (others=>'0');
fnum <= (others=>'0');
blk <= (others=>'0');
key <= '0';
rks <= (others=>'0');
rhythm <= '0';
extra_mode := '0';
vindex := 0;
elsif clk'event and clk='1' then
if clkena='1' then
case stage is
--------------------------------------------------------------------------
-- 1st stage (setting up a read request for register and voice memories.)
--------------------------------------------------------------------------
when "00" =>
-- if extra_mode = '0' then
-- alternately read modulator or carrior.
vindex := conv_integer(slot) mod 2;
-- else
-- if vindex = 37 then
-- vindex:= 0;
-- else
-- vindex:= vindex + 1;
-- end if;
-- end if;
user_voice_addr <= vindex;
regs_wr <= '0';
user_voice_wr <='0';
--------------------------------------------------------------------------
-- 2nd stage (just a wait for register and voice memories.)
--------------------------------------------------------------------------
when "01" =>
null;
--------------------------------------------------------------------------
-- 3rd stage (updating a register and voice parameters.)
--------------------------------------------------------------------------
when "10" =>
if wr='1' then
-- if ( extra_mode = '0' and conv_integer(addr) < 8 ) or
-- ( extra_mode = '1' and ( conv_integer(addr) - 64 ) / 8 = vindex / 2 ) then
if( extra_mode = '0' and conv_integer(addr) < 8 )then
-- update user voice parameter.
user_voice_tmp := user_voice_rdata;
case addr(2 downto 1) is
when "00" =>
if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.am := data(7);
user_voice_tmp.pm := data(6);
user_voice_tmp.eg := data(5);
user_voice_tmp.kr := data(4);
user_voice_tmp.ml := data(3 downto 0);
user_voice_wr <= '1';
end if;
when "01" =>
if addr(0)='0' and (vindex mod 2 = 0) then
user_voice_tmp.kl := data(7 downto 6);
user_voice_tmp.tl := data(5 downto 0);
user_voice_wr <= '1';
elsif addr(0)='1' and (vindex mod 2 = 0) then
user_voice_tmp.wf := data(3);
user_voice_tmp.fb := data(2 downto 0);
user_voice_wr <= '1';
elsif addr(0)='1' and (vindex mod 2 = 1) then
user_voice_tmp.kl := data(7 downto 6);
user_voice_tmp.wf := data(4);
user_voice_wr <= '1';
end if;
when "10" =>
if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.ar := data(7 downto 4);
user_voice_tmp.dr := data(3 downto 0);
user_voice_wr <= '1';
end if;
when "11" =>
if conv_integer(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.sl := data(7 downto 4);
user_voice_tmp.rr := data(3 downto 0);
user_voice_wr <= '1';
end if;
when others =>
null;
end case;
user_voice_wdata <= user_voice_tmp;
elsif conv_integer(addr) = 14 then
rflag <= data;
elsif conv_integer(addr) < 16 then
null;
elsif conv_integer(addr) <= 63 then
if( conv_integer(addr(3 downto 0) ) = conv_integer(slot) / 2 ) then
regs_tmp := regs_rdata;
case addr( 5 downto 4 ) is
when "01" => -- 10h�`18h �̏ꍇ�i���� F-Number�j
regs_tmp(7 downto 0) := data; -- F-Number
regs_wr <= '1';
when "10" => -- 20h�`28h �̏ꍇ�iSus, Key, Block, F-Number MSB�j
regs_tmp(13) := data(5); -- Sus
regs_tmp(12) := data(4); -- Key
regs_tmp(11 downto 9) := data(3 downto 1); -- Block
regs_tmp(8) := data(0); -- F-Number
regs_wr <= '1';
when "11" => -- 30h�`38h �̏ꍇ�iInst, Vol�j
regs_tmp(23 downto 20) := data(7 downto 4); -- Inst
regs_tmp(19 downto 16) := data(3 downto 0); -- Vol
regs_wr <='1';
when others =>
null;
end case;
regs_wdata <= regs_tmp;
end if;
elsif conv_integer(addr) = 240 then
if data(7 downto 0) = "10000000" then
extra_mode := '1';
else
extra_mode := '0';
end if;
end if;
end if;
--------------------------------------------------------------------------
-- 4th stage (updating a register and voice parameters.)
--------------------------------------------------------------------------
when "11" =>
-- output slot number (for explicit synchonization with other units).
-- slot_out <= slot;
-- updating insturument cache
inst_cache(conv_integer(slot)/2) <= conv_integer(regs_rdata(23 downto 20));
rhythm <= rflag(5);
-- updating rhythm status and key flag
if rflag(5) = '1' and 12 <= slot then
case slot is
when "01100" | "01101" => -- bd
kflag := rflag(4);
when "01110" => -- hh
kflag := rflag(0);
when "01111" => -- sd
kflag := rflag(3);
when "10000" => -- tom
kflag := rflag(2);
when "10001" => -- cym
kflag := rflag(1);
when others => null;
end case;
else
kflag := '0';
end if;
kflag := kflag or regs_rdata(12);
-- calculate key-scale attenuation amount.
kll := (("0"&kl_table(conv_integer(regs_rdata(8 downto 5))))
- ("0"&("111"-regs_rdata(11 downto 9))&"000")) & '0';
if kll(kll'high) ='1' or slot_voice_data.kl = "00" then
kll := (others=>'0');
else
kll := shr(kll, "11" - slot_voice_data.kl );
end if;
-- calculate base total level from volume register value.
if rflag(5) = '1' and (slot = "01110" or slot = "10000") then -- hh and cym
tll := ('0' & regs_rdata(23 downto 20) & "000");
elsif( slot(0) = '0' )then
tll := ('0' & slot_voice_data.tl & '0'); -- mod
else
tll := ('0' & regs_rdata(19 downto 16) & "000"); -- car
end if;
tll := tll + kll;
if tll(tll'high) ='1' then
tl <= (others=>'1');
else
tl <= tll(tl'range);
end if;
-- output rks, f-number, block and key-status.
fnum <= regs_rdata(8 downto 0);
blk <= regs_rdata(11 downto 9);
key <= kflag;
if rflag(5) = '1' and 14 <= slot then
if slot_voice_data.kr = '1' then
rks <= "0101";
else
rks <= "00" & regs_rdata(11 downto 10);
end if;
else
if slot_voice_data.kr = '1' then
rks <= regs_rdata(11 downto 9) & regs_rdata(8);
else
rks <= "00" & regs_rdata(11 downto 10);
end if;
end if;
-- output voice parameters
-- note that wf and fb output must keep its value
-- at least 3 clocks since the operator module will fetch
-- the wf and fb 2 clocks later of this stage.
am <= slot_voice_data.am;
pm <= slot_voice_data.pm;
ml <= slot_voice_data.ml;
wf_buf := slot_voice_data.wf;
fb_buf := slot_voice_data.fb;
wf <= wf_buf;
fb <= fb_buf;
ar <= slot_voice_data.ar;
dr <= slot_voice_data.dr;
sl <= slot_voice_data.sl;
-- output release rate (depends on the sustine and envelope type).
if( kflag = '1' ) then -- key on
if slot_voice_data.eg = '1' then
rr <= "0000";
else
rr <= slot_voice_data.rr;
end if;
else -- key off
if (slot(0) = '0') and not ( rflag(5) = '1' and (7 <= conv_integer(slot)/2) ) then
rr <= "0000";
elsif regs_rdata(13) = '1' then
rr <= "0101";
elsif slot_voice_data.eg = '0' then
rr <= "0111";
else
rr <= slot_voice_data.rr;
end if;
end if;
when others =>
null;
end case;
end if; end if;
end process;
end rtl;
|
gpl-3.0
|
b77f948c36dc05b39607a78f9fd04dc5
| 0.54823 | 3.231776 | false | false | false | false |
hoglet67/AtomBusMon
|
src/T80/T80.vhd
| 1 | 40,194 |
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup.
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0250
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
-- 0210 : Fixed wait and halt
-- 0211 : Fixed Refresh addition and IM 1
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
-- 0237 : Changed 8080 I/O address output, added IntE output
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
-- 0247 : Fixed bus req/ack cycle
-- 0250 : Added R800 Multiplier by TobiFlex 2017.10.15
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
NMICycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
R800_mode : in std_logic := '0';
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
REG : out std_logic_vector(211 downto 0); -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
DIRSet : in std_logic := '0';
DIR : in std_logic_vector(211 downto 0) := (others => '0') -- IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end T80;
architecture rtl of T80 is
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal WZ : std_logic_vector(15 downto 0); -- MEMPTR register
signal TmpAddr2 : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal MULU_Prod32 : std_logic_vector(31 downto 0);
signal MULU_tmp : std_logic_vector(31 downto 0);
signal MULU_Fakt1 : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic := '0';
signal BusAck : std_logic := '0';
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal Rot_Akku : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal LDHLSP : std_logic;
signal ADDSPdd : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_RXDD : std_logic;
signal I_INRC : std_logic;
signal I_MULUB : std_logic;
signal I_MULU : std_logic;
signal SetWZ : std_logic_vector(1 downto 0);
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
signal No_PC : std_logic;
signal DOR : std_logic_vector(127 downto 0);
begin
REG <= IntE_FF2 & IntE_FF1 & IStatus & DOR & std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC when Alternate = '0'
else IntE_FF2 & IntE_FF1 & IStatus & DOR(127 downto 112) & DOR(47 downto 0) & DOR(63 downto 48) & DOR(111 downto 64) &
std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC;
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
Rot_Akku => Rot_Akku,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
LDHLSP => LDHLSP,
ADDSPdd => ADDSPdd,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
I_MULUB => I_MULUB,
I_MULU => I_MULU,
SetWZ => SetWZ,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
R800_mode => R800_mode,
No_PC => No_PC,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
WZ => WZ,
XY_State=> XY_State,
ALU_Op => ALU_Op_r,
Rot_Akku => Rot_Akku,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
variable n : std_logic_vector(7 downto 0);
variable ioq : std_logic_vector(8 downto 0);
variable temp_c : unsigned(8 downto 0);
variable temp_h : unsigned(4 downto 0);
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
WZ <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
if Mode = 3 then
ACC <= (others => '0');
F <= "11110000";
end if;
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
I_RXDD <= '0';
elsif rising_edge(CLK_n) then
if DIRSet = '1' then
ACC <= DIR( 7 downto 0);
F <= DIR(15 downto 8);
Ap <= DIR(23 downto 16);
Fp <= DIR(31 downto 24);
I <= DIR(39 downto 32);
R <= unsigned(DIR(47 downto 40));
SP <= unsigned(DIR(63 downto 48));
PC <= unsigned(DIR(79 downto 64));
A <= DIR(79 downto 64);
IStatus <= DIR(209 downto 208);
elsif ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if LDHLSP = '1' and MCycle = "011" and TState = 1 then
temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
F(Flag_Z) <= '0';
F(Flag_N) <= '0';
F(Flag_H) <= temp_h(4);
F(Flag_C) <= temp_c(8);
end if;
if ADDSPdd = '1' and TState = 1 then
temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
F(Flag_Z) <= '0';
F(Flag_N) <= '0';
F(Flag_H) <= temp_h(4);
F(Flag_C) <= temp_c(8);
end if;
if Mode = 3 then
IStatus <= "10";
elsif IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
if Mode <= 1 and IntCycle = '1' and IStatus = "10" then
-- IM2 vector address low byte from bus
WZ(7 downto 0) <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= WZ(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(WZ(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= WZ;
PC <= unsigned(WZ);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif ((Mode /= 3 and MCycle = "011") or (Mode = 3 and MCycle = "100"))
and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= WZ(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(WZ(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= WZ;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
WZ <= (ACC & DI_Reg) + "1";
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
if SetWZ = "01" then
WZ <= RegBusC + "1";
end if;
if SetWZ = "10" then
WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
end if;
when aDE =>
A <= RegBusC;
if SetWZ = "10" then
WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(WZ) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= WZ(7 downto 0);
if SetWZ = "10" then
WZ(7 downto 0) <= WZ(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
end if;
when others =>
if ISet = "10" and IR(7 downto 4) = x"B" and IR(2 downto 1) = "01" and MCycle = 3 and No_BTR = '0' then
-- INIR, INDR, OTIR, OTDR
A <= RegBusA_r;
elsif No_PC = '0' or No_BTR = '1' or (I_DJNZ = '1' and IncDecZ = '1') or Mode > 1 then
A <= std_logic_vector(PC);
end if;
end case;
end if;
if SetWZ = "11" then
WZ <= std_logic_vector(ID16);
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if Mode = 3 then
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_H) <= '1';
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
else
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
end if;
if (TState = 2 and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then
ioq := ('0' & DI_Reg) + ('0' & std_logic_vector(ID16(7 downto 0)));
F(Flag_N) <= DI_Reg(7);
F(Flag_C) <= ioq(8);
F(Flag_H) <= ioq(8);
ioq := (ioq and ('0'&x"07")) xor ('0'&BusA);
F(Flag_P) <= not (ioq(0) xor ioq(1) xor ioq(2) xor ioq(3) xor ioq(4) xor ioq(5) xor ioq(6) xor ioq(7));
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
WZ <= std_logic_vector(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
WZ <= (others =>'0');
WZ(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
WZ <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if MCycle = "011" and TState = 4 and No_BTR = '0' then
if I_BT = '1' or I_BC = '1' then
WZ <= std_logic_vector(PC)-"1";
end if;
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if ADDSPdd = '1' and TState = 2 then
WZ <= std_logic_vector(SP);
SP <= unsigned(signed(SP)+signed(Save_Mux));
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
WZ(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
WZ(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
F(Flag_S) <= I(7);
if I = x"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_Y) <= I(5);
F(Flag_H) <= '0';
F(Flag_X) <= I(3);
F(Flag_N) <= '0';
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
F(Flag_S) <= R(7);
if R = x"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_Y) <= R(5);
F(Flag_H) <= '0';
F(Flag_X) <= R(3);
F(Flag_N) <= '0';
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
F(Flag_X) <= DI_Reg(3);
F(Flag_Y) <= DI_Reg(5);
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 and Auto_Wait_t1 = '0' then
-- Keep D0 from M3 for RLD/RRD (Sorgelig)
I_RXDD <= I_RLD or I_RRD;
if I_RXDD='0' then
DO <= BusB;
end if;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if TState = 1 and I_BC = '1' then
n := ALU_Q - ("0000000" & F_Out(Flag_H));
F(Flag_X) <= n(3);
F(Flag_Y) <= n(1);
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
if Mode = 3 then
F(7 downto 4) <= Save_Mux(7 downto 4);
F(3 downto 0) <= "0000"; -- bit 3 to 0 always return 0
else
F <= Save_Mux;
end if;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Multiply
--
---------------------------------------------------------------------------
process (CLK_n, ACC, RegBusB, MULU_tmp, MULU_Fakt1, MULU_Prod32)
begin
MULU_tmp(31 downto 12) <= std_logic_vector((unsigned(MULU_Fakt1)*unsigned(MULU_Prod32(3 downto 0)))+unsigned("0000"&MULU_Prod32(31 downto 16)));
MULU_tmp(11 downto 0) <= MULU_Prod32(15 downto 4);
if rising_edge(CLK_n) then
if ClkEn = '1' then
if T_Res='1' then
if I_MULUB='1' then
MULU_Prod32(7 downto 0) <= ACC;
MULU_Prod32(15 downto 8) <= "--------";
MULU_Prod32(31 downto 16) <= X"0000";
MULU_Fakt1(7 downto 0) <= "00000000";
if Set_BusB_To(0) = '1' then
MULU_Fakt1(15 downto 8) <= RegBusB(7 downto 0);
else
MULU_Fakt1(15 downto 8) <= RegBusB(15 downto 8);
end if;
else
MULU_Prod32(15 downto 0) <= RegBusA;
MULU_Prod32(31 downto 16) <= X"0000";
MULU_Fakt1 <= RegBusB;
end if;
else
MULU_Prod32 <= MULU_tmp;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if rising_edge(CLK_n) then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when (ExchangeDH = '1' or I_MULU = '1') and TState = 4 else
-- LDHLSP
"010" when LDHLSP = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, I_MULU, T_Res,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if I_MULU = '1' and (T_Res = '1' or TState = 4) then -- TState = 4 DE write
RegWEH <= '1';
RegWEL <= '1';
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if LDHLSP = '1' and MCycle = "010" and TState = 4 then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux)));
process (Save_Mux, RegBusB, RegBusA_r, ID16, I_MULU, MULU_Prod32, MULU_tmp, T_Res,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP, TmpAddr2)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if I_MULU = '1' then
if T_Res = '1' then
RegDIH <= MULU_Prod32(31 downto 24);
RegDIL <= MULU_Prod32(23 downto 16);
else
RegDIH <= MULU_tmp(15 downto 8); -- TState = 4 DE write
RegDIL <= MULU_tmp(7 downto 0);
end if;
end if;
if LDHLSP = '1' and MCycle = "010" and TState = 4 then
RegDIH <= TmpAddr2(15 downto 8);
RegDIL <= TmpAddr2(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0),
DOR => DOR,
DIRSet => DIRSet,
DIR => DIR(207 downto 80));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if rising_edge(CLK_n) then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
if IR = x"71" and out0 = '1' then
BusB <= "11111111";
else
BusB <= "00000000";
end if;
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif rising_edge(CLK_n) then
if DIRSet = '0' and CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not (BusAck and RESET_n);
IntCycle_n <= not IntCycle;
NMICycle_n <= not NMICycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
--BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
--BusReq_s <= '0';
NMI_s <= '0';
elsif rising_edge(CLK_n) then
if DIRSet = '1' then
IntE_FF2 <= DIR(211);
IntE_FF1 <= DIR(210);
else
if NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
Auto_Wait_t2 <= Auto_Wait_t1;
if T_Res = '1' then
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
else
Auto_Wait_t1 <= Auto_Wait or IORQ_i;
end if;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' and ( not(Mode = 3 and INT_n = '0' and IntE_FF1 = '0')) then -- halt bug when Mode = 3 , INT_n = '0' and IME=0
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if (IntCycle = '1' and Mode = 3) then -- GB: read interrupt at MCycle 3
if (MCycle = "010") then
M1_n <= '0';
else
M1_n <= '1';
end if;
end if;
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or (MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or No_BTR = '1' or (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMI_s <= '0';
NMICycle <= '1';
IntE_FF1 <= '0';
elsif IntE_FF1 = '1' and INT_n='0' and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
elsif (Halt_FF = '1' and INT_n = '0' and Mode = 3) then
Halt_FF <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end if;
end process;
Auto_Wait <= '1' when IntCycle = '1' and MCycle = "001" else '0';
end;
|
gpl-3.0
|
fb1aada81be7a0db386cdc355493a511
| 0.503807 | 2.940307 | false | false | false | false |
hoglet67/AtomBusMon
|
src/MOS6502CpuMonLX9.vhd
| 2 | 4,255 |
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : MOS6502CpuMonLX9.vhd
-- /___/ /\ Timestamp : 03/11/2019
-- \ \ / \
-- \___\/\___\
--
--Design Name: MOS6502CpuMonLX9
--Device: XC6SLX9
--
-- Note: in 65C02 mode, BE, ML_n and VP_n are not implemented
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity MOS6502CpuMonLX9 is
generic (
UseT65Core : boolean := true;
UseAlanDCore : boolean := false;
num_comparators : integer := 8;
avr_prog_mem_size : integer := 8 * 1024
);
port (
clock : in std_logic;
-- 6502 Signals
Phi0 : in std_logic;
Phi1 : out std_logic;
Phi2 : out std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
Sync : out std_logic;
Addr : out std_logic_vector(15 downto 0);
R_W_n : out std_logic;
Data : inout std_logic_vector(7 downto 0);
SO_n : in std_logic;
Res_n : in std_logic;
Rdy : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Jumpers
fakeTube_n : in std_logic;
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw1 : in std_logic;
sw2 : in std_logic;
-- LEDs
led3 : out std_logic;
led6 : out std_logic;
led8 : out std_logic;
-- OHO_DY1 LED display
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end MOS6502CpuMonLX9;
architecture behavioral of MOS6502CpuMonLX9 is
signal sw_reset_cpu : std_logic;
signal sw_reset_avr : std_logic;
signal led_bkpt : std_logic;
signal led_trig0 : std_logic;
signal led_trig1 : std_logic;
begin
sw_reset_cpu <= sw1;
sw_reset_avr <= sw2;
led8 <= led_bkpt;
led3 <= led_trig0;
led6 <= led_trig1;
wrapper : entity work.MOS6502CpuMon
generic map (
UseT65Core => UseT65Core,
UseAlanDCore => UseAlanDCore,
ClkMult => 8,
ClkDiv => 25,
ClkPer => 20.000,
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock => clock,
-- 6502 Signals
Phi0 => Phi0,
Phi1 => Phi1,
Phi2 => Phi2,
IRQ_n => IRQ_n,
NMI_n => NMI_n,
Sync => Sync,
Addr => Addr,
R_W_n => R_W_n,
Data => Data,
SO_n => SO_n,
Res_n => Res_n,
Rdy => Rdy,
-- External trigger inputs
trig => trig,
-- Jumpers
fakeTube_n => fakeTube_n,
-- Serial Console
avr_RxD => avr_RxD,
avr_TxD => avr_TxD,
-- Switches
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
-- LEDs
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
-- OHO_DY1 LED display
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk
);
end behavioral;
|
gpl-3.0
|
890877d4dc97e8e9621f79401cec33e7
| 0.381434 | 4.135083 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd
| 1 | 16,878 |
-------------------------------------------------------------------------------
-- White Rabbit Switch / GSI BEL
-------------------------------------------------------------------------------
--
-- unit name: Parallel-In/Serial-Out shift register
--
-- author: Mathias Kreider, [email protected]
--
-- date: $Date:: $:
--
-- version: $Rev:: $:
--
-- description: <file content, behaviour, purpose, special usage notes...>
-- <further description>
--
-- dependencies: <entity name>, ...
--
-- references: <reference one>
-- <reference two> ...
--
-- modified by: $Author:: $:
--
-------------------------------------------------------------------------------
-- last changes: <date> <initials> <log>
-- <extended description>
-------------------------------------------------------------------------------
-- TODO: <next thing to do>
-- <another thing to do>
--
-- This code is subject to GPL
-------------------------------------------------------------------------------
-- Modified by Lucas Russo <[email protected]>.
-- Simple convertion of regular pipelined wishbone to wishbone streaming
-- fabric used by etherbone (32-bit to 16-bit data).
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity xwb_ethmac_adapter is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in;
tx_ram_o : out t_wishbone_master_out;
tx_ram_i : in t_wishbone_master_in;
rx_ram_o : out t_wishbone_master_out;
rx_ram_i : in t_wishbone_master_in;
--rx_eb_o : out t_wishbone_master_out;
--rx_eb_i : in t_wishbone_master_in;
--
--tx_eb_i : in t_wishbone_slave_in;
--tx_eb_o : out t_wishbone_slave_out;
rx_eb_o : out t_wrf_source_out;
rx_eb_i : in t_wrf_source_in;
tx_eb_o : out t_wrf_sink_out;
tx_eb_i : in t_wrf_sink_in;
irq_tx_done_o : out std_logic;
irq_rx_done_o : out std_logic
);
end xwb_ethmac_adapter;
architecture behavioral of xwb_ethmac_adapter is
--function f_ceil_log2(x : natural) return natural is
--begin
-- if x <= 2
-- then return 1;
-- else
-- return f_ceil_log2((x+1)/2) +1;
-- end if;
--end f_ceil_log2;
--constant c_ram_width : natural := 32;
--constant c_wrf_width : natural := 16;
--constant c_counter_full : natural := c_ram_width/c_wrf_width;
--constant c_counter_msb : natural := f_ceil_log2(c_ram_width/c_wrf_width);
-- Wishbone Interface
signal ctrl : std_logic_vector(31 downto 0); --x00
alias buffers_rdy : std_logic is ctrl(0);
signal base_adr_rx : std_logic_vector(31 downto 0); --x04
signal base_adr_tx : std_logic_vector(31 downto 0); --x08
signal length_rx : std_logic_vector(31 downto 0); --c
signal bytes_rx : std_logic_vector(31 downto 0); --c
signal bytes_tx : std_logic_vector(31 downto 0); --c
signal rx_done : std_logic;
signal eb_stall : std_logic;
signal wb_adr : std_logic_vector(31 downto 0);
alias adr : std_logic_vector(7 downto 0) is wb_adr(7 downto 0);
-- Dma Controller
signal irq_tx_done : std_logic;
signal irq_rx_done : std_logic;
type fsm is (idle, init, transfer, waiting, done);
signal state_tx : fsm;
signal state_rx : fsm;
signal rx_counter : unsigned(15 downto 0);
signal tx_counter : unsigned(31 downto 0);
-- Internal Streaming interface
--signal rx_eb32_i : t_wrf_source32_in;
--signal rx_eb32_o : t_wrf_source32_out;
signal rx_eb32_i : t_wishbone_master_in;
signal rx_eb32_o : t_wishbone_master_out;
--signal tx_eb32_i : t_wrf_sink32_in;
--signal tx_eb32_o : t_wrf_sink32_out;
signal tx_eb32_i : t_wishbone_slave_in;
signal tx_eb32_o : t_wishbone_slave_out;
-- word counter
--signal transfer_counter : unsigned(c_ram_width/c_wrf_width-1 downto 0);
--signal transfer_in_progress : std_logic;
signal rx_ram_dat_reg : std_logic_vector(31 downto 0);
-- From the etherbone repository
component WB_bus_adapter_streaming_sg
generic(g_adr_width_A : natural := 16; g_adr_width_B : natural := 32;
g_dat_width_A : natural := 16; g_dat_width_B : natural := 32;
g_pipeline : natural := 2
);
-- pipeline: 0 => A-x, 1 x-B, 2 A-B
port(
clk_i : in std_logic;
nRst_i : in std_logic;
A_CYC_i : in std_logic;
A_STB_i : in std_logic;
A_ADR_i : in std_logic_vector(g_adr_width_A-1 downto 0);
A_SEL_i : in std_logic_vector(g_dat_width_A/8-1 downto 0);
A_WE_i : in std_logic;
A_DAT_i : in std_logic_vector(g_dat_width_A-1 downto 0);
A_ACK_o : out std_logic;
A_ERR_o : out std_logic;
A_RTY_o : out std_logic;
A_STALL_o : out std_logic;
A_DAT_o : out std_logic_vector(g_dat_width_A-1 downto 0);
B_CYC_o : out std_logic;
B_STB_o : out std_logic;
B_ADR_o : out std_logic_vector(g_adr_width_B-1 downto 0);
B_SEL_o : out std_logic_vector(g_dat_width_B/8-1 downto 0);
B_WE_o : out std_logic;
B_DAT_o : out std_logic_vector(g_dat_width_B-1 downto 0);
B_ACK_i : in std_logic;
B_ERR_i : in std_logic;
B_RTY_i : in std_logic;
B_STALL_i : in std_logic;
B_DAT_i : in std_logic_vector(g_dat_width_B-1 downto 0)
);
end component;
begin
wb_adr <= wb_slave_i.adr;
wishbone_if : process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(rstn_i = '0') then
ctrl <= (others => '0');
base_adr_tx <= (others => '0');
base_adr_rx <= (others => '0');
length_rx <= (others => '0');
--length_tx <= (others => '0');
wb_slave_o <= (
ack => '0',
err => '0',
rty => '0',
stall => '0',
int => '0',
dat => (others => '0'));
else
wb_slave_o.ack <= wb_slave_i.cyc and wb_slave_i.stb;
wb_slave_o.dat <= (others => '0');
ctrl <= (others => '0');
if(wb_slave_i.we ='1') then
case adr is
when x"00" => ctrl <= wb_slave_i.dat and x"00000001";
when x"04" => base_adr_tx <= wb_slave_i.dat;
when x"08" => base_adr_rx <= wb_slave_i.dat;
when x"0C" => length_rx <= wb_slave_i.dat;
when others => null;
end case;
else
-- set output to zero so all bits are driven
case adr is
--when x"00" => ctrl <= wb_slave_i.dat and x"00000003";
when x"04" => wb_slave_o.dat <= base_adr_tx;
when x"08" => wb_slave_o.dat <= base_adr_rx;
when x"0C" => wb_slave_o.dat <= length_rx;
when x"10" => wb_slave_o.dat <= bytes_rx;
when x"14" => wb_slave_o.dat <= bytes_tx;
when others => null;
end case;
end if;
end if;
end if;
end process;
------------------------------------------
tx_eb32_o.stall <= tx_ram_i.stall;
tx_eb32_o.ack <= tx_ram_i.ack;
tx_ram_o.cyc <= tx_eb32_i.cyc;
tx_ram_o.stb <= tx_eb32_i.stb;
tx_ram_o.dat <= tx_eb32_i.dat;
tx_ram_o.adr <= std_logic_vector(tx_counter);
tx_ram_o.we <= '1';
tx_ram_o.sel <= (others => '1');
irq_tx_done_o <= irq_tx_done;
bytes_tx <= std_logic_vector(tx_counter);
-- convert streaming output from 16 to 32 bit data width
cmp_tx_adapter_16_to_32: WB_bus_adapter_streaming_sg
generic map (
g_adr_width_A => 2,
g_adr_width_B => 32,
g_dat_width_A => 16,
g_dat_width_B => 32,
g_pipeline => 3
)
port map (
clk_i => clk_i,
nRst_i => rstn_i,
A_CYC_i => tx_eb_i.cyc,
A_STB_i => tx_eb_i.stb,
A_ADR_i => tx_eb_i.adr,
A_SEL_i => tx_eb_i.sel,
A_WE_i => tx_eb_i.we,
A_DAT_i => tx_eb_i.dat,
A_ACK_o => tx_eb_o.ack,
A_ERR_o => tx_eb_o.err,
A_RTY_o => tx_eb_o.rty,
A_STALL_o => tx_eb_o.stall,
A_DAT_o => open,
B_CYC_o => tx_eb32_i.cyc,
B_STB_o => tx_eb32_i.stb,
B_ADR_o => tx_eb32_i.adr,
B_SEL_o => tx_eb32_i.sel,
B_WE_o => tx_eb32_i.we,
B_DAT_o => tx_eb32_i.dat,
B_ACK_i => tx_eb32_o.ack,
B_ERR_i => tx_eb32_o.err,
B_RTY_i => tx_eb32_o.rty,
B_STALL_i => tx_eb32_o.stall,
B_DAT_i => (others => '0')
);
dma_tx : process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(rstn_i = '0') then
tx_eb32_o.err <= '0';
tx_eb32_o.rty <= '0';
--tx_eb_o.dat <= (others => '0');
rx_ram_dat_reg <= (others => '0');
irq_tx_done <= '0';
tx_counter <= (others => '0');
state_tx <= idle;
else
case state_tx is
when idle =>
if(buffers_rdy = '1') then -- rx is already receiving and the ebcore wants to send an answer
state_tx <= init;
end if;
when init =>
irq_tx_done <= '0';
tx_counter <= unsigned(base_adr_tx); -- reply must be the same length than request
state_tx <= transfer;
when transfer =>
if((tx_counter < unsigned(length_rx)+unsigned(base_adr_tx)) and tx_eb32_i.cyc = '1') then
if(tx_eb32_i.stb = '1' and tx_ram_i.stall = '0') then
tx_counter <= tx_counter + 4;
end if;
else
state_tx <= done;
end if;
when done =>
irq_tx_done <= '1';
state_tx <= idle;
when others =>
state_tx <= idle;
end case;
end if;
end if;
end process;
irq_rx_done_o <= irq_rx_done;
rx_done <= '0' when (rx_counter < (unsigned(length_rx(15 downto 0))+unsigned(base_adr_rx(15 downto 0))))
else '1';
--transfer_in_progress <= '1' when state_rx = transfer and transfer_counter_full = '0';
--transfer_counter_full <= '1' when transfer_counter = c_counter_full else '0';
rx_ram_o.stb <= not (rx_eb32_i.stall) and not rx_done;
--rx_ram_o.stb <= not (rx_eb_i.stall) and not rx_done and w_counter_full;
rx_ram_o.adr <= std_logic_vector(resize(rx_counter, 32));
rx_eb32_o.dat <= rx_ram_i.dat;
--rx_eb_o.dat <= ;
rx_eb32_o.stb <= rx_ram_i.ack;
--rx_eb_o.stb <= ;
bytes_rx <= std_logic_vector(resize(rx_counter, 32));
-- convert streaming input from 16 to 32 bit data width
cmp_rx_adapter_32_to_16: WB_bus_adapter_streaming_sg
generic map (
g_adr_width_A => 32,
g_adr_width_B => 2,
g_dat_width_A => 32,
g_dat_width_B => 16,
g_pipeline => 3
)
port map (
clk_i => clk_i,
nRst_i => rstn_i,
A_CYC_i => rx_eb32_o.cyc,
A_STB_i => rx_eb32_o.stb,
A_ADR_i => rx_eb32_o.adr,
A_SEL_i => rx_eb32_o.sel,
A_WE_i => rx_eb32_o.we,
A_DAT_i => rx_eb32_o.dat,
A_ACK_o => rx_eb32_i.ack,
A_ERR_o => rx_eb32_i.err,
A_RTY_o => rx_eb32_i.rty,
A_STALL_o => rx_eb32_i.stall,
A_DAT_o => open,
B_CYC_o => rx_eb_o.cyc,
B_STB_o => rx_eb_o.stb,
B_ADR_o => rx_eb_o.adr,
B_SEL_o => rx_eb_o.sel,
B_WE_o => rx_eb_o.we,
B_DAT_o => rx_eb_o.dat,
B_ACK_i => rx_eb_i.ack,
B_ERR_i => rx_eb_i.err,
B_RTY_i => rx_eb_i.rty,
B_STALL_i => rx_eb_i.stall,
B_DAT_i => (others => '0')
);
dma_rx : process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(rstn_i = '0') then
state_rx <= idle;
irq_rx_done <= '0';
rx_counter <= (others => '0');
--transfer_counter <= (others => '0');
--transfer_in_progress <= '0';
rx_ram_o.cyc <= '0';
rx_ram_o.we <= '0';
rx_ram_o.sel <= (others => '1');
rx_ram_o.dat <= (others => '0');
rx_eb32_o.cyc <= '0';
rx_eb32_o.we <= '1';
rx_eb32_o.sel <= (others => '1');
--rx_eb_o.adr <= (others => '0');
rx_eb32_o.adr <= std_logic_vector(resize(unsigned(c_WRF_DATA), rx_eb32_o.adr'length));
eb_stall <= '0';
else
eb_stall <= rx_eb32_i.stall;
case state_rx is
when idle =>
if(buffers_rdy ='1') then
state_rx <= init;
end if;
when init =>
irq_rx_done <= '0';
rx_counter <= unsigned(base_adr_rx(15 downto 0));
rx_ram_o.cyc <= '1';
rx_eb32_o.cyc <= '1';
state_rx <= transfer;
when transfer =>
--if (rx_done = '0') then --- all rx done
-- rx_ram_data_int <= rx_ram_i.dat;
-- rx_ram_valid_int <= rx_ram_i.ack;
--
-- if(rx_eb_i.stall = '0' and eb_stall = '0') then
--
--
-- if(rx_ram_i.stall = '0' and and transfer_counter_full = '1') then
-- rx_counter <= rx_counter + 4;
-- end if;
--else
-- state_rx <= done;
-- rx_ram_o.cyc <= '0';
--end if;
--
--if (transfer_counter_full = '0') then
-- transfer_counter <= transfer_counter + 1;
--else
-- transfer_counter <= (others => '0');
--end if;
if (rx_done = '0') then --- all rx done
if(rx_ram_i.stall = '0' and rx_eb32_i.stall = '0' and eb_stall = '0') then
rx_counter <= rx_counter + 4;
end if;
else
state_rx <= done;
rx_ram_o.cyc <= '0';
end if;
when done =>
rx_eb32_o.cyc <= '0';
irq_rx_done <= '1';
state_rx <= idle;
when others =>
state_rx <= idle;
end case;
end if;
end if;
end process;
end behavioral;
|
lgpl-3.0
|
ad1faab1598c6afaba9f8fb7c7a2565f
| 0.40929 | 3.516983 | false | false | false | false |
huljar/klein-vhdl
|
src/util.vhd
| 1 | 618 |
library ieee;
use ieee.std_logic_1164.all;
package util is
type key_enum is (K_64, K_80, K_96);
type key_lookup is array(key_enum) of natural;
constant key_bits: key_lookup := (
K_64 => 64,
K_80 => 80,
K_96 => 96
);
type rc_lookup is array(key_enum) of std_logic_vector(4 downto 0);
constant final_rc: rc_lookup := (
K_64 => "01101",
K_80 => "10001",
K_96 => "10101"
);
type round_lookup is array(key_enum) of natural;
constant rounds: round_lookup := (
K_64 => 12,
K_80 => 16,
K_96 => 20
);
end package;
|
mit
|
fbe3891d9013701b16ae416982508d81
| 0.530744 | 3.121212 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/cpu/t80_mcode.vhd
| 2 | 101,512 |
--
-- Z80 compatible microprocessor core
--
-- Version : 0249
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0235 : Added IM 2 fix by Mike Johnson
--
-- 0238 : Added NoRead signal
--
-- 0238b: Fixed instruction timing for POP and DJNZ
--
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
--
-- 0242 : Fixed I/O instruction timing, cleanup
--
-- 0242a: 31st of August, 2003 by Kazuhiro Tsujikawa ([email protected])
-- Fixed INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR instructions
--
-- 0248 : add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
--
-- 0249 : add undocumented XY-Flags for CPI/CPD by TobiFlex 22.07.2012
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_MCode is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,CB,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
ALU_cpi : out std_logic; --for undoc XY-Flags
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end T80_MCode;
architecture rtl of T80_MCode is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
cc : bit_vector(2 downto 0)
) return boolean is
begin
if Mode = 3 then
case cc is
when "000" => return F(7) = '0'; -- NZ
when "001" => return F(7) = '1'; -- Z
when "010" => return F(4) = '0'; -- NC
when "011" => return F(4) = '1'; -- C
when "100" => return false;
when "101" => return false;
when "110" => return false;
when "111" => return false;
end case;
else
case cc is
when "000" => return F(6) = '0'; -- NZ
when "001" => return F(6) = '1'; -- Z
when "010" => return F(0) = '0'; -- NC
when "011" => return F(0) = '1'; -- C
when "100" => return F(2) = '0'; -- PO
when "101" => return F(2) = '1'; -- PE
when "110" => return F(7) = '0'; -- P
when "111" => return F(7) = '1'; -- M
end case;
end if;
end;
begin
process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
variable DDD : std_logic_vector(2 downto 0);
variable SSS : std_logic_vector(2 downto 0);
variable DPair : std_logic_vector(1 downto 0);
variable IRB : bit_vector(7 downto 0);
begin
DDD := IR(5 downto 3);
SSS := IR(2 downto 0);
DPair := IR(5 downto 4);
IRB := to_bitvector(IR);
MCycles <= "001";
if MCycle = "001" then
TStates <= "100";
else
TStates <= "011";
end if;
Prefix <= "00";
Inc_PC <= '0';
Inc_WZ <= '0';
IncDec_16 <= "0000";
Read_To_Acc <= '0';
Read_To_Reg <= '0';
Set_BusB_To <= "0000";
Set_BusA_To <= "0000";
ALU_Op <= "0" & IR(5 downto 3);
ALU_cpi <= '0';
Save_ALU <= '0';
PreserveC <= '0';
Arith16 <= '0';
IORQ <= '0';
Set_Addr_To <= aNone;
Jump <= '0';
JumpE <= '0';
JumpXY <= '0';
Call <= '0';
RstP <= '0';
LDZ <= '0';
LDW <= '0';
LDSPHL <= '0';
Special_LD <= "000";
ExchangeDH <= '0';
ExchangeRp <= '0';
ExchangeAF <= '0';
ExchangeRS <= '0';
I_DJNZ <= '0';
I_CPL <= '0';
I_CCF <= '0';
I_SCF <= '0';
I_RETN <= '0';
I_BT <= '0';
I_BC <= '0';
I_BTR <= '0';
I_RLD <= '0';
I_RRD <= '0';
I_INRC <= '0';
SetDI <= '0';
SetEI <= '0';
IMode <= "11";
Halt <= '0';
NoRead <= '0';
Write <= '0';
XYbit_undoc <= '0';
case ISet is
when "00" =>
------------------------------------------------------------------------------
--
-- Unprefixed instructions
--
------------------------------------------------------------------------------
case IRB is
-- 8 BIT LOAD GROUP
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- LD r,r'
Set_BusB_To(2 downto 0) <= SSS;
ExchangeRp <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
-- LD r,n
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
-- LD r,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
when others => null;
end case;
when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
-- LD (HL),r
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110110" =>
-- LD (HL),n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aXY;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
when 3 =>
Write <= '1';
when others => null;
end case;
when "00001010" =>
-- LD A,(BC)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00011010" =>
-- LD A,(DE)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
when 2 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "00111010" =>
if Mode = 3 then
-- LDD A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end if;
when "00000010" =>
-- LD (BC),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00010010" =>
-- LD (DE),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aDE;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
when others => null;
end case;
when "00110010" =>
if Mode = 3 then
-- LDD (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "1110";
when others => null;
end case;
else
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
end if;
-- 16 BIT LOAD GROUP
when "00000001"|"00010001"|"00100001"|"00110001" =>
-- LD dd,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1000";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
Inc_PC <= '1';
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1001";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "00101010" =>
if Mode = 3 then
-- LDI A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Acc <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD HL,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end if;
when "00100010" =>
if Mode = 3 then
-- LDI (HL),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IncDec_16 <= "0110";
when others => null;
end case;
else
-- LD (nn),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "0101"; -- L
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "0100"; -- H
when 5 =>
Write <= '1';
when others => null;
end case;
end if;
when "11111001" =>
-- LD SP,HL
TStates <= "110";
LDSPHL <= '1';
when "11000101"|"11010101"|"11100101"|"11110101" =>
-- PUSH qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "0111";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 2 =>
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
if DPAIR = "11" then
Set_BusB_To <= "1011";
else
Set_BusB_To(2 downto 1) <= DPAIR;
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
Write <= '1';
when 3 =>
Write <= '1';
when others => null;
end case;
when "11000001"|"11010001"|"11100001"|"11110001" =>
-- POP qq
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "1011";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '1';
end if;
when 3 =>
IncDec_16 <= "0111";
Read_To_Reg <= '1';
if DPAIR = "11" then
Set_BusA_To(3 downto 0) <= "0111";
else
Set_BusA_To(2 downto 1) <= DPAIR;
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
when "11101011" =>
if Mode /= 3 then
-- EX DE,HL
ExchangeDH <= '1';
end if;
when "00001000" =>
if Mode = 3 then
-- LD (nn),SP
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
Set_BusB_To <= "1000";
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
Set_BusB_To <= "1001";
when 5 =>
Write <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EX AF,AF'
ExchangeAF <= '1';
end if;
when "11011001" =>
if Mode = 3 then
-- RETI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
SetEI <= '1';
when others => null;
end case;
elsif Mode < 2 then
-- EXX
ExchangeRS <= '1';
end if;
when "11100011" =>
if Mode /= 3 then
-- EX (SP),HL
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aSP;
when 2 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0101";
Set_BusB_To <= "0101";
Set_Addr_To <= aSP;
when 3 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
TStates <= "100";
Write <= '1';
when 4 =>
Read_To_Reg <= '1';
Set_BusA_To <= "0100";
Set_BusB_To <= "0100";
Set_Addr_To <= aSP;
when 5 =>
IncDec_16 <= "1111";
TStates <= "101";
Write <= '1';
when others => null;
end case;
end if;
-- 8 BIT ARITHMETIC AND LOGICAL GROUP
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- ADD A,r
-- ADC A,r
-- SUB A,r
-- SBC A,r
-- AND A,r
-- OR A,r
-- XOR A,r
-- CP A,r
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
Save_ALU <= '1';
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- ADD A,(HL)
-- ADC A,(HL)
-- SUB A,(HL)
-- SBC A,(HL)
-- AND A,(HL)
-- OR A,(HL)
-- XOR A,(HL)
-- CP A,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
when others => null;
end case;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- ADD A,n
-- ADC A,n
-- SUB A,n
-- SBC A,n
-- AND A,n
-- OR A,n
-- XOR A,n
-- CP A,n
MCycles <= "010";
if MCycle = "010" then
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusB_To(2 downto 0) <= SSS;
Set_BusA_To(2 downto 0) <= "111";
end if;
when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
-- INC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
when "00110100" =>
-- INC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0000";
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
-- DEC r
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
ALU_Op <= "0010";
when "00110101" =>
-- DEC (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
when 2 =>
TStates <= "100";
Set_Addr_To <= aXY;
ALU_Op <= "0010";
Read_To_Reg <= '1';
Save_ALU <= '1';
PreserveC <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= DDD;
when 3 =>
Write <= '1';
when others => null;
end case;
-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
when "00100111" =>
-- DAA
Set_BusA_To(2 downto 0) <= "111";
Read_To_Reg <= '1';
ALU_Op <= "1100";
Save_ALU <= '1';
when "00101111" =>
-- CPL
I_CPL <= '1';
when "00111111" =>
-- CCF
I_CCF <= '1';
when "00110111" =>
-- SCF
I_SCF <= '1';
when "00000000" =>
if NMICycle = '1' then
-- NMI
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when others => null;
end case;
elsif IntCycle = '1' then
-- INT (IM 2)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 1 =>
LDZ <= '1';
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
TStates <= "100";
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
TStates <= "100";
Write <= '1';
when 4 =>
Inc_PC <= '1';
LDZ <= '1';
when 5 =>
Jump <= '1';
when others => null;
end case;
else
-- NOP
end if;
when "01110110" =>
-- HALT
Halt <= '1';
when "11110011" =>
-- DI
SetDI <= '1';
when "11111011" =>
-- EI
SetEI <= '1';
-- 16 BIT ARITHMETIC GROUP
when "00001001"|"00011001"|"00101001"|"00111001" =>
-- ADD HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
Arith16 <= '1';
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
Arith16 <= '1';
when others =>
end case;
when "00000011"|"00010011"|"00100011"|"00110011" =>
-- INC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "01";
IncDec_16(1 downto 0) <= DPair;
when "00001011"|"00011011"|"00101011"|"00111011" =>
-- DEC ss
TStates <= "110";
IncDec_16(3 downto 2) <= "11";
IncDec_16(1 downto 0) <= DPair;
-- ROTATE AND SHIFT GROUP
when "00000111"
-- RLCA
|"00010111"
-- RLA
|"00001111"
-- RRCA
|"00011111" =>
-- RRA
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
-- JUMP GROUP
when "11000011" =>
-- JP nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
Jump <= '1';
when others => null;
end case;
when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+C),A
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "0111";
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "01" =>
-- LD (nn),A
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
Set_BusB_To <= "0111";
when 4 =>
Write <= '1';
when others => null;
end case;
when "10" =>
-- LD A,($FF00+C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others =>
end case;
when "11" =>
-- LD A,(nn)
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
when 4 =>
Read_To_Acc <= '1';
when others => null;
end case;
end case;
else
-- JP cc,nn
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Jump <= '1';
end if;
when others => null;
end case;
end if;
when "00011000" =>
if Mode /= 2 then
-- JR e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00111000" =>
if Mode /= 2 then
-- JR C,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00110000" =>
if Mode /= 2 then
-- JR NC,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_C) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00101000" =>
if Mode /= 2 then
-- JR Z,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '0' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "00100000" =>
if Mode /= 2 then
-- JR NZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
if F(Flag_Z) = '1' then
MCycles <= "010";
end if;
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
when "11101001" =>
-- JP (HL)
JumpXY <= '1';
when "00010000" =>
if Mode = 3 then
I_DJNZ <= '1';
elsif Mode < 2 then
-- DJNZ,e
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
I_DJNZ <= '1';
Set_BusB_To <= "1010";
Set_BusA_To(2 downto 0) <= "000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
I_DJNZ <= '1';
Inc_PC <= '1';
when 3 =>
NoRead <= '1';
JumpE <= '1';
TStates <= "101";
when others => null;
end case;
end if;
-- CALL AND RETURN GROUP
when "11001101" =>
-- CALL nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
IncDec_16 <= "1111";
Inc_PC <= '1';
TStates <= "100";
Set_Addr_To <= aSP;
LDW <= '1';
Set_BusB_To <= "1101";
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
if IR(5) = '0' or Mode /= 3 then
-- CALL cc,nn
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Inc_PC <= '1';
LDW <= '1';
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
IncDec_16 <= "1111";
Set_Addr_TO <= aSP;
TStates <= "100";
Set_BusB_To <= "1101";
else
MCycles <= "011";
end if;
when 4 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 5 =>
Write <= '1';
Call <= '1';
when others => null;
end case;
end if;
when "11001001" =>
-- RET
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
if IR(5) = '1' and Mode = 3 then
case IRB(4 downto 3) is
when "00" =>
-- LD ($FF00+nn),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
when others => null;
end case;
when "01" =>
-- ADD SP,n
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
ALU_Op <= "0000";
Inc_PC <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To <= "1000";
Set_BusB_To <= "0110";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To <= "1001";
Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
when others =>
end case;
when "10" =>
-- LD A,($FF00+nn)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
when others => null;
end case;
when "11" =>
-- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Set_BusA_To(2 downto 0) <= "101"; -- L
Read_To_Reg <= '1';
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Set_BusA_To(2 downto 0) <= "100"; -- H
Read_To_Reg <= '1';
when others => null;
end case;
end case;
else
-- RET cc
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
Set_Addr_TO <= aSP;
else
MCycles <= "001";
end if;
TStates <= "101";
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
when others => null;
end case;
end if;
when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
-- RST p
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1101";
when 2 =>
Write <= '1';
IncDec_16 <= "1111";
Set_Addr_To <= aSP;
Set_BusB_To <= "1100";
when 3 =>
Write <= '1';
RstP <= '1';
when others => null;
end case;
-- INPUT AND OUTPUT GROUP
when "11011011" =>
if Mode /= 3 then
-- IN A,(n)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
when 3 =>
Read_To_Acc <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
when "11010011" =>
if Mode /= 3 then
-- OUT (n),A
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
Set_Addr_To <= aIOA;
Set_BusB_To <= "0111";
when 3 =>
Write <= '1';
IORQ <= '1';
when others => null;
end case;
end if;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- MULTIBYTE INSTRUCTIONS
------------------------------------------------------------------------------
------------------------------------------------------------------------------
when "11001011" =>
if Mode /= 2 then
Prefix <= "01";
end if;
when "11101101" =>
if Mode < 2 then
Prefix <= "10";
end if;
when "11011101"|"11111101" =>
if Mode < 2 then
Prefix <= "11";
end if;
end case;
when "01" =>
------------------------------------------------------------------------------
--
-- CB prefixed instructions
--
------------------------------------------------------------------------------
Set_BusA_To(2 downto 0) <= IR(2 downto 0);
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
-- RLC r
-- RL r
-- RRC r
-- RR r
-- SLA r
-- SRA r
-- SRL r
-- SLL r (Undocumented) / SWAP r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- R/S (IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
-- RLC (HL)
-- RL (HL)
-- RRC (HL)
-- RR (HL)
-- SRA (HL)
-- SRL (HL)
-- SLA (HL)
-- SLL (HL) (Undocumented) / SWAP (HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1000";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others =>
end case;
when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
|"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
|"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
|"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
|"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
|"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
|"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
|"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
-- BIT b,r
if XY_State="00" then
if MCycle = "001" then
Set_BusB_To(2 downto 0) <= IR(2 downto 0);
ALU_Op <= "1001";
end if;
else
-- BIT b,(IX+d), undocumented
MCycles <= "010";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
end if;
when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
-- SET b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- SET b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
|"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
|"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
|"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
|"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
-- RES b,r
if XY_State="00" then
if MCycle = "001" then
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
end if;
else
-- RES b,(IX+d),Reg, undocumented
MCycles <= "011";
XYbit_undoc <= '1';
case to_integer(unsigned(MCycle)) is
when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end if;
when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
-- RES b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 | 7 =>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_Addr_To <= aXY;
TStates <= "100";
when 3 =>
Write <= '1';
when others => null;
end case;
end case;
when others =>
------------------------------------------------------------------------------
--
-- ED prefixed instructions
--
------------------------------------------------------------------------------
case IRB is
when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
|"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
|"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
|"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
|"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
|"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
|"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
|"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
|"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
|"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
|"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
| "10100100"|"10100101"|"10100110"|"10100111"
| "10101100"|"10101101"|"10101110"|"10101111"
| "10110100"|"10110101"|"10110110"|"10110111"
| "10111100"|"10111101"|"10111110"|"10111111"
|"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
|"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
|"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
|"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
|"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
|"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
|"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
null; -- NOP, undocumented
when "01111110"|"01111111" =>
-- NOP, undocumented
null;
-- 8 BIT LOAD GROUP
when "01010111" =>
-- LD A,I
Special_LD <= "100";
TStates <= "101";
when "01011111" =>
-- LD A,R
Special_LD <= "101";
TStates <= "101";
when "01000111" =>
-- LD I,A
Special_LD <= "110";
TStates <= "101";
when "01001111" =>
-- LD R,A
Special_LD <= "111";
TStates <= "101";
-- 16 BIT LOAD GROUP
when "01001011"|"01011011"|"01101011"|"01111011" =>
-- LD dd,(nn)
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
when 4 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1000";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '1';
end if;
Inc_WZ <= '1';
Set_Addr_To <= aZI;
when 5 =>
Read_To_Reg <= '1';
if IR(5 downto 4) = "11" then
Set_BusA_To <= "1001";
else
Set_BusA_To(2 downto 1) <= IR(5 downto 4);
Set_BusA_To(0) <= '0';
end if;
when others => null;
end case;
when "01000011"|"01010011"|"01100011"|"01110011" =>
-- LD (nn),dd
MCycles <= "101";
case to_integer(unsigned(MCycle)) is
when 2 =>
Inc_PC <= '1';
LDZ <= '1';
when 3 =>
Set_Addr_To <= aZI;
Inc_PC <= '1';
LDW <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1000";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
Set_BusB_To(3) <= '0';
end if;
when 4 =>
Inc_WZ <= '1';
Set_Addr_To <= aZI;
Write <= '1';
if IR(5 downto 4) = "11" then
Set_BusB_To <= "1001";
else
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
Set_BusB_To(3) <= '0';
end if;
when 5 =>
Write <= '1';
when others => null;
end case;
when "10100000" | "10101000" | "10110000" | "10111000" =>
-- LDI, LDD, LDIR, LDDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0000";
Set_Addr_To <= aDE;
if IR(3) = '0' then
IncDec_16 <= "0110"; -- IX
else
IncDec_16 <= "1110";
end if;
when 3 =>
I_BT <= '1';
TStates <= "101";
Write <= '1';
if IR(3) = '0' then
IncDec_16 <= "0101"; -- DE
else
IncDec_16 <= "1101";
end if;
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100001" | "10101001" | "10110001" | "10111001" =>
-- CPI, CPD, CPIR, CPDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aXY;
IncDec_16 <= "1100"; -- BC
when 2 =>
Set_BusB_To <= "0110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "0111";
ALU_cpi <= '1';
Save_ALU <= '1';
PreserveC <= '1';
if IR(3) = '0' then
IncDec_16 <= "0110";
else
IncDec_16 <= "1110";
end if;
when 3 =>
NoRead <= '1';
I_BC <= '1';
TStates <= "101";
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
-- NEG
Alu_OP <= "0010";
Set_BusB_To <= "0111";
Set_BusA_To <= "1010";
Read_To_Acc <= '1';
Save_ALU <= '1';
when "01000110"|"01001110"|"01100110"|"01101110" =>
-- IM 0
IMode <= "00";
when "01010110"|"01110110" =>
-- IM 1
IMode <= "01";
when "01011110"|"01110111" =>
-- IM 2
IMode <= "10";
-- 16 bit arithmetic
when "01001010"|"01011010"|"01101010"|"01111010" =>
-- ADC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0001";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0001";
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '0';
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01000010"|"01010010"|"01100010"|"01110010" =>
-- SBC HL,ss
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "101";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
Set_BusB_To(0) <= '1';
when others =>
Set_BusB_To <= "1000";
end case;
TStates <= "100";
when 3 =>
NoRead <= '1';
ALU_Op <= "0011";
Read_To_Reg <= '1';
Save_ALU <= '1';
Set_BusA_To(2 downto 0) <= "100";
case to_integer(unsigned(IR(5 downto 4))) is
when 0|1|2 =>
Set_BusB_To(2 downto 1) <= IR(5 downto 4);
when others =>
Set_BusB_To <= "1001";
end case;
when others =>
end case;
when "01101111" =>
-- RLD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
NoRead <= '1';
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1101";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RLD <= '1';
Write <= '1';
when others =>
end case;
when "01100111" =>
-- RRD
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 2 =>
Set_Addr_To <= aXY;
when 3 =>
Read_To_Reg <= '1';
Set_BusB_To(2 downto 0) <= "110";
Set_BusA_To(2 downto 0) <= "111";
ALU_Op <= "1110";
TStates <= "100";
Set_Addr_To <= aXY;
Save_ALU <= '1';
when 4 =>
I_RRD <= '1';
Write <= '1';
when others =>
end case;
when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
-- RETI, RETN
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_TO <= aSP;
when 2 =>
IncDec_16 <= "0111";
Set_Addr_To <= aSP;
LDZ <= '1';
when 3 =>
Jump <= '1';
IncDec_16 <= "0111";
I_RETN <= '1';
when others => null;
end case;
when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
-- IN r,(C)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
when 2 =>
IORQ <= '1';
if IR(5 downto 3) /= "110" then
Read_To_Reg <= '1';
Set_BusA_To(2 downto 0) <= IR(5 downto 3);
end if;
I_INRC <= '1';
when others =>
end case;
when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
-- OUT (C),r
-- OUT (C),0
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To(2 downto 0) <= IR(5 downto 3);
if IR(5 downto 3) = "110" then
Set_BusB_To(3) <= '1';
end if;
when 2 =>
Write <= '1';
IORQ <= '1';
when others =>
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
Set_Addr_To <= aBC;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
IORQ <= '1';
Set_BusB_To <= "0110";
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110"; -- 0242a
else
IncDec_16 <= "1110"; -- 0242a
end if;
TStates <= "100";
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
TStates <= "101";
Set_Addr_To <= aXY;
Set_BusB_To <= "1010";
Set_BusA_To <= "0000";
Read_To_Reg <= '1';
Save_ALU <= '1';
ALU_Op <= "0010";
when 2 =>
Set_BusB_To <= "0110";
Set_Addr_To <= aBC;
when 3 =>
if IR(3) = '0' then
IncDec_16 <= "0110"; -- 0242a
else
IncDec_16 <= "1110"; -- 0242a
end if;
IORQ <= '1';
Write <= '1';
I_BTR <= '1';
when 4 =>
NoRead <= '1';
TStates <= "101";
when others => null;
end case;
end case;
end case;
if Mode = 1 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "011";
end if;
end if;
if Mode = 3 then
if MCycle = "001" then
-- TStates <= "100";
else
TStates <= "100";
end if;
end if;
if Mode < 2 then
if MCycle = "110" then
Inc_PC <= '1';
if Mode = 1 then
Set_Addr_To <= aXY;
TStates <= "100";
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
end if;
if IRB = "00110110" or IRB = "11001011" then
Set_Addr_To <= aNone;
end if;
end if;
if MCycle = "111" then
if Mode = 0 then
TStates <= "101";
end if;
if ISet /= "01" then
Set_Addr_To <= aXY;
end if;
Set_BusB_To(2 downto 0) <= SSS;
Set_BusB_To(3) <= '0';
if IRB = "00110110" or ISet = "01" then
-- LD (HL),n
Inc_PC <= '1';
else
NoRead <= '1';
end if;
end if;
end if;
end process;
end;
|
gpl-3.0
|
fe32c558be734c2f8eb6c6bb78664685
| 0.267338 | 6.448482 | false | false | false | false |
z3774/sparcv8-monocycle
|
ALU.vhd
| 1 | 2,103 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port (
ope1 : in STD_LOGIC_VECTOR (31 downto 0);
ope2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
carry : in STD_LOGIC;
alurs : out STD_LOGIC_VECTOR (31 downto 0)
);
end ALU;
architecture Behavioral of ALU is
begin
process(ope1,ope2,aluop, carry)
begin
case aluop is
-- ADD
when "100000" => alurs <= ope1 + ope2;
-- ADDcc
when "100001" => alurs <= ope1 + ope2;
-- ADDX
when "100010" => alurs <= ope1 + ope2 + carry;
--ADDXcc
when "100011" => alurs <= ope1 + ope2 + carry;
-- SUB
when "100100" => alurs <= ope1 - ope2;
-- SUBcc
when "100101" => alurs <= ope1 - ope2;
-- SUBX
when "100110" => alurs <= ope1 - ope2 - carry;
--SUBXcc
when "100111" => alurs <= ope1 - ope2 - carry;
-- AND
when "101000" => alurs <= ope1 and ope2;
-- ANDcc
when "101001" => alurs <= ope1 and ope2;
-- ANDN
when "101010" => alurs <= ope1 nand ope2;
-- ANDNcc
when "101011" => alurs <= ope1 nand ope2;
-- OR
when "101100" => alurs <= ope1 or ope2;
-- ORcc
when "101101" => alurs <= ope1 or ope2;
-- ORN
when "101110" => alurs <= ope1 nor ope2;
-- ORNcc
when "101111" => alurs <= ope1 nor ope2;
-- XOR
when "110000" => alurs <= ope1 xor ope2;
-- XORcc
when "110001" => alurs <= ope1 xor ope2;
-- XNOR
when "110010" => alurs <= ope1 xnor ope2;
-- XNORcc
when "110011" => alurs <= ope1 xnor ope2;
--SAVE 57
when "111001" => alurs <= ope1 + ope2;
--RESTORE 58
when "111010" => alurs <= ope1 + ope2;
when others => alurs <= (others=>'0');
end case;
end process;
end Behavioral;
|
gpl-3.0
|
3cb4c7fa50cd6ee745a48caf3537e300
| 0.587256 | 3.092647 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/fabric/xwb_fabric_sink.vhd
| 2 | 7,688 |
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity xwb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end xwb_fabric_sink;
architecture rtl of xwb_fabric_sink is
constant c_fifo_width : integer := 16 + 2 + 4;
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(1 downto 0);
signal post_data : std_logic_vector(15 downto 0);
signal snk_out : t_wrf_sink_out;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_i.cyc;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_i.cyc and not cyc_d0; -- sof
pre_eof <= not snk_i.cyc and cyc_d0; -- eof
pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(15 downto 0) <= snk_i.dat;
fin(17 downto 16) <= snk_i.adr;
fin(21 downto 18) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
end if;
end if;
end process;
snk_o <= snk_out;
we <= '1' when fin(21 downto 18) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => 16)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
post_data <= fout_reg(15 downto 0);
post_addr <= fout_reg(17 downto 16);
post_sof <= fout_reg(21) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(18);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = c_WRF_STATUS) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
eof_o <= fout_reg(20) and rd_d0;
bytesel_o <= fout_reg(19);
data_o <= post_data;
addr_o <= post_addr;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wr_fabric_pkg.all;
entity wb_fabric_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_dat_i : in std_logic_vector(15 downto 0);
snk_adr_i : in std_logic_vector(1 downto 0);
snk_sel_i : in std_logic_vector(1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_fabric_sink;
architecture wrapper of wb_fabric_sink is
component xwb_fabric_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
addr_o : out std_logic_vector(1 downto 0);
data_o : out std_logic_vector(15 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
signal snk_in : t_wrf_sink_in;
signal snk_out : t_wrf_sink_out;
begin -- wrapper
U_Wrapped_Sink : xwb_fabric_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
addr_o => addr_o,
data_o => data_o,
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
bytesel_o => bytesel_o,
dreq_i => dreq_i);
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.cyc <= snk_cyc_i;
snk_in.sel <= snk_sel_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
|
lgpl-3.0
|
550baf784dc0329da8f8e1e7da49cd22
| 0.522112 | 3.153404 | false | false | false | false |
hoglet67/AtomBusMon
|
src/AVR8/Memory/XPM_T65.vhd
| 1 | 140,315 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- This contains 0.987 of the ICE-65C02 firmware
-- For f_log2 definition
use WORK.SynthCtrlPack.all;
entity XPM is
generic (
WIDTH : integer;
SIZE : integer
);
port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(f_log2(SIZE) - 1 downto 0);
din : in std_logic_vector(WIDTH - 1 downto 0);
dout : out std_logic_vector(WIDTH - 1 downto 0);
we : in std_logic
);
end;
architecture RTL of XPM is
type ram_type is array (0 to SIZE - 1) of std_logic_vector (WIDTH - 1 downto 0);
signal RAM : ram_type := (
x"940C",
x"05C8",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"940C",
x"05EA",
x"1A2A",
x"1AF6",
x"1A30",
x"1A3E",
x"1A44",
x"1A52",
x"1A63",
x"1A73",
x"1A7C",
x"1A6A",
x"1AF6",
x"1A93",
x"1A9D",
x"1AAF",
x"1AC5",
x"1ADA",
x"205D",
x"2000",
x"2A2A",
x"0A2A",
x"6D00",
x"6D65",
x"726F",
x"2079",
x"6974",
x"656D",
x"756F",
x"0074",
x"696D",
x"7373",
x"6E69",
x"2067",
x"6C63",
x"636F",
x"006B",
x"2A2A",
x"202A",
x"4900",
x"746E",
x"7265",
x"7572",
x"7470",
x"6465",
x"000A",
x"5043",
x"2055",
x"7266",
x"6565",
x"7220",
x"6E75",
x"696E",
x"676E",
x"2E2E",
x"0A2E",
x"2000",
x"203D",
x"2000",
x"2020",
x"0020",
x"7254",
x"6769",
x"6567",
x"2072",
x"6F43",
x"6564",
x"3A73",
x"000A",
x"6120",
x"2074",
x"5200",
x"6D65",
x"766F",
x"6E69",
x"2067",
x"4E00",
x"206F",
x"7262",
x"6165",
x"706B",
x"696F",
x"746E",
x"2073",
x"6573",
x"0A74",
x"2900",
x"000A",
x"203A",
x"2000",
x"616D",
x"6B73",
x"0020",
x"203A",
x"2000",
x"696D",
x"7263",
x"736F",
x"6365",
x"6E6F",
x"7364",
x"2820",
x"6568",
x"2978",
x"000A",
x"6974",
x"656D",
x"756F",
x"3D74",
x"0A00",
x"3B00",
x"7220",
x"7365",
x"7465",
x"6120",
x"6464",
x"6572",
x"7373",
x"003D",
x"203B",
x"7270",
x"7365",
x"6163",
x"656C",
x"003D",
x"6F6D",
x"6564",
x"203A",
x"4900",
x"6C6C",
x"6765",
x"6C61",
x"6F20",
x"7470",
x"6F69",
x"0A6E",
x"2000",
x"203D",
x"7300",
x"696B",
x"7070",
x"6E69",
x"2067",
x"0053",
x"2D20",
x"3020",
x"0078",
x"6220",
x"7479",
x"7365",
x"7420",
x"206F",
x"7830",
x"7400",
x"6172",
x"736E",
x"6566",
x"7272",
x"6465",
x"3020",
x"0078",
x"6220",
x"6461",
x"7220",
x"6365",
x"726F",
x"7364",
x"000A",
x"6720",
x"6F6F",
x"2064",
x"6572",
x"6F63",
x"6472",
x"2C73",
x"0020",
x"6572",
x"6563",
x"7669",
x"6465",
x"0020",
x"7420",
x"206F",
x"5700",
x"6F72",
x"6574",
x"0020",
x"7250",
x"7365",
x"2073",
x"6E61",
x"2079",
x"656B",
x"2079",
x"6F74",
x"7320",
x"6174",
x"7472",
x"7420",
x"6172",
x"736E",
x"696D",
x"7373",
x"6F69",
x"206E",
x"6128",
x"646E",
x"6120",
x"6167",
x"6E69",
x"6120",
x"2074",
x"6E65",
x"2964",
x"000A",
x"2F20",
x"003D",
x"6F43",
x"706D",
x"7261",
x"2065",
x"6166",
x"6C69",
x"6465",
x"003A",
x"7263",
x"3A63",
x"0020",
x"3D20",
x"0020",
x"7420",
x"206F",
x"5700",
x"3A72",
x"0020",
x"6C46",
x"7375",
x"6968",
x"676E",
x"4520",
x"6576",
x"746E",
x"4620",
x"4649",
x"0A4F",
x"2000",
x"6E69",
x"7473",
x"7572",
x"7463",
x"6F69",
x"736E",
x"000A",
x"6E49",
x"6574",
x"7272",
x"7075",
x"6574",
x"2064",
x"6661",
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x"7473",
x"7572",
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x"6F69",
x"736E",
x"000A",
x"7453",
x"7065",
x"6970",
x"676E",
x"0020",
x"754E",
x"626D",
x"7265",
x"6F20",
x"2066",
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x"7473",
x"6375",
x"6974",
x"6E6F",
x"2073",
x"756D",
x"7473",
x"6220",
x"2065",
x"6F70",
x"6973",
x"6974",
x"6576",
x"000A",
x"6F43",
x"6D6D",
x"6E61",
x"7364",
x"0A3A",
x"2000",
x"2020",
x"5200",
x"7365",
x"7465",
x"6974",
x"676E",
x"4320",
x"5550",
x"000A",
x"203A",
x"6170",
x"7373",
x"6465",
x"000A",
x"6520",
x"7272",
x"726F",
x"0A73",
x"3A00",
x"6620",
x"6961",
x"656C",
x"3A64",
x"0020",
x"654D",
x"6F6D",
x"7972",
x"7420",
x"7365",
x"3A74",
x"0020",
x"0A29",
x"2C00",
x"5220",
x"6165",
x"2064",
x"6162",
x"6B63",
x"0020",
x"2820",
x"7257",
x"746F",
x"3A65",
x"0020",
x"6146",
x"6C69",
x"6120",
x"2074",
x"2000",
x"6C61",
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x"2079",
x"6573",
x"2074",
x"7461",
x"0020",
x"6220",
x"6572",
x"6B61",
x"6F70",
x"6E69",
x"7374",
x"6120",
x"6572",
x"6120",
x"726C",
x"6165",
x"7964",
x"7320",
x"7465",
x"000A",
x"6C41",
x"206C",
x"2000",
x"6573",
x"2074",
x"7461",
x"0020",
x"7254",
x"6361",
x"6E69",
x"2067",
x"6964",
x"6173",
x"6C62",
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x"000A",
x"6920",
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x"6375",
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x"6E6F",
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x"2020",
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x"3032",
x"3232",
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x"0020",
x"3031",
x"323A",
x"3A32",
x"3333",
x"0A00",
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x"6C69",
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x"2074",
x"3000",
x"392E",
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x"2020",
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x"454C",
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x"0020",
x"202C",
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x"0020",
x"6E49",
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x"2904",
x"0404",
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x"0504",
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x"2205",
x"2111",
x"2B0E",
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x"2D12",
x"2E12",
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x"8800",
x"7A08",
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x"4308",
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x"0808",
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x"E807",
x"DA07",
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x"0000",
x"0000",
x"0000",
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x"0000"
);
begin
process (cp2)
begin
if rising_edge(cp2) then
if ce = '1' then
if (we = '1') then
RAM(conv_integer(address)) <= din;
end if;
dout <= RAM(conv_integer(address));
end if;
end if;
end process;
end RTL;
|
gpl-3.0
|
bc6e02f4505baa2c7f9d2dff0604f60b
| 0.295891 | 2.754515 | false | false | false | false |
freecores/camellia-vhdl
|
pipelining/fl128.vhd
| 1 | 5,117 |
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/09/2008
-- Project Name: camellia-vhdl
-- Description: FL and FL^-1 functions, only for 128-bit key en/decryption
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity FL128 is
generic (
fl_ke_offset : INTEGER; -- encryption
fl_ke_shift : INTEGER;
fli_ke_offset : INTEGER;
fli_ke_shift : INTEGER;
fl_kd_offset : INTEGER; -- decryption
fl_kd_shift : INTEGER;
fli_kd_offset : INTEGER;
fli_kd_shift : INTEGER
);
port(
reset : in STD_LOGIC;
clk : in STD_LOGIC;
fl_in : in STD_LOGIC_VECTOR (0 to 63);
fli_in : in STD_LOGIC_VECTOR (0 to 63);
k : in STD_LOGIC_VECTOR (0 to 255);
dec : in STD_LOGIC;
fl_out : out STD_LOGIC_VECTOR (0 to 63);
fli_out : out STD_LOGIC_VECTOR (0 to 63)
);
end FL128;
architecture RTL of FL128 is
signal fl_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_in_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_in_r : STD_LOGIC_VECTOR (0 to 31);
signal tmp_fl_ke : STD_LOGIC_VECTOR (0 to 127); -- encryption
signal tmp_fli_ke : STD_LOGIC_VECTOR (0 to 127);
signal tmp_fl_kd : STD_LOGIC_VECTOR (0 to 127); -- decryption
signal tmp_fli_kd : STD_LOGIC_VECTOR (0 to 127);
signal fl_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fl_k_r : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_l : STD_LOGIC_VECTOR (0 to 31);
signal fli_k_r : STD_LOGIC_VECTOR (0 to 31);
signal fl_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fl_b2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_a2 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b1 : STD_LOGIC_VECTOR (0 to 31);
signal fli_b2 : STD_LOGIC_VECTOR (0 to 31);
-- registers
signal reg_fl_in : STD_LOGIC_VECTOR (0 to 63);
signal reg_fli_in : STD_LOGIC_VECTOR (0 to 63);
begin
REG : process(reset, clk)
begin
if (reset = '1') then
reg_fl_in <= (others=>'0');
reg_fli_in <= (others=>'0');
else
if (rising_edge(clk)) then -- rising clock edge
reg_fl_in <= fl_in;
reg_fli_in <= fli_in;
end if;
end if;
end process;
--FL function
fl_in_l <= reg_fl_in(0 to 31);
fl_in_r <= reg_fl_in(32 to 63);
tmp_fl_ke <= k(fl_ke_offset+fl_ke_shift to fl_ke_offset+127) &
k(fl_ke_offset to fl_ke_offset+fl_ke_shift-1);
tmp_fl_kd <= k(fl_kd_offset+fl_kd_shift to fl_kd_offset+127) &
k(fl_kd_offset to fl_kd_offset+fl_kd_shift-1);
fl_k_l <= tmp_fl_ke(0 to 31) when dec='0' else tmp_fl_kd(64 to 95);
fl_k_r <= tmp_fl_ke(32 to 63) when dec='0' else tmp_fl_kd(96 to 127);
fl_a1 <= fl_in_l and fl_k_l;
fl_a2 <= (fl_a1(1 to 31) & fl_a1(0)) xor fl_in_r;
fl_b1 <= fl_a2 or fl_k_r;
fl_b2 <= fl_in_l xor fl_b1;
fl_out <= fl_b2 & fl_a2;
--FL^-1 function
fli_in_l <= reg_fli_in(0 to 31);
fli_in_r <= reg_fli_in(32 to 63);
tmp_fli_ke <= k(fli_ke_offset+fli_ke_shift to fli_ke_offset+127) &
k(fli_ke_offset to fli_ke_offset+fli_ke_shift-1);
tmp_fli_kd <= k(fli_kd_offset+fli_kd_shift to fli_kd_offset+127) &
k(fli_kd_offset to fli_kd_offset+fli_kd_shift-1);
fli_k_l <= tmp_fli_ke(64 to 95) when dec='0' else tmp_fli_kd(0 to 31);
fli_k_r <= tmp_fli_ke(96 to 127) when dec='0' else tmp_fli_kd(32 to 63);
fli_a1 <= fli_in_r or fli_k_r;
fli_a2 <= fli_in_l xor fli_a1;
fli_b1 <= fli_a2 and fli_k_l;
fli_b2 <= (fli_b1(1 to 31) & fli_b1(0)) xor fli_in_r;
fli_out <= fli_a2 & fli_b2;
end RTL;
|
gpl-3.0
|
dd37ae95492c6185ef4851da7256f8fb
| 0.559312 | 3.086248 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/controller/rank_mach.vhd
| 1 | 16,673 |
--*****************************************************************************
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : rank_mach.vhd
-- /___/ /\ Date Last Modified : $date$
-- \ \ / \ Date Created :
-- \___\/\___\
--
--Device : Virtex-6
--Design Name : DDR3 SDRAM
--Purpose :
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Top level rank machine structural block. This block
-- instantiates a configurable number of rank controller blocks.
entity rank_mach is
generic (
BURST_MODE : string := "8";
CS_WIDTH : integer := 4;
DRAM_TYPE : string := "DDR3";
MAINT_PRESCALER_DIV : integer := 40;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
CL : integer := 5;
nFAW : integer := 30;
nREFRESH_BANK : integer := 8;
nRRD : integer := 4;
nWTR : integer := 4;
PERIODIC_RD_TIMER_DIV : integer := 20;
RANK_BM_BV_WIDTH : integer := 16;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
PHASE_DETECT : string := "OFF"; --Added to control periodic reads
REFRESH_TIMER_DIV : integer := 39;
ZQ_TIMER_DIV : integer := 640000
);
port (
-- Outputs
-- Inputs
-- Beginning of automatic inputs (from unused autoinst inputs)
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_common0 of rank_common.v
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_common0 of rank_common.v
-- To rank_common0 of rank_common.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v, ...
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_cntrl0 of rank_cntrl.v
-- To rank_common0 of rank_common.v
-- To rank_common0 of rank_common.v
-- To rank_cntrl0 of rank_cntrl.v
-- End of automatics
-- Beginning of automatic outputs (from unused autoinst outputs)
-- From rank_common0 of rank_common.v
-- From rank_common0 of rank_common.v
periodic_rd_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0); -- From rank_common0 of rank_common.v
periodic_rd_r : out std_logic;
maint_req_r : out std_logic;
-- End of automatics
-- Beginning of automatic wires (for undeclared instantiated-module outputs)
-- From rank_common0 of rank_common.v
-- From rank_common0 of rank_common.v
-- End of automatics
inhbt_act_faw_r : out std_logic_vector(RANKS - 1 downto 0);
inhbt_rd_r : out std_logic_vector(RANKS - 1 downto 0);
wtr_inhbt_config_r : out std_logic_vector(RANKS - 1 downto 0);
maint_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
maint_zq_r : out std_logic;
wr_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
slot_0_present : in std_logic_vector(7 downto 0);
sending_row : in std_logic_vector(nBANK_MACHS - 1 downto 0);
sending_col : in std_logic_vector(nBANK_MACHS - 1 downto 0);
rst : in std_logic;
rd_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
rank_busy_r : in std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
periodic_rd_ack_r : in std_logic;
maint_wip_r : in std_logic;
insert_maint_r1 : in std_logic;
dfi_init_complete : in std_logic;
clk : in std_logic;
app_zq_req : in std_logic;
app_ref_req : in std_logic;
app_periodic_rd_req : in std_logic;
act_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0)
);
end entity rank_mach;
architecture trans of rank_mach is
component rank_cntrl is
generic (
TCQ : integer := 100;
BURST_MODE : string := "8";
ID : integer := 0;
nBANK_MACHS : integer := 4;
nCK_PER_CLK : integer := 2;
CL : integer := 5;
nFAW : integer := 30;
nREFRESH_BANK : integer := 8;
nRRD : integer := 4;
nWTR : integer := 4;
PERIODIC_RD_TIMER_DIV : integer := 20;
RANK_BM_BV_WIDTH : integer := 16;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
PHASE_DETECT : string := "OFF";
REFRESH_TIMER_DIV : integer := 39
);
port (
inhbt_act_faw_r : out std_logic;
inhbt_rd_r : out std_logic;
wtr_inhbt_config_r : out std_logic;
refresh_request : out std_logic;
periodic_rd_request : out std_logic;
clk : in std_logic;
rst : in std_logic;
sending_row : in std_logic_vector(nBANK_MACHS - 1 downto 0);
act_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
sending_col : in std_logic_vector(nBANK_MACHS - 1 downto 0);
wr_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0);
app_ref_req : in std_logic;
dfi_init_complete : in std_logic;
rank_busy_r : in std_logic_vector((RANKS * nBANK_MACHS) - 1 downto 0);
refresh_tick : in std_logic;
insert_maint_r1 : in std_logic;
maint_zq_r : in std_logic;
maint_rank_r : in std_logic_vector(RANK_WIDTH - 1 downto 0);
app_periodic_rd_req : in std_logic;
maint_prescaler_tick_r : in std_logic;
clear_periodic_rd_request : in std_logic;
rd_this_rank_r : in std_logic_vector(RANK_BM_BV_WIDTH - 1 downto 0)
);
end component;
component rank_common is
generic (
TCQ : integer := 100;
DRAM_TYPE : string := "DDR3";
MAINT_PRESCALER_DIV : integer := 40;
nBANK_MACHS : integer := 4;
RANK_WIDTH : integer := 2;
RANKS : integer := 4;
REFRESH_TIMER_DIV : integer := 39;
ZQ_TIMER_DIV : integer := 640000
);
port (
maint_prescaler_tick_r : out std_logic;
refresh_tick : out std_logic;
maint_zq_r : out std_logic;
maint_req_r : out std_logic;
maint_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
clear_periodic_rd_request : out std_logic_vector(RANKS - 1 downto 0);
periodic_rd_r : out std_logic;
periodic_rd_rank_r : out std_logic_vector(RANK_WIDTH - 1 downto 0);
clk : in std_logic;
rst : in std_logic;
dfi_init_complete : in std_logic;
app_zq_req : in std_logic;
insert_maint_r1 : in std_logic;
refresh_request : in std_logic_vector(RANKS - 1 downto 0);
maint_wip_r : in std_logic;
slot_0_present : in std_logic_vector(7 downto 0);
slot_1_present : in std_logic_vector(7 downto 0);
periodic_rd_request : in std_logic_vector(RANKS - 1 downto 0);
periodic_rd_ack_r : in std_logic
);
end component;
signal maint_prescaler_tick_r : std_logic;
signal refresh_tick : std_logic;
signal refresh_request : std_logic_vector(RANKS - 1 downto 0);
signal periodic_rd_request : std_logic_vector(RANKS - 1 downto 0);
signal clear_periodic_rd_request : std_logic_vector(RANKS - 1 downto 0);
-- Declare intermediate signals for referenced outputs
signal periodic_rd_rank_r_int6 : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal periodic_rd_r_int5 : std_logic;
signal maint_req_r_int3 : std_logic;
signal inhbt_act_faw_r_int0 : std_logic_vector(RANKS - 1 downto 0);
signal inhbt_rd_r_int1 : std_logic_vector(RANKS - 1 downto 0);
signal wtr_inhbt_config_r_int7 : std_logic_vector(RANKS - 1 downto 0);
signal maint_rank_r_int2 : std_logic_vector(RANK_WIDTH - 1 downto 0);
signal maint_zq_r_int4 : std_logic;
begin
-- Drive referenced outputs
periodic_rd_rank_r <= periodic_rd_rank_r_int6;
periodic_rd_r <= periodic_rd_r_int5;
maint_req_r <= maint_req_r_int3;
inhbt_act_faw_r <= inhbt_act_faw_r_int0;
inhbt_rd_r <= inhbt_rd_r_int1;
wtr_inhbt_config_r <= wtr_inhbt_config_r_int7;
maint_rank_r <= maint_rank_r_int2;
maint_zq_r <= maint_zq_r_int4;
rank_cntrl_inst : for ID in 0 to RANKS - 1 generate
-- Parameters
rank_cntrl0 : rank_cntrl
generic map (
BURST_MODE => BURST_MODE,
ID => ID,
nBANK_MACHS => nBANK_MACHS,
nCK_PER_CLK => nCK_PER_CLK,
CL => CL,
nFAW => nFAW,
nREFRESH_BANK => nREFRESH_BANK,
nRRD => nRRD,
nWTR => nWTR,
PERIODIC_RD_TIMER_DIV => PERIODIC_RD_TIMER_DIV,
RANK_BM_BV_WIDTH => RANK_BM_BV_WIDTH,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
PHASE_DETECT => PHASE_DETECT,
REFRESH_TIMER_DIV => REFRESH_TIMER_DIV
)
port map (
clear_periodic_rd_request => clear_periodic_rd_request(ID),
inhbt_act_faw_r => inhbt_act_faw_r_int0(ID),
inhbt_rd_r => inhbt_rd_r_int1(ID),
periodic_rd_request => periodic_rd_request(ID),
refresh_request => refresh_request(ID),
wtr_inhbt_config_r => wtr_inhbt_config_r_int7(ID),
-- Inputs
clk => clk,
rst => rst,
sending_row => sending_row(nBANK_MACHS - 1 downto 0),
act_this_rank_r => act_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
sending_col => sending_col(nBANK_MACHS - 1 downto 0),
wr_this_rank_r => wr_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0),
app_ref_req => app_ref_req,
dfi_init_complete => dfi_init_complete,
rank_busy_r => rank_busy_r((RANKS * nBANK_MACHS) - 1 downto 0),
refresh_tick => refresh_tick,
insert_maint_r1 => insert_maint_r1,
maint_zq_r => maint_zq_r_int4,
maint_rank_r => maint_rank_r_int2(RANK_WIDTH - 1 downto 0),
app_periodic_rd_req => app_periodic_rd_req,
maint_prescaler_tick_r => maint_prescaler_tick_r,
rd_this_rank_r => rd_this_rank_r(RANK_BM_BV_WIDTH - 1 downto 0)
);
end generate;
-- Parameters
rank_common0 : rank_common
generic map (
DRAM_TYPE => DRAM_TYPE,
MAINT_PRESCALER_DIV => MAINT_PRESCALER_DIV,
nBANK_MACHS => nBANK_MACHS,
RANK_WIDTH => RANK_WIDTH,
RANKS => RANKS,
REFRESH_TIMER_DIV => REFRESH_TIMER_DIV,
ZQ_TIMER_DIV => ZQ_TIMER_DIV
)
port map (
clear_periodic_rd_request => clear_periodic_rd_request(RANKS - 1 downto 0),
-- Outputs
maint_prescaler_tick_r => maint_prescaler_tick_r,
refresh_tick => refresh_tick,
maint_zq_r => maint_zq_r_int4,
maint_req_r => maint_req_r_int3,
maint_rank_r => maint_rank_r_int2(RANK_WIDTH - 1 downto 0),
periodic_rd_r => periodic_rd_r_int5,
periodic_rd_rank_r => periodic_rd_rank_r_int6(RANK_WIDTH - 1 downto 0),
-- Inputs
clk => clk,
rst => rst,
dfi_init_complete => dfi_init_complete,
app_zq_req => app_zq_req,
insert_maint_r1 => insert_maint_r1,
refresh_request => refresh_request(RANKS - 1 downto 0),
maint_wip_r => maint_wip_r,
slot_0_present => slot_0_present(7 downto 0),
slot_1_present => slot_1_present(7 downto 0),
periodic_rd_request => periodic_rd_request(RANKS - 1 downto 0),
periodic_rd_ack_r => periodic_rd_ack_r
);
end architecture trans;
|
lgpl-3.0
|
5351edf5bd2420776e0d6b1fad27d38e
| 0.503089 | 4.036069 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/modules/dbe_wishbone/wb_fmc150/sim/dac3283_init_mem.vhd
| 1 | 5,466 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file dac3283_init_mem.vhd when simulating
-- the core, dac3283_init_mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY dac3283_init_mem IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END dac3283_init_mem;
ARCHITECTURE dac3283_init_mem_a OF dac3283_init_mem IS
-- synthesis translate_off
COMPONENT wrapped_dac3283_init_mem
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_dac3283_init_mem USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "virtex6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/sim/dac3283_init_mem.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32,
c_read_depth_b => 32,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32,
c_write_depth_b => 32,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_dac3283_init_mem
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END dac3283_init_mem_a;
|
lgpl-3.0
|
39329ef92bdf5072bab92cb447a62539
| 0.536407 | 3.926724 | false | false | false | false |
lerwys/bpm-sw-old-backup
|
hdl/ip_cores/pcie/ml605/ddr_v6/user_design/rtl/phy/phy_rdctrl_sync.vhd
| 1 | 8,271 |
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: phy_rdctrl_sync.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:12 $
-- \ \ / \ Date Created: Mon Jun 30 2008
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Synchronization of read control signal from MC/PHY rdlvl logic (clk) to
-- read capture logic (clk_rsync) clock domain. Also adds additional delay
-- to account for read latency
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: phy_rdctrl_sync.vhd,v 1.1 2011/06/02 07:18:12 mishra Exp $
--**$Date: 2011/06/02 07:18:12 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/phy_rdctrl_sync.vhd,v $
--******************************************************************************
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity phy_rdctrl_sync is
generic (
TCQ : integer := 100
);
port (
clk : in std_logic;
rst_rsync : in std_logic; -- Use only CLK_RSYNC[0] reset
-- Control for control sync logic
mc_data_sel : in std_logic;
rd_active_dly : in std_logic_vector(4 downto 0);
-- DFI signals from MC/PHY rdlvl logic
dfi_rddata_en : in std_logic;
phy_rddata_en : in std_logic;
-- Control for read logic, initialization logic
dfi_rddata_valid : out std_logic;
dfi_rddata_valid_phy : out std_logic;
rdpath_rdy : out std_logic -- asserted when read path
-- ready for use
);
end phy_rdctrl_sync;
architecture trans of phy_rdctrl_sync is
-- # of clock cycles after RST_RSYNC has deasserted before init/cal logic
-- is taken out of reset. This is only needed for simulation when the "no
-- init/no cal" option is selected. In this case, PHY_INIT will assert
-- DFI_INIT_COMPLETE signal almost instantaneously once it is taken out
-- of reset - however, there are certain pipe stages that must "flush
-- out" (related to circular buffer synchronization) for a few cycles after
-- RST_RSYNC is deasserted - in particular, the one related to generating
-- DFI_RDDATA_VALID must not drive an unknown value on the bus after
-- DFI_INIT_COMPLETE is asserted.
-- NOTE: # of cycles of delay required depends on the circular buffer
-- depth for RD_ACTIVE - it should >= (0.5*depth + 1)
constant RDPATH_RDY_DLY : integer := 10;
signal rddata_en : std_logic;
signal rddata_en_rsync : std_logic;
signal rddata_en_srl_out : std_logic;
signal rdpath_rdy_dly_r : std_logic_vector(RDPATH_RDY_DLY-1 downto 0);
begin
--***************************************************************************
-- Delay RDDATA_EN by an amount determined during read-leveling
-- calibration to reflect the round trip delay from command issuance until
-- when read data is returned
--***************************************************************************
rddata_en <= dfi_rddata_en when (mc_data_sel = '1') else
phy_rddata_en;
-- May need to flop output of SRL for better timing
u_rddata_en_srl : SRLC32E
port map (
Q => rddata_en_srl_out,
Q31 => open,
A => rd_active_dly,
CE => '1',
CLK => clk,
D => rddata_en
);
-- Flop once more for better timing
process (clk)
begin
if (clk'event and clk = '1') then
-- Only assert valid on DFI bus after initialization complete
dfi_rddata_valid <= rddata_en_srl_out and mc_data_sel after (TCQ)*1 ps;
-- Assert valid for PHY during initialization
dfi_rddata_valid_phy <= rddata_en_srl_out after (TCQ)*1 ps;
end if;
end process;
--***************************************************************************
-- Generate a signal that tells initialization logic that read path is
-- ready for use (i.e. for read leveling). Use RST_RSYNC, and delay it by
-- RDPATH_RDY_DLY clock cycles, then synchronize to CLK domain.
-- NOTE: This logic only required for simulation; for final h/w, there will
-- always be a long delay between RST_RSYNC deassertion and
-- DFI_INIT_COMPLETE assertion (for DRAM init, and leveling)
--***************************************************************************
-- First delay by X number of clock cycles to guarantee that RDPATH_RDY
-- isn't asserted too soon after RST_RSYNC is deasserted (to allow various
-- synchronization pipe stages to "flush"). NOTE: Only RST_RSYNC[0] (or
-- any of the up to 4 RST_RSYNC's) is used - any of them is sufficient
-- close enough in timing to use
process (clk, rst_rsync)
begin
if (rst_rsync = '1') then
rdpath_rdy_dly_r <= (others => '0') after (TCQ)*1 ps;
elsif (clk'event and clk = '1') then
rdpath_rdy_dly_r((RDPATH_RDY_DLY-1) downto 1) <= (rdpath_rdy_dly_r((RDPATH_RDY_DLY-3) downto 0) & '1') after (TCQ)*1 ps;
end if;
end process;
-- Flop once more to prevent ISE tools from analyzing asynchronous path
-- through this flop to receiving logic
process (clk)
begin
if (clk'event and clk = '1') then
rdpath_rdy <= rdpath_rdy_dly_r(RDPATH_RDY_DLY-1);
end if;
end process;
end trans;
|
lgpl-3.0
|
0e3f10ea7a9a3e2b2ccbc74a9b0b890a
| 0.596179 | 4.237193 | false | false | false | false |
fbelavenuto/msx1fpga
|
src/audio/vm2413/outputgenerator.vhd
| 2 | 4,551 |
--
-- OutputGenerator.vhd
--
-- Copyright (c) 2006 Mitsutaka Okazaki ([email protected])
-- All rights reserved.
--
-- Redistribution and use of this source code or any derivative works, are
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial
-- product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity OutputGenerator is
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in std_logic_vector( 4 downto 0 );
stage : in std_logic_vector( 1 downto 0 );
rhythm : in std_logic;
opout : in std_logic_vector( 13 downto 0 );
faddr : in integer range 0 to 9-1;
fdata : out SIGNED_LI_TYPE;
maddr : in std_logic_vector( 4 downto 0 );
mdata : out SIGNED_LI_TYPE
);
end entity;
architecture RTL of OutputGenerator is
function AVERAGE ( L : SIGNED_LI_TYPE ; R : SIGNED_LI_TYPE ) return SIGNED_LI_TYPE is
variable vL, vR : std_logic_vector(LI_TYPE'high + 2 downto 0);
begin
-- {âÎl ¨ QÌâ
if( L.sign = '0' )then
vL := "00" & L.value;
else
vL := not ( "00" & L.value ) + '1';
end if;
if( R.sign = '0' )then
vR := "00" & R.value;
else
vR := not ( "00" & R.value ) + '1';
end if;
vL := vL + vR;
-- QÌâ ¨ {âÎlA¢ÅÉ 1/2 {B±±ÅPrbgÁ¸B
if vL(vL'high) = '0' then -- positive
return ( sign => '0', value => vL(vL'high-1 downto 1) );
else -- negative
vL := not ( vL - '1' );
return ( sign => '1', value => vL(vL'high-1 downto 1) );
end if;
end;
signal fb_wr, mo_wr : std_logic;
signal fb_addr : integer range 0 to 9-1;
signal mo_addr : std_logic_vector( 4 downto 0 );
signal li_data, fb_wdata, mo_wdata, mo_rdata : SIGNED_LI_TYPE;
begin
Fmem : entity work.FeedbackMemory
port map(
clk => clk,
reset => reset,
wr => fb_wr,
waddr => fb_addr,
wdata => fb_wdata,
raddr => faddr,
rdata => fdata
);
Mmem : entity work.OutputMemory
port map(
clk => clk,
reset => reset,
wr => mo_wr,
addr => mo_addr,
wdata => mo_wdata,
rdata => mo_rdata,
addr2 => maddr,
rdata2 => mdata
);
Ltbl : entity work.LinearTable
port map (
clk => clk,
reset => reset,
addr => opout, -- 0`127 (opout Í FF Ìo;©ç_CNgÉüêÄàâèÈ¢j
data => li_data -- 0`511
);
process( reset, clk )
begin
if( reset = '1' )then
mo_wr <= '0';
fb_wr <= '0';
elsif( clk'event and clk = '1' )then
if( clkena = '1' )then
mo_addr <= slot;
if( stage = 0 )then
mo_wr <= '0';
fb_wr <= '0';
elsif( stage = 1 )then
-- opout É]ÌlªüÁÄéXe[W
elsif( stage = 2 )then
-- Ò¿
elsif( stage = 3 )then
-- LinerTable ©ç opout Åwè³ê½AhXÉηélªoÄéXe[W
if( slot(0) = '0' )then
-- tB[hobNÉÍW
[^ÌÆ«µ©«ÜÈ¢
fb_addr <= conv_integer(slot)/2;
fb_wdata<= AVERAGE(mo_rdata, li_data);
fb_wr <= '1';
end if;
-- Store raw output
mo_wdata<= li_data;
mo_wr <= '1';
end if;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
71ffcf42f47f2bb9f396c2bb45238d8c
| 0.601187 | 2.792025 | false | false | false | false |
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