repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
notti/schaltungstechnik_vertiefung
|
shiftreg/vhdl/tb_shiftreg.vhd
| 1 | 1,380 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_shiftreg is
end tb_shiftreg;
architecture behav of tb_shiftreg is
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal leftShift : std_logic := '0';
signal rightShift : std_logic := '0';
signal leftIn : std_logic := '0';
signal rightIn : std_logic := '0';
signal regOut : std_logic_vector(7 downto 0) := "00000000";
begin
process
begin
clk <= '1', '0' after 5 ns;
wait for 10 ns;
end process;
process
begin
wait for 10 ns;
rst <= '1' after 12 ns;
wait for 20 ns;
rst <= '0';
wait for 10 ns;
leftShift <= '1';
rightIn <= '1';
wait for 30 ns;
leftShift <= '0';
wait for 30 ns;
rightShift <= '1';
wait for 50 ns;
leftShift <= '1';
wait for 50 ns;
assert false report "done" severity failure;
wait;
end process;
shiftreg_i: entity work.shiftreg
port map(
rst => rst,
clk => clk,
leftShift => leftShift,
rightShift => rightShift,
leftIn => leftIn,
rightIn => rightIn,
regOut => regOut
);
end behav;
|
mit
|
b73e059759c2dd261733ab9768de53d9
| 0.519565 | 3.833333 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_SEPERATE_RAMROUTE/ram.vhd
| 5 | 1,814 |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: RAM
-- Module Name: RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple RAM (Random Access Memory)
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 44*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ram is
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end ram;
architecture Behavioral of ram is
type ramtype is array(0 to 43) of std_logic_vector(31 downto 0);
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rw = '1' then
memory_ram(to_integer(unsigned(address))) <= data_in;
data_out <= data_in; -- small modification to make data_out contain what was written upon every write operation
else
data_out <= memory_ram(to_integer(unsigned(address)));
end if;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
6ae101b3eefde5c91cb10d06f8d74933
| 0.48677 | 4.238318 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/tb_master.vhd
| 1 | 3,551 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use work.tb_package.all;
entity tb_master is
Port (
done_i : in std_logic_vector(gen_number downto 0);
command_o : out command_rec
);
end tb_master;
architecture Behavioral of tb_master is
begin
p_main: process
file stimuli_file : text is in gen_filename&"/stimulate.txt";
variable v_line : line;
variable blank : string(1 to 1);
variable char : string(1 to 1);
variable n : integer:=1;
variable v_trans : bit:='0';
variable v_gen_number : integer:=0;
variable v_event : boolean;
variable generator : string (1 to 14);
variable v_command : string (1 to 10);
variable v_value1 : string (1 to 8);
variable v_value2 : string (1 to 8);
variable v_value3 : string (1 to 8);
variable v_value4 : string (1 to 8);
variable v_value5 : string (1 to 8);
variable v_value6 : string (1 to 8);
variable master_command : string (1 to 4);
variable help_done : boolean := false;
variable compare_help : std_logic_vector(gen_number downto 0);
variable done_help : std_logic_vector(gen_number downto 0);
variable v_time : time;
variable time_value : string (1 to 8);
begin
while true loop
while v_event = false and (not endfile(stimuli_file))loop
char := " ";
done_help := (others =>'U');
compare_help :=(others=>'0');
readline(stimuli_file, v_line);
while char /= "(" and char/="$" and char/="-" loop
read(v_line,char);
generator(n to n) := char;
n:=n+1;
end loop;
n:=1;
if generator(1 to 1)="$" then
read(v_line,master_command);
if master_command(1 to 4)="quit" then
assert false
report"Simulation Complete (This is not a failure)"
severity failure;
elsif master_command(1 to 4)="wait" then
read(v_line,blank);
n:=1;
while char /= "s" loop
read(v_line,char);
time_value(n to n) := char;
n:=n+1;
end loop;
v_time:=string_to_time(time_value(1 to n-1));
wait for v_time;
v_event:= false;
n:=1;
end if;
elsif generator(1 to 1)="-" then
v_event:= false;
else
v_event:=true;
read(v_line,v_command);
read(v_line,blank);
read(v_line,v_value1);
read(v_line,blank);
read(v_line,v_value2);
read(v_line,blank);
read(v_line,v_value3);
read(v_line,blank);
read(v_line,v_value4);
read(v_line,blank);
read(v_line,v_value5);
read(v_line,blank);
read(v_line,v_value6);
read(v_line,blank);
end if;
if v_event then
if generator(1 to 5) = "reset" then
v_gen_number:=0;
elsif generator(1 to 5) ="clock" then
v_gen_number:=1;
elsif generator(1 to 6) ="enable" then
v_gen_number:=5;
elsif generator(1 to 6) ="bit_in" then
v_gen_number:=6;
end if;
end if;
if v_event then
v_trans := not v_trans;
command_o.gen_number <= v_gen_number;
command_o.mnemonic <= v_command;
command_o.value1 <= v_value1;
command_o.value2 <= v_value2;
command_o.value3 <= v_value3;
command_o.value4 <= v_value4;
command_o.value5 <= v_value5;
command_o.value6 <= v_value6;
command_o.trans <= v_trans;
end if;
end loop;
if done_i=done_help then
wait for 1 ps;
wait until (done_i'EVENT and done_i(gen_number downto 0)=compare_help) ;
else
wait until (done_i'EVENT and done_i(gen_number downto 0)=compare_help) ;
end if;
v_event:=false;
end loop;
end process p_main;
end Behavioral;
|
mit
|
31ae578af4a5c9151fbcf3f9c5fb763e
| 0.612222 | 2.744204 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
std_fifo/tb/tb_std_fifo.vhd
| 1 | 4,567 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_std_fifo is
end tb_std_fifo;
architecture test of tb_std_fifo is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal sim_finished : boolean := false;
-- std_fifo ---------------------------------------------------------------
constant DATA_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 8;
signal clr : std_logic := '0';
signal write_en : std_logic := '0';
signal data_in : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal read_en : std_logic := '0';
signal data_out : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal empty : std_logic := '0';
signal full : std_logic := '0';
signal usedw : std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH + 1)))) - 1 downto 0) := (others => '0');
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
std_fifo_inst : entity work.std_fifo
generic map(DATA_WIDTH => DATA_WIDTH,
FIFO_DEPTH => FIFO_DEPTH)
port map(
clk => clk,
reset => reset,
clr => clr,
write_en => write_en,
data_in => data_in,
read_en => read_en,
data_out => data_out,
empty => empty,
full => full,
usedw => usedw);
sim : process
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure sync_clr is
begin
wait until falling_edge(clk);
clr <= '1';
wait until falling_edge(clk);
clr <= '0';
end procedure sync_clr;
procedure push(constant val : in natural) is
begin
wait until falling_edge(clk);
write_en <= '1';
data_in <= std_logic_vector(to_unsigned(val, data_in'length));
wait until falling_edge(clk);
write_en <= '0';
data_in <= (others => '0');
end procedure push;
procedure pop is
begin
wait until falling_edge(clk);
read_en <= '1';
wait until falling_edge(clk);
read_en <= '0';
end procedure pop;
procedure push_pop(constant val : in natural) is
begin
wait until falling_edge(clk);
write_en <= '1';
data_in <= std_logic_vector(to_unsigned(val, data_in'length));
read_en <= '1';
wait until falling_edge(clk);
write_en <= '0';
data_in <= (others => '0');
read_en <= '0';
end procedure push_pop;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
begin
-- async reset
async_reset;
wait_clock_cycles(10);
-- push
for i in 1 to FIFO_DEPTH loop
push(i);
end loop;
wait_clock_cycles(10);
-- pop
for i in 1 to FIFO_DEPTH loop
pop;
end loop;
wait_clock_cycles(10);
-- pushpop
push(FIFO_DEPTH + 1);
for i in 2 to FIFO_DEPTH loop
push_pop(FIFO_DEPTH + i);
end loop;
pop;
wait_clock_cycles(10);
-- sync clr
sync_clr;
wait_clock_cycles(10);
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
unlicense
|
d2302aa2ed88f8852435b6d6c6382d77
| 0.450843 | 4.280225 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_INTEGRATED_CACHEROUTE/key_schedule.vhd
| 3 | 1,711 |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (r : in std_logic_vector(7 downto 0);
-- we don't need k_2 here because of the way we schedule k(r) in the simon component
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal seqC : std_logic_vector(31 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
-- 0xFFFFFFFFFFFFFFFC xor sequence[(r-4) % 62]
-- TODO: 1-bit latch for seqC(0) is used, not recommended...
seqC <= ("1111111111111111111111111111110" & sequence((to_integer(unsigned(r))) mod 62));
-- tmp = K[3] >> 3
op_3_s <= std_logic_vector(rotate_right(unsigned(k_3), 3));
-- tmp = tmp xor k[1]
op_xor_0 <= (op_3_s xor k_1);
-- tmp >> 1
op_1_s <= std_logic_vector(rotate_right(unsigned(op_xor_0), 1));
-- Original NSA specification lists ~K[0] ^ 3 but this can be rewritten to K[0] ^ ((1 << word_size)-4) where the latter can be stored as a constant for speed
subkey_out <= op_1_s xor op_xor_0 xor k_0 xor seqC;
end Behavioral;
|
gpl-2.0
|
fa3d6a3f2f6f1e230bb34a388bb51b4c
| 0.656341 | 2.991259 | false | false | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/Comparador21.vhd
| 1 | 5,041 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: Comparador21.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Comparador21 IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
AeB : OUT STD_LOGIC ;
AgB : OUT STD_LOGIC
);
END Comparador21;
ARCHITECTURE SYN OF comparador21 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2_bv : BIT_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC ;
AgB : OUT STD_LOGIC ;
AeB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(4 DOWNTO 0) <= "10101";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
AgB <= sub_wire0;
AeB <= sub_wire1;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_pipeline => 1,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 5
)
PORT MAP (
dataa => dataa,
datab => sub_wire2,
clock => clock,
AgB => sub_wire0,
AeB => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: PRIVATE: Latency NUMERIC "1"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "21"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: AeB 0 0 0 0 OUTPUT NODEFVAL AeB
-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: dataa 0 0 5 0 INPUT NODEFVAL dataa[4..0]
-- Retrieval info: CONNECT: AeB 0 0 0 0 @AeB 0 0 0 0
-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 5 0 dataa 0 0 5 0
-- Retrieval info: CONNECT: @datab 0 0 5 0 21 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21_wave*.jpg TRUE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
85869f822a088a9c62961dd5faac6997
| 0.659195 | 3.637085 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_INTEGRATED_RAMROUTE/simon.vhd
| 1 | 4,523 |
-- SIMON 64/128
-- Simon core component
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component round_f is
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end component;
component key_schedule is
port (r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end component;
component ram is
port (data_in : in std_logic_vector(31 downto 0);
rw : in std_logic;
clk : in std_logic;
address : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal r_s : std_logic_vector(7 downto 0); -- round index
signal key_s : key_t; -- intermediate key (in words)
signal subkey_out_s : std_logic_vector(31 downto 0); -- round key
signal v_in_s : std_logic_vector(63 downto 0); -- intermediate 'plaintext'
signal v_out_s : std_logic_vector(63 downto 0); -- intermediate 'ciphertext'
signal ram_rw : std_logic;
signal ram_data_out : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (r_s, key_s(0), key_s(1), key_s(3), subkey_out_s);
ROUND_F_0 : round_f port map (v_in_s, ram_data_out, v_out_s);
-- round index is used as ram address, round key is ram input
RAM_0 : ram port map (subkey_out_s, ram_rw, clk, r_s, ram_data_out);
pr_r : process(clk, rst)
begin
if rising_edge(clk) then
-- initialization clock
if rst = '1' then
if enc = '0' then
if r_s = X"00" then
r_s <= X"01";
else
r_s <= (others => '0');
end if;
else
r_s <= X"2A";
end if;
-- running clock
else
if enc = '0' then
if r_s /= X"2B" then
r_s <= std_logic_vector(unsigned(r_s) + 1);
end if;
else
if r_s /= X"00" then
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
end if;
end if;
end if;
end process;
-- SIMON Core
-- Take 2 clock cycle for initialization (since we route key through RAM) + 1 clock cycle per round for encryption/decryption
pr_smn : process(clk, rst, enc, r_s, key, key_s, subkey_out_s, block_in, v_in_s, v_out_s, ram_rw, ram_data_out)
begin
if rising_edge(clk) then
-- initalize
if rst = '1' then
if enc = '0' then
v_in_s <= block_in;
-- write every round key to RAM during encryption
-- so that encryption also functions as pre-expansion for decryption
ram_rw <= '1';
else
-- swap blocks for decryption
v_in_s <= block_in(31 downto 0) & block_in(63 downto 32);
ram_rw <= '0';
end if;
if r_s = X"00" then
-- first encryption round is done during rst='1' phase to account for keys being routed through RAM
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out_s;
else
-- initialize intermediate key from master key
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
end if;
-- run
else
v_in_s <= v_out_s;
if enc = '0' then
-- intermediate key rotates for initial 4 key words, beyond that gets gradually filled in by expansion
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out_s;
-- last round of encryption, prepare for potential subsequent decryption (when using encryption as pre-scheduling)
if r_s = X"2B" then
ram_rw <= '0';
end if;
end if;
end if;
end if;
end process;
block_out <= v_out_s when (enc = '0') else v_out_s(31 downto 0) & v_out_s(63 downto 32);
end Behavioral;
|
gpl-2.0
|
48c617213c1d3067793c71594c9713cf
| 0.600044 | 2.866286 | false | false | false | false |
NickShaffner/rhea
|
rhea/cores/usbext/fpgalink/comm_fpga_fx2_v2.vhd
| 3 | 7,093 |
-- File: comm_fpga_fx2_v2.vhd
-- Generated by MyHDL 0.9dev
-- Date: Sat Jul 13 22:29:39 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_09.all;
entity comm_fpga_fx2_v2 is
port (
clk_in: in std_logic;
reset_in: in std_logic;
fx2FifoSel_out: out std_logic;
fx2Data_in: in unsigned(7 downto 0);
fx2Data_out: out unsigned(7 downto 0);
fx2Data_sel: out std_logic;
fx2Read_out: in std_logic;
fx2GotData_in: in std_logic;
fx2Write_out: in std_logic;
fx2GotRoom_in: in std_logic;
fx2PktEnd_out: in std_logic;
chanAddr_out: in unsigned(6 downto 0);
h2fData_out: in unsigned(7 downto 0);
h2fValid_out: in std_logic;
h2fReady_in: in std_logic;
f2hData_in: in unsigned(7 downto 0);
f2hValid_in: in std_logic;
f2hReady_out: in std_logic
);
end entity comm_fpga_fx2_v2;
-- Original port definition
-- This module bridges the "original" port mapping to the MyHDL
-- version.
architecture MyHDL of comm_fpga_fx2_v2 is
constant fopREAD: integer := 2;
constant FX2_IN_FIFO: integer := 1;
constant FX2_OUT_FIFO: integer := 0;
constant fopNOP: integer := 3;
constant fopWRITE: integer := 1;
signal g_fl_bus_chan_addr: unsigned(6 downto 0);
signal g_fx2_bus_read: std_logic;
signal g_is_write: std_logic;
signal g_state: None;
signal g_fl_bus_data_i: unsigned(7 downto 0);
signal g_fx2_bus_gotroom: std_logic;
signal g_fl_bus_data_o: unsigned(7 downto 0);
signal g_fl_bus_ready_i: std_logic;
signal g_fl_bus_ready_o: std_logic;
signal g_is_aligned: std_logic;
signal g_count: unsigned(31 downto 0);
signal g_fifop: unsigned(1 downto 0);
signal g_fl_bus_valid_o: std_logic;
signal g_fx2_bus_write: std_logic;
signal g_fl_bus_valid_i: std_logic;
signal g_fx2_bus_gotdata: std_logic;
signal g_fx2_bus_pktend: std_logic;
begin
g_fl_bus_data_i <= to_unsigned(0, 8);
g_fx2_bus_gotroom <= '0';
g_fl_bus_ready_i <= '0';
g_fl_bus_valid_i <= '0';
g_fx2_bus_gotdata <= '0';
COMM_FPGA_FX2_V2_G_HDL_SM: process (clk_in, reset_in) is
begin
if (reset_in = '0') then
g_count <= to_unsigned(0, 32);
g_fl_bus_chan_addr <= to_unsigned(0, 7);
fx2Data_out <= to_unsigned(0, 8);
fx2FifoSel_out <= '0';
g_fifop <= to_unsigned(3, 2);
g_is_write <= '0';
g_fl_bus_ready_o <= '0';
fx2Data_sel <= '0';
g_fl_bus_valid_o <= '0';
g_state <= IDLE;
g_fx2_bus_pktend <= '0';
g_fl_bus_data_o <= to_unsigned(0, 8);
g_is_aligned <= '0';
elsif rising_edge(clk_in) then
case g_state is
when GET_COUNT0 =>
if bool(g_fx2_bus_gotdata) then
g_count <= shift_left(resize(fx2Data_in, 32), 24);
g_state <= GET_COUNT1;
else
g_count <= to_unsigned(0, 32);
end if;
when GET_COUNT1 =>
if bool(g_fx2_bus_gotdata) then
g_count <= (g_count or shift_left(resize(fx2Data_in, 32), 16));
g_state <= GET_COUNT2;
end if;
when GET_COUNT2 =>
if bool(g_fx2_bus_gotdata) then
g_count <= (g_count or shift_left(resize(fx2Data_in, 32), 8));
g_state <= GET_COUNT3;
end if;
when GET_COUNT3 =>
if bool(g_fx2_bus_gotdata) then
g_count <= (g_count or resize(fx2Data_in, 32));
if bool(g_is_write) then
g_state <= BEGIN_WRITE;
else
if bool(g_fl_bus_ready_i) then
g_fifop <= to_unsigned(fopREAD, 2);
g_state <= READ;
else
g_fifop <= to_unsigned(fopNOP, 2);
g_state <= READ_WAIT;
end if;
end if;
end if;
when BEGIN_WRITE =>
fx2FifoSel_out <= stdl(FX2_IN_FIFO);
g_fifop <= to_unsigned(fopNOP, 2);
if (g_count(9-1 downto 0) = 0) then
g_is_aligned <= '1';
else
g_is_aligned <= '0';
end if;
g_state <= WRITE;
when WRITE =>
if bool(g_fx2_bus_gotroom) then
g_fl_bus_ready_o <= '1';
end if;
if (bool(g_fx2_bus_gotroom) and bool(g_fl_bus_valid_i)) then
g_fifop <= to_unsigned(fopWRITE, 2);
fx2Data_out <= g_fl_bus_data_i;
fx2Data_sel <= '1';
g_count <= (g_count - 1);
if (g_count = 1) then
if bool(g_is_aligned) then
g_state <= END_WRITE_ALIGNED;
else
g_state <= END_WRITE_NONALIGNED;
end if;
end if;
else
g_fifop <= to_unsigned(fopNOP, 2);
end if;
when END_WRITE_ALIGNED =>
fx2FifoSel_out <= stdl(FX2_IN_FIFO);
g_fifop <= to_unsigned(fopNOP, 2);
g_state <= IDLE;
when END_WRITE_NONALIGNED =>
fx2FifoSel_out <= stdl(FX2_IN_FIFO);
g_fifop <= to_unsigned(fopNOP, 2);
g_fx2_bus_pktend <= '0';
g_state <= IDLE;
when READ =>
fx2FifoSel_out <= stdl(FX2_OUT_FIFO);
if (bool(g_fx2_bus_gotdata) and bool(g_fl_bus_ready_i)) then
assert (not bool(g_fx2_bus_read))
report "*** AssertionError ***"
severity error;
g_fl_bus_valid_o <= '1';
g_fl_bus_data_o <= fx2Data_in;
if (g_count <= 1) then
g_state <= IDLE;
g_count <= to_unsigned(0, 32);
else
g_count <= (g_count - 1);
end if;
end if;
when READ_WAIT =>
if (bool(g_fx2_bus_gotdata) and bool(g_fl_bus_ready_i)) then
g_state <= READ;
g_fifop <= to_unsigned(fopREAD, 2);
end if;
when others =>
g_fifop <= to_unsigned(fopREAD, 2);
g_count <= to_unsigned(0, 32);
g_fl_bus_valid_o <= '0';
if bool(g_fx2_bus_gotdata) then
g_fl_bus_chan_addr <= fx2Data_in(7-1 downto 0);
g_is_write <= fx2Data_in(7);
g_state <= GET_COUNT0;
end if;
end case;
end if;
end process COMM_FPGA_FX2_V2_G_HDL_SM;
g_fx2_bus_read <= g_fifop(0);
g_fx2_bus_write <= g_fifop(1);
end architecture MyHDL;
|
mit
|
1cf9667da10f3a01dab3c98f411b3f6e
| 0.476949 | 3.395404 | false | false | false | false |
thelonious/display4
|
rotary.vhd
| 1 | 1,469 |
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on Ben Jordon's code in this forum post:
-- http://forum.allaboutcircuits.com/showthread.php?t=23344
--
library ieee;
use ieee.std_logic_1164.all;
entity Rotary is
port(
clock: in std_logic;
A: in std_logic;
B: in std_logic;
inc: out std_logic;
dec: out std_logic
);
end Rotary;
architecture behavioral of Rotary is
signal prevA, prevB: std_logic;
signal currA, currB: std_logic;
begin
read_rotary: process(clock)
begin
if clock'event and clock = '1' then
prevA <= currA;
prevB <= currB;
currA <= A;
currB <= B;
if prevA = '0' and currA = '1' then -- a rising
if currB = '1' then
inc <= '0';
dec <= '1';
elsif currB = '0' then
inc <= '1';
dec <= '0';
end if;
elsif prevA = '1' and currA = '0' then -- a falling
if currB = '1' then
inc <= '1';
dec <= '0';
elsif currB = '0' then
inc <= '0';
dec <= '1';
end if;
elsif prevB = '0' and currB = '1' then -- b rising
if currA = '1' then
inc <= '1';
dec <= '0';
elsif currA = '0' then
inc <= '0';
dec <= '1';
end if;
elsif prevB = '1' and currB = '0' then -- b falling
if currA = '1' then
inc <= '0';
dec <= '1';
elsif currA = '0' then
inc <= '1';
dec <= '0';
end if;
else
inc <= '0';
dec <= '0';
end if;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
2728cc639b8a741d28acb46a38111775
| 0.543907 | 2.642086 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task5/keyboardsig.vhd
| 1 | 1,792 |
library ieee;
use ieee.std_logic_1164.all;
-- Module simulation a PS2 communication
entity keyboardSig is
port(
ps2c : out std_logic;
ps2d : out std_logic
);
end entity keyboardSig;
architecture RTL of keyboardSig is
signal TxData : std_logic_vector(7 downto 0);
-- Procedure for sending one dedicated data packet
procedure PS2Send(signal din : in std_logic_vector(7 downto 0);
signal ps2c : OUT std_logic;
signal ps2d : OUT std_logic) is
variable parity : std_logic := '1';
begin
wait for 1 ns;
ps2c <= '1';
ps2d <= '1';
wait for 5 us;
ps2d <= '0'; -- startbit
wait for 20 us;
ps2c <= '0';
wait for 40 us;
ps2c <= '1';
wait for 20 us;
parity := '1';
for i in 0 to 7 loop
ps2d <= din(i);
if (din(i) = '1') then
parity := not parity;
end if;
wait for 20 us;
ps2c <= '0';
wait for 40 us;
ps2c <= '1';
wait for 20 us;
end loop;
ps2d <= parity; -- parity
wait for 20 us;
ps2c <= '0';
wait for 40 us;
ps2c <= '1';
wait for 20 us;
ps2d <= '1'; -- stopbit
wait for 20 us;
ps2c <= '0';
wait for 40 us;
ps2c <= '1';
wait for 20 us;
end procedure;
begin
-- Simulus process which sends some dummy data
stim_proc : process
begin
wait for 100 ns;
TXData <= x"AA";
PS2Send(TXData, ps2c, ps2d);
wait for 100 us;
TXData <= x"55";
PS2Send(TXData, ps2c, ps2d);
wait for 100 us;
TXData <= x"11";
PS2Send(TXData, ps2c, ps2d);
wait for 100 us;
TXData <= x"80";
PS2Send(TXData, ps2c, ps2d);
wait for 100 us;
TXData <= x"01";
PS2Send(TXData, ps2c, ps2d);
wait for 100 us;
TXData <= x"C3";
PS2Send(TXData, ps2c, ps2d);
wait for 100 us;
wait;
end process;
end architecture RTL;
|
mit
|
6b7d652da159401f3aa1bce0a4be0b9a
| 0.583147 | 2.658754 | false | false | false | false |
samvartaka/simon_vhdl
|
MIXED_ROUND_PIPELINING/phi.vhd
| 3 | 898 |
-- SIMON 64/128
-- feistel round function operation phi
-- phi(x) = (((x << 1) & (x << 8)) xor (x << 2))
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- x_in: plaintext block right half
-- x_out: transformed block right half
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity phi is
port(x_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0)
);
end phi;
architecture Behavioral of phi is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_8_s : std_logic_vector(31 downto 0);
begin
op_1_s <= std_logic_vector(rotate_left(unsigned(x_in), 1));
op_2_s <= std_logic_vector(rotate_left(unsigned(x_in), 2));
op_8_s <= std_logic_vector(rotate_left(unsigned(x_in), 8));
x_out <= (op_1_s and op_8_s) xor op_2_s;
end Behavioral;
|
gpl-2.0
|
ac51da4f9b45d44c42aeb7e969f906a8
| 0.640312 | 2.721212 | false | false | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/ComparadorFinal.vhd
| 1 | 5,295 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: ComparadorFinal.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY ComparadorFinal IS
PORT
(
clken : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
AeB : OUT STD_LOGIC ;
AgB : OUT STD_LOGIC ;
AlB : OUT STD_LOGIC
);
END ComparadorFinal;
ARCHITECTURE SYN OF comparadorfinal IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clken : IN STD_LOGIC ;
AlB : OUT STD_LOGIC ;
clock : IN STD_LOGIC ;
AgB : OUT STD_LOGIC ;
AeB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AlB <= sub_wire0;
AgB <= sub_wire1;
AeB <= sub_wire2;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_pipeline => 4,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 5
)
PORT MAP (
dataa => dataa,
datab => datab,
clken => clken,
clock => clock,
AlB => sub_wire0,
AgB => sub_wire1,
AeB => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "4"
-- Retrieval info: PRIVATE: Latency NUMERIC "1"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "1"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: AeB 0 0 0 0 OUTPUT NODEFVAL AeB
-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB
-- Retrieval info: USED_PORT: AlB 0 0 0 0 OUTPUT NODEFVAL AlB
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: dataa 0 0 5 0 INPUT NODEFVAL dataa[4..0]
-- Retrieval info: USED_PORT: datab 0 0 5 0 INPUT NODEFVAL datab[4..0]
-- Retrieval info: CONNECT: AeB 0 0 0 0 @AeB 0 0 0 0
-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0
-- Retrieval info: CONNECT: AlB 0 0 0 0 @AlB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 5 0 dataa 0 0 5 0
-- Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL ComparadorFinal.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ComparadorFinal.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ComparadorFinal.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ComparadorFinal.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ComparadorFinal_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ComparadorFinal_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ComparadorFinal_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
069ab5083eeb3d3b758c80ea99ef0753
| 0.659112 | 3.671983 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/tb_pwm.vhd
| 1 | 1,006 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_pwm is
end tb_pwm;
architecture behav of tb_pwm is
signal clk_10 : std_logic := '0';
signal rst : std_logic := '0';
signal duty : std_logic_vector(7 downto 0) := "00000000";
signal outSig : std_logic := '0';
begin
process
begin
clk_10 <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
begin
wait for 205 ns;
rst <= '1';
wait for 205 ns;
rst <= '0';
wait for 10 ns;
wait for 5 ms;
duty <= X"64";
wait for 5 ms;
duty <= X"FF";
wait for 5 ms;
assert false report "done" severity failure;
wait;
end process;
pwm: entity work.pwmUnit
port map(
clk_10 =>clk_10,
rst =>rst,
duty =>duty,
outSig =>outSig
);
end behav;
|
mit
|
7455b5d6878d727a847329982b42fd70
| 0.533797 | 3.309211 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/clock_gen.vhd
| 1 | 1,442 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tb_package.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
entity clock_gen is
Port ( command_i : in command_rec;
clk_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
end clock_gen;
architecture Behavioral of clock_gen is
signal start : boolean := false;
signal s_clk_o : std_logic:='0';
signal width : time;
signal s_done_o : std_logic;
begin
clk_o <= s_clk_o;
done_o(0) <= 'Z';
done_o(1) <= s_done_o;
done_o(2) <= 'Z';
done_o(3) <= 'Z';
done_o(4) <= 'Z';
done_o(5) <= 'Z';
done_o(6) <= 'Z';
p_main: process
variable value1 : string(1 to 8);
begin
s_done_o <= '0';
wait on command_i;
if command_i.gen_number=1 then
if command_i.mnemonic(1 to 5)="start" then
value1:= command_i.value1;
width <=string_to_time(value1);
start <= true;
elsif command_i.mnemonic(1 to 4)="stop" then
start <= false;
end if;
s_done_o <= '1';
wait on s_done_o;
else
s_done_o <= '0';
start <= start;
end if;
end process p_main;
p_clock: process
begin
wait on start;
s_clk_o <='0';
while start loop
s_clk_o <= not s_clk_o;
wait for (width/2);
end loop;
end process p_clock;
end Behavioral;
|
mit
|
97071fac6db72f3daeee63c9109fa148
| 0.606796 | 2.650735 | false | false | false | false |
samvartaka/simon_vhdl
|
OUTER_ROUND_PIPELINING/key_schedule.vhd
| 2 | 16,248 |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal int_0 : std_logic_vector(31 downto 0);
signal int_1 : std_logic_vector(31 downto 0);
signal int_2 : std_logic_vector(31 downto 0);
signal int_3 : std_logic_vector(31 downto 0);
signal int_4 : std_logic_vector(31 downto 0);
signal int_5 : std_logic_vector(31 downto 0);
signal int_6 : std_logic_vector(31 downto 0);
signal int_7 : std_logic_vector(31 downto 0);
signal int_8 : std_logic_vector(31 downto 0);
signal int_9 : std_logic_vector(31 downto 0);
signal int_10 : std_logic_vector(31 downto 0);
signal int_11 : std_logic_vector(31 downto 0);
signal int_12 : std_logic_vector(31 downto 0);
signal int_13 : std_logic_vector(31 downto 0);
signal int_14 : std_logic_vector(31 downto 0);
signal int_15 : std_logic_vector(31 downto 0);
signal int_16 : std_logic_vector(31 downto 0);
signal int_17 : std_logic_vector(31 downto 0);
signal int_18 : std_logic_vector(31 downto 0);
signal int_19 : std_logic_vector(31 downto 0);
signal int_20 : std_logic_vector(31 downto 0);
signal int_21 : std_logic_vector(31 downto 0);
signal int_22 : std_logic_vector(31 downto 0);
signal int_23 : std_logic_vector(31 downto 0);
signal int_24 : std_logic_vector(31 downto 0);
signal int_25 : std_logic_vector(31 downto 0);
signal int_26 : std_logic_vector(31 downto 0);
signal int_27 : std_logic_vector(31 downto 0);
signal int_28 : std_logic_vector(31 downto 0);
signal int_29 : std_logic_vector(31 downto 0);
signal int_30 : std_logic_vector(31 downto 0);
signal int_31 : std_logic_vector(31 downto 0);
signal int_32 : std_logic_vector(31 downto 0);
signal int_33 : std_logic_vector(31 downto 0);
signal int_34 : std_logic_vector(31 downto 0);
signal int_35 : std_logic_vector(31 downto 0);
signal int_36 : std_logic_vector(31 downto 0);
signal int_37 : std_logic_vector(31 downto 0);
signal int_38 : std_logic_vector(31 downto 0);
signal int_39 : std_logic_vector(31 downto 0);
signal int_40 : std_logic_vector(31 downto 0);
signal int_41 : std_logic_vector(31 downto 0);
signal int_42 : std_logic_vector(31 downto 0);
signal int_43 : std_logic_vector(31 downto 0);
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal c_const : std_logic_vector(30 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
c_const <= "1111111111111111111111111111110";
-- Round 0 to 3
k_0 <= k_in_0;
int_0 <= k_in_0;
k_1 <= k_in_1;
int_1 <= k_in_1;
k_2 <= k_in_2;
int_2 <= k_in_2;
k_3 <= k_in_3;
int_3 <= k_in_3;
-- Round 4
int_4 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_3), 3)) xor int_1)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_3), 3)) xor int_1)
xor int_0 xor (c_const & sequence(0)));
k_4 <= int_4;
-- Round 5
int_5 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_4), 3)) xor int_2)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_4), 3)) xor int_2)
xor int_1 xor (c_const & sequence(1)));
k_5 <= int_5;
-- Round 6
int_6 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_5), 3)) xor int_3)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_5), 3)) xor int_3)
xor int_2 xor (c_const & sequence(2)));
k_6 <= int_6;
-- Round 7
int_7 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_6), 3)) xor int_4)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_6), 3)) xor int_4)
xor int_3 xor (c_const & sequence(3)));
k_7 <= int_7;
-- Round 8
int_8 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_7), 3)) xor int_5)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_7), 3)) xor int_5)
xor int_4 xor (c_const & sequence(4)));
k_8 <= int_8;
-- Round 9
int_9 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_8), 3)) xor int_6)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_8), 3)) xor int_6)
xor int_5 xor (c_const & sequence(5)));
k_9 <= int_9;
-- Round 10
int_10 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_9), 3)) xor int_7)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_9), 3)) xor int_7)
xor int_6 xor (c_const & sequence(6)));
k_10 <= int_10;
-- Round 11
int_11 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_10), 3)) xor int_8)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_10), 3)) xor int_8)
xor int_7 xor (c_const & sequence(7)));
k_11 <= int_11;
-- Round 12
int_12 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_11), 3)) xor int_9)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_11), 3)) xor int_9)
xor int_8 xor (c_const & sequence(8)));
k_12 <= int_12;
-- Round 13
int_13 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_12), 3)) xor int_10)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_12), 3)) xor int_10)
xor int_9 xor (c_const & sequence(9)));
k_13 <= int_13;
-- Round 14
int_14 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_13), 3)) xor int_11)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_13), 3)) xor int_11)
xor int_10 xor (c_const & sequence(10)));
k_14 <= int_14;
-- Round 15
int_15 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_14), 3)) xor int_12)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_14), 3)) xor int_12)
xor int_11 xor (c_const & sequence(11)));
k_15 <= int_15;
-- Round 16
int_16 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_15), 3)) xor int_13)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_15), 3)) xor int_13)
xor int_12 xor (c_const & sequence(12)));
k_16 <= int_16;
-- Round 17
int_17 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_16), 3)) xor int_14)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_16), 3)) xor int_14)
xor int_13 xor (c_const & sequence(13)));
k_17 <= int_17;
-- Round 18
int_18 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_17), 3)) xor int_15)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_17), 3)) xor int_15)
xor int_14 xor (c_const & sequence(14)));
k_18 <= int_18;
-- Round 19
int_19 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_18), 3)) xor int_16)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_18), 3)) xor int_16)
xor int_15 xor (c_const & sequence(15)));
k_19 <= int_19;
-- Round 20
int_20 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_19), 3)) xor int_17)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_19), 3)) xor int_17)
xor int_16 xor (c_const & sequence(16)));
k_20 <= int_20;
-- Round 21
int_21 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_20), 3)) xor int_18)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_20), 3)) xor int_18)
xor int_17 xor (c_const & sequence(17)));
k_21 <= int_21;
-- Round 22
int_22 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_21), 3)) xor int_19)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_21), 3)) xor int_19)
xor int_18 xor (c_const & sequence(18)));
k_22 <= int_22;
-- Round 23
int_23 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_22), 3)) xor int_20)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_22), 3)) xor int_20)
xor int_19 xor (c_const & sequence(19)));
k_23 <= int_23;
-- Round 24
int_24 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_23), 3)) xor int_21)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_23), 3)) xor int_21)
xor int_20 xor (c_const & sequence(20)));
k_24 <= int_24;
-- Round 25
int_25 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_24), 3)) xor int_22)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_24), 3)) xor int_22)
xor int_21 xor (c_const & sequence(21)));
k_25 <= int_25;
-- Round 26
int_26 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_25), 3)) xor int_23)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_25), 3)) xor int_23)
xor int_22 xor (c_const & sequence(22)));
k_26 <= int_26;
-- Round 27
int_27 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_26), 3)) xor int_24)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_26), 3)) xor int_24)
xor int_23 xor (c_const & sequence(23)));
k_27 <= int_27;
-- Round 28
int_28 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_27), 3)) xor int_25)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_27), 3)) xor int_25)
xor int_24 xor (c_const & sequence(24)));
k_28 <= int_28;
-- Round 29
int_29 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_28), 3)) xor int_26)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_28), 3)) xor int_26)
xor int_25 xor (c_const & sequence(25)));
k_29 <= int_29;
-- Round 30
int_30 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_29), 3)) xor int_27)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_29), 3)) xor int_27)
xor int_26 xor (c_const & sequence(26)));
k_30 <= int_30;
-- Round 31
int_31 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_30), 3)) xor int_28)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_30), 3)) xor int_28)
xor int_27 xor (c_const & sequence(27)));
k_31 <= int_31;
-- Round 32
int_32 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_31), 3)) xor int_29)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_31), 3)) xor int_29)
xor int_28 xor (c_const & sequence(28)));
k_32 <= int_32;
-- Round 33
int_33 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_32), 3)) xor int_30)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_32), 3)) xor int_30)
xor int_29 xor (c_const & sequence(29)));
k_33 <= int_33;
-- Round 34
int_34 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_33), 3)) xor int_31)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_33), 3)) xor int_31)
xor int_30 xor (c_const & sequence(30)));
k_34 <= int_34;
-- Round 35
int_35 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_34), 3)) xor int_32)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_34), 3)) xor int_32)
xor int_31 xor (c_const & sequence(31)));
k_35 <= int_35;
-- Round 36
int_36 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_35), 3)) xor int_33)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_35), 3)) xor int_33)
xor int_32 xor (c_const & sequence(32)));
k_36 <= int_36;
-- Round 37
int_37 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_36), 3)) xor int_34)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_36), 3)) xor int_34)
xor int_33 xor (c_const & sequence(33)));
k_37 <= int_37;
-- Round 38
int_38 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_37), 3)) xor int_35)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_37), 3)) xor int_35)
xor int_34 xor (c_const & sequence(34)));
k_38 <= int_38;
-- Round 39
int_39 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_38), 3)) xor int_36)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_38), 3)) xor int_36)
xor int_35 xor (c_const & sequence(35)));
k_39 <= int_39;
-- Round 40
int_40 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_39), 3)) xor int_37)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_39), 3)) xor int_37)
xor int_36 xor (c_const & sequence(36)));
k_40 <= int_40;
-- Round 41
int_41 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_40), 3)) xor int_38)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_40), 3)) xor int_38)
xor int_37 xor (c_const & sequence(37)));
k_41 <= int_41;
-- Round 42
int_42 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_41), 3)) xor int_39)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_41), 3)) xor int_39)
xor int_38 xor (c_const & sequence(38)));
k_42 <= int_42;
-- Round 43
int_43 <= (std_logic_vector(rotate_right(unsigned((std_logic_vector(rotate_right(unsigned(int_42), 3)) xor int_40)), 1))
xor (std_logic_vector(rotate_right(unsigned(int_42), 3)) xor int_40)
xor int_39 xor (c_const & sequence(39)));
k_43 <= int_43;
end Behavioral;
|
gpl-2.0
|
d3c116d22c7396bea822f5689078310c
| 0.648141 | 2.723433 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task5/lcd16x2_ctrl.vhd
| 1 | 10,129 |
-------------------------------------------------------------------------------
-- Title : 16x2 LCD controller
-- Project :
-------------------------------------------------------------------------------
-- File : lcd16x2_ctrl.vhd
-- Author : <stachelsau@T420>
-- Company :
-- Created : 2012-07-28
-- Last update: 2012-11-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The controller initializes the display when rst goes to '0'.
-- After that it writes the contend of the input signals
-- line1_buffer and line2_buffer continously to the display.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-07-28 1.0 stachelsau Created
-------------------------------------------------------------------------------
-- This file is distributed under the LGPL
-- See http://opencores.org/project,16x2_lcd_controller
library ieee;
use ieee.std_logic_1164.all;
library work;
entity lcd16x2_ctrl is
generic (
CLK_PERIOD_NS : positive := 20); -- 50MHz
port (
clk : in std_logic;
rst : in std_logic;
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_db : out std_logic_vector(7 downto 4);
line1_buffer : in std_logic_vector(127 downto 0); -- 16x8bit
line2_buffer : in std_logic_vector(127 downto 0));
end entity lcd16x2_ctrl;
architecture rtl of lcd16x2_ctrl is
constant DELAY_15_MS : positive := 15 * 10**6 / CLK_PERIOD_NS + 1;
constant DELAY_1640_US : positive := 1640 * 10**3 / CLK_PERIOD_NS + 1;
constant DELAY_4100_US : positive := 4100 * 10**3 / CLK_PERIOD_NS + 1;
constant DELAY_100_US : positive := 100 * 10**3 / CLK_PERIOD_NS + 1;
constant DELAY_40_US : positive := 40 * 10**3 / CLK_PERIOD_NS + 1;
constant DELAY_NIBBLE : positive := 10**3 / CLK_PERIOD_NS + 1;
constant DELAY_LCD_E : positive := 230 / CLK_PERIOD_NS + 1;
constant DELAY_SETUP_HOLD : positive := 40 / CLK_PERIOD_NS + 1;
constant MAX_DELAY : positive := DELAY_15_MS;
-- this record describes one write operation
type op_t is record
rs : std_logic;
data : std_logic_vector(7 downto 0);
delay_h : integer range 0 to MAX_DELAY;
delay_l : integer range 0 to MAX_DELAY;
end record op_t;
constant default_op : op_t := (rs => '1', data => X"00", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
constant op_select_line1 : op_t := (rs => '0', data => X"80", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
constant op_select_line2 : op_t := (rs => '0', data => X"C0", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US);
-- init + config operations:
-- write 3 x 0x3 followed by 0x2
-- function set command
-- entry mode set command
-- display on/off command
-- clear display
type config_ops_t is array(0 to 5) of op_t;
constant config_ops : config_ops_t
:= (5 => (rs => '0', data => X"33", delay_h => DELAY_4100_US, delay_l => DELAY_100_US),
4 => (rs => '0', data => X"32", delay_h => DELAY_40_US, delay_l => DELAY_40_US),
3 => (rs => '0', data => X"28", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US),
2 => (rs => '0', data => X"06", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US),
1 => (rs => '0', data => X"0C", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US),
0 => (rs => '0', data => X"01", delay_h => DELAY_NIBBLE, delay_l => DELAY_1640_US));
signal this_op : op_t;
type op_state_t is (IDLE,
WAIT_SETUP_H,
ENABLE_H,
WAIT_HOLD_H,
WAIT_DELAY_H,
WAIT_SETUP_L,
ENABLE_L,
WAIT_HOLD_L,
WAIT_DELAY_L,
DONE);
signal op_state : op_state_t := DONE;
signal next_op_state : op_state_t;
signal cnt : natural range 0 to MAX_DELAY;
signal next_cnt : natural range 0 to MAX_DELAY;
type state_t is (RESET,
CONFIG,
SELECT_LINE1,
WRITE_LINE1,
SELECT_LINE2,
WRITE_LINE2);
signal state : state_t := RESET;
signal next_state : state_t;
signal ptr : natural range 0 to 15 := 0;
signal next_ptr : natural range 0 to 15;
begin
proc_state : process(state, op_state, ptr, line1_buffer, line2_buffer) is
begin
case state is
when RESET =>
this_op <= default_op;
next_state <= CONFIG;
next_ptr <= config_ops_t'high;
when CONFIG =>
this_op <= config_ops(ptr);
next_ptr <= ptr;
next_state <= CONFIG;
if op_state = DONE then
next_ptr <= ptr - 1;
if ptr = 0 then
next_state <= SELECT_LINE1;
end if;
end if;
when SELECT_LINE1 =>
this_op <= op_select_line1;
next_ptr <= 15;
if op_state = DONE then
next_state <= WRITE_LINE1;
else
next_state <= SELECT_LINE1;
end if;
when WRITE_LINE1 =>
this_op <= default_op;
this_op.data <= line1_buffer(ptr*8 + 7 downto ptr*8);
next_ptr <= ptr;
next_state <= WRITE_LINE1;
if op_state = DONE then
next_ptr <= ptr - 1;
if ptr = 0 then
next_state <= SELECT_LINE2;
end if;
end if;
when SELECT_LINE2 =>
this_op <= op_select_line2;
next_ptr <= 15;
if op_state = DONE then
next_state <= WRITE_LINE2;
else
next_state <= SELECT_LINE2;
end if;
when WRITE_LINE2 =>
this_op <= default_op;
this_op.data <= line2_buffer(ptr*8 + 7 downto ptr*8);
next_ptr <= ptr;
next_state <= WRITE_LINE2;
if op_state = DONE then
next_ptr <= ptr - 1;
if ptr = 0 then
next_state <= SELECT_LINE1;
end if;
end if;
end case;
end process proc_state;
reg_state : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= RESET;
ptr <= 0;
else
state <= next_state;
ptr <= next_ptr;
end if;
end if;
end process reg_state;
-- we never read from the lcd
lcd_rw <= '0';
proc_op_state : process(op_state, cnt, this_op) is
begin
case op_state is
when IDLE =>
lcd_db <= (others => '0');
lcd_rs <= '0';
lcd_e <= '0';
next_op_state <= WAIT_SETUP_H;
next_cnt <= DELAY_SETUP_HOLD;
when WAIT_SETUP_H =>
lcd_db <= this_op.data(7 downto 4);
lcd_rs <= this_op.rs;
lcd_e <= '0';
if cnt = 0 then
next_op_state <= ENABLE_H;
next_cnt <= DELAY_LCD_E;
else
next_op_state <= WAIT_SETUP_H;
next_cnt <= cnt - 1;
end if;
when ENABLE_H =>
lcd_db <= this_op.data(7 downto 4);
lcd_rs <= this_op.rs;
lcd_e <= '1';
if cnt = 0 then
next_op_state <= WAIT_HOLD_H;
next_cnt <= DELAY_SETUP_HOLD;
else
next_op_state <= ENABLE_H;
next_cnt <= cnt - 1;
end if;
when WAIT_HOLD_H =>
lcd_db <= this_op.data(7 downto 4);
lcd_rs <= this_op.rs;
lcd_e <= '0';
if cnt = 0 then
next_op_state <= WAIT_DELAY_H;
next_cnt <= this_op.delay_h;
else
next_op_state <= WAIT_HOLD_H;
next_cnt <= cnt - 1;
end if;
when WAIT_DELAY_H =>
lcd_db <= (others => '0');
lcd_rs <= '0';
lcd_e <= '0';
if cnt = 0 then
next_op_state <= WAIT_SETUP_L;
next_cnt <= DELAY_SETUP_HOLD;
else
next_op_state <= WAIT_DELAY_H;
next_cnt <= cnt - 1;
end if;
when WAIT_SETUP_L =>
lcd_db <= this_op.data(3 downto 0);
lcd_rs <= this_op.rs;
lcd_e <= '0';
if cnt = 0 then
next_op_state <= ENABLE_L;
next_cnt <= DELAY_LCD_E;
else
next_op_state <= WAIT_SETUP_L;
next_cnt <= cnt - 1;
end if;
when ENABLE_L =>
lcd_db <= this_op.data(3 downto 0);
lcd_rs <= this_op.rs;
lcd_e <= '1';
if cnt = 0 then
next_op_state <= WAIT_HOLD_L;
next_cnt <= DELAY_SETUP_HOLD;
else
next_op_state <= ENABLE_L;
next_cnt <= cnt - 1;
end if;
when WAIT_HOLD_L =>
lcd_db <= this_op.data(3 downto 0);
lcd_rs <= this_op.rs;
lcd_e <= '0';
if cnt = 0 then
next_op_state <= WAIT_DELAY_L;
next_cnt <= this_op.delay_l;
else
next_op_state <= WAIT_HOLD_L;
next_cnt <= cnt - 1;
end if;
when WAIT_DELAY_L =>
lcd_db <= (others => '0');
lcd_rs <= '0';
lcd_e <= '0';
if cnt = 0 then
next_op_state <= DONE;
next_cnt <= 0;
else
next_op_state <= WAIT_DELAY_L;
next_cnt <= cnt - 1;
end if;
when DONE =>
lcd_db <= (others => '0');
lcd_rs <= '0';
lcd_e <= '0';
next_op_state <= IDLE;
next_cnt <= 0;
end case;
end process proc_op_state;
reg_op_state : process (clk) is
begin
if rising_edge(clk) then
if state = RESET then
op_state <= IDLE;
else
op_state <= next_op_state;
cnt <= next_cnt;
end if;
end if;
end process reg_op_state;
end architecture rtl;
|
mit
|
e1d8c17ff7bb83458c52ddee2e1f5a02
| 0.468358 | 3.519458 | false | false | false | false |
samvartaka/simon_vhdl
|
MIXED_ROUND_PIPELINING/tb_simon.vhd
| 1 | 2,671 |
-- SIMON 64/128
-- Encryption & decryption test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_simon IS
END tb_simon;
ARCHITECTURE behavior OF tb_simon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT simon
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal enc : std_logic := '0';
signal key : std_logic_vector(127 downto 0) := (others => '0');
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal block_out : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: simon PORT MAP (
clk => clk,
rst => rst,
enc => enc,
key => key,
block_in => block_in,
block_out => block_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- ==============================================
-- T_0: Test encryption and subsequent decryption
-- ==============================================
-- SIMON 64/128 test vectors
block_in <= X"656b696c20646e75";
key <= X"1b1a1918131211100b0a090803020100";
-- Test encryption
enc <= '0';
-- Initialize
rst <= '1';
-- Wait for initialization
wait for clk_period;
-- Run
rst <= '0';
-- Wait for registers
wait for 44*clk_period;
assert block_out = X"44c8fc20b9dfa07a"
report "ENCRYPT ERROR (e_0)" severity FAILURE;
-- Use output of encryption as input for decryption
block_in <= block_out;
-- Test decryption
enc <= '1';
-- Initialize
rst <= '1';
-- Wait for initialization
wait for clk_period;
-- Run
rst <= '0';
-- Wait for registers
wait for 44*clk_period;
assert block_out = X"656b696c20646e75"
report "DECRYPT ERROR (d_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
d03cd893a9387330a0893b912ce4e4bd
| 0.581056 | 3.419974 | false | true | false | false |
sahandKashani/HDL-IP-cores
|
i2c/hdl/i2c_core.vhd
| 5 | 21,685 |
------------------------------------------------------
-- i2c_core.vhd - I2C core V2 logic
------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.4 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 22-mar-2002 CG 0.2 complete rewrite
-- 27-mar-2002 CG 0.3 minor corrections
-- 02-apr-2002 CG 0.4 sync. of outputs
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_core is
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
-- state : out std_logic_vector(5 downto 0)
);
end i2c_core;
architecture behavorial of i2c_core is
type state_type is (
s_Reset, s_Idle, s_Done, s_DoneAck,
s_Start_A, s_Start_B, s_Start_C, s_Start_D,
s_Stop_A, s_Stop_B, s_Stop_C,
s_Rd_A, s_Rd_B, s_Rd_C, s_Rd_D, s_Rd_E, s_Rd_F,
s_RdAck_A, s_RdAck_B, s_RdAck_C, s_RdAck_D, s_RdAck_E,
s_Wr_A, s_Wr_B, s_Wr_C, s_Wr_D, s_Wr_E,
s_WrAck_A, s_WrAck_B, s_WrAck_C, s_WrAck_D
);
-- data output register
signal i_dout_ld : std_logic;
signal i_dout : std_logic_vector(7 downto 0);
-- ack output register
signal i_ack_out_ld : std_logic;
signal i_ack_out : std_logic;
-- data input bit
signal i_data_in : std_logic;
-- bit counter
signal i_ctr : unsigned(2 downto 0);
signal i_ctr_incr : std_logic;
signal i_ctr_clr : std_logic;
signal p_state : state_type;
signal n_state : state_type;
signal i_scl_out : std_logic;
signal i_sda_out : std_logic;
signal i_sclk_en : std_logic;
signal i_cmd_done : std_logic;
signal i_cmd_go : std_logic;
signal i_busy : std_logic;
begin
-- syncronize output signals
output_sync : process(clk, rst)
begin
if (rst = '1') then
scl_out <= '1';
sda_out <= '1';
data_out <= (others => '0');
ack_out <= '0';
busy <= '0';
cmd_done <= '0';
elsif (rising_edge(clk)) then
scl_out <= i_scl_out;
sda_out <= i_sda_out;
data_out <= i_dout;
ack_out <= i_ack_out;
busy <= i_busy;
cmd_done <= i_cmd_done;
end if;
end process output_sync;
-- select current bit
data_input_selector : process(i_ctr, data_in)
begin
case i_ctr is
when "000" => i_data_in <= data_in(7);
when "001" => i_data_in <= data_in(6);
when "010" => i_data_in <= data_in(5);
when "011" => i_data_in <= data_in(4);
when "100" => i_data_in <= data_in(3);
when "101" => i_data_in <= data_in(2);
when "110" => i_data_in <= data_in(1);
when "111" => i_data_in <= data_in(0);
when others => null;
end case;
end process data_input_selector;
-- indicate start of command
i_cmd_go <= (cmd_read OR cmd_write) AND NOT i_busy;
-- i2c bit counter
counter : process(clk, rst)
begin
if (rst = '1') then
i_ctr <= (others => '0');
elsif (rising_edge(clk)) then
if (i_ctr_clr = '1') then
i_ctr <= (others => '0');
elsif (i_ctr_incr = '1') then
i_ctr <= i_ctr + 1;
end if;
end if;
end process counter;
-- data output register
dout_reg : process(clk, rst)
begin
if (rst = '1') then
i_dout <= (others => '0');
elsif (rising_edge(clk)) then
if (i_dout_ld = '1') then
case i_ctr is
when "000" => i_dout(7) <= sda_in;
when "001" => i_dout(6) <= sda_in;
when "010" => i_dout(5) <= sda_in;
when "011" => i_dout(4) <= sda_in;
when "100" => i_dout(3) <= sda_in;
when "101" => i_dout(2) <= sda_in;
when "110" => i_dout(1) <= sda_in;
when "111" => i_dout(0) <= sda_in;
when others => null;
end case;
end if;
end if;
end process dout_reg;
-- ack bit output register
ack_out_reg : process(clk, rst)
begin
if (rst = '1') then
i_ack_out <= '0';
elsif (rising_edge(clk)) then
if (i_ack_out_ld = '1') then
i_ack_out <= sda_in;
end if;
end if;
end process ack_out_reg;
-- i2c send / receive byte
i2c_sync : process(rst, clk)
begin
if (rst = '1') then
p_state <= s_Reset;
elsif (rising_edge(clk)) then
if ((sclk = '1' and i_sclk_en = '1') or i_sclk_en = '0') then
p_state <= n_state;
end if;
end if;
end process i2c_sync;
i2c_comb : process(p_state, sda_in, scl_in, i_cmd_go, i_ctr, ack_in, i_data_in, cmd_start, cmd_stop, cmd_write, cmd_read, cmd_done_ack)
begin
n_state <= p_state;
--n_state <= p_state;
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
--i_dout_ld <= '0';
--i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
--state <= "111111";
case p_state is
when s_Reset =>
--state <= "000000";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Idle;
when s_Idle =>
--state <= "000001";
i_sclk_en <= '0';
i_busy <= '0';
i_ctr_clr <= '1';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (i_cmd_go = '1') then
if (cmd_start = '1') then
-- do a START
n_state <= s_Start_A;
elsif (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
end if;
when s_Start_A =>
--state <= "001000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= scl_in;
n_state <= s_Start_B;
when s_Start_B =>
--state <= "001001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Start_C;
when s_Start_C =>
--state <= "001010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Start_D;
when s_Start_D =>
--state <= "001011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
if (cmd_write = '1') then
-- do a WRITE
n_state <= s_Wr_A;
elsif (cmd_read = '1') then
-- do a READ
n_state <= s_Rd_A;
end if;
when s_Rd_A =>
--state <= "010000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_B;
when s_Rd_B =>
--state <= "010001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_C;
when s_Rd_C =>
--state <= "010010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '1';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_D;
when s_Rd_D =>
--state <= "010011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Rd_E;
when s_Rd_E =>
--state <= "010100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKOUT
n_state <= s_WrAck_A;
else
-- increment bit counter
n_state <= s_Rd_F;
end if;
when s_Rd_F =>
--state <= "010101";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_Rd_A;
when s_WrAck_A =>
--state <= "011000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
n_state <= s_WrAck_B;
when s_WrAck_B =>
--state <= "011001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_C;
when s_WrAck_C =>
--state <= "011010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '1';
n_state <= s_WrAck_D;
when s_WrAck_D =>
--state <= "011011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= ack_in;
i_scl_out <= '0';
-- do a STOP ?
if (cmd_stop = '1') then
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Wr_A =>
--state <= "100000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_B;
when s_Wr_B =>
--state <= "100001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_C;
when s_Wr_C =>
--state <= "100010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '1';
n_state <= s_Wr_D;
when s_Wr_D =>
--state <= "100011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
if (i_ctr = 7) then
-- do ACKIN
n_state <= s_RdAck_A;
else
-- increment bit counter
n_state <= s_Wr_E;
end if;
when s_Wr_E =>
--state <= "100100";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '1';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= i_data_in;
i_scl_out <= '0';
n_state <= s_Wr_A;
when s_RdAck_A =>
--state <= "101000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
n_state <= s_RdAck_B;
when s_RdAck_B =>
--state <= "101001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_C;
when s_RdAck_C =>
--state <= "101010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '1';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_D;
when s_RdAck_D =>
--state <= "101011";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_RdAck_E;
when s_RdAck_E =>
--state <= "101100";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '0';
if (cmd_stop = '1') then
-- do a STOP
n_state <= s_Stop_A;
else
-- we are DONE
n_state <= s_Done;
end if;
when s_Stop_A =>
--state <= "111000";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '0';
n_state <= s_Stop_B;
when s_Stop_B =>
--state <= "111001";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '0';
i_scl_out <= '1';
n_state <= s_Stop_C;
when s_Stop_C =>
--state <= "111010";
i_sclk_en <= '1';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '0';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= '1';
i_scl_out <= '1';
n_state <= s_Done;
when s_Done =>
--state <= "000010";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
n_state <= s_DoneAck;
when s_DoneAck =>
--state <= "000011";
i_sclk_en <= '0';
i_busy <= '1';
i_ctr_clr <= '0';
i_ctr_incr <= '0';
i_cmd_done <= '1';
i_dout_ld <= '0';
i_ack_out_ld <= '0';
i_sda_out <= sda_in;
i_scl_out <= scl_in;
if (cmd_done_ack = '1') then
n_state <= s_Idle;
end if;
end case;
end process i2c_comb;
end behavorial;
|
unlicense
|
eb0351ef11a2bf8a1ca1e4fd1ea11f34
| 0.307877 | 3.510442 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/reset_gen.vhd
| 1 | 1,539 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tb_package.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
entity reset_gen is
Port ( command_i : in command_rec;
reset_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
end reset_gen;
architecture Behavioral of reset_gen is
signal duration : time;
signal start : boolean:=false;
signal s_done_o : std_logic;
begin
-- signal assignement
done_o(0) <= s_done_o;
done_o(1) <= 'Z';
done_o(2) <= 'Z';
done_o(3) <= 'Z';
done_o(4) <= 'Z';
done_o(5) <= 'Z';
done_o(6) <= 'Z';
-- signal assignement
p_main: process
--variable duration : time;
variable value1 : string(1 to 8);
begin
s_done_o <= '0';
--reset_o <= '0';
wait on command_i;
if command_i.gen_number=0 then
-- done_o(0) <= '1';
if command_i.mnemonic(1 to 5)="start" then
value1:= command_i.value1;
duration<=string_to_time(value1);
start <= true; -- new
wait until start'EVENT and start=true;
start <= false; -- new
s_done_o <= '1';
wait on s_done_o;
end if;
end if;
end process p_main;
p_reset: process
variable reset_length : time;
begin
reset_o <= '0';
wait until start'EVENT and start=true;
reset_length := duration;
reset_o <= '1';
wait for reset_length;
end process p_reset;
end Behavioral;
|
mit
|
fdc532c09ee3a1a1757a3a8e54f7ec43
| 0.614685 | 2.85 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/rotkey.vhd
| 1 | 1,775 |
library ieee;
use ieee.std_logic_1164.all;
entity rotKey is
generic(
CNT : integer := 5000 -- 30 ms at 50 MHz
);
port(
clk_50 : in std_logic;
rotA : in std_logic;
rotB : in std_logic;
rotPush : in std_logic;
rotRightEvent : out std_logic;
rotLeftEvent : out std_logic;
rotPushEvent : out std_logic
);
end entity rotKey;
architecture RTL of rotKey is
-- Declaration of the debounce component
component debounce
port(clk_50 : in std_logic;
input : in std_logic;
output : out std_logic;
riseedge : out std_logic;
falledge : out std_logic);
end component debounce;
signal rotA_d : std_logic;
signal rotB_d : std_logic;
signal rotA_rise : std_logic;
signal rotA_fall : std_logic;
signal rotB_rise : std_logic;
signal rotB_fall : std_logic;
begin
deb_rotA: entity work.debounce
generic map(
CNT => CNT)
port map(
clk_50 => clk_50,
input => rotA,
output => rotA_d,
riseedge => rotA_rise,
falledge => rotA_fall
);
deb_rotB: entity work.debounce
generic map(
CNT => CNT)
port map(
clk_50 => clk_50,
input => rotB,
output => rotB_d,
riseedge => rotB_rise,
falledge => rotB_fall
);
deb_rotPush: entity work.debounce
generic map(
CNT => CNT)
port map(
clk_50 => clk_50,
input => rotPush,
output => open,
riseedge => rotPushEvent,
falledge => open
);
rotRightEvent <= '1' when rotA_rise = '1' and rotB_d = '0' else
'0';
rotLeftEvent <= '1' when rotB_rise = '1' and rotA_d = '0' else
'0';
end architecture RTL;
|
mit
|
124026692f28a1fce5c6fb5b8b06ce33
| 0.550423 | 3.564257 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task5/ps2receiver.vhd
| 1 | 3,532 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity ps2Receiver is
generic(
TIMEOUT :integer := 5000 -- = 100us at 50Mhz
);
port(
clk : in std_logic;
rst : in std_logic;
-- data
rxData : out std_logic_vector(7 downto 0);
-- module sync signals
dataReady : out std_logic;
dataFetched : in std_logic;
-- ps2 pins
ps2Data : in std_logic;
ps2Clk : in std_logic
);
end entity ps2Receiver;
architecture RTL of ps2Receiver is
signal ps2Clk_sync : std_logic_vector(1 downto 0);
signal ps2Clk_dly : std_logic;
signal ps2Clk_fall : std_logic;
type state_type is (idle, wait_start, shift, check);
signal fsm : state_type;
signal data : std_logic_vector(10 downto 0);
signal bit_cnt : integer;
signal timeout_cnt : integer;
function xor_many(input : std_logic_vector) return std_logic is
variable result : std_logic;
variable i : integer;
begin
result := '0';
for i in input'low to input'high
loop
result := result xor input(i);
end loop;
return result;
end;
begin
ps2Clk_synchronizer: process(clk)
begin
if rising_edge(clk) then
ps2Clk_sync <= ps2Clk & ps2Clk_sync(1);
end if;
end process ps2Clk_synchronizer;
ps2Clk_delay: process(clk)
begin
if rising_edge(clk) then
ps2Clk_dly <= ps2Clk_sync(0);
end if;
end process ps2Clk_delay;
ps2Clk_fall <= (not ps2Clk_sync(0)) and ps2Clk_dly;
timeout_process: process(clk, rst)
begin
if rst = '1' then
timeout_cnt <= 0;
elsif rising_edge(clk) then
if ps2Clk_fall = '1' or timeout_cnt = TIMEOUT then
timeout_cnt <= 0;
else
timeout_cnt <= timeout_cnt + 1;
end if;
end if;
end process;
fsm_p: process(clk, rst)
begin
if rst = '1' then
fsm <= idle;
bit_cnt <= 0;
data <= (others => '1');
rxData <= (others => '0');
dataReady <= '0';
elsif rising_edge(clk) then
case fsm is
when idle =>
if dataFetched = '1' then
fsm <= wait_start;
dataReady <= '0';
end if;
when wait_start =>
if ps2Clk_fall = '1' and ps2Data = '0' then
fsm <= shift;
bit_cnt <= 0;
data <= (10 => '0', others => '1');
end if;
when shift =>
if timeout_cnt = TIMEOUT then
fsm <= idle;
end if;
if ps2Clk_fall = '1' then
bit_cnt <= bit_cnt + 1;
data <= ps2Data & data(10 downto 1);
end if;
if bit_cnt = 10 then
fsm <= check;
end if;
when check =>
fsm <= idle;
if xor_many(data(9 downto 1)) = '1' and data(0) = '0' and data(10) = '1' then
rxData <= data(8 downto 1);
dataReady <= '1';
end if;
end case;
end if;
end process fsm_p;
end architecture RTL;
|
mit
|
09b8fb3194efca63762b31a7403b8644
| 0.464043 | 3.973003 | false | false | false | false |
twasiluk/hdmilight
|
fpga/avr/common.vhd
| 3 | 7,859 |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: common
-- Create Date: 13:51:24 11/07/2009
-- Description: constants shared by different modules.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package common is
-----------------------------------------------------------------------
-- ALU operations
--
constant ALU_ADC : std_logic_vector(4 downto 0) := "00000";
constant ALU_ADD : std_logic_vector(4 downto 0) := "00001";
constant ALU_ADIW : std_logic_vector(4 downto 0) := "00010";
constant ALU_AND : std_logic_vector(4 downto 0) := "00011";
constant ALU_ASR : std_logic_vector(4 downto 0) := "00100";
constant ALU_BLD : std_logic_vector(4 downto 0) := "00101";
constant ALU_BIT_CS : std_logic_vector(4 downto 0) := "00110";
constant ALU_COM : std_logic_vector(4 downto 0) := "00111";
constant ALU_DEC : std_logic_vector(4 downto 0) := "01000";
constant ALU_EOR : std_logic_vector(4 downto 0) := "01001";
constant ALU_MV_16 : std_logic_vector(4 downto 0) := "01010";
constant ALU_INC : std_logic_vector(4 downto 0) := "01011";
constant ALU_INTR : std_logic_vector(4 downto 0) := "01100";
constant ALU_LSR : std_logic_vector(4 downto 0) := "01101";
constant ALU_D_MV_Q : std_logic_vector(4 downto 0) := "01110";
constant ALU_R_MV_Q : std_logic_vector(4 downto 0) := "01111";
constant ALU_MULT : std_logic_vector(4 downto 0) := "10000";
constant ALU_NEG : std_logic_vector(4 downto 0) := "10001";
constant ALU_OR : std_logic_vector(4 downto 0) := "10010";
constant ALU_PC_1 : std_logic_vector(4 downto 0) := "10011";
constant ALU_PC_2 : std_logic_vector(4 downto 0) := "10100";
constant ALU_ROR : std_logic_vector(4 downto 0) := "10101";
constant ALU_SBC : std_logic_vector(4 downto 0) := "10110";
constant ALU_SBIW : std_logic_vector(4 downto 0) := "10111";
constant ALU_SREG : std_logic_vector(4 downto 0) := "11000";
constant ALU_SUB : std_logic_vector(4 downto 0) := "11001";
constant ALU_SWAP : std_logic_vector(4 downto 0) := "11010";
-----------------------------------------------------------------------
--
-- PC manipulations
--
constant PC_NEXT : std_logic_vector(2 downto 0) := "000"; -- PC += 1
constant PC_BCC : std_logic_vector(2 downto 0) := "001"; -- PC ?= IMM
constant PC_LD_I : std_logic_vector(2 downto 0) := "010"; -- PC = IMM
constant PC_LD_Z : std_logic_vector(2 downto 0) := "011"; -- PC = Z
constant PC_LD_S : std_logic_vector(2 downto 0) := "100"; -- PC = (SP)
constant PC_SKIP_Z : std_logic_vector(2 downto 0) := "101"; -- SKIP if Z
constant PC_SKIP_T : std_logic_vector(2 downto 0) := "110"; -- SKIP if T
-----------------------------------------------------------------------
--
-- Addressing modes. An address mode consists of two sub-fields,
-- which are the source of the address and an offset from the source.
-- Bit 3 indicates if the address will be modified.
-- address source
constant AS_SP : std_logic_vector(2 downto 0) := "000"; -- SP
constant AS_Z : std_logic_vector(2 downto 0) := "001"; -- Z
constant AS_Y : std_logic_vector(2 downto 0) := "010"; -- Y
constant AS_X : std_logic_vector(2 downto 0) := "011"; -- X
constant AS_IMM : std_logic_vector(2 downto 0) := "100"; -- IMM
-- address offset
constant AO_0 : std_logic_vector(5 downto 3) := "000"; -- as is
constant AO_Q : std_logic_vector(5 downto 3) := "010"; -- +q
constant AO_i : std_logic_vector(5 downto 3) := "001"; -- +1
constant AO_ii : std_logic_vector(5 downto 3) := "011"; -- +2
constant AO_d : std_logic_vector(5 downto 3) := "101"; -- -1
constant AO_dd : std_logic_vector(5 downto 3) := "111"; -- -2
-- |
-- +--+
-- address updated ? |
-- v
constant AM_WX : std_logic_vector(3 downto 0) := '1' & AS_X; -- X ++ or --
constant AM_WY : std_logic_vector(3 downto 0) := '1' & AS_Y; -- Y ++ or --
constant AM_WZ : std_logic_vector(3 downto 0) := '1' & AS_Z; -- Z ++ or --
constant AM_WS : std_logic_vector(3 downto 0) := '1' & AS_SP; -- SP ++/--
-- address modes used
--
constant AMOD_ABS : std_logic_vector(5 downto 0) := AO_0 & AS_IMM; -- IMM
constant AMOD_X : std_logic_vector(5 downto 0) := AO_0 & AS_X; -- X
constant AMOD_Xq : std_logic_vector(5 downto 0) := AO_Q & AS_X; -- X+q
constant AMOD_Xi : std_logic_vector(5 downto 0) := AO_i & AS_X; -- X+
constant AMOD_dX : std_logic_vector(5 downto 0) := AO_d & AS_X; -- -X
constant AMOD_Y : std_logic_vector(5 downto 0) := AO_0 & AS_Y; -- Y
constant AMOD_Yq : std_logic_vector(5 downto 0) := AO_Q & AS_Y; -- Y+q
constant AMOD_Yi : std_logic_vector(5 downto 0) := AO_i & AS_Y; -- Y+
constant AMOD_dY : std_logic_vector(5 downto 0) := AO_d & AS_Y; -- -Y
constant AMOD_Z : std_logic_vector(5 downto 0) := AO_0 & AS_Z; -- Z
constant AMOD_Zq : std_logic_vector(5 downto 0) := AO_Q & AS_Z; -- Z+q
constant AMOD_Zi : std_logic_vector(5 downto 0) := AO_i & AS_Z; -- Z+
constant AMOD_dZ : std_logic_vector(5 downto 0) := AO_d & AS_Z; -- -Z
constant AMOD_iSP : std_logic_vector(5 downto 0) := AO_i & AS_SP; -- +SP
constant AMOD_iiSP: std_logic_vector(5 downto 0) := AO_ii & AS_SP; -- ++SP
constant AMOD_SPd : std_logic_vector(5 downto 0) := AO_d & AS_SP; -- SP-
constant AMOD_SPdd: std_logic_vector(5 downto 0) := AO_dd & AS_SP; -- SP--
-----------------------------------------------------------------------
--
-- ALU multiplexers.
--
constant RS_REG : std_logic_vector(1 downto 0) := "00";
constant RS_IMM : std_logic_vector(1 downto 0) := "01";
constant RS_DIN : std_logic_vector(1 downto 0) := "10";
-----------------------------------------------------------------------
--
-- Multiplier variants. F means FMULT (as opposed to MULT).
-- S and U means signed vs. unsigned operands.
--
constant MULT_UU : std_logic_vector(2 downto 0) := "000";
constant MULT_SU : std_logic_vector(2 downto 0) := "010";
constant MULT_SS : std_logic_vector(2 downto 0) := "011";
constant MULT_FUU : std_logic_vector(2 downto 0) := "100";
constant MULT_FSU : std_logic_vector(2 downto 0) := "110";
constant MULT_FSS : std_logic_vector(2 downto 0) := "111";
-----------------------------------------------------------------------
end common;
|
gpl-2.0
|
1d21b7ef66fa2792557832dd22b3964d
| 0.521695 | 3.44693 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task2/uart_transmit.vhd
| 1 | 2,568 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:53 10/01/2013
-- Design Name:
-- Module Name: uart_transmit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_transmit is
port(
rst_i : in std_logic;
clk_i : in std_logic;
TopTX : in std_logic;
Din_i : in std_logic_vector(7 downto 0);
Tx_o : out std_logic;
TxBusy_o: out std_logic;
LD_i : in std_logic
);
end uart_transmit;
architecture Behavioral of uart_transmit is
type state_type is (idle, load_tx, shift_tx, stop_tx);
signal Tx_Reg : std_logic_vector(9 downto 0);
signal RegDin : std_logic_vector(7 downto 0);
signal TxBitCnt : natural;
signal TxFSM : state_type;
begin
-- --------------------------
-- Transmit State Machine
-- --------------------------
TX_o <= Tx_Reg(0);
Tx_FSM: process (rst_i, clk_i)
begin
if rst_i='1' then
Tx_Reg <= (others => '1');
TxBitCnt <= 0;
TxFSM <= idle;
TxBusy_o <= '0';
RegDin <= (others=>'0');
elsif rising_edge(clk_i) then
case TxFSM is
when Idle =>
if Ld_i = '1' then
TxFSM <= Load_tx;
RegDin <= Din_i;
TxBusy_o <= '1';
end if;
when Load_Tx =>
if TopTX = '1' then
TxFSM <= Shift_tx;
TxBitCnt <= 10;
Tx_Reg <= '1' & RegDin & '0';
end if;
when Shift_Tx =>
if TopTX = '1' then
if TXBitCnt = 1 then
TxFSM <= Stop_tx;
end if;
TxBitCnt <= TxBitCnt - 1;
Tx_Reg <= '1' & Tx_Reg(9 downto 1);
end if;
when Stop_Tx =>
if TopTX = '1' then
TxFSM <= Idle;
TxBusy_o <= '0';
end if;
when others =>
TxFSM <= Idle;
end case;
end if;
end process;
end Behavioral;
|
mit
|
e0975ad9e0162e97a041fa5158b184bd
| 0.487539 | 3.844311 | false | false | false | false |
samvartaka/simon_vhdl
|
OUTER_ROUND_PIPELINING/tb_keyschedule.vhd
| 3 | 10,132 |
-- SIMON 64/128
-- key schedule test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.NUMERIC_STD.ALL;
ENTITY tb_keyschedule IS
END tb_keyschedule;
ARCHITECTURE behavior OF tb_keyschedule IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT key_schedule
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- k0..3
--Outputs
signal k_0 : std_logic_vector(31 downto 0);
signal k_1 : std_logic_vector(31 downto 0);
signal k_2 : std_logic_vector(31 downto 0);
signal k_3 : std_logic_vector(31 downto 0);
signal k_4 : std_logic_vector(31 downto 0);
signal k_5 : std_logic_vector(31 downto 0);
signal k_6 : std_logic_vector(31 downto 0);
signal k_7 : std_logic_vector(31 downto 0);
signal k_8 : std_logic_vector(31 downto 0);
signal k_9 : std_logic_vector(31 downto 0);
signal k_10 : std_logic_vector(31 downto 0);
signal k_11 : std_logic_vector(31 downto 0);
signal k_12 : std_logic_vector(31 downto 0);
signal k_13 : std_logic_vector(31 downto 0);
signal k_14 : std_logic_vector(31 downto 0);
signal k_15 : std_logic_vector(31 downto 0);
signal k_16 : std_logic_vector(31 downto 0);
signal k_17 : std_logic_vector(31 downto 0);
signal k_18 : std_logic_vector(31 downto 0);
signal k_19 : std_logic_vector(31 downto 0);
signal k_20 : std_logic_vector(31 downto 0);
signal k_21 : std_logic_vector(31 downto 0);
signal k_22 : std_logic_vector(31 downto 0);
signal k_23 : std_logic_vector(31 downto 0);
signal k_24 : std_logic_vector(31 downto 0);
signal k_25 : std_logic_vector(31 downto 0);
signal k_26 : std_logic_vector(31 downto 0);
signal k_27 : std_logic_vector(31 downto 0);
signal k_28 : std_logic_vector(31 downto 0);
signal k_29 : std_logic_vector(31 downto 0);
signal k_30 : std_logic_vector(31 downto 0);
signal k_31 : std_logic_vector(31 downto 0);
signal k_32 : std_logic_vector(31 downto 0);
signal k_33 : std_logic_vector(31 downto 0);
signal k_34 : std_logic_vector(31 downto 0);
signal k_35 : std_logic_vector(31 downto 0);
signal k_36 : std_logic_vector(31 downto 0);
signal k_37 : std_logic_vector(31 downto 0);
signal k_38 : std_logic_vector(31 downto 0);
signal k_39 : std_logic_vector(31 downto 0);
signal k_40 : std_logic_vector(31 downto 0);
signal k_41 : std_logic_vector(31 downto 0);
signal k_42 : std_logic_vector(31 downto 0);
signal k_43 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: key_schedule PORT MAP (
k_in_0 => key_s(0),
k_in_1 => key_s(1),
k_in_2 => key_s(2),
k_in_3 => key_s(3),
k_0 => k_0,
k_1 => k_1,
k_2 => k_2,
k_3 => k_3,
k_4 => k_4,
k_5 => k_5,
k_6 => k_6,
k_7 => k_7,
k_8 => k_8,
k_9 => k_9,
k_10 => k_10,
k_11 => k_11,
k_12 => k_12,
k_13 => k_13,
k_14 => k_14,
k_15 => k_15,
k_16 => k_16,
k_17 => k_17,
k_18 => k_18,
k_19 => k_19,
k_20 => k_20,
k_21 => k_21,
k_22 => k_22,
k_23 => k_23,
k_24 => k_24,
k_25 => k_25,
k_26 => k_26,
k_27 => k_27,
k_28 => k_28,
k_29 => k_29,
k_30 => k_30,
k_31 => k_31,
k_32 => k_32,
k_33 => k_33,
k_34 => k_34,
k_35 => k_35,
k_36 => k_36,
k_37 => k_37,
k_38 => k_38,
k_39 => k_39,
k_40 => k_40,
k_41 => k_41,
k_42 => k_42,
k_43 => k_43
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- Round 0
key_s(0) <= X"03020100";
key_s(1) <= X"0b0a0908";
key_s(2) <= X"13121110";
key_s(3) <= X"1b1a1918";
wait for 20*clk_period;
assert k_0 = X"03020100"
report "KEY_SCHEDULE ERROR (0)" severity FAILURE;
assert k_1 = X"0b0a0908"
report "KEY_SCHEDULE ERROR (1)" severity FAILURE;
assert k_2 = X"13121110"
report "KEY_SCHEDULE ERROR (2)" severity FAILURE;
assert k_3 = X"1b1a1918"
report "KEY_SCHEDULE ERROR (3)" severity FAILURE;
assert k_4 = X"70a011c3"
report "KEY_SCHEDULE ERROR (4)" severity FAILURE;
assert k_5 = X"b770ec49"
report "KEY_SCHEDULE ERROR (5)" severity FAILURE;
assert k_6 = X"57e3e835"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_7 = X"d397bc42"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_8 = X"94dcf81f"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_9 = X"bf4b5f18"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_10 = X"8e5dabb9"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_11 = X"dbf4a863"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_12 = X"cd0c28fc"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_13 = X"5cb69911"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_14 = X"79f112a5"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_15 = X"77205863"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_16 = X"99880c12"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_17 = X"1ce97c58"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_18 = X"c8ed2145"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_19 = X"b800dbb8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_20 = X"e86a2756"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_21 = X"7c06d4dd"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_22 = X"ab52df0a"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_23 = X"247f66a8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_24 = X"53587ca6"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_25 = X"d25c13f1"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_26 = X"4583b64b"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_27 = X"7d9c960d"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_28 = X"efbfc2f3"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_29 = X"89ed8513"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_30 = X"308dfc4e"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_31 = X"bf1a2a36"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_32 = X"e1499d70"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_33 = X"4ce4d2ff"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_34 = X"32b7ebef"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_35 = X"c47505c1"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_36 = X"d0e929e8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_37 = X"8fe484b9"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_38 = X"42054bee"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_39 = X"af77bae2"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_40 = X"18199c02"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_41 = X"719e3f1c"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_42 = X"0c1cf793"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
assert k_43 = X"15df4696"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
e023ac8e06fa2feb1e6d5367f4793af5
| 0.628504 | 2.762268 | false | false | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/Acumulador_inst.vhd
| 1 | 163 |
Acumulador_inst : Acumulador PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
result => result_sig
);
|
mit
|
9cc19a4279c845ed89e5c2931bf2a91e
| 0.576687 | 2.859649 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_SEPERATE_RAMROUTE/key_schedule.vhd
| 1 | 1,848 |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
r : in std_logic_vector(7 downto 0);
-- we don't need k_2 here because of the way we schedule k(r) in the simon component
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal seqC : std_logic_vector(31 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
-- 0xFFFFFFFFFFFFFFFC xor sequence[(r-4) % 62]
-- TODO: 1-bit latch for seqC(0) is used, not recommended...
seqC <= ("1111111111111111111111111111110" & sequence((to_integer(unsigned(r)) - 4) mod 62)) when (to_integer(unsigned(r)) > 3) else "11111111111111111111111111111100";
-- tmp = K[3] >> 3
op_3_s <= std_logic_vector(rotate_right(unsigned(k_3), 3));
-- tmp = tmp xor k[1]
op_xor_0 <= (op_3_s xor k_1);
-- tmp >> 1
op_1_s <= std_logic_vector(rotate_right(unsigned(op_xor_0), 1));
-- Original NSA specification lists ~K[0] ^ 3 but this can be rewritten to K[0] ^ ((1 << word_size)-4) where the latter can be stored as a constant for speed
subkey_out <= k_0 when (to_integer(unsigned(r)) < 4) else (op_1_s xor op_xor_0 xor k_0 xor seqC);
end Behavioral;
|
gpl-2.0
|
79f9e5f33e84a7c2a3b26234bf566b4c
| 0.655844 | 3.019608 | false | false | false | false |
gralco/click-clock-board
|
myhdl/pck_myhdl_081.vhd
| 1 | 3,363 |
-- File: pck_myhdl_081.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sat May 28 18:39:08 2016
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_081 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_081;
package body pck_myhdl_081 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_081;
|
gpl-3.0
|
e61c481b97b824658f02b5d9d4ce7530
| 0.601249 | 4.022727 | false | false | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/A.vhd
| 1 | 4,757 |
-- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: A.vhd
-- Megafunction Name(s):
-- altaccumulate
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY A IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END A;
ARCHITECTURE SYN OF a IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(4 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 4,
width_out => 5
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
0cfe82d99ea6b0b710609ad7c0e0c602
| 0.630439 | 3.611997 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
cmos_sensor_input/hdl/cmos_sensor_input_avalon_st_source.vhd
| 5 | 3,540 |
library ieee;
use ieee.std_logic_1164.all;
entity cmos_sensor_input_avalon_st_source is
generic(
DATA_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- Avalon-ST Source
ready : in std_logic;
valid : out std_logic;
data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- fifo
fifo_read : out std_logic;
fifo_empty : in std_logic;
fifo_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
fifo_end_of_frame : in std_logic;
fifo_overflow : in std_logic;
-- sampler
end_of_frame_out : out std_logic;
end_of_frame_out_ack : in std_logic
);
end entity cmos_sensor_input_avalon_st_source;
architecture rtl of cmos_sensor_input_avalon_st_source is
type state_type is (STATE_IDLE, STATE_READY_CYCLE, STATE_WAIT_END_OF_FRAME_ACK);
signal reg_state, next_reg_state : state_type;
signal data_little_endian : std_logic_vector(data'range);
signal data_big_endian : std_logic_vector(data'range);
begin
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
elsif rising_edge(clk) then
if stop_and_reset = '1' then
reg_state <= STATE_IDLE;
else
reg_state <= next_reg_state;
end if;
end if;
end process;
NEXT_STATE_LOGIC : process(data_big_endian, end_of_frame_out_ack, fifo_empty, fifo_end_of_frame, fifo_overflow, ready, reg_state)
begin
fifo_read <= '0';
valid <= '0';
data <= (others => '0');
end_of_frame_out <= '0';
next_reg_state <= reg_state;
case reg_state is
when STATE_IDLE =>
if ready = '1' then
next_reg_state <= STATE_READY_CYCLE;
end if;
when STATE_READY_CYCLE =>
if ready = '0' then
next_reg_state <= STATE_IDLE;
end if;
if fifo_empty = '0' and fifo_overflow = '0' then
fifo_read <= '1';
valid <= '1';
data <= data_big_endian;
if fifo_end_of_frame = '1' then
next_reg_state <= STATE_WAIT_END_OF_FRAME_ACK;
end if;
end if;
when STATE_WAIT_END_OF_FRAME_ACK =>
end_of_frame_out <= '1';
if end_of_frame_out_ack = '1' then
next_reg_state <= STATE_IDLE;
end if;
end case;
end process;
data_little_endian <= fifo_data;
NETWORK_ORDER : process(data_little_endian)
begin
-- data is an Avalon-ST interface, so it needs to arrange data in
-- network order (a.k.a big-endian).
-- This component is specified to support 8 bits per symbol for its
-- Avalon-ST interface, so data is flipped on 8-bit boundaries.
for i in 0 to (DATA_WIDTH / 8) - 1 loop
data_big_endian(8 * (i + 1) - 1 downto 8 * i) <= data_little_endian(data_little_endian'length - 8 * i - 1 downto data_little_endian'length - 8 * (i + 1));
end loop;
end process;
end architecture rtl;
|
unlicense
|
a0020b25f59ae586a8ab4d9ff4aa0dd8
| 0.504237 | 3.79015 | false | false | false | false |
samvartaka/simon_vhdl
|
LOOP_UNROLL/simon.vhd
| 1 | 10,907 |
-- SIMON 64/128
-- Simon core component
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end component;
component round_f
port(enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- intermediate key (in words)
signal k_0 : std_logic_vector(31 downto 0);
signal k_1 : std_logic_vector(31 downto 0);
signal k_2 : std_logic_vector(31 downto 0);
signal k_3 : std_logic_vector(31 downto 0);
signal k_4 : std_logic_vector(31 downto 0);
signal k_5 : std_logic_vector(31 downto 0);
signal k_6 : std_logic_vector(31 downto 0);
signal k_7 : std_logic_vector(31 downto 0);
signal k_8 : std_logic_vector(31 downto 0);
signal k_9 : std_logic_vector(31 downto 0);
signal k_10 : std_logic_vector(31 downto 0);
signal k_11 : std_logic_vector(31 downto 0);
signal k_12 : std_logic_vector(31 downto 0);
signal k_13 : std_logic_vector(31 downto 0);
signal k_14 : std_logic_vector(31 downto 0);
signal k_15 : std_logic_vector(31 downto 0);
signal k_16 : std_logic_vector(31 downto 0);
signal k_17 : std_logic_vector(31 downto 0);
signal k_18 : std_logic_vector(31 downto 0);
signal k_19 : std_logic_vector(31 downto 0);
signal k_20 : std_logic_vector(31 downto 0);
signal k_21 : std_logic_vector(31 downto 0);
signal k_22 : std_logic_vector(31 downto 0);
signal k_23 : std_logic_vector(31 downto 0);
signal k_24 : std_logic_vector(31 downto 0);
signal k_25 : std_logic_vector(31 downto 0);
signal k_26 : std_logic_vector(31 downto 0);
signal k_27 : std_logic_vector(31 downto 0);
signal k_28 : std_logic_vector(31 downto 0);
signal k_29 : std_logic_vector(31 downto 0);
signal k_30 : std_logic_vector(31 downto 0);
signal k_31 : std_logic_vector(31 downto 0);
signal k_32 : std_logic_vector(31 downto 0);
signal k_33 : std_logic_vector(31 downto 0);
signal k_34 : std_logic_vector(31 downto 0);
signal k_35 : std_logic_vector(31 downto 0);
signal k_36 : std_logic_vector(31 downto 0);
signal k_37 : std_logic_vector(31 downto 0);
signal k_38 : std_logic_vector(31 downto 0);
signal k_39 : std_logic_vector(31 downto 0);
signal k_40 : std_logic_vector(31 downto 0);
signal k_41 : std_logic_vector(31 downto 0);
signal k_42 : std_logic_vector(31 downto 0);
signal k_43 : std_logic_vector(31 downto 0);
signal ct_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_1 : std_logic_vector(63 downto 0);
signal ct_2 : std_logic_vector(63 downto 0);
signal ct_3 : std_logic_vector(63 downto 0);
signal ct_4 : std_logic_vector(63 downto 0);
signal ct_5 : std_logic_vector(63 downto 0);
signal ct_6 : std_logic_vector(63 downto 0);
signal ct_7 : std_logic_vector(63 downto 0);
signal ct_8 : std_logic_vector(63 downto 0);
signal ct_9 : std_logic_vector(63 downto 0);
signal ct_10 : std_logic_vector(63 downto 0);
signal ct_11 : std_logic_vector(63 downto 0);
signal ct_12 : std_logic_vector(63 downto 0);
signal ct_13 : std_logic_vector(63 downto 0);
signal ct_14 : std_logic_vector(63 downto 0);
signal ct_15 : std_logic_vector(63 downto 0);
signal ct_16 : std_logic_vector(63 downto 0);
signal ct_17 : std_logic_vector(63 downto 0);
signal ct_18 : std_logic_vector(63 downto 0);
signal ct_19 : std_logic_vector(63 downto 0);
signal ct_20 : std_logic_vector(63 downto 0);
signal ct_21 : std_logic_vector(63 downto 0);
signal ct_22 : std_logic_vector(63 downto 0);
signal ct_23 : std_logic_vector(63 downto 0);
signal ct_24 : std_logic_vector(63 downto 0);
signal ct_25 : std_logic_vector(63 downto 0);
signal ct_26 : std_logic_vector(63 downto 0);
signal ct_27 : std_logic_vector(63 downto 0);
signal ct_28 : std_logic_vector(63 downto 0);
signal ct_29 : std_logic_vector(63 downto 0);
signal ct_30 : std_logic_vector(63 downto 0);
signal ct_31 : std_logic_vector(63 downto 0);
signal ct_32 : std_logic_vector(63 downto 0);
signal ct_33 : std_logic_vector(63 downto 0);
signal ct_34 : std_logic_vector(63 downto 0);
signal ct_35 : std_logic_vector(63 downto 0);
signal ct_36 : std_logic_vector(63 downto 0);
signal ct_37 : std_logic_vector(63 downto 0);
signal ct_38 : std_logic_vector(63 downto 0);
signal ct_39 : std_logic_vector(63 downto 0);
signal ct_40 : std_logic_vector(63 downto 0);
signal ct_41 : std_logic_vector(63 downto 0);
signal ct_42 : std_logic_vector(63 downto 0);
signal ct_43 : std_logic_vector(63 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (
key_s(0), key_s(1), key_s(2), key_s(3),
k_0, k_1, k_2, k_3, k_4, k_5, k_6, k_7, k_8, k_9, k_10,
k_11, k_12, k_13, k_14, k_15, k_16, k_17, k_18, k_19, k_20,
k_21, k_22, k_23, k_24, k_25, k_26, k_27, k_28, k_29, k_30,
k_31, k_32, k_33, k_34, k_35, k_36, k_37, k_38, k_39, k_40,
k_41, k_42, k_43);
ROUND_F_0 : round_f port map (enc, block_in, k_0, k_43, ct_0);
ROUND_F_1 : round_f port map (enc, ct_0, k_1, k_42, ct_1);
ROUND_F_2 : round_f port map (enc, ct_1, k_2, k_41, ct_2);
ROUND_F_3 : round_f port map (enc, ct_2, k_3, k_40, ct_3);
ROUND_F_4 : round_f port map (enc, ct_3, k_4, k_39, ct_4);
ROUND_F_5 : round_f port map (enc, ct_4, k_5, k_38, ct_5);
ROUND_F_6 : round_f port map (enc, ct_5, k_6, k_37, ct_6);
ROUND_F_7 : round_f port map (enc, ct_6, k_7, k_36, ct_7);
ROUND_F_8 : round_f port map (enc, ct_7, k_8, k_35, ct_8);
ROUND_F_9 : round_f port map (enc, ct_8, k_9, k_34, ct_9);
ROUND_F_10 : round_f port map (enc, ct_9, k_10, k_33, ct_10);
ROUND_F_11 : round_f port map (enc, ct_10, k_11, k_32, ct_11);
ROUND_F_12 : round_f port map (enc, ct_11, k_12, k_31, ct_12);
ROUND_F_13 : round_f port map (enc, ct_12, k_13, k_30, ct_13);
ROUND_F_14 : round_f port map (enc, ct_13, k_14, k_29, ct_14);
ROUND_F_15 : round_f port map (enc, ct_14, k_15, k_28, ct_15);
ROUND_F_16 : round_f port map (enc, ct_15, k_16, k_27, ct_16);
ROUND_F_17 : round_f port map (enc, ct_16, k_17, k_26, ct_17);
ROUND_F_18 : round_f port map (enc, ct_17, k_18, k_25, ct_18);
ROUND_F_19 : round_f port map (enc, ct_18, k_19, k_24, ct_19);
ROUND_F_20 : round_f port map (enc, ct_19, k_20, k_23, ct_20);
ROUND_F_21 : round_f port map (enc, ct_20, k_21, k_22, ct_21);
ROUND_F_22 : round_f port map (enc, ct_21, k_22, k_21, ct_22);
ROUND_F_23 : round_f port map (enc, ct_22, k_23, k_20, ct_23);
ROUND_F_24 : round_f port map (enc, ct_23, k_24, k_19, ct_24);
ROUND_F_25 : round_f port map (enc, ct_24, k_25, k_18, ct_25);
ROUND_F_26 : round_f port map (enc, ct_25, k_26, k_17, ct_26);
ROUND_F_27 : round_f port map (enc, ct_26, k_27, k_16, ct_27);
ROUND_F_28 : round_f port map (enc, ct_27, k_28, k_15, ct_28);
ROUND_F_29 : round_f port map (enc, ct_28, k_29, k_14, ct_29);
ROUND_F_30 : round_f port map (enc, ct_29, k_30, k_13, ct_30);
ROUND_F_31 : round_f port map (enc, ct_30, k_31, k_12, ct_31);
ROUND_F_32 : round_f port map (enc, ct_31, k_32, k_11, ct_32);
ROUND_F_33 : round_f port map (enc, ct_32, k_33, k_10, ct_33);
ROUND_F_34 : round_f port map (enc, ct_33, k_34, k_9, ct_34);
ROUND_F_35 : round_f port map (enc, ct_34, k_35, k_8, ct_35);
ROUND_F_36 : round_f port map (enc, ct_35, k_36, k_7, ct_36);
ROUND_F_37 : round_f port map (enc, ct_36, k_37, k_6, ct_37);
ROUND_F_38 : round_f port map (enc, ct_37, k_38, k_5, ct_38);
ROUND_F_39 : round_f port map (enc, ct_38, k_39, k_4, ct_39);
ROUND_F_40 : round_f port map (enc, ct_39, k_40, k_3, ct_40);
ROUND_F_41 : round_f port map (enc, ct_40, k_41, k_2, ct_41);
ROUND_F_42 : round_f port map (enc, ct_41, k_42, k_1, ct_42);
ROUND_F_43 : round_f port map (enc, ct_42, k_43, k_0, ct_43);
block_out <= ct_43;
-- SIMON Core
pr_smn : process(clk, enc, key, key_s)
begin
if rising_edge(clk) then
-- no rst switch/phase distinction needed due to full unrolling of key schedule
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
end if;
end process;
end Behavioral;
|
gpl-2.0
|
9a59df5c55bcad5cb0c3e8c05bc8136f
| 0.638122 | 2.453216 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/rotkeygen.vhd
| 1 | 1,215 |
library ieee;
use ieee.std_logic_1164.all;
-- Simulates the A and B signal of the rotatory key encoder
entity rotKeyGen is
port (
A: out std_logic;
B: out std_logic;
Push : out std_logic
);
end entity rotKeyGen;
architecture RTL of rotKeyGen is
begin
-- This process generates the A and B signals
-- YOU may modify this for your own test cases !
process
begin
while TRUE loop
A<='0';
B<='0';
wait for 300 ns;
A<='1';
B<='0';
wait for 10 ns;
A<='0';
B<='0';
wait for 10 ns;
A<='1';
B<='0';
wait for 200 ns;
A<='1';
B<='1';
wait for 10 ns;
A<='1';
B<='0';
wait for 10 ns;
A<='1';
B<='1';
wait for 1 us;
A<='0';
B<='1';
wait for 10 ns;
A<='1';
B<='1';
wait for 10 ns;
A<='0';
B<='1';
wait for 200 ns;
A<='0';
B<='0';
wait for 10 ns;
A<='0';
B<='1';
wait for 10 ns;
A<='0';
B<='0';
wait for 500 ns;
wait for 200 ns;
A<='0';
B<='1';
wait for 200 ns;
A<='1';
B<='1';
wait for 1 us;
A<='1';
B<='0';
wait for 200 ns;
A<='0';
B<='0';
wait for 100 ms;
end loop;
end process;
end architecture RTL;
|
mit
|
ab43956358e04b14310bcdd5bf02bac7
| 0.487243 | 2.601713 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_SEPERATE_RAMROUTE/tb_ram.vhd
| 5 | 2,692 |
----------------------------------------------------------------------------------
-- Company: Digital Security Gorup - Faculty of Science - University of Radbound
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/02/2015
-- Design Name: TB_RAM
-- Module Name: TB_RAM
-- Project Name: Example
-- Target Devices: Any
-- Tool versions:
--
-- Description:
--
-- A simple test bench for the simple RAM
--
-- Dependencies:
-- VHDL-93
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
-- - Modified RAM to store 40*32 bits for the round keys (Jos Wetzels & Wouter Bokslag)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ram is
Generic (
PERIOD : time := 10 ns
);
end tb_ram;
architecture Behavioral of tb_ram is
component ram
Port (
data_in : in STD_LOGIC_VECTOR(31 downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(7 downto 0);
data_out : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
signal test_data_in : STD_LOGIC_VECTOR(31 downto 0);
signal test_rw : STD_LOGIC;
signal test_address : STD_LOGIC_VECTOR(7 downto 0);
signal test_data_out : STD_LOGIC_VECTOR(31 downto 0);
signal clk : STD_LOGIC := '0';
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
begin
test : ram
Port Map(
data_in => test_data_in,
rw => test_rw,
clk => clk,
address => test_address,
data_out => test_data_out
);
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
end loop;
wait;
end process;
process
begin
wait for PERIOD/2;
test_data_in <= X"03020100";
test_rw <= '1';
test_address <= X"00";
wait for PERIOD;
test_data_in <= X"0b0a0908";
test_rw <= '1';
test_address <= X"01";
wait for PERIOD;
test_data_in <= X"13121110";
test_rw <= '1';
test_address <= X"02";
wait for PERIOD;
test_data_in <= X"1b1a1918";
test_rw <= '1';
test_address <= X"03";
wait for PERIOD;
test_rw <= '0';
test_address <= X"00";
wait for PERIOD;
assert test_data_out = X"03020100" report "Error in RAM" severity FAILURE;
test_address <= X"01";
wait for PERIOD;
assert test_data_out = X"0b0a0908" report "Error in RAM" severity FAILURE;
test_address <= X"02";
wait for PERIOD;
assert test_data_out = X"13121110" report "Error in RAM" severity FAILURE;
test_address <= X"03";
wait for PERIOD;
assert test_data_out = X"1b1a1918" report "Error in RAM" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for PERIOD;
wait;
end process;
end Behavioral;
|
gpl-2.0
|
755244a46afcba838972741381f48030
| 0.611813 | 3.052154 | false | true | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/Comparador17.vhd
| 1 | 4,810 |
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: Comparador17.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Comparador17 IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
AgeB : OUT STD_LOGIC
);
END Comparador17;
ARCHITECTURE SYN OF comparador17 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
AgeB : OUT STD_LOGIC ;
clock : IN STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire1_bv(4 DOWNTO 0) <= "10001";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
AgeB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_pipeline => 2,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 5
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
clock => clock,
AgeB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
-- Retrieval info: PRIVATE: Latency NUMERIC "1"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "17"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: AgeB 0 0 0 0 OUTPUT NODEFVAL AgeB
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: dataa 0 0 5 0 INPUT NODEFVAL dataa[4..0]
-- Retrieval info: CONNECT: AgeB 0 0 0 0 @AgeB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 5 0 dataa 0 0 5 0
-- Retrieval info: CONNECT: @datab 0 0 5 0 17 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador17_wave*.jpg TRUE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
a8c53831b1bf3a228181f120f57f45b9
| 0.661123 | 3.691481 | false | false | false | false |
samvartaka/simon_vhdl
|
MIXED_ROUND_PIPELINING/simon.vhd
| 1 | 17,071 |
-- SIMON 64/128
-- Simon core component
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end component;
component round_f
port(clk : in std_logic;
rst : in std_logic;
enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END component;
component reg_64 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(63 downto 0);
data_out : out std_logic_vector(63 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- intermediate key (in words)
signal k_0 : std_logic_vector(31 downto 0);
signal k_1 : std_logic_vector(31 downto 0);
signal k_2 : std_logic_vector(31 downto 0);
signal k_3 : std_logic_vector(31 downto 0);
signal k_4 : std_logic_vector(31 downto 0);
signal k_5 : std_logic_vector(31 downto 0);
signal k_6 : std_logic_vector(31 downto 0);
signal k_7 : std_logic_vector(31 downto 0);
signal k_8 : std_logic_vector(31 downto 0);
signal k_9 : std_logic_vector(31 downto 0);
signal k_10 : std_logic_vector(31 downto 0);
signal k_11 : std_logic_vector(31 downto 0);
signal k_12 : std_logic_vector(31 downto 0);
signal k_13 : std_logic_vector(31 downto 0);
signal k_14 : std_logic_vector(31 downto 0);
signal k_15 : std_logic_vector(31 downto 0);
signal k_16 : std_logic_vector(31 downto 0);
signal k_17 : std_logic_vector(31 downto 0);
signal k_18 : std_logic_vector(31 downto 0);
signal k_19 : std_logic_vector(31 downto 0);
signal k_20 : std_logic_vector(31 downto 0);
signal k_21 : std_logic_vector(31 downto 0);
signal k_22 : std_logic_vector(31 downto 0);
signal k_23 : std_logic_vector(31 downto 0);
signal k_24 : std_logic_vector(31 downto 0);
signal k_25 : std_logic_vector(31 downto 0);
signal k_26 : std_logic_vector(31 downto 0);
signal k_27 : std_logic_vector(31 downto 0);
signal k_28 : std_logic_vector(31 downto 0);
signal k_29 : std_logic_vector(31 downto 0);
signal k_30 : std_logic_vector(31 downto 0);
signal k_31 : std_logic_vector(31 downto 0);
signal k_32 : std_logic_vector(31 downto 0);
signal k_33 : std_logic_vector(31 downto 0);
signal k_34 : std_logic_vector(31 downto 0);
signal k_35 : std_logic_vector(31 downto 0);
signal k_36 : std_logic_vector(31 downto 0);
signal k_37 : std_logic_vector(31 downto 0);
signal k_38 : std_logic_vector(31 downto 0);
signal k_39 : std_logic_vector(31 downto 0);
signal k_40 : std_logic_vector(31 downto 0);
signal k_41 : std_logic_vector(31 downto 0);
signal k_42 : std_logic_vector(31 downto 0);
signal k_43 : std_logic_vector(31 downto 0);
signal ct_in_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_in_1 : std_logic_vector(63 downto 0);
signal ct_in_2 : std_logic_vector(63 downto 0);
signal ct_in_3 : std_logic_vector(63 downto 0);
signal ct_in_4 : std_logic_vector(63 downto 0);
signal ct_in_5 : std_logic_vector(63 downto 0);
signal ct_in_6 : std_logic_vector(63 downto 0);
signal ct_in_7 : std_logic_vector(63 downto 0);
signal ct_in_8 : std_logic_vector(63 downto 0);
signal ct_in_9 : std_logic_vector(63 downto 0);
signal ct_in_10 : std_logic_vector(63 downto 0);
signal ct_in_11 : std_logic_vector(63 downto 0);
signal ct_in_12 : std_logic_vector(63 downto 0);
signal ct_in_13 : std_logic_vector(63 downto 0);
signal ct_in_14 : std_logic_vector(63 downto 0);
signal ct_in_15 : std_logic_vector(63 downto 0);
signal ct_in_16 : std_logic_vector(63 downto 0);
signal ct_in_17 : std_logic_vector(63 downto 0);
signal ct_in_18 : std_logic_vector(63 downto 0);
signal ct_in_19 : std_logic_vector(63 downto 0);
signal ct_in_20 : std_logic_vector(63 downto 0);
signal ct_in_21 : std_logic_vector(63 downto 0);
signal ct_in_22 : std_logic_vector(63 downto 0);
signal ct_in_23 : std_logic_vector(63 downto 0);
signal ct_in_24 : std_logic_vector(63 downto 0);
signal ct_in_25 : std_logic_vector(63 downto 0);
signal ct_in_26 : std_logic_vector(63 downto 0);
signal ct_in_27 : std_logic_vector(63 downto 0);
signal ct_in_28 : std_logic_vector(63 downto 0);
signal ct_in_29 : std_logic_vector(63 downto 0);
signal ct_in_30 : std_logic_vector(63 downto 0);
signal ct_in_31 : std_logic_vector(63 downto 0);
signal ct_in_32 : std_logic_vector(63 downto 0);
signal ct_in_33 : std_logic_vector(63 downto 0);
signal ct_in_34 : std_logic_vector(63 downto 0);
signal ct_in_35 : std_logic_vector(63 downto 0);
signal ct_in_36 : std_logic_vector(63 downto 0);
signal ct_in_37 : std_logic_vector(63 downto 0);
signal ct_in_38 : std_logic_vector(63 downto 0);
signal ct_in_39 : std_logic_vector(63 downto 0);
signal ct_in_40 : std_logic_vector(63 downto 0);
signal ct_in_41 : std_logic_vector(63 downto 0);
signal ct_in_42 : std_logic_vector(63 downto 0);
signal ct_in_43 : std_logic_vector(63 downto 0);
signal ct_out_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_out_1 : std_logic_vector(63 downto 0);
signal ct_out_2 : std_logic_vector(63 downto 0);
signal ct_out_3 : std_logic_vector(63 downto 0);
signal ct_out_4 : std_logic_vector(63 downto 0);
signal ct_out_5 : std_logic_vector(63 downto 0);
signal ct_out_6 : std_logic_vector(63 downto 0);
signal ct_out_7 : std_logic_vector(63 downto 0);
signal ct_out_8 : std_logic_vector(63 downto 0);
signal ct_out_9 : std_logic_vector(63 downto 0);
signal ct_out_10 : std_logic_vector(63 downto 0);
signal ct_out_11 : std_logic_vector(63 downto 0);
signal ct_out_12 : std_logic_vector(63 downto 0);
signal ct_out_13 : std_logic_vector(63 downto 0);
signal ct_out_14 : std_logic_vector(63 downto 0);
signal ct_out_15 : std_logic_vector(63 downto 0);
signal ct_out_16 : std_logic_vector(63 downto 0);
signal ct_out_17 : std_logic_vector(63 downto 0);
signal ct_out_18 : std_logic_vector(63 downto 0);
signal ct_out_19 : std_logic_vector(63 downto 0);
signal ct_out_20 : std_logic_vector(63 downto 0);
signal ct_out_21 : std_logic_vector(63 downto 0);
signal ct_out_22 : std_logic_vector(63 downto 0);
signal ct_out_23 : std_logic_vector(63 downto 0);
signal ct_out_24 : std_logic_vector(63 downto 0);
signal ct_out_25 : std_logic_vector(63 downto 0);
signal ct_out_26 : std_logic_vector(63 downto 0);
signal ct_out_27 : std_logic_vector(63 downto 0);
signal ct_out_28 : std_logic_vector(63 downto 0);
signal ct_out_29 : std_logic_vector(63 downto 0);
signal ct_out_30 : std_logic_vector(63 downto 0);
signal ct_out_31 : std_logic_vector(63 downto 0);
signal ct_out_32 : std_logic_vector(63 downto 0);
signal ct_out_33 : std_logic_vector(63 downto 0);
signal ct_out_34 : std_logic_vector(63 downto 0);
signal ct_out_35 : std_logic_vector(63 downto 0);
signal ct_out_36 : std_logic_vector(63 downto 0);
signal ct_out_37 : std_logic_vector(63 downto 0);
signal ct_out_38 : std_logic_vector(63 downto 0);
signal ct_out_39 : std_logic_vector(63 downto 0);
signal ct_out_40 : std_logic_vector(63 downto 0);
signal ct_out_41 : std_logic_vector(63 downto 0);
signal ct_out_42 : std_logic_vector(63 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (
key_s(0), key_s(1), key_s(2), key_s(3),
k_0, k_1, k_2, k_3, k_4, k_5, k_6, k_7, k_8, k_9, k_10,
k_11, k_12, k_13, k_14, k_15, k_16, k_17, k_18, k_19, k_20,
k_21, k_22, k_23, k_24, k_25, k_26, k_27, k_28, k_29, k_30,
k_31, k_32, k_33, k_34, k_35, k_36, k_37, k_38, k_39, k_40,
k_41, k_42, k_43);
-- Outer-round registers
REG_STAGE_0 : reg_64 port map (clk, rst, ct_in_0, ct_out_0);
REG_STAGE_1 : reg_64 port map (clk, rst, ct_in_1, ct_out_1);
REG_STAGE_2 : reg_64 port map (clk, rst, ct_in_2, ct_out_2);
REG_STAGE_3 : reg_64 port map (clk, rst, ct_in_3, ct_out_3);
REG_STAGE_4 : reg_64 port map (clk, rst, ct_in_4, ct_out_4);
REG_STAGE_5 : reg_64 port map (clk, rst, ct_in_5, ct_out_5);
REG_STAGE_6 : reg_64 port map (clk, rst, ct_in_6, ct_out_6);
REG_STAGE_7 : reg_64 port map (clk, rst, ct_in_7, ct_out_7);
REG_STAGE_8 : reg_64 port map (clk, rst, ct_in_8, ct_out_8);
REG_STAGE_9 : reg_64 port map (clk, rst, ct_in_9, ct_out_9);
REG_STAGE_10 : reg_64 port map (clk, rst, ct_in_10, ct_out_10);
REG_STAGE_11 : reg_64 port map (clk, rst, ct_in_11, ct_out_11);
REG_STAGE_12 : reg_64 port map (clk, rst, ct_in_12, ct_out_12);
REG_STAGE_13 : reg_64 port map (clk, rst, ct_in_13, ct_out_13);
REG_STAGE_14 : reg_64 port map (clk, rst, ct_in_14, ct_out_14);
REG_STAGE_15 : reg_64 port map (clk, rst, ct_in_15, ct_out_15);
REG_STAGE_16 : reg_64 port map (clk, rst, ct_in_16, ct_out_16);
REG_STAGE_17 : reg_64 port map (clk, rst, ct_in_17, ct_out_17);
REG_STAGE_18 : reg_64 port map (clk, rst, ct_in_18, ct_out_18);
REG_STAGE_19 : reg_64 port map (clk, rst, ct_in_19, ct_out_19);
REG_STAGE_20 : reg_64 port map (clk, rst, ct_in_20, ct_out_20);
REG_STAGE_21 : reg_64 port map (clk, rst, ct_in_21, ct_out_21);
REG_STAGE_22 : reg_64 port map (clk, rst, ct_in_22, ct_out_22);
REG_STAGE_23 : reg_64 port map (clk, rst, ct_in_23, ct_out_23);
REG_STAGE_24 : reg_64 port map (clk, rst, ct_in_24, ct_out_24);
REG_STAGE_25 : reg_64 port map (clk, rst, ct_in_25, ct_out_25);
REG_STAGE_26 : reg_64 port map (clk, rst, ct_in_26, ct_out_26);
REG_STAGE_27 : reg_64 port map (clk, rst, ct_in_27, ct_out_27);
REG_STAGE_28 : reg_64 port map (clk, rst, ct_in_28, ct_out_28);
REG_STAGE_29 : reg_64 port map (clk, rst, ct_in_29, ct_out_29);
REG_STAGE_30 : reg_64 port map (clk, rst, ct_in_30, ct_out_30);
REG_STAGE_31 : reg_64 port map (clk, rst, ct_in_31, ct_out_31);
REG_STAGE_32 : reg_64 port map (clk, rst, ct_in_32, ct_out_32);
REG_STAGE_33 : reg_64 port map (clk, rst, ct_in_33, ct_out_33);
REG_STAGE_34 : reg_64 port map (clk, rst, ct_in_34, ct_out_34);
REG_STAGE_35 : reg_64 port map (clk, rst, ct_in_35, ct_out_35);
REG_STAGE_36 : reg_64 port map (clk, rst, ct_in_36, ct_out_36);
REG_STAGE_37 : reg_64 port map (clk, rst, ct_in_37, ct_out_37);
REG_STAGE_38 : reg_64 port map (clk, rst, ct_in_38, ct_out_38);
REG_STAGE_39 : reg_64 port map (clk, rst, ct_in_39, ct_out_39);
REG_STAGE_40 : reg_64 port map (clk, rst, ct_in_40, ct_out_40);
REG_STAGE_41 : reg_64 port map (clk, rst, ct_in_41, ct_out_41);
REG_STAGE_42 : reg_64 port map (clk, rst, ct_in_42, ct_out_42);
-- round function combinatorial logic
ROUND_F_0 : round_f port map (clk, rst, enc, block_in, k_0, k_43, ct_in_0);
ROUND_F_1 : round_f port map (clk, rst, enc, ct_out_0, k_1, k_42, ct_in_1);
ROUND_F_2 : round_f port map (clk, rst, enc, ct_out_1, k_2, k_41, ct_in_2);
ROUND_F_3 : round_f port map (clk, rst, enc, ct_out_2, k_3, k_40, ct_in_3);
ROUND_F_4 : round_f port map (clk, rst, enc, ct_out_3, k_4, k_39, ct_in_4);
ROUND_F_5 : round_f port map (clk, rst, enc, ct_out_4, k_5, k_38, ct_in_5);
ROUND_F_6 : round_f port map (clk, rst, enc, ct_out_5, k_6, k_37, ct_in_6);
ROUND_F_7 : round_f port map (clk, rst, enc, ct_out_6, k_7, k_36, ct_in_7);
ROUND_F_8 : round_f port map (clk, rst, enc, ct_out_7, k_8, k_35, ct_in_8);
ROUND_F_9 : round_f port map (clk, rst, enc, ct_out_8, k_9, k_34, ct_in_9);
ROUND_F_10 : round_f port map (clk, rst, enc, ct_out_9, k_10, k_33, ct_in_10);
ROUND_F_11 : round_f port map (clk, rst, enc, ct_out_10, k_11, k_32, ct_in_11);
ROUND_F_12 : round_f port map (clk, rst, enc, ct_out_11, k_12, k_31, ct_in_12);
ROUND_F_13 : round_f port map (clk, rst, enc, ct_out_12, k_13, k_30, ct_in_13);
ROUND_F_14 : round_f port map (clk, rst, enc, ct_out_13, k_14, k_29, ct_in_14);
ROUND_F_15 : round_f port map (clk, rst, enc, ct_out_14, k_15, k_28, ct_in_15);
ROUND_F_16 : round_f port map (clk, rst, enc, ct_out_15, k_16, k_27, ct_in_16);
ROUND_F_17 : round_f port map (clk, rst, enc, ct_out_16, k_17, k_26, ct_in_17);
ROUND_F_18 : round_f port map (clk, rst, enc, ct_out_17, k_18, k_25, ct_in_18);
ROUND_F_19 : round_f port map (clk, rst, enc, ct_out_18, k_19, k_24, ct_in_19);
ROUND_F_20 : round_f port map (clk, rst, enc, ct_out_19, k_20, k_23, ct_in_20);
ROUND_F_21 : round_f port map (clk, rst, enc, ct_out_20, k_21, k_22, ct_in_21);
ROUND_F_22 : round_f port map (clk, rst, enc, ct_out_21, k_22, k_21, ct_in_22);
ROUND_F_23 : round_f port map (clk, rst, enc, ct_out_22, k_23, k_20, ct_in_23);
ROUND_F_24 : round_f port map (clk, rst, enc, ct_out_23, k_24, k_19, ct_in_24);
ROUND_F_25 : round_f port map (clk, rst, enc, ct_out_24, k_25, k_18, ct_in_25);
ROUND_F_26 : round_f port map (clk, rst, enc, ct_out_25, k_26, k_17, ct_in_26);
ROUND_F_27 : round_f port map (clk, rst, enc, ct_out_26, k_27, k_16, ct_in_27);
ROUND_F_28 : round_f port map (clk, rst, enc, ct_out_27, k_28, k_15, ct_in_28);
ROUND_F_29 : round_f port map (clk, rst, enc, ct_out_28, k_29, k_14, ct_in_29);
ROUND_F_30 : round_f port map (clk, rst, enc, ct_out_29, k_30, k_13, ct_in_30);
ROUND_F_31 : round_f port map (clk, rst, enc, ct_out_30, k_31, k_12, ct_in_31);
ROUND_F_32 : round_f port map (clk, rst, enc, ct_out_31, k_32, k_11, ct_in_32);
ROUND_F_33 : round_f port map (clk, rst, enc, ct_out_32, k_33, k_10, ct_in_33);
ROUND_F_34 : round_f port map (clk, rst, enc, ct_out_33, k_34, k_9, ct_in_34);
ROUND_F_35 : round_f port map (clk, rst, enc, ct_out_34, k_35, k_8, ct_in_35);
ROUND_F_36 : round_f port map (clk, rst, enc, ct_out_35, k_36, k_7, ct_in_36);
ROUND_F_37 : round_f port map (clk, rst, enc, ct_out_36, k_37, k_6, ct_in_37);
ROUND_F_38 : round_f port map (clk, rst, enc, ct_out_37, k_38, k_5, ct_in_38);
ROUND_F_39 : round_f port map (clk, rst, enc, ct_out_38, k_39, k_4, ct_in_39);
ROUND_F_40 : round_f port map (clk, rst, enc, ct_out_39, k_40, k_3, ct_in_40);
ROUND_F_41 : round_f port map (clk, rst, enc, ct_out_40, k_41, k_2, ct_in_41);
ROUND_F_42 : round_f port map (clk, rst, enc, ct_out_41, k_42, k_1, ct_in_42);
ROUND_F_43 : round_f port map (clk, rst, enc, ct_out_42, k_43, k_0, ct_in_43);
block_out <= ct_in_43;
-- SIMON Core
pr_smn : process(clk, rst, enc, key, key_s)
begin
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
end process;
end Behavioral;
|
gpl-2.0
|
479e79106d990678c7c01d9394d75c92
| 0.643899 | 2.409797 | false | false | false | false |
Derek-X-Wang/VGA-Text-Generator
|
VGA-Text-Generator.srcs/sources_1/new/commonPak.vhd
| 1 | 2,198 |
-- Original Source from FP-V-GA-Text: https://github.com/MadLittleMods/FP-V-GA-Text
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.math_real.all;
package commonPak is
constant ADDR_WIDTH : integer := 11;
constant DATA_WIDTH : integer := 8;
constant FONT_WIDTH : integer := 8;
constant FONT_HEIGHT : integer := 16;
------------------------------------------
type point_2d is
record
x : integer;
y : integer;
end record;
type type_textColorMap is array(natural range <>) of std_logic_vector(7 downto 0);
------------------------------------------
type type_drawElement is
record
pixelOn: boolean;
rgb: std_logic_vector(7 downto 0);
end record;
constant init_type_drawElement: type_drawElement := (pixelOn => false, rgb => (others => '0'));
type type_drawElementArray is array(natural range <>) of type_drawElement;
------------------------------------------
type type_inArbiterPort is
record
dataRequest: boolean;
addr: std_logic_vector(ADDR_WIDTH-1 downto 0);
writeRequest: boolean;
writeData: std_logic_vector(DATA_WIDTH-1 downto 0);
end record;
constant init_type_inArbiterPort: type_inArbiterPort := (dataRequest => false, addr => (others => '0'), writeRequest => false, writeData => (others => '0'));
type type_inArbiterPortArray is array(natural range <>) of type_inArbiterPort;
type type_outArbiterPort is
record
dataWaiting: boolean;
data: std_logic_vector(DATA_WIDTH-1 downto 0);
dataWritten: boolean;
end record;
constant init_type_outArbiterPort: type_outArbiterPort := (dataWaiting => false, data => (others => '0'), dataWritten => false);
type type_outArbiterPortArray is array(natural range <>) of type_outArbiterPort;
----------------------
function log2_float(val : positive) return natural;
end commonPak;
package body commonPak is
function log2_float(val : positive) return natural is
begin
return integer(ceil(log2(real(val))));
end function;
end commonPak;
|
mit
|
6a8c9a7d7f668777be837513384d7456
| 0.665605 | 3.562399 | false | false | false | false |
twasiluk/hdmilight
|
fpga/avr/opc_deco.vhd
| 2 | 29,554 |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: opc_deco - Behavioral
-- Create Date: 16:05:16 10/29/2009
-- Description: the opcode decoder of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.common.ALL;
entity opc_deco is
port ( I_CLK : in std_logic;
I_OPC : in std_logic_vector(31 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_T0 : in std_logic;
Q_ALU_OP : out std_logic_vector( 4 downto 0);
Q_AMOD : out std_logic_vector( 5 downto 0);
Q_BIT : out std_logic_vector( 3 downto 0);
Q_DDDDD : out std_logic_vector( 4 downto 0);
Q_IMM : out std_logic_vector(15 downto 0);
Q_JADR : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PC_OP : out std_logic_vector( 2 downto 0);
Q_PMS : out std_logic; -- program memory select
Q_RD_M : out std_logic;
Q_RRRRR : out std_logic_vector( 4 downto 0);
Q_RSEL : out std_logic_vector( 1 downto 0);
Q_WE_01 : out std_logic;
Q_WE_D : out std_logic_vector( 1 downto 0);
Q_WE_F : out std_logic;
Q_WE_M : out std_logic_vector( 1 downto 0);
Q_WE_XYZS : out std_logic);
end opc_deco;
architecture Behavioral of opc_deco is
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
--
-- set the most common settings as default.
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_AMOD <= AMOD_ABS;
Q_BIT <= I_OPC(10) & I_OPC(2 downto 0);
Q_DDDDD <= I_OPC(8 downto 4);
Q_IMM <= X"0000";
Q_JADR <= I_OPC(31 downto 16);
Q_OPC <= I_OPC(15 downto 0);
Q_PC <= I_PC;
Q_PC_OP <= PC_NEXT;
Q_PMS <= '0';
Q_RD_M <= '0';
Q_RRRRR <= I_OPC(9) & I_OPC(3 downto 0);
Q_RSEL <= RS_REG;
Q_WE_D <= "00";
Q_WE_01 <= '0';
Q_WE_F <= '0';
Q_WE_M <= "00";
Q_WE_XYZS <= '0';
case I_OPC(15 downto 10) is
when "000000" => -- 0000 00xx xxxx xxxx
case I_OPC(9 downto 8) is
when "00" =>
--
-- 0000 0000 0000 0000 - NOP
-- 0000 0000 001v vvvv - INTERRUPT
--
if (I_OPC(5)) = '1' then -- interrupt
Q_ALU_OP <= ALU_INTR;
Q_AMOD <= AMOD_SPdd;
Q_JADR <= "0000000000" & I_OPC(4 downto 0) & "0";
Q_PC_OP <= PC_LD_I;
Q_WE_F <= '1'; -- clear I-flag
Q_WE_M <= "11"; -- write return address
Q_WE_XYZS <= '1'; -- write new SP
end if;
when "01" =>
--
-- 0000 0001 dddd rrrr - MOVW
--
Q_DDDDD <= I_OPC(7 downto 4) & "0";
Q_RRRRR <= I_OPC(3 downto 0) & "0";
Q_ALU_OP <= ALU_MV_16;
Q_WE_D <= "11";
when "10" =>
--
-- 0000 0010 dddd rrrr - MULS
--
Q_DDDDD <= "1" & I_OPC(7 downto 4);
Q_RRRRR <= "1" & I_OPC(3 downto 0);
Q_ALU_OP <= ALU_MULT;
Q_IMM(7 downto 5) <= MULT_SS;
Q_WE_01 <= '1';
Q_WE_F <= '1';
when others =>
--
-- 0000 0011 0ddd 0rrr - _MULSU SU "010"
-- 0000 0011 0ddd 1rrr - FMUL UU "100"
-- 0000 0011 1ddd 0rrr - FMULS SS "111"
-- 0000 0011 1ddd 1rrr - FMULSU SU "110"
--
Q_DDDDD(4 downto 3) <= "10"; -- regs 16 to 23
Q_RRRRR(4 downto 3) <= "10"; -- regs 16 to 23
Q_ALU_OP <= ALU_MULT;
if I_OPC(7) = '0' then
if I_OPC(3) = '0' then
Q_IMM(7 downto 5) <= MULT_SU;
else
Q_IMM(7 downto 5) <= MULT_FUU;
end if;
else
if I_OPC(3) = '0' then
Q_IMM(7 downto 5) <= MULT_FSS;
else
Q_IMM(7 downto 5) <= MULT_FSU;
end if;
end if;
Q_WE_01 <= '1';
Q_WE_F <= '1';
end case;
when "000001" | "000010" =>
--
-- 0000 01rd dddd rrrr - CPC = SBC without Q_WE_D
-- 0000 10rd dddd rrrr - SBC
--
Q_ALU_OP <= ALU_SBC;
Q_WE_D <= '0' & I_OPC(11); -- write Rd if SBC.
Q_WE_F <= '1';
when "000011" => -- 0000 11xx xxxx xxxx
--
-- 0000 11rd dddd rrrr - ADD
--
Q_ALU_OP <= ALU_ADD;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "000100" => -- 0001 00xx xxxx xxxx
--
-- 0001 00rd dddd rrrr - CPSE
--
Q_ALU_OP <= ALU_SUB;
if (I_T0 = '0') then -- second cycle.
Q_PC_OP <= PC_SKIP_Z;
end if;
when "000101" | "000110" =>
--
-- 0001 01rd dddd rrrr - CP = SUB without Q_WE_D
-- 0000 10rd dddd rrrr - SUB
--
Q_ALU_OP <= ALU_SUB;
Q_WE_D <= '0' & I_OPC(11); -- write Rd if SUB.
Q_WE_F <= '1';
when "000111" => -- 0001 11xx xxxx xxxx
--
-- 0001 11rd dddd rrrr - ADC
--
Q_ALU_OP <= ALU_ADC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001000" => -- 0010 00xx xxxx xxxx
--
-- 0010 00rd dddd rrrr - AND
--
Q_ALU_OP <= ALU_AND;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001001" => -- 0010 01xx xxxx xxxx
--
-- 0010 01rd dddd rrrr - EOR
--
Q_ALU_OP <= ALU_EOR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001010" => -- 0010 10xx xxxx xxxx
--
-- 0010 10rd dddd rrrr - OR
--
Q_ALU_OP <= ALU_OR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "001011" => -- 0010 11xx xxxx xxxx
--
-- 0010 11rd dddd rrrr - MOV
--
Q_ALU_OP <= ALU_R_MV_Q;
Q_WE_D <= "01";
when "001100" | "001101" | "001110" | "001111"
| "010100" | "010101" | "010110" | "010111" =>
--
-- 0011 KKKK dddd KKKK - CPI
-- 0101 KKKK dddd KKKK - SUBI
--
Q_ALU_OP <= ALU_SUB;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= '0' & I_OPC(14);
Q_WE_F <= '1';
when "010000" | "010001" | "010010" | "010011" =>
--
-- 0100 KKKK dddd KKKK - SBCI
--
Q_ALU_OP <= ALU_SBC;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "011000" | "011001" | "011010" | "011011" =>
--
-- 0110 KKKK dddd KKKK - ORI
--
Q_ALU_OP <= ALU_OR;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "011100" | "011101" | "011110" | "011111" =>
--
-- 0111 KKKK dddd KKKK - ANDI
--
Q_ALU_OP <= ALU_AND;
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD(4) <= '1'; -- Rd = 16...31
Q_WE_D <= "01";
Q_WE_F <= '1';
when "100000" | "100001" | "100010" | "100011"
| "101000" | "101001" | "101010" | "101011" =>
--
-- LDD (Y + q) == LD (y) if q == 0
--
-- 10q0 qq0d dddd 1qqq LDD (Y + q)
-- 10q0 qq0d dddd 0qqq LDD (Z + q)
-- 10q0 qq1d dddd 1qqq SDD (Y + q)
-- 10q0 qq1d dddd 0qqq SDD (Z + q)
-- L/ Z/
-- S Y
--
Q_IMM(5) <= I_OPC(13);
Q_IMM(4 downto 3) <= I_OPC(11 downto 10);
Q_IMM(2 downto 0) <= I_OPC( 2 downto 0);
if (I_OPC(3) = '0') then Q_AMOD <= AMOD_Zq;
else Q_AMOD <= AMOD_Yq;
end if;
if (I_OPC(9) = '0') then -- LDD
Q_RSEL <= RS_DIN;
Q_RD_M <= I_T0;
Q_WE_D <= '0' & not I_T0;
else -- STD
Q_WE_M <= '0' & I_OPC(9);
end if;
when "100100" => -- 1001 00xx xxxx xxxx
Q_IMM <= I_OPC(31 downto 16); -- absolute address for LDS/STS
if (I_OPC(9) = '0') then -- LDD / POP
--
-- 1001 00-0d dddd 0000 - LDS
-- 1001 00-0d dddd 0001 - LD Rd, Z+
-- 1001 00-0d dddd 0010 - LD Rd, -Z
-- 1001 00-0d dddd 0100 - LPM Rd, (Z) (ii)
-- 1001 00-0d dddd 0101 - LPM Rd, (Z+) (iii)
-- 1001 00-0d dddd 0110 - ELPM Z --- not mega8
-- 1001 00-0d dddd 0111 - ELPM Z+ --- not mega8
-- 1001 00-0d dddd 1001 - LD Rd, Y+
-- 1001 00-0d dddd 1010 - LD Rd, -Y
-- 1001 00-0d dddd 1100 - LD Rd, X
-- 1001 00-0d dddd 1101 - LD Rd, X+
-- 1001 00-0d dddd 1110 - LD Rd, -X
-- 1001 00-0d dddd 1111 - POP Rd
--
Q_RSEL <= RS_DIN;
Q_RD_M <= I_T0;
Q_WE_D <= '0' & not I_T0;
Q_WE_XYZS <= not I_T0;
Q_PMS <= (not I_OPC(3)) and I_OPC(2) and (not I_OPC(1));
case I_OPC(3 downto 0) is
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
when "0001" => Q_AMOD <= AMOD_Zi;
when "0100" => Q_AMOD <= AMOD_Z; Q_WE_XYZS <= '0';
when "0101" => Q_AMOD <= AMOD_Zi;
when "1001" => Q_AMOD <= AMOD_Yi;
when "1010" => Q_AMOD <= AMOD_dY;
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_iSP;
when others => Q_WE_XYZS <= '0';
end case;
else -- STD / PUSH
--
-- 1001 00-1r rrrr 0000 - STS
-- 1001 00-1r rrrr 0001 - ST Z+. Rr
-- 1001 00-1r rrrr 0010 - ST -Z. Rr
-- 1001 00-1r rrrr 1000 - ST Y. Rr
-- 1001 00-1r rrrr 1001 - ST Y+. Rr
-- 1001 00-1r rrrr 1010 - ST -Y. Rr
-- 1001 00-1r rrrr 1100 - ST X. Rr
-- 1001 00-1r rrrr 1101 - ST X+. Rr
-- 1001 00-1r rrrr 1110 - ST -X. Rr
-- 1001 00-1r rrrr 1111 - PUSH Rr
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_WE_M <= "01";
Q_WE_XYZS <= '1';
case I_OPC(3 downto 0) is
when "0000" => Q_AMOD <= AMOD_ABS; Q_WE_XYZS <= '0';
when "0001" => Q_AMOD <= AMOD_Zi;
when "0010" => Q_AMOD <= AMOD_dZ;
when "1001" => Q_AMOD <= AMOD_Yi;
when "1010" => Q_AMOD <= AMOD_dY;
when "1100" => Q_AMOD <= AMOD_X; Q_WE_XYZS <= '0';
when "1101" => Q_AMOD <= AMOD_Xi;
when "1110" => Q_AMOD <= AMOD_dX;
when "1111" => Q_AMOD <= AMOD_SPd;
when others =>
end case;
end if;
when "100101" => -- 1001 01xx xxxx xxxx
if (I_OPC(9) = '0') then -- 1001 010
case I_OPC(3 downto 0) is
when "0000" =>
--
-- 1001 010d dddd 0000 - COM Rd
--
Q_ALU_OP <= ALU_COM;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0001" =>
--
-- 1001 010d dddd 0001 - NEG Rd
--
Q_ALU_OP <= ALU_NEG;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0010" =>
--
-- 1001 010d dddd 0010 - SWAP Rd
--
Q_ALU_OP <= ALU_SWAP;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0011" =>
--
-- 1001 010d dddd 0011 - INC Rd
--
Q_ALU_OP <= ALU_INC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0101" =>
--
-- 1001 010d dddd 0101 - ASR Rd
--
Q_ALU_OP <= ALU_ASR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0110" =>
--
-- 1001 010d dddd 0110 - LSR Rd
--
Q_ALU_OP <= ALU_LSR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "0111" =>
--
-- 1001 010d dddd 0111 - ROR Rd
--
Q_ALU_OP <= ALU_ROR;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "1000" => -- 1001 010x xxxx 1000
if I_OPC(8) = '0' then -- 1001 0100 xxxx 1000
--
-- 1001 0100 0sss 1000 - BSET
-- 1001 0100 1sss 1000 - BCLR
--
Q_BIT(3 downto 0) <= I_OPC(7 downto 4);
Q_ALU_OP <= ALU_SREG;
Q_WE_F <= '1';
else -- 1001 0101 xxxx 1000
--
-- 1001 0101 0000 1000 - RET
-- 1001 0101 0001 1000 - RETI
-- 1001 0101 1000 1000 - SLEEP
-- 1001 0101 1001 1000 - BREAK
-- 1001 0101 1100 1000 - LPM [ R0,(Z) ]
-- 1001 0101 1101 1000 - ELPM not mega8
-- 1001 0101 1110 1000 - SPM
-- 1001 0101 1111 1000 - SPM #2
-- 1001 0101 1010 1000 - WDR
--
case I_OPC(7 downto 4) is
when "0000" => -- RET
Q_AMOD <= AMOD_iiSP;
Q_RD_M <= I_T0;
Q_WE_XYZS <= not I_T0;
if (I_T0 = '0') then
Q_PC_OP <= PC_LD_S;
end if;
when "0001" => -- RETI
Q_ALU_OP <= ALU_INTR;
Q_IMM(6) <= '1';
Q_AMOD <= AMOD_iiSP;
Q_RD_M <= I_T0;
Q_WE_F <= not I_T0; -- I flag
Q_WE_XYZS <= not I_T0;
if (I_T0 = '0') then
Q_PC_OP <= PC_LD_S;
end if;
when "1100" => -- (i) LPM R0, (Z)
Q_DDDDD <= "00000";
Q_AMOD <= AMOD_Z;
Q_PMS <= '1';
Q_WE_D <= '0' & not I_T0;
when "1110" => -- SPM
Q_ALU_OP <= ALU_D_MV_Q;
Q_DDDDD <= "00000";
Q_AMOD <= AMOD_Z;
Q_PMS <= '1';
Q_WE_M <= "01";
when "1111" => -- SPM #2
-- page write: not supported
when others =>
end case;
end if;
when "1001" => -- 1001 010x xxxx 1001
--
-- 1001 0100 0000 1001 IJMP
-- 1001 0100 0001 1001 EIJMP -- not mega8
-- 1001 0101 0000 1001 ICALL
-- 1001 0101 0001 1001 EICALL -- not mega8
--
Q_PC_OP <= PC_LD_Z;
if (I_OPC(8) = '1') then -- ICALL
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_SPdd;
Q_WE_M <= "11";
Q_WE_XYZS <= '1';
end if;
when "1010" => -- 1001 010x xxxx 1010
--
-- 1001 010d dddd 1010 - DEC Rd
--
Q_ALU_OP <= ALU_DEC;
Q_WE_D <= "01";
Q_WE_F <= '1';
when "1011" => -- 1001 010x xxxx 1011
--
-- 1001 0100 KKKK 1011 - DES -- not mega8
--
when "1100" | "1101" =>
--
-- 1001 010k kkkk 110k - JMP (k = 0 for 16 bit)
-- kkkk kkkk kkkk kkkk
--
Q_PC_OP <= PC_LD_I;
when "1110" | "1111" => -- 1001 010x xxxx 111x
--
-- 1001 010k kkkk 111k - CALL (k = 0)
-- kkkk kkkk kkkk kkkk
--
Q_ALU_OP <= ALU_PC_2;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
when others =>
end case;
else -- 1001 011
--
-- 1001 0110 KKdd KKKK - ADIW
-- 1001 0111 KKdd KKKK - SBIW
--
if (I_OPC(8) = '0') then Q_ALU_OP <= ALU_ADIW;
else Q_ALU_OP <= ALU_SBIW;
end if;
Q_IMM(5 downto 4) <= I_OPC(7 downto 6);
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_RSEL <= RS_IMM;
Q_DDDDD <= "11" & I_OPC(5 downto 4) & "0";
Q_WE_D <= "11";
Q_WE_F <= '1';
end if; -- I_OPC(9) = 0/1
when "100110" => -- 1001 10xx xxxx xxxx
--
-- 1001 1000 AAAA Abbb - CBI
-- 1001 1001 AAAA Abbb - SBIC
-- 1001 1010 AAAA Abbb - SBI
-- 1001 1011 AAAA Abbb - SBIS
--
Q_ALU_OP <= ALU_BIT_CS;
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(9); -- set/clear
-- IMM = AAAAAA + 0x20
--
Q_IMM(4 downto 0) <= I_OPC(7 downto 3);
Q_IMM(6 downto 5) <= "01";
Q_RD_M <= I_T0;
if ((I_OPC(8) = '0') ) then -- CBI or SBI
Q_WE_M(0) <= '1';
else -- SBIC or SBIS
if (I_T0 = '0') then -- second cycle.
Q_PC_OP <= PC_SKIP_T;
end if;
end if;
when "100111" => -- 1001 11xx xxxx xxxx
--
-- 1001 11rd dddd rrrr - MUL
--
Q_ALU_OP <= ALU_MULT;
Q_IMM(7 downto 5) <= "000"; -- -MUL UU;
Q_WE_01 <= '1';
Q_WE_F <= '1';
when "101100" | "101101" => -- 1011 0xxx xxxx xxxx
--
-- 1011 0AAd dddd AAAA - IN
--
Q_RSEL <= RS_DIN;
Q_AMOD <= AMOD_ABS;
-- IMM = AAAAAA
-- + 010000 (0x20)
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_IMM(4) <= I_OPC(9);
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
Q_RD_M <= '1';
Q_WE_D <= "01";
when "101110" | "101111" => -- 1011 1xxx xxxx xxxx
--
-- 1011 1AAr rrrr AAAA - OUT
--
Q_ALU_OP <= ALU_D_MV_Q;
Q_AMOD <= AMOD_ABS;
-- IMM = AAAAAA
-- + 010000 (0x20)
--
Q_IMM(3 downto 0) <= I_OPC(3 downto 0);
Q_IMM(4) <= I_OPC(9);
Q_IMM(6 downto 5) <= "01" + ('0' & I_OPC(10 downto 10));
Q_WE_M <= "01";
when "110000" | "110001" | "110010" | "110011" =>
--
-- 1100 kkkk kkkk kkkk - RJMP
--
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
& I_OPC(11 downto 0)) + X"0001";
Q_PC_OP <= PC_LD_I;
when "110100" | "110101" | "110110" | "110111" =>
--
-- 1101 kkkk kkkk kkkk - RCALL
--
Q_JADR <= I_PC + (I_OPC(11) & I_OPC(11) & I_OPC(11) & I_OPC(11)
& I_OPC(11 downto 0)) + X"0001";
Q_ALU_OP <= ALU_PC_1;
Q_AMOD <= AMOD_SPdd;
Q_PC_OP <= PC_LD_I;
Q_WE_M <= "11"; -- both PC bytes
Q_WE_XYZS <= '1';
when "111000" | "111001" | "111010" | "111011" => -- LDI
--
-- 1110 KKKK dddd KKKK - LDI Rd, K
--
Q_ALU_OP <= ALU_R_MV_Q;
Q_RSEL <= RS_IMM;
Q_DDDDD <= '1' & I_OPC(7 downto 4); -- 16..31
Q_IMM(7 downto 0) <= I_OPC(11 downto 8) & I_OPC(3 downto 0);
Q_WE_D <= "01";
when "111100" | "111101" => -- 1111 0xxx xxxx xxxx
--
-- 1111 00kk kkkk kbbb - BRBS
-- 1111 01kk kkkk kbbb - BRBC
-- v
-- bbb: status register bit
-- v: value (set/cleared) of status register bit
--
Q_JADR <= I_PC + (I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
& I_OPC(9) & I_OPC(9) & I_OPC(9) & I_OPC(9)
& I_OPC(9) & I_OPC(9 downto 3)) + X"0001";
Q_PC_OP <= PC_BCC;
when "111110" => -- 1111 10xx xxxx xxxx
--
-- 1111 100d dddd 0bbb - BLD
-- 1111 101d dddd 0bbb - BST
--
if I_OPC(9) = '0' then -- BLD: T flag to register
Q_ALU_OP <= ALU_BLD;
Q_WE_D <= "01";
else -- BST: register to T flag
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(10);
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
Q_ALU_OP <= ALU_BIT_CS;
Q_WE_F <= '1';
end if;
when "111111" => -- 1111 11xx xxxx xxxx
--
-- 1111 110r rrrr 0bbb - SBRC
-- 1111 111r rrrr 0bbb - SBRS
--
-- like SBIC, but and general purpose regs instead of I/O regs.
--
Q_ALU_OP <= ALU_BIT_CS;
Q_AMOD <= AMOD_ABS;
Q_BIT(3) <= I_OPC(9); -- set/clear bit
Q_IMM(4 downto 0) <= I_OPC(8 downto 4);
if (I_T0 = '0') then
Q_PC_OP <= PC_SKIP_T;
end if;
when others =>
end case;
end if;
end process;
end Behavioral;
|
gpl-2.0
|
82ea8dcea415a891aba00874adb9b9ae
| 0.299046 | 4.334702 | false | false | false | false |
Derek-X-Wang/VGA-Text-Generator
|
VGA-Text-Generator.srcs/sources_1/new/Pixel_On_Text2.vhd
| 1 | 3,266 |
-- Pixel_On_Text2 determines if the current pixel is on text and make it easiler to call from verilog
-- param:
-- display text
-- input:
-- VGA clock(the clk you used to update VGA)
-- top left corner of the text area -- positionX, positionY
-- current X and Y position
-- output:
-- a bit that represent whether is the pixel in text
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- note this line.The package is compiled to this directory by default.
-- so don't forget to include this directory.
library work;
-- this line also is must.This includes the particular package into your program.
use work.commonPak.all;
entity Pixel_On_Text2 is
generic(
displayText: string := (others => NUL)
);
port (
clk: in std_logic;
-- top left corner of the text
positionX: in integer;
positionY: in integer;
-- current pixel postion
horzCoord: in integer;
vertCoord: in integer;
pixel: out std_logic := '0'
);
end Pixel_On_Text2;
architecture Behavioral of Pixel_On_Text2 is
signal fontAddress: integer;
-- A row of bit in a charactor, we check if our current (x,y) is 1 in char row
signal charBitInRow: std_logic_vector(FONT_WIDTH-1 downto 0) := (others => '0');
-- char in ASCII code
signal charCode:integer := 0;
-- the position(column) of a charactor in the given text
signal charPosition:integer := 0;
-- the bit position(column) in a charactor
signal bitPosition:integer := 0;
begin
-- (horzCoord - position.x): x positionin the top left of the whole text
charPosition <= (horzCoord - positionX)/FONT_WIDTH + 1;
bitPosition <= (horzCoord - positionX) mod FONT_WIDTH;
charCode <= character'pos(displayText(charPosition));
-- charCode*16: first row of the char
fontAddress <= charCode*16+(vertCoord - positionY);
FontRom: entity work.Font_Rom
port map(
clk => clk,
addr => fontAddress,
fontRow => charBitInRow
);
pixelOn: process(clk)
variable inXRange: boolean := false;
variable inYRange: boolean := false;
begin
if rising_edge(clk) then
-- reset
inXRange := false;
inYRange := false;
pixel <= '0';
-- If current pixel is in the horizontal range of text
if horzCoord >= positionX and horzCoord < positionX + (FONT_WIDTH * displayText'length) then
inXRange := true;
end if;
-- If current pixel is in the vertical range of text
if vertCoord >= positionY and vertCoord < positionY + FONT_HEIGHT then
inYRange := true;
end if;
-- need to check if the pixel is on for text
if inXRange and inYRange then
-- FONT_WIDTH-bitPosition: we are reverting the charactor
if charBitInRow(FONT_WIDTH-bitPosition) = '1' then
pixel <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
1bc99330c904e87a6c3a1ee2e6717bba
| 0.649724 | 3.874259 | false | false | false | false |
samvartaka/simon_vhdl
|
OUTER_ROUND_PIPELINING/reg_64.vhd
| 2 | 832 |
-- SIMON 64/128
-- outer-pipelining word (64-bit) registry
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- data_in: registry input
-- data_out: registry output
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity reg_64 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(63 downto 0);
data_out : out std_logic_vector(63 downto 0)
);
end reg_64;
architecture Behavioral of reg_64 is
signal reg_64_s : std_logic_vector(63 downto 0);
begin
pr_reg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_64_s <= (others => '0');
else
reg_64_s <= data_in;
end if;
end if;
end process;
data_out <= reg_64_s;
end Behavioral;
|
gpl-2.0
|
d0b1e6c2dc54d91c7c164ab051c337fa
| 0.614183 | 2.878893 | false | false | false | false |
samvartaka/simon_vhdl
|
LOOP_UNROLL/tb_simon.vhd
| 1 | 2,404 |
-- SIMON 64/128
-- Encryption & decryption test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_simon IS
END tb_simon;
ARCHITECTURE behavior OF tb_simon IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT simon
port(clk : in std_logic;
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal enc : std_logic := '0';
signal key : std_logic_vector(127 downto 0) := (others => '0');
signal block_in : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal block_out : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: simon PORT MAP (
clk => clk,
enc => enc,
key => key,
block_in => block_in,
block_out => block_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- ==============================================
-- T_0: Test encryption and subsequent decryption
-- ==============================================
-- Test encryption
enc <= '0';
-- SIMON 64/128 test vectors
block_in <= X"656b696c20646e75";
key <= X"1b1a1918131211100b0a090803020100";
-- Wait for initialization
wait for clk_period;
-- Do rounds
wait for clk_period;
assert block_out = X"44c8fc20b9dfa07a"
report "ENCRYPT ERROR (e_0)" severity FAILURE;
-- Test decryption
enc <= '1';
-- Use output of encryption as input for decryption
block_in <= block_out;
-- Wait for initialization
wait for clk_period;
-- Run
wait for clk_period;
assert block_out = X"656b696c20646e75"
report "DECRYPT ERROR (d_0)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
78b8da4bca4a57294ea7f1c144a43abe
| 0.594842 | 3.424501 | false | true | false | false |
sahandKashani/HDL-IP-cores
|
fwft_fifo/tb/tb_fwft_fifo.vhd
| 1 | 4,573 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_fwft_fifo is
end tb_fwft_fifo;
architecture test of tb_fwft_fifo is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal sim_finished : boolean := false;
-- fwft_fifo ---------------------------------------------------------------
constant DATA_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 8;
signal clr : std_logic := '0';
signal write_en : std_logic := '0';
signal data_in : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal read_en : std_logic := '0';
signal data_out : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
signal empty : std_logic := '0';
signal full : std_logic := '0';
signal usedw : std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH + 1)))) - 1 downto 0) := (others => '0');
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
fwft_fifo_inst : entity work.fwft_fifo
generic map(DATA_WIDTH => DATA_WIDTH,
FIFO_DEPTH => FIFO_DEPTH)
port map(
clk => clk,
reset => reset,
clr => clr,
write_en => write_en,
data_in => data_in,
read_en => read_en,
data_out => data_out,
empty => empty,
full => full,
usedw => usedw);
sim : process
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure sync_clr is
begin
wait until falling_edge(clk);
clr <= '1';
wait until falling_edge(clk);
clr <= '0';
end procedure sync_clr;
procedure push(constant val : in natural) is
begin
wait until falling_edge(clk);
write_en <= '1';
data_in <= std_logic_vector(to_unsigned(val, data_in'length));
wait until falling_edge(clk);
write_en <= '0';
data_in <= (others => '0');
end procedure push;
procedure pop is
begin
wait until falling_edge(clk);
read_en <= '1';
wait until falling_edge(clk);
read_en <= '0';
end procedure pop;
procedure push_pop(constant val : in natural) is
begin
wait until falling_edge(clk);
write_en <= '1';
data_in <= std_logic_vector(to_unsigned(val, data_in'length));
read_en <= '1';
wait until falling_edge(clk);
write_en <= '0';
data_in <= (others => '0');
read_en <= '0';
end procedure push_pop;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
begin
-- async reset
async_reset;
wait_clock_cycles(10);
-- push
for i in 1 to FIFO_DEPTH loop
push(i);
end loop;
wait_clock_cycles(10);
-- pop
for i in 1 to FIFO_DEPTH loop
pop;
end loop;
wait_clock_cycles(10);
-- pushpop
push(FIFO_DEPTH + 1);
for i in 2 to FIFO_DEPTH loop
push_pop(FIFO_DEPTH + i);
end loop;
pop;
wait_clock_cycles(10);
-- sync clr
sync_clr;
wait_clock_cycles(10);
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
unlicense
|
0ce4918ea160ce33393f56420784f15a
| 0.451564 | 4.285848 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
std_fifo/hdl/std_fifo.vhd
| 1 | 3,774 |
-- Slightly modified from original source from [email protected]:
-- http://www.deathbylogic.com/2013/07/vhdl-standard-fifo/
--
-- Added usedw output to know how many words are currently stored in the fifo.
-- Added async reset port (useful for some designs)
-- Reset internal memory as well when receiving async reset or sync clr.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity std_fifo is
generic(
DATA_WIDTH : positive := 8;
FIFO_DEPTH : positive := 256
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
write_en : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
read_en : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH + 1)))) - 1 downto 0)
);
end std_fifo;
architecture behavioral of std_fifo is
begin
-- memory pointer process
fifo_proc : process(clk, reset)
type fifo_memory is array (0 to FIFO_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
variable memory : fifo_memory;
variable head : natural range 0 to FIFO_DEPTH - 1;
variable tail : natural range 0 to FIFO_DEPTH - 1;
variable fill_level : natural range 0 to FIFO_DEPTH;
variable looped : boolean;
begin
if reset = '1' then
head := 0;
tail := 0;
fill_level := 0;
looped := false;
full <= '0';
empty <= '1';
elsif rising_edge(clk) then
if clr = '1' then
head := 0;
tail := 0;
fill_level := 0;
looped := false;
full <= '0';
empty <= '1';
else
if (read_en = '1') then
if ((looped = true) or (head /= tail)) then
-- update data output
data_out <= memory(tail);
fill_level := fill_level - 1;
-- update tail pointer as needed
if (tail = FIFO_DEPTH - 1) then
tail := 0;
looped := false;
else
tail := tail + 1;
end if;
end if;
end if;
if (write_en = '1') then
if ((looped = false) or (head /= tail)) then
-- write data to memory
memory(head) := data_in;
fill_level := fill_level + 1;
-- increment head pointer as needed
if (head = FIFO_DEPTH - 1) then
head := 0;
looped := true;
else
head := head + 1;
end if;
end if;
end if;
usedw <= std_logic_vector(to_unsigned(fill_level, usedw'length));
-- update empty and full flags
if (head = tail) then
if looped then
full <= '1';
else
empty <= '1';
end if;
else
empty <= '0';
full <= '0';
end if;
end if;
end if;
end process;
end behavioral;
|
unlicense
|
89b5a7644d5a982b04bc906e907c6bf3
| 0.431638 | 4.585662 | false | false | false | false |
samvartaka/simon_vhdl
|
OUTER_ROUND_PIPELINING/simon.vhd
| 1 | 16,660 |
-- SIMON 64/128
-- Simon core component
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end component;
component round_f
port(enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END component;
component reg_64 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(63 downto 0);
data_out : out std_logic_vector(63 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- intermediate key (in words)
signal k_0 : std_logic_vector(31 downto 0);
signal k_1 : std_logic_vector(31 downto 0);
signal k_2 : std_logic_vector(31 downto 0);
signal k_3 : std_logic_vector(31 downto 0);
signal k_4 : std_logic_vector(31 downto 0);
signal k_5 : std_logic_vector(31 downto 0);
signal k_6 : std_logic_vector(31 downto 0);
signal k_7 : std_logic_vector(31 downto 0);
signal k_8 : std_logic_vector(31 downto 0);
signal k_9 : std_logic_vector(31 downto 0);
signal k_10 : std_logic_vector(31 downto 0);
signal k_11 : std_logic_vector(31 downto 0);
signal k_12 : std_logic_vector(31 downto 0);
signal k_13 : std_logic_vector(31 downto 0);
signal k_14 : std_logic_vector(31 downto 0);
signal k_15 : std_logic_vector(31 downto 0);
signal k_16 : std_logic_vector(31 downto 0);
signal k_17 : std_logic_vector(31 downto 0);
signal k_18 : std_logic_vector(31 downto 0);
signal k_19 : std_logic_vector(31 downto 0);
signal k_20 : std_logic_vector(31 downto 0);
signal k_21 : std_logic_vector(31 downto 0);
signal k_22 : std_logic_vector(31 downto 0);
signal k_23 : std_logic_vector(31 downto 0);
signal k_24 : std_logic_vector(31 downto 0);
signal k_25 : std_logic_vector(31 downto 0);
signal k_26 : std_logic_vector(31 downto 0);
signal k_27 : std_logic_vector(31 downto 0);
signal k_28 : std_logic_vector(31 downto 0);
signal k_29 : std_logic_vector(31 downto 0);
signal k_30 : std_logic_vector(31 downto 0);
signal k_31 : std_logic_vector(31 downto 0);
signal k_32 : std_logic_vector(31 downto 0);
signal k_33 : std_logic_vector(31 downto 0);
signal k_34 : std_logic_vector(31 downto 0);
signal k_35 : std_logic_vector(31 downto 0);
signal k_36 : std_logic_vector(31 downto 0);
signal k_37 : std_logic_vector(31 downto 0);
signal k_38 : std_logic_vector(31 downto 0);
signal k_39 : std_logic_vector(31 downto 0);
signal k_40 : std_logic_vector(31 downto 0);
signal k_41 : std_logic_vector(31 downto 0);
signal k_42 : std_logic_vector(31 downto 0);
signal k_43 : std_logic_vector(31 downto 0);
signal ct_in_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_in_1 : std_logic_vector(63 downto 0);
signal ct_in_2 : std_logic_vector(63 downto 0);
signal ct_in_3 : std_logic_vector(63 downto 0);
signal ct_in_4 : std_logic_vector(63 downto 0);
signal ct_in_5 : std_logic_vector(63 downto 0);
signal ct_in_6 : std_logic_vector(63 downto 0);
signal ct_in_7 : std_logic_vector(63 downto 0);
signal ct_in_8 : std_logic_vector(63 downto 0);
signal ct_in_9 : std_logic_vector(63 downto 0);
signal ct_in_10 : std_logic_vector(63 downto 0);
signal ct_in_11 : std_logic_vector(63 downto 0);
signal ct_in_12 : std_logic_vector(63 downto 0);
signal ct_in_13 : std_logic_vector(63 downto 0);
signal ct_in_14 : std_logic_vector(63 downto 0);
signal ct_in_15 : std_logic_vector(63 downto 0);
signal ct_in_16 : std_logic_vector(63 downto 0);
signal ct_in_17 : std_logic_vector(63 downto 0);
signal ct_in_18 : std_logic_vector(63 downto 0);
signal ct_in_19 : std_logic_vector(63 downto 0);
signal ct_in_20 : std_logic_vector(63 downto 0);
signal ct_in_21 : std_logic_vector(63 downto 0);
signal ct_in_22 : std_logic_vector(63 downto 0);
signal ct_in_23 : std_logic_vector(63 downto 0);
signal ct_in_24 : std_logic_vector(63 downto 0);
signal ct_in_25 : std_logic_vector(63 downto 0);
signal ct_in_26 : std_logic_vector(63 downto 0);
signal ct_in_27 : std_logic_vector(63 downto 0);
signal ct_in_28 : std_logic_vector(63 downto 0);
signal ct_in_29 : std_logic_vector(63 downto 0);
signal ct_in_30 : std_logic_vector(63 downto 0);
signal ct_in_31 : std_logic_vector(63 downto 0);
signal ct_in_32 : std_logic_vector(63 downto 0);
signal ct_in_33 : std_logic_vector(63 downto 0);
signal ct_in_34 : std_logic_vector(63 downto 0);
signal ct_in_35 : std_logic_vector(63 downto 0);
signal ct_in_36 : std_logic_vector(63 downto 0);
signal ct_in_37 : std_logic_vector(63 downto 0);
signal ct_in_38 : std_logic_vector(63 downto 0);
signal ct_in_39 : std_logic_vector(63 downto 0);
signal ct_in_40 : std_logic_vector(63 downto 0);
signal ct_in_41 : std_logic_vector(63 downto 0);
signal ct_in_42 : std_logic_vector(63 downto 0);
signal ct_in_43 : std_logic_vector(63 downto 0);
signal ct_out_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_out_1 : std_logic_vector(63 downto 0);
signal ct_out_2 : std_logic_vector(63 downto 0);
signal ct_out_3 : std_logic_vector(63 downto 0);
signal ct_out_4 : std_logic_vector(63 downto 0);
signal ct_out_5 : std_logic_vector(63 downto 0);
signal ct_out_6 : std_logic_vector(63 downto 0);
signal ct_out_7 : std_logic_vector(63 downto 0);
signal ct_out_8 : std_logic_vector(63 downto 0);
signal ct_out_9 : std_logic_vector(63 downto 0);
signal ct_out_10 : std_logic_vector(63 downto 0);
signal ct_out_11 : std_logic_vector(63 downto 0);
signal ct_out_12 : std_logic_vector(63 downto 0);
signal ct_out_13 : std_logic_vector(63 downto 0);
signal ct_out_14 : std_logic_vector(63 downto 0);
signal ct_out_15 : std_logic_vector(63 downto 0);
signal ct_out_16 : std_logic_vector(63 downto 0);
signal ct_out_17 : std_logic_vector(63 downto 0);
signal ct_out_18 : std_logic_vector(63 downto 0);
signal ct_out_19 : std_logic_vector(63 downto 0);
signal ct_out_20 : std_logic_vector(63 downto 0);
signal ct_out_21 : std_logic_vector(63 downto 0);
signal ct_out_22 : std_logic_vector(63 downto 0);
signal ct_out_23 : std_logic_vector(63 downto 0);
signal ct_out_24 : std_logic_vector(63 downto 0);
signal ct_out_25 : std_logic_vector(63 downto 0);
signal ct_out_26 : std_logic_vector(63 downto 0);
signal ct_out_27 : std_logic_vector(63 downto 0);
signal ct_out_28 : std_logic_vector(63 downto 0);
signal ct_out_29 : std_logic_vector(63 downto 0);
signal ct_out_30 : std_logic_vector(63 downto 0);
signal ct_out_31 : std_logic_vector(63 downto 0);
signal ct_out_32 : std_logic_vector(63 downto 0);
signal ct_out_33 : std_logic_vector(63 downto 0);
signal ct_out_34 : std_logic_vector(63 downto 0);
signal ct_out_35 : std_logic_vector(63 downto 0);
signal ct_out_36 : std_logic_vector(63 downto 0);
signal ct_out_37 : std_logic_vector(63 downto 0);
signal ct_out_38 : std_logic_vector(63 downto 0);
signal ct_out_39 : std_logic_vector(63 downto 0);
signal ct_out_40 : std_logic_vector(63 downto 0);
signal ct_out_41 : std_logic_vector(63 downto 0);
signal ct_out_42 : std_logic_vector(63 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (
key_s(0), key_s(1), key_s(2), key_s(3),
k_0, k_1, k_2, k_3, k_4, k_5, k_6, k_7, k_8, k_9, k_10,
k_11, k_12, k_13, k_14, k_15, k_16, k_17, k_18, k_19, k_20,
k_21, k_22, k_23, k_24, k_25, k_26, k_27, k_28, k_29, k_30,
k_31, k_32, k_33, k_34, k_35, k_36, k_37, k_38, k_39, k_40,
k_41, k_42, k_43);
-- Outer-round registers
REG_STAGE_0 : reg_64 port map (clk, rst, ct_in_0, ct_out_0);
REG_STAGE_1 : reg_64 port map (clk, rst, ct_in_1, ct_out_1);
REG_STAGE_2 : reg_64 port map (clk, rst, ct_in_2, ct_out_2);
REG_STAGE_3 : reg_64 port map (clk, rst, ct_in_3, ct_out_3);
REG_STAGE_4 : reg_64 port map (clk, rst, ct_in_4, ct_out_4);
REG_STAGE_5 : reg_64 port map (clk, rst, ct_in_5, ct_out_5);
REG_STAGE_6 : reg_64 port map (clk, rst, ct_in_6, ct_out_6);
REG_STAGE_7 : reg_64 port map (clk, rst, ct_in_7, ct_out_7);
REG_STAGE_8 : reg_64 port map (clk, rst, ct_in_8, ct_out_8);
REG_STAGE_9 : reg_64 port map (clk, rst, ct_in_9, ct_out_9);
REG_STAGE_10 : reg_64 port map (clk, rst, ct_in_10, ct_out_10);
REG_STAGE_11 : reg_64 port map (clk, rst, ct_in_11, ct_out_11);
REG_STAGE_12 : reg_64 port map (clk, rst, ct_in_12, ct_out_12);
REG_STAGE_13 : reg_64 port map (clk, rst, ct_in_13, ct_out_13);
REG_STAGE_14 : reg_64 port map (clk, rst, ct_in_14, ct_out_14);
REG_STAGE_15 : reg_64 port map (clk, rst, ct_in_15, ct_out_15);
REG_STAGE_16 : reg_64 port map (clk, rst, ct_in_16, ct_out_16);
REG_STAGE_17 : reg_64 port map (clk, rst, ct_in_17, ct_out_17);
REG_STAGE_18 : reg_64 port map (clk, rst, ct_in_18, ct_out_18);
REG_STAGE_19 : reg_64 port map (clk, rst, ct_in_19, ct_out_19);
REG_STAGE_20 : reg_64 port map (clk, rst, ct_in_20, ct_out_20);
REG_STAGE_21 : reg_64 port map (clk, rst, ct_in_21, ct_out_21);
REG_STAGE_22 : reg_64 port map (clk, rst, ct_in_22, ct_out_22);
REG_STAGE_23 : reg_64 port map (clk, rst, ct_in_23, ct_out_23);
REG_STAGE_24 : reg_64 port map (clk, rst, ct_in_24, ct_out_24);
REG_STAGE_25 : reg_64 port map (clk, rst, ct_in_25, ct_out_25);
REG_STAGE_26 : reg_64 port map (clk, rst, ct_in_26, ct_out_26);
REG_STAGE_27 : reg_64 port map (clk, rst, ct_in_27, ct_out_27);
REG_STAGE_28 : reg_64 port map (clk, rst, ct_in_28, ct_out_28);
REG_STAGE_29 : reg_64 port map (clk, rst, ct_in_29, ct_out_29);
REG_STAGE_30 : reg_64 port map (clk, rst, ct_in_30, ct_out_30);
REG_STAGE_31 : reg_64 port map (clk, rst, ct_in_31, ct_out_31);
REG_STAGE_32 : reg_64 port map (clk, rst, ct_in_32, ct_out_32);
REG_STAGE_33 : reg_64 port map (clk, rst, ct_in_33, ct_out_33);
REG_STAGE_34 : reg_64 port map (clk, rst, ct_in_34, ct_out_34);
REG_STAGE_35 : reg_64 port map (clk, rst, ct_in_35, ct_out_35);
REG_STAGE_36 : reg_64 port map (clk, rst, ct_in_36, ct_out_36);
REG_STAGE_37 : reg_64 port map (clk, rst, ct_in_37, ct_out_37);
REG_STAGE_38 : reg_64 port map (clk, rst, ct_in_38, ct_out_38);
REG_STAGE_39 : reg_64 port map (clk, rst, ct_in_39, ct_out_39);
REG_STAGE_40 : reg_64 port map (clk, rst, ct_in_40, ct_out_40);
REG_STAGE_41 : reg_64 port map (clk, rst, ct_in_41, ct_out_41);
REG_STAGE_42 : reg_64 port map (clk, rst, ct_in_42, ct_out_42);
-- round function combinatorial logic
ROUND_F_0 : round_f port map (enc, block_in, k_0, k_43, ct_in_0);
ROUND_F_1 : round_f port map (enc, ct_out_0, k_1, k_42, ct_in_1);
ROUND_F_2 : round_f port map (enc, ct_out_1, k_2, k_41, ct_in_2);
ROUND_F_3 : round_f port map (enc, ct_out_2, k_3, k_40, ct_in_3);
ROUND_F_4 : round_f port map (enc, ct_out_3, k_4, k_39, ct_in_4);
ROUND_F_5 : round_f port map (enc, ct_out_4, k_5, k_38, ct_in_5);
ROUND_F_6 : round_f port map (enc, ct_out_5, k_6, k_37, ct_in_6);
ROUND_F_7 : round_f port map (enc, ct_out_6, k_7, k_36, ct_in_7);
ROUND_F_8 : round_f port map (enc, ct_out_7, k_8, k_35, ct_in_8);
ROUND_F_9 : round_f port map (enc, ct_out_8, k_9, k_34, ct_in_9);
ROUND_F_10 : round_f port map (enc, ct_out_9, k_10, k_33, ct_in_10);
ROUND_F_11 : round_f port map (enc, ct_out_10, k_11, k_32, ct_in_11);
ROUND_F_12 : round_f port map (enc, ct_out_11, k_12, k_31, ct_in_12);
ROUND_F_13 : round_f port map (enc, ct_out_12, k_13, k_30, ct_in_13);
ROUND_F_14 : round_f port map (enc, ct_out_13, k_14, k_29, ct_in_14);
ROUND_F_15 : round_f port map (enc, ct_out_14, k_15, k_28, ct_in_15);
ROUND_F_16 : round_f port map (enc, ct_out_15, k_16, k_27, ct_in_16);
ROUND_F_17 : round_f port map (enc, ct_out_16, k_17, k_26, ct_in_17);
ROUND_F_18 : round_f port map (enc, ct_out_17, k_18, k_25, ct_in_18);
ROUND_F_19 : round_f port map (enc, ct_out_18, k_19, k_24, ct_in_19);
ROUND_F_20 : round_f port map (enc, ct_out_19, k_20, k_23, ct_in_20);
ROUND_F_21 : round_f port map (enc, ct_out_20, k_21, k_22, ct_in_21);
ROUND_F_22 : round_f port map (enc, ct_out_21, k_22, k_21, ct_in_22);
ROUND_F_23 : round_f port map (enc, ct_out_22, k_23, k_20, ct_in_23);
ROUND_F_24 : round_f port map (enc, ct_out_23, k_24, k_19, ct_in_24);
ROUND_F_25 : round_f port map (enc, ct_out_24, k_25, k_18, ct_in_25);
ROUND_F_26 : round_f port map (enc, ct_out_25, k_26, k_17, ct_in_26);
ROUND_F_27 : round_f port map (enc, ct_out_26, k_27, k_16, ct_in_27);
ROUND_F_28 : round_f port map (enc, ct_out_27, k_28, k_15, ct_in_28);
ROUND_F_29 : round_f port map (enc, ct_out_28, k_29, k_14, ct_in_29);
ROUND_F_30 : round_f port map (enc, ct_out_29, k_30, k_13, ct_in_30);
ROUND_F_31 : round_f port map (enc, ct_out_30, k_31, k_12, ct_in_31);
ROUND_F_32 : round_f port map (enc, ct_out_31, k_32, k_11, ct_in_32);
ROUND_F_33 : round_f port map (enc, ct_out_32, k_33, k_10, ct_in_33);
ROUND_F_34 : round_f port map (enc, ct_out_33, k_34, k_9, ct_in_34);
ROUND_F_35 : round_f port map (enc, ct_out_34, k_35, k_8, ct_in_35);
ROUND_F_36 : round_f port map (enc, ct_out_35, k_36, k_7, ct_in_36);
ROUND_F_37 : round_f port map (enc, ct_out_36, k_37, k_6, ct_in_37);
ROUND_F_38 : round_f port map (enc, ct_out_37, k_38, k_5, ct_in_38);
ROUND_F_39 : round_f port map (enc, ct_out_38, k_39, k_4, ct_in_39);
ROUND_F_40 : round_f port map (enc, ct_out_39, k_40, k_3, ct_in_40);
ROUND_F_41 : round_f port map (enc, ct_out_40, k_41, k_2, ct_in_41);
ROUND_F_42 : round_f port map (enc, ct_out_41, k_42, k_1, ct_in_42);
ROUND_F_43 : round_f port map (enc, ct_out_42, k_43, k_0, ct_in_43);
block_out <= ct_in_43;
-- SIMON Core
pr_smn : process(clk, rst, enc, key, key_s)
begin
-- no rst switch/phase distinction needed due to full unrolling of key schedule
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
end process;
end Behavioral;
|
gpl-2.0
|
0b6f07b59b9e721596382d081375ba73
| 0.646218 | 2.409952 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/testbench.vhd
| 1 | 3,835 |
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.tb_package.all;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT tb_master
PORT(
done_i : IN std_logic_vector(gen_number downto 0);
command_o : OUT command_rec
);
END COMPONENT;
COMPONENT reset_gen
Port (
command_i : in command_rec;
reset_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT clock_gen
Port (
command_i : in command_rec;
clk_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT enable_gen
Port (
command_i : in command_rec;
enable_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT bit_in_gen
Port (
command_i : in command_rec;
enable_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
END COMPONENT;
COMPONENT out_tracer
Port (
clk_i : in std_logic;
out_data_i : in std_logic_vector(7 downto 0)
);
END COMPONENT;
-- *************************************************************
-- D U T
-- *************************************************************
COMPONENT shiftreg
Port (
clk : in std_logic;
rst : in std_logic;
leftShift : in std_logic;
rightShift : in std_logic;
leftIn : in std_logic;
rightIn : in std_logic;
regOut : out std_logic_vector(7 downto 0) := (others => '0')
);
END COMPONENT;
signal done_i : std_logic_vector(gen_number downto 0);
signal command_o : command_rec;
signal s_reset : std_logic;
signal s_not_reset : std_logic;
signal s_clk : std_logic;
signal s_enable : std_logic;
signal s_not_enable : std_logic;
signal s_bit_in : std_logic;
signal s_not_bit_in : std_logic;
signal s_out_data_o : std_logic_vector(7 downto 0);
BEGIN
i_tb_master: tb_master PORT MAP(
done_i => done_i,
command_o => command_o
);
i_reset_gen: reset_gen PORT MAP(
command_i => command_o,
reset_o => s_reset,
done_o => done_i
);
i_clock_gen: clock_gen PORT MAP(
command_i => command_o,
clk_o => s_clk,
done_o => done_i
);
i_enable_gen: enable_gen PORT MAP(
command_i => command_o,
enable_o => s_enable,
done_o => done_i
);
i_bit_in_gen: bit_in_gen PORT MAP(
command_i => command_o,
enable_o => s_bit_in,
done_o => done_i
);
i_out_tracer: out_tracer PORT MAP(
clk_i => s_clk,
out_data_i => s_out_data_o
);
-- *************************************************************
-- D U T
-- *************************************************************
i_shiftreg: shiftreg PORT MAP(
clk => s_clk,
rst => s_reset,
leftShift => s_enable,
rightShift => s_not_enable,
leftIn => s_not_bit_in,
rightIn => s_bit_in,
regOut => s_out_data_o
);
-- *************************************************************
-- assignements
-- *************************************************************
done_i(2) <= '0';
done_i(3) <= '0';
done_i(4) <= '0';
done_i(0) <= 'Z';
done_i(1) <= 'Z';
done_i(5) <= 'Z';
done_i(6) <= 'Z';
s_not_reset <= not s_reset;
s_not_enable <= not s_enable;
s_not_bit_in <= not s_bit_in;
END;
|
mit
|
7cf4bee24467bb248199917128d525a7
| 0.462842 | 3.280582 | false | false | false | false |
samvartaka/simon_vhdl
|
INNER_ROUND_PIPELINING/K_2/simon.vhd
| 2 | 4,591 |
-- SIMON 64/128
-- Simon core component
--
-- K=1 inner-round pipelining based of iterative cache-routing architecture
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end component;
component key_schedule is
port (r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end component;
component ram is
port (data_in : in std_logic_vector(31 downto 0);
rw : in std_logic;
clk : in std_logic;
address : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal r_s : std_logic_vector(7 downto 0); -- round index
signal key_s : key_t; -- intermediate key (in words)
signal subkey_out_s : std_logic_vector(31 downto 0); -- round key
signal v_in_s : std_logic_vector(63 downto 0); -- intermediate 'plaintext'
signal v_out_s : std_logic_vector(63 downto 0); -- intermediate 'ciphertext'
signal ram_rw : std_logic;
signal ram_data_out : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (r_s, key_s(0), key_s(1), key_s(3), subkey_out_s);
ROUND_F_0 : round_f port map (clk, rst, v_in_s, key_s(0), v_out_s);
RAM_0 : ram port map (key_s(0), ram_rw, clk, r_s, ram_data_out);
-- SIMON round index regulation
pr_r : process(clk, rst)
begin
if rising_edge(clk) then
-- initialization clock
if rst = '1' then
if enc = '0' then
if (r_s = X"00") then
r_s <= X"01";
else
r_s <= (others => '0');
end if;
else
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
-- running clock
else
if enc = '0' then
if r_s /= X"2B" then
r_s <= std_logic_vector(unsigned(r_s) + 1);
else
-- in preparation for subsequent decryption
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
else
if r_s /= X"00" then
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
end if;
end if;
end if;
end process;
-- SIMON key cache rotation
pr_ks : process(clk, rst, key_s, key, ram_data_out, subkey_out_s)
begin
if rising_edge(clk) then
if enc = '0' then
if rst = '1' then
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
else
-- final iteration is just to write final round key to ram
if (r_s /= X"2B") then
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out_s;
end if;
end if;
else
key_s(0) <= ram_data_out;
end if;
end if;
end process;
-- SIMON Core
pr_smn : process(clk, rst, enc, r_s, block_in, v_in_s, v_out_s, ram_rw)
begin
if rising_edge(clk) then
-- initalize
if rst = '1' then
if enc = '0' then
v_in_s <= block_in;
-- write every round key to RAM during encryption
-- so that encryption also functions as pre-expansion for decryption
ram_rw <= '1';
else
-- swap blocks for decryption
v_in_s <= block_in(31 downto 0) & block_in(63 downto 32);
ram_rw <= '0';
end if;
-- run
else
if enc = '0' then
if (r_s /= X"2B") then
v_in_s <= v_out_s;
else
ram_rw <= '0';
end if;
else
v_in_s <= v_out_s;
end if;
end if;
end if;
end process;
-- v_in_s instead of v_out_s during decryption because of inner-round pipelining with negative-edge triggered registers
block_out <= v_out_s when (enc = '0') else v_in_s(31 downto 0) & v_in_s(63 downto 32);
end Behavioral;
|
gpl-2.0
|
260ab3c42f99d32aec768bb6ceea9e1e
| 0.590721 | 2.794279 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/tb_debounce.vhd
| 1 | 1,710 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_debounce is
end tb_debounce;
architecture behav of tb_debounce is
signal clk : std_logic := '0';
signal io_i : std_logic := '0';
signal io_o : std_logic := '0';
signal noise : std_logic := '0';
signal fixed : std_logic := '0';
signal toggling : std_logic := '0';
signal riseedge : std_logic := '0';
signal falledge: std_logic := '0';
begin
process
begin
clk <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
VARIABLE seed1: positive := 1;
VARIABLE seed2: positive := 1;
VARIABLE rand: real;
VARIABLE t_rand: time;
begin
noise <= not noise;
UNIFORM(seed1, seed2, rand);
t_rand := (rand*100.0)*1 ns;
wait for t_rand;
end process;
process
begin
wait for 1400 ns;
toggling <= '1';
wait for 600 ns;
toggling <= '0';
fixed <= '1';
wait for 2000 ns;
toggling <= '1';
fixed <= '0';
wait for 1000 ns;
toggling <= '0';
wait for 3000 ns;
assert false report "done" severity failure;
wait;
end process;
io_i <= noise when toggling = '1' else
fixed;
debounce : entity work.debounce
generic map(
CNT => 15 -- 1500000 = 30 ms at 50 MHz; hier 300ns
)
port map(
clk_50 => clk,
input => io_i,
output => io_o,
riseedge => riseedge,
falledge => falledge
);
end behav;
|
mit
|
ce070b4f271d2934f9ef0ee40ba5259d
| 0.525731 | 3.741794 | false | false | false | false |
samvartaka/simon_vhdl
|
OUTER_ROUND_PIPELINING/round_f.vhd
| 2 | 1,444 |
-- SIMON 64/128
-- feistel round function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- v_in: plaintext block
-- v_k: subkey
-- v_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity round_f is
port(enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end round_f;
architecture Behavioral of round_f is
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal op_8_s : std_logic_vector(31 downto 0);
signal v_l : std_logic_vector(31 downto 0);
signal v_r : std_logic_vector(31 downto 0);
begin
-- written out for clarity but this is optimized to single expression by synthesis
v_l <= v_in(31 downto 0) when enc = '0' else v_in(63 downto 32);
v_r <= v_in(63 downto 32) when enc = '0' else v_in(31 downto 0);
-- shifts over left half
op_1_s <= std_logic_vector(rotate_left(unsigned(v_r), 1));
op_2_s <= std_logic_vector(rotate_left(unsigned(v_r), 2));
op_8_s <= std_logic_vector(rotate_left(unsigned(v_r), 8));
-- xors/ands over subkey and right half
v_out <= (((op_1_s and op_8_s) xor op_2_s xor v_l xor v_k_e) & v_r) when enc = '0' else (v_r & ((op_1_s and op_8_s) xor op_2_s xor v_l xor v_k_d));
end Behavioral;
|
gpl-2.0
|
e4c3312cbafc7eb7bf6e26d15fe41492
| 0.639197 | 2.6593 | false | false | false | false |
samvartaka/simon_vhdl
|
INNER_ROUND_PIPELINING/K_1/tb_round.vhd
| 1 | 2,672 |
-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(clk : in std_logic;
rst : in std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal v_k : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rst => rst,
v_in => v_in,
v_k => v_k,
v_out => v_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- init
rst <= '1';
wait for clk_period;
-- prepare first right half
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k <= X"03020100";
rst <= '0';
wait for clk_period;
-- do first round
-- already set new right-half value to be loaded into reg
v_in <= v_out(31 downto 0) & v_out(31 downto 0);
v_k <= X"0B0A0908";
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
v_in <= v_out(63 downto 32) & v_out(63 downto 32);
v_k <= X"13121110";
wait for clk_period;
assert v_out = X"154D4E7FFC8B8A84"
report "ROUND_F ERROR (r_1)" severity FAILURE;
v_in <= v_out(63 downto 32) & v_out(63 downto 32);
v_k <= X"1B1A1918";
wait for clk_period;
assert v_out = X"B2A6BE7C154D4E7F"
report "ROUND_F ERROR (r_2)" severity FAILURE;
v_in <= v_out(63 downto 32) & v_out(63 downto 32);
v_k <= X"70A011C3";
wait for clk_period;
assert v_out = X"E0C1D225B2A6BE7C"
report "ROUND_F ERROR (r_3)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
862b2b42ce2a4e0be24dbc561ac3d93c
| 0.605913 | 2.888649 | false | false | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/A_inst.vhd
| 1 | 145 |
A_inst : A PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
result => result_sig
);
|
mit
|
b9243c78aab557d422534bfd4c5668c8
| 0.524138 | 2.589286 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
shiftreg/vhdl/shiftreg.vhd
| 1 | 986 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
entity shiftreg is
port(
rst : in std_logic;
clk : in std_logic;
leftShift : in std_logic;
rightShift : in std_logic;
leftIn : in std_logic;
rightIn : in std_logic;
regOut : out std_logic_vector(7 downto 0)
);
end shiftreg;
architecture Structural of shiftreg is
signal value : std_logic_vector(7 downto 0);
begin
assert not (leftShift = '1' and rightShift = '1') report "can't shift both directions!" severity note;
shift: process(clk, rst)
begin
if rst = '1' then
value <= (others => '0');
elsif rising_edge(clk) then
if leftShift = '1' then
value <= rightIn & value(7 downto 1);
elsif rightShift = '1' then
value <= value(6 downto 0) & leftIn;
end if;
end if;
end process shift;
regOut <= value;
end Structural;
|
mit
|
47f3bc44b512d618ec5fbea120f5008b
| 0.589249 | 3.651852 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
i2c/hdl/i2c_interface.vhd
| 5 | 11,176 |
------------------------------------------------------------------
-- i2c_interface.vhd -- I2C Master Interface for
-- Avalon Bus Slave Interface
------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.8 alpha
-- History :
-- 20-mar-2002 CG 0.1 initial alpha release
-- 20-mar-2002 CG 0.2 minor corrections
-- 27-mar-2002 CG 0.6 interface is working yet
-- 02-apr-2002 CG 0.7 minor corrections
-- 09-05 -2006 RB 0.8 synchronise scl_in and sda_in with rising_edge of clk
------------------------------------------------------------------
-- Registers description:
--
-- Adr RW Name
-- 00 RW DR - transmit and receive data register
-- 01 RW CR - control register (changed to RW mode)
-- 10 RO SR - status register
-- 11 RW CD - clock divisor
--
-- SR - status register bits
--
-- +---------+-------+-------+-------+-------+
-- |bit 7..5 | bit 3 | bit 2 | bit 1 | bit 0 |
-- +---------+-------+-------+-------+-------+
-- | UNUSED | TIP | IPE | BSY | LAR |
-- +---------+-------+-------+-------+-------+
--
-- TIP - transfer in progress
-- IPE - interrupt pending
-- BSY - I2C bus busy
-- LAR - last acknowledge received
--
-- CR - control register bits
--
-- +---------+-------+-------+-------+-------+-------+-------+
-- | bit 7..6| bit 5 | bit 4 | bit 3 | bit 2 | bit 1 | bit 0 |
-- +---------+-------+-------+-------+-------+-------+-------+
-- | UNUSED | IEN | WR | RD | STA | STP | ACK |
-- +---------+-------+-------+-------+-------+-------+-------+
--
-- ACK - Acknowledge bit for reading
-- STP - Generate a I2C Stop Sequence
-- STA - Generate a I2C Start Sequence
-- RD - Read command bit
-- WR - Write command bit
-- IEN - Interrupt Enable
--
-- To start a transfer WR or RD *MUST* BE set.
-- When command transfer has started TIP goes high
-- and write to CR are ignored until TIP goes low.
-- At end of transfer IRQ goes high if interrupt is enabled (IEN=1).
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_interface is
port(
clk : in std_logic;
reset : in std_logic;
-- Avalon bus signals
address : in std_logic_vector(1 downto 0);
chipselect : in std_logic;
write : in std_logic;
writedata : in std_logic_vector(7 downto 0);
read : in std_logic;
readdata : out std_logic_vector(7 downto 0);
irq : out std_logic;
-- I2C signals
scl : inout std_logic;
sda : inout std_logic
);
end i2c_interface;
architecture structural of i2c_interface is
component i2c_core
port(
-- I2C signals
sda_in : in std_logic;
scl_in : in std_logic;
sda_out : out std_logic;
scl_out : out std_logic;
-- interface signals
clk : in std_logic;
rst : in std_logic;
sclk : in std_logic;
ack_in : in std_logic;
ack_out : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
cmd_start : in std_logic;
cmd_stop : in std_logic;
cmd_read : in std_logic;
cmd_write : in std_logic;
cmd_done_ack : in std_logic;
cmd_done : out std_logic;
busy : out std_logic
-- debug signals
--state : out std_logic_vector(5 downto 0)
);
end component;
component i2c_clkgen
port(
signal clk : in std_logic;
signal rst : in std_logic;
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end component;
-- I2C base clock
signal i_sclk : std_logic;
-- I2C serial clock output
signal i_scl_out : std_logic;
-- clock divisor register
signal i_clkdiv_reg : std_logic_vector(7 downto 0);
-- status register bits
signal i_tip_reg : std_logic; -- transfer in progress ( bit 3 )
signal i_int_pe_reg : std_logic; -- interrupt pending ( bit 2 )
signal i_busy_reg : std_logic; -- busy ( bit 1 )
signal i_lar_reg : std_logic; -- last acknowledge received ( bit 0 )
-- control register bits
signal i_int_en_reg : std_logic; -- interrupt enable ( bit 5 )
signal i_write_reg : std_logic; -- write command ( bit 4 )
signal i_read_reg : std_logic; -- read command ( bit 3 )
signal i_start_reg : std_logic; -- command with a start ( bit 2 )
signal i_stop_reg : std_logic; -- command with a stop ( bit 1 )
signal i_ack_reg : std_logic; -- acknowledge to send ( bit 0 )
-- data register
signal i_data_out : std_logic_vector(7 downto 0);
signal i_data_in : std_logic_vector(7 downto 0);
-- command done & acknowledge signals
signal i_cmd_done_ack : std_logic;
signal i_cmd_done : std_logic;
-- internal signals
signal i_readdata : std_logic_vector(7 downto 0);
signal i_irq : std_logic;
-- write strobe
signal i_write_strobe : std_logic;
-- read strobe
signal i_read_strobe : std_logic;
-- interrupt clear
signal i_int_clr : std_logic;
-- just implement open collector in module
signal scl_in : std_logic;
signal sda_in : std_logic;
signal scl_out : std_logic;
signal sda_out : std_logic;
begin
scl_in <= scl when rising_edge(clk); -- RB 0.8
sda_in <= sda when rising_edge(clk); -- RB 0.8
--scl <= 'Z' when (scl_out = '1') else '0';
scl <= '1' when (scl_out = '1') else '0'; -- RB 0.8 to have nice scl ( no more open collector !! )
sda <= 'Z' when (sda_out = '1') else '0';
clkgen : i2c_clkgen port map(
clk => clk,
rst => reset,
clk_cnt => i_clkdiv_reg,
sclk => i_sclk,
scl_in => scl_in,
scl_out => i_scl_out
);
core : i2c_core port map(
clk => clk,
rst => reset,
sclk => i_sclk,
ack_in => i_ack_reg,
ack_out => i_lar_reg,
data_in => i_data_in,
data_out => i_data_out,
cmd_start => i_start_reg,
cmd_stop => i_stop_reg,
cmd_read => i_read_reg,
cmd_write => i_write_reg,
cmd_done_ack => i_cmd_done_ack,
cmd_done => i_cmd_done,
busy => i_busy_reg,
sda_in => sda_in,
scl_in => scl_in,
sda_out => sda_out,
scl_out => i_scl_out
-- state => state
);
-- read strobe
i_read_strobe <= (chipselect and read);
-- output to avalon bus
data_out_sync : process(clk, reset)
begin
if (reset = '1') then
readdata <= (others => '0');
irq <= '0';
elsif (rising_edge(clk)) then
if (i_read_strobe = '1') then
readdata <= i_readdata;
end if;
irq <= i_irq;
end if;
end process;
-- output multiplexer
data_out_comb : process(address, i_ack_reg, i_stop_reg, i_start_reg, i_read_reg, i_write_reg, i_int_en_reg, i_data_out, i_lar_reg, i_busy_reg, i_int_pe_reg, i_tip_reg, i_clkdiv_reg)
begin
i_readdata <= (others => '0');
case address is
when "00" => i_readdata <= i_data_out;
when "01" =>
i_readdata(0) <= i_ack_reg;
i_readdata(1) <= i_stop_reg;
i_readdata(2) <= i_start_reg;
i_readdata(3) <= i_read_reg;
i_readdata(4) <= i_write_reg;
i_readdata(5) <= i_int_en_reg;
when "10" => i_readdata(0) <= i_lar_reg;
i_readdata(1) <= i_busy_reg;
i_readdata(2) <= i_int_pe_reg;
i_readdata(3) <= i_tip_reg;
when "11" => i_readdata <= i_clkdiv_reg;
when others => i_readdata <= (others => '0');
end case;
end process;
-- output scl already syncronized in core
scl_out <= i_scl_out;
-- transfer in progress
i_tip_reg <= (i_read_reg OR i_write_reg);
-- write strobe
i_write_strobe <= (chipselect and write);
-- interrupt output
i_irq <= (i_int_pe_reg AND i_int_en_reg);
-- interrupt clear signal coming from outside
i_int_clr <= '1' when (address = "00" and chipselect = '1') else '0';
data_in_sync : process(clk, reset)
begin
if (reset = '1') then
i_int_pe_reg <= '0';
i_data_in <= (others => '0');
i_int_en_reg <= '0';
i_write_reg <= '0';
i_read_reg <= '0';
i_start_reg <= '0';
i_stop_reg <= '0';
i_ack_reg <= '0';
i_clkdiv_reg <= "10000011";
i_cmd_done_ack <= '0';
elsif (rising_edge(clk)) then
i_cmd_done_ack <= '0';
-- no transfer in progress
if (i_tip_reg = '0') then
if (i_write_strobe = '1') then
case address is
when "00" => i_data_in <= writedata;
when "01" => i_ack_reg <= writedata(0);
i_stop_reg <= writedata(1);
i_start_reg <= writedata(2);
i_read_reg <= writedata(3);
i_write_reg <= writedata(4);
i_int_en_reg <= writedata(5);
when "11" => i_clkdiv_reg <= writedata;
when others => null;
end case;
end if;
if (i_int_clr = '1') then
i_int_pe_reg <= '0';
end if;
else
if (i_cmd_done = '1') then
-- clear command bits
i_write_reg <= '0';
i_read_reg <= '0';
i_start_reg <= '0';
i_stop_reg <= '0';
-- set interrupt pending
i_int_pe_reg <= '1';
-- acknowledge cmd done to core controller
i_cmd_done_ack <= '1';
end if;
end if;
end if;
end process data_in_sync;
end structural;
|
unlicense
|
ad9bdf27dd048043c26472055bc7f2f0
| 0.451544 | 3.736209 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/out_tracer.vhd
| 1 | 2,174 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_textio.all;
library std;
use std.textio.all;
use work.tb_package.all;
entity out_tracer is
Port (
clk_i : in std_logic;
out_data_i : in std_logic_vector(7 downto 0)
);
end out_tracer;
architecture Behavioral of out_tracer is
begin
p_main: process
--file emifb_tracer_file : text is OUT "$model_tech_tcl/../../../RTS_DSP/vhdl/Testcase/TC_RESET/TRACEFILES/emifb_trace.txt";
file out_tracer_file : text is OUT gen_filename&"/tracefiles/out_trace.txt";
variable v_line : line;
variable v_read_data0_hex : string (2 downto 1);
variable v_trace_nr : natural;
variable v_read_data0 : std_logic_vector(7 downto 0);
begin
write(v_line, string'(" ************************************************************** "));
writeline(out_tracer_file, v_line);
write(v_line, string'(" *** OUT Trace File *** "));
writeline(out_tracer_file, v_line);
write(v_line, string'(" ************************************************************** "));
writeline(out_tracer_file, v_line);
write(v_line, string'(" NR"));
write(v_line, string'(" "));
write(v_line, string'(" TIME"));
write(v_line, string'(" "));
write(v_line, string'(" DATA"));
write(v_line, string'(" "));
writeline(out_tracer_file, v_line);
write(v_line, string'(" ---------------------------------------------------------------"));
writeline(out_tracer_file, v_line);
write(v_line, string'(" | | |"));
writeline(out_tracer_file, v_line);
while true loop
wait until out_data_i'EVENT;
v_read_data0 :=out_data_i;
write(v_line, v_trace_nr, justified => right, field => 4);
write(v_line, string'(" "));
write(v_line, now, justified => right, field => 12, unit => ns);
write(v_line, string'(" "));
v_read_data0_hex :=stdlogicvector_to_hexstring(v_read_data0);
write(v_line, v_read_data0_hex);
writeline(out_tracer_file, v_line);
v_trace_nr := v_trace_nr+1;
end loop;
end process p_main;
end Behavioral;
|
mit
|
2aa7b318b63e8e1f5a72c3f7edffbc33
| 0.561178 | 3.101284 | false | false | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/Acumulador.vhd
| 1 | 4,856 |
-- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: Acumulador.vhd
-- Megafunction Name(s):
-- altaccumulate
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Acumulador IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END Acumulador;
ARCHITECTURE SYN OF acumulador IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(4 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 4,
width_out => 5
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Acumulador.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Acumulador.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Acumulador.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Acumulador.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Acumulador_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Acumulador_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Acumulador_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
2890229a7efdc04fc230c31e8bf3de22
| 0.637974 | 3.687168 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task2/clock_gen.vhd
| 1 | 3,186 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:04:12 10/01/2013
-- Design Name:
-- Module Name: clock_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock_gen is
port(
rst_i : in std_logic;
clk_i : in std_logic;
ClrDiv_i : in std_logic;
TopRx : out std_logic;
TopTx : out std_logic;
Top16 : out std_logic;
Baud : in std_logic_vector(2 downto 0)
);
end clock_gen;
architecture Behavioral of clock_gen is
signal Divisor : natural;
signal s_Top16 : std_logic;
signal Div16 : integer;
signal ClkDiv : natural;
signal RxDiv : natural;
begin
-- --------------------------
-- Baud rate selection
-- --------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
Divisor <= 0;
elsif rising_edge(clk_i) then
case Baud is
when "000" => Divisor <= 26; -- 115.200
when "001" => Divisor <= 52; -- 57.600
when "010" => Divisor <= 93; -- 38.400
when "011" => Divisor <= 160; -- 19.200
when "100" => Divisor <= 322; -- 9.600
when "101" => Divisor <= 646; -- 4.800
when "110" => Divisor <= 1294; -- 2.400
when "111" => Divisor <= 2590; -- 1.200
when others => Divisor <= 26; -- n.u.
end case;
end if;
end process;
-- --------------------------
-- Clk16 Clock Generation
-- --------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
s_Top16 <= '0';
Div16 <= 0;
elsif rising_edge(clk_i) then
s_Top16 <= '0';
if Div16 = Divisor then
Div16 <= 0;
s_Top16 <= '1';
else
Div16 <= Div16 + 1;
end if;
end if;
end process;
-- --------------------------
-- Tx Clock Generation
-- --------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
TopTx <= '0';
ClkDiv <= 0;
elsif rising_edge(clk_i) then
TopTx <= '0';
if s_Top16='1' then
ClkDiv <= ClkDiv + 1;
if ClkDiv = 15 then
TopTx <= '1';
ClkDiv<=0;
end if;
end if;
end if;
end process;
-- ------------------------------
-- Rx Sampling Clock Generation
-- ------------------------------
process (rst_i, clk_i)
begin
if rst_i='1' then
TopRx <= '0';
RxDiv <= 0;
elsif rising_edge(clk_i) then
TopRx <= '0';
if ClrDiv_i='1' then
RxDiv <= 0;
elsif s_Top16='1' then
if RxDiv = 7 then
RxDiv <= 0;
TopRx <= '1';
else
RxDiv <= RxDiv + 1;
end if;
end if;
end if;
end process;
Top16 <= s_Top16;
end Behavioral;
|
mit
|
a9d8e380a42d0f7fca0bfaf72689ae9e
| 0.497803 | 3.516556 | false | false | false | false |
samvartaka/simon_vhdl
|
MIXED_ROUND_PIPELINING/tb_round.vhd
| 1 | 2,985 |
-- SIMON 64/128
-- feistel round function test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_round IS
END tb_round;
ARCHITECTURE behavior OF tb_round IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT round_f
port(clk : in std_logic;
rst : in std_logic;
enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal v_k_e : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key (encrypt)
signal v_k_d : std_logic_vector(31 downto 0) := (others => '0'); -- Round Key (decrypt)
signal v_in : std_logic_vector(63 downto 0) := (others => '0'); -- Input block
signal enc : std_logic := '0';
--Outputs
signal v_out : std_logic_vector(63 downto 0); -- Output block
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: round_f PORT MAP (
clk => clk,
rst => rst,
enc => enc,
v_in => v_in,
v_k_e => v_k_e,
v_k_d => v_k_d,
v_out => v_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
v_in <= X"656B696C20646E75";
v_k_e <= X"03020100";
--encrypt
enc <= '0';
-- init
rst <= '1';
wait for clk_period;
-- run
rst <= '0';
wait for clk_period;
assert v_out = X"FC8B8A84656B696C"
report "ROUND_F ERROR (r_0)" severity FAILURE;
v_in <= v_out;
v_k_e <= X"0B0A0908";
wait for clk_period;
assert v_out = X"154D4E7FFC8B8A84"
report "ROUND_F ERROR (r_1)" severity FAILURE;
v_in <= v_out;
v_k_e <= X"13121110";
wait for clk_period;
assert v_out = X"B2A6BE7C154D4E7F"
report "ROUND_F ERROR (r_2)" severity FAILURE;
v_in <= v_out;
v_k_e <= X"1B1A1918";
wait for clk_period;
assert v_out = X"E0C1D225B2A6BE7C"
report "ROUND_F ERROR (r_3)" severity FAILURE;
-- decrypt
enc <= '1';
v_in <= v_out;
v_k_d <= v_k_e;
wait for clk_period;
assert v_out = X"B2A6BE7C154D4E7F"
report "ROUND_F ERROR (r_4)" severity FAILURE;
v_in <= v_out;
v_k_d <= X"13121110";
wait for clk_period;
assert v_out = X"154D4E7FFC8B8A84"
report "ROUND_F ERROR (r_5)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
3e1368b42139bc432dc9dd56f36f35d5
| 0.59062 | 2.748619 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_SEPERATE_RAMROUTE/tb_keyschedule.vhd
| 2 | 12,901 |
-- SIMON 64/128
-- key schedule test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.NUMERIC_STD.ALL;
ENTITY tb_keyschedule IS
END tb_keyschedule;
ARCHITECTURE behavior OF tb_keyschedule IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT key_schedule
port (
r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal r : std_logic_vector(7 downto 0); -- round index
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- k0..3
--Outputs
signal subkey_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: key_schedule PORT MAP (
r => r,
k_0 => key_s(0),
k_1 => key_s(1),
k_3 => key_s(3),
subkey_out => subkey_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
key_s(0) <= X"03020100";
key_s(1) <= X"0b0a0908";
key_s(2) <= X"13121110";
key_s(3) <= X"1b1a1918";
r <= X"00";
wait for clk_period;
assert subkey_out = X"03020100"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"0b0a0908"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"13121110"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"1b1a1918"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"70a011c3"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"b770ec49"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"57e3e835"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"d397bc42"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"94dcf81f"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"bf4b5f18"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"8e5dabb9"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"dbf4a863"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"cd0c28fc"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"5cb69911"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"79f112a5"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"77205863"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"99880c12"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"1ce97c58"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"c8ed2145"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"b800dbb8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"e86a2756"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"7c06d4dd"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"ab52df0a"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"247f66a8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"53587ca6"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"d25c13f1"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"4583b64b"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"7d9c960d"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"efbfc2f3"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"89ed8513"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"308dfc4e"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"bf1a2a36"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"e1499d70"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"4ce4d2ff"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"32b7ebef"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"c47505c1"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"d0e929e8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"8fe484b9"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"42054bee"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"af77bae2"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"18199c02"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"719e3f1c"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"0c1cf793"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"15df4696"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
6c17fa563e322ccdbf92e33cc34d8c47
| 0.582358 | 2.394839 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task5/tb_ps2.vhd
| 1 | 1,708 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_ps2 is
end tb_ps2;
architecture behav of tb_ps2 is
component clk_res_gen is
port(
clk_50 : out std_logic;
rst : out std_logic
);
end component clk_res_gen;
component keyboardSig is
port(
ps2c : out std_logic;
ps2d : out std_logic
);
end component keyboardSig;
component ps2Receiver is
port(
clk : in std_logic;
rst : in std_logic;
-- data
rxData : out std_logic_vector(7 downto 0);
-- module sync signals
dataReady : out std_logic;
dataFetched : in std_logic;
-- ps2 pins
ps2Data : in std_logic;
ps2Clk : in std_logic
);
end component ps2Receiver;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal rxData : std_logic_vector(7 downto 0) := (others => '0');
signal dataReady : std_logic := '0';
signal dataFetched : std_logic := '1';
signal ps2Data : std_logic := '0';
signal ps2Clk : std_logic := '0';
begin
process
begin
wait for 7 ms;
assert false report "done" severity failure;
wait;
end process;
clk_res: clk_res_gen
port map(
clk_50 => clk,
rst => rst
);
keyboard: keyboardSig
port map(
ps2c => ps2Clk,
ps2d => ps2Data
);
rec: ps2Receiver
port map(
clk => clk,
rst => rst,
rxData => rxData,
dataReady => dataReady,
dataFetched => dataFetched,
ps2Data => ps2Data,
ps2Clk => ps2Clk
);
end behav;
|
mit
|
d2becb381ace248ebb6177ace0b6c901
| 0.570843 | 3.105455 | false | false | false | false |
Derek-X-Wang/VGA-Text-Generator
|
VGA-Text-Generator.srcs/sources_1/new/wrapper.vhd
| 1 | 3,564 |
-- This is a wrapper made for calling Pixel_On_Text.vhd form verilog
-- Since I'm not familiar with mapping string and structure(point_2d) bewteen verilog and vhdl, this is a simple walkaround.
-- By using Pixel_On_Text2.vhd, this file may not be necessary anymore.
-- However, sometimes it's a bit more convenient to group all you text in one place.
-- I also include some sample code for acheiving dynamic text(a simple way).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- note this line.The package is compiled to this directory by default.
-- so don't forget to include this directory.
library work;
-- this line also is must.This includes the particular package into your program.
use work.commonPak.all;
entity wrapper is
Port (
clk: in std_logic;
xCoord: in std_logic_vector(11 downto 0);
yCoord: in std_logic_vector(11 downto 0);
pixOn: out std_logic
);
end wrapper;
architecture Behavioral of wrapper is
signal h : integer := to_integer(signed(xCoord));
signal v : integer := to_integer(signed(yCoord));
-- results
signal d1 : std_logic := '0';
signal d2 : std_logic := '0';
signal d3 : std_logic := '0';
begin
textElement1: entity work.Pixel_On_Text
generic map (
textLength => 38
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 1!@#$ at (50,50)",
position => (50, 50),
horzCoord => h,
vertCoord => v,
pixel => d1
);
textElement2: entity work.Pixel_On_Text
generic map (
textLength => 39
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 2%^&* at (500,50)",
position => (500, 50),
horzCoord => h,
vertCoord => v,
pixel => d2
);
textElement3: entity work.Pixel_On_Text
generic map (
textLength => 41
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 3()_+-= at (50,130)",
position => (50, 130),
horzCoord => h,
vertCoord => v,
pixel => d3
);
-- -- This is a simply way for a dynamic text. Of course, I know you probably have a better solution :)
-- -- With a new input "timeDiv", we can switch on different string
-- with timeDiv select
-- timeDivDigitNum <= "Time/Div: 0.8 sec/div " when 0,
-- "Time/Div: 0.2 sec/div " when 1,
-- "Time/Div: 0.1 sec/div " when 2,
-- "Time/Div: 100 ms/div " when 3,
-- "Time/Div: 50 ms/div " when 4,
-- "Time/Div: 10 ms/div " when 5,
-- "Time/Div: 1 ms/div " when 6,
-- "Time/Div: 0.1ms/div " when 7,
-- "Time/Div: unknown " when OTHERS;
-- textDrawElement4: entity work.Pixel_On_Text
-- generic map (
-- textLength => 23
-- )
-- port map(
-- clk => clk,
-- reset => reset,
-- textPassage => timeDivDigitNum ,--& integer'image(timeDiv),
-- position => (70, 90),
-- hCount => h,
-- vCount => v,
-- drawElement => d4
-- );
pixelInTextGroup: process(clk)
begin
if rising_edge(clk) then
-- the pixel is on when one of the text matched
pixOn <= d1 or d2 or d3;
end if;
end process;
end Behavioral;
|
mit
|
4154b1abebbabd4f65eaf2b3fb53ca0b
| 0.592593 | 3.375 | false | false | false | false |
twasiluk/hdmilight
|
fpga/avr/prog_mem_content.vhd
| 1 | 13,101 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package prog_mem_content is
-- content of p_0 ----------------------------------------------------------------------------------
constant p0_00 : BIT_VECTOR := X"C002E0E0E6A0BFCDE0D4BE1FC01BC01DC01FC021C023C025C027C029C02BC012";
constant p0_01 : BIT_VECTOR := X"0FE82FE201C0C007E0E081AA306393DFCFD1D1EE07B1921DE0B1E01107B1920D";
constant p0_02 : BIT_VECTOR := X"93DF950891DFE090C002E680E0F023229611539024110293E03A81BDF7B1912C";
constant p0_03 : BIT_VECTOR := X"B7CDE783B7FED000D000912CE0B02322963153A0241102A3E03A2DE080023062";
constant p0_04 : BIT_VECTOR := X"E04A2DE08002F00901FC91CFD20CE78ABF8DBF9EB60FB79ED513832483B3839A";
constant p0_05 : BIT_VECTOR := X"BF8DBF9EB60FB79EB548E08ABD87B568E0889530273323339631532024110224";
constant p0_06 : BIT_VECTOR := X"D1C0E982BF8DBF9EB60FB79ED4C78740835683648333938E9612B7ADE884B7FE";
constant p0_07 : BIT_VECTOR := X"C00924FF91FC961423229631531024110213E03A971391EDC0663064931F92FF";
constant p0_08 : BIT_VECTOR := X"D531D4DF23229631530024110203E03A971791EDF7A181200EF82EF924110243";
constant p0_09 : BIT_VECTOR := X"821582139711939CB7BEE0909631B7EDBE0F94F8970AB78DD529D52BD4D9D52F";
constant p0_0A : BIT_VECTOR := X"971391EDC0583064931F92FF90FF911FE090C003BE0F94F8960AB78D86118217";
constant p0_0B : BIT_VECTOR := X"F7B181200F082F0201C0C007E00091FC9614232296310EF2ED4001C02D4FE03A";
constant p0_0C : BIT_VECTOR := X"D0002F18E090D4B7D465D4BBD4BDD46B23229631531024110213E03A971791ED";
constant p0_0D : BIT_VECTOR := X"931F92FF92DF90FF911FE090C003900F900F82139711939CB7BEE0909631B7ED";
constant p0_0E : BIT_VECTOR := X"F35032C083005FEAF049300D0511D0B0F3D13F0F018CE0D0C002E0C02EE993DF";
constant p0_0F : BIT_VECTOR := X"01FC939C4F9E01C9238832804F3F921195702777E050E03001D92D9E82185FCA";
constant p0_10 : BIT_VECTOR := X"92DF92BF950890EF910F91CF2F844FFE01F9075796125F4F2388F01981805F2F";
constant p0_11 : BIT_VECTOR := X"2ED52EC51CF194082EB62EA6D396E090D06BE881BE0F94F89760B7CD93DF92FF";
constant p0_12 : BIT_VECTOR := X"C01134893583358281FAF754900FD34982D2B7ED2F18E068900FD35582B2B7ED";
constant p0_13 : BIT_VECTOR := X"2F61CFC22F61CFC6F641F021F0518181DDEE01C7DDC401C7DE2F01C7F6E1F039";
constant p0_14 : BIT_VECTOR := X"95089380939001C92F28C003EF2FFC009508E090CFFDB400DFFAF4112F18CFBE";
constant p0_15 : BIT_VECTOR := X"971191ED950891DF019CE08A238891F091E09509C00CEF2F2B899190918093DF";
constant p0_16 : BIT_VECTOR := X"9508932E96155F2F1FF3F44C1728919C9616913C9614973091FC96129509F019";
constant p0_17 : BIT_VECTOR := X"F04C070A16E881AE818C810A80E805710551F121859E01E993DF931F92FF92DF";
constant p0_18 : BIT_VECTOR := X"926F924F922F90CF90EF910F91CFF37C070A16E881AE818C1D011CE1DFB801C6";
constant p0_19 : BIT_VECTOR := X"920DE181EFE401DE0169012CBE0F94F897E1B7CD93DF930F92EF92CF92AF928F";
constant p0_1A : BIT_VECTOR := X"01B71E9D2C91E1922422017A2C31E0210B061AE424FFC00BF46904C116A8F7E1";
constant p0_1B : BIT_VECTOR := X"9381E28D2823051104F1018D01DAD36B019501C8938D81800FE60FECE0E101A6";
constant p0_1C : BIT_VECTOR := X"E070E050F4218990E070E05083B3839101F3E0A01B8E01CD200001DF01FE01D4";
constant p0_1D : BIT_VECTOR := X"94F896E101932F76FD57895001F3051F4010DF0E01D8C0040EEC2EE801840193";
constant p0_1E : BIT_VECTOR := X"92BF929F927F925F923F9508903F905F907F909F90BF90DF90FF911F91CFBE0F";
constant p0_1F : BIT_VECTOR := X"861F01C432651C5194082C31E0E1017ABFCDBFDEB60FB7DE93CF931F92FF92DF";
constant p0_20 : BIT_VECTOR := X"1461F0085380916C1CB194082E67C003246624CC87AB8789E0A0EF8FE2808A19";
constant p0_21 : BIT_VECTOR := X"1CB194081F4A0F2895A027AA9590279901ACD290E040E02A01CAE050E030F149";
constant p0_22 : BIT_VECTOR := X"9590279901ACD264E040E02A01CAE050E030876D3360875C873AF30853808110";
constant p0_23 : BIT_VECTOR := X"27335481CF9908A1862E8758833EF3085380911C1CB194081F4A0F2895A027AA";
constant p0_24 : BIT_VECTOR := X"C0BA0591C026F009F13132850591CF800591F4BC3685059101C99680F4189530";
constant p0_25 : BIT_VECTOR := X"E265CF572EC6C02FF0093788F4093783C0C80591F42C3781F4093780C0D40591";
constant p0_26 : BIT_VECTOR := X"2F76FD57915C01D70CCE2EC4C00C816281401CDF2CD1E054346428CD8A28C0B6";
constant p0_27 : BIT_VECTOR := X"F7E9900D911C01D7E030E01001C4816281401CDF2CD1E03401760172E020E00A";
constant p0_28 : BIT_VECTOR := X"01D801C49161C0050192E070E050F4218999E070E05083BC839AE0B00B919701";
constant p0_29 : BIT_VECTOR := X"1B8001CD200001D80EEEE0E205B197001DA187BC879A09B1970185AB85892388";
constant p0_2A : BIT_VECTOR := X"F491F41CF069C01EDD6401F74F1F0187DD9001C495602766894883AB8389E0A0";
constant p0_2B : BIT_VECTOR := X"CE7B236601D51CA1CE9D1CA1DD48C00101C4E06DC00701C4E067C0063762366E";
constant p0_2C : BIT_VECTOR := X"9728B7CD93DF902F904F906F908F90AF90CF90EF910F91DFBFCDBFDEB60FE090";
constant p0_2D : BIT_VECTOR := X"019C01A9856D01CE8618821E821C839A5F21C012E020970091909180BE0F94F8";
constant p0_2E : BIT_VECTOR := X"B5832F322F542B4A2B28E0A0B5842F322F54E040B525950891CFBE0F94F89628";
constant p0_2F : BIT_VECTOR := X"BD89B589BF81B781708C950801B92B4A2B28E0A0B5822F322F542B4A2B28E0A0";
constant p0_30 : BIT_VECTOR := X"9601E090BD89B58905919601E090BD89B589E081FC02F7D9308A0000E0807F87";
constant p0_31 : BIT_VECTOR := X"E0807F8BF7D9308A0000E0806088BD89B589E08005919601E090BD89B5890591";
constant p0_32 : BIT_VECTOR := X"0000000000006088C002B589FF372F38F7D9308A0000E0807F87F7D9308A0000";
constant p0_33 : BIT_VECTOR := X"0000E0807F8BBD89B5890F3330280000000000006084F7D9308A0000E0807F8B";
constant p0_34 : BIT_VECTOR := X"E090BD89B589E0307081952A9596E090F7D1302A5F2FE030BD89B589F7D9308A";
constant p0_35 : BIT_VECTOR := X"01D09508F6F95F3F05919601E090BD89B5897081954A9596E090B78005919601";
constant p0_36 : BIT_VECTOR := X"1BAAE2A1241101BD1DE19F631DE19F720DF00DF00DF00DF01DF19F640DE001F0";
constant p0_37 : BIT_VECTOR := X"94F801CF01AC95909570F7691F991F770BF50BB3F02007E417A21FEE1FAA01FD";
constant p0_38 : BIT_VECTOR := X"250067693A72000A20646425642564643A72000A3D6465757620646172724B4F";
constant p0_39 : BIT_VECTOR := X"316C2031646172720A643A645200617672642031762064643A72000A3D646425";
constant p0_3A : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFF000044433938353431303E0A203E213841006464";
constant p0_3B : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3C : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3D : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3E : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3F : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
-- content of p_1 ----------------------------------------------------------------------------------
constant p1_00 : BIT_VECTOR := X"9005E0FEE0B0E011BFDEE5CF2411C01CC01EC020C022C024C026C028C02AC02C";
constant p1_01 : BIT_VECTOR := X"961153E0241102E3E03A81BBF51901EC93CFC6D0F7E132A8C001E0A6F7D930A6";
constant p1_02 : BIT_VECTOR := X"01FC93CF91CFD245E683E090A390F7B1912C0F982F9201C0C007E09081AC2322";
constant p1_03 : BIT_VECTOR := X"B7DEE0909631B7EDD00097909690F7B181200FA82FA201C0C007E0A081F3F571";
constant p1_04 : BIT_VECTOR := X"C007E02081F3C0423062950891DFE090C003BE0F94F89606B78D821583A28389";
constant p1_05 : BIT_VECTOR := X"B7EDBE0F94F8970AB78DBD87B558E089BD87BD26FD27F7B181300F282F2301C0";
constant p1_06 : BIT_VECTOR := X"9508E0909508BE0F94F8960AB78D86118217821583229711939CB7BEE0909631";
constant p1_07 : BIT_VECTOR := X"2D4FE03A971591EDF7B181200F182F1201C0C007E01091FC9612F00901DC930F";
constant p1_08 : BIT_VECTOR := X"2D8F2F81F7B181200F082F0201C0C007E00091FC9616232296310EF2ED9001C0";
constant p1_09 : BIT_VECTOR := X"831682F48312938E9612B7ADE98DB7FEBF8DBF9EB60FB79ED5062F802F81D50C";
constant p1_0A : BIT_VECTOR := X"24FF91FC9612F00901DC930F9508910FD14FEA8ABF8DBF9EB60FB79ED4568700";
constant p1_0B : BIT_VECTOR := X"961623229631530024110203E03A971591EDF7A181200EF82EF424110243C009";
constant p1_0C : BIT_VECTOR := X"D000D490D4FCE0802F81D4982F802D8FF7B181200F182F1201C0C007E01091FC";
constant p1_0D : BIT_VECTOR := X"93CF930F92EF9508910FD0E9EC8F900F900FD3EC8312938E9612B7ADEC85B7FE";
constant p1_0E : BIT_VECTOR := X"CFE705D196214FFE01FE0511F061300A2F800718EF8FD0C5E1CFE0D02ED62EF8";
constant p1_0F : BIT_VECTOR := X"C002938E96115F8AF0D1F3D181805F2FC01BFD672D6DE040E020019C2D8F4FDE";
constant p1_10 : BIT_VECTOR := X"92EF92CF92AF90DF90FF911F91DFCFE15FEAF42417464F5FF7C1963132804F3F";
constant p1_11 : BIT_VECTOR := X"D000E050EE5F1CE1017EE060EE6BD06DEE85E092BFCDBFDEB60FB7DE93CF931F";
constant p1_12 : BIT_VECTOR := X"3587F709F41CF051818081E91611900F82C1B7FED000DF7001C7900F82A1B7FE";
constant p1_13 : BIT_VECTOR := X"DED401C7DE6401C7D37D348935873582CFCF2F61CFD32F61CFD72F61C0083588";
constant p1_14 : BIT_VECTOR := X"93CF012601279508E030B581EF3FC003B400911FE080FC03BD11E08D308A931F";
constant p1_15 : BIT_VECTOR := X"973091FC01DC91CF01C99509F7B90127012681889621EF3FF4290127012601EC";
constant p1_16 : BIT_VECTOR := X"92CF9714933C4F3F83600FE207399717918D9715912DF0A1971391ED95082F86";
constant p1_17 : BIT_VECTOR := X"C011071B06F981BF819D811B80F9F0F9056115412B89858D016C93CF930F92EF";
constant p1_18 : BIT_VECTOR := X"927F925F923F950890DF90FF911F91DF071B06F981BF819D1D111CF19408856C";
constant p1_19 : BIT_VECTOR := X"50819001E0F0961101370158BFCDBFDEB60FB7DE93CF931F92FF92DF92BF929F";
constant p1_1A : BIT_VECTOR := X"019501C80E8C2E892433018BC0042E220B170AF5018724EEFF7704D104B1E08A";
constant p1_1B : BIT_VECTOR := X"014F01F4F021F719050114E1017C01C901A601B7014D01D41FF71FFDE0F0D37A";
constant p1_1C : BIT_VECTOR := X"01C2E060E0412B898587E060E04083A28380E0B00B9F9701F7E9900D9672921C";
constant p1_1D : BIT_VECTOR := X"BFDEB60FDF2301C2956027668547F7B8150E5001916C01C21EFD2CF1E182DF3D";
constant p1_1E : BIT_VECTOR := X"92CF92AF928F926F924F922F902F904F906F908F90AF90CF90EF910F91DFBFCD";
constant p1_1F : BIT_VECTOR := X"861EC0C1F011C1801C41012E2E2E015B014CBE0F94F89761B7CD93DF930F92EF";
constant p1_20 : BIT_VECTOR := X"0471C05D308A2F8601D51CA12C71E071247724DD87BC879AE0B0E79F878D8A18";
constant p1_21 : BIT_VECTOR := X"01F51CA11F5B1F392FBAFD9797C0FD872F81019BE050E03001B9C019E040E020";
constant p1_22 : BIT_VECTOR := X"97C0FD872F81019BE050E03001B9C019E040E020F409C02D874B8729308A2F81";
constant p1_23 : BIT_VECTOR := X"FD272F262F8608B19408863F834F832D308A2F8101D51CA11F5B1F392FBAFD97";
constant p1_24 : BIT_VECTOR := X"3683F409358CC0DD978D0591F43C328FF409328E0591F1D13684C00101C9318A";
constant p1_25 : BIT_VECTOR := X"DDFB01C42CD1E061C0BF0591C0440591C009F009368C0591C0400591C0ACF009";
constant p1_26 : BIT_VECTOR := X"01C495602766914D1CDF2CD1E0428173815101F70CCE2EC5F459F411CF508A39";
constant p1_27 : BIT_VECTOR := X"01CD200001D8910DCFECE020E1008173815101F70CCE2EC3C08FDE34E030E010";
constant p1_28 : BIT_VECTOR := X"918CDD9D018F01F8DDC701C4E060E0412B898988E060E04083AB8389E0A01B80";
constant p1_29 : BIT_VECTOR := X"0B919701F7E9900D1EFFE0F0F72905A11DB1960187AB878909A185BC859AF091";
constant p1_2A : BIT_VECTOR := X"C0053661366936680178816001C45F0CC02701922F76FD57895983BC839AE0B0";
constant p1_2B : BIT_VECTOR := X"E080F009916C1CB194081CB1940801C4E06AC00401C4E068C00A01C4F469F061";
constant p1_2C : BIT_VECTOR := X"B60FB7DE93CF9508903F905F907F909F90BF90DF90FF911F91CFBE0F94F89661";
constant p1_2D : BIT_VECTOR := X"01C9DE17857E9601821F821D821B83894F3F019EE030F41901270126BFCDBFDE";
constant p1_2E : BIT_VECTOR := X"E09027222F432B5B2B39E0B0E09027222F43E050E030BC1291DFBFCDBFDEB60F";
constant p1_2F : BIT_VECTOR := X"B5897F8B9508708CBD89B58901CA2B5B2B39E0B0E09027222F432B5B2B39E0B0";
constant p1_30 : BIT_VECTOR := X"308A0000E0806084F7D9308A0000E08060889508C002B60005919601E090BD89";
constant p1_31 : BIT_VECTOR := X"E090BD89B58905919601E090BD89B58960849508F7D9308A0000E0807F87F7D9";
constant p1_32 : BIT_VECTOR := X"B58900000000BD89B5897F87C003E020950805919601E090BD89B58905919601";
constant p1_33 : BIT_VECTOR := X"9601E090BD89B5897F87CFDCF0115F2F00000000BD89B58905919601E090BD89";
constant p1_34 : BIT_VECTOR := X"0000E0807F8BE0209508F7E19587E0232F8905314F3F0000E0206084B7900591";
constant p1_35 : BIT_VECTOR := X"9F739F622F823038F7D9308A0000E08060842B28F7E19587E0430F22F7D9308A";
constant p1_36 : BIT_VECTOR := X"1BBB2E1A950801CF1FF90DB01FF90DB027999F659F749F839F920DE01DF19F82";
constant p1_37 : BIT_VECTOR := X"CFFF950801BD019B95809560941A1F881F660BE41BA207F507B31FFF1FBBC00D";
constant p1_38 : BIT_VECTOR := X"3D6474686C20726564252520203A007261207265642525006C617264203A6500";
constant p1_39 : BIT_VECTOR := X"612061767264203A650025206165326C203264616C6131726120726564252520";
constant p1_3A : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF464542413736333200200D000A0052563272";
constant p1_3B : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3C : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3D : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3E : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3F : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
end prog_mem_content;
|
gpl-2.0
|
a23b7f7d31850d4c66b674208e0e156c
| 0.847493 | 2.366938 | false | false | false | false |
gralco/click-clock-board
|
myhdl/clock.vhd
| 1 | 4,656 |
-- File: clock.vhd
-- Generated by MyHDL 0.8.1
-- Date: Sat May 28 18:39:08 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_081.all;
entity clock is
port (
clk: in std_logic;
reset: in std_logic;
en: in std_logic;
count_vec: in unsigned(23 downto 0);
pm: inout std_logic;
LED_vec: in unsigned(41 downto 0)
);
end entity clock;
architecture MyHDL of clock is
type t_array_count is array(0 to 6-1) of unsigned(3 downto 0);
signal count: t_array_count;
type t_array_LED is array(0 to 6-1) of unsigned(6 downto 0);
signal LED: t_array_LED;
begin
count(0) <= count_vec(4-1 downto 0);
count(1) <= count_vec(8-1 downto 4);
count(2) <= count_vec(12-1 downto 8);
count(3) <= count_vec(16-1 downto 12);
count(4) <= count_vec(20-1 downto 16);
count(5) <= count_vec(24-1 downto 20);
CLOCK_COUNTER: process (clk, reset) is
begin
if (reset = '1') then
count(0) <= to_unsigned(0, 4);
count(1) <= to_unsigned(0, 4);
count(2) <= to_unsigned(0, 4);
count(3) <= to_unsigned(0, 4);
count(4) <= to_unsigned(0, 4);
count(5) <= to_unsigned(0, 4);
elsif rising_edge(clk) then
if bool(en) then
count(0) <= ((count(0) + 1) mod 10);
count(1) <= ((count(1) + to_unsigned(count(0) = 9, 1)) mod 6);
count(2) <= ((count(2) + ((count(0) = 9) and (count(1) = 5))) mod 10);
count(3) <= ((count(3) + ((count(0) = 9) and (count(1) = 5) and (count(2) = 9))) mod 6);
count(4) <= resize(unsigned((signed(resize(count(4), 5) + ((count(0) = 9) and (count(1) = 5) and (count(2) = 9) and (count(3) = 5))) mod (10 - signed(resize(7 * count(5), 9)))) + ((count(0) = 9) and (count(1) = 5) and (count(2) = 9) and (count(3) = 5) and (count(4) = 2) and bool(count(5)))), 4);
end if;
if bool(reset) then
count(0) <= to_unsigned(0, 4);
count(1) <= to_unsigned(0, 4);
count(2) <= to_unsigned(0, 4);
count(3) <= to_unsigned(0, 4);
count(4) <= to_unsigned(0, 4);
end if;
end if;
end process CLOCK_COUNTER;
CLOCK_TFF: process (clk, reset) is
begin
if (reset = '1') then
count(0) <= to_unsigned(0, 4);
count(1) <= to_unsigned(0, 4);
count(2) <= to_unsigned(0, 4);
count(3) <= to_unsigned(0, 4);
count(4) <= to_unsigned(0, 4);
count(5) <= to_unsigned(0, 4);
pm <= '0';
elsif rising_edge(clk) then
if bool(en) then
count(5) <= to_unsigned((count(5) xor (((count(0) = 9) and (count(1) = 5) and (count(2) = 9) and (count(3) = 5) and (count(4) = 9)) or ((count(0) = 9) and (count(1) = 5) and (count(2) = 9) and (count(3) = 5) and (count(4) = 2) and bool(count(5))))), 4);
pm <= (pm xor stdl((count(0) = 9) and (count(1) = 5) and (count(2) = 9) and (count(3) = 5) and (count(4) = 1) and bool(count(5))));
end if;
if bool(reset) then
count(5) <= to_unsigned(0, 4);
pm <= '0';
end if;
end if;
end process CLOCK_TFF;
CLOCK_DECODER: process (count(0), count(1), count(2), count(3), count(4), count(5)) is
begin
for i in 0 to 6-1 loop
LED(i) <= unsigned'(((bool(count(i)(0)) and (not bool(count(i)(1))) and (not bool(count(i)(2))) and (not bool(count(i)(3)))) or ((not bool(count(i)(0))) and (not bool(count(i)(1))) and bool(count(i)(2))) or (bool(count(i)(1)) and bool(count(i)(3)))) & ((bool(count(i)(0)) and (not bool(count(i)(1))) and bool(count(i)(2))) or ((not bool(count(i)(0))) and bool(count(i)(1)) and bool(count(i)(2))) or (bool(count(i)(1)) and bool(count(i)(3)))) & (((not bool(count(i)(0))) and bool(count(i)(1)) and (not bool(count(i)(2)))) or (bool(count(i)(2)) and bool(count(i)(3)))) & ((bool(count(i)(0)) and (not bool(count(i)(1))) and (not bool(count(i)(2))) and (not bool(count(i)(3)))) or (bool(count(i)(0)) and bool(count(i)(1)) and bool(count(i)(2))) or ((not bool(count(i)(0))) and (not bool(count(i)(1))) and bool(count(i)(2)))) & (bool(count(i)(0)) or ((not bool(count(i)(1))) and bool(count(i)(2)))) & ((bool(count(i)(0)) and (not bool(count(i)(2))) and (not bool(count(i)(3)))) or (bool(count(i)(0)) and bool(count(i)(1))) or (bool(count(i)(1)) and (not bool(count(i)(2))))) & ((bool(count(i)(0)) and bool(count(i)(1)) and bool(count(i)(2))) or ((not bool(count(i)(1))) and (not bool(count(i)(2))) and (not bool(count(i)(3))))));
end loop;
if (not bool(count(5))) then
LED(5) <= to_unsigned(127, 7);
end if;
end process CLOCK_DECODER;
end architecture MyHDL;
|
gpl-3.0
|
f6dab84cd58e44ba87d348b305c4b00e
| 0.54768 | 2.711706 | false | false | false | false |
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/ComparadorFinal_inst.vhd
| 1 | 202 |
ComparadorFinal_inst : ComparadorFinal PORT MAP (
clken => clken_sig,
clock => clock_sig,
dataa => dataa_sig,
datab => datab_sig,
AeB => AeB_sig,
AgB => AgB_sig,
AlB => AlB_sig
);
|
mit
|
4cf220d9efde64235e18670a2e5f4608
| 0.594059 | 2.623377 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_INTEGRATED_RAMROUTE/key_schedule.vhd
| 1 | 1,850 |
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
r : in std_logic_vector(7 downto 0);
-- we don't need k_2 here because of the way we schedule k(r) in the simon component
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal seqC : std_logic_vector(31 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
-- 0xFFFFFFFFFFFFFFFC xor sequence[(r-4) % 62]
-- TODO: 1-bit latch for seqC(0) is used, not recommended...
seqC <= ("1111111111111111111111111111110" & sequence((to_integer(unsigned(r)) - 4) mod 62)) when (to_integer(unsigned(r)) > 3) else ("11111111111111111111111111111100");
-- tmp = K[3] >> 3
op_3_s <= std_logic_vector(rotate_right(unsigned(k_3), 3));
-- tmp = tmp xor k[1]
op_xor_0 <= (op_3_s xor k_1);
-- tmp >> 1
op_1_s <= std_logic_vector(rotate_right(unsigned(op_xor_0), 1));
-- Original NSA specification lists ~K[0] ^ 3 but this can be rewritten to K[0] ^ ((1 << word_size)-4) where the latter can be stored as a constant for speed
subkey_out <= k_0 when (to_integer(unsigned(r)) < 4) else (op_1_s xor op_xor_0 xor k_0 xor seqC);
end Behavioral;
|
gpl-2.0
|
9187ef984f4ce37ce54b8aa864d18295
| 0.655135 | 3.022876 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task2/uart_receive.vhd
| 1 | 3,562 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:03:34 10/01/2013
-- Design Name:
-- Module Name: uart_receive - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_receive is
port(
rst_i : in std_logic;
clk_i : in std_logic;
Top16_i : in std_logic;
TopRx_i : in std_logic;
Dout_o : out std_logic_vector(7 downto 0);
ClrDiv_o: out std_logic;
Recvd : out std_logic;
Rx_i : in std_logic
);
end uart_receive;
architecture Behavioral of uart_receive is
type state_type is (idle, start_rx, edge_rx, shift_rx, stop_rx, rxovf);
--constant NDbits : std_logic_vector(2 downto 0) :=8;
signal RxFSM : state_type;
signal Rx_Reg : std_logic_vector(7 downto 0);
signal RxBitCnt : integer;
signal RxRdyi : std_logic;
signal ClrDiv : std_logic;
signal RxErr : std_logic;
begin
-- ------------------------
-- RECEIVE State Machine
-- ------------------------
Rx_FSM: process (rst_i, clk_i)
begin
if rst_i='1' then
Rx_Reg <= (others => '0');
Dout_o <= (others => '0');
RxBitCnt <= 0;
Recvd <= '0';
RxFSM <= Idle;
elsif rising_edge(clk_i) then
case RxFSM is
when Idle =>
Recvd <= '0';
if Top16_i = '1' and Rx_i = '0' then
RxFSM <= Start_Rx;
RxBitCnt <= 0;
end if;
when Start_Rx =>
if TopRx_i = '1' then
if Rx_i = '1' then
RxFSM <= RxOVF;
else
RxFSM <= Edge_Rx;
end if;
end if;
when Edge_Rx =>
if TopRx_i = '1' then
if RxBitCnt = 8 then
RxFSM <= Stop_Rx;
else
RxFSM <= Shift_Rx;
end if;
end if;
when Shift_Rx =>
if TopRx_i = '1' then
RxFSM <= Edge_Rx;
Rx_Reg(RxBitCnt) <= Rx_i;
RxBitCnt <= RxBitCnt + 1;
end if;
when Stop_Rx =>
if TopRx_i = '1' then
RxFSM <= Idle;
Dout_o <= Rx_Reg;
Recvd <= '1';
end if;
when RxOVF =>
if Rx_i = '1' then
RxFSM <= Idle;
end if;
end case;
end if;
end process Rx_FSM;
ClrDiv_o <= ClrDiv;
RxRdyi <= '1' when RxFSM = Idle else '0';
RxErr <= '1' when RxFSM = RxOVF else '0';
ClrDiv <= '1' when RxFSM = idle and Top16_i = '1' and Rx_i = '0' else '0';
end Behavioral;
|
mit
|
3ae2abd0b7910e53f03aae6eaa9eac35
| 0.429815 | 4.200472 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
cmos_sensor_input/hdl/cmos_sensor_input_synchronizer.vhd
| 5 | 2,616 |
library ieee;
use ieee.std_logic_1164.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_synchronizer is
generic(
PIX_DEPTH : positive;
SAMPLE_EDGE : string
);
port(
clk : in std_logic;
reset : in std_logic;
-- cmos sensor
frame_valid_in : in std_logic;
line_valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- sampler
frame_valid_out : out std_logic;
line_valid_out : out std_logic;
data_out : out std_logic_vector(PIX_DEPTH - 1 downto 0)
);
end entity cmos_sensor_input_synchronizer;
architecture rtl of cmos_sensor_input_synchronizer is
signal reg_frame_valid_in : std_logic;
signal reg_line_valid_in : std_logic;
signal reg_data_in : std_logic_vector(data_in'range);
-- registered outputs
signal reg_frame_valid_out : std_logic;
signal reg_line_valid_out : std_logic;
signal reg_data_out : std_logic_vector(data_out'range);
begin
-- registered outputs
frame_valid_out <= reg_frame_valid_out;
line_valid_out <= reg_line_valid_out;
data_out <= reg_data_out;
process(clk, reset)
begin
if SAMPLE_EDGE = "RISING" then
if reset = '1' then
reg_frame_valid_in <= '0';
reg_line_valid_in <= '0';
reg_data_in <= (others => '0');
elsif rising_edge(clk) then
reg_frame_valid_in <= frame_valid_in;
reg_line_valid_in <= line_valid_in;
reg_data_in <= data_in;
end if;
elsif SAMPLE_EDGE = "FALLING" then
if reset = '1' then
reg_frame_valid_in <= '0';
reg_line_valid_in <= '0';
reg_data_in <= (others => '0');
elsif falling_edge(clk) then
reg_frame_valid_in <= frame_valid_in;
reg_line_valid_in <= line_valid_in;
reg_data_in <= data_in;
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
reg_frame_valid_out <= '0';
reg_line_valid_out <= '0';
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
reg_frame_valid_out <= reg_frame_valid_in;
reg_line_valid_out <= reg_line_valid_in;
reg_data_out <= reg_data_in;
end if;
end process;
end architecture rtl;
|
unlicense
|
10c3918cce65b77b3a97f3da25a2e1ba
| 0.518349 | 3.544715 | false | false | false | false |
twasiluk/hdmilight
|
fpga/avr/opc_fetch.vhd
| 2 | 7,140 |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: opc_fetch - Behavioral
-- Create Date: 13:00:44 10/30/2009
-- Description: the opcode fetch stage of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
entity opc_fetch is
port ( I_CLK : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_LOAD_PC : in std_logic;
I_NEW_PC : in std_logic_vector(15 downto 0);
I_PM_ADR : in std_logic_vector(15 downto 0);
I_SKIP : in std_logic;
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0);
Q_T0 : out std_logic);
end opc_fetch;
architecture Behavioral of opc_fetch is
component prog_mem
port ( I_CLK : in std_logic;
I_WAIT : in std_logic;
I_PC : in std_logic_vector (15 downto 0);
I_PM_ADR : in std_logic_vector (15 downto 0);
Q_OPC : out std_logic_vector (31 downto 0);
Q_PC : out std_logic_vector (15 downto 0);
Q_PM_DOUT : out std_logic_vector ( 7 downto 0));
end component;
signal P_OPC : std_logic_vector(31 downto 0);
signal P_PC : std_logic_vector(15 downto 0);
signal L_INVALIDATE : std_logic;
signal L_LONG_OP : std_logic;
signal L_NEXT_PC : std_logic_vector(15 downto 0);
signal L_OPC_1_0123 : std_logic;
signal L_OPC_8A_014589CD: std_logic;
signal L_OPC_9_01 : std_logic;
signal L_OPC_9_5_01_8 : std_logic;
signal L_OPC_9_5_CD_8 : std_logic;
signal L_OPC_9_9B : std_logic;
signal L_OPC_F_CDEF : std_logic;
signal L_PC : std_logic_vector(15 downto 0);
signal L_T0 : std_logic;
signal L_WAIT : std_logic;
begin
pmem : prog_mem
port map( I_CLK => I_CLK,
I_WAIT => L_WAIT,
I_PC => L_NEXT_PC,
I_PM_ADR => I_PM_ADR,
Q_OPC => P_OPC,
Q_PC => P_PC,
Q_PM_DOUT => Q_PM_DOUT);
lpc: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
L_PC <= L_NEXT_PC;
L_T0 <= not L_WAIT;
end if;
end process;
L_NEXT_PC <= X"0000" when (I_CLR = '1')
else L_PC when (L_WAIT = '1')
else I_NEW_PC when (I_LOAD_PC = '1')
else L_PC + X"0002" when (L_LONG_OP = '1')
else L_PC + X"0001";
-- Two word opcodes:
--
-- 9 3210
-- 1001 000d dddd 0000 kkkk kkkk kkkk kkkk - LDS
-- 1001 001d dddd 0000 kkkk kkkk kkkk kkkk - SDS
-- 1001 010k kkkk 110k kkkk kkkk kkkk kkkk - JMP
-- 1001 010k kkkk 111k kkkk kkkk kkkk kkkk - CALL
--
L_LONG_OP <= '1' when (((P_OPC(15 downto 9) = "1001010") and
(P_OPC( 3 downto 2) = "11")) -- JMP, CALL
or ((P_OPC(15 downto 10) = "100100") and
(P_OPC( 3 downto 0) = "0000"))) -- LDS, STS
else '0';
----------------------------------
-- Two cycle opcodes... --
----------------------------------
-------------------------------------------------
-- 0001 00rd dddd rrrr - CPSE
--
L_OPC_1_0123 <= '1' when (P_OPC(15 downto 10) = "000100" )
else '0';
-------------------------------------------------
-- 10q0 qq0d dddd 1qqq - LDD (Y + q)
-- 10q0 qq0d dddd 0qqq - LDD (Z + q)
--
L_OPC_8A_014589CD <= '1' when ((P_OPC(15 downto 14) = "10" )
and (P_OPC(12) = '0')
and (P_OPC( 9) = '0'))
else '0';
-------------------------------------------------
-- 1001 000d dddd .... - LDS, LD, LPM (ii/iii), ELPM, POP
--
L_OPC_9_01 <= '1' when ( P_OPC(15 downto 9) = "1001000")
else '0';
-------------------------------------------------
-- 1001 0101 0000 1000 - RET
-- 1001 0101 0001 1000 - RETI
--
L_OPC_9_5_01_8 <= '1' when ((P_OPC(15 downto 5) = "10010101000")
and (P_OPC( 3 downto 0) = "1000"))
else '0';
-------------------------------------------------
-- 1001 0101 1100 1000 - LPM (i)
-- 1001 0101 1101 1000 - ELPM
--
L_OPC_9_5_CD_8 <= '1' when ((P_OPC(15 downto 5) = "10010101110")
and (P_OPC( 3 downto 0) = "1000"))
else '0';
-------------------------------------------------
-- 1001 1001 AAAA Abbb - SBIC
-- 1001 1011 AAAA Abbb - SBIS
--
L_OPC_9_9B <= '1' when ((P_OPC(15 downto 10) = "100110")
and (P_OPC(8) = '1'))
else '0';
-------------------------------------------------
-- 1111 110r rrrr 0bbb - SBRC
-- 1111 111r rrrr 0bbb - SBRS
--
L_OPC_F_CDEF <= '1' when ( P_OPC(15 downto 10) = "111111")
else '0';
L_WAIT <= L_T0 and (not L_INVALIDATE)
and (not I_INTVEC(5))
and (L_OPC_1_0123 or -- CPSE
L_OPC_8A_014589CD or -- LDD
L_OPC_9_01 or -- LDS, LD, LPM, POP
L_OPC_9_5_01_8 or -- RET, RETI
L_OPC_9_5_CD_8 or -- LPM, ELPM
L_OPC_9_9B or -- SBIC, SBIS
L_OPC_F_CDEF); -- SBRC, SBRS
L_INVALIDATE <= I_CLR or I_SKIP;
Q_OPC <= X"00000000" when (L_INVALIDATE = '1')
else P_OPC when (I_INTVEC(5) = '0')
else (X"000000" & "00" & I_INTVEC); -- "interrupt opcode"
Q_PC <= P_PC;
Q_T0 <= L_T0;
end Behavioral;
|
gpl-2.0
|
ff93140e53bc232b9ff26d7f2989b558
| 0.428011 | 3.606061 | false | false | false | false |
thelonious/display4
|
debouncer.vhd
| 1 | 1,562 |
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
-- Based on code from:
-- http://www.labbookpages.co.uk/electronics/debounce.html
--
library ieee;
use ieee.std_logic_1164.all;
entity Debouncer is
generic(
CLOCK_FREQUENCY: positive := 32_000_000;
SAMPLE_FREQUENCY: positive := 2000; -- 500us
SAMPLE_COUNT: positive := 20
);
port(
clock: in std_logic;
reset: in std_logic;
d_in: in std_logic;
d_out: out std_logic
);
end Debouncer;
architecture behavioral of Debouncer is
component Timer is
generic(
CLOCK_FREQUENCY: positive;
TIMER_FREQUENCY: positive
);
port(
clock: in std_logic;
reset: in std_logic;
tick: out std_logic
);
end component;
signal sample_tick : std_logic;
signal sync : std_logic_vector(1 downto 0);
signal sample_counter : integer range 0 to SAMPLE_COUNT;
begin
sample_clock: Timer
generic map(
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMER_FREQUENCY => SAMPLE_FREQUENCY
)
port map(
clock => clock,
reset => reset,
tick => sample_tick
);
debounce: process(clock)
begin
if clock'event and clock = '1' then
if reset = '1' then
sync <= (others => '0');
sample_counter <= 0;
d_out <= '0';
else
sync <= sync(0) & d_in;
if sync(1) = '0' then
sample_counter <= 0;
d_out <= '0';
elsif sample_tick = '1' then
if sample_counter = SAMPLE_COUNT then
d_out <= '1';
else
sample_counter <= sample_counter + 1;
end if;
end if;
end if;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
b9637a8ffd65b21b5913e4d8be742592
| 0.638924 | 3.021277 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/enable.vhd
| 1 | 1,248 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tb_package.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity enable_gen is
Port ( command_i : in command_rec;
enable_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
end enable_gen;
architecture Behavioral of enable_gen is
signal s_enable : std_logic:='0';
signal s_done_o : std_logic;
begin
done_o(0) <= 'Z';
done_o(1) <= 'Z';
done_o(2) <= 'Z';
done_o(3) <= 'Z';
done_o(4) <= 'Z';
done_o(5) <= s_done_o;
done_o(6) <= 'Z';
enable_o <= s_enable;
p_main: process
variable value1 : string(1 to 8);
begin
s_done_o <= '0';
wait on command_i;
if command_i.gen_number=5 then
if command_i.mnemonic(1 to 6)="enable" then
if command_i.value1(8)='1' then
s_enable <= '1';
else
s_enable <= '0';
end if;
elsif command_i.mnemonic(1 to 4)="stop" then
-- start <= false;
end if;
s_done_o <= '1';
wait on s_done_o;
end if;
end process p_main;
end Behavioral;
|
mit
|
ec5dd85745b9ddb355fad02ce11c2cc9
| 0.611378 | 2.666667 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/tb_package.vhd
| 1 | 5,362 |
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package tb_package is
constant gen_number : integer:= 6;
constant gen_filename : string:= "/home/notti/uni/schaltungstech_vert/Assignement/Task1/testcase";
constant mc_width : integer:= 31;
type command_rec is record
gen_number : integer;
Mnemonic : string (1 to 10);
value1 : string (1 to 8);
value2 : string (1 to 8);
value3 : string (1 to 8);
value4 : string (1 to 8);
value5 : string (1 to 8);
value6 : string (1 to 8);
trans : bit;
end record;
function string_to_integer (string_in:string) return integer;
function string_to_time (string_in:string) return time;
function string_to_stdlogicvector (string_in : string; width : natural) return std_logic_vector;
function stdlogicvector_to_hexstring (vector_in:std_logic_vector) return string;
end tb_package;
package body tb_package is
function string_to_integer (string_in:string) return integer is
variable value : integer := 0;
variable temp : integer := 0;
begin
for i in 1 to string_in'length loop
case string_in(i) is
when '0' => value :=0;
when '1' => value :=1;
when '2' => value :=2;
when '3' => value :=3;
when '4' => value :=4;
when '5' => value :=5;
when '6' => value :=6;
when '7' => value :=7;
when '8' => value :=8;
when '9' => value :=9;
when 'A' => value :=10;
when 'a' => value :=10;
when 'B' => value :=11;
when 'b' => value :=11;
when 'C' => value :=12;
when 'c' => value :=12;
when 'D' => value :=13;
when 'd' => value :=13;
when 'E' => value :=14;
when 'e' => value :=14;
when 'F' => value :=15;
when 'f' => value :=15;
when others => report "Integer not recognized";
end case;
temp:= temp+((16**(string_in'length-i))*value);
end loop;
return temp;
end;
function string_to_time (string_in:string) return time is
variable temp : time;
variable temp0 : integer:=0;
variable value : integer:=0;
variable value1: integer:=0;
variable value2: integer:=0;
begin
for i in 1 to string_in'length-2 loop
case string_in(i) is
when '0' => value :=0;
when '1' => value :=1;
when '2' => value :=2;
when '3' => value :=3;
when '4' => value :=4;
when '5' => value :=5;
when '6' => value :=6;
when '7' => value :=7;
when '8' => value :=8;
when '9' => value :=9;
when others => report "Integer Time not recognized";
end case;
temp0:=temp0+((10**(string_in'length-i-2))*value);
end loop;
value1:= string_in'length-1;
value2:= string_in'length;
case string_in(value1) is
when 'f' => temp := temp0*(1 fs);
when 'p' => temp := temp0*(1 ps);
when 'n' => temp := temp0*(1 ns);
when 'u' => temp := temp0*(1 us);
when 'm' => temp := temp0*(1 ms);
when others => report "Time base not recognized";
end case;
return temp;
end;
function string_to_stdlogicvector (string_in:string; width:natural) return std_logic_vector is
variable temp : std_logic_vector(width-1 downto 0);
variable value: std_logic_vector(3 downto 0);
variable j : natural;
begin
temp:=(others =>'0');
for i in (width/4) downto 1 loop
j:=j+1;
case string_in(j) is
when'0' => value:="0000";
when'1' => value:="0001";
when'2' => value:="0010";
when'3' => value:="0011";
when'4' => value:="0100";
when'5' => value:="0101";
when'6' => value:="0110";
when'7' => value:="0111";
when'8' => value:="1000";
when'9' => value:="1001";
when'A' => value:="1010";
when'a' => value:="1010";
when'B' => value:="1011";
when'b' => value:="1011";
when'C' => value:="1100";
when'c' => value:="1100";
when'D' => value:="1101";
when'd' => value:="1101";
when'E' => value:="1110";
when'e' => value:="1110";
when'F' => value:="1111";
when'f' => value:="1111";
when others => report "wrong stdlogicvector representation";
end case;
temp((((i-1)*4)+3) downto (i-1)*4) := value;
end loop;
return temp;
end;
function stdlogicvector_to_hexstring (vector_in:std_logic_vector) return string is
variable temp : string((vector_in'length/4) downto 1);
variable char : string(1 downto 1);
variable help_vector : std_logic_vector(3 downto 0);
begin
for i in (vector_in'length/4) downto 1 loop
help_vector := vector_in((i*4)-1 downto ((i*4)-4));
case help_vector is
when "0000" => char :="0";
when "0001" => char :="1";
when "0010" => char :="2";
when "0011" => char :="3";
when "0100" => char :="4";
when "0101" => char :="5";
when "0110" => char :="6";
when "0111" => char :="7";
when "1000" => char :="8";
when "1001" => char :="9";
when "1010" => char :="A";
when "1011" => char :="B";
when "1100" => char :="C";
when "1101" => char :="D";
when "1110" => char :="E";
when "1111" => char :="F";
when others => report "hexstring not recognized";
end case;
temp(i downto i):=char;
end loop;
return temp;
end;
end tb_package;
|
mit
|
32b0010d0af37a42e3103741f1dffe78
| 0.556322 | 2.967349 | false | false | false | false |
samvartaka/simon_vhdl
|
MIXED_ROUND_PIPELINING/round_f.vhd
| 1 | 2,097 |
-- SIMON 64/128
-- feistel round function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- v_in: plaintext block
-- v_k: subkey
-- v_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end round_f;
architecture Behavioral of round_f is
signal op_0_s : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal op_2_s : std_logic_vector(31 downto 0);
signal stage_0_out_s : std_logic_vector(31 downto 0);
signal stage_1_out_s : std_logic_vector(31 downto 0);
signal v_l : std_logic_vector(31 downto 0);
signal v_r : std_logic_vector(31 downto 0);
signal v_k : std_logic_vector(31 downto 0);
component phi is
port(x_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0));
end component;
component gamma is
port(x_in : in std_logic_vector(31 downto 0);
y_in : in std_logic_vector(31 downto 0);
x_out : out std_logic_vector(31 downto 0));
end component;
component neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
begin
v_l <= v_in(31 downto 0) when enc = '0' else v_in(63 downto 32);
v_r <= v_in(63 downto 32) when enc = '0' else v_in(31 downto 0);
v_k <= v_k_e when enc = '0' else v_k_d;
PHI_0 : phi port map (v_r, op_0_s);
REG_STAGE_0 : neg_reg_32 port map (clk, rst, op_0_s, stage_0_out_s);
GAMMA_0 : gamma port map (v_l, v_k, op_1_s);
REG_STAGE_1 : neg_reg_32 port map (clk, rst, op_1_s, stage_1_out_s);
GAMMA_1 : gamma port map (stage_0_out_s, stage_1_out_s, op_2_s);
v_out <= (op_2_s & v_r) when enc = '0' else (v_r & op_2_s);
end Behavioral;
|
gpl-2.0
|
6b8d0ee5c19f8be2441f2ddb5acfb7d6
| 0.621364 | 2.62125 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/debounce.vhd
| 1 | 1,318 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity debounce is
generic(
CNT : integer := 1500000; -- 30 ms at 50 MHz
CNT_WDT : integer := 21
);
port(
clk_50 : in std_logic;
input : in std_logic;
output : out std_logic;
riseedge : out std_logic;
falledge : out std_logic
);
end debounce;
architecture behavioural of debounce is
signal scnt : unsigned(CNT_WDT-1 downto 0) := (others => '0');
signal values : std_logic_vector(3 downto 0) := (others => '0');
signal io_out : std_logic;
signal io_out_dly : std_logic;
begin
io_out <= '1' when values(2 downto 0) = "111" else
'0';
output <= io_out;
riseedge <= io_out and (not io_out_dly);
falledge <= (not io_out) and io_out_dly;
io_dly: process(clk_50)
begin
if rising_edge(clk_50) then
io_out_dly <= io_out;
end if;
end process;
shift_in: process(clk_50, scnt)
begin
if rising_edge(clk_50) and scnt = CNT then
values <= input & values(3 downto 1);
end if;
end process;
delay_cnt : process(clk_50)
begin
if rising_edge(clk_50) then
if scnt = CNT then
scnt <= (others=>'0');
else
scnt <= scnt + 1;
end if;
end if;
end process;
end behavioural;
|
mit
|
707766cc76d2f60c610e9d1760e59e26
| 0.579666 | 2.988662 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_INTEGRATED_CACHEROUTE/simon.vhd
| 1 | 4,393 |
-- SIMON 64/128
-- Simon core component
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component round_f is
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end component;
component key_schedule is
port (r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end component;
component ram is
port (data_in : in std_logic_vector(31 downto 0);
rw : in std_logic;
clk : in std_logic;
address : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal r_s : std_logic_vector(7 downto 0); -- round index
signal key_s : key_t; -- intermediate key (in words)
signal subkey_out_s : std_logic_vector(31 downto 0); -- round key
signal v_in_s : std_logic_vector(63 downto 0); -- intermediate 'plaintext'
signal v_out_s : std_logic_vector(63 downto 0); -- intermediate 'ciphertext'
signal ram_rw : std_logic;
signal ram_data_out : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (r_s, key_s(0), key_s(1), key_s(3), subkey_out_s);
ROUND_F_0 : round_f port map (v_in_s, key_s(0), v_out_s);
RAM_0 : ram port map (key_s(0), ram_rw, clk, r_s, ram_data_out);
-- SIMON round index regulation
pr_r : process(clk, rst)
begin
if rising_edge(clk) then
-- initialization clock
if rst = '1' then
if enc = '0' then
if r_s = X"00" then
r_s <= X"01";
else
r_s <= (others => '0');
end if;
else
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
-- running clock
else
if enc = '0' then
if r_s /= X"2B" then
r_s <= std_logic_vector(unsigned(r_s) + 1);
else
-- in preparation for subsequent decryption
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
else
if r_s /= X"00" then
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
end if;
end if;
end if;
end process;
-- SIMON key cache rotation
pr_ks : process(clk, rst, key_s, key, ram_data_out, subkey_out_s)
begin
if rising_edge(clk) then
if enc = '0' then
if rst = '1' then
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
else
-- final iteration is just to write final round key to ram
if (r_s /= X"2B") then
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out_s;
end if;
end if;
else
key_s(0) <= ram_data_out;
end if;
end if;
end process;
-- SIMON Core
pr_smn : process(clk, rst, enc, r_s, block_in, v_in_s, v_out_s, ram_rw)
begin
if rising_edge(clk) then
-- initalize
if rst = '1' then
if enc = '0' then
v_in_s <= block_in;
-- write every round key to RAM during encryption
-- so that encryption also functions as pre-expansion for decryption
ram_rw <= '1';
else
-- swap blocks for decryption
v_in_s <= block_in(31 downto 0) & block_in(63 downto 32);
ram_rw <= '0';
end if;
-- run
else
if enc = '0' then
-- final iteration is just to write final round key to ram
if (r_s /= X"2B") then
v_in_s <= v_out_s;
else
ram_rw <= '0';
end if;
else
v_in_s <= v_out_s;
end if;
end if;
end if;
end process;
block_out <= v_out_s when (enc = '0') else v_out_s(31 downto 0) & v_out_s(63 downto 32);
end Behavioral;
|
gpl-2.0
|
aad58323004e86d21fc2ee3111876b5e
| 0.584566 | 2.764632 | false | false | false | false |
samvartaka/simon_vhdl
|
MIXED_ROUND_PIPELINING/tb_neg_reg_32.vhd
| 3 | 1,825 |
-- SIMON 64/128
-- feistel round function operation phi test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_neg_reg_32 IS
END tb_neg_reg_32;
ARCHITECTURE behavior OF tb_neg_reg_32 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal data_in : std_logic_vector(31 downto 0) := (others => '0'); -- input
--Outputs
signal data_out : std_logic_vector(31 downto 0); -- output
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: neg_reg_32 PORT MAP (
clk => clk,
rst => rst,
data_in => data_in,
data_out => data_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
rst <= '1';
wait for clk_period;
assert data_out = X"00000000"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
rst <= '0';
data_in <= X"CAFECAFE";
wait for clk_period;
assert data_out = X"CAFECAFE"
report "NEG_REG_32 ERROR (r_1)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
f3ecb8fa19deaae4519ec2b47e406ceb
| 0.606575 | 3.230088 | false | true | false | false |
thelonious/display4
|
display_counter.vhd
| 1 | 4,322 |
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DisplayCounter is
port(
-- main clock
clock: in std_logic;
-- rotary push button
A, B, PB: in std_logic;
-- 4-digit 7-segment display
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(3 downto 0)
);
end DisplayCounter;
architecture Behavioral of DisplayCounter is
-- component for rotary-only support of rotary switch
component Rotary is
port(
clock: in std_logic;
A: in std_logic;
B: in std_logic;
inc: out std_logic;
dec: out std_logic
);
end component;
-- component to display 4 7-segment digits
component Display4 is
generic(
DIGIT_COUNT: positive
);
port(
clock: in std_logic;
data_write_enable: in std_logic;
data: in std_logic_vector(DIGIT_COUNT * 4 - 1 downto 0);
dps: in std_logic_vector(DIGIT_COUNT - 1 downto 0);
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(DIGIT_COUNT - 1 downto 0)
);
end component;
-- component to debounce rotary push button
component Debouncer is
port(
clock: in std_logic;
reset: in std_logic;
d_in: in std_logic;
d_out: out std_logic
);
end component;
-- individual digit data and an aggregate of those values
subtype digitType is std_logic_vector(3 downto 0);
type digitTypes is array(0 to 3) of digitType;
signal digits: digitTypes;
signal display_data: std_logic_vector(15 downto 0);
-- signals from rotary indicating rotation direction
signal up, down: std_logic;
-- signals to write current display data
signal enable_write: std_logic := '1';
signal active_digit: std_logic_vector(3 downto 0) := (others => '0');
-- state tracking to detect push button edges
signal last_debounced: std_logic := '0';
signal current_debounced: std_logic := '0';
signal PB_debounced: std_logic := '0';
begin
-- create rotary decoder
r: Rotary
port map(
clock => clock,
A => A,
B => B,
inc => up,
dec => down
);
-- create 4-digit display
d4: Display4
generic map(
DIGIT_COUNT => 4
)
port map(
clock => clock,
data_write_enable => enable_write,
data => display_data,
dps => active_digit,
segments => segments,
dp => dp,
sel => sel
);
-- create button debouncer
db: Debouncer
port map(
clock => clock,
reset => PB,
d_in => not PB,
d_out => PB_debounced
);
-- concatenate individual digits into a single 16-bit value
update_display: process(clock, digits)
begin
if clock'event and clock = '1' then
display_data <= digits(0) & digits(1) & digits(2) & digits(3);
end if;
end process;
-- update current digit based on rotary output
-- update active digit which turns on that digits decimal point. Normally,
-- I would separate the logic for rotary and the push button into separate
-- processes, but since both require activation of enable_write, I decided
-- to combine both into a single process
update_counter: process(clock, up, down, PB, active_digit)
variable digit_index: integer range 0 to 3 := 0;
begin
if clock'event and clock = '1' then
-- shift last value and current value for edge detection
last_debounced <= current_debounced;
current_debounced <= PB_debounced;
-- handle increment/decrement if a digit is active; otherwise,
-- handle possible postive edge of push button
if down = '1' and active_digit /= "0000" then
digits(digit_index) <= digits(digit_index) - 1;
enable_write <= '1';
elsif up = '1' and active_digit /= "0000" then
digits(digit_index) <= digits(digit_index) + 1;
enable_write <= '1';
elsif last_debounced = '0' and current_debounced = '1' then
case active_digit is
when "0000" => active_digit <= "0001"; digit_index := 0;
when "0001" => active_digit <= "0010"; digit_index := 1;
when "0010" => active_digit <= "0100"; digit_index := 2;
when "0100" => active_digit <= "1000"; digit_index := 3;
when "1000" => active_digit <= "0000"; digit_index := 0;
when others => active_digit <= "0000"; digit_index := 0;
end case;
enable_write <= '1';
else
enable_write <= '0';
end if;
end if;
end process;
end Behavioral;
|
bsd-3-clause
|
0ec3c0d51a31fb6bfcaecfb0f818732f
| 0.66335 | 3.201481 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/tb_rotkey.vhd
| 1 | 1,629 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.math_real.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_rotkey is
end tb_rotkey;
architecture behav of tb_rotkey is
signal clk_50 : std_logic := '0';
signal rotA : std_logic := '0';
signal rotB : std_logic := '0';
signal rotPush : std_logic := '0';
signal rotRightEvent : std_logic := '0';
signal rotLeftEvent : std_logic := '0';
signal rotPushEvent : std_logic := '0';
begin
process
begin
clk_50 <= '1', '0' after 10 ns;
wait for 20 ns;
end process;
process
begin
wait for 1400 ns;
rotPush <= '1';
wait for 1400 ns;
rotPush <= '0';
wait for 1400 ns;
rotA <= '1';
wait for 1400 ns;
rotB <= '1';
wait for 1400 ns;
rotA <= '0';
wait for 1400 ns;
rotB <= '0';
wait for 2000 ns;
rotB <= '1';
wait for 1400 ns;
rotA <= '1';
wait for 1400 ns;
rotB <= '0';
wait for 1400 ns;
rotA <= '0';
wait for 3000 ns;
assert false report "done" severity failure;
wait;
end process;
rotkey: entity work.rotkey
generic map(
CNT => 15 -- 1500000 = 30 ms at 50 MHz; hier 300ns
)
port map(
clk_50 => clk_50,
rotA => rotA,
rotB => rotB,
rotPush => rotPush,
rotRightEvent => rotRightEvent,
rotLeftEvent => rotLeftEvent,
rotPushEvent => rotPushEvent
);
end behav;
|
mit
|
2311f64514739d39fa17edb3cde1f6d1
| 0.517495 | 3.644295 | false | false | false | false |
thelonious/display4
|
display_4.vhd
| 1 | 3,786 |
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Display4 is
generic(
CLOCK_FREQUENCY: positive := 32_000_000;
DIGIT_COUNT: positive := 4
);
port(
-- main clock
clock: in std_logic;
-- digit data, decimal point input, and write enable flag
data_write_enable: in std_logic;
data: in std_logic_vector(DIGIT_COUNT * 4 - 1 downto 0);
dps: in std_logic_vector(DIGIT_COUNT - 1 downto 0);
-- display and selection output
segments: out std_logic_vector(6 downto 0);
dp: out std_logic;
sel: out std_logic_vector(DIGIT_COUNT - 1 downto 0)
);
end Display4;
architecture behavioral of Display4 is
-- component to decode nibble to 7-segment display
component SevenSegment is
port(
clock: in std_logic;
num: in std_logic_vector(3 downto 0);
segments: out std_logic_vector(6 downto 0)
);
end component;
-- timer component that fires at a regular interval
component Timer is
generic(
CLOCK_FREQUENCY: positive;
TIMER_FREQUENCY: positive
);
port(
clock: in std_logic;
reset: in std_logic;
tick: out std_logic
);
end component;
-- registers for digit data and decimal points
signal digit_data_register: std_logic_vector(DIGIT_COUNT * 4 - 1 downto 0) := (others => '0');
signal decimal_points_register: std_logic_vector(DIGIT_COUNT - 1 downto 0) := (others => '0');
-- signal indicating when the timer has expired
signal advance_tick: std_logic := '0';
-- the current digit index and the digit's value
signal current_value: std_logic_vector(3 downto 0) := "0000";
signal digit_index: integer range 0 to DIGIT_COUNT - 1;
begin
-- decode nibble to 7-segment display
ss: SevenSegment
port map(
clock => clock,
num => current_value,
segments => segments
);
-- timer used to time multiplex the digits in the display
advance_timer: Timer
generic map(
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMER_FREQUENCY => 1000 * (DIGIT_COUNT + 1)
)
port map(
clock => clock,
reset => '0',
tick => advance_tick
);
-- possibly update digit data and decimal point registers
set_registers: process(clock, data_write_enable)
begin
if clock'event and clock = '1' then
if data_write_enable = '1' then
digit_data_register <= data;
decimal_points_register <= dps;
end if;
end if;
end process;
-- update currently active digit
update_digit_index: process(clock)
begin
if clock'event and clock = '1' then
if advance_tick = '1' then
digit_index <= digit_index + 1;
end if;
end if;
end process;
-- update current value based on current digit index
update_current_value: process(clock, digit_index)
variable top: integer;
begin
if clock'event and clock = '1' then
-- digits are numbered left-to-right, but we need them right-to-left
-- calculate segment offsets based on (corrected) digit index
top := DIGIT_COUNT * ((DIGIT_COUNT - 1) - digit_index) + 3;
-- grab slice for the current digit
current_value <= digit_data_register(top downto top - 3);
end if;
end process;
-- activate current digit on display
activate_digit: process(clock, digit_index)
begin
-- TODO: use generic mux which will probably require an enable signal as well
if clock'event and clock = '1' then
case digit_index is
when 0 => sel <= "0001";
when 1 => sel <= "0010";
when 2 => sel <= "0100";
when 3 => sel <= "1000";
when others => sel <= "0000";
end case;
end if;
end process;
-- activate decimal point for current digit
activate_decimal_point: process(clock, digit_index)
begin
if clock'event and clock = '1' then
dp <= not decimal_points_register(digit_index);
end if;
end process;
end behavioral;
|
bsd-3-clause
|
1156160bf833036bd4d71456b59e4a4b
| 0.682515 | 3.277922 | false | false | false | false |
twasiluk/hdmilight
|
fpga/DCM32to16.vhd
| 3 | 3,045 |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 11.1
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM32to16.vhd
-- /___/ /\ Timestamp : 07/29/2010 14:42:37
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16.xaw C:\dbdev\My Dropbox\GadgetFactory\AVR8\svn\trunk\ipcore_dir\DCM32to16
--Design Name: DCM32to16
--Device: xc3s250e-4vq100
--
-- Module DCM32to16
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.43 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM32to16 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end DCM32to16;
architecture BEHAVIORAL of DCM32to16 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
gpl-2.0
|
f11c0e4ff955f566285d567c5d186a09
| 0.485386 | 3.66426 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_INTEGRATED_CACHEROUTE/tb_keyschedule.vhd
| 3 | 11,886 |
-- SIMON 64/128
-- key schedule test bench
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.NUMERIC_STD.ALL;
ENTITY tb_keyschedule IS
END tb_keyschedule;
ARCHITECTURE behavior OF tb_keyschedule IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT key_schedule
port (
r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal r : std_logic_vector(7 downto 0); -- round index
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- k0..3
--Outputs
signal subkey_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal clk_generator_finish : STD_LOGIC := '0';
signal test_bench_finish : STD_LOGIC := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: key_schedule PORT MAP (
r => r,
k_0 => key_s(0),
k_1 => key_s(1),
k_3 => key_s(3),
subkey_out => subkey_out
);
-- Clock process definitions
clock : process
begin
while ( clk_generator_finish /= '1') loop
clk <= not clk;
wait for clk_period/2;
end loop;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + 10*clk_period;
-- SIMON 64/128 test vectors
key_s(0) <= X"03020100";
key_s(1) <= X"0b0a0908";
key_s(2) <= X"13121110";
key_s(3) <= X"1b1a1918";
r <= X"00";
wait for clk_period;
assert subkey_out = X"70a011c3"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"b770ec49"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"57e3e835"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"d397bc42"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"94dcf81f"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"bf4b5f18"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"8e5dabb9"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"dbf4a863"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"cd0c28fc"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"5cb69911"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"79f112a5"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"77205863"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"99880c12"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"1ce97c58"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"c8ed2145"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"b800dbb8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"e86a2756"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"7c06d4dd"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"ab52df0a"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"247f66a8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"53587ca6"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"d25c13f1"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"4583b64b"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"7d9c960d"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"efbfc2f3"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"89ed8513"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"308dfc4e"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"bf1a2a36"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"e1499d70"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"4ce4d2ff"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"32b7ebef"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"c47505c1"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"d0e929e8"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"8fe484b9"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"42054bee"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"af77bae2"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"18199c02"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"719e3f1c"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"0c1cf793"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out;
r <= std_logic_vector(unsigned(r) + 1);
wait for clk_period;
assert subkey_out = X"15df4696"
report "KEY_SCHEDULE ERROR (k)" severity FAILURE;
test_bench_finish <= '1';
clk_generator_finish <= '1';
wait for clk_period;
wait;
end process;
END;
|
gpl-2.0
|
40818c874f49522f6ece4810c22ce58a
| 0.582618 | 2.401212 | false | false | false | false |
twasiluk/hdmilight
|
fpga/avr/prog_mem.vhd
| 2 | 13,569 |
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: prog_mem - Behavioral
-- Create Date: 14:09:04 10/30/2009
-- Description: the program memory of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-- the content of the program memory.
--
use work.prog_mem_content.all;
entity prog_mem is
port ( I_CLK : in std_logic;
I_WAIT : in std_logic;
I_PC : in std_logic_vector(15 downto 0); -- word address
I_PM_ADR : in std_logic_vector(15 downto 0); -- byte address
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0));
end prog_mem;
architecture Behavioral of prog_mem is
constant zero_256 : bit_vector := X"00000000000000000000000000000000"
& X"00000000000000000000000000000000";
signal M_OPC_E1 : std_logic_vector(15 downto 0);
signal M_OPC_E2 : std_logic_vector(15 downto 0);
signal M_OPC_O1 : std_logic_vector(15 downto 0);
signal M_OPC_O2 : std_logic_vector(15 downto 0);
signal M_PMD_E1 : std_logic_vector(15 downto 0);
signal M_PMD_E2 : std_logic_vector(15 downto 0);
signal M_PMD_O1 : std_logic_vector(15 downto 0);
signal M_PMD_O2 : std_logic_vector(15 downto 0);
signal L_WAIT_N : std_logic;
signal L_PC_0 : std_logic;
signal L_PC_11 : std_logic;
signal L_PC_E : std_logic_vector(10 downto 1);
signal L_PC_O : std_logic_vector(10 downto 1);
signal L_PMD : std_logic_vector(15 downto 0);
signal L_PM_ADR_1_0 : std_logic_vector( 1 downto 0);
signal L_PM_ADR_12 : std_logic;
begin
pe1 : RAMB16_S18_S18
generic map(INIT_00 => p0_00, INIT_01 => p0_01, INIT_02 => p0_02,
INIT_03 => p0_03, INIT_04 => p0_04, INIT_05 => p0_05,
INIT_06 => p0_06, INIT_07 => p0_07, INIT_08 => p0_08,
INIT_09 => p0_09, INIT_0A => p0_0A, INIT_0B => p0_0B,
INIT_0C => p0_0C, INIT_0D => p0_0D, INIT_0E => p0_0E,
INIT_0F => p0_0F,
INIT_10 => p0_10, INIT_11 => p0_11, INIT_12 => p0_12,
INIT_13 => p0_13, INIT_14 => p0_14, INIT_15 => p0_15,
INIT_16 => p0_16, INIT_17 => p0_17, INIT_18 => p0_18,
INIT_19 => p0_19, INIT_1A => p0_1A, INIT_1B => p0_1B,
INIT_1C => p0_1C, INIT_1D => p0_1D, INIT_1E => p0_1E,
INIT_1F => p0_1F,
INIT_20 => p0_20, INIT_21 => p0_21, INIT_22 => p0_22,
INIT_23 => p0_23, INIT_24 => p0_24, INIT_25 => p0_25,
INIT_26 => p0_26, INIT_27 => p0_27, INIT_28 => p0_28,
INIT_29 => p0_29, INIT_2A => p0_2A, INIT_2B => p0_2B,
INIT_2C => p0_2C, INIT_2D => p0_2D, INIT_2E => p0_2E,
INIT_2F => p0_2F,
INIT_30 => p0_30, INIT_31 => p0_31, INIT_32 => p0_32,
INIT_33 => p0_33, INIT_34 => p0_34, INIT_35 => p0_35,
INIT_36 => p0_36, INIT_37 => p0_37, INIT_38 => p0_38,
INIT_39 => p0_39, INIT_3A => p0_3A, INIT_3B => p0_3B,
INIT_3C => p0_3C, INIT_3D => p0_3D, INIT_3E => p0_3E,
INIT_3F => p0_3F)
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E1, DOB => M_PMD_E1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe2 : RAMB16_S18_S18
generic map(INIT_00 => p0_00, INIT_01 => p0_01, INIT_02 => p0_02,
INIT_03 => p0_03, INIT_04 => p0_04, INIT_05 => p0_05,
INIT_06 => p0_06, INIT_07 => p0_07, INIT_08 => p0_08,
INIT_09 => p0_09, INIT_0A => p0_0A, INIT_0B => p0_0B,
INIT_0C => p0_0C, INIT_0D => p0_0D, INIT_0E => p0_0E,
INIT_0F => p0_0F,
INIT_10 => p0_10, INIT_11 => p0_11, INIT_12 => p0_12,
INIT_13 => p0_13, INIT_14 => p0_14, INIT_15 => p0_15,
INIT_16 => p0_16, INIT_17 => p0_17, INIT_18 => p0_18,
INIT_19 => p0_19, INIT_1A => p0_1A, INIT_1B => p0_1B,
INIT_1C => p0_1C, INIT_1D => p0_1D, INIT_1E => p0_1E,
INIT_1F => p0_1F,
INIT_20 => p0_20, INIT_21 => p0_21, INIT_22 => p0_22,
INIT_23 => p0_23, INIT_24 => p0_24, INIT_25 => p0_25,
INIT_26 => p0_26, INIT_27 => p0_27, INIT_28 => p0_28,
INIT_29 => p0_29, INIT_2A => p0_2A, INIT_2B => p0_2B,
INIT_2C => p0_2C, INIT_2D => p0_2D, INIT_2E => p0_2E,
INIT_2F => p0_2F,
INIT_30 => p0_30, INIT_31 => p0_31, INIT_32 => p0_32,
INIT_33 => p0_33, INIT_34 => p0_34, INIT_35 => p0_35,
INIT_36 => p0_36, INIT_37 => p0_37, INIT_38 => p0_38,
INIT_39 => p0_39, INIT_3A => p0_3A, INIT_3B => p0_3B,
INIT_3C => p0_3C, INIT_3D => p0_3D, INIT_3E => p0_3E,
INIT_3F => p0_3F)
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E2, DOB => M_PMD_E2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po1 : RAMB16_S18_S18
generic map(INIT_00 => p1_00, INIT_01 => p1_01, INIT_02 => p1_02,
INIT_03 => p1_03, INIT_04 => p1_04, INIT_05 => p1_05,
INIT_06 => p1_06, INIT_07 => p1_07, INIT_08 => p1_08,
INIT_09 => p1_09, INIT_0A => p1_0A, INIT_0B => p1_0B,
INIT_0C => p1_0C, INIT_0D => p1_0D, INIT_0E => p1_0E,
INIT_0F => p1_0F,
INIT_10 => p1_10, INIT_11 => p1_11, INIT_12 => p1_12,
INIT_13 => p1_13, INIT_14 => p1_14, INIT_15 => p1_15,
INIT_16 => p1_16, INIT_17 => p1_17, INIT_18 => p1_18,
INIT_19 => p1_19, INIT_1A => p1_1A, INIT_1B => p1_1B,
INIT_1C => p1_1C, INIT_1D => p1_1D, INIT_1E => p1_1E,
INIT_1F => p1_1F,
INIT_20 => p1_20, INIT_21 => p1_21, INIT_22 => p1_22,
INIT_23 => p1_23, INIT_24 => p1_24, INIT_25 => p1_25,
INIT_26 => p1_26, INIT_27 => p1_27, INIT_28 => p1_28,
INIT_29 => p1_29, INIT_2A => p1_2A, INIT_2B => p1_2B,
INIT_2C => p1_2C, INIT_2D => p1_2D, INIT_2E => p1_2E,
INIT_2F => p1_2F,
INIT_30 => p1_30, INIT_31 => p1_31, INIT_32 => p1_32,
INIT_33 => p1_33, INIT_34 => p1_34, INIT_35 => p1_35,
INIT_36 => p1_36, INIT_37 => p1_37, INIT_38 => p1_38,
INIT_39 => p1_39, INIT_3A => p1_3A, INIT_3B => p1_3B,
INIT_3C => p1_3C, INIT_3D => p1_3D, INIT_3E => p1_3E,
INIT_3F => p1_3F)
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O1, DOB => M_PMD_O1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po2 : RAMB16_S18_S18
generic map(INIT_00 => p1_00, INIT_01 => p1_01, INIT_02 => p1_02,
INIT_03 => p1_03, INIT_04 => p1_04, INIT_05 => p1_05,
INIT_06 => p1_06, INIT_07 => p1_07, INIT_08 => p1_08,
INIT_09 => p1_09, INIT_0A => p1_0A, INIT_0B => p1_0B,
INIT_0C => p1_0C, INIT_0D => p1_0D, INIT_0E => p1_0E,
INIT_0F => p1_0F,
INIT_10 => p1_10, INIT_11 => p1_11, INIT_12 => p1_12,
INIT_13 => p1_13, INIT_14 => p1_14, INIT_15 => p1_15,
INIT_16 => p1_16, INIT_17 => p1_17, INIT_18 => p1_18,
INIT_19 => p1_19, INIT_1A => p1_1A, INIT_1B => p1_1B,
INIT_1C => p1_1C, INIT_1D => p1_1D, INIT_1E => p1_1E,
INIT_1F => p1_1F,
INIT_20 => p1_20, INIT_21 => p1_21, INIT_22 => p1_22,
INIT_23 => p1_23, INIT_24 => p1_24, INIT_25 => p1_25,
INIT_26 => p1_26, INIT_27 => p1_27, INIT_28 => p1_28,
INIT_29 => p1_29, INIT_2A => p1_2A, INIT_2B => p1_2B,
INIT_2C => p1_2C, INIT_2D => p1_2D, INIT_2E => p1_2E,
INIT_2F => p1_2F,
INIT_30 => p1_30, INIT_31 => p1_31, INIT_32 => p1_32,
INIT_33 => p1_33, INIT_34 => p1_34, INIT_35 => p1_35,
INIT_36 => p1_36, INIT_37 => p1_37, INIT_38 => p1_38,
INIT_39 => p1_39, INIT_3A => p1_3A, INIT_3B => p1_3B,
INIT_3C => p1_3C, INIT_3D => p1_3D, INIT_3E => p1_3E,
INIT_3F => p1_3F)
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O2, DOB => M_PMD_O2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
-- remember I_PC0 and I_PM_ADR for the output mux.
--
pc0: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
Q_PC <= I_PC;
L_PM_ADR_1_0 <= I_PM_ADR(1 downto 0);
L_PM_ADR_12 <= I_PM_ADR(12);
if ((I_WAIT = '0')) then
L_PC_0 <= I_PC(0);
L_PC_11 <= I_PC(11);
end if;
end if;
end process;
L_WAIT_N <= not I_WAIT;
-- we use two memory blocks _E and _O (even and odd).
-- This gives us a quad-port memory so that we can access
-- I_PC, I_PC + 1, and PM simultaneously.
--
-- I_PC and I_PC + 1 are handled by port A of the memory while PM
-- is handled by port B.
--
-- Q_OPC(15 ... 0) shall contain the word addressed by I_PC, while
-- Q_OPC(31 ... 16) shall contain the word addressed by I_PC + 1.
--
-- There are two cases:
--
-- case A: I_PC is even, thus I_PC + 1 is odd
-- case B: I_PC + 1 is odd , thus I_PC is even
--
L_PC_O <= I_PC(10 downto 1);
L_PC_E <= I_PC(10 downto 1) + ("000000000" & I_PC(0));
Q_OPC(15 downto 0) <= M_OPC_E1 when L_PC_11 = '0' and L_PC_0 = '0' else
M_OPC_E2 when L_PC_11 = '1' and L_PC_0 = '0' else
M_OPC_O1 when L_PC_11 = '0' and L_PC_0 = '1' else
M_OPC_O2;
Q_OPC(31 downto 16) <= M_OPC_E1 when L_PC_11 = '0' and L_PC_0 = '1' else
M_OPC_E2 when L_PC_11 = '1' and L_PC_0 = '1' else
M_OPC_O1 when L_PC_11 = '0' and L_PC_0 = '0' else
M_OPC_O2;
--Q_OPC(15 downto 0) <= M_OPC_E when L_PC_0 = '0' else M_OPC_O;
--Q_OPC(31 downto 16) <= M_OPC_E when L_PC_0 = '1' else M_OPC_O;
L_PMD <= M_PMD_E1 when L_PM_ADR_12 = '0' and L_PM_ADR_1_0(1) = '0' else
M_PMD_O1 when L_PM_ADR_12 = '0' and L_PM_ADR_1_0(1) = '1' else
M_PMD_E2 when L_PM_ADR_12 = '1' and L_PM_ADR_1_0(1) = '0' else
M_PMD_O2;
--L_PMD <= M_PMD_E when (L_PM_ADR_1_0(1) = '0') else M_PMD_O;
Q_PM_DOUT <= L_PMD(7 downto 0) when (L_PM_ADR_1_0(0) = '0')
else L_PMD(15 downto 8);
end Behavioral;
|
gpl-2.0
|
39592e98829883644ee932613cb23803
| 0.443069 | 2.783956 | false | false | false | false |
quartushaters/project
|
M1/Part 1/clock_LCD/DE2_CLOCK.vhd
| 1 | 8,104 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- This code displays time in the DE2's LCD Display
-- Key2 resets time
ENTITY DE2_CLOCK IS
PORT(reset, clk_50Mhz : IN STD_LOGIC;
LCD_RS, LCD_E, LCD_ON, RESET_LED, SEC_LED : OUT STD_LOGIC;
LCD_RW : BUFFER STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END DE2_CLOCK;
ARCHITECTURE a OF DE2_CLOCK IS
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, WRITE_CHAR1,
WRITE_CHAR2,WRITE_CHAR3,WRITE_CHAR4,WRITE_CHAR5,WRITE_CHAR6,WRITE_CHAR7,
WRITE_CHAR8, WRITE_CHAR9, WRITE_CHAR10, RETURN_HOME, TOGGLE_E, RESET1, RESET2,
RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL DATA_BUS_VALUE: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL CLK_COUNT_10HZ: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL BCD_SECD0,BCD_SECD1,BCD_MIND0,BCD_MIND1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BCD_HRD0,BCD_HRD1,BCD_TSEC: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLK_400HZ, CLK_10HZ : STD_LOGIC;
BEGIN
LCD_ON <= '1';
RESET_LED <= NOT RESET;
SEC_LED <= BCD_SECD0(0);
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
DATA_BUS <= DATA_BUS_VALUE WHEN LCD_RW = '0' ELSE "ZZZZZZZZ";
PROCESS
BEGIN
WAIT UNTIL CLK_50MHZ'EVENT AND CLK_50MHZ = '1';
IF RESET = '0' THEN
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ <= '0';
ELSE
IF CLK_COUNT_400HZ < X"0F424" THEN
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1;
ELSE
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ <= NOT CLK_400HZ;
END IF;
END IF;
END PROCESS;
PROCESS (CLK_400HZ, reset)
BEGIN
IF reset = '0' THEN
state <= RESET1;
DATA_BUS_VALUE <= X"38";
next_command <= RESET2;
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
ELSIF CLK_400HZ'EVENT AND CLK_400HZ = '1' THEN
-- GENERATE 1/10 SEC CLOCK SIGNAL FOR SECOND COUNT PROCESS
IF CLK_COUNT_10HZ < 19 THEN
CLK_COUNT_10HZ <= CLK_COUNT_10HZ + 1;
ELSE
CLK_COUNT_10HZ <= X"00";
CLK_10HZ <= NOT CLK_10HZ;
END IF;
-- SEND TIME TO LCD
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= RESET2;
WHEN RESET2 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= RESET3;
WHEN RESET3 =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"38";
state <= TOGGLE_E;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"08";
state <= TOGGLE_E;
next_command <= DISPLAY_CLEAR;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"01";
state <= TOGGLE_E;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"0C";
state <= TOGGLE_E;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"06";
state <= TOGGLE_E;
next_command <= WRITE_CHAR1;
-- Write ASCII hex character in first LCD character location
WHEN WRITE_CHAR1 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_HRD1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR2;
-- Write ASCII hex character in second LCD character location
WHEN WRITE_CHAR2 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_HRD0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR3;
-- Write ASCII hex character in third LCD character location
WHEN WRITE_CHAR3 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3A" ;
state <= TOGGLE_E;
next_command <= WRITE_CHAR4;
-- Write ASCII hex character in fourth LCD character location
WHEN WRITE_CHAR4 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_MIND1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR5;
-- Write ASCII hex character in fifth LCD character location
WHEN WRITE_CHAR5 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_MIND0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR6;
-- Write ASCII hex character in sixth LCD character location
WHEN WRITE_CHAR6 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3A" ;
state <= TOGGLE_E;
next_command <= WRITE_CHAR7;
-- Write ASCII hex character in seventh LCD character location
WHEN WRITE_CHAR7 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_SECD1;
state <= TOGGLE_E;
next_command <= WRITE_CHAR8;
-- Write ASCII hex character in eighth LCD character location
WHEN WRITE_CHAR8 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_SECD0;
state <= TOGGLE_E;
next_command <= WRITE_CHAR9;
WHEN WRITE_CHAR9 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"2E";
state <= TOGGLE_E;
next_command <= WRITE_CHAR10;
WHEN WRITE_CHAR10 =>
LCD_E <= '1';
LCD_RS <= '1';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"3" & BCD_TSEC;
state <= TOGGLE_E;
next_command <= RETURN_HOME;
-- Return write address to first character postion
WHEN RETURN_HOME =>
LCD_E <= '1';
LCD_RS <= '0';
LCD_RW <= '0';
DATA_BUS_VALUE <= X"80";
state <= TOGGLE_E;
next_command <= WRITE_CHAR1;
-- The next two states occur at the end of each command to the LCD
-- Toggle E line - falling edge loads inst/data to LCD controller
WHEN TOGGLE_E =>
LCD_E <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END PROCESS;
PROCESS (Clk_10hz, reset)
BEGIN
IF reset = '0' THEN
BCD_HRD1 <= X"0";
BCD_HRD0 <= X"0";
BCD_MIND1 <= X"0";
BCD_MIND0 <= X"0";
BCD_SECD1 <= X"0";
BCD_SECD0 <= X"0";
BCD_TSEC <= X"0";
ELSIF clk_10HZ'EVENT AND clk_10HZ = '1' THEN
-- TENTHS OF SECONDS
IF BCD_TSEC < 9 THEN
BCD_TSEC <= BCD_TSEC + 1;
ELSE
BCD_TSEC <= X"0";
-- SECONDS
IF BCD_SECD0 < 9 THEN
BCD_SECD0 <= BCD_SECD0 + 1;
ELSE
-- TENS OF SECONDS
BCD_SECD0 <= "0000";
IF BCD_SECD1 < 5 THEN
BCD_SECD1 <= BCD_SECD1 + 1;
ELSE
-- MINUTES
BCD_SECD1 <= "0000";
IF BCD_MIND0 < 9 THEN
BCD_MIND0 <= BCD_MIND0 + 1;
ELSE
-- TENS OF MINUTES
BCD_MIND0 <= "0000";
IF BCD_MIND1 < 5 THEN
BCD_MIND1 <= BCD_MIND1 + 1;
ELSE
-- HOURS
BCD_MIND1 <= "0000";
IF BCD_HRD0 < 9 AND NOT((BCD_HRD1 = 2) AND (BCD_HRD0 = 3))THEN
BCD_HRD0 <= BCD_HRD0 + 1;
ELSE
-- TENS OF HOURS
IF NOT((BCD_HRD1 = 2) AND (BCD_HRD0 = 3)) THEN
BCD_HRD1 <= BCD_HRD1 + 1;
BCD_HRD0 <= "0000";
ELSE
-- NEW DAY
BCD_HRD1 <= "0000";
BCD_HRD0 <= "0000";
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END a;
|
gpl-2.0
|
ac4a67bd77d8373deeda5f49ee6b052d
| 0.558736 | 2.823693 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
cmos_sensor_output_generator/tb/tb_cmos_sensor_output_generator.vhd
| 1 | 6,665 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library osvvm;
use osvvm.RandomPkg.all;
use work.cmos_sensor_output_generator_constants.all;
entity tb_cmos_sensor_output_generator is
end tb_cmos_sensor_output_generator;
architecture test of tb_cmos_sensor_output_generator is
-- 10 MHz -> 100 ns period. Duty cycle = 1/2.
constant CLK_PERIOD : time := 100 ns;
constant CLK_HIGH_PERIOD : time := 50 ns;
constant CLK_LOW_PERIOD : time := 50 ns;
signal clk : std_logic;
signal reset : std_logic;
signal sim_finished : boolean := false;
-- cmos_sensor_output_generator --------------------------------------------
constant PIX_DEPTH : positive := 8;
constant MAX_WIDTH : positive := 1920;
constant MAX_HEIGHT : positive := 1080;
constant FRAME_WIDTH : positive := 5;
constant FRAME_HEIGHT : positive := 4;
constant FRAME_FRAME_BLANK : positive := 1;
constant FRAME_LINE_BLANK : natural := 1;
constant LINE_LINE_BLANK : positive := 1;
constant LINE_FRAME_BLANK : natural := 1;
signal addr : std_logic_vector(2 downto 0);
signal read : std_logic;
signal write : std_logic;
signal rddata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal wrdata : std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
signal frame_valid : std_logic;
signal line_valid : std_logic;
signal data : std_logic_vector(PIX_DEPTH - 1 downto 0);
begin
clk_generation : process
begin
if not sim_finished then
clk <= '1';
wait for CLK_HIGH_PERIOD;
clk <= '0';
wait for CLK_LOW_PERIOD;
else
wait;
end if;
end process clk_generation;
cmos_sensor_output_generator_inst : entity work.cmos_sensor_output_generator
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => clk,
reset => reset,
addr => addr,
read => read,
write => write,
rddata => rddata,
wrdata => wrdata,
frame_valid => frame_valid,
line_valid => line_valid,
data => data);
sim : process
procedure async_reset is
begin
wait until rising_edge(clk);
wait for CLK_PERIOD / 4;
reset <= '1';
wait for CLK_PERIOD / 2;
reset <= '0';
end procedure async_reset;
procedure write_register(constant ofst : in std_logic_vector;
constant val : in natural) is
begin
wait until falling_edge(clk);
addr <= ofst;
write <= '1';
wrdata <= std_logic_vector(to_unsigned(val, wrdata'length));
wait until falling_edge(clk);
addr <= (others => '0');
write <= '0';
wrdata <= (others => '0');
end procedure write_register;
procedure write_register(constant ofst : in std_logic_vector;
constant val : in std_logic_vector) is
begin
wait until falling_edge(clk);
addr <= ofst;
write <= '1';
wrdata <= std_logic_vector(resize(unsigned(val), wrdata'length));
wait until falling_edge(clk);
addr <= (others => '0');
write <= '0';
wrdata <= (others => '0');
end procedure write_register;
procedure read_register(constant ofst : in std_logic_vector) is
begin
wait until falling_edge(clk);
addr <= ofst;
read <= '1';
wait until falling_edge(clk);
addr <= (others => '0');
read <= '0';
end procedure read_register;
procedure check_idle is
begin
read_register(CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_OFST);
assert rddata = CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_IDLE report "Error: unit should be idle, but is busy" severity error;
end procedure check_idle;
procedure check_busy is
begin
read_register(CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_OFST);
assert rddata = CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_BUSY report "Error: unit should be busy, but is idle" severity error;
end procedure check_busy;
procedure wait_clock_cycles(constant count : in positive) is
begin
wait for count * CLK_PERIOD;
end procedure wait_clock_cycles;
variable rand_gen : RandomPType;
begin
-- initialize random number generator
rand_gen.InitSeed(rand_gen'instance_name);
rand_gen.SetRandomParm(UNIFORM);
async_reset;
-- configure
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST, FRAME_WIDTH);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST, FRAME_HEIGHT);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST, FRAME_FRAME_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST, FRAME_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST, LINE_LINE_BLANK);
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST, LINE_FRAME_BLANK);
-- start generator
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START);
check_busy;
wait_clock_cycles(rand_gen.RandInt(0, 100));
-- stop generator
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_STOP);
check_idle;
-- start generator
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START);
check_busy;
wait_clock_cycles(rand_gen.RandInt(0, 100));
-- stop generator
write_register(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST, CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_STOP);
check_idle;
sim_finished <= true;
wait;
end process sim;
end architecture test;
|
unlicense
|
d4f56fd349432a29216a9990e70c4f54
| 0.563091 | 4.261509 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/toplevel.vhd
| 1 | 5,449 |
library ieee;
use ieee.std_logic_1164.all;
entity toplevel is
port(
-- input pins
IN_clk_50 : in std_logic;
IN_rst : in std_logic;
IN_RotA : in std_logic;
IN_RotB : in std_logic;
IN_RotPush : in std_logic;
-- output pins
OUT_LED_ch0 : out std_logic := '0';
OUT_LED_ch1 : out std_logic := '0';
OUT_LED_ch2 : out std_logic := '0';
OUT_LED_ch3 : out std_logic := '0';
OUT_LED_ch4 : out std_logic := '0';
OUT_LED_ch5 : out std_logic := '0';
OUT_LED_ch6 : out std_logic := '0';
OUT_LED_ch7 : out std_logic := '0'
);
end entity toplevel;
architecture RTL of toplevel is
-- component declarations
component rotKey
port(clk_50 : in std_logic;
rotA : in std_logic;
rotB : in std_logic;
rotPush : in std_logic;
rotRightEvent : out std_logic;
rotLeftEvent : out std_logic;
rotPushEvent : out std_logic);
end component rotKey;
component controller
port(clk_50 : in std_logic;
rst : in std_logic;
leftEvent : in std_logic;
rightEvent : in std_logic;
pushEvent : in std_logic;
pwm0 : out std_logic_vector(5 downto 0);
pwm1 : out std_logic_vector(5 downto 0);
pwm2 : out std_logic_vector(5 downto 0);
pwm3 : out std_logic_vector(5 downto 0);
pwm4 : out std_logic_vector(5 downto 0);
pwm5 : out std_logic_vector(5 downto 0);
pwm6 : out std_logic_vector(5 downto 0);
pwm7 : out std_logic_vector(5 downto 0));
end component controller;
component logDim
port(pwmIn : in std_logic_vector(5 downto 0);
logPwm : out std_logic_vector(7 downto 0));
end component logDim;
component pwmUnit
port(clk_10 : in std_logic;
rst : in std_logic;
duty : in std_logic_vector(7 downto 0);
outSig : out std_logic := '0');
end component pwmUnit;
-- signal declarations
signal sig_rotRightEvent : std_logic;
signal sig_rotLeftEvent : std_logic;
signal sig_rotPushEvent : std_logic;
signal sig_duty0 : std_logic_vector(5 downto 0);
signal sig_duty1 : std_logic_vector(5 downto 0);
signal sig_duty2 : std_logic_vector(5 downto 0);
signal sig_duty3 : std_logic_vector(5 downto 0);
signal sig_duty4 : std_logic_vector(5 downto 0);
signal sig_duty5 : std_logic_vector(5 downto 0);
signal sig_duty6 : std_logic_vector(5 downto 0);
signal sig_duty7 : std_logic_vector(5 downto 0);
signal sig_pwm0 : std_logic_vector(7 downto 0);
signal sig_pwm1 : std_logic_vector(7 downto 0);
signal sig_pwm2 : std_logic_vector(7 downto 0);
signal sig_pwm3 : std_logic_vector(7 downto 0);
signal sig_pwm4 : std_logic_vector(7 downto 0);
signal sig_pwm5 : std_logic_vector(7 downto 0);
signal sig_pwm6 : std_logic_vector(7 downto 0);
signal sig_pwm7 : std_logic_vector(7 downto 0);
begin
-- create instances and route signals
inst_rotKey : rotKey
port map(clk_50 => IN_clk_50,
rotA => IN_rotA,
rotB => IN_rotB,
rotPush => IN_rotPush,
rotRightEvent => sig_rotRightEvent,
rotLeftEvent => sig_rotLeftEvent,
rotPushEvent => sig_rotPushEvent);
inst_controller : controller
port map(clk_50 => IN_clk_50,
rst => IN_rst,
leftEvent => sig_rotLeftEvent,
rightEvent => sig_rotRightEvent,
pushEvent => sig_rotPushEvent,
pwm0 => sig_duty0,
pwm1 => sig_duty1,
pwm2 => sig_duty2,
pwm3 => sig_duty3,
pwm4 => sig_duty4,
pwm5 => sig_duty5,
pwm6 => sig_duty6,
pwm7 => sig_duty7);
inst_log0 : logDim
port map(pwmIn => sig_duty0,
logPwm => sig_pwm0);
inst_pwm0 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm0,
outSig => OUT_LED_ch0);
inst_log1 : logDim
port map(pwmIn => sig_duty1,
logPwm => sig_pwm1);
inst_pwm1 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm1,
outSig => OUT_LED_ch1);
inst_log2 : logDim
port map(pwmIn => sig_duty2,
logPwm => sig_pwm2);
inst_pwm2 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm2,
outSig => OUT_LED_ch2);
inst_log3 : logDim
port map(pwmIn => sig_duty3,
logPwm => sig_pwm3);
inst_pwm3 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm3,
outSig => OUT_LED_ch3);
inst_log4 : logDim
port map(pwmIn => sig_duty4,
logPwm => sig_pwm4);
inst_pwm4 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm4,
outSig => OUT_LED_ch4);
inst_log5 : logDim
port map(pwmIn => sig_duty5,
logPwm => sig_pwm5);
inst_pwm5 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm5,
outSig => OUT_LED_ch5);
inst_log6 : logDim
port map(pwmIn => sig_duty6,
logPwm => sig_pwm6);
inst_pwm6 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm6,
outSig => OUT_LED_ch6);
inst_log7 : logDim
port map(pwmIn => sig_duty7,
logPwm => sig_pwm7);
inst_pwm7 : pwmUnit
port map(clk_10 => IN_clk_50,
rst => IN_rst,
duty => sig_pwm7,
outSig => OUT_LED_ch7);
end architecture RTL;
|
mit
|
fc42d6dacdfbdeb016abc2442aae8b8f
| 0.578088 | 2.969482 | false | false | false | false |
twasiluk/hdmilight
|
fpga/uart.vhd
| 1 | 5,285 |
-----------------------------------------------------------------------------
-- Simple UART with 1 byte buffer and without hardware flowcontrol.
-- by Joerg Bornschein ([email protected])
--
-- divisor parametrizes the baundrate:
--
-- divisor = 50 MHz / 115200 Baud = 434
-- divisor = 32 MHz / 115200 Baud = 278
--
-- All files under GPLv2
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------
-- UART ---------------------------------------------------------------------
entity uart is
generic (
divisor : integer := 278 );
port (
clk : in std_logic;
reset : in std_logic;
--
txdata : in std_logic_vector(7 downto 0);
rxdata : out std_logic_vector(7 downto 0);
wr : in std_logic;
rd : in std_logic;
tx_avail : out std_logic;
tx_busy : out std_logic;
rx_avail : out std_logic;
rx_full : out std_logic;
rx_error : out std_logic;
--
uart_rxd : in std_logic;
uart_txd : out std_logic );
end uart;
-----------------------------------------------------------------------------
-- implementation -----------------------------------------------------------
architecture rtl of uart is
-----------------------------------------------------------------------------
-- component declarations ---------------------------------------------------
component uart_rx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
dout : out std_logic_vector(7 downto 0);
avail : out std_logic;
error : out std_logic;
clear : in std_logic;
--
rxd : in std_logic );
end component;
component uart_tx is
generic (
fullbit : integer );
port (
clk : in std_logic;
reset : in std_logic;
--
din : in std_logic_vector(7 downto 0);
wr : in std_logic;
busy : out std_logic;
--
txd : out std_logic );
end component;
-----------------------------------------------------------------------------
-- local signals ------------------------------------------------------------
signal utx_busy : std_logic;
signal utx_wr : std_logic;
signal urx_dout : std_logic_vector(7 downto 0);
signal urx_avail : std_logic;
signal urx_clear : std_logic;
signal urx_error : std_logic;
signal txbuf : std_logic_vector(7 downto 0);
signal txbuf_full : std_logic;
signal rxbuf : std_logic_vector(7 downto 0);
signal rxbuf_full : std_logic;
begin
iotxproc: process(clk, reset) is
begin
if reset='1' then
utx_wr <= '0';
txbuf_full <= '0';
urx_clear <= '0';
rxbuf_full <= '0';
elsif clk'event and clk='1' then
-- TX Buffer Logic
if wr='1' then
txbuf <= txdata;
txbuf_full <= '1';
end if;
if txbuf_full='1' and utx_busy='0' then
utx_wr <= '1';
txbuf_full <= '0';
else
utx_wr <= '0';
end if;
-- RX Buffer Logic
if rd='1' then
rxbuf_full <= '0';
end if;
if urx_avail='1' and rxbuf_full='0' then
rxbuf <= urx_dout;
rxbuf_full <= '1';
urx_clear <= '1';
else
urx_clear <= '0';
end if;
end if;
end process;
uart_rx0: uart_rx
generic map (
fullbit => divisor )
port map (
clk => clk,
reset => reset,
--
dout => urx_dout,
avail => urx_avail,
error => urx_error,
clear => urx_clear,
--
rxd => uart_rxd );
uart_tx0: uart_tx
generic map (
fullbit => divisor )
port map (
clk => clk,
reset => reset,
--
din => txbuf,
wr => utx_wr,
busy => utx_busy,
--
txd => uart_txd );
rxdata <= rxbuf;
rx_avail <= rxbuf_full and not rd;
rx_full <= rxbuf_full and urx_avail and not rd;
rx_error <= urx_error;
tx_busy <= utx_busy or txbuf_full or wr;
tx_avail <= not txbuf_full;
end rtl;
|
gpl-2.0
|
f109fc82a829d35245168679b505e5ca
| 0.347966 | 4.866483 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/pwm.vhd
| 1 | 1,411 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
entity pwmUnit is
generic(
div : natural := 7
);
port(
clk_10 : in std_logic;
rst : in std_logic;
duty : in std_logic_vector(7 downto 0);
outSig : out std_logic := '0'
);
end entity pwmUnit;
-- Led frequency 1kHz 256 Steps
-- 50 Mhz / 128 = 390625 Hz / 256 Steps = 1526 Hz
architecture RTL of pwmUnit is
signal freq_cnt : unsigned(div-1 downto 0);
signal pwm_cnt : unsigned(7 downto 0);
signal duty_reg : unsigned(7 downto 0);
begin
clk_div: process(clk_10, rst)
begin
if rst = '1' then
freq_cnt <= (others => '0');
elsif rising_edge(clk_10) then
freq_cnt <= freq_cnt + 1;
end if;
end process;
pwm: process(clk_10, rst)
begin
if rst = '1' then
pwm_cnt <= (others => '0');
elsif rising_edge(clk_10) and freq_cnt = 0 then
pwm_cnt <= pwm_cnt + 1;
end if;
end process;
duty_register: process(clk_10, rst)
begin
if rst = '1' then
duty_reg <= (others => '0');
elsif rising_edge(clk_10) and pwm_cnt = 0 then
duty_reg <= unsigned(duty);
end if;
end process;
outSig <= '0' when duty_reg = 0 else
'1' when pwm_cnt <= duty_reg else
'0';
end architecture RTL;
|
mit
|
9b4184786729cc7933a3f09f0647f49f
| 0.549965 | 3.30445 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task2/tb_uart.vhd
| 1 | 1,154 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_uart is
end tb_uart;
architecture behav of tb_uart is
signal rst_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal Din_i : std_logic_vector(7 downto 0) := X"AA";
signal rx_i : std_logic := '0';
signal tx_o : std_logic := '0';
signal ld_i : std_logic := '0';
begin
process
begin
clk_i <= '1', '0' after 166 ns;
wait for 333 ns;
end process;
process
begin
wait for 1*333 ns;
rst_i <= '1';
wait for 3*333 ns;
rst_i <= '0';
wait for 1*333 ns;
Din_i <= X"55";
wait for 4 ms;
Din_i <= X"CD";
wait for 4 ms;
assert false report "done" severity failure;
wait;
end process;
rx_i <= tx_o; --loop back
uart_i: entity work.uart_top_shell
port map(
rst_i => rst_i,
clk_i => clk_i,
Din_i => Din_i,
rx_i => rx_i,
tx_o => tx_o,
ld_i => ld_i
);
end behav;
|
mit
|
a17e89a2bee9938bf796f750cefc9fbb
| 0.4974 | 3.085561 | false | false | false | false |
Derek-X-Wang/VGA-Text-Generator
|
VGA-Text-Generator.srcs/sources_1/new/Pixel_On_Text.vhd
| 1 | 3,354 |
-- Pixel_On_Text determines if the current pixel is on text
-- param:
-- textlength, use to init the string
-- input:
-- VGA clock(the clk you used to update VGA)
-- display text
-- top left corner of the text box
-- current X and Y position
-- output:
-- a bit that represent whether is the pixel in text
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- note this line.The package is compiled to this directory by default.
-- so don't forget to include this directory.
library work;
-- this line also is must.This includes the particular package into your program.
use work.commonPak.all;
entity Pixel_On_Text is
generic(
-- needed for init displayText, the default value 11 is just a random number
textLength: integer := 11
);
port (
clk: in std_logic;
displayText: in string (1 to textLength) := (others => NUL);
-- top left corner of the text
position: in point_2d := (0, 0);
-- current pixel postion
horzCoord: in integer;
vertCoord: in integer;
pixel: out std_logic := '0'
);
end Pixel_On_Text;
architecture Behavioral of Pixel_On_Text is
signal fontAddress: integer;
-- A row of bit in a charactor, we check if our current (x,y) is 1 in char row
signal charBitInRow: std_logic_vector(FONT_WIDTH-1 downto 0) := (others => '0');
-- char in ASCII code
signal charCode:integer := 0;
-- the position(column) of a charactor in the given text
signal charPosition:integer := 0;
-- the bit position(column) in a charactor
signal bitPosition:integer := 0;
begin
-- (horzCoord - position.x): x positionin the top left of the whole text
charPosition <= (horzCoord - position.x)/FONT_WIDTH + 1;
bitPosition <= (horzCoord - position.x) mod FONT_WIDTH;
charCode <= character'pos(displayText(charPosition));
-- charCode*16: first row of the char
fontAddress <= charCode*16+(vertCoord - position.y);
fontRom: entity work.Font_Rom
port map(
clk => clk,
addr => fontAddress,
fontRow => charBitInRow
);
pixelOn: process(clk)
variable inXRange: boolean := false;
variable inYRange: boolean := false;
begin
if rising_edge(clk) then
-- reset
inXRange := false;
inYRange := false;
pixel <= '0';
-- If current pixel is in the horizontal range of text
if horzCoord >= position.x and horzCoord < position.x + (FONT_WIDTH * textlength) then
inXRange := true;
end if;
-- If current pixel is in the vertical range of text
if vertCoord >= position.y and vertCoord < position.y + FONT_HEIGHT then
inYRange := true;
end if;
-- need to check if the pixel is on for text
if inXRange and inYRange then
-- FONT_WIDTH-bitPosition: we are reverting the charactor
if charBitInRow(FONT_WIDTH-bitPosition) = '1' then
pixel <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
c38f86f6e7fcf6f155599de7f68bba8d
| 0.6452 | 3.855172 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
cmos_sensor_input/hdl/cmos_sensor_input_sc_fifo.vhd
| 5 | 4,445 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_sc_fifo is
generic(
DATA_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read : in std_logic;
write : in std_logic;
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
overflow : out std_logic
);
end cmos_sensor_input_sc_fifo;
architecture rtl of cmos_sensor_input_sc_fifo is
component scfifo
generic(
add_ram_output_register : string;
intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
port(
clock : in std_logic;
data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rdreq : in std_logic;
sclr : in std_logic;
wrreq : in std_logic;
empty : out std_logic;
full : out std_logic;
q : out std_logic_vector(DATA_WIDTH - 1 downto 0);
usedw : out std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0)
);
end component;
signal scfifo_clock : std_logic;
signal scfifo_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_rdreq : std_logic;
signal scfifo_sclr : std_logic;
signal scfifo_wrreq : std_logic;
signal scfifo_empty : std_logic;
signal scfifo_full : std_logic;
signal scfifo_q : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal scfifo_usedw : std_logic_vector(bit_width(FIFO_DEPTH) - 2 downto 0);
signal reg_overflow : std_logic;
begin
FIFO_OVERFLOW : process(clk, reset)
begin
if reset = '1' then
reg_overflow <= '0';
elsif rising_edge(clk) then
if clr = '1' then
reg_overflow <= '0';
else
reg_overflow <= reg_overflow or (write and scfifo_full);
end if;
end if;
end process;
OUTPUTS : process(reg_overflow, scfifo_empty, scfifo_full, scfifo_q, scfifo_usedw)
begin
data_out <= scfifo_q;
empty <= scfifo_empty;
full <= scfifo_full;
overflow <= reg_overflow;
if scfifo_full = '1' then
usedw <= std_logic_vector(to_unsigned(FIFO_DEPTH, usedw'length));
elsif scfifo_empty = '1' then
usedw <= std_logic_vector(to_unsigned(0, usedw'length));
else
usedw <= std_logic_vector(resize(unsigned(scfifo_usedw), usedw'length));
end if;
end process;
-- scfifo connections ------------------------------------------------------
scfifo_clock <= clk;
scfifo_data <= data_in;
scfifo_rdreq <= read and not scfifo_empty;
scfifo_sclr <= clr;
scfifo_wrreq <= write and not scfifo_full;
scfifo_component : scfifo
generic map(
add_ram_output_register => "OFF",
intended_device_family => DEVICE_FAMILY,
lpm_numwords => FIFO_DEPTH,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => DATA_WIDTH,
lpm_widthu => bit_width(FIFO_DEPTH) - 1,
overflow_checking => "OFF",
underflow_checking => "OFF",
use_eab => "ON"
)
port map(
clock => scfifo_clock,
data => scfifo_data,
rdreq => scfifo_rdreq,
sclr => scfifo_sclr,
wrreq => scfifo_wrreq,
empty => scfifo_empty,
full => scfifo_full,
q => scfifo_q,
usedw => scfifo_usedw
);
end rtl;
|
unlicense
|
623472cbb9dce95508098d3fb8dc0527
| 0.510911 | 4.0009 | false | false | false | false |
cfangmeier/VFPIX-telescope-Code
|
DAQ_Firmware/src/ram/ram_controller_phy_alt_mem_phy_seq.vhd
| 1 | 648,425 |
--
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ram_controller_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ram_controller_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ram_controller_phy_alt_mem_phy_record_pkg;
--
package body ram_controller_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 9;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ram_controller_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ram_controller_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ram_controller_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ram_controller_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ram_controller_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ram_controller_phy_alt_mem_phy_iram_addr_pkg;
--
package body ram_controller_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ram_controller_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
package ram_controller_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ram_controller_phy_alt_mem_phy_regs_pkg;
--
package body ram_controller_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ram_controller_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ram_controller_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 10;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
ac_state <= s_0;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ram_controller_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ram_controller_phy_alt_mem_phy_iram_ram;
--
entity ram_controller_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ram_controller_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ram_controller_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ram_controller_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ram_controller_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ram_controller_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ram_controller_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ram_controller_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ram_controller_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ram_controller_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ram_controller_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ram_controller_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ram_controller_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ram_controller_phy_alt_mem_phy_admin;
--
use work.ram_controller_phy_alt_mem_phy_mmi;
--
use work.ram_controller_phy_alt_mem_phy_iram;
--
use work.ram_controller_phy_alt_mem_phy_dgrb;
--
use work.ram_controller_phy_alt_mem_phy_dgwb;
--
use work.ram_controller_phy_alt_mem_phy_ctrl;
--
architecture struct of ram_controller_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ram_controller_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ram_controller_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ram_controller_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ram_controller_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ram_controller_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ram_controller_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ram_controller_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
|
gpl-2.0
|
fc1fdf772dde9fe3032792697a0436a1
| 0.442074 | 4.431615 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task1/bit_in.vhd
| 1 | 1,248 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.tb_package.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bit_in_gen is
Port ( command_i : in command_rec;
enable_o : out std_logic;
done_o : out std_logic_vector(gen_number downto 0)
);
end bit_in_gen;
architecture Behavioral of bit_in_gen is
signal s_enable : std_logic:='0';
signal s_done_o : std_logic;
begin
done_o(0) <= 'Z';
done_o(1) <= 'Z';
done_o(2) <= 'Z';
done_o(3) <= 'Z';
done_o(4) <= 'Z';
done_o(5) <= 'Z';
done_o(6) <= s_done_o;
enable_o <= s_enable;
p_main: process
variable value1 : string(1 to 8);
begin
s_done_o <= '0';
wait on command_i;
if command_i.gen_number=6 then
if command_i.mnemonic(1 to 6)="enable" then
if command_i.value1(8)='1' then
s_enable <= '1';
else
s_enable <= '0';
end if;
elsif command_i.mnemonic(1 to 4)="stop" then
-- start <= false;
end if;
s_done_o <= '1';
wait on s_done_o;
end if;
end process p_main;
end Behavioral;
|
mit
|
f05b742f8c0c59546f50019e2a5ca1a7
| 0.608974 | 2.632911 | false | false | false | false |
thelonious/display4
|
timer.vhd
| 2 | 824 |
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
entity Timer is
generic(
CLOCK_FREQUENCY: positive := 32_000_000;
TIMER_FREQUENCY: positive := 1_000
);
port(
clock: in std_logic;
reset: in std_logic;
tick: out std_logic
);
end Timer;
architecture behavioral of Timer is
constant CLOCK_TICKS: integer := (CLOCK_FREQUENCY / TIMER_FREQUENCY) - 1;
signal tick_count : integer range 0 to CLOCK_TICKS;
begin
update_clock: process(clock)
begin
if clock'event and clock = '1' then
if reset = '1' then
tick_count <= 0;
tick <= '0';
elsif tick_count = CLOCK_TICKS then
tick_count <= 0;
tick <= '1';
else
tick_count <= tick_count + 1;
tick <= '0';
end if;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
cc41b18080d0799255c4fed89c8b3b90
| 0.657767 | 3.029412 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task4/controller.vhd
| 1 | 6,131 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- This is the controller entity
entity controller is
port(
clk_50 : in std_logic;
rst : in std_logic;
-- Input events
leftEvent : in std_logic;
rightEvent : in std_logic;
pushEvent : in std_logic;
-- PWM registers
pwm0 : out std_logic_vector(5 downto 0);
pwm1 : out std_logic_vector(5 downto 0);
pwm2 : out std_logic_vector(5 downto 0);
pwm3 : out std_logic_vector(5 downto 0);
pwm4 : out std_logic_vector(5 downto 0);
pwm5 : out std_logic_vector(5 downto 0);
pwm6 : out std_logic_vector(5 downto 0);
pwm7 : out std_logic_vector(5 downto 0)
);
end entity controller;
architecture RTL of controller is
-- output registers
signal reg_pwm0 : unsigned(5 downto 0) := "000000";
signal reg_pwm1 : unsigned(5 downto 0) := "000000";
signal reg_pwm2 : unsigned(5 downto 0) := "000000";
signal reg_pwm3 : unsigned(5 downto 0) := "000000";
signal reg_pwm4 : unsigned(5 downto 0) := "000000";
signal reg_pwm5 : unsigned(5 downto 0) := "000000";
signal reg_pwm6 : unsigned(5 downto 0) := "000000";
signal reg_pwm7 : unsigned(5 downto 0) := "000000";
-- channel selector
signal channel : unsigned(2 downto 0) := "000";
type direction is (UP, DOWN);
signal rEv_old : std_logic := '0';
signal lEv_old : std_logic := '0';
procedure inc_dec(dir : in direction;
signal reg_pwm0 : inout unsigned(5 downto 0);
signal reg_pwm1 : inout unsigned(5 downto 0);
signal reg_pwm2 : inout unsigned(5 downto 0);
signal reg_pwm3 : inout unsigned(5 downto 0);
signal reg_pwm4 : inout unsigned(5 downto 0);
signal reg_pwm5 : inout unsigned(5 downto 0);
signal reg_pwm6 : inout unsigned(5 downto 0);
signal reg_pwm7 : inout unsigned(5 downto 0)) is
begin
-- channel register increase or destease with saturation
case channel is
when "000" => if (dir = UP) then
if (reg_pwm0 = "111111") then
reg_pwm0 <= "111111";
else
reg_pwm0 <= reg_pwm0 + "1";
end if;
else
if (reg_pwm0 = "000000") then
reg_pwm0 <= "000000";
else
reg_pwm0 <= reg_pwm0 - "1";
end if;
end if;
when "001" => if (dir = UP) then
if (reg_pwm1 = "111111") then
reg_pwm1 <= "111111";
else
reg_pwm1 <= reg_pwm1 + "1";
end if;
else
if (reg_pwm1 = "000000") then
reg_pwm1 <= "000000";
else
reg_pwm1 <= reg_pwm1 - "1";
end if;
end if;
when "010" => if (dir = UP) then
if (reg_pwm2 = "111111") then
reg_pwm2 <= "111111";
else
reg_pwm2 <= reg_pwm2 + "1";
end if;
else
if (reg_pwm2 = "000000") then
reg_pwm2 <= "000000";
else
reg_pwm2 <= reg_pwm2 - "1";
end if;
end if;
when "011" => if (dir = UP) then
if (reg_pwm3 = "111111") then
reg_pwm3 <= "111111";
else
reg_pwm3 <= reg_pwm3 + "1";
end if;
else
if (reg_pwm3 = "000000") then
reg_pwm3 <= "000000";
else
reg_pwm3 <= reg_pwm3 - "1";
end if;
end if;
when "100" => if (dir = UP) then
if (reg_pwm4 = "111111") then
reg_pwm4 <= "111111";
else
reg_pwm4 <= reg_pwm4 + "1";
end if;
else
if (reg_pwm4 = "000000") then
reg_pwm4 <= "000000";
else
reg_pwm4 <= reg_pwm4 - "1";
end if;
end if;
when "101" => if (dir = UP) then
if (reg_pwm5 = "111111") then
reg_pwm5 <= "111111";
else
reg_pwm5 <= reg_pwm5 + "1";
end if;
else
if (reg_pwm5 = "000000") then
reg_pwm5 <= "000000";
else
reg_pwm5 <= reg_pwm5 - "1";
end if;
end if;
when "110" => if (dir = UP) then
if (reg_pwm6 = "111111") then
reg_pwm6 <= "111111";
else
reg_pwm6 <= reg_pwm6 + "1";
end if;
else
if (reg_pwm6 = "000000") then
reg_pwm6 <= "000000";
else
reg_pwm6 <= reg_pwm6 - "1";
end if;
end if;
when "111" => if (dir = UP) then
if (reg_pwm7 = "111111") then
reg_pwm7 <= "111111";
else
reg_pwm7 <= reg_pwm7 + "1";
end if;
else
if (reg_pwm7 = "000000") then
reg_pwm7 <= "000000";
else
reg_pwm7 <= reg_pwm7 - "1";
end if;
end if;
when others =>
end case;
end procedure inc_dec;
begin
p_intensityUpDown : process(clk_50, rst)
variable catREv : std_logic_vector(1 downto 0);
variable catLEv : std_logic_vector(1 downto 0);
begin
if (rst = '1') then
reg_pwm0 <= "000000";
reg_pwm1 <= "000000";
reg_pwm2 <= "000000";
reg_pwm3 <= "000000";
reg_pwm4 <= "000000";
reg_pwm5 <= "000000";
reg_pwm6 <= "000000";
reg_pwm7 <= "000000";
else
if (clk_50'event and clk_50 = '1') then
catREv := rightEvent & rEv_old;
catLEv := leftEvent & lEv_old;
-- cover a right twist event
case (catREv) is
when "10" => inc_dec(UP, reg_pwm0, reg_pwm1, reg_pwm2, reg_pwm3, reg_pwm4, reg_pwm5, reg_pwm6, reg_pwm7);
--report "UP for channel";
when others =>
end case;
-- cover a left twist event
case (catLEv) is
when "10" => inc_dec(DOWN, reg_pwm0, reg_pwm1, reg_pwm2, reg_pwm3, reg_pwm4, reg_pwm5, reg_pwm6, reg_pwm7);
--report "DOWN for channel";
when others =>
end case;
rEv_old <= rightEvent;
lEv_old <= leftEvent;
end if;
end if;
end process p_intensityUpDown;
p_channelSelector : process(pushEvent, rst)
begin
if (rst = '1') then
channel <= "000";
else
if (pushEvent'event and pushEvent = '1') then
channel <= channel + "1";
end if;
end if;
end process p_channelSelector;
-- write to output ports
pwm0 <= std_logic_vector(reg_pwm0);
pwm1 <= std_logic_vector(reg_pwm1);
pwm2 <= std_logic_vector(reg_pwm2);
pwm3 <= std_logic_vector(reg_pwm3);
pwm4 <= std_logic_vector(reg_pwm4);
pwm5 <= std_logic_vector(reg_pwm5);
pwm6 <= std_logic_vector(reg_pwm6);
pwm7 <= std_logic_vector(reg_pwm7);
end architecture RTL;
|
mit
|
a498c1684d8d3f7e1890dd6d4dbef0fa
| 0.560757 | 2.817555 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
cmos_sensor_input/hdl/cmos_sensor_input.vhd
| 5 | 26,442 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input is
generic(
PIX_DEPTH : positive;
SAMPLE_EDGE : string;
MAX_WIDTH : positive range 2 to 65535; -- does not support images with only 1 column (in order for start_of_frame and end_of_frame not to overlap)
MAX_HEIGHT : positive range 1 to 65535; -- but any height is supported
OUTPUT_WIDTH : positive;
FIFO_DEPTH : positive;
DEVICE_FAMILY : string;
DEBAYER_ENABLE : boolean;
PACKER_ENABLE : boolean
);
port(
clk : in std_logic;
reset : in std_logic;
-- cmos sensor
frame_valid : in std_logic;
line_valid : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
-- Avalon-ST Src
ready : in std_logic;
valid : out std_logic;
data_out : out std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
-- Avalon-MM Slave
addr : in std_logic_vector(1 downto 0);
read : in std_logic;
write : in std_logic;
rddata : out std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
wrdata : in std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
-- Avalon Interrupt Sender
irq : out std_logic
);
end entity cmos_sensor_input;
architecture rtl of cmos_sensor_input is
constant PIX_DEPTH_RGB : positive := 3 * PIX_DEPTH;
constant FIFO_DATA_WIDTH : positive := OUTPUT_WIDTH + 1;
constant FIFO_END_OF_FRAME_BIT_OFST : positive := OUTPUT_WIDTH; -- sc_fifo_data(FIFO_END_OF_FRAME_BIT_OFST) = end_of_frame
-- avalon_mm_slave ---------------------------------------------------------
signal avalon_mm_slave_clk_in : std_logic;
signal avalon_mm_slave_reset_in : std_logic;
signal avalon_mm_slave_addr_in : std_logic_vector(1 downto 0);
signal avalon_mm_slave_read_in : std_logic;
signal avalon_mm_slave_write_in : std_logic;
signal avalon_mm_slave_rddata_out : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal avalon_mm_slave_wrdata_in : std_logic_vector(CMOS_SENSOR_INPUT_MM_S_DATA_WIDTH - 1 downto 0);
signal avalon_mm_slave_irq_out : std_logic;
signal avalon_mm_slave_idle_in : std_logic;
signal avalon_mm_slave_snapshot_out : std_logic;
signal avalon_mm_slave_get_frame_info_out : std_logic;
signal avalon_mm_slave_irq_en_out : std_logic;
signal avalon_mm_slave_irq_ack_out : std_logic;
signal avalon_mm_slave_wait_irq_ack_in : std_logic;
signal avalon_mm_slave_frame_width_in : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal avalon_mm_slave_frame_height_in : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal avalon_mm_slave_debayer_pattern_out : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0);
signal avalon_mm_slave_fifo_usedw_in : std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
signal avalon_mm_slave_fifo_overflow_in : std_logic;
signal avalon_mm_slave_stop_and_reset_out : std_logic;
-- synchronizer ------------------------------------------------------------
signal synchronizer_clk_in : std_logic;
signal synchronizer_reset_in : std_logic;
signal synchronizer_frame_valid_in_in : std_logic;
signal synchronizer_line_valid_in_in : std_logic;
signal synchronizer_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal synchronizer_frame_valid_out_out : std_logic;
signal synchronizer_line_valid_out_out : std_logic;
signal synchronizer_data_out_out : std_logic_vector(PIX_DEPTH - 1 downto 0);
-- sampler -----------------------------------------------------------------
signal sampler_clk_in : std_logic;
signal sampler_reset_in : std_logic;
signal sampler_stop_and_reset_in : std_logic;
signal sampler_idle_out : std_logic;
signal sampler_wait_irq_ack_out : std_logic;
signal sampler_irq_en_in : std_logic;
signal sampler_irq_ack_in : std_logic;
signal sampler_snapshot_in : std_logic;
signal sampler_get_frame_info_in : std_logic;
signal sampler_frame_width_out : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal sampler_frame_height_out : std_logic_vector(bit_width(max(MAX_WIDTH, MAX_HEIGHT)) - 1 downto 0);
signal sampler_frame_valid_in : std_logic;
signal sampler_line_valid_in : std_logic;
signal sampler_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal sampler_valid_out_out : std_logic;
signal sampler_data_out_out : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal sampler_start_of_frame_out_out : std_logic;
signal sampler_end_of_frame_out_out : std_logic;
signal sampler_fifo_overflow_in : std_logic;
signal sampler_end_of_frame_in_in : std_logic;
signal sampler_end_of_frame_in_ack_out : std_logic;
-- debayer -----------------------------------------------------------------
signal debayer_clk_in : std_logic;
signal debayer_reset_in : std_logic;
signal debayer_stop_and_reset_in : std_logic;
signal debayer_debayer_pattern_in : std_logic_vector(CMOS_SENSOR_INPUT_CONFIG_DEBAYER_PATTERN_WIDTH - 1 downto 0);
signal debayer_valid_in_in : std_logic;
signal debayer_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal debayer_start_of_frame_in_in : std_logic;
signal debayer_end_of_frame_in_in : std_logic;
signal debayer_valid_out_out : std_logic;
signal debayer_data_out_out : std_logic_vector(PIX_DEPTH_RGB - 1 downto 0);
signal debayer_start_of_frame_out_out : std_logic;
signal debayer_end_of_frame_out_out : std_logic;
-- packer_raw --------------------------------------------------------------
signal packer_raw_clk_in : std_logic;
signal packer_raw_reset_in : std_logic;
signal packer_raw_stop_and_reset_in : std_logic;
signal packer_raw_valid_in_in : std_logic;
signal packer_raw_data_in_in : std_logic_vector(PIX_DEPTH - 1 downto 0);
signal packer_raw_start_of_frame_in_in : std_logic;
signal packer_raw_end_of_frame_in_in : std_logic;
signal packer_raw_valid_out_out : std_logic;
signal packer_raw_data_out_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal packer_raw_end_of_frame_out_out : std_logic;
-- packer_rgb --------------------------------------------------------------
signal packer_rgb_clk_in : std_logic;
signal packer_rgb_reset_in : std_logic;
signal packer_rgb_stop_and_reset_in : std_logic;
signal packer_rgb_valid_in_in : std_logic;
signal packer_rgb_data_in_in : std_logic_vector(PIX_DEPTH_RGB - 1 downto 0);
signal packer_rgb_start_of_frame_in_in : std_logic;
signal packer_rgb_end_of_frame_in_in : std_logic;
signal packer_rgb_valid_out_out : std_logic;
signal packer_rgb_data_out_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal packer_rgb_end_of_frame_out_out : std_logic;
-- sc_fifo -----------------------------------------------------------------
signal sc_fifo_clk_in : std_logic;
signal sc_fifo_reset_in : std_logic;
signal sc_fifo_clr_in : std_logic;
signal sc_fifo_data_in_in : std_logic_vector(FIFO_DATA_WIDTH - 1 downto 0);
signal sc_fifo_data_out_out : std_logic_vector(FIFO_DATA_WIDTH - 1 downto 0);
signal sc_fifo_read_in : std_logic;
signal sc_fifo_write_in : std_logic;
signal sc_fifo_empty_out : std_logic;
signal sc_fifo_full_out : std_logic;
signal sc_fifo_usedw_out : std_logic_vector(bit_width(FIFO_DEPTH) - 1 downto 0);
signal sc_fifo_overflow_out : std_logic;
-- avalon_st_source --------------------------------------------------------
signal avalon_st_source_clk_in : std_logic;
signal avalon_st_source_reset_in : std_logic;
signal avalon_st_source_stop_and_reset_in : std_logic;
signal avalon_st_source_ready_in : std_logic;
signal avalon_st_source_valid_out : std_logic;
signal avalon_st_source_data_out : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal avalon_st_source_fifo_read_out : std_logic;
signal avalon_st_source_fifo_empty_in : std_logic;
signal avalon_st_source_fifo_data_in : std_logic_vector(OUTPUT_WIDTH - 1 downto 0);
signal avalon_st_source_fifo_end_of_frame_in : std_logic;
signal avalon_st_source_fifo_overflow_in : std_logic;
signal avalon_st_source_end_of_frame_out_out : std_logic;
signal avalon_st_source_end_of_frame_out_ack_in : std_logic;
begin
valid <= avalon_st_source_valid_out;
data_out <= avalon_st_source_data_out;
rddata <= avalon_mm_slave_rddata_out;
irq <= avalon_mm_slave_irq_out;
cmos_sensor_input_avalon_mm_slave_inst : entity work.cmos_sensor_input_avalon_mm_slave
generic map(DEBAYER_ENABLE => DEBAYER_ENABLE,
FIFO_DEPTH => FIFO_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => avalon_mm_slave_clk_in,
reset => avalon_mm_slave_reset_in,
addr => avalon_mm_slave_addr_in,
read => avalon_mm_slave_read_in,
write => avalon_mm_slave_write_in,
rddata => avalon_mm_slave_rddata_out,
wrdata => avalon_mm_slave_wrdata_in,
irq => avalon_mm_slave_irq_out,
idle => avalon_mm_slave_idle_in,
snapshot => avalon_mm_slave_snapshot_out,
get_frame_info => avalon_mm_slave_get_frame_info_out,
irq_en => avalon_mm_slave_irq_en_out,
irq_ack => avalon_mm_slave_irq_ack_out,
wait_irq_ack => avalon_mm_slave_wait_irq_ack_in,
frame_width => avalon_mm_slave_frame_width_in,
frame_height => avalon_mm_slave_frame_height_in,
debayer_pattern => avalon_mm_slave_debayer_pattern_out,
fifo_usedw => avalon_mm_slave_fifo_usedw_in,
fifo_overflow => avalon_mm_slave_fifo_overflow_in,
stop_and_reset => avalon_mm_slave_stop_and_reset_out);
cmos_sensor_input_synchronizer_inst : entity work.cmos_sensor_input_synchronizer
generic map(PIX_DEPTH => PIX_DEPTH,
SAMPLE_EDGE => SAMPLE_EDGE)
port map(clk => synchronizer_clk_in,
reset => synchronizer_reset_in,
frame_valid_in => synchronizer_frame_valid_in_in,
line_valid_in => synchronizer_line_valid_in_in,
data_in => synchronizer_data_in_in,
frame_valid_out => synchronizer_frame_valid_out_out,
line_valid_out => synchronizer_line_valid_out_out,
data_out => synchronizer_data_out_out);
cmos_sensor_input_sampler_inst : entity work.cmos_sensor_input_sampler
generic map(PIX_DEPTH => PIX_DEPTH,
MAX_WIDTH => MAX_WIDTH,
MAX_HEIGHT => MAX_HEIGHT)
port map(clk => sampler_clk_in,
reset => sampler_reset_in,
stop_and_reset => sampler_stop_and_reset_in,
idle => sampler_idle_out,
wait_irq_ack => sampler_wait_irq_ack_out,
irq_en => sampler_irq_en_in,
irq_ack => sampler_irq_ack_in,
snapshot => sampler_snapshot_in,
get_frame_info => sampler_get_frame_info_in,
frame_width => sampler_frame_width_out,
frame_height => sampler_frame_height_out,
frame_valid => sampler_frame_valid_in,
line_valid => sampler_line_valid_in,
data_in => sampler_data_in_in,
valid_out => sampler_valid_out_out,
data_out => sampler_data_out_out,
start_of_frame_out => sampler_start_of_frame_out_out,
end_of_frame_out => sampler_end_of_frame_out_out,
fifo_overflow => sampler_fifo_overflow_in,
end_of_frame_in => sampler_end_of_frame_in_in,
end_of_frame_in_ack => sampler_end_of_frame_in_ack_out);
debayer_inst : if DEBAYER_ENABLE generate
cmos_sensor_input_debayer_inst : entity work.cmos_sensor_input_debayer
generic map(PIX_DEPTH_RAW => PIX_DEPTH,
PIX_DEPTH_RGB => PIX_DEPTH_RGB,
MAX_WIDTH => MAX_WIDTH)
port map(clk => debayer_clk_in,
reset => debayer_reset_in,
stop_and_reset => debayer_stop_and_reset_in,
debayer_pattern => debayer_debayer_pattern_in,
valid_in => debayer_valid_in_in,
data_in => debayer_data_in_in,
start_of_frame_in => debayer_start_of_frame_in_in,
end_of_frame_in => debayer_end_of_frame_in_in,
valid_out => debayer_valid_out_out,
data_out => debayer_data_out_out,
start_of_frame_out => debayer_start_of_frame_out_out,
end_of_frame_out => debayer_end_of_frame_out_out);
end generate debayer_inst;
packer_inst : if PACKER_ENABLE generate
packer_raw : if not DEBAYER_ENABLE generate
cmos_sensor_input_packer_inst : entity work.cmos_sensor_input_packer
generic map(PIX_DEPTH => PIX_DEPTH,
PACK_WIDTH => OUTPUT_WIDTH)
port map(clk => packer_raw_clk_in,
reset => packer_raw_reset_in,
stop_and_reset => packer_raw_stop_and_reset_in,
valid_in => packer_raw_valid_in_in,
data_in => packer_raw_data_in_in,
start_of_frame_in => packer_raw_start_of_frame_in_in,
end_of_frame_in => packer_raw_end_of_frame_in_in,
valid_out => packer_raw_valid_out_out,
data_out => packer_raw_data_out_out,
end_of_frame_out => packer_raw_end_of_frame_out_out);
end generate packer_raw;
packer_rgb : if DEBAYER_ENABLE generate
cmos_sensor_input_packer_inst : entity work.cmos_sensor_input_packer
generic map(PIX_DEPTH => PIX_DEPTH_RGB,
PACK_WIDTH => OUTPUT_WIDTH)
port map(clk => packer_rgb_clk_in,
reset => packer_rgb_reset_in,
stop_and_reset => packer_rgb_stop_and_reset_in,
valid_in => packer_rgb_valid_in_in,
data_in => packer_rgb_data_in_in,
start_of_frame_in => packer_rgb_start_of_frame_in_in,
end_of_frame_in => packer_rgb_end_of_frame_in_in,
valid_out => packer_rgb_valid_out_out,
data_out => packer_rgb_data_out_out,
end_of_frame_out => packer_rgb_end_of_frame_out_out);
end generate packer_rgb;
end generate packer_inst;
cmos_sensor_input_sc_fifo_inst : entity work.cmos_sensor_input_sc_fifo
generic map(DATA_WIDTH => FIFO_DATA_WIDTH,
FIFO_DEPTH => FIFO_DEPTH,
DEVICE_FAMILY => DEVICE_FAMILY)
port map(clk => sc_fifo_clk_in,
reset => sc_fifo_reset_in,
clr => sc_fifo_clr_in,
data_in => sc_fifo_data_in_in,
data_out => sc_fifo_data_out_out,
read => sc_fifo_read_in,
write => sc_fifo_write_in,
empty => sc_fifo_empty_out,
full => sc_fifo_full_out,
usedw => sc_fifo_usedw_out,
overflow => sc_fifo_overflow_out);
cmos_sensor_input_avalon_st_source_inst : entity work.cmos_sensor_input_avalon_st_source
generic map(DATA_WIDTH => OUTPUT_WIDTH)
port map(clk => avalon_st_source_clk_in,
reset => avalon_st_source_reset_in,
stop_and_reset => avalon_st_source_stop_and_reset_in,
ready => avalon_st_source_ready_in,
valid => avalon_st_source_valid_out,
data => avalon_st_source_data_out,
fifo_read => avalon_st_source_fifo_read_out,
fifo_empty => avalon_st_source_fifo_empty_in,
fifo_data => avalon_st_source_fifo_data_in,
fifo_end_of_frame => avalon_st_source_fifo_end_of_frame_in,
fifo_overflow => avalon_st_source_fifo_overflow_in,
end_of_frame_out => avalon_st_source_end_of_frame_out_out,
end_of_frame_out_ack => avalon_st_source_end_of_frame_out_ack_in);
TOP_LEVEL_INTERNALS_CONNECTIONS : process(addr, avalon_mm_slave_debayer_pattern_out, avalon_mm_slave_get_frame_info_out, avalon_mm_slave_irq_ack_out, avalon_mm_slave_irq_en_out, avalon_mm_slave_snapshot_out, avalon_mm_slave_stop_and_reset_out, avalon_st_source_end_of_frame_out_out, avalon_st_source_fifo_read_out, clk, data_in, debayer_data_out_out, debayer_end_of_frame_out_out, debayer_start_of_frame_out_out, debayer_valid_out_out, frame_valid, line_valid, packer_raw_data_out_out, packer_raw_end_of_frame_out_out, packer_raw_valid_out_out, packer_rgb_data_out_out, packer_rgb_end_of_frame_out_out, packer_rgb_valid_out_out, read, ready, reset, sampler_data_out_out, sampler_end_of_frame_in_ack_out, sampler_end_of_frame_out_out, sampler_frame_height_out, sampler_frame_width_out, sampler_idle_out, sampler_start_of_frame_out_out, sampler_valid_out_out, sampler_wait_irq_ack_out, sc_fifo_data_out_out, sc_fifo_empty_out, sc_fifo_overflow_out, sc_fifo_usedw_out, synchronizer_data_out_out, synchronizer_frame_valid_out_out, synchronizer_line_valid_out_out, wrdata, write)
begin
-- always existing top-level connections -------------------------------
avalon_mm_slave_clk_in <= clk;
avalon_mm_slave_reset_in <= reset;
avalon_mm_slave_addr_in <= addr;
avalon_mm_slave_read_in <= read;
avalon_mm_slave_write_in <= write;
avalon_mm_slave_wrdata_in <= wrdata;
avalon_mm_slave_idle_in <= sampler_idle_out;
avalon_mm_slave_wait_irq_ack_in <= sampler_wait_irq_ack_out;
avalon_mm_slave_frame_width_in <= sampler_frame_width_out;
avalon_mm_slave_frame_height_in <= sampler_frame_height_out;
avalon_mm_slave_fifo_usedw_in <= sc_fifo_usedw_out;
avalon_mm_slave_fifo_overflow_in <= sc_fifo_overflow_out;
synchronizer_clk_in <= clk;
synchronizer_reset_in <= reset;
synchronizer_frame_valid_in_in <= frame_valid;
synchronizer_line_valid_in_in <= line_valid;
synchronizer_data_in_in <= data_in;
sampler_clk_in <= clk;
sampler_reset_in <= reset;
sampler_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
sampler_irq_en_in <= avalon_mm_slave_irq_en_out;
sampler_irq_ack_in <= avalon_mm_slave_irq_ack_out;
sampler_snapshot_in <= avalon_mm_slave_snapshot_out;
sampler_get_frame_info_in <= avalon_mm_slave_get_frame_info_out;
sampler_frame_valid_in <= synchronizer_frame_valid_out_out;
sampler_line_valid_in <= synchronizer_line_valid_out_out;
sampler_data_in_in <= synchronizer_data_out_out;
sampler_fifo_overflow_in <= sc_fifo_overflow_out;
sampler_end_of_frame_in_in <= avalon_st_source_end_of_frame_out_out;
debayer_clk_in <= clk;
debayer_reset_in <= reset;
debayer_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
debayer_debayer_pattern_in <= avalon_mm_slave_debayer_pattern_out;
packer_raw_clk_in <= clk;
packer_raw_reset_in <= reset;
packer_raw_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
packer_rgb_clk_in <= clk;
packer_rgb_reset_in <= reset;
packer_rgb_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
sc_fifo_clk_in <= clk;
sc_fifo_reset_in <= reset;
sc_fifo_clr_in <= avalon_mm_slave_stop_and_reset_out;
sc_fifo_read_in <= avalon_st_source_fifo_read_out;
avalon_st_source_clk_in <= clk;
avalon_st_source_reset_in <= reset;
avalon_st_source_stop_and_reset_in <= avalon_mm_slave_stop_and_reset_out;
avalon_st_source_ready_in <= ready;
avalon_st_source_fifo_empty_in <= sc_fifo_empty_out;
avalon_st_source_fifo_data_in <= sc_fifo_data_out_out(avalon_st_source_fifo_data_in'range);
avalon_st_source_fifo_end_of_frame_in <= sc_fifo_data_out_out(FIFO_END_OF_FRAME_BIT_OFST);
avalon_st_source_fifo_overflow_in <= sc_fifo_overflow_out;
avalon_st_source_end_of_frame_out_ack_in <= sampler_end_of_frame_in_ack_out;
-- default values for "configurable" signals ---------------------------
debayer_valid_in_in <= '0';
debayer_data_in_in <= (others => '0');
debayer_start_of_frame_in_in <= '0';
debayer_end_of_frame_in_in <= '0';
packer_raw_valid_in_in <= '0';
packer_raw_data_in_in <= (others => '0');
packer_raw_start_of_frame_in_in <= '0';
packer_raw_end_of_frame_in_in <= '0';
packer_rgb_valid_in_in <= '0';
packer_rgb_data_in_in <= (others => '0');
packer_rgb_start_of_frame_in_in <= '0';
packer_rgb_end_of_frame_in_in <= '0';
sc_fifo_write_in <= '0';
sc_fifo_data_in_in <= (others => '0');
if not DEBAYER_ENABLE and not PACKER_ENABLE then
sc_fifo_write_in <= sampler_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(sampler_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= sampler_end_of_frame_out_out;
elsif not DEBAYER_ENABLE and PACKER_ENABLE then
packer_raw_valid_in_in <= sampler_valid_out_out;
packer_raw_data_in_in <= sampler_data_out_out;
packer_raw_start_of_frame_in_in <= sampler_start_of_frame_out_out;
packer_raw_end_of_frame_in_in <= sampler_end_of_frame_out_out;
sc_fifo_write_in <= packer_raw_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(packer_raw_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= packer_raw_end_of_frame_out_out;
elsif DEBAYER_ENABLE and not PACKER_ENABLE then
debayer_valid_in_in <= sampler_valid_out_out;
debayer_data_in_in <= sampler_data_out_out;
debayer_start_of_frame_in_in <= sampler_start_of_frame_out_out;
debayer_end_of_frame_in_in <= sampler_end_of_frame_out_out;
sc_fifo_write_in <= debayer_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(debayer_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= debayer_end_of_frame_out_out;
elsif DEBAYER_ENABLE and PACKER_ENABLE then
debayer_valid_in_in <= sampler_valid_out_out;
debayer_data_in_in <= sampler_data_out_out;
debayer_start_of_frame_in_in <= sampler_start_of_frame_out_out;
debayer_end_of_frame_in_in <= sampler_end_of_frame_out_out;
packer_rgb_valid_in_in <= debayer_valid_out_out;
packer_rgb_data_in_in <= debayer_data_out_out;
packer_rgb_start_of_frame_in_in <= debayer_start_of_frame_out_out;
packer_rgb_end_of_frame_in_in <= debayer_end_of_frame_out_out;
sc_fifo_write_in <= packer_rgb_valid_out_out;
sc_fifo_data_in_in <= std_logic_vector(resize(unsigned(packer_rgb_data_out_out), FIFO_DATA_WIDTH));
sc_fifo_data_in_in(FIFO_END_OF_FRAME_BIT_OFST) <= packer_rgb_end_of_frame_out_out;
end if;
end process;
end architecture rtl;
|
unlicense
|
11c2c918071d6cf5d964b0bc3b2a2dea
| 0.543756 | 3.580986 | false | false | false | false |
thelonious/display4
|
seven_segment.vhd
| 1 | 1,192 |
--
-- Copyright 2011, Kevin Lindsey
-- See LICENSE file for licensing information
--
library ieee;
use ieee.std_logic_1164.all;
entity SevenSegment is
port(
clock: in std_logic;
num: in std_logic_vector(3 downto 0);
segments: out std_logic_vector(6 downto 0)
);
end SevenSegment;
architecture behavioral of SevenSegment is
begin
display: process(clock)
begin
if clock'event and clock='1' then
case num is
when "0000" => segments <= "1000000";
when "0001" => segments <= "1111001";
when "0010" => segments <= "0100100";
when "0011" => segments <= "0110000";
when "0100" => segments <= "0011001";
when "0101" => segments <= "0010010";
when "0110" => segments <= "0000010";
when "0111" => segments <= "1111000";
when "1000" => segments <= "0000000";
when "1001" => segments <= "0011000";
when "1010" => segments <= "0001000";
when "1011" => segments <= "0000011";
when "1100" => segments <= "1000110";
when "1101" => segments <= "0100001";
when "1110" => segments <= "0000110";
when "1111" => segments <= "0001110";
when others => segments <= "1111111";
end case;
end if;
end process;
end behavioral;
|
bsd-3-clause
|
a6094c25db27cd869449fb43ac1793ec
| 0.619128 | 3.425287 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task5/clk_res_gen.vhd
| 2 | 907 |
library ieee;
use ieee.std_logic_1164.all;
entity clk_res_gen is
port(
clk_50 : out std_logic;
rst : out std_logic
);
end entity clk_res_gen;
architecture RTL of clk_res_gen is
begin
-- This process generates a 50MHz clock signal
p_clk_generate : process
begin
while TRUE loop
clk_50 <= '0';
wait for 10 ns;
clk_50 <= '1';
wait for 10 ns;
end loop;
end process p_clk_generate;
p_report_sim_progress : process
variable sim_time : integer := 0;
begin
while TRUE loop
--report "Simulation time in ns is " & integer'image(sim_time);
wait for 10 ns;
sim_time := sim_time + 10;
end loop;
end process p_report_sim_progress;
-- This process generate a test reset signal and enables the design after 15 ns
p_res_generate : process
begin
rst <= '1';
wait for 15 ns;
rst <= '0';
wait for 5000 ms;
end process p_res_generate;
end architecture RTL;
|
mit
|
0c05880ef8ed0d36feeb64d71b151bba
| 0.665932 | 2.935275 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task5/toplevel.vhd
| 1 | 4,549 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
entity toplevel is
port(
clk : in std_logic;
rst : in std_logic;
ps2Data : in std_logic;
ps2Clk : in std_logic;
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_db : out std_logic_vector(7 downto 0)
);
end entity toplevel;
architecture RTL of toplevel is
signal rxData : std_logic_vector(7 downto 0);
signal asciiData : std_logic_vector(7 downto 0);
signal asciiDataBig : std_logic_vector(7 downto 0);
signal dataReady : std_logic;
signal dataReadydly : std_logic;
signal dataFetched : std_logic;
signal released : std_logic;
signal line_buffer : std_logic_vector(255 downto 0);
signal pos : natural;
signal shifta : std_logic;
signal shiftb : std_logic;
begin
inst_ps2Recv : entity work.ps2Receiver
port map(
clk => clk,
rst => rst,
rxData => rxData,
dataReady => dataReady,
dataFetched => dataFetched,
ps2Data => ps2Data,
ps2Clk => ps2Clk);
dataFetched <= '1';
inst_lcd : entity work.lcd16x2_ctrl
port map(
clk => clk,
rst => rst,
lcd_e => lcd_e,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw,
lcd_db => lcd_db(7 downto 4),
line1_buffer => line_buffer(255 downto 128),
line2_buffer => line_buffer(127 downto 0));
lcd_db(3 downto 0) <= (others => '1');
pos_counter: process(clk, rst)
begin
if rst = '1' then
pos <= 31;
released <= '0';
line_buffer <= X"2020202020202020202020202020202020202020202020202020202020202020";
shifta <= '0';
shiftb <= '0';
elsif rising_edge(clk) then
dataReadydly <= dataReady;
if dataReady = '1' and dataReadydly = '0' then
if rxData = X"F0" then
released <= '1';
elsif released = '1' then
if rxData = X"12" then
shifta <= '0';
elsif rxData = X"59" then
shiftb <= '0';
end if;
released <= '0';
else
if rxData = X"12" then
shifta <= '1';
elsif rxData = X"59" then
shiftb <= '1';
else
line_buffer((pos*8)+7 downto pos*8) <= asciiDataBig;
if pos = 0 then
pos <= 32;
else
pos <= pos - 1;
end if;
end if;
end if;
end if;
end if;
end process pos_counter;
asciiData <=
X"61" when rxData = X"1C" else --a
X"62" when rxData = X"32" else
X"63" when rxData = X"21" else
X"64" when rxData = X"23" else
X"65" when rxData = X"24" else
X"66" when rxData = X"2B" else
X"67" when rxData = X"34" else
X"68" when rxData = X"33" else
X"69" when rxData = X"43" else
X"6A" when rxData = X"3B" else
X"6B" when rxData = X"42" else
X"6C" when rxData = X"4B" else
X"6D" when rxData = X"3A" else
X"6E" when rxData = X"31" else
X"6F" when rxData = X"44" else
X"70" when rxData = X"4D" else
X"71" when rxData = X"15" else
X"72" when rxData = X"2D" else
X"73" when rxData = X"1B" else
X"74" when rxData = X"2C" else
X"75" when rxData = X"3C" else
X"76" when rxData = X"2A" else
X"77" when rxData = X"1D" else
X"78" when rxData = X"22" else
X"79" when rxData = X"35" else
X"7A" when rxData = X"1A" else
X"30" when rxData = X"45" else --0
X"31" when rxData = X"16" else
X"32" when rxData = X"1E" else
X"33" when rxData = X"26" else
X"34" when rxData = X"25" else
X"35" when rxData = X"2E" else
X"36" when rxData = X"36" else
X"37" when rxData = X"3D" else
X"38" when rxData = X"3E" else
X"39" when rxData = X"46" else
X"20" when rxData = X"29" else
X"FF";
asciiDataBig <= asciiData - X"20" when shifta = '1' or shiftb = '1' else
asciiData;
end architecture RTL;
|
mit
|
8a001a50b898220db8c9e8f7d2932b49
| 0.485162 | 3.529092 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
cmos_sensor_input/hdl/cmos_sensor_input_packer.vhd
| 5 | 3,601 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_input_constants.all;
entity cmos_sensor_input_packer is
generic(
PIX_DEPTH : positive;
PACK_WIDTH : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- avalon_mm_slave
stop_and_reset : in std_logic;
-- sampler / debayer
valid_in : in std_logic;
data_in : in std_logic_vector(PIX_DEPTH - 1 downto 0);
start_of_frame_in : in std_logic;
end_of_frame_in : in std_logic;
-- fifo
valid_out : out std_logic;
data_out : out std_logic_vector(PACK_WIDTH - 1 downto 0);
end_of_frame_out : out std_logic
);
end entity cmos_sensor_input_packer;
architecture rtl of cmos_sensor_input_packer is
constant COMPRESSED_PIX_COUNT : positive := floor_div(data_out'length, PIX_DEPTH);
signal reg_count : unsigned(bit_width(COMPRESSED_PIX_COUNT) - 1 downto 0);
signal reg_data_out : std_logic_vector((COMPRESSED_PIX_COUNT - 1) * PIX_DEPTH - 1 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
reg_count <= (others => '0');
reg_data_out <= (others => '0');
elsif rising_edge(clk) then
valid_out <= '0';
data_out <= (others => '0');
end_of_frame_out <= '0';
if stop_and_reset = '1' then
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
else
if valid_in = '1' then
if start_of_frame_in = '1' then
reg_count <= to_unsigned(1, reg_count'length);
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= (others => '0');
elsif end_of_frame_in = '1' then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
end_of_frame_out <= '1';
reg_count <= to_unsigned(0, reg_count'length);
elsif reg_count < COMPRESSED_PIX_COUNT - 1 then
reg_count <= reg_count + 1;
reg_data_out(PIX_DEPTH - 1 downto 0) <= data_in;
reg_data_out(reg_data_out'length - 1 downto PIX_DEPTH) <= reg_data_out(reg_data_out'length - PIX_DEPTH - 1 downto 0);
elsif reg_count = COMPRESSED_PIX_COUNT - 1 then
valid_out <= '1';
data_out(PIX_DEPTH - 1 downto 0) <= data_in;
data_out(reg_data_out'length + PIX_DEPTH - 1 downto PIX_DEPTH) <= reg_data_out;
reg_count <= to_unsigned(0, reg_count'length);
reg_data_out <= (others => '0');
end if;
end if;
end if;
end if;
end process;
end architecture rtl;
|
unlicense
|
c37acc163292b7b8df290be98fa18249
| 0.440989 | 4.059752 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
i2c/hdl/i2c_clkgen.vhd
| 5 | 2,023 |
--------------------------------------------------------------------
-- i2c_clkgen.vhd -- I2C base clock generator
-- with clock stretching feature
-- generate 1 pulse every clk_cnt clk cycles, for 1 clk duration
--------------------------------------------------------------------
-- Author : Cédric Gaudin
-- Version : 0.2 alpha
-- History :
-- 20-apr-2002 CG 0.1 Initial alpha release
-- 27-apr-2002 CG 0.2 minor cosmetic changes
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity i2c_clkgen is
port(
signal clk : in std_logic;
signal rst : in std_logic;
-- count used for dividing clk signal
signal clk_cnt : in std_logic_vector(7 downto 0);
-- I2C clock output generated
signal sclk : out std_logic;
-- I2C clock line SCL (used for clock stretching)
signal scl_in : in std_logic;
signal scl_out : in std_logic
);
end i2c_clkgen;
architecture behavioral of i2c_clkgen is
signal clk_ctr : unsigned(7 downto 0);
signal clk_wait : std_logic;
signal i_clk_out : std_logic;
begin
sclk <= i_clk_out;
process(clk, rst)
begin
if (rst = '1') then
clk_ctr <= (others => '0');
i_clk_out <= '1';
elsif (rising_edge(clk)) then
if (clk_ctr >= unsigned(clk_cnt)) then
clk_ctr <= (others => '0');
i_clk_out <= '1';
else
if (clk_wait = '0') then
clk_ctr <= clk_ctr + 1;
end if;
i_clk_out <= '0';
end if;
end if;
end process;
-- clk_wait <= '1' when (scl_out = '1' and scl_in = '0') else '0'; -- problem rencontres avec ce mode
clk_wait <= '0';
end behavioral;
|
unlicense
|
41c5e27bbda24c9f6ba44ba2d04e5d26
| 0.463897 | 3.822306 | false | false | false | false |
quartushaters/project
|
M1/Part 1/LCD_Display.vhd
| 1 | 9,000 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of live Hex hardware data values to display
-- (do not count ASCII character constants)
GENERIC(Num_Hex_Digits: Integer:= 8);
-----------------------------------------------------------------------
-- LCD Displays 16 Characters on 2 lines
-- LCD_display string is an ASCII character string entered in hex for
-- the two lines of the LCD Display (See ASCII to hex table below)
-- Edit LCD_Display_String entries above to modify display
-- Enter the ASCII character's 2 hex digit equivalent value
-- (see table below for ASCII hex values)
-- To display character assign ASCII value to LCD_display_string(x)
-- To skip a character use X"20" (ASCII space)
-- To dislay "live" hex values from hardware on LCD use the following:
-- make array element for that character location X"0" & 4-bit field from Hex_Display_Data
-- state machine sees X"0" in high 4-bits & grabs the next lower 4-bits from Hex_Display_Data input
-- and performs 4-bit binary to ASCII conversion needed to print a hex digit
-- Num_Hex_Digits must be set to the count of hex data characters (ie. "00"s) in the display
-- Connect hardware bits to display to Hex_Display_Data input
-- To display less than 32 characters, terminate string with an entry of X"FE"
-- (fewer characters may slightly increase the LCD's data update rate)
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is X"41"
-- *see LCD Controller's Datasheet for other graphics characters available
--
PORT(reset, clk_48Mhz : IN STD_LOGIC;
Hex_Display_Data : IN STD_LOGIC_VECTOR((Num_Hex_Digits*4)-1 DOWNTO 0);
Display_Data : IN STD_LOGIC_VECTOR(((Num_Hex_Digits*4)*4)-1 DOWNTO 0);
LCD_RS, LCD_EN : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY LCD_Display;
ARCHITECTURE a OF LCD_Display IS
TYPE character_string IS ARRAY ( 0 TO 31 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, Print_String,
LINE2, RETURN_HOME, DROP_LCD_EN, RESET1, RESET2,
RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL LCD_display_string : character_string;
-- Enter new ASCII hex data above for LCD Display
SIGNAL DATA_BUS_VALUE, Next_Char: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL CHAR_COUNT: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL CLK_400HZ_Enable,LCD_RW_INT : STD_LOGIC;
SIGNAL Line1_chars, Line2_chars: STD_LOGIC_VECTOR(127 DOWNTO 0);
BEGIN
LCD_display_string <= (
-- ASCII hex values for LCD Display
-- Enter Live Hex Data Values from hardware here
-- LCD DISPLAYS THE FOLLOWING:
------------------------------
--| Count=XX |
--| Data =XXXXXXXX |
------------------------------
-- Line 1
X"43",X"6F",X"75",X"6E",X"74",X"3D",
X"0" & Hex_Display_Data(7 DOWNTO 4),X"0" & Hex_Display_Data(3 DOWNTO 0),
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 2
X"44",X"41",X"54",X"41",X"20",X"3D",
X"0" & Display_Data(31 DOWNTO 28),
X"0" & Display_Data(27 DOWNTO 24),
X"0" & Display_Data(23 DOWNTO 20),
X"0" & Display_Data(19 DOWNTO 16),
X"0" & Display_Data(15 DOWNTO 12),
X"0" & Display_Data(11 DOWNTO 8),
X"0" & Display_Data(7 DOWNTO 4),
X"0" & Display_Data(3 DOWNTO 0),
X"20",X"20");
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
DATA_BUS <= DATA_BUS_VALUE WHEN LCD_RW_INT = '0' ELSE "ZZZZZZZZ";
-- get next character in display string
Next_Char <= LCD_display_string(CONV_INTEGER(CHAR_COUNT));
LCD_RW <= LCD_RW_INT;
PROCESS
BEGIN
WAIT UNTIL CLK_48MHZ'EVENT AND CLK_48MHZ = '1';
IF RESET = '0' THEN
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '0';
ELSE
IF CLK_COUNT_400HZ < X"0EA60" THEN
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1;
CLK_400HZ_Enable <= '0';
ELSE
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (CLK_48MHZ, reset)
BEGIN
IF reset = '0' THEN
state <= RESET1;
DATA_BUS_VALUE <= X"38";
next_command <= RESET2;
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '1';
ELSIF CLK_48MHZ'EVENT AND CLK_48MHZ = '1' THEN
-- State Machine to send commands and data to LCD DISPLAY
IF CLK_400HZ_Enable = '1' THEN
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= RESET2;
CHAR_COUNT <= "00000";
WHEN RESET2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= RESET3;
WHEN RESET3 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"08";
state <= DROP_LCD_EN;
next_command <= DISPLAY_CLEAR;
-- Clear Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"01";
state <= DROP_LCD_EN;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"0C";
state <= DROP_LCD_EN;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"06";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- Write ASCII hex character in first LCD character location
WHEN Print_String =>
state <= DROP_LCD_EN;
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW_INT <= '0';
-- ASCII character to output
IF Next_Char(7 DOWNTO 4) /= X"0" THEN
DATA_BUS_VALUE <= Next_Char;
ELSE
-- Convert 4-bit value to an ASCII hex digit
IF Next_Char(3 DOWNTO 0) >9 THEN
-- ASCII A...F
DATA_BUS_VALUE <= X"4" & (Next_Char(3 DOWNTO 0)-9);
ELSE
-- ASCII 0...9
DATA_BUS_VALUE <= X"3" & Next_Char(3 DOWNTO 0);
END IF;
END IF;
state <= DROP_LCD_EN;
-- Loop to send out 32 characters to LCD Display (16 by 2 lines)
IF (CHAR_COUNT < 31) AND (Next_Char /= X"FE") THEN
CHAR_COUNT <= CHAR_COUNT +1;
ELSE
CHAR_COUNT <= "00000";
END IF;
-- Jump to second line?
IF CHAR_COUNT = 15 THEN next_command <= line2;
-- Return to first line?
ELSIF (CHAR_COUNT = 31) OR (Next_Char = X"FE") THEN
next_command <= return_home;
ELSE next_command <= Print_String; END IF;
-- Set write address to line 2 character 1
WHEN LINE2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"C0";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- Return write address to first character postion on line 1
WHEN RETURN_HOME =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"80";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- The next three states occur at the end of each command or data transfer to the LCD
-- Drop LCD E line - falling edge loads inst/data to LCD controller
WHEN DROP_LCD_EN =>
LCD_EN <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END IF;
END PROCESS;
END a;
|
gpl-2.0
|
94eb3bc8196a71464c199ac27368ab5e
| 0.568333 | 3.032345 | false | false | false | false |
notti/schaltungstechnik_vertiefung
|
Assignement/Task2/uart_top_shell.vhd
| 1 | 2,991 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:04:42 10/01/2013
-- Design Name:
-- Module Name: uart_top_shell - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity uart_top_shell is
port(
rst_i : in std_logic;
clk_i : in std_logic;
rx_i : in std_logic;
tx_o : out std_logic
);
end uart_top_shell;
architecture Behavioral of uart_top_shell is
component clock_gen is
port (
rst_i : in std_logic;
clk_i : in std_logic;
ClrDiv_i : in std_logic;
TopRx : out std_logic;
TopTx : out std_logic;
Top16 : out std_logic;
Baud : in std_logic_vector(2 downto 0)
);
end component clock_gen;
component uart_receive is
port (
rst_i : in std_logic;
clk_i : in std_logic;
ClrDiv_o : out std_logic;
Top16_i : std_logic;
TopRx_i : std_logic;
Dout_o : out std_logic_vector(7 downto 0);
Recvd : out std_logic;
Rx_i : in std_logic
);
end component uart_receive;
component uart_transmit is
port (
rst_i : in std_logic;
clk_i : in std_logic;
TopTX : in std_logic;
Din_i : in std_logic_vector(7 downto 0);
Tx_o : out std_logic;
TxBusy_o: out std_logic;
LD_i : in std_logic
);
end component uart_transmit;
constant c_baud : std_logic_vector(2 downto 0) := "000";
signal s_toprx : std_logic;
signal s_toptx : std_logic;
signal s_top16 : std_logic;
signal s_dout : std_logic_vector(7 downto 0);
signal s_txbusy : std_logic;
signal s_clr_div : std_logic;
signal s_recvd : std_logic;
begin
i_clock_gen : clock_gen
port map (
rst_i => rst_i,
clk_i => clk_i,
ClrDiv_i => s_clr_div,
TopRx => s_toprx,
TopTx => s_toptx,
Top16 => s_top16,
Baud => c_baud
);
i_uart_rec : uart_receive
port map (
rst_i => rst_i,
clk_i => clk_i,
ClrDiv_o => s_clr_div,
Top16_i => s_top16,
TopRx_i => s_toprx,
Dout_o => s_dout,
Recvd => s_recvd,
Rx_i => rx_i
);
i_uart_tra : uart_transmit
port map (
rst_i => rst_i,
clk_i => clk_i,
TopTX => s_toptx,
Din_i => s_dout,
Tx_o => tx_o,
TxBusy_o => s_txbusy,
LD_i => s_recvd
);
end Behavioral;
|
mit
|
eaf2f46e7d6bb03b35723651814b92e6
| 0.535607 | 3.158395 | false | false | false | false |
samvartaka/simon_vhdl
|
MIXED_ROUND_PIPELINING/neg_reg_32.vhd
| 3 | 922 |
-- SIMON 64/128
-- negative-edge triggered inner-round pipelining word (32-bit) registry
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- data_in: registry input
-- data_out: registry output
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity neg_reg_32 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0)
);
end neg_reg_32;
architecture Behavioral of neg_reg_32 is
signal neg_reg_32_s : std_logic_vector(31 downto 0);
begin
pr_reg: process(clk)
begin
-- triggers on negative edge
if falling_edge(clk) then
if rst = '1' then
neg_reg_32_s <= (others => '0');
else
neg_reg_32_s <= data_in;
end if;
end if;
end process;
data_out <= neg_reg_32_s;
end Behavioral;
|
gpl-2.0
|
97d20cfbde3f172295d6d3b920a78483
| 0.630152 | 2.926984 | false | false | false | false |
sahandKashani/HDL-IP-cores
|
fwft_fifo/hdl/fwft_fifo.vhd
| 1 | 3,777 |
-- Slightly modified from original source from [email protected]:
-- http://www.deathbylogic.com/2015/01/vhdl-first-word-fall-through-fifo/
--
-- Added usedw output to know how many words are currently stored in the fifo.
-- Added async reset port (useful for some designs)
-- Reset internal memory as well when receiving async reset or sync clr.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity fwft_fifo is
generic(
DATA_WIDTH : positive := 8;
FIFO_DEPTH : positive := 256
);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
write_en : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
read_en : in std_logic;
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
empty : out std_logic;
full : out std_logic;
usedw : out std_logic_vector(integer(ceil(log2(real(FIFO_DEPTH + 1)))) - 1 downto 0)
);
end fwft_fifo;
architecture behavioral of fwft_fifo is
begin
-- memory pointer process
fifo_proc : process(clk, reset)
type fifo_memory is array (0 to FIFO_DEPTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0);
variable memory : fifo_memory;
variable head : natural range 0 to FIFO_DEPTH - 1;
variable tail : natural range 0 to FIFO_DEPTH - 1;
variable fill_level : natural range 0 to FIFO_DEPTH;
variable looped : boolean;
begin
if reset = '1' then
head := 0;
tail := 0;
fill_level := 0;
looped := false;
full <= '0';
empty <= '1';
elsif rising_edge(clk) then
if clr = '1' then
head := 0;
tail := 0;
fill_level := 0;
looped := false;
full <= '0';
empty <= '1';
else
if (read_en = '1') then
if ((looped = true) or (head /= tail)) then
fill_level := fill_level - 1;
-- update tail pointer as needed
if (tail = FIFO_DEPTH - 1) then
tail := 0;
looped := false;
else
tail := tail + 1;
end if;
end if;
end if;
if (write_en = '1') then
if ((looped = false) or (head /= tail)) then
-- write data to memory
memory(head) := data_in;
fill_level := fill_level + 1;
-- increment head pointer as needed
if (head = FIFO_DEPTH - 1) then
head := 0;
looped := true;
else
head := head + 1;
end if;
end if;
end if;
-- update data output
data_out <= memory(tail);
usedw <= std_logic_vector(to_unsigned(fill_level, usedw'length));
-- update empty and full flags
if (head = tail) then
if looped then
full <= '1';
else
empty <= '1';
end if;
else
empty <= '0';
full <= '0';
end if;
end if;
end if;
end process;
end behavioral;
|
unlicense
|
e2722c5b481a6e3b77a08c12dcaa202f
| 0.435266 | 4.550602 | false | false | false | false |
samvartaka/simon_vhdl
|
ITERATIVE/ITERATIVE_SEPERATE_RAMROUTE/simon.vhd
| 1 | 4,275 |
-- SIMON 64/128
-- Simon core component (encryption and decryption presume pre-expansion of key to RAM)
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic_vector(1 downto 0); -- state indicator (11 = init, 01 = pre-expand, 00 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component round_f is
port(v_in : in std_logic_vector(63 downto 0);
v_k : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
end component;
component key_schedule is
port (r : in std_logic_vector(7 downto 0);
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end component;
component ram is
port (data_in : in std_logic_vector(31 downto 0);
rw : in std_logic;
clk : in std_logic;
address : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(31 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal r_s : std_logic_vector(7 downto 0); -- round index
signal key_s : key_t; -- intermediate key (in words)
signal subkey_out_s : std_logic_vector(31 downto 0); -- round key
signal v_in_s : std_logic_vector(63 downto 0); -- intermediate 'plaintext'
signal v_out_s : std_logic_vector(63 downto 0); -- intermediate 'ciphertext'
signal ram_rw : std_logic;
signal ram_data_out : std_logic_vector(31 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (r_s, key_s(0), key_s(1), key_s(3), subkey_out_s);
ROUND_F_0 : round_f port map (v_in_s, ram_data_out, v_out_s);
-- round index is used as ram address, round key is ram input
RAM_0 : ram port map (subkey_out_s, ram_rw, clk, r_s, ram_data_out);
pr_r : process(clk, rst)
begin
if rising_edge(clk) then
-- initialization clock
if rst = "11" then
r_s <= (others => '0');
-- pre-expansion clock
elsif rst = "01" then
if (r_s = X"2B") then
if (enc = '0') then
r_s <= (others => '0');
else
r_s <= X"2A";
end if;
else
r_s <= std_logic_vector(unsigned(r_s) + 1);
end if;
-- running clock
else
if enc = '0' then
if r_s /= X"2B" then
r_s <= std_logic_vector(unsigned(r_s) + 1);
end if;
else
if r_s /= X"00" then
r_s <= std_logic_vector(unsigned(r_s) - 1);
end if;
end if;
end if;
end if;
end process;
-- SIMON Core
-- Take 2 clock cycle for initialization (since we route key through RAM) + 1 clock cycle per round for encryption/decryption
pr_smn : process(clk, rst, enc, r_s, key, key_s, subkey_out_s, block_in, v_in_s, v_out_s, ram_rw, ram_data_out)
begin
if rising_edge(clk) then
-- initalize
if rst = "11" then
if enc = '0' then
v_in_s <= block_in;
else
v_in_s <= block_in(31 downto 0) & block_in(63 downto 32);
end if;
-- initialize intermediate key from master key
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
-- write pre-expansion to RAM
ram_rw <= '1';
-- pre-expansion (run 0x2C times, 0x2B to expand + 1 to put correct value on ram_data_out)
elsif rst = "01" then
-- intermediate key rotates for initial 4 key words, beyond that gets gradually filled in by expansion
key_s(0) <= key_s(1);
key_s(1) <= key_s(2);
key_s(2) <= key_s(3);
key_s(3) <= subkey_out_s;
if r_s = X"2B" then
ram_rw <= '0';
end if;
-- run
else
v_in_s <= v_out_s;
end if;
end if;
end process;
block_out <= v_out_s when (enc = '0') else v_out_s(31 downto 0) & v_out_s(63 downto 32);
end Behavioral;
|
gpl-2.0
|
66c97b662c5041b3a2a7d6fac3d0539e
| 0.604211 | 2.818062 | false | false | false | false |
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