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luebbers/reconos
|
core/pcores/plb_osif_v2_03_a/hdl/vhdl/plb_osif.vhd
| 1 | 51,966 |
--!
--! \file osif.vhd
--!
--! OSIF logic and interface to IPIF
--!
--! \author Enno Luebbers <[email protected]>
--! \date 01.08.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- Copyright (c) 2008, Computer Engineering Group, University of
-- Paderborn.
--
-- For details regarding licensing and redistribution, see COPYING. If
-- you did not receive a COPYING file as part of the distribution package
-- containing this file, you can get it at http://www.reconos.de/COPYING.
--
-- This software is provided "as is" without express or implied warranty,
-- and with no claim as to its suitability for any particular purpose.
-- The copyright owner or the contributors shall not be liable for any
-- damages arising out of the use of this software.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 01.08.2006 Enno Luebbers File created (from opb_reconos_slot_v1_00_c)
-- 03.08.2006 Enno Luebbers Added PLB bus master (moved to v1.01.a),
-- removed BRAM interface
-- 23.11.2007 Enno Luebbers Moved OS communications to DCR
-- 07.12.2008 Enno Luebbers Moved memory bus interface to separate module
--
------------------------------------------------------------------------------
--
-- Original Xilinx header follows
--
------------------------------------------------------------------------------
-- osif.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: osif.vhd
-- Version: 1.01.a
-- Description: Top level design, instantiates IPIF and user logic.
-- Date: Tue Aug 1 12:51:51 2006 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_e;
use ipif_common_v1_00_e.ipif_pkg.all;
library plb_ipif_v2_01_a;
use plb_ipif_v2_01_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library plb_osif_v2_03_a;
use plb_osif_v2_03_a.all;
library osif_core_v2_03_a;
use osif_core_v2_03_a.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_PLB_AWIDTH -- PLB address bus width
-- C_PLB_DWIDTH -- PLB address data width
-- C_PLB_NUM_MASTERS -- Number of PLB masters
-- C_PLB_MID_WIDTH -- log2(C_PLB_NUM_MASTERS)
-- C_FAMILY -- Target FPGA architecture
--
-- Definition of Ports:
-- PLB_Clk -- PLB Clock
-- PLB_Rst -- PLB Reset
-- Sl_addrAck -- Slave address acknowledge
-- Sl_MBusy -- Slave busy indicator
-- Sl_MErr -- Slave error indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- PLB_abort -- PLB abort request indicator
-- PLB_ABus -- PLB address bus
-- PLB_BE -- PLB byte enables
-- PLB_busLock -- PLB bus lock
-- PLB_compress -- PLB compressed data transfer indicator
-- PLB_guarded -- PLB guarded transfer indicator
-- PLB_lockErr -- PLB lock error indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_MSize -- PLB master data bus size
-- PLB_ordered -- PLB synchronize transfer indicator
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_pendPri -- PLB pending request priority
-- PLB_pendReq -- PLB pending bus request indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_reqPri -- PLB current request priority
-- PLB_RNW -- PLB read/not write
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- M_abort -- Master abort bus request indicator
-- M_ABus -- Master address bus
-- M_BE -- Master byte enables
-- M_busLock -- Master buslock
-- M_compress -- Master compressed data transfer indicator
-- M_guarded -- Master guarded transfer indicator
-- M_lockErr -- Master lock error indicator
-- M_MSize -- Master data bus size
-- M_ordered -- Master synchronize transfer indicator
-- M_priority -- Master request priority
-- M_rdBurst -- Master burst read transfer indicator
-- M_request -- Master request
-- M_RNW -- Master read/nor write
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_wrBurst -- Master burst write transfer indicator
-- M_wrDBus -- Master write data bus
-- PLB_MBusy -- PLB master slave busy indicator
-- PLB_MErr -- PLB master slave error indicator
-- PLB_MWrBTerm -- PLB master terminate write burst indicator
-- PLB_MWrDAck -- PLB master write data acknowledge
-- PLB_MAddrAck -- PLB master address acknowledge
-- PLB_MRdBTerm -- PLB master terminate read burst indicator
-- PLB_MRdDAck -- PLB master read data acknowledge
-- PLB_MRdDBus -- PLB master read data bus
-- PLB_MRdWdAddr -- PLB master read word address
-- PLB_MRearbitrate -- PLB master bus re-arbitrate indicator
-- PLB_MSSize -- PLB slave data bus size
------------------------------------------------------------------------------
entity plb_osif is
generic
(
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_FIFO_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_BURSTLEN_WIDTH : integer := 5;
C_FAMILY : string := "virtex2p";
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_DCR_ILA : integer := 0; -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
C_ENABLE_MMU : boolean := true;
C_MMU_STAT_REGS : boolean := false;
C_TLB_DATA_WIDTH : integer := 21;
C_TLB_TAG_WIDTH : integer := 20
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- burst mem interface
burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
burstWrData : out std_logic_vector(0 to C_PLB_DWIDTH-1);
burstRdData : in std_logic_vector(0 to C_PLB_DWIDTH-1);
burstWE : out std_logic;
burstBE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
-- FIFO access signals
o_fifo_clk : out std_logic;
o_fifo_reset : out std_logic;
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic;
-- bus macro control
bmEnable : out std_logic;
-- tlb interface
i_tlb_rdata : in std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_wdata : out std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
o_tlb_tag : out std_logic_vector(C_TLB_TAG_WIDTH - 1 downto 0);
i_tlb_match : in std_logic;
o_tlb_we : out std_logic;
i_tlb_busy : in std_logic;
o_tlb_request : out std_logic;
--i_tlb_wdone : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DCR Bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0); -- chipscope
-- PLB Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
attribute SIGIS of interrupt : signal is "INTR_LEVEL_HIGH";
end entity plb_osif;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plb_osif is
------------------------------------------
-- constants : generated by wizard for instantiation - do not change
------------------------------------------
-- specify address range definition identifier value, each entry with
-- predefined identifier indicates inclusion of corresponding ipif
-- service, following ipif mandatory service identifiers are predefined:
-- IPIF_INTR
-- IPIF_RST
-- IPIF_SEST_SEAR
-- IPIF_DMA_SG
-- IPIF_WRFIFO_REG
-- IPIF_WRFIFO_DATA
-- IPIF_RDFIFO_REG
-- IPIF_RDFIFO_DATA
constant USER_SLAVE : integer := USER_00;
constant RECONOS_BURST : integer := USER_01; -- shared memory burst transfers
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_SLAVE, -- user logic slave space (s/w addressable constrol/status registers)
1 => RECONOS_BURST -- memory burst access range
);
-- specify actual address range (defined by a pair of base address and
-- high address) for each address space, which are byte relative.
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant SLAVE_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant SLAVE_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant BURST_BASEADDR : std_logic_vector := C_BASEADDR or X"00004000";
constant BURST_HIGHADDR : std_logic_vector := C_BASEADDR or X"00007FFF";
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & SLAVE_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & SLAVE_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & BURST_BASEADDR, -- burst range base addresss
ZERO_ADDR_PAD & BURST_HIGHADDR -- burst range high addresss
);
-- specify data width for each target address range.
constant USER_DWIDTH : integer := 32;
constant RECONOS_BURST_DWIDTH : integer := 64;
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_DWIDTH, -- user logic slave space data width
1 => RECONOS_BURST_DWIDTH
);
-- specify desired number of chip enables for each address range,
-- typically one ce per register and each ipif service has its
-- predefined value.
constant USER_NUM_SLAVE_CE : integer := 1;
constant RECONOS_BURST_NUM_CE : integer := 1;
constant USER_NUM_CE : integer := USER_NUM_SLAVE_CE+RECONOS_BURST_NUM_CE;
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
-- 0 => pad_power2(USER_NUM_SLAVE_CE), -- number of chip enableds for user logic slave space (one per register)
-- 1 => pad_power2(RECONOS_BURST_NUM_CE)
0 => USER_NUM_SLAVE_CE, -- number of chip enableds for user logic slave space (one per register)
1 => RECONOS_BURST_NUM_CE
);
-- specify unique properties for each address range, currently
-- only used for packet fifo data spaces.
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0), -- user logic slave space dependent properties (none defined)
1 => (others => 0) -- reconos burst range properties (none defined)
);
-- specify determinate timing parameters to be used during read
-- accesses for each address range, these values are used to optimize
-- data beat timing response for burst reads from addresses sources such
-- as ddr and sdram memory, each address space requires three integer
-- entries for mode [0-2], latency [0-31] and wait states [0-31].
constant ARD_DTIME_READ_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate read parameters
0, 0, 0
);
-- specify determinate timing parameters to be used during write
-- accesses for each address range, they not used currently, so
-- all entries should be set to zeros.
constant ARD_DTIME_WRITE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0, 0, 0, -- user logic slave space determinate write parameters
0, 0, 0
);
-- specify user defined device block id, which is used to uniquely
-- identify a device within a system.
constant DEV_BLK_ID : integer := 0;
-- specify inclusion/omission of module information register to be
-- read via the plb bus.
constant DEV_MIR_ENABLE : integer := 0;
-- specify inclusion/omission of additional logic needed to support
-- plb fixed burst transfers and optimized cacahline transfers.
constant DEV_BURST_ENABLE : integer := 1;
-- specify the maximum number of bytes that are allowed to be
-- transferred in a single burst operation, currently this needs
-- to be fixed at 128.
constant DEV_MAX_BURST_SIZE : integer := 128;
-- specify size of the largest target burstable memory space (in
-- bytes and a power of 2), this is to optimize the size of the
-- internal burst address counters.
constant DEV_BURST_PAGE_SIZE : integer := 1024;
-- specify number of plb clock cycles are allowed before a
-- data phase transfer timeout, this feature is useful during
-- system integration and debug.
constant DEV_DPHASE_TIMEOUT : integer := 64;
-- specify inclusion/omission of device interrupt source
-- controller for internal ipif generated interrupts.
constant INCLUDE_DEV_ISC : integer := 0;
-- specify inclusion/omission of device interrupt priority
-- encoder, this is useful in aiding the user interrupt service
-- routine to resolve the source of an interrupt within a plb
-- device incorporating an ipif.
constant INCLUDE_DEV_PENCODER : integer := 0;
-- specify number and capture mode of interrupt events from the
-- user logic to the ip isc located in the ipif interrupt service,
-- user logic interrupt event capture mode [1-6]:
-- 1 = Level Pass through (non-inverted)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Event (non-inverted)
-- 4 = Registered Event (inverted input)
-- 5 = Rising Edge Detect
-- 6 = Falling Edge Detect
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify inclusion/omission of plb master service for user logic.
constant IP_MASTER_PRESENT : integer := 1;
-- specify dma type for each channel (currently only 2 channels
-- supported), use following number:
-- 0 - simple dma
-- 1 - simple scatter gather
-- 2 - tx scatter gather with packet mode support
-- 3 - rx scatter gather with packet mode support
constant DMA_CHAN_TYPE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify maximum width in bits for dma transfer byte counters.
constant DMA_LENGTH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify address assigement for the length fifos used in
-- scatter gather operation.
constant DMA_PKT_LEN_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify address assigement for the status fifos used in
-- scatter gather operation.
constant DMA_PKT_STAT_FIFO_ADDR_ARRAY : SLV64_ARRAY_TYPE :=
(
0 => X"00000000_00000000" -- not used
);
-- specify interrupt coalescing value (number of interrupts to
-- accrue before issuing interrupt to system) for each dma
-- channel, apply to software design consideration.
constant DMA_INTR_COALESCE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 0 -- not used
);
-- specify allowing dma busrt mode transactions or not.
constant DMA_ALLOW_BURST : integer := 0;
-- specify maximum allowed time period (in ns) a packet may wait
-- before transfer by the scatter gather dma, apply to software
-- design consideration.
constant DMA_PACKET_WAIT_UNIT_NS : integer := 1000;
-- specify period of the plb clock in picoseconds, which is used
-- by the dma/sg service for timing funtions.
constant PLB_CLK_PERIOD_PS : integer := 10000;
-- specify ipif data bus size, used for future ipif optimization,
-- should be set equal to the plb data bus width.
constant IPIF_DWIDTH : integer := C_PLB_DWIDTH;
-- specify ipif address bus size, used for future ipif optimization,
-- should be set equal to the plb address bus width.
constant IPIF_AWIDTH : integer := C_PLB_AWIDTH;
-- specify user logic address bus width, must be same as the target bus.
constant USER_AWIDTH : integer := C_PLB_AWIDTH;
-- specify index for user logic slave/master spaces chip enable.
constant USER_SLAVE_CE_INDEX : integer := calc_start_ce_index(ARD_NUM_CE_ARRAY, get_id_index(ARD_ID_ARRAY, USER_SLAVE));
------------------------------------------
-- IP Interconnect (IPIC) signal declarations -- do not delete
-- prefix 'i' stands for IPIF while prefix 'u' stands for user logic
-- typically user logic will be hooked up to IPIF directly via i<sig>
-- unless signal slicing and muxing are needed via u<sig>
------------------------------------------
signal iBus2IP_Clk : std_logic;
signal iBus2IP_Reset : std_logic;
signal ZERO_IP2Bus_IntrEvent : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length - 1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal iIP2Bus_Data : std_logic_vector(0 to C_PLB_DWIDTH-1) := (others => '0');
signal iIP2Bus_WrAck : std_logic := '0';
signal iIP2Bus_RdAck : std_logic := '0';
signal iIP2Bus_Retry : std_logic := '0';
signal iIP2Bus_Error : std_logic := '0';
signal iIP2Bus_ToutSup : std_logic := '0';
signal iBus2IP_Addr : std_logic_vector(0 to C_PLB_AWIDTH - 1);
signal iBus2IP_Data : std_logic_vector(0 to C_PLB_DWIDTH - 1);
signal iBus2IP_BE : std_logic_vector(0 to (C_PLB_DWIDTH/8) - 1);
signal iBus2IP_Burst : std_logic;
signal iBus2IP_WrReq : std_logic;
signal iBus2IP_RdReq : std_logic;
signal iBus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iBus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal iIP2Bus_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstBE : std_logic_vector(0 to (IPIF_DWIDTH/8) - 1) := (others => '0');
signal iIP2IP_Addr : std_logic_vector(0 to IPIF_AWIDTH - 1) := (others => '0');
signal iIP2Bus_MstWrReq : std_logic := '0';
signal iIP2Bus_MstRdReq : std_logic := '0';
signal iIP2Bus_MstBurst : std_logic := '0';
signal iIP2Bus_MstBusLock : std_logic := '0';
signal iIP2Bus_MstNum : std_logic_vector(0 to log2(DEV_MAX_BURST_SIZE/(C_PLB_DWIDTH/8))) := (others => '0');
signal iBus2IP_MstWrAck : std_logic;
signal iBus2IP_MstRdAck : std_logic;
signal iBus2IP_MstRetry : std_logic;
signal iBus2IP_MstError : std_logic;
signal iBus2IP_MstTimeOut : std_logic;
signal iBus2IP_MstLastAck : std_logic;
signal ZERO_IP2RFIFO_Data : std_logic_vector(0 to find_id_dwidth(ARD_ID_ARRAY, ARD_DWIDTH_ARRAY, IPIF_RDFIFO_DATA, 32)-1) := (others => '0'); -- work around for XST not taking (others => '0') in port mapping
signal uBus2IP_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uBus2IP_DataX : std_logic_vector(USER_DWIDTH to C_PLB_DWIDTH-1);
signal uBus2IP_BE : std_logic_vector(0 to (RECONOS_BURST_DWIDTH/8)-1);
signal uBus2IP_RdCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uBus2IP_WrCE : std_logic_vector(0 to USER_NUM_CE-1);
signal uIP2Bus_Data : std_logic_vector(0 to USER_DWIDTH-1);
signal uIP2Bus_DataX : std_logic_vector(USER_DWIDTH to C_PLB_DWIDTH-1); -- extended data
signal uIP2Bus_MstBE : std_logic_vector(0 to USER_DWIDTH/8-1);
signal task_clk_internal : std_logic;
signal task_reset_internal : std_logic;
-- single word data input/output
signal mem2osif_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal osif2mem_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- addresses for master transfers
signal mem_localAddr : std_logic_vector(0 to USER_AWIDTH-1);
signal mem_targetAddr : std_logic_vector(0 to USER_AWIDTH-1);
-- single word transfer requests
signal mem_singleRdReq : std_logic;
signal mem_singleWrReq : std_logic;
-- burst transfer requests
signal mem_burstRdReq : std_logic;
signal mem_burstWrReq : std_logic;
signal mem_burstLen : std_logic_vector(0 to C_BURSTLEN_WIDTH-1);
-- status outputs
signal mem_busy : std_logic;
signal mem_rdDone : std_logic;
signal mem_wrDone : std_logic;
---------
-- local FIFO control and data lines
---------
signal fifomgr_read_remove : std_logic;
signal fifomgr_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_read_wait : std_logic;
signal fifomgr_write_add : std_logic;
signal fifomgr_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_write_wait : std_logic;
begin
------------------------------------------
-- instantiate the PLB IPIF, if necessary
------------------------------------------
PLB_IPIF_I : entity plb_ipif_v2_01_a.plb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_ARD_DTIME_READ_ARRAY => ARD_DTIME_READ_ARRAY,
C_ARD_DTIME_WRITE_ARRAY => ARD_DTIME_WRITE_ARRAY,
C_DEV_BLK_ID => DEV_BLK_ID,
C_DEV_MIR_ENABLE => DEV_MIR_ENABLE,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_DEV_MAX_BURST_SIZE => DEV_MAX_BURST_SIZE,
C_DEV_BURST_PAGE_SIZE => DEV_BURST_PAGE_SIZE,
C_DEV_DPHASE_TIMEOUT => DEV_DPHASE_TIMEOUT,
C_INCLUDE_DEV_ISC => INCLUDE_DEV_ISC,
C_INCLUDE_DEV_PENCODER => INCLUDE_DEV_PENCODER,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_IP_MASTER_PRESENT => IP_MASTER_PRESENT,
C_DMA_CHAN_TYPE_ARRAY => DMA_CHAN_TYPE_ARRAY,
C_DMA_LENGTH_WIDTH_ARRAY => DMA_LENGTH_WIDTH_ARRAY,
C_DMA_PKT_LEN_FIFO_ADDR_ARRAY => DMA_PKT_LEN_FIFO_ADDR_ARRAY,
C_DMA_PKT_STAT_FIFO_ADDR_ARRAY => DMA_PKT_STAT_FIFO_ADDR_ARRAY,
C_DMA_INTR_COALESCE_ARRAY => DMA_INTR_COALESCE_ARRAY,
C_DMA_ALLOW_BURST => DMA_ALLOW_BURST,
C_DMA_PACKET_WAIT_UNIT_NS => DMA_PACKET_WAIT_UNIT_NS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_CLK_PERIOD_PS => PLB_CLK_PERIOD_PS,
C_IPIF_DWIDTH => IPIF_DWIDTH,
C_IPIF_AWIDTH => IPIF_AWIDTH,
C_FAMILY => C_FAMILY
)
port map
(
PLB_clk => PLB_Clk,
Reset => PLB_Rst,
Freeze => '0',
IP2INTC_Irpt => open,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_ordered => PLB_ordered,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_pendReq => PLB_pendReq,
PLB_pendPri => PLB_pendPri,
PLB_reqPri => PLB_reqPri,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
IP2Bus_Clk => '0',
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Freeze => open,
IP2Bus_IntrEvent => ZERO_IP2Bus_IntrEvent,
IP2Bus_Data => iIP2Bus_Data,
IP2Bus_WrAck => iIP2Bus_WrAck,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_PostedWrInh => '0',
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => iBus2IP_Data,
Bus2IP_RNW => open,
Bus2IP_BE => iBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_WrReq => iBus2IP_WrReq,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_CS => open,
Bus2IP_CE => open,
Bus2IP_RdCE => iBus2IP_RdCE,
Bus2IP_WrCE => iBus2IP_WrCE,
IP2DMA_RxLength_Empty => '0',
IP2DMA_RxStatus_Empty => '0',
IP2DMA_TxLength_Full => '0',
IP2DMA_TxStatus_Empty => '0',
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2IP_Addr => iIP2IP_Addr,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_IPMstTrans => open,
IP2RFIFO_WrReq => '0',
IP2RFIFO_Data => ZERO_IP2RFIFO_Data,
IP2RFIFO_WrMark => '0',
IP2RFIFO_WrRelease => '0',
IP2RFIFO_WrRestore => '0',
RFIFO2IP_WrAck => open,
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_Data => open,
WFIFO2IP_RdAck => open,
WFIFO2IP_AlmostEmpty => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
IP2Bus_DMA_Req => '0',
Bus2IP_DMA_Ack => open
);
------------------------------------------
-- instantiate the OSIF core
------------------------------------------
USER_LOGIC_I : entity osif_core_v2_03_a.osif_core
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_NUM_CE => USER_NUM_CE,
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_ENABLE_MMU => C_ENABLE_MMU,
C_MMU_STAT_REGS => C_MMU_STAT_REGS,
C_DCR_ILA => C_DCR_ILA
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => interrupt,
busy => busy,
blocking => blocking,
-- task interface
task_clk => task_clk_internal,
task_reset => task_reset_internal,
osif_os2task_vec => osif_os2task_vec,
osif_task2os_vec => osif_task2os_vec,
-- FIFO manager access signals
o_fifomgr_read_remove => fifomgr_read_remove,
i_fifomgr_read_data => fifomgr_read_data,
i_fifomgr_read_wait => fifomgr_read_wait,
o_fifomgr_write_add => fifomgr_write_add,
o_fifomgr_write_data => fifomgr_write_data,
i_fifomgr_write_wait => fifomgr_write_wait,
-- memory access signals
o_mem_singleData => osif2mem_singleData,
i_mem_singleData => mem2osif_singleData,
o_mem_localAddr => mem_localAddr,
o_mem_targetAddr => mem_targetAddr,
o_mem_singleRdReq => mem_singleRdReq,
o_mem_singleWrReq => mem_singleWrReq,
o_mem_burstRdReq => mem_burstRdReq,
o_mem_burstWrReq => mem_burstWrReq,
o_mem_burstLen => mem_burstLen,
i_mem_busy => mem_busy,
i_mem_rdDone => mem_rdDone,
i_mem_wrDone => mem_wrDone,
-- bus macro control
o_bm_enable => bmEnable,
-- tlb interface
i_tlb_rdata => i_tlb_rdata,
o_tlb_wdata => o_tlb_wdata,
o_tlb_tag => o_tlb_tag,
i_tlb_match => i_tlb_match,
o_tlb_we => o_tlb_we,
i_tlb_busy => i_tlb_busy,
o_tlb_request => o_tlb_request,
-- MAP USER PORTS ABOVE THIS LINE ------------------
sys_clk => sys_clk,
sys_reset => sys_reset,
-- DCR Bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON
);
---------------------------------------
-- memory bus controller core
--
-- PLBv34
---------------------------------------
mem_plb34_i : entity plb_osif_v2_03_a.mem_plb34
generic map
(
C_SLAVE_BASEADDR => SLAVE_BASEADDR,
-- Bus protocol parameters
C_AWIDTH => USER_AWIDTH,
C_DWIDTH => USER_DWIDTH,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_NUM_CE => USER_NUM_CE,
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_BURST_BASEADDR => BURST_BASEADDR
)
port map
(
clk => task_clk_internal,
reset => task_reset_internal,
-- data interface ---------------------------
-- burst mem interface
o_burstAddr => burstAddr,
o_burstData => burstWrData,
i_burstData => burstRdData,
o_burstWE => burstWE,
o_burstBE => burstBE,
-- single word data input/output
i_singleData => osif2mem_singleData,
o_singleData => mem2osif_singleData,
-- control interface ------------------------
-- addresses for master transfers
i_localAddr => mem_localAddr,
i_targetAddr => mem_targetAddr,
-- single word transfer requests
i_singleRdReq => mem_singleRdReq,
i_singleWrReq => mem_singleWrReq,
-- burst transfer requests
i_burstRdReq => mem_burstRdReq,
i_burstWrReq => mem_burstWrReq,
i_burstLen => mem_burstLen,
-- status outputs
o_busy => mem_busy,
o_rdDone => mem_rdDone,
o_wrDone => mem_wrDone,
-- PLBv34 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk => iBus2IP_Clk,
Bus2IP_Reset => iBus2IP_Reset,
Bus2IP_Addr => iBus2IP_Addr,
Bus2IP_Data => uBus2IP_Data,
Bus2IP_DataX => uBus2IP_DataX,
Bus2IP_BE => uBus2IP_BE,
Bus2IP_Burst => iBus2IP_Burst,
Bus2IP_RdCE => uBus2IP_RdCE,
Bus2IP_WrCE => uBus2IP_WrCE,
Bus2IP_RdReq => iBus2IP_RdReq,
Bus2IP_WrReq => iBus2IP_WrReq,
IP2Bus_Data => uIP2Bus_Data,
IP2Bus_DataX => uIP2Bus_DataX,
IP2Bus_Retry => iIP2Bus_Retry,
IP2Bus_Error => iIP2Bus_Error,
IP2Bus_ToutSup => iIP2Bus_ToutSup,
IP2Bus_RdAck => iIP2Bus_RdAck,
IP2Bus_WrAck => iIP2Bus_WrAck,
Bus2IP_MstError => iBus2IP_MstError,
Bus2IP_MstLastAck => iBus2IP_MstLastAck,
Bus2IP_MstRdAck => iBus2IP_MstRdAck,
Bus2IP_MstWrAck => iBus2IP_MstWrAck,
Bus2IP_MstRetry => iBus2IP_MstRetry,
Bus2IP_MstTimeOut => iBus2IP_MstTimeOut,
IP2Bus_Addr => iIP2Bus_Addr,
IP2Bus_MstBE => iIP2Bus_MstBE,
IP2Bus_MstBurst => iIP2Bus_MstBurst,
IP2Bus_MstBusLock => iIP2Bus_MstBusLock,
IP2Bus_MstNum => iIP2Bus_MstNum,
IP2Bus_MstRdReq => iIP2Bus_MstRdReq,
IP2Bus_MstWrReq => iIP2Bus_MstWrReq,
IP2IP_Addr => iIP2IP_Addr
);
-----------------------------------------------------------------------
-- fifo_mgr_inst: FIFO manager instantiation
--
-- The FIFO manager handles incoming push/pop requests to the two
-- hardware FIFOs attached to the OSIF. It arbitrates between
-- local hardware-thread-initiated requests and indirect bus accesses
-- by other hardware threads.
-----------------------------------------------------------------------
fifo_mgr_inst : entity plb_osif_v2_03_a.fifo_mgr
generic map (
C_FIFO_DWIDTH => C_FIFO_DWIDTH
)
port map (
clk => sys_clk,
reset => sys_reset, -- we don't want a thread reset command to flush
-- the FIFOs, therefore no thread_reset_i!
-- local FIFO access signals
i_local_read_remove => fifomgr_read_remove,
o_local_read_data => fifomgr_read_data,
o_local_read_wait => fifomgr_read_wait,
i_local_write_add => fifomgr_write_add,
i_local_write_data => fifomgr_write_data,
o_local_write_wait => fifomgr_write_wait,
-- "real" FIFO access signals
o_fifo_read_en => o_fifo_read_en,
i_fifo_read_data => i_fifo_read_data,
i_fifo_read_ready => i_fifo_read_ready,
o_fifo_write_en => o_fifo_write_en,
o_fifo_write_data => o_fifo_write_data,
i_fifo_write_ready => i_fifo_write_ready
-- TODO: signal to communicate with the bus_slave_regs module
);
--------
-- set FIFO clock/reset
--------
o_fifo_clk <= sys_clk;
o_fifo_reset <= sys_reset;
---------
-- set task clock/reset
---------
task_clk <= task_clk_internal;
task_reset <= task_reset_internal;
------------------------------------------
-- hooking up signal slicing
------------------------------------------
uBus2IP_Data <= iBus2IP_Data(0 to USER_DWIDTH-1);
uBus2IP_DataX <= iBus2IP_Data(USER_DWIDTH to C_PLB_DWIDTH-1);
uBus2IP_BE <= iBus2IP_BE; --(0 to USER_DWIDTH/8-1);
-- uBus2IP_RdCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_RdCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
-- uBus2IP_WrCE(0 to USER_NUM_SLAVE_CE-1) <= iBus2IP_WrCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_SLAVE_CE-1);
uBus2IP_RdCE(0 to USER_NUM_CE-1) <= iBus2IP_RdCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_CE-1);
uBus2IP_WrCE(0 to USER_NUM_CE-1) <= iBus2IP_WrCE(USER_SLAVE_CE_INDEX to USER_SLAVE_CE_INDEX+USER_NUM_CE-1);
iIP2Bus_Data(0 to USER_DWIDTH-1) <= uIP2Bus_Data;
iIP2Bus_Data(USER_DWIDTH to C_PLB_DWIDTH-1) <= uIP2Bus_DataX;
end IMP;
|
gpl-3.0
|
61bcd3936500a43ae98953dba3479437
| 0.492322 | 4.246976 | false | false | false | false |
luebbers/reconos
|
tests/benchmarks/mq/hw/pcores/hw_task_v1_01_b/hdl/vhdl/hw_task.vhd
| 1 | 5,093 |
------------
-- pcore top level wrapper
-- generated at 2008-11-24 15:39:39.893897 by 'mkhwthread.py hwt_mq 1 ../src/hwt_mq.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.ALL;
library burst_ram_v2_01_a;
use burst_ram_v2_01_a.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 14; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 12; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
i_burstBE : in std_logic_vector(0 to C_BUS_BURST_DWIDTH/8-1);
i_timebase : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end hw_task;
architecture structural of hw_task is
constant C_GND_TASK_DATA : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
constant C_GND_TASK_ADDR : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal o_osif_flat_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal i_osif_flat_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
signal inv_RAM : std_logic;
signal burstData :std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
-- connect top level signals
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
i_osif <= to_osif_os2task_t(i_osif_flat_i);
-- instantiate user task
hwt_mq_i : entity hwt_mq
generic map (
C_BURST_AWIDTH => C_TASK_BURST_AWIDTH,
C_BURST_DWIDTH => C_TASK_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk,
o_inv_RAM => inv_RAM,
i_timebase => i_timebase
);
burst_ram_i : entity burst_ram_v2_01_a.burst_ram
generic map (
G_PORTA_AWIDTH => C_TASK_BURST_AWIDTH,
G_PORTA_DWIDTH => C_TASK_BURST_DWIDTH,
G_PORTA_PORTS => 1,
G_PORTB_AWIDTH => C_BUS_BURST_AWIDTH-3,
G_PORTB_DWIDTH => C_BUS_BURST_DWIDTH,
G_PORTB_USE_BE => 1
)
port map (
addra => task2burst_Addr,
addrax => C_GND_TASK_ADDR,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkax => '0',
clkb => clk,
dina => task2burst_Data,
dinax => C_GND_TASK_DATA,
dinb => i_burstData,
douta => burst2task_Data,
doutax => open,
doutb => burstData,
wea => task2burst_WE,
weax => '0',
web => i_burstWE,
ena => '1',
enax => '0',
enb => '1',
beb => i_burstBE
);
o_burstData <= burstData when inv_RAM = '0' else NOT burstData;
end structural;
|
gpl-3.0
|
889838668543641fe4a6ea1ac27fd145
| 0.491066 | 3.820705 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_fa4_test2.vhd
| 4 | 1,868 |
library ieee;
use ieee.numeric_bit.all;
-- Declare a 1-bit full-adder.
entity fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit
);
end entity fa1;
architecture fa1_rtl of fa1 is
begin
s_o <= a_i xor b_i xor c_i;
c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
end architecture fa1_rtl;
-- Declare and implement a 4-bit full-adder that uses the
-- 1-bit full-adder described above.
entity fa4 is
port (va_i, vb_i: in bit_vector (3 downto 0);
c_i: in bit;
vs_o: out bit_vector (3 downto 0);
c_o: out bit
);
end entity fa4;
architecture fa4_rtl of fa4 is
-- full 1-bit adder
component fa1 is
port (a_i, b_i, c_i: in bit;
s_o, c_o: out bit);
end component fa1;
-- internal carry signals propagation
signal c_int: bit_vector (4 downto 0);
begin
-- carry in
c_int(0) <= c_i;
-- slice 0
s0: fa1 port map (c_i => c_int(0),
a_i => va_i(0),
b_i => vb_i(0),
s_o => vs_o(0),
c_o => c_int(1)
);
-- slice 1
s1: fa1 port map (c_i => c_int(1),
a_i => va_i(1),
b_i => vb_i(1),
s_o => vs_o(1),
c_o => c_int(2)
);
-- slice 2
s2: fa1 port map (c_i => c_int(2),
a_i => va_i(2),
b_i => vb_i(2),
s_o => vs_o(2),
c_o => c_int(3)
);
-- slice 3
s3: fa1 port map (c_i => c_int(3),
a_i => va_i(3),
b_i => vb_i(3),
s_o => vs_o(3),
c_o => c_int(4)
);
-- carry out
c_o <= c_int(4);
end architecture fa4_rtl;
|
gpl-2.0
|
be785d4b6ab6be6cdcffc2f712794338
| 0.40364 | 3.003215 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/enumsystem.vhd
| 4 | 2,181 |
------------------------------------------------------------------------------
-- Author: Oswaldo Cadenas
-- Date: September 27 2011
--
-- Summary: This system runs an internal counter 0,1,2, ..., 7, 0, 1,
-- and also accepts an enable signal
-- it generates an output y (4 bits) as:
-- if (e = 0) y = 0000
-- if (e = 1) then
-- y = 1000 when counter is 0
-- y = 0100 when counter is 1
-- y = 0010 when counter is 2
-- y = 0001 when counter is 3
-- y = 1111 other count
-- internaly the design uses some enumartion arguments for decoding and encoding
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity enumsystem is
port (clk, reset: in std_logic;
en: in std_logic; -- enable
y: out std_logic_vector (0 to 3) ); -- decoded output
end enumsystem;
architecture enumsystem_rtl of enumsystem is
type States is (zero, one, two, three, other);
signal mystate: States;
signal Counter: std_logic_vector (2 downto 0);
begin
SmallCounter : process (clk, reset)
begin
if ( clk'event and clk = '1') then
if (reset = '1') then
Counter <= (others => '0');
else
Counter <= Counter + 1;
end if;
end if;
end process;
encoding_process: process (Counter)
begin
case Counter is
when "000" => mystate <= zero;
when "001" => mystate <= one;
when "010" => mystate <= two;
when "011" => mystate <= three;
when others => mystate <= other;
end case;
end process;
decoding_process: process (mystate, en)
begin
if (en = '1') then
case mystate is
when zero => y <= "1000";
when one => y <= "0100";
when two => y <= "0010";
when three => y <= "0001";
when others => y <= "1111";
end case;
else
y <= "0000";
end if;
end process;
end enumsystem_rtl;
|
gpl-2.0
|
50ea7d4ebce9f4bbd6c156bdbf48adca
| 0.483265 | 4.091932 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_pulse_synchronizer.vhd
| 2 | 4,191 |
-------------------------------------------------------------------------------
-- Title : Pulse synchronizer
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : gc_pulse_synchronizer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2012-08-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Full feedback pulse synchronizer (works independently of the
-- input/output clock domain frequency ratio)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-12 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
entity gc_pulse_synchronizer is
port (
-- pulse input clock
clk_in_i : in std_logic;
-- pulse output clock
clk_out_i : in std_logic;
-- system reset (clk_in_i domain)
rst_n_i : in std_logic;
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o : out std_logic;
-- pulse input (clk_in_i domain)
d_p_i : in std_logic;
-- pulse output (clk_out_i domain)
q_p_o : out std_logic);
end gc_pulse_synchronizer;
architecture rtl of gc_pulse_synchronizer is
constant c_sync_stages : integer := 3;
signal ready, d_p_d0 : std_logic;
signal in_ext, out_ext : std_logic;
signal out_feedback : std_logic;
signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
begin -- rtl
process(clk_out_i, rst_n_i)
begin
if rst_n_i = '0' then
d_in2out <= (others => '0');
out_ext <= '0';
elsif rising_edge(clk_out_i) then
d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
out_ext <= d_in2out(c_sync_stages-1);
end if;
end process;
process(clk_in_i, rst_n_i)
begin
if rst_n_i = '0' then
d_out2in <= (others => '0');
elsif rising_edge(clk_in_i) then
d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
end if;
end process;
out_feedback <= d_out2in(c_sync_stages-1);
p_input_ack : process(clk_in_i, rst_n_i)
begin
if rst_n_i = '0' then
ready <= '1';
in_ext <= '0';
d_p_d0 <= '0';
elsif rising_edge(clk_in_i) then
d_p_d0 <= d_p_i;
if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
in_ext <= '1';
ready <= '0';
elsif(in_ext = '1' and out_feedback = '1') then
in_ext <= '0';
elsif(in_ext = '0' and out_feedback = '0') then
ready <= '1';
end if;
end if;
end process;
p_drive_output : process(clk_out_i, rst_n_i)
begin
if rst_n_i = '0' then
q_p_o <= '0';
elsif rising_edge(clk_out_i) then
q_p_o <= not out_ext and d_in2out(c_sync_stages-1);
end if;
end process;
d_ready_o <= ready;
end rtl;
|
lgpl-3.0
|
5143f0817e599422d74546852a155b57
| 0.524457 | 3.472245 | false | false | false | false |
makestuff/vhdl
|
dpimext/topLevel.vhd
| 1 | 5,845 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic;
led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0)
);
end TopLevel;
architecture Behavioural of TopLevel is
type State is (
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- Data to be mux'd back to host
signal iDataOutput : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
signal iThisR3, iNextR3 : std_logic_vector(7 downto 0);
begin
-- Drive the outputs
eppAck <= iThisAck;
led <= iThisR3;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
sw when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisR3 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisR3 <= iNextR3;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2, iThisR3)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iNextR3 <= iThisR3;
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iNextR3 <= eppDataBus;
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
gpl-3.0
|
e23c78dcea61f40a331df2438dcaada2
| 0.591788 | 3.572738 | false | false | false | false |
luebbers/reconos
|
tests/simulation/plb/mem/test_mem.vhd
| 1 | 4,745 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_mem is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_mem;
architecture Behavioral of test_mem is
constant C_READ_MEM : std_logic_vector(0 to 31) := X"10000004";
constant C_WRITE_MEM : std_logic_vector(0 to 31) := X"20000004";
type t_state is (STATE_INIT, STATE_READ_SINGLE, STATE_WRITE_SINGLE, STATE_READ_BURST,
STATE_ADD, STATE_ADD_INC, STATE_WRITE_BURST, STATE_EXIT);
signal state : t_state := STATE_INIT;
signal in_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal out_value : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1) ;
begin
-- burst ram interface is not used
o_RAMAddr <= RAMAddr;
o_RAMData <= i_RAMData + init_data;
o_RAMClk <= clk;
out_value <= in_value + init_data;
-- for i in 0 to 15 do
-- read a 32-bit word from 10000000 + i
-- add 0x01010101 to it (or whatever is in init_data)
-- write it to 20000000 + i
state_proc : process(clk, reset)
variable counter : integer range 0 to 512;
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
counter := 0;
RAMAddr <= (others => '0');
o_RAMWE <= '0';
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data);
if done then
counter := 0;
state <= STATE_READ_SINGLE;
end if;
when STATE_READ_SINGLE =>
reconos_read_s(done, o_osif, i_osif, C_READ_MEM + counter, in_value);
if done then
state <= STATE_WRITE_SINGLE;
end if;
when STATE_WRITE_SINGLE =>
reconos_write(done, o_osif, i_osif, C_WRITE_MEM + counter, out_value);
if done then
if counter = 15 then
counter := 2; -- bursts work only from 2 data beats up
state <= STATE_READ_BURST;
else
counter := counter + 1;
state <= STATE_READ_SINGLE;
end if;
end if;
when STATE_READ_BURST =>
reconos_read_burst_l( done, o_osif, i_osif, X"00000000", C_READ_MEM, counter);
if done then
state <= STATE_ADD;
RAMAddr <= (others => '0');
end if;
when STATE_ADD =>
if RAMAddr = counter*2 then
state <= STATE_WRITE_BURST;
else
o_RAMWE <= '1';
state <= STATE_ADD_INC;
end if;
when STATE_ADD_INC =>
o_RAMWE <= '0';
RAMAddr <= RAMAddr + 1;
state <= STATE_ADD;
when STATE_WRITE_BURST =>
reconos_write_burst_l( done, o_osif, i_osif, X"00000000", C_WRITE_MEM, counter);
if done then
if counter = 512 then
counter := 0;
state <= STATE_EXIT;
else
counter := counter + 1;
state <= STATE_READ_BURST;
end if;
end if;
when STATE_EXIT =>
reconos_thread_exit (o_osif, i_osif, C_RECONOS_SUCCESS);
state <= STATE_EXIT;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
25c951dbb29e2f54d6f033161e0447c7
| 0.514015 | 3.835893 | false | false | false | false |
oetr/FPGA-I2C-Slave
|
I2C_minion.vhd
| 1 | 11,261 |
------------------------------------------------------------
-- File : I2C_minion.vhd
------------------------------------------------------------
-- Author : Peter Samarin <[email protected]>
------------------------------------------------------------
-- Copyright (c) 2019 Peter Samarin
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------
entity I2C_minion is
generic (
MINION_ADDR : std_logic_vector(6 downto 0);
-- noisy SCL/SDA lines can confuse the minion
-- use low-pass filter to smooth the signal
-- (this might not be necessary!)
USE_INPUT_DEBOUNCING : boolean := false;
-- play with different number of wait cycles
-- larger wait cycles increase the resource usage
DEBOUNCING_WAIT_CYCLES : integer := 4);
port (
scl : inout std_logic;
sda : inout std_logic;
clk : in std_logic;
rst : in std_logic;
-- User interface
read_req : out std_logic;
data_to_master : in std_logic_vector(7 downto 0);
data_valid : out std_logic;
data_from_master : out std_logic_vector(7 downto 0));
end entity I2C_minion;
------------------------------------------------------------
architecture arch of I2C_minion is
type state_t is (idle, get_address_and_cmd,
answer_ack_start, write,
read, read_ack_start,
read_ack_got_rising, read_stop);
-- I2C state management
signal state_reg : state_t := idle;
signal cmd_reg : std_logic := '0';
signal bits_processed_reg : integer range 0 to 8 := 0;
signal continue_reg : std_logic := '0';
signal scl_reg : std_logic := 'Z';
signal sda_reg : std_logic := 'Z';
signal scl_debounced : std_logic := 'Z';
signal sda_debounced : std_logic := 'Z';
signal scl_pre_internal : std_logic := 'Z';
signal scl_internal : std_logic := '1';
signal sda_pre_internal : std_logic := 'Z';
signal sda_internal : std_logic := '1';
-- Helpers to figure out next state
signal start_reg : std_logic := '0';
signal stop_reg : std_logic := '0';
signal scl_rising_reg : std_logic := '0';
signal scl_falling_reg : std_logic := '0';
-- Address and data received from master
signal addr_reg : std_logic_vector(6 downto 0) := (others => '0');
signal data_reg : std_logic_vector(6 downto 0) := (others => '0');
signal data_from_master_reg : std_logic_vector(7 downto 0) := (others => '0');
signal scl_prev_reg : std_logic := 'Z';
-- Minion writes on scl
signal scl_wen_reg : std_logic := '0';
signal scl_o_reg : std_logic := '0'; -- unused for now
signal sda_prev_reg : std_logic := 'Z';
-- Minion writes on sda
signal sda_wen_reg : std_logic := '0';
signal sda_o_reg : std_logic := '0';
-- User interface
signal data_valid_reg : std_logic := '0';
signal read_req_reg : std_logic := '0';
signal data_to_master_reg : std_logic_vector(7 downto 0) := (others => '0');
begin
debounce : if USE_INPUT_DEBOUNCING generate
-- debounce SCL and SDA
SCL_debounce : entity work.debounce
generic map (
WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
port map (
clk => clk,
signal_in => scl,
signal_out => scl_debounced);
-- it might not make sense to debounce SDA, since master
-- and minion can both write to it...
SDA_debounce : entity work.debounce
generic map (
WAIT_CYCLES => DEBOUNCING_WAIT_CYCLES)
port map (
clk => clk,
signal_in => sda,
signal_out => sda_debounced);
scl_pre_internal <= scl_debounced;
sda_pre_internal <= sda_debounced;
end generate debounce;
dont_debounce : if (not USE_INPUT_DEBOUNCING) generate
process (clk) is
begin
if rising_edge(clk) then
scl_pre_internal <= scl;
sda_pre_internal <= sda;
end if;
end process;
end generate dont_debounce;
scl_internal <= '0' when scl_pre_internal = '0' else '1';
sda_internal <= '0' when sda_pre_internal = '0' else '1';
process (clk) is
begin
if rising_edge(clk) then
-- Delay SCL and SDA by 1 clock cycle
scl_prev_reg <= scl_internal;
sda_prev_reg <= sda_internal;
-- Detect rising and falling SCL
scl_rising_reg <= '0';
if scl_prev_reg = '0' and scl_internal = '1' then
scl_rising_reg <= '1';
end if;
scl_falling_reg <= '0';
if scl_prev_reg = '1' and scl_internal = '0' then
scl_falling_reg <= '1';
end if;
-- Detect I2C START condition
start_reg <= '0';
stop_reg <= '0';
if scl_internal = '1' and scl_prev_reg = '1' and
sda_prev_reg = '1' and sda_internal = '0' then
start_reg <= '1';
stop_reg <= '0';
end if;
-- Detect I2C STOP condition
if scl_prev_reg = '1' and scl_internal = '1' and
sda_prev_reg = '0' and sda_internal = '1' then
start_reg <= '0';
stop_reg <= '1';
end if;
end if;
end process;
----------------------------------------------------------
-- I2C state machine
----------------------------------------------------------
process (clk) is
begin
if rising_edge(clk) then
-- Default assignments
sda_o_reg <= '0';
sda_wen_reg <= '0';
-- User interface
data_valid_reg <= '0';
read_req_reg <= '0';
case state_reg is
when idle =>
if start_reg = '1' then
state_reg <= get_address_and_cmd;
bits_processed_reg <= 0;
end if;
when get_address_and_cmd =>
if scl_rising_reg = '1' then
if bits_processed_reg < 7 then
bits_processed_reg <= bits_processed_reg + 1;
addr_reg(6-bits_processed_reg) <= sda_internal;
elsif bits_processed_reg = 7 then
bits_processed_reg <= bits_processed_reg + 1;
cmd_reg <= sda_internal;
end if;
end if;
if bits_processed_reg = 8 and scl_falling_reg = '1' then
bits_processed_reg <= 0;
if addr_reg = MINION_ADDR then -- check req address
state_reg <= answer_ack_start;
if cmd_reg = '1' then -- issue read request
read_req_reg <= '1';
data_to_master_reg <= data_to_master;
end if;
else
assert false
report ("I2C: target/minion address mismatch (data is being sent to another minion).")
severity note;
state_reg <= idle;
end if;
end if;
----------------------------------------------------
-- I2C acknowledge to master
----------------------------------------------------
when answer_ack_start =>
sda_wen_reg <= '1';
sda_o_reg <= '0';
if scl_falling_reg = '1' then
if cmd_reg = '0' then
state_reg <= write;
else
state_reg <= read;
end if;
end if;
----------------------------------------------------
-- WRITE
----------------------------------------------------
when write =>
if scl_rising_reg = '1' then
bits_processed_reg <= bits_processed_reg + 1;
if bits_processed_reg < 7 then
data_reg(6-bits_processed_reg) <= sda_internal;
else
data_from_master_reg <= data_reg & sda_internal;
data_valid_reg <= '1';
end if;
end if;
if scl_falling_reg = '1' and bits_processed_reg = 8 then
state_reg <= answer_ack_start;
bits_processed_reg <= 0;
end if;
----------------------------------------------------
-- READ: send data to master
----------------------------------------------------
when read =>
sda_wen_reg <= '1';
if data_to_master_reg(7-bits_processed_reg) = '0' then
sda_o_reg <= '0';
else
sda_o_reg <= 'Z';
end if;
if scl_falling_reg = '1' then
if bits_processed_reg < 7 then
bits_processed_reg <= bits_processed_reg + 1;
elsif bits_processed_reg = 7 then
state_reg <= read_ack_start;
bits_processed_reg <= 0;
end if;
end if;
----------------------------------------------------
-- I2C read master acknowledge
----------------------------------------------------
when read_ack_start =>
if scl_rising_reg = '1' then
state_reg <= read_ack_got_rising;
if sda_internal = '1' then -- nack = stop read
continue_reg <= '0';
else -- ack = continue read
continue_reg <= '1';
read_req_reg <= '1'; -- request reg byte
data_to_master_reg <= data_to_master;
end if;
end if;
when read_ack_got_rising =>
if scl_falling_reg = '1' then
if continue_reg = '1' then
if cmd_reg = '0' then
state_reg <= write;
else
state_reg <= read;
end if;
else
state_reg <= read_stop;
end if;
end if;
-- Wait for START or STOP to get out of this state
when read_stop =>
null;
-- Wait for START or STOP to get out of this state
when others =>
assert false
report ("I2C: error: ended in an impossible state.")
severity error;
state_reg <= idle;
end case;
--------------------------------------------------------
-- Reset counter and state on start/stop
--------------------------------------------------------
if start_reg = '1' then
state_reg <= get_address_and_cmd;
bits_processed_reg <= 0;
end if;
if stop_reg = '1' then
state_reg <= idle;
bits_processed_reg <= 0;
end if;
if rst = '1' then
state_reg <= idle;
end if;
end if;
end process;
----------------------------------------------------------
-- I2C interface
----------------------------------------------------------
sda <= sda_o_reg when sda_wen_reg = '1' else
'Z';
scl <= scl_o_reg when scl_wen_reg = '1' else
'Z';
----------------------------------------------------------
-- User interface
----------------------------------------------------------
-- Master writes
data_valid <= data_valid_reg;
data_from_master <= data_from_master_reg;
-- Master reads
read_req <= read_req_reg;
end architecture arch;
|
mit
|
827bc7a5eb202d2dc243b07c3b280fe6
| 0.453601 | 4.124908 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/PdmSer.vhd
| 1 | 5,013 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:25:21 04/02/2013
-- Design Name:
-- Module Name: PdmSer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module represents the serializer for the audio output data. The module generates
-- an internal clk_int signal, having the same frequency as the M_CLK signal sent to the
-- ADMP421 Microphone (see description of the PdmDes component). Data is sent to the audio line
-- at the positive edge of this internal clk signal.
-- The audio data is filtered on the board by the Sallen-Key Butterworth Low Pass 4th Order Filter
-- and sent to the audio output.
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PdmSer is
generic(
C_NR_OF_BITS : integer := 16;
C_SYS_CLK_FREQ_MHZ : integer := 100;
C_PDM_FREQ_HZ : integer := 2000000
);
port(
clk_i : in std_logic;
en_i : in std_logic; -- Enable serializing (during playback)
done_o : out std_logic; -- Signaling that data_i is sent
data_i : in std_logic_vector(C_NR_OF_BITS - 1 downto 0); -- input data
-- PWM
pwm_audio_o : inout std_logic -- Output audio data
);
end PdmSer;
architecture Behavioral of PdmSer is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- divider to create clk_int
signal cnt_clk : integer range 0 to 255 := 0;
-- internal pdm_clk signal
signal clk_int : std_logic := '0';
-- Piped clk_int signal to create pdm_clk_rising
signal pdm_clk_rising : std_logic;
-- Shift register used to temporary store then serialize data
signal pdm_s_tmp : std_logic_vector((C_NR_OF_BITS-1) downto 0);
-- Count the number of bits
signal cnt_bits : integer range 0 to 31 := 0;
signal en_int, done_int : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- Register en_i
SYNC: process(clk_i)
begin
if rising_edge(clk_i) then
en_int <= en_i;
end if;
end process SYNC;
-- Count the number of sampled bits
CNT: process(clk_i) begin
if rising_edge(clk_i) then
if en_int = '0' then
cnt_bits <= 0;
else
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
cnt_bits <= 0;
else
cnt_bits <= cnt_bits + 1;
end if;
end if;
end if;
end if;
end process CNT;
-- Generate done_o when the number of bits are serialized
process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = (C_NR_OF_BITS-1) then
done_int <= '1';
end if;
else
done_int <= '0';
end if;
end if;
end process;
done_o <= done_int;
------------------------------------------------------------------------
-- Serializer
------------------------------------------------------------------------
SHFT_OUT: process(clk_i)
begin
if rising_edge(clk_i) then
if pdm_clk_rising = '1' then
if cnt_bits = 0 then
pdm_s_tmp <= data_i;
else
pdm_s_tmp <= pdm_s_tmp(C_NR_OF_BITS-2 downto 0) & '0';
end if;
end if;
end if;
end process SHFT_OUT;
-- output the serial pdm data
pwm_audio_o <= '0' when pdm_s_tmp(C_NR_OF_BITS-1) = '0' else 'Z';
-- Generate the internal PDM Clock
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if en_int = '0' then
cnt_clk <= 0;
pdm_clk_rising <= '0';
else
if cnt_clk = (((C_SYS_CLK_FREQ_MHZ*1000000)/C_PDM_FREQ_HZ)-1) then
cnt_clk <= 0;
pdm_clk_rising <= '1';
else
cnt_clk <= cnt_clk + 1;
pdm_clk_rising <= '0';
end if;
end if;
end if;
end process CLK_CNT;
end Behavioral;
|
gpl-3.0
|
8bb51b36c046ed921ed4b0e2bcc7dd24
| 0.492519 | 4.065693 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/v_ram/sim/v_ram.vhd
| 1 | 12,515 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY v_ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END v_ram;
ARCHITECTURE v_ram_arch OF v_ram IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF v_ram_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 1,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "v_ram.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 12,
C_READ_WIDTH_A => 12,
C_WRITE_DEPTH_A => 76800,
C_READ_DEPTH_A => 76800,
C_ADDRA_WIDTH => 17,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 12,
C_READ_WIDTH_B => 12,
C_WRITE_DEPTH_B => 76800,
C_READ_DEPTH_B => 76800,
C_ADDRB_WIDTH => 17,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "26",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 16.2184 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => addrb,
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END v_ram_arch;
|
mit
|
8538f56d1a1b5eb40932a80d887444c2
| 0.60799 | 3.213094 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/virtex2p.vhd
| 1 | 197,297 |
library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity PULLUP is
port (
O : out std_logic
);
attribute syn_not_a_driver : boolean;
attribute syn_not_a_driver of O : signal is true;
end entity PULLUP;
architecture bb of PULLUP is
attribute syn_black_box of bb : architecture is true;
attribute syn_noprune of bb : architecture is true;
begin
end architecture bb;
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity PULLDOWN is
port (
O : out std_logic
);
attribute syn_not_a_driver : boolean;
attribute syn_not_a_driver of O : signal is true;
end entity PULLDOWN;
architecture bb of PULLDOWN is
attribute syn_black_box of bb : architecture is true;
attribute syn_noprune of bb : architecture is true;
begin
end architecture bb;
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
entity LUT1 is
generic (INIT : bit_vector(1 downto 0));
port (
O : out std_logic;
I0 : in std_logic
);
end entity LUT1;
architecture lut of LUT1 is
attribute xc_map of lut : architecture is "lut";
begin
O <= To_StdULogic(INIT(1)) when I0 = '1' else To_StdULogic(INIT(0));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT2 is
generic (INIT : bit_vector(3 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end entity LUT2;
architecture lut of LUT2 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(1 downto 0);
signal tmp : integer range 0 to 7;
begin
b <= (I1, I0);
tmp <= conv_integer(b);
O <= To_StdULogic(INIT(tmp));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT3 is
generic (INIT : bit_vector(7 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end entity LUT3;
architecture lut of LUT3 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(2 downto 0);
signal tmp : integer range 0 to 7;
begin
b <= (I2, I1, I0);
tmp <= conv_integer(b);
O <= To_StdULogic(INIT(tmp));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity LUT4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end entity LUT4;
architecture lut of LUT4 is
attribute xc_map of lut : architecture is "lut";
signal b : std_logic_vector(3 downto 0);
signal tmp : integer range 0 to 15;
begin
b <= (I3, I2, I1, I0);
tmp <= conv_integer(b);
O <= To_StdUlogic(INIT(tmp));
end architecture lut;
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.attributes.all;
package components is
attribute syn_black_box of components : package is true;
attribute syn_noprune : boolean;
component BSCAN_VIRTEX2
port (
TDO1 : in std_logic;
TDO2 : in std_logic;
CAPTURE : out std_logic;
DRCK1 : out std_logic;
DRCK2 : out std_logic;
RESET : out std_logic;
SEL1 : out std_logic;
SEL2 : out std_logic;
SHIFT : out std_logic;
TDI : out std_logic;
UPDATE : out std_logic
);
end component;
attribute syn_black_box of BSCAN_VIRTEX2 : component is true;
component BUF
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUF : component is true;
component BUFCF
port (
O : out std_logic;
I : in std_logic
);
end component;
component BUFE
port (
O : out std_logic;
E : in std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFE : component is true;
attribute black_box_tri_pins of BUFE : component is "O";
component BUFG
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFG : component is true;
component BUFGDLL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFGDLL : component is true;
component BUFGMUX0
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of BUFGMUX0 : component is true;
component BUFGMUX1
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of BUFGMUX1 : component is true;
component BUFGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of BUFGP : component is true;
component BUFT
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of BUFT : component is true;
attribute black_box_tri_pins of BUFT : component is "O";
component CAPTURE_VIRTEX2
port (
CAP : in std_logic;
CLK : in std_logic
);
end component;
attribute syn_black_box of CAPTURE_VIRTEX2 : component is true;
attribute syn_noprune of CAPTURE_VIRTEX2 : component is true;
component CLKDLL
port (
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of CLKDLL : component is true;
component CLKDLLE
port (
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of CLKDLLE : component is true;
component CLKDLLHF
port (
CLK0 : out std_logic;
CLK180 : out std_logic;
CLKDV : out std_logic;
LOCKED : out std_logic;
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of CLKDLLHF : component is true;
component DCM
generic (DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLK_FEEDBACK : string := "1X";
CLKOUT_PHASE_SHIFT : string := "NONE";
FACTORY_JF : bit_vector := X"C080";
STARTUP_WAIT : boolean := FALSE;
DSS_MODE : string := "NONE";
PHASE_SHIFT : integer := 0 ;
CLKFX_MULTIPLY : integer := 4 ;
CLKFX_DIVIDE : integer := 1;
CLKDV_DIVIDE : real := 2.0;
CLKIN_PERIOD : real := 0.0;
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"
);
port ( CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector(7 downto 0)
);
end component;
attribute syn_black_box of DCM : component is true;
component FD
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FD : component is true;
component FDC
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDC : component is true;
component FDCE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDCE : component is true;
component FDCE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDCE_1 : component is true;
component FDCP
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCP : component is true;
component FDCPE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCPE : component is true;
component FDCPE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCPE_1 : component is true;
component FDCP_1
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDCP_1 : component is true;
component FDC_1
port (
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDC_1 : component is true;
component FDDRCPE
port (
Q : out std_logic;
C0 : in std_logic;
C1 : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDDRCPE : component is true;
component FDDRRSE
port (
Q : out std_logic;
C0 : in std_logic;
C1 : in std_logic;
CE : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDDRRSE : component is true;
component FDE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDE : component is true;
component FDE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FDE_1 : component is true;
component FDP
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDP : component is true;
component FDPE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDPE : component is true;
component FDPE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDPE_1 : component is true;
component FDP_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of FDP_1 : component is true;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDR : component is true;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDRE : component is true;
component FDRE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDRE_1 : component is true;
component FDRS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRS : component is true;
component FDRSE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRSE : component is true;
component FDRSE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRSE_1 : component is true;
component FDRS_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDRS_1 : component is true;
component FDR_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
attribute syn_black_box of FDR_1 : component is true;
component FDS
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDS : component is true;
component FDSE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDSE : component is true;
component FDSE_1
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDSE_1 : component is true;
component FDS_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of FDS_1 : component is true;
component FD_1
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of FD_1 : component is true;
component GND
port (
G : out std_logic
);
end component;
attribute syn_black_box of GND : component is true;
attribute syn_noprune of GND : component is true;
component IBUF
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF : component is true;
component IBUFDS
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS : component is true;
component IBUFDS_BLVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_BLVDS_25 : component is true;
component IBUFDS_LDT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LDT_25 : component is true;
component IBUFDS_LVDSEXT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDSEXT_25 : component is true;
component IBUFDS_LVDSEXT_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDSEXT_33 : component is true;
component IBUFDS_LVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDS_25 : component is true;
component IBUFDS_LVDS_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVDS_33 : component is true;
component IBUFDS_LVPECL_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_LVPECL_33 : component is true;
component IBUFDS_ULVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFDS_ULVDS_25 : component is true;
component IBUFG
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG : component is true;
component IBUFGDS
generic (
IOSTANDARD : string := "default"
);
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS : component is true;
component IBUFGDS_BLVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_BLVDS_25 : component is true;
component IBUFGDS_LDT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LDT_25 : component is true;
component IBUFGDS_LVDSEXT_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDSEXT_25 : component is true;
component IBUFGDS_LVDSEXT_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDSEXT_33 : component is true;
component IBUFGDS_LVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDS_25 : component is true;
component IBUFGDS_LVDS_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVDS_33 : component is true;
component IBUFGDS_LVPECL_33
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_LVPECL_33 : component is true;
component IBUFGDS_ULVDS_25
port (
O : out std_logic;
I : in std_logic;
IB : in std_logic
);
end component;
attribute syn_black_box of IBUFGDS_ULVDS_25 : component is true;
component IBUFG_AGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_AGP : component is true;
component IBUFG_GTL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTL : component is true;
component IBUFG_GTL_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTL_DCI : component is true;
component IBUFG_GTLP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTLP : component is true;
component IBUFG_GTLP_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_GTLP_DCI : component is true;
component IBUFG_HSTL_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I : component is true;
component IBUFG_HSTL_I_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I_18 : component is true;
component IBUFG_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I_DCI : component is true;
component IBUFG_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_I_DCI_18 : component is true;
component IBUFG_HSTL_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II : component is true;
component IBUFG_HSTL_II_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II_18 : component is true;
component IBUFG_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II_DCI : component is true;
component IBUFG_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_II_DCI_18 : component is true;
component IBUFG_HSTL_III
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III : component is true;
component IBUFG_HSTL_III_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III_18 : component is true;
component IBUFG_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III_DCI : component is true;
component IBUFG_HSTL_III_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_III_DCI_18 : component is true;
component IBUFG_HSTL_IV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV : component is true;
component IBUFG_HSTL_IV_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV_18 : component is true;
component IBUFG_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV_DCI : component is true;
component IBUFG_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_HSTL_IV_DCI_18 : component is true;
component IBUFG_LVDCI_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_15 : component is true;
component IBUFG_LVDCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_18 : component is true;
component IBUFG_LVDCI_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_25 : component is true;
component IBUFG_LVDCI_33
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_33 : component is true;
component IBUFG_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_15 : component is true;
component IBUFG_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_18 : component is true;
component IBUFG_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVDCI_DV2_25 : component is true;
component IBUFG_LVCMOS15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS15 : component is true;
component IBUFG_LVCMOS18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS18 : component is true;
component IBUFG_LVCMOS2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS2 : component is true;
component IBUFG_LVCMOS25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_LVCMOS25 : component is true;
component IBUFG_PCI33_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_PCI33_3 : component is true;
component IBUFG_PCI66_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_PCI66_3 : component is true;
component IBUFG_PCIX
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_PCIX : component is true;
component IBUFG_SSTL2_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_I : component is true;
component IBUFG_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_I_DCI : component is true;
component IBUFG_SSTL2_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_II : component is true;
component IBUFG_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUFG_SSTL2_II_DCI : component is true;
component IBUF_AGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_AGP : component is true;
component IBUF_GTL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTL : component is true;
component IBUF_GTL_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTL_DCI : component is true;
component IBUF_GTLP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTLP : component is true;
component IBUF_GTLP_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_GTLP_DCI : component is true;
component IBUF_HSTL_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I : component is true;
component IBUF_HSTL_I_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I_18 : component is true;
component IBUF_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I_DCI : component is true;
component IBUF_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_I_DCI_18 : component is true;
component IBUF_HSTL_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II : component is true;
component IBUF_HSTL_II_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II_18 : component is true;
component IBUF_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II_DCI : component is true;
component IBUF_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_II_DCI_18 : component is true;
component IBUF_HSTL_III
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III : component is true;
component IBUF_HSTL_III_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III_18 : component is true;
component IBUF_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III_DCI : component is true;
component IBUF_HSTL_III_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_III_DCI_18 : component is true;
component IBUF_HSTL_IV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV : component is true;
component IBUF_HSTL_IV_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV_18 : component is true;
component IBUF_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV_DCI : component is true;
component IBUF_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_HSTL_IV_DCI_18 : component is true;
component IBUF_LVCMOS15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS15 : component is true;
component IBUF_LVCMOS18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS18 : component is true;
component IBUF_LVCMOS2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS2 : component is true;
component IBUF_LVCMOS25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVCMOS25 : component is true;
component IBUF_LVDCI_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_15 : component is true;
component IBUF_LVDCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_18 : component is true;
component IBUF_LVDCI_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_25 : component is true;
component IBUF_LVDCI_33
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_33 : component is true;
component IBUF_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_15 : component is true;
component IBUF_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_18 : component is true;
component IBUF_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDCI_DV2_25 : component is true;
component IBUF_LVDS
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVDS : component is true;
component IBUF_LVPECL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_LVPECL : component is true;
component IBUF_PCI33_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_PCI33_3 : component is true;
component IBUF_PCI66_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_PCI66_3 : component is true;
component IBUF_PCIX
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_PCIX : component is true;
component IBUF_SSTL2_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_I : component is true;
component IBUF_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_I_DCI : component is true;
component IBUF_SSTL2_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_II : component is true;
component IBUF_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of IBUF_SSTL2_II_DCI : component is true;
component INV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of INV : component is true;
component PIPEBUF
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of PIPEBUF : component is true;
component IOBUF
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF : component is true;
component IOBUFDS
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
IO : inout std_logic;
IOB : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUFDS : component is true;
component IOBUFDS_BLVDS_25
port (
O : out std_logic;
IO : inout std_logic;
IOB : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUFDS_BLVDS_25 : component is true;
component IOBUFDS_LVPECL_33
port (
O : out std_logic;
IO : inout std_logic;
IOB : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUFDS_LVPECL_33 : component is true;
component IOBUF_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_12 : component is true;
component IOBUF_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_16 : component is true;
component IOBUF_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_2 : component is true;
component IOBUF_F_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_24 : component is true;
component IOBUF_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_4 : component is true;
component IOBUF_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_6 : component is true;
component IOBUF_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_F_8 : component is true;
component IOBUF_GTL
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTL : component is true;
component IOBUF_GTL_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTL_DCI : component is true;
component IOBUF_GTLP
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTLP : component is true;
component IOBUF_GTLP_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_GTLP_DCI : component is true;
component IOBUF_HSTL_I
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_I : component is true;
component IOBUF_HSTL_I_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_I_18 : component is true;
component IOBUF_HSTL_I_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_I_DCI : component is true;
component IOBUF_HSTL_II
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II : component is true;
component IOBUF_HSTL_II_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II_18 : component is true;
component IOBUF_HSTL_II_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II_DCI : component is true;
component IOBUF_HSTL_II_DCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_II_DCI_18 : component is true;
component IOBUF_HSTL_III
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III : component is true;
component IOBUF_HSTL_III_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III_18 : component is true;
component IOBUF_HSTL_III_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III_DCI : component is true;
component IOBUF_HSTL_III_DCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_III_DCI_18 : component is true;
component IOBUF_HSTL_IV
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV : component is true;
component IOBUF_HSTL_IV_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV_18 : component is true;
component IOBUF_HSTL_IV_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV_DCI : component is true;
component IOBUF_HSTL_IV_DCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_HSTL_IV_DCI_18 : component is true;
component IOBUF_LVCMOS15
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15 : component is true;
component IOBUF_LVCMOS15_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_12 : component is true;
component IOBUF_LVCMOS15_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_16 : component is true;
component IOBUF_LVCMOS15_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_2 : component is true;
component IOBUF_LVCMOS15_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_4 : component is true;
component IOBUF_LVCMOS15_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_6 : component is true;
component IOBUF_LVCMOS15_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_F_8 : component is true;
component IOBUF_LVCMOS15_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_12 : component is true;
component IOBUF_LVCMOS15_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_16 : component is true;
component IOBUF_LVCMOS15_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_2 : component is true;
component IOBUF_LVCMOS15_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_4 : component is true;
component IOBUF_LVCMOS15_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_6 : component is true;
component IOBUF_LVCMOS15_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS15_S_8 : component is true;
component IOBUF_LVCMOS18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18 : component is true;
component IOBUF_LVCMOS18_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_12 : component is true;
component IOBUF_LVCMOS18_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_16 : component is true;
component IOBUF_LVCMOS18_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_2 : component is true;
component IOBUF_LVCMOS18_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_4 : component is true;
component IOBUF_LVCMOS18_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_6 : component is true;
component IOBUF_LVCMOS18_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_F_8 : component is true;
component IOBUF_LVCMOS18_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_12 : component is true;
component IOBUF_LVCMOS18_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_16 : component is true;
component IOBUF_LVCMOS18_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_2 : component is true;
component IOBUF_LVCMOS18_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_4 : component is true;
component IOBUF_LVCMOS18_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_6 : component is true;
component IOBUF_LVCMOS18_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS18_S_8 : component is true;
component IOBUF_LVCMOS2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS2 : component is true;
component IOBUF_LVCMOS25
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25 : component is true;
component IOBUF_LVCMOS25_F_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_12 : component is true;
component IOBUF_LVCMOS25_F_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_16 : component is true;
component IOBUF_LVCMOS25_F_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_2 : component is true;
component IOBUF_LVCMOS25_F_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_24 : component is true;
component IOBUF_LVCMOS25_F_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_4 : component is true;
component IOBUF_LVCMOS25_F_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_6 : component is true;
component IOBUF_LVCMOS25_F_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_F_8 : component is true;
component IOBUF_LVCMOS25_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_12 : component is true;
component IOBUF_LVCMOS25_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_16 : component is true;
component IOBUF_LVCMOS25_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_2 : component is true;
component IOBUF_LVCMOS25_S_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_24 : component is true;
component IOBUF_LVCMOS25_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_4 : component is true;
component IOBUF_LVCMOS25_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_6 : component is true;
component IOBUF_LVCMOS25_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVCMOS25_S_8 : component is true;
component IOBUF_LVDCI_15
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_15 : component is true;
component IOBUF_LVDCI_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_18 : component is true;
component IOBUF_LVDCI_25
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_25 : component is true;
component IOBUF_LVDCI_33
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_33 : component is true;
component IOBUF_LVDCI_DV2_15
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_15 : component is true;
component IOBUF_LVDCI_DV2_18
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_18 : component is true;
component IOBUF_LVDCI_DV2_25
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_25 : component is true;
component IOBUF_LVDS
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVDS : component is true;
component IOBUF_LVPECL
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_LVPECL : component is true;
component IOBUF_PCI33_3
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_PCI33_3 : component is true;
component IOBUF_PCI66_3
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_PCI66_3 : component is true;
component IOBUF_PCIX
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_PCIX : component is true;
component IOBUF_SSTL2_I
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_I : component is true;
component IOBUF_SSTL2_I_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_I_DCI : component is true;
component IOBUF_SSTL2_II
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_II : component is true;
component IOBUF_SSTL2_II_DCI
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_SSTL2_II_DCI : component is true;
component IOBUF_S_12
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_12 : component is true;
component IOBUF_S_16
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_16 : component is true;
component IOBUF_S_2
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_2 : component is true;
component IOBUF_S_24
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_24 : component is true;
component IOBUF_S_4
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_4 : component is true;
component IOBUF_S_6
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_6 : component is true;
component IOBUF_S_8
port (
O : out std_logic;
IO : inout std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of IOBUF_S_8 : component is true;
component KEEPER
port (
O : inout std_logic
);
end component;
attribute syn_black_box of KEEPER : component is true;
attribute syn_noprune of KEEPER : component is true;
component LD
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LD : component is true;
component LDC
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LDC : component is true;
component LDCE
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDCE : component is true;
component LDCE_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDCE_1 : component is true;
component LDCP
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCP : component is true;
component LDCPE
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCPE : component is true;
component LDCPE_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCPE_1 : component is true;
component LDCP_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDCP_1 : component is true;
component LDC_1
port (
Q : out std_logic;
CLR : in std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LDC_1 : component is true;
component LDE
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDE : component is true;
component LDE_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic
);
end component;
attribute syn_black_box of LDE_1 : component is true;
component LDP
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDP : component is true;
component LDPE
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDPE : component is true;
component LDPE_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
GE : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDPE_1 : component is true;
component LDP_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic;
PRE : in std_logic
);
end component;
attribute syn_black_box of LDP_1 : component is true;
component LD_1
port (
Q : out std_logic;
D : in std_logic;
G : in std_logic
);
end component;
attribute syn_black_box of LD_1 : component is true;
component LUT1
generic(INIT : bit_vector := "00");
port (
O : out std_logic;
I0 : in std_logic
);
end component;
attribute syn_black_box of LUT1 : component is true;
attribute xc_map of LUT1 : component is "lut";
component LUT1_D
generic(INIT : bit_vector := "00");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic
);
end component;
attribute syn_black_box of LUT1_D : component is true;
attribute xc_map of LUT1_D : component is "lut";
component LUT1_L
generic(INIT : bit_vector := "00");
port (
LO : out std_logic;
I0 : in std_logic
);
end component;
attribute syn_black_box of LUT1_L : component is true;
attribute xc_map of LUT1_L : component is "lut";
component LUT2
generic(INIT : bit_vector := X"0");
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of LUT2 : component is true;
attribute xc_map of LUT2 : component is "lut";
component LUT2_D
generic(INIT : bit_vector := X"0");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of LUT2_D : component is true;
attribute xc_map of LUT2_D : component is "lut";
component LUT2_L
generic(INIT : bit_vector := X"0");
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of LUT2_L : component is true;
attribute xc_map of LUT2_L : component is "lut";
component LUT3
generic(INIT : bit_vector := X"00");
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end component;
attribute syn_black_box of LUT3 : component is true;
attribute xc_map of LUT3 : component is "lut";
component LUT3_D
generic(INIT : bit_vector := X"00");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end component;
attribute syn_black_box of LUT3_D : component is true;
attribute xc_map of LUT3_D : component is "lut";
component LUT3_L
generic(INIT : bit_vector := X"00");
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic
);
end component;
attribute syn_black_box of LUT3_L : component is true;
attribute xc_map of LUT3_L : component is "lut";
component LUT4
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
attribute syn_black_box of LUT4 : component is true;
attribute xc_map of LUT4 : component is "lut";
component LUT4_D
generic(INIT : bit_vector := X"0000");
port (
LO : out std_logic;
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
attribute syn_black_box of LUT4_D : component is true;
attribute xc_map of LUT4_D : component is "lut";
component LUT4_L
generic(INIT : bit_vector := X"0000");
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component;
attribute syn_black_box of LUT4_L : component is true;
attribute xc_map of LUT4_L : component is "lut";
component MULT18X18
port (
P : out std_logic_vector(35 downto 0);
A : in std_logic_Vector(17 downto 0);
B : in std_logic_vector(17 downto 0)
);
end component;
attribute syn_black_box of MULT18X18 : component is true;
component MULT18X18S
port (A : in STD_LOGIC_VECTOR (17 downto 0);
B : in STD_LOGIC_VECTOR (17 downto 0);
C : in STD_ULOGIC ;
CE : in STD_ULOGIC ;
P : out STD_LOGIC_VECTOR (35 downto 0);
R : in STD_ULOGIC );
end component;
attribute syn_black_box of MULT18X18S : component is true;
component MULT_AND
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic
);
end component;
attribute syn_black_box of MULT_AND : component is true;
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXCY : component is true;
component MUXCY_D
port (
O : out std_logic;
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXCY_D : component is true;
component MUXCY_L
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXCY_L : component is true;
component MUXF5
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF5 : component is true;
component MUXF5_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF5_D : component is true;
component MUXF5_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF5_L : component is true;
component MUXF6
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF6 : component is true;
component MUXF6_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF6_D : component is true;
component MUXF6_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF6_L : component is true;
component MUXF7
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF7 : component is true;
component MUXF7_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF7_D : component is true;
component MUXF7_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF7_L : component is true;
component MUXF8
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF8 : component is true;
component MUXF8_D
port (
O : out std_logic;
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF8_D : component is true;
component MUXF8_L
port (
LO : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component;
attribute syn_black_box of MUXF8_L : component is true;
component OBUF
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF : component is true;
component OBUFDS
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS : component is true;
component OBUFDS_BLVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_BLVDS_25 : component is true;
component OBUFDS_LDT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LDT_25 : component is true;
component OBUFDS_LVDSEXT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDSEXT_25 : component is true;
component OBUFDS_LVDSEXT_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDSEXT_33 : component is true;
component OBUFDS_LVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDS_25 : component is true;
component OBUFDS_LVDS_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVDS_33 : component is true;
component OBUFDS_ULVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_ULVDS_25 : component is true;
component OBUFDS_LVPECL_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUFDS_LVPECL_33 : component is true;
component OBUFT
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT : component is true;
attribute black_box_tri_pins of OBUFT : component is "O";
component OBUFTDS
generic (
IOSTANDARD : string := "default";
SLEW : string := "SLOW";
DRIVE : integer := 12
);
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS : component is true;
attribute black_box_tri_pins of OBUFTDS : component is "O,OB";
component OBUFTDS_BLVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_BLVDS_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_BLVDS_25 : component is "O,OB";
component OBUFTDS_LDT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LDT_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_LDT_25 : component is "O,OB";
component OBUFTDS_LVDSEXT_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDSEXT_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDSEXT_25 : component is "O,OB";
component OBUFTDS_LVDSEXT_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDSEXT_33 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDSEXT_33 : component is "O,OB";
component OBUFTDS_LVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDS_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDS_25 : component is "O,OB";
component OBUFTDS_LVDS_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVDS_33 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVDS_33 : component is "O,OB";
component OBUFTDS_ULVDS_25
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_ULVDS_25 : component is true;
attribute black_box_tri_pins of OBUFTDS_ULVDS_25 : component is "O,OB";
component OBUFTDS_LVPECL_33
port (
O : out std_logic;
OB : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFTDS_LVPECL_33 : component is true;
attribute black_box_tri_pins of OBUFTDS_LVPECL_33 : component is "O,OB";
component OBUFT_AGP
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_AGP : component is true;
attribute black_box_tri_pins of OBUFT_AGP : component is "O";
component OBUFT_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_F_12 : component is "O";
component OBUFT_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_F_16 : component is "O";
component OBUFT_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_F_2 : component is "O";
component OBUFT_F_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_24 : component is true;
attribute black_box_tri_pins of OBUFT_F_24 : component is "O";
component OBUFT_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_F_4 : component is "O";
component OBUFT_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_F_6 : component is "O";
component OBUFT_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_F_8 : component is "O";
component OBUFT_GTL
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTL : component is true;
attribute black_box_tri_pins of OBUFT_GTL : component is "O";
component OBUFT_GTL_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTL_DCI : component is true;
attribute black_box_tri_pins of OBUFT_GTL_DCI : component is "O";
component OBUFT_GTLP
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTLP : component is true;
attribute black_box_tri_pins of OBUFT_GTLP : component is "O";
component OBUFT_GTLP_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_GTLP_DCI : component is true;
attribute black_box_tri_pins of OBUFT_GTLP_DCI : component is "O";
component OBUFT_HSTL_I
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_I : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I : component is "O";
component OBUFT_HSTL_I_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_I_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I_18 : component is "O";
component OBUFT_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_I_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I_DCI : component is "O";
component OBUFT_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_Box of OBUFT_HSTL_I_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_I_DCI_18 : component is "O";
component OBUFT_HSTL_II
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II : component is "O";
component OBUFT_HSTL_II_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II_18 : component is "O";
component OBUFT_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II_DCI : component is "O";
component OBUFT_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_II_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_II_DCI_18 : component is "O";
component OBUFT_HSTL_III
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III : component is "O";
component OBUFT_HSTL_III_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III_18 : component is "O";
component OBUFT_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III_DCI : component is "O";
component OBUFT_HSTL_III_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_III_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_III_DCI_18 : component is "O";
component OBUFT_HSTL_IV
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_IV : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_IV : component is "O";
component OBUFT_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_IV_DCI : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_IV_DCI : component is "O";
component OBUFT_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_HSTL_IV_DCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_HSTL_IV_DCI_18 : component is "O";
component OBUFT_LVCMOS15
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15 : component is "O";
component OBUFT_LVCMOS15_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_12 : component is "O";
component OBUFT_LVCMOS15_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_16 : component is "O";
component OBUFT_LVCMOS15_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_2 : component is "O";
component OBUFT_LVCMOS15_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_4 : component is "O";
component OBUFT_LVCMOS15_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_6 : component is "O";
component OBUFT_LVCMOS15_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_F_8 : component is "O";
component OBUFT_LVCMOS15_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_12 : component is "O";
component OBUFT_LVCMOS15_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_16 : component is "O";
component OBUFT_LVCMOS15_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_2 : component is "O";
component OBUFT_LVCMOS15_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_4 : component is "O";
component OBUFT_LVCMOS15_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_6 : component is "O";
component OBUFT_LVCMOS15_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS15_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS15_S_8 : component is "O";
component OBUFT_LVCMOS18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18 : component is "O";
component OBUFT_LVCMOS18_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_12 : component is "O";
component OBUFT_LVCMOS18_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_16 : component is "O";
component OBUFT_LVCMOS18_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_2 : component is "O";
component OBUFT_LVCMOS18_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_4 : component is "O";
component OBUFT_LVCMOS18_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_6 : component is "O";
component OBUFT_LVCMOS18_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_F_8 : component is "O";
component OBUFT_LVCMOS18_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_12 : component is "O";
component OBUFT_LVCMOS18_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_16 : component is "O";
component OBUFT_LVCMOS18_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_2 : component is "O";
component OBUFT_LVCMOS18_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_4 : component is "O";
component OBUFT_LVCMOS18_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_6 : component is "O";
component OBUFT_LVCMOS18_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS18_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS18_S_8 : component is "O";
component OBUFT_LVCMOS2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS2 : component is "O";
component OBUFT_LVCMOS25
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25 : component is "O";
component OBUFT_LVCMOS25_F_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_12 : component is "O";
component OBUFT_LVCMOS25_F_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_16 : component is "O";
component OBUFT_LVCMOS25_F_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_2 : component is "O";
component OBUFT_LVCMOS25_F_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_24 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_24 : component is "O";
component OBUFT_LVCMOS25_F_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_4 : component is "O";
component OBUFT_LVCMOS25_F_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_6 : component is "O";
component OBUFT_LVCMOS25_F_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_F_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_F_8 : component is "O";
component OBUFT_LVCMOS25_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_12 : component is "O";
component OBUFT_LVCMOS25_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_16 : component is "O";
component OBUFT_LVCMOS25_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_2 : component is "O";
component OBUFT_LVCMOS25_S_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_24 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_24 : component is "O";
component OBUFT_LVCMOS25_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_4 : component is "O";
component OBUFT_LVCMOS25_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_6 : component is "O";
component OBUFT_LVCMOS25_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVCMOS25_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_LVCMOS25_S_8 : component is "O";
component OBUFT_LVDCI_15
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_15 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_15 : component is "O";
component OBUFT_LVDCI_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_18 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_18 : component is "O";
component OBUFT_LVDCI_25
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_25 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_25 : component is "O";
component OBUFT_LVDCI_33
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_33 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_33 : component is "O";
component OBUFT_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_DV2_15 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_DV2_15 : component is "O";
component OBUFT_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_DV2_18 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_DV2_18 : component is "O";
component OBUFT_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDCI_DV2_25 : component is true;
attribute black_box_tri_pins of OBUFT_LVDCI_DV2_25 : component is "O";
component OBUFT_LVDS
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVDS : component is true;
attribute black_box_tri_pins of OBUFT_LVDS : component is "O";
component OBUFT_LVPECL
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_LVPECL : component is true;
attribute black_box_tri_pins of OBUFT_LVPECL : component is "O";
component OBUFT_PCI33_3
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_PCI33_3 : component is true;
attribute black_box_tri_pins of OBUFT_PCI33_3 : component is "O";
component OBUFT_PCI66_3
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_PCI66_3 : component is true;
attribute black_box_tri_pins of OBUFT_PCI66_3 : component is "O";
component OBUFT_PCIX
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_PCIX : component is true;
attribute black_box_tri_pins of OBUFT_PCIX : component is "O";
component OBUFT_SSTL2_I
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_I : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_I : component is "O";
component OBUFT_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_I_DCI : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_I_DCI : component is "O";
component OBUFT_SSTL2_II
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_II : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_II : component is "O";
component OBUFT_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_SSTL2_II_DCI : component is true;
attribute black_box_tri_pins of OBUFT_SSTL2_II_DCI : component is "O";
component OBUFT_S_12
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_12 : component is true;
attribute black_box_tri_pins of OBUFT_S_12 : component is "O";
component OBUFT_S_16
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_16 : component is true;
attribute black_box_tri_pins of OBUFT_S_16 : component is "O";
component OBUFT_S_2
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_2 : component is true;
attribute black_box_tri_pins of OBUFT_S_2 : component is "O";
component OBUFT_S_24
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_24 : component is true;
attribute black_box_tri_pins of OBUFT_S_24 : component is "O";
component OBUFT_S_4
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_4 : component is true;
attribute black_box_tri_pins of OBUFT_S_4 : component is "O";
component OBUFT_S_6
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_6 : component is true;
attribute black_box_tri_pins of OBUFT_S_6 : component is "O";
component OBUFT_S_8
port (
O : out std_logic;
I : in std_logic;
T : in std_logic
);
end component;
attribute syn_black_box of OBUFT_S_8 : component is true;
attribute black_box_tri_pins of OBUFT_S_8 : component is "O";
component OBUF_AGP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_AGP : component is true;
component OBUF_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_12 : component is true;
component OBUF_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_16 : component is true;
component OBUF_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_2 : component is true;
component OBUF_F_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_24 : component is true;
component OBUF_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_4 : component is true;
component OBUF_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_6 : component is true;
component OBUF_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_F_8 : component is true;
component OBUF_GTL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTL : component is true;
component OBUF_GTL_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTL_DCI : component is true;
component OBUF_GTLP
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTLP : component is true;
component OBUF_GTLP_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_GTLP_DCI : component is true;
component OBUF_HSTL_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_I : component is true;
component OBUF_HSTL_I_18
port (
O : out std_logic;
i : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_I_18 : component is true;
component OBUF_HSTL_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_I_DCI : component is true;
component OBUF_HSTL_I_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_Box of OBUF_HSTL_I_DCI_18 : component is true;
component OBUF_HSTL_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II : component is true;
component OBUF_HSTL_II_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II_18 : component is true;
component OBUF_HSTL_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II_DCI : component is true;
component OBUF_HSTL_II_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_II_DCI_18 : component is true;
component OBUF_HSTL_III
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_III : component is true;
component OBUF_HSTL_III_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_III_18 : component is true;
component OBUF_HSTL_III_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_III_DCI : component is true;
component OBUF_HSTL_IV
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV : component is true;
component OBUF_HSTL_IV_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV_18 : component is true;
component OBUF_HSTL_IV_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV_DCI : component is true;
component OBUF_HSTL_IV_DCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_HSTL_IV_DCI_18 : component is true;
component OBUF_LVCMOS15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15 : component is true;
component OBUF_LVCMOS15_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_12 : component is true;
component OBUF_LVCMOS15_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_16 : component is true;
component OBUF_LVCMOS15_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_2 : component is true;
component OBUF_LVCMOS15_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_4 : component is true;
component OBUF_LVCMOS15_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_6 : component is true;
component OBUF_LVCMOS15_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_F_8 : component is true;
component OBUF_LVCMOS15_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_12 : component is true;
component OBUF_LVCMOS15_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_16 : component is true;
component OBUF_LVCMOS15_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_2 : component is true;
component OBUF_LVCMOS15_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_4 : component is true;
component OBUF_LVCMOS15_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_6 : component is true;
component OBUF_LVCMOS15_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS15_S_8 : component is true;
component OBUF_LVCMOS18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18 : component is true;
component OBUF_LVCMOS18_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_12 : component is true;
component OBUF_LVCMOS18_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_16 : component is true;
component OBUF_LVCMOS18_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_2 : component is true;
component OBUF_LVCMOS18_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_4 : component is true;
component OBUF_LVCMOS18_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_6 : component is true;
component OBUF_LVCMOS18_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_F_8 : component is true;
component OBUF_LVCMOS18_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_12 : component is true;
component OBUF_LVCMOS18_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_16 : component is true;
component OBUF_LVCMOS18_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_2 : component is true;
component OBUF_LVCMOS18_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_4 : component is true;
component OBUF_LVCMOS18_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_6 : component is true;
component OBUF_LVCMOS18_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS18_S_8 : component is true;
component OBUF_LVCMOS2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS2 : component is true;
component OBUF_LVCMOS25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25 : component is true;
component OBUF_LVCMOS25_F_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_12 : component is true;
component OBUF_LVCMOS25_F_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_16 : component is true;
component OBUF_LVCMOS25_F_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_2 : component is true;
component OBUF_LVCMOS25_F_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_24 : component is true;
component OBUF_LVCMOS25_F_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_4 : component is true;
component OBUF_LVCMOS25_F_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_6 : component is true;
component OBUF_LVCMOS25_F_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_F_8 : component is true;
component OBUF_LVCMOS25_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_12 : component is true;
component OBUF_LVCMOS25_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_16 : component is true;
component OBUF_LVCMOS25_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_2 : component is true;
component OBUF_LVCMOS25_S_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_24 : component is true;
component OBUF_LVCMOS25_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_4 : component is true;
component OBUF_LVCMOS25_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_6 : component is true;
component OBUF_LVCMOS25_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVCMOS25_S_8 : component is true;
component OBUF_LVDS
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDS : component is true;
component OBUF_LVDCI_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_15 : component is true;
component OBUF_LVDCI_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_18 : component is true;
component OBUF_LVDCI_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_25 : component is true;
component OBUF_LVDCI_33
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_33 : component is true;
component OBUF_LVDCI_DV2_15
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_DV2_15 : component is true;
component OBUF_LVDCI_DV2_18
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_DV2_18 : component is true;
component OBUF_LVDCI_DV2_25
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVDCI_DV2_25 : component is true;
component OBUF_LVPECL
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_LVPECL : component is true;
component OBUF_PCI33_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_PCI33_3 : component is true;
component OBUF_PCI66_3
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_PCI66_3 : component is true;
component OBUF_PCIX
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_PCIX : component is true;
component OBUF_SSTL2_I
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_I : component is true;
component OBUF_SSTL2_I_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_I_DCI : component is true;
component OBUF_SSTL2_II
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_II : component is true;
component OBUF_SSTL2_II_DCI
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_SSTL2_II_DCI : component is true;
component OBUF_S_12
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_12 : component is true;
component OBUF_S_16
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_16 : component is true;
component OBUF_S_2
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_2 : component is true;
component OBUF_S_24
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_24 : component is true;
component OBUF_S_4
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_4 : component is true;
component OBUF_S_6
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_6 : component is true;
component OBUF_S_8
port (
O : out std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of OBUF_S_8 : component is true;
component ORCY
port (
O : out std_logic;
CI : in std_logic;
I : in std_logic
);
end component;
attribute syn_black_box of ORCY : component is true;
component PULLDOWN
port (
O : out std_logic
);
end component;
attribute syn_black_box of PULLDOWN : component is true;
attribute syn_noprune of PULLDOWN : component is true;
component PULLUP
port (
O : out std_logic
);
end component;
attribute syn_black_box of PULLUP : component is true;
attribute syn_noprune of PULLUP : component is true;
component RAM128X1S
generic(INIT : bit_vector := X"00000000000000000000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM128X1S : component is true;
component RAM128X1S_1
generic(INIT : bit_vector := X"00000000000000000000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM128X1S_1 : component is true;
component RAM16X1D
generic(INIT : bit_vector := X"0000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1D : component is true;
component RAM16X1D_1
generic(INIT : bit_vector := X"0000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1D_1 : component is true;
component RAM16X1S
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1S : component is true;
component RAM16X1S_1
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X1S_1 : component is true;
component RAM16X2S
generic (
INIT_00 : bit_vector(15 downto 0) := X"0000";
INIT_01 : bit_vector(15 downto 0) := X"0000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X2S : component is true;
component RAM16X4S
generic (
INIT_00 : bit_vector(15 downto 0) := X"0000";
INIT_01 : bit_vector(15 downto 0) := X"0000";
INIT_02 : bit_vector(15 downto 0) := X"0000";
INIT_03 : bit_vector(15 downto 0) := X"0000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X4S : component is true;
component RAM16X8S
generic (
INIT_00 : bit_vector(15 downto 0) := X"0000";
INIT_01 : bit_vector(15 downto 0) := X"0000";
INIT_02 : bit_vector(15 downto 0) := X"0000";
INIT_03 : bit_vector(15 downto 0) := X"0000";
INIT_04 : bit_vector(15 downto 0) := X"0000";
INIT_05 : bit_vector(15 downto 0) := X"0000";
INIT_06 : bit_vector(15 downto 0) := X"0000";
INIT_07 : bit_vector(15 downto 0) := X"0000"
);
port (
O : out std_logic_vector(7 downto 0);
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
D : in std_logic_vector(7 downto 0);
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM16X8S : component is true;
component RAM32X1D
generic(INIT : bit_vector := X"00000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1D : component is true;
component RAM32X1D_1
generic(INIT : bit_vector := X"00000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1D_1 : component is true;
component RAM32X1S
generic(INIT : bit_vector := X"00000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1S : component is true;
component RAM32X1S_1
generic(INIT : bit_vector := X"00000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X1S_1 : component is true;
component RAM32X2S
generic (
INIT_00 : bit_vector(31 downto 0) := X"00000000";
INIT_01 : bit_vector(31 downto 0) := X"00000000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X2S : component is true;
component RAM32X4S
generic (
INIT_00 : bit_vector(31 downto 0) := X"00000000";
INIT_01 : bit_vector(31 downto 0) := X"00000000";
INIT_02 : bit_vector(31 downto 0) := X"00000000";
INIT_03 : bit_vector(31 downto 0) := X"00000000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
O2 : out std_logic;
O3 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
D2 : in std_logic;
D3 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X4S : component is true;
component RAM32X8S
generic (
INIT_00 : bit_vector(31 downto 0) := X"00000000";
INIT_01 : bit_vector(31 downto 0) := X"00000000";
INIT_02 : bit_vector(31 downto 0) := X"00000000";
INIT_03 : bit_vector(31 downto 0) := X"00000000";
INIT_04 : bit_vector(31 downto 0) := X"00000000";
INIT_05 : bit_vector(31 downto 0) := X"00000000";
INIT_06 : bit_vector(31 downto 0) := X"00000000";
INIT_07 : bit_vector(31 downto 0) := X"00000000"
);
port (
O : out std_logic_vector(7 downto 0);
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
D : in std_logic_vector(7 downto 0);
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM32X8S : component is true;
component RAM64X1D
generic (INIT : bit_vector := X"0000000000000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
DPRA5 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1D : component is true;
component RAM64X1D_1
generic (INIT : bit_vector := X"0000000000000000");
port (
DPO : out std_logic;
SPO : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
DPRA0 : in std_logic;
DPRA1 : in std_logic;
DPRA2 : in std_logic;
DPRA3 : in std_logic;
DPRA4 : in std_logic;
DPRA5 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1D_1 : component is true;
component RAM64X1S
generic (INIT : bit_vector := X"0000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1S : component is true;
component RAM64X1S_1
generic (INIT : bit_vector := X"0000000000000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X1S_1 : component is true;
component RAM64X2S
generic (
INIT_00 : bit_vector(63 downto 0) := X"0000000000000000";
INIT_01 : bit_vector(63 downto 0) := X"0000000000000000"
);
port (
O0 : out std_logic;
O1 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
D0 : in std_logic;
D1 : in std_logic;
WCLK : in std_logic;
WE : in std_logic
);
end component;
attribute syn_black_box of RAM64X2S : component is true;
component RAMB4_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (11 downto 0);
DI : in std_logic_vector (0 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1 : component is true;
component RAMB4_S16
port (
DO : out std_logic_vector (15 downto 0);
ADDR : in std_logic_vector (7 downto 0);
DI : in std_logic_vector (15 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S16 : component is true;
component RAMB4_S16_S16
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (7 downto 0);
DIA : in std_logic_vector (15 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S16_S16 : component is true;
component RAMB4_S1_S1
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S1 : component is true;
component RAMB4_S1_S16
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S16 : component is true;
component RAMB4_S1_S2
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S2 : component is true;
component RAMB4_S1_S4
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S4 : component is true;
component RAMB4_S1_S8
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S1_S8 : component is true;
component RAMB4_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (10 downto 0);
DI : in std_logic_vector (1 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2 : component is true;
component RAMB4_S2_S16
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S16 : component is true;
component RAMB4_S2_S2
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S2 : component is true;
component RAMB4_S2_S4
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S4 : component is true;
component RAMB4_S2_S8
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S2_S8 : component is true;
component RAMB4_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (9 downto 0);
DI : in std_logic_vector (3 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4 : component is true;
component RAMB4_S4_S16
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4_S16 : component is true;
component RAMB4_S4_S4
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4_S4 : component is true;
component RAMB4_S4_S8
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S4_S8 : component is true;
component RAMB4_S8
port (
DO : out std_logic_vector (7 downto 0);
ADDR : in std_logic_vector (8 downto 0);
DI : in std_logic_vector (7 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
RST : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S8 : component is true;
component RAMB4_S8_S16
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (15 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (15 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
attribute syn_black_box of RAMB4_S8_S16 : component is true;
component RAMB4_S8_S8
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (7 downto 0);
ENA : in std_logic;
CLKA : in std_logic;
WEA : in std_logic;
RSTA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
DIB : in std_logic_vector (7 downto 0);
ENB : in std_logic;
CLKB : in std_logic;
WEB : in std_logic;
RSTB : in std_logic
);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
DI : in std_logic_vector (0 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1 : component is true;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S18 : component is true;
component RAMB16_S18_S18
port (
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S18_S18 : component is true;
component RAMB16_S18_S36
port (
DOA : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S18_S36 : component is true;
component RAMB16_S1_S1
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (13 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S1 : component is true;
component RAMB16_S1_S18
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S18 : component is true;
component RAMB16_S1_S2
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (12 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S2 : component is true;
component RAMB16_S1_S36
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S36 : component is true;
component RAMB16_S1_S4
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S4 : component is true;
component RAMB16_S1_S9
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S1_S9 : component is true;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
DI : in std_logic_vector (1 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2 : component is true;
component RAMB16_S2_S18
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S18 : component is true;
component RAMB16_S2_S2
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (12 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S2 : component is true;
component RAMB16_S2_S36
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S36 : component is true;
component RAMB16_S2_S4
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S4 : component is true;
component RAMB16_S2_S9
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (1 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S2_S9 : component is true;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S36 : component is true;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S36_S36 : component is true;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
DI : in std_logic_vector (3 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4 : component is true;
component RAMB16_S4_S18
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S18 : component is true;
component RAMB16_S4_S36
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S36 : component is true;
component RAMB16_S4_S4
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (11 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S4 : component is true;
component RAMB16_S4_S9
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (3 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S4_S9 : component is true;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_logic;
CLK : in std_logic;
WE : in std_logic;
SSR : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9 : component is true;
component RAMB16_S9_S18
port (
DOA : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (9 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (15 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9_S18 : component is true;
component RAMB16_S9_S36
port (
DOA : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (8 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (31 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9_S36 : component is true;
component RAMB16_S9_S9
port (
DOA : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
CLKA : in std_logic;
DIA : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
ENA : in std_logic;
SSRA : in std_logic;
WEA : in std_logic;
ADDRB : in std_logic_vector (10 downto 0);
CLKB : in std_logic;
DIB : in std_logic_vector (7 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENB : in std_logic;
SSRB : in std_logic;
WEB : in std_logic
);
end component;
attribute syn_black_box of RAMB16_S9_S9 : component is true;
component ROM16X1
generic(INIT : bit_vector := X"0000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic
);
end component;
attribute syn_black_box of ROM16X1 : component is true;
component ROM32X1
generic(INIT : bit_vector := X"00000000");
port (
O : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
A4 : in std_logic
);
end component;
attribute syn_black_box of ROM32X1 : component is true;
component ROM128X1
generic(INIT : bit_vector := X"00000000000000000000000000000000");
port (A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
O : out std_ulogic
);
end component;
attribute syn_black_box of ROM128X1 : component is true;
component ROM256X1
generic(INIT : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
port (A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
A6 : in std_ulogic;
A7 : in std_ulogic;
O : out std_ulogic
);
end component;
attribute syn_black_box of ROM256X1 : component is true;
component ROM64X1
generic(INIT : bit_vector := X"0000000000000000");
port (A0 : in std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
A3 : in std_ulogic;
A4 : in std_ulogic;
A5 : in std_ulogic;
O : out std_ulogic
);
end component;
attribute syn_black_box of ROM64X1 : component is true;
component SRL16
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16 : component is true;
component SRL16E
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16E : component is true;
component SRL16E_1
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16E_1 : component is true;
component SRL16_1
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRL16_1 : component is true;
component SRLC16
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16 : component is true;
component SRLC16E
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16E : component is true;
component SRLC16E_1
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16E_1 : component is true;
component SRLC16_1
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CLK : in std_logic;
D : in std_logic
);
end component;
attribute syn_black_box of SRLC16_1 : component is true;
component STARTUP_VIRTEX2_CLK
port (
CLK : in std_logic
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_CLK : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_CLK : component is true;
attribute xc_alias of STARTUP_VIRTEX2_CLK : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2_GSR
port (
GSR : in std_logic
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_GSR : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_GSR : component is true;
attribute xc_alias of STARTUP_VIRTEX2_GSR : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2_GTS
port (
GTS : in std_logic
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_GTS : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_GTS : component is true;
attribute xc_alias of STARTUP_VIRTEX2_GTS : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2_ALL
port (
CLK,GSR,GTS : in std_logic := '0'
);
end component;
attribute syn_black_box of STARTUP_VIRTEX2_ALL : component is true;
attribute syn_noprune of STARTUP_VIRTEX2_ALL : component is true;
attribute xc_alias of STARTUP_VIRTEX2_ALL : component is "STARTUP_VIRTEX2";
component STARTUP_VIRTEX2
port (
CLK : in std_logic;
GSR : in std_logic;
GTS : in std_logic
);
end component;
component VCC
port (
P : out std_logic
);
end component;
attribute syn_black_box of VCC : component is true;
attribute syn_noprune of VCC : component is true;
component XORCY
port (
O : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component;
attribute syn_black_box of XORCY : component is true;
component XORCY_D
port (
O : out std_logic;
LO : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component;
attribute syn_black_box of XORCY_D : component is true;
component XORCY_L
port (
LO : out std_logic;
CI : in std_logic;
LI : in std_logic
);
end component;
attribute syn_black_box of XORCY_L : component is true;
component GT_SWIFT
port (
TX_CRC_FORCE_VALUE : in std_logic_vector(7 downto 0);
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXCLKCORCNT : out std_logic_vector(2 downto 0);
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
RXP : in std_logic;
RXN : in std_logic;
GSR : in std_logic;
TXP : out std_logic;
TXN : out std_logic;
CONFIGENABLE : in std_logic;
CONFIGIN : in std_logic;
CONFIGOUT : out std_logic;
CRC_END_OF_PKT : in std_logic_vector(7 downto 0);
CRC_FORMAT : in std_logic_vector(1 downto 0);
CRC_START_OF_PKT : in std_logic_vector(7 downto 0);
CHAN_BOND_LIMIT : in std_logic_vector(4 downto 0);
REFCLK : in std_logic;
REFCLK2 : in std_logic;
REFCLKSEL : in std_logic;
RXUSRCLK : in std_logic;
TXUSRCLK : in std_logic;
RXUSRCLK2 : in std_logic;
TXUSRCLK2 : in std_logic;
RXRESET : in std_logic;
TXRESET : in std_logic;
POWERDOWN : in std_logic;
LOOPBACK : in std_logic_vector(1 downto 0);
TXDATA : in std_logic_vector(31 downto 0);
RX_LOSS_OF_SYNC_FSM : in std_logic;
RX_LOS_INVALID_INCR : in std_logic_vector(2 downto 0);
RX_LOS_THRESHOLD : in std_logic_vector(2 downto 0);
TXCHARDISPMODE : in std_logic_vector(3 downto 0);
TXCHARDISPVAL : in std_logic_vector(3 downto 0);
TXCHARISK : in std_logic_vector(3 downto 0);
TXBYPASS8B10B : in std_logic_vector(3 downto 0);
TXPOLARITY : in std_logic;
TXINHIBIT : in std_logic;
ENCHANSYNC : in std_logic;
RXPOLARITY : in std_logic;
CHBONDI : in std_logic_vector(3 downto 0);
RXRECCLK : out std_logic;
TXBUFERR : out std_logic;
TXFORCECRCERR : in std_logic;
TXRUNDISP : out std_logic_vector(3 downto 0);
TXKERR : out std_logic_vector(3 downto 0);
RXREALIGN : out std_logic;
RXCOMMADET : out std_logic;
RXCHECKINGCRC : out std_logic;
RXCRCERR : out std_logic;
RXDATA : out std_logic_vector(31 downto 0);
RXCHARISCOMMA : out std_logic_vector(3 downto 0);
RXCHARISK : out std_logic_vector(3 downto 0);
RXNOTINTABLE : out std_logic_vector(3 downto 0);
RXDISPERR : out std_logic_vector(3 downto 0);
RXRUNDISP : out std_logic_vector(3 downto 0);
RXBUFSTATUS : out std_logic_vector(1 downto 0);
CHBONDO : out std_logic_vector(3 downto 0);
CHBONDDONE : out std_logic;
TX_PREEMPHASIS : in std_logic_vector(1 downto 0);
TX_DIFF_CTRL : in std_logic_vector(2 downto 0);
RX_TERM_IMP : in std_logic;
SERDES_10B : in std_logic;
ALIGN_COMMA_MSB : in std_logic;
PCOMMA_DETECT : in std_logic;
PCOMMA_ALIGN : in std_logic;
MCOMMA_DETECT : in std_logic;
MCOMMA_ALIGN : in std_logic;
PCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
MCOMMA_10B_VALUE : in std_logic_vector(0 to 9);
COMMA_10B_MASK : in std_logic_vector(0 to 9);
DEC_PCOMMA_DETECT : in std_logic;
DEC_MCOMMA_DETECT : in std_logic;
DEC_VALID_COMMA_ONLY : in std_logic;
RX_DECODE_USE : in std_logic;
RX_BUFFER_USE : in std_logic;
TX_BUFFER_USE : in std_logic;
CLK_CORRECT_USE : in std_logic;
CLK_COR_SEQ_LEN : in std_logic_vector(1 downto 0);
CLK_COR_INSERT_IDLE_FLAG : in std_logic;
CLK_COR_KEEP_IDLE : in std_logic;
CLK_COR_REPEAT_WAIT : in std_logic_vector(4 downto 0);
CLK_COR_SEQ_1_1 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_1_2 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_1_3 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_1_4 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_USE : in std_logic;
CLK_COR_SEQ_2_1 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_2 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_3 : in std_logic_vector(10 downto 0);
CLK_COR_SEQ_2_4 : in std_logic_vector(10 downto 0);
CHAN_BOND_MODE : in std_logic_vector(1 downto 0);
CHAN_BOND_SEQ_LEN : in std_logic_vector(1 downto 0);
CHAN_BOND_SEQ_1_1 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_1_2 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_1_3 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_1_4 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_USE : in std_logic;
CHAN_BOND_SEQ_2_1 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_2 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_3 : in std_logic_vector(10 downto 0);
CHAN_BOND_SEQ_2_4 : in std_logic_vector(10 downto 0);
CHAN_BOND_WAIT : in std_logic_vector(3 downto 0);
CHAN_BOND_OFFSET : in std_logic_vector(3 downto 0);
TX_CRC_USE : in std_logic;
RX_CRC_USE : in std_logic;
CHAN_BOND_ONE_SHOT : in std_logic;
RX_DATA_WIDTH : in std_logic_vector(1 downto 0);
TX_DATA_WIDTH : in std_logic_vector(1 downto 0)
);
end component;
attribute syn_black_box of GT_SWIFT : component is true;
component GT
port (
CHBONDDONE : out std_ulogic;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic;
TXP : out std_ulogic ;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end Component;
attribute syn_black_box of GT : component is true;
component GT_AURORA_1
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_AURORA_1 : component is true;
component GT_AURORA_2
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_AURORA_2 : component is true;
component GT_AURORA_4
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_AURORA_4 : component is true;
component GT_CUSTOM
port (
CHBONDDONE : out std_ulogic;
CHBONDO : out std_logic_vector(3 DOWNTO 0);
CONFIGOUT : out std_ulogic;
RXBUFSTATUS : out std_logic_vector(1 DOWNTO 0);
RXCHARISCOMMA : out std_logic_vector(3 DOWNTO 0);
RXCHARISK : out std_logic_vector(3 DOWNTO 0);
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 DOWNTO 0);
RXCOMMADET : out std_ulogic;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector(31 DOWNTO 0);
RXDISPERR : out std_logic_vector(3 DOWNTO 0);
RXLOSSOFSYNC : out std_logic_vector(1 DOWNTO 0);
RXNOTINTABLE : out std_logic_vector(3 DOWNTO 0);
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic;
RXRUNDISP : out std_logic_vector(3 DOWNTO 0);
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector(3 DOWNTO 0);
TXN : out std_ulogic;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector(3 DOWNTO 0);
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector(3 DOWNTO 0);
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic;
ENCHANSYNC : in std_ulogic;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector(1 DOWNTO 0);
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic;
RXP : in std_ulogic;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector(3 DOWNTO 0);
TXCHARDISPMODE : in std_logic_vector(3 DOWNTO 0);
TXCHARDISPVAL : in std_logic_vector(3 DOWNTO 0);
TXCHARISK : in std_logic_vector(3 DOWNTO 0);
TXDATA : in std_logic_vector(31 DOWNTO 0);
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_logic
) ;
end component;
attribute syn_black_box of GT_CUSTOM : component is true;
component GT_ETHERNET_4
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_ETHERNET_4 : component is true;
component GT_ETHERNET_1
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_ETHERNET_1 : component is true;
component GT_ETHERNET_2
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_ETHERNET_2 : component is true;
component GT_FIBRE_CHAN_1
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXFORCECRCERR : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_FIBRE_CHAN_1 : component is true;
component GT_FIBRE_CHAN_2
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_FIBRE_CHAN_2 : component is true;
component GT_FIBRE_CHAN_4
port (
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_FIBRE_CHAN_4 : component is true;
component GT_INFINIBAND_1
port (
CHBONDO : out std_logic_vector ( 3 downto 0 );
CHBONDDONE : out std_ulogic ;
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_INFINIBAND_1 : component is true;
component GT_INFINIBAND_2
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic ;
REFCLKSEL : in std_ulogic ;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2 : in std_ulogic
);
end component;
attribute syn_black_box of GT_INFINIBAND_2 : component is true;
component GT_INFINIBAND_4
port (
CHBONDO : out std_logic_vector ( 3 downto 0 );
CHBONDDONE : out std_ulogic ;
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_INFINIBAND_4 : component is true;
component GT_XAUI_1
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 0 downto 0);
RXCHARISK : out std_logic_vector ( 0 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 7 downto 0);
RXDISPERR : out std_logic_vector ( 0 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 0 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 0 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 0 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 0 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 0 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 0 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 0 downto 0 );
TXCHARISK : in std_logic_vector ( 0 downto 0 );
TXDATA : in std_logic_vector ( 7 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_XAUI_1 : component is true;
component GT_XAUI_2
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 1 downto 0);
RXCHARISK : out std_logic_vector ( 1 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 15 downto 0);
RXDISPERR : out std_logic_vector ( 1 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 1 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 1 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 1 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 1 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 1 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 1 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 1 downto 0 );
TXCHARISK : in std_logic_vector ( 1 downto 0 );
TXDATA : in std_logic_vector ( 15 downto 0 );
TXFORCECRCERR : in std_ulogic;
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_XAUI_2 : component is true;
component GT_XAUI_4
port (
CHBONDDONE : out std_ulogic ;
CHBONDO : out std_logic_vector ( 3 downto 0 );
CONFIGOUT : out std_ulogic ;
RXBUFSTATUS: out std_logic_vector (1 downto 0);
RXCHARISCOMMA : out std_logic_vector ( 3 downto 0);
RXCHARISK : out std_logic_vector ( 3 downto 0 );
RXCHECKINGCRC : out std_ulogic;
RXCLKCORCNT : out std_logic_vector(2 downto 0);
RXCOMMADET : out std_ulogic ;
RXCRCERR : out std_ulogic;
RXDATA : out std_logic_vector ( 31 downto 0);
RXDISPERR : out std_logic_vector ( 3 downto 0) ;
RXLOSSOFSYNC : out std_logic_vector(1 downto 0);
RXNOTINTABLE : out std_logic_vector ( 3 downto 0 );
RXREALIGN : out std_ulogic;
RXRECCLK : out std_ulogic ;
RXRUNDISP : out std_logic_vector ( 3 downto 0 );
TXBUFERR : out std_ulogic;
TXKERR : out std_logic_vector ( 3 downto 0 );
TXN : out std_ulogic ;
TXP : out std_ulogic;
TXRUNDISP : out std_logic_vector ( 3 downto 0 );
BREFCLK : in std_logic;
BREFCLK2 : in std_logic;
CHBONDI : in std_logic_vector ( 3 downto 0 );
CONFIGENABLE : in std_ulogic;
CONFIGIN : in std_ulogic ;
ENCHANSYNC : in std_ulogic ;
ENMCOMMAALIGN : in std_ulogic ;
ENPCOMMAALIGN : in std_ulogic ;
LOOPBACK : in std_logic_vector ( 1 downto 0 );
POWERDOWN : in std_ulogic;
REFCLK : in std_ulogic ;
REFCLK2 : in std_ulogic;
REFCLKSEL : in std_ulogic;
RXN : in std_ulogic ;
RXP : in std_ulogic ;
RXPOLARITY : in std_ulogic;
RXRESET : in std_ulogic;
RXUSRCLK : in std_ulogic;
RXUSRCLK2 : in std_ulogic;
TXFORCECRCERR : in std_ulogic;
TXBYPASS8B10B : in std_logic_vector ( 3 downto 0 );
TXCHARDISPMODE : in std_logic_vector ( 3 downto 0 );
TXCHARDISPVAL : in std_logic_vector ( 3 downto 0 );
TXCHARISK : in std_logic_vector ( 3 downto 0 );
TXDATA : in std_logic_vector ( 31 downto 0 );
TXINHIBIT : in std_ulogic ;
TXPOLARITY : in std_ulogic;
TXRESET : in std_ulogic;
TXUSRCLK : in std_ulogic;
TXUSRCLK2: in std_ulogic
);
end component;
attribute syn_black_box of GT_XAUI_4 : component is true;
component JTAGPPC
port (
TCK : out std_logic;
TDIPPC : out std_logic;
TMS : out std_logic;
TDOPPC : in std_logic;
TDOTSPPC : in std_logic
);
end component;
attribute syn_black_box of JTAGPPC : component is true;
component PPC405
port (
C405CPMCORESLEEPREQ : out std_ulogic;
C405CPMMSRCE : out std_ulogic;
C405CPMMSREE : out std_ulogic;
C405CPMTIMERIRQ : out std_ulogic;
C405CPMTIMERRESETREQ : out std_ulogic;
C405DBGMSRWE : out std_ulogic;
C405DBGSTOPACK : out std_ulogic;
C405DBGWBCOMPLETE : out std_ulogic;
C405DBGWBFULL : out std_ulogic;
C405DBGWBIAR : out std_logic_vector(0 TO 29);
C405DCRABUS : out std_logic_vector(0 TO 9);
C405DCRDBUSOUT : out std_logic_vector(0 TO 31);
C405DCRREAD : out std_ulogic;
C405DCRWRITE : out std_ulogic;
C405JTGCAPTUREDR : out std_ulogic;
C405JTGEXTEST : out std_ulogic;
C405JTGPGMOUT : out std_ulogic;
C405JTGSHIFTDR : out std_ulogic;
C405JTGTDO : out std_ulogic;
C405JTGTDOEN : out std_ulogic;
C405JTGUPDATEDR : out std_ulogic;
C405PLBDCUABORT : out std_ulogic;
C405PLBDCUABUS : out std_logic_vector(0 TO 31);
C405PLBDCUBE : out std_logic_vector(0 TO 7);
C405PLBDCUCACHEABLE : out std_ulogic;
C405PLBDCUGUARDED : out std_ulogic;
C405PLBDCUPRIORITY : out std_logic_vector(0 TO 1);
C405PLBDCUREQUEST : out std_ulogic;
C405PLBDCURNW : out std_ulogic;
C405PLBDCUSIZE2 : out std_ulogic;
C405PLBDCUU0ATTR : out std_ulogic;
C405PLBDCUWRDBUS : out std_logic_vector(0 TO 63);
C405PLBDCUWRITETHRU : out std_ulogic;
C405PLBICUABORT : out std_ulogic;
C405PLBICUABUS : out std_logic_vector(0 TO 29);
C405PLBICUCACHEABLE : out std_ulogic;
C405PLBICUPRIORITY : out std_logic_vector(0 TO 1);
C405PLBICUREQUEST : out std_ulogic;
C405PLBICUSIZE : out std_logic_vector(2 TO 3);
C405PLBICUU0ATTR : out std_ulogic;
C405RSTCHIPRESETREQ : out std_ulogic;
C405RSTCORERESETREQ : out std_ulogic;
C405RSTSYSRESETREQ : out std_ulogic;
C405TRCCYCLE : out std_ulogic;
C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 TO 1);
C405TRCODDEXECUTIONSTATUS : out std_logic_vector(0 TO 1);
C405TRCTRACESTATUS : out std_logic_vector(0 TO 3);
C405TRCTRIGGEREVENTOUT : out std_ulogic;
C405TRCTRIGGEREVENTTYPE : out std_logic_vector(0 TO 10);
C405XXXMACHINECHECK : out std_ulogic;
DSOCMBRAMABUS : out std_logic_vector(8 TO 29);
DSOCMBRAMBYTEWRITE : out std_logic_vector(0 TO 3);
DSOCMBRAMEN : out std_ulogic;
DSOCMBRAMWRDBUS : out std_logic_vector(0 TO 31);
DSOCMBUSY : out std_ulogic;
ISOCMBRAMEN : out std_ulogic;
ISOCMBRAMEVENWRITEEN : out std_ulogic;
ISOCMBRAMODDWRITEEN : out std_ulogic;
ISOCMBRAMRDABUS : out std_logic_vector(8 TO 28);
ISOCMBRAMWRABUS : out std_logic_vector(8 TO 28);
ISOCMBRAMWRDBUS : out std_logic_vector(0 TO 31);
BRAMDSOCMCLK : in std_ulogic;
BRAMDSOCMRDDBUS : in std_logic_vector(0 TO 31);
BRAMISOCMCLK : in std_ulogic;
BRAMISOCMRDDBUS : in std_logic_vector(0 TO 63);
CPMC405CLOCK : in std_ulogic;
CPMC405CORECLKINACTIVE : in std_ulogic;
CPMC405CPUCLKEN : in std_ulogic;
CPMC405JTAGCLKEN : in std_ulogic;
CPMC405TIMERCLKEN : in std_ulogic;
CPMC405TIMERTICK : in std_ulogic;
DBGC405DEBUGHALT : in std_ulogic;
DBGC405EXTBUSHOLDACK : in std_ulogic;
DBGC405UNCONDDEBUGEVENT : in std_ulogic;
DCRC405ACK : in std_ulogic;
DCRC405DBUSIN : in std_logic_vector(0 TO 31);
DSARCVALUE : in std_logic_vector(0 TO 7);
DSCNTLVALUE : in std_logic_vector(0 TO 7);
EICC405CRITINPUTIRQ : in std_ulogic;
EICC405EXTINPUTIRQ : in std_ulogic;
ISARCVALUE : in std_logic_vector(0 TO 7);
ISCNTLVALUE : in std_logic_vector(0 TO 7);
JTGC405BNDSCANTDO : in std_ulogic;
JTGC405TCK : in std_ulogic;
JTGC405TDI : in std_ulogic;
JTGC405TMS : in std_ulogic;
JTGC405TRSTNEG : in std_ulogic;
MCBCPUCLKEN : in std_ulogic;
MCBJTAGEN : in std_ulogic;
MCBTIMEREN : in std_ulogic;
MCPPCRST : in std_ulogic;
PLBC405DCUADDRACK : in std_ulogic;
PLBC405DCUBUSY : in std_ulogic;
PLBC405DCUERR : in std_ulogic;
PLBC405DCURDDACK : in std_ulogic;
PLBC405DCURDDBUS : in std_logic_vector(0 TO 63);
PLBC405DCURDWDADDR : in std_logic_vector(1 TO 3);
PLBC405DCUSSIZE1 : in std_ulogic;
PLBC405DCUWRDACK : in std_ulogic;
PLBC405ICUADDRACK : in std_ulogic;
PLBC405ICUBUSY : in std_ulogic;
PLBC405ICUERR : in std_ulogic;
PLBC405ICURDDACK : in std_ulogic;
PLBC405ICURDDBUS : in std_logic_vector(0 TO 63);
PLBC405ICURDWDADDR : in std_logic_vector(1 TO 3);
PLBC405ICUSSIZE1 : in std_ulogic;
PLBCLK : in std_ulogic;
RSTC405RESETCHIP : in std_ulogic;
RSTC405RESETCORE : in std_ulogic;
RSTC405RESETSYS : in std_ulogic;
TIEC405DETERMINISTICMULT : in std_ulogic;
TIEC405DISOPERANDFWD : in std_ulogic;
TIEC405MMUEN : in std_ulogic;
TIEDSOCMDCRADDR : in std_logic_vector(0 TO 7);
TIEISOCMDCRADDR : in std_logic_vector(0 TO 7);
TRCC405TRACEDISABLE : in std_ulogic;
TRCC405TRIGGEREVENTIN : in std_ulogic
);
end component ;
attribute syn_black_box of PPC405 : component is true;
component BUFGCE
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC);
end component;
attribute syn_black_box of BUFGCE : component is true;
component BUFGCE_1
port(
O : out STD_ULOGIC;
CE: in STD_ULOGIC;
I : in STD_ULOGIC);
end component;
attribute syn_black_box of BUFGCE_1 : component is true;
component IFDDRCPE
port(
Q0 : out STD_ULOGIC;
Q1 : out STD_ULOGIC;
D : in STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLR : in STD_ULOGIC);
end component;
attribute syn_black_box of IFDDRCPE : component is true;
component IFDDRRSE
port(
Q0 : out STD_ULOGIC;
Q1 : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
D : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
attribute syn_black_box of IFDDRRSE : component is true;
component OFDDRCPE
port(
Q : out STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
PRE : in STD_ULOGIC;
CLR : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRCPE : component is true;
component OFDDRRSE
port(
Q : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRRSE : component is true;
component OFDDRTCPE
port(
O : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLR : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
PRE : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRTCPE : component is true;
component OFDDRTRSE
port(
O : out STD_ULOGIC;
C0 : in STD_ULOGIC;
C1 : in STD_ULOGIC;
CE : in STD_ULOGIC;
D0 : in STD_ULOGIC;
D1 : in STD_ULOGIC;
R : in STD_ULOGIC;
S : in STD_ULOGIC;
T : in STD_ULOGIC);
end component;
attribute syn_black_box of OFDDRTRSE : component is true;
component STARTBUF_VIRTEX2
port( GSRIN : in std_ulogic := 'X';
GTSIN : in std_ulogic := 'X';
CLKIN : in std_ulogic := 'X';
GTSOUT : out std_ulogic
);
end component;
attribute syn_black_box of STARTBUF_VIRTEX2 : component is true;
end package components;
library IEEE;
use IEEE.std_logic_1164.all;
library virtex2;
use virtex2.components.all;
entity STARTUP_VIRTEX2 is
port(CLK, GSR, GTS: in std_logic := '0');
end STARTUP_VIRTEX2;
architecture struct of STARTUP_VIRTEX2 is
attribute syn_noprune of struct : architecture is true;
begin
gsr0 : STARTUP_VIRTEX2_GSR port map ( GSR => GSR );
gts0 : STARTUP_VIRTEX2_GTS port map ( GTS => GTS );
clk0 : STARTUP_VIRTEX2_CLK port map ( CLK => CLK);
end struct;
|
gpl-3.0
|
c1bd92ea931d99a04fcdc2824b0c7dee
| 0.648327 | 3.162673 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/Mem/sim/Mem.vhd
| 1 | 12,364 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY Mem IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Mem;
ARCHITECTURE Mem_arch OF Mem IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Mem_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(16 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "Mem.mif",
C_INIT_FILE => "Mem.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 131072,
C_READ_DEPTH_A => 131072,
C_ADDRA_WIDTH => 17,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 131072,
C_READ_DEPTH_B => 131072,
C_ADDRB_WIDTH => 17,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "32",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.5485 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 17)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END Mem_arch;
|
mit
|
871ca7f2b006cfdf2f9fb130536da1bc
| 0.606357 | 3.214769 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/srl_fifo.vhd
| 4 | 7,616 |
-------------------------------------------------------------------------------
-- $Id: srl_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : integer := 8;
C_DEPTH : integer := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
Clear_FIFO : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
FIFO_Level : out std_logic_vector(0 to 3);
Half_Full : out std_logic;
Half_Empty : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.all;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
-- pragma translate_off
Xon : boolean;
-- pragma translate_on
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
signal Addr : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
signal reset_int : std_logic;
begin -- architecture IMP
FIFO_Level <= Addr;
reset_int <= Clear_FIFO or Reset;
buffer_Full <= '1' when (Addr = "1111") else '0';
FIFO_Full <= buffer_Full;
Half_Full <= Addr(3);
Half_Empty <= not Addr(3);
buffer_Empty <= '1' when (Addr = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (reset_int = '1') then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(4) is not used anywhere
Used_MuxCY : if I < 3 generate
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => reset_int); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
end architecture IMP;
|
gpl-3.0
|
afeb63a11e16866f88f32836612273f5
| 0.421218 | 3.783408 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_sa1_test3.vhd
| 4 | 3,028 |
library ieee;
use ieee.std_logic_1164.all;
package work6 is
-- D-type flip flop
component fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
component TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end component;
end package work6;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter (of 25 bits) is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a count of 20000000 pulses has been accumulated
entity TimeBase is
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (24 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
constant DIVIDER_VALUE : std_logic_vector := x"7cf"; -- 20000000 count value, 1 second
signal RunningCounter : std_logic_vector(24 downto 0); -- this is the 25 bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= '0' & x"000000";
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = DIVIDER_VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.work6.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;-- a D-type flip-flop with synchronous reset
library ieee;
use ieee.std_logic_1164.all;
entity fdc is
port (clk: in std_logic;
reset: in std_logic;
d: in std_logic;
q: out std_logic
);
end fdc;
architecture fdc_rtl of fdc is
begin
i_finish: process (clk)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end fdc_rtl;
|
gpl-2.0
|
251fb0571eedbf901153f2254c6d1cca
| 0.641017 | 3.48046 | false | false | false | false |
whitef0x0/EECE353-Lab5
|
datapath_line.vhd
| 1 | 3,099 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY datapath_line IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
RESETX, RESETY, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0); -- x0
y : OUT STD_LOGIC_VECTOR(6 downto 0);
x1in : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
y1in : IN STD_LOGIC_VECTOR(6 downto 0);
x0in : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
y0in : IN STD_LOGIC_VECTOR(6 downto 0);
xdone, ydone, ldone : OUT STD_LOGIC
);
END datapath_line;
ARCHITECTURE mixed OF datapath_line IS
BEGIN
PROCESS(clock, resetb)
VARIABLE x_tmp : unsigned(7 downto 0) := "00000000";
VARIABLE y_tmp : unsigned(6 downto 0) := "0000000";
VARIABLE dx : signed(8 downto 0);
VARIABLE dy : signed(7 downto 0);
VARIABLE x0 : unsigned(7 downto 0) := "01010000"; -- 80
VARIABLE y0 : unsigned(6 downto 0) := "0111100"; -- 60
VARIABLE x1 : unsigned(7 downto 0) := "01010000";
VARIABLE y1 : unsigned(6 downto 0) := "0111100";
VARIABLE sx : signed(1 downto 0);
VARIABLE sy : signed(1 downto 0);
VARIABLE error : signed(8 downto 0);
VARIABLE e2 : signed(9 downto 0);
BEGIN
IF (resetb = '0') THEN
y_tmp := "0000000";
x_tmp := "00000000";
x0 := "01010000"; -- 80
y0 := "0111100"; -- 60
x1 := "01010000"; -- 80
y1 := "0111100"; -- 60
ELSIF rising_edge(clock) THEN
--initialize line
IF (initl = '1') THEN
x0 := unsigned(x0in); -- start point
y0 := unsigned(x0in);
x1 := unsigned(x1in); -- end point
y1 := unsigned(yin);
dx := to_signed(abs(to_integer(x1) - to_integer(x0)), 9);
dy := to_signed(abs(to_integer(y1) - to_integer(y0)), 8);
IF (x0 < x1) THEN
sx := to_signed(1, 2);
ELSE
sx := to_signed(-1, 2);
END IF;
IF (y0 < y1) THEN
sy := to_signed(1, 2);
ELSE
sy := to_signed(-1, 2);
END IF;
error := to_signed(to_integer(dx) - to_integer(dy), 9);
ldone <= '0';
--draw line loop
ELSIF (drawl = '1') THEN
x <= STD_LOGIC_VECTOR(x0);
y <= STD_LOGIC_VECTOR(y0);
-- Exit loop if we are at destination point
IF (x0 = x1) THEN
IF(y0 = y1) THEN
ldone <= '1';
END IF;
ELSE
e2 := signed(2*error)(9 downto 0);
IF (e2 > -dy) THEN
error := error - dy;
x0 := unsigned(signed(x0) + sx);
END IF;
IF (e2 < dx) THEN
error := error + dx;
y0 := unsigned(signed(y0) + sy);
END IF;
END IF;
--clear screen
ELSE
IF (RESETY = '1') THEN
y_tmp := "0000000";
ELSIF (INCR_Y = '1') THEN
y_tmp := y_tmp + 1;
IF (y_tmp = 119) THEN
YDONE <= '1';
ELSE
YDONE <= '0';
END IF;
END IF;
Y <= std_logic_vector(y_tmp);
IF (RESETX = '1') THEN
x_tmp := "00000000";
ELSIF (INCR_X = '1') THEN
x_tmp := x_tmp + 1;
IF (x_tmp = 159) THEN
XDONE <= '1';
ELSE
XDONE <= '0';
END IF;
END IF;
X <= std_logic_vector(x_tmp);
END IF;
END IF;
END PROCESS;
END mixed;
|
mit
|
8f9858a5ee396e1c8cd4c96eef6718f1
| 0.551791 | 2.725594 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/client/fifo/tx_client_fifo_8.vhd
| 1 | 48,464 |
-------------------------------------------------------------------------------
-- Title : 8-bit Client-to-LocalLink Transmitter FIFO
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : tx_client_fifo_8.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Description: This is a transmit-side LocalLink FIFO implementation for
-- the example design of the Virtex-6 Embedded Tri-Mode Ethernet
-- MAC Wrapper core.
--
-- The transmit FIFO is created from a Block RAM of size 4096
-- words of 8-bits per word.
--
-- Valid frame data received from LocalLink interface is written
-- into the Block RAM on the write clock. The FIFO will store
-- frames upto 4kbytes in length. If larger frames are written
-- to the FIFO the LocalLink interface will accept the rest of the
-- frame, but that frame will be dropped by the FIFO and
-- the overflow signal will be asserted.
--
-- The FIFO is designed to work with a minimum frame length of 14
-- bytes.
--
-- When there is at least one complete frame in the FIFO,
-- the MAC transmitter client interface will be driven to
-- request frame transmission by placing the first byte of
-- the frame onto tx_data[15:0] and by asserting
-- tx_data_valid. The MAC will later respond by asserting
-- tx_ack. At this point the remaining frame data is read
-- out of the FIFO in a continuous burst. Data is read out
-- of the FIFO on the rd_clk.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The write clock (LocalLink clock)
-- can be an equal or faster frequency than the read clock
-- (client clock). The minimum write clock frequency is the read
-- clock frequency divided by 2.5.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity tx_client_fifo_8 is
generic (
-- If FULL_DUPLEX_ONLY is true then all the half duplex logic in the FIFO is removed.
-- The default for the fifo is to include the half duplex functionality
FULL_DUPLEX_ONLY : boolean := false);
port (
-- MAC Interface
rd_clk : in std_logic;
rd_sreset : in std_logic;
rd_enable : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
tx_data_valid : out std_logic;
tx_ack : in std_logic;
tx_collision : in std_logic;
tx_retransmit : in std_logic;
overflow : out std_logic;
-- LocalLink Interface
wr_clk : in std_logic;
wr_sreset : in std_logic; -- synchronous reset (write_clock)
wr_data : in std_logic_vector(7 downto 0);
wr_sof_n : in std_logic;
wr_eof_n : in std_logic;
wr_src_rdy_n : in std_logic;
wr_dst_rdy_n : out std_logic;
wr_fifo_status : out std_logic_vector(3 downto 0)
);
end tx_client_fifo_8;
architecture RTL of tx_client_fifo_8 is
signal GND : std_logic;
signal VCC : std_logic;
signal GND_BUS : std_logic_vector(31 downto 0);
type rd_state_typ is (IDLE_s, QUEUE1_s, QUEUE2_s, QUEUE3_s, QUEUE_ACK_s, WAIT_ACK_s, FRAME_s, DROP_s, RETRANSMIT_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
type wr_state_typ is (WAIT_s, DATA_s, EOF_s, OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array(0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array(0 to 1) of std_logic;
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_sof_pipe : cntl_pipe;
signal wr_eof_pipe : cntl_pipe;
signal wr_accept_pipe : cntl_pipe;
signal wr_accept_bram : std_logic;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_fifo_full : std_logic;
signal wr_en : std_logic;
signal wr_ovflow_dst_rdy : std_logic;
signal wr_dst_rdy_int_n : std_logic;
signal frame_in_fifo : std_logic;
signal frame_in_fifo_sync : std_logic;
signal rd_eof_bram : std_logic;
signal rd_eof : std_logic;
signal rd_eof_reg : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0);
signal rd_en : std_logic;
signal rd_en_bram : std_logic;
signal dob_bram : std_logic_vector(31 downto 0);
signal dopb_bram : std_logic_vector(3 downto 0);
signal rd_tran_frame_tog : std_logic;
signal wr_tran_frame_tog : std_logic;
signal wr_tran_frame_sync : std_logic;
signal wr_tran_frame_delay : std_logic;
signal rd_retran_frame_tog : std_logic;
signal wr_retran_frame_tog : std_logic;
signal wr_retran_frame_sync : std_logic;
signal wr_retran_frame_delay : std_logic;
signal wr_store_frame : std_logic;
signal wr_eof_state : std_logic;
signal wr_eof_state_reg : std_logic;
signal wr_transmit_frame : std_logic;
signal wr_retransmit_frame : std_logic;
signal wr_frames : std_logic_vector(8 downto 0);
signal wr_frame_in_fifo : std_logic;
signal rd_16_count : unsigned(3 downto 0);
signal rd_txfer_en : std_logic;
signal rd_addr_txfer : unsigned(11 downto 0);
signal rd_txfer_tog : std_logic;
signal wr_txfer_tog : std_logic;
signal wr_txfer_tog_sync : std_logic;
signal wr_txfer_tog_delay : std_logic;
signal wr_txfer_en : std_logic;
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal rd_drop_frame : std_logic;
signal rd_retransmit : std_logic;
signal rd_start_addr : unsigned(11 downto 0);
signal rd_start_addr_load : std_logic;
signal rd_start_addr_reload : std_logic;
signal rd_dec_addr : unsigned(11 downto 0);
signal rd_transmit_frame : std_logic;
signal rd_retransmit_frame : std_logic;
signal rd_col_window_expire : std_logic;
signal rd_col_window_pipe : cntl_pipe;
signal wr_col_window_pipe : cntl_pipe;
signal wr_fifo_overflow : std_logic;
signal rd_slot_timer : unsigned(9 downto 0);
signal wr_col_window_expire : std_logic;
signal rd_idle_state : std_logic;
signal rd_enable_delay : std_logic;
signal rd_enable_delay2 : std_logic;
-- Small delay for simulation purposes.
constant dly : time := 1 ps;
-----------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
-----------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_tran_frame_tog : signal is "TRUE";
attribute ASYNC_REG of wr_retran_frame_tog : signal is "TRUE";
attribute ASYNC_REG of frame_in_fifo_sync : signal is "TRUE";
attribute ASYNC_REG of wr_rd_addr : signal is "TRUE";
attribute ASYNC_REG of wr_txfer_tog : signal is "TRUE";
attribute ASYNC_REG of wr_col_window_pipe : signal is "TRUE";
-------------------------------------------------------------------------------
-- Begin FIFO architecture
-------------------------------------------------------------------------------
begin
GND <= '0';
VCC <= '1';
GND_BUS <= (others => '0');
rd_enable_del_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_enable_delay <= '0' after dly;
rd_enable_delay2 <= '0' after dly;
else
rd_enable_delay <= rd_enable after dly;
rd_enable_delay2 <= rd_enable_delay after dly;
end if;
end if;
end process rd_enable_del_p;
-----------------------------------------------------------------------------
-- Write state machine and control
-----------------------------------------------------------------------------
-- Write state machine
-- states are WAIT, DATA, EOF, OVFLOW
-- clock through next state of sm
clock_wrs_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_state <= WAIT_s after dly;
else
wr_state <= wr_nxt_state after dly;
end if;
end if;
end process clock_wrs_p;
-- decode next state, combinitorial
-- should never be able to overflow whilst not in the data state.
next_wrs_p : process(wr_state, wr_sof_pipe(1), wr_eof_pipe, wr_eof_bram(0), wr_fifo_overflow)
begin
case wr_state is
when WAIT_s =>
-- when the sof is detected move to frame state
if wr_sof_pipe(1) = '1' then
wr_nxt_state <= DATA_s;
else
wr_nxt_state <= WAIT_s;
end if;
when DATA_s =>
-- wait for the end of frame to be detected
if wr_fifo_overflow = '1' and wr_eof_pipe = "00" then
wr_nxt_state <= OVFLOW_s;
elsif wr_eof_pipe(1) = '1' then
wr_nxt_state <= EOF_s;
else
wr_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- if the start of frame is already in the pipe, a back to back frame
-- transmission has occured. move straight back to frame state
if wr_sof_pipe(1) = '1' then
wr_nxt_state <= DATA_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= EOF_s;
end if;
when OVFLOW_s =>
-- wait until the end of frame is reached before clearing the overflow
if wr_eof_bram(0) = '1' then
wr_nxt_state <= WAIT_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= WAIT_s;
end case;
end process;
-- decode output signals.
wr_en <= '0' when wr_state = OVFLOW_s else wr_accept_bram;
wr_addr_inc <= wr_en;
wr_addr_reload <= '1' when wr_state = OVFLOW_s else '0';
wr_start_addr_load <= '1' when wr_state = EOF_s and wr_nxt_state = WAIT_s else
'1' when wr_state = EOF_s and wr_nxt_state = DATA_s else '0';
-- pause the LocalLink flow when the fifo is full.
wr_dst_rdy_int_n <= wr_ovflow_dst_rdy when wr_state = OVFLOW_s else wr_fifo_full;
wr_dst_rdy_n <= wr_dst_rdy_int_n;
overflow <= '1' when wr_state = OVFLOW_s else '0';
-- when in overflow and have captured ovflow eof send dst rdy high again.
p_ovflow_dst_rdy : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_ovflow_dst_rdy <= '0' after dly;
else
if wr_fifo_overflow = '1' and wr_state = DATA_s then
wr_ovflow_dst_rdy <= '0' after dly;
elsif wr_eof_n = '0' and wr_src_rdy_n = '0' then
wr_ovflow_dst_rdy <= '1' after dly;
end if;
end if;
end if;
end process;
-- eof signals for use in overflow logic
wr_eof_state <= '1' when wr_state = EOF_s else '0';
p_reg_eof_st : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_eof_state_reg <= '0' after dly;
else
wr_eof_state_reg <= wr_eof_state after dly;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Read state machine and control
-----------------------------------------------------------------------------
-- clock through the read state machine
clock_rds_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_state <= IDLE_s after dly;
elsif rd_enable = '1' then
rd_state <= rd_nxt_state after dly;
end if;
end if;
end process clock_rds_p;
-- Full duplex only state machine
gen_fd_sm : if (FULL_DUPLEX_ONLY = TRUE) generate
-- decode the next state
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, tx_ack)
begin
case rd_state is
when IDLE_s =>
-- if there is a frame in the fifo start to queue the new frame
-- to the output
if frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
when QUEUE1_s =>
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_ACK_s;
when QUEUE_ACK_s =>
rd_nxt_state <= WAIT_ACK_s;
when WAIT_ACK_s =>
-- the output pipe line is fully loaded, so wait for ack from mac
-- before moving on
if tx_ack = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_ACK_s;
end if;
when FRAME_s =>
-- when the end of frame has been reached wait another frame in
-- the fifo
if rd_eof = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FRAME_s;
end if;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_fd_sm;
-- Full and Half Duplex State Machine
gen_hd_sm : if (FULL_DUPLEX_ONLY = FALSE) generate
-- decode the next state
-- should never receive a rd_drop_frame pulse outside of the Frame state
next_rds_p : process(rd_state, frame_in_fifo, rd_eof_reg, tx_ack, rd_drop_frame, rd_retransmit)
begin
case rd_state is
when IDLE_s =>
-- if a retransmit request is detected go to retransmit state
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
-- if there is a frame in the fifo then queue the new frame to
-- the output
elsif frame_in_fifo = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= IDLE_s;
end if;
when QUEUE1_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE2_s;
end if;
when QUEUE2_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE3_s;
end if;
when QUEUE3_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= QUEUE_ACK_s;
end if;
when QUEUE_ACK_s =>
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
else
rd_nxt_state <= WAIT_ACK_s;
end if;
when WAIT_ACK_s =>
-- the output pipeline is now fully loaded so wait for ack from
-- mac before moving on.
if rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
elsif tx_ack = '1' then
rd_nxt_state <= FRAME_s;
else
rd_nxt_state <= WAIT_ACK_s;
end if;
when FRAME_s =>
-- if a collision only request, then must drop the rest of the
-- current frame, move to drop state
if rd_drop_frame = '1' then
rd_nxt_state <= DROP_s;
elsif rd_retransmit = '1' then
rd_nxt_state <= RETRANSMIT_s;
-- continue transmitting frame until the end of the frame is
-- detected, then wait for a new frame to be sent.
elsif rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= FRAME_s;
end if;
when DROP_s =>
-- wait until rest of frame has been cleared.
if rd_eof_reg = '1' then
rd_nxt_state <= IDLE_s;
else
rd_nxt_state <= DROP_s;
end if;
when RETRANSMIT_s =>
-- reload the data pipe from the start of the frame
rd_nxt_state <= QUEUE1_s;
when others =>
rd_nxt_state <= IDLE_s;
end case;
end process next_rds_p;
end generate gen_hd_sm;
-- decode output signals
-- decode output data
rd_data_decode_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_nxt_state = FRAME_s then
tx_data <= rd_data_pipe after dly;
else
case rd_state is
when QUEUE_ACK_s =>
tx_data <= rd_data_pipe after dly;
when WAIT_ACK_s => null;
when FRAME_s =>
tx_data <= rd_data_pipe after dly;
when others =>
tx_data <= (others => '0') after dly;
end case;
end if;
end if;
end if;
end process rd_data_decode_p;
-- decode output data valid
rd_dv_decode_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_nxt_state = FRAME_s then
tx_data_valid <= not(tx_collision and not(tx_retransmit)) after dly;
else
case rd_state is
when QUEUE_ACK_s =>
tx_data_valid <= '1' after dly;
when WAIT_ACK_s =>
tx_data_valid <= '1' after dly;
when FRAME_s =>
if (rd_nxt_state /= DROP_s) then
tx_data_valid <= '1' after dly;
else
tx_data_valid <= '0' after dly;
end if;
when others =>
tx_data_valid <= '0' after dly;
end case;
end if;
end if;
end if;
end process rd_dv_decode_p;
-- decode full duplex only control signals
gen_fd_decode : if (FULL_DUPLEX_ONLY = TRUE) generate
rd_en <= '0' when rd_state = IDLE_s else
'1' when rd_nxt_state = FRAME_s else
'0' when rd_state = WAIT_ACK_s else '1';
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state = FRAME_s and rd_nxt_state = IDLE_s else '0';
-- Transmit frame pulse is only 1 clock enabled pulse long.
-- Transmit frame pulse must never be more frequent than 64 clocks to allow toggle to cross clock domain
rd_transmit_frame <= '1' when rd_state = WAIT_ACK_s and rd_nxt_state = FRAME_s else '0';
-- unused for full duplex only
rd_start_addr_reload <= '0';
rd_start_addr_load <= '0';
rd_retransmit_frame <= '0';
end generate gen_fd_decode;
-- decode half duplex control signals
gen_hd_decode : if (FULL_DUPLEX_ONLY = FALSE) generate
rd_en <= '0' when rd_state = IDLE_s else
'0' when (rd_nxt_state = DROP_s and rd_eof = '1') else
'1' when rd_nxt_state = FRAME_s else
'0' when rd_state = RETRANSMIT_s else
'0' when rd_state = WAIT_ACK_s else '1';
rd_addr_inc <= rd_en;
rd_addr_reload <= '1' when rd_state = FRAME_s and rd_nxt_state = IDLE_s else
'1' when rd_state = DROP_s and rd_nxt_state = IDLE_s else '0';
rd_start_addr_reload <= '1' when rd_state = RETRANSMIT_s else '0';
rd_start_addr_load <= '1' when rd_state = WAIT_ACK_s and rd_nxt_state = FRAME_s else
'1' when rd_col_window_expire = '1' else '0';
-- Transmit frame pulse must never be more frequent than 64 clocks to allow toggle to cross clock domain
rd_transmit_frame <= '1' when rd_state = WAIT_ACK_s and rd_nxt_state = FRAME_s else '0';
-- Retransmit frame pulse must never be more frequent than 16 clocks to allow toggle to cross clock domain
rd_retransmit_frame <= '1' when rd_state = RETRANSMIT_s else '0';
end generate gen_hd_decode;
-----------------------------------------------------------------------------
-- Frame Count
-- We need to maintain a count of frames in the fifo, so that we know when a
-- frame is available for transmission. The counter must be held on the
-- write clock domain as this is the faster clock.
-----------------------------------------------------------------------------
-- A frame has been written to the fifo
wr_store_frame <= '1' when wr_state = EOF_s and wr_nxt_state /= EOF_s else '0';
-- generate a toggle to indicate when a frame has been transmitted from the fifo
p_rd_trans_tog : process (rd_clk)
begin -- process
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_tran_frame_tog <= '0' after dly;
elsif rd_enable = '1' then
if rd_transmit_frame = '1' then
rd_tran_frame_tog <= not rd_tran_frame_tog after dly;
end if;
end if;
end if;
end process;
-- move the read transmit frame signal onto the write clock domain
p_sync_wr_trans : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_tran_frame_tog <= '0' after dly;
wr_tran_frame_sync <= '0' after dly;
wr_tran_frame_delay <= '0' after dly;
wr_transmit_frame <= '0' after dly;
else
wr_tran_frame_tog <= rd_tran_frame_tog after dly;
wr_tran_frame_sync <= wr_tran_frame_tog after dly;
wr_tran_frame_delay <= wr_tran_frame_sync after dly;
-- edge detector
if (wr_tran_frame_delay xor wr_tran_frame_sync) = '1' then
wr_transmit_frame <= '1' after dly;
else
wr_transmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
gen_fd_count : if (FULL_DUPLEX_ONLY = TRUE) generate
-- count the number of frames in the fifo. the counter is incremented when a
-- frame is stored and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock.
p_wr_frames : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (not wr_store_frame and wr_transmit_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_fd_count;
gen_hd_count : if (FULL_DUPLEX_ONLY = FALSE) generate
-- generate a toggle to indicate when a frame has been transmitted from the fifo
p_rd_retran_tog : process (rd_clk)
begin -- process
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_retran_frame_tog <= '0' after dly;
elsif rd_enable = '1' then
if rd_retransmit_frame = '1' then
rd_retran_frame_tog <= not rd_retran_frame_tog after dly;
end if;
end if;
end if;
end process;
-- move the read retransmit frame signal onto the write clock domain
p_sync_wr_trans : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_retran_frame_tog <= '0' after dly;
wr_retran_frame_sync <= '0' after dly;
wr_retran_frame_delay <= '0' after dly;
wr_retransmit_frame <= '0' after dly;
else
wr_retran_frame_tog <= rd_retran_frame_tog after dly;
wr_retran_frame_sync <= wr_retran_frame_tog after dly;
wr_retran_frame_delay <= wr_retran_frame_sync after dly;
-- edge detector
if (wr_retran_frame_delay xor wr_retran_frame_sync) = '1' then
wr_retransmit_frame <= '1' after dly;
else
wr_retransmit_frame <= '0' after dly;
end if;
end if;
end if;
end process p_sync_wr_trans;
-- count the number of frames in the fifo. the counter is incremented when a
-- frame is stored or retransmitted and decremented when a frame is transmitted. Need to keep
-- the counter on the write clock as this is the fastest clock.
-- Assumes transmit and retransmit cannot happen at same time
p_wr_frames : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_frames <= (others => '0') after dly;
else
if (wr_store_frame and wr_retransmit_frame) = '1' then
wr_frames <= wr_frames + 2 after dly;
elsif ((wr_store_frame or wr_retransmit_frame) and not wr_transmit_frame) = '1' then
wr_frames <= wr_frames + 1 after dly;
elsif (wr_transmit_frame and not wr_store_frame) = '1' then
wr_frames <= wr_frames - 1 after dly;
end if;
end if;
end if;
end process p_wr_frames;
end generate gen_hd_count;
-- generate a frame in fifo signal for use in control logic
p_wr_avail : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_frame_in_fifo <= '0' after dly;
else
if wr_frames /= (wr_frames'range => '0') then
wr_frame_in_fifo <= '1' after dly;
else
wr_frame_in_fifo <= '0' after dly;
end if;
end if;
end if;
end process p_wr_avail;
-- register back onto read domain for use in the read logic
p_rd_avail : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
frame_in_fifo_sync <= '0' after dly;
frame_in_fifo <= '0' after dly;
elsif rd_enable = '1' then
frame_in_fifo_sync <= wr_frame_in_fifo after dly;
frame_in_fifo <= frame_in_fifo_sync after dly;
end if;
end if;
end process p_rd_avail;
-----------------------------------------------------------------------------
-- Address counters
-----------------------------------------------------------------------------
-- Address counters
-- write address is incremented when write enable signal has been asserted
wr_addr_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_addr <= (others => '0') after dly;
elsif wr_addr_reload = '1' then
wr_addr <= wr_start_addr after dly;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_addr_p;
-- store the start address incase the address must be reset
wr_staddr_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_start_addr <= (others => '0') after dly;
elsif wr_start_addr_load = '1' then
wr_start_addr <= wr_addr + 1 after dly;
end if;
end if;
end process wr_staddr_p;
gen_fd_addr : if (FULL_DUPLEX_ONLY = TRUE) generate
-- read address is incremented when read enable signal has been asserted
rd_addr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
-- do not need to keep a start address, but the address is needed to
-- calculate fifo occupancy.
rd_start_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_start_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
rd_start_addr <= rd_addr after dly;
end if;
end if;
end process rd_start_p;
end generate gen_fd_addr;
gen_hd_addr : if (FULL_DUPLEX_ONLY = FALSE) generate
-- read address is incremented when read enable signal has been asserted
rd_addr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_addr_reload = '1' then
rd_addr <= rd_dec_addr after dly;
elsif rd_start_addr_reload = '1' then
rd_addr <= rd_start_addr after dly;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1 after dly;
end if;
end if;
end if;
end process rd_addr_p;
rd_staddr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_start_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_start_addr_load = '1' then
rd_start_addr <= rd_addr - 4 after dly;
end if;
end if;
end if;
end process rd_staddr_p;
-- Collision window expires after MAC has been transmitting for required slot
-- time. This is 512 clock cycles at 1G. Also if the end of frame has fully
-- been transmitted by the mac then a collision cannot occur. This collision
-- expire signal goes high at 768 cycles from the start of the frame.
-- Inefficient for short frames, however should be enough to prevent fifo
-- locking up.
rd_col_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_enable = '1' then
if rd_transmit_frame = '1' then
rd_col_window_expire <= '0' after dly;
elsif rd_slot_timer(9 downto 8) = "11" then
rd_col_window_expire <= '1' after dly;
end if;
end if;
end if;
end process;
rd_idle_state <= '1' when rd_state = IDLE_s else '0';
rd_colreg_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
rd_col_window_pipe(0) <= rd_col_window_expire and rd_idle_state after dly;
if rd_txfer_en = '1' then
rd_col_window_pipe(1) <= rd_col_window_pipe(0) after dly;
end if;
end if;
end if;
end process;
rd_slot_time_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then -- will not count until after first
-- frame is sent.
rd_slot_timer <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_transmit_frame = '1' then -- reset counter
rd_slot_timer <= (others => '0') after dly;
-- do not allow counter to role over.
-- only count when frame is being transmitted.
elsif rd_slot_timer /= "1111111111" then
rd_slot_timer <= rd_slot_timer + 1 after dly;
end if;
end if;
end if;
end process;
end generate gen_hd_addr;
-----------------------------------------------------------------------------
-- rd_dec addr dhouls be addr-2 assumes that rd_addr_reload will NOT happen
-- on very first packet in the fifo
-- should be ok as pipe is not loaded until data is present
rd_decaddr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_dec_addr <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_addr_inc = '1' then
rd_dec_addr <= rd_addr - 1 after dly;
end if;
end if;
end if;
end process rd_decaddr_p;
-----------------------------------------------------------------------------
-- Data pipelines
-----------------------------------------------------------------------------
-- register input signals to fifo
-- no reset to allow srl16 target
reg_din_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
wr_data_pipe(0) <= wr_data after dly;
if wr_accept_pipe(0) = '1' then
wr_data_pipe(1) <= wr_data_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_data_bram <= wr_data_pipe(1) after dly;
end if;
end if;
end process reg_din_p;
-- no reset to allow srl16 target
reg_sof_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
wr_sof_pipe(0) <= not wr_sof_n after dly;
if wr_accept_pipe(0) = '1' then
wr_sof_pipe(1) <= wr_sof_pipe(0) after dly;
end if;
end if;
end process reg_sof_p;
reg_acc_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if (wr_sreset = '1') then
wr_accept_pipe(0) <= '0' after dly;
wr_accept_pipe(1) <= '0' after dly;
wr_accept_bram <= '0' after dly;
else
wr_accept_pipe(0) <= wr_src_rdy_n nor wr_dst_rdy_int_n after dly;
wr_accept_pipe(1) <= wr_accept_pipe(0) after dly;
wr_accept_bram <= wr_accept_pipe(1) after dly;
end if;
end if;
end process reg_acc_p;
reg_eof_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
wr_eof_pipe(0) <= not wr_eof_n after dly;
if wr_accept_pipe(0) = '1' then
wr_eof_pipe(1) <= wr_eof_pipe(0) after dly;
end if;
if wr_accept_pipe(1) = '1' then
wr_eof_bram(0) <= wr_eof_pipe(1) after dly;
end if;
end if;
end process reg_eof_p;
-- register data output
-- no reset to allow srl16 target
reg_dout_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_en = '1' then
rd_data_pipe <= rd_data_bram after dly;
end if;
end if;
end if;
end process reg_dout_p;
-- register data output
-- no reset to allow srl16 target
reg_eofout_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
if rd_en = '1' then
rd_eof <= rd_eof_bram after dly;
rd_eof_reg <= rd_eof or rd_eof_bram after dly;
end if;
end if;
end if;
end process reg_eofout_p;
gen_hd_input : if (FULL_DUPLEX_ONLY = FALSE) generate
-- register the collision and retransmit signals
reg_col_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
rd_drop_frame <= tx_collision and not tx_retransmit after dly;
end if;
end if;
end process reg_col_p;
reg_retr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_enable = '1' then
rd_retransmit <= tx_collision and tx_retransmit after dly;
end if;
end if;
end process reg_retr_p;
end generate gen_hd_input;
-----------------------------------------------------------------------------
-- FIFO full functionality
-----------------------------------------------------------------------------
-- when full duplex full functionality is difference between read and write addresses.
-- when in half duplex is difference between read start and write addresses.
-- Cannot use gray code this time as the read address and read start addresses jump by more than 1
-- generate an enable pulse for the read side every 16 read clocks. This provides for the worst case
-- situation where wr clk is 20Mhz and rd clk is 125 Mhz.
p_rd_16_pulse : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_16_count <= (others => '0') after dly;
elsif rd_enable = '1' then
rd_16_count <= rd_16_count + 1 after dly;
end if;
end if;
end process;
rd_txfer_en <= '1' when rd_16_count = "1111" else '0';
-- register the start address on the enable pulse
p_rd_addr_txfer : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_addr_txfer <= (others => '0') after dly;
elsif rd_enable = '1' then
if rd_txfer_en = '1' then
rd_addr_txfer <= rd_start_addr after dly;
end if;
end if;
end if;
end process;
-- generate a toggle to indicate that the address has been loaded.
p_rd_tog_txfer : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_txfer_tog <= '0' after dly;
elsif rd_enable = '1' then
if rd_txfer_en = '1' then
rd_txfer_tog <= not rd_txfer_tog after dly;
end if;
end if;
end if;
end process;
-- pass the toggle to the write side
p_wr_tog_txfer : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_txfer_tog <= '0' after dly;
wr_txfer_tog_sync <= '0' after dly;
wr_txfer_tog_delay <= '0' after dly;
else
wr_txfer_tog <= rd_txfer_tog after dly;
wr_txfer_tog_sync <= wr_txfer_tog after dly;
wr_txfer_tog_delay <= wr_txfer_tog_sync after dly;
end if;
end if;
end process;
-- generate an enable pulse from the toggle, the address should have been steady on the wr clock input for at least one clock
wr_txfer_en <= wr_txfer_tog_delay xor wr_txfer_tog_sync;
-- capture the address on the write clock when the enable pulse is high.
p_wr_addr_txfer : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_rd_addr <= (others => '0') after dly;
elsif wr_txfer_en = '1' then
wr_rd_addr <= rd_addr_txfer after dly;
end if;
end if;
end process;
-- Obtain the difference between write and read pointers
p_wr_addr_diff : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_addr_diff <= (others => '0') after dly;
else
wr_addr_diff <= wr_rd_addr - wr_addr after dly;
end if;
end if;
end process;
-- Detect when the FIFO is full
p_wr_full : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_fifo_full <= '0' after dly;
else
-- The FIFO is considered to be full if the write address
-- pointer is within 1 to 3 of the read address pointer.
if wr_addr_diff(11 downto 4) = 0 and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1' after dly;
else
wr_fifo_full <= '0' after dly;
end if;
end if;
end if;
end process p_wr_full;
-- memory overflow occurs when the fifo is full and there are no frames
-- available in the fifo for transmission. If the collision window has
-- expired and there are no frames in the fifo and the fifo is full, then the
-- fifo is in an overflow state. we must accept the rest of the incoming
-- frame in overflow condition.
gen_fd_ovflow : if (FULL_DUPLEX_ONLY = TRUE) generate
-- in full duplex mode, the fifo memory can only overflow if the fifo goes
-- full but there is no frame available to be retranmsitted
-- prevent signal from being asserted when store_frame signal is high, as frame count is being updated
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0' else '0';
end generate gen_fd_ovflow;
gen_hd_ovflow : if (FULL_DUPLEX_ONLY = FALSE) generate
-- register wr col window to give address counter sufficient time to update.
-- prevent signal from being asserted when store_frame signal is high, as frame count is being updated
wr_fifo_overflow <= '1' when wr_fifo_full = '1' and wr_frame_in_fifo = '0'
and wr_eof_state = '0' and wr_eof_state_reg = '0' and wr_col_window_expire = '1' else '0';
-- register rd_col_window signal
-- this signal is long, and will remain high until overflow functionality
-- has finished, so save just to register the once.
p_wr_col_expire : process (wr_clk)
begin -- process
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_col_window_pipe(0) <= '0' after dly;
wr_col_window_pipe(1) <= '0' after dly;
wr_col_window_expire <= '0' after dly;
else
if wr_txfer_en = '1' then
wr_col_window_pipe(0) <= rd_col_window_pipe(1) after dly;
end if;
wr_col_window_pipe(1) <= wr_col_window_pipe(0) after dly;
wr_col_window_expire <= wr_col_window_pipe(1) after dly;
end if;
end if;
end process;
end generate gen_hd_ovflow;
----------------------------------------------------------------------
-- Create FIFO Status Signals in the Write Domain
----------------------------------------------------------------------
-- The FIFO status signal is four bits which represents the occupancy
-- of the FIFO in 16'ths. To generate this signal we therefore only
-- need to compare the 4 most significant bits of the write address
-- pointer with the 4 most significant bits of the read address
-- pointer.
-- The 4 most significant bits of the write pointer minus the 4 msb of
-- the read pointer gives us our FIFO status.
p_fifo_status : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_fifo_status <= "0000" after dly;
else
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000" after dly;
else
wr_fifo_status(3) <= not wr_addr_diff(11) after dly;
wr_fifo_status(2) <= not wr_addr_diff(10) after dly;
wr_fifo_status(1) <= not wr_addr_diff(9) after dly;
wr_fifo_status(0) <= not wr_addr_diff(8) after dly;
end if;
end if;
end if;
end process p_fifo_status;
-----------------------------------------------------------------------------
-- Memory
-----------------------------------------------------------------------------
rd_en_bram <= rd_en and rd_enable_delay2;
ramgen : RAMB36E1
generic map (
DOB_REG => 1,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SRVAL_B => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9)
port map (
ENARDEN => VCC,
CLKARDCLK => wr_clk,
RSTRAMARSTRAM => wr_sreset,
RSTREGARSTREG => GND,
CASCADEINA => GND,
REGCEAREGCE => GND,
ENBWREN => rd_en_bram,
CLKBWRCLK => rd_clk,
RSTRAMB => rd_sreset,
RSTREGB => rd_sreset,
CASCADEINB => GND,
REGCEB => rd_en_bram,
INJECTDBITERR => GND,
INJECTSBITERR => GND,
ADDRARDADDR(15) => GND,
ADDRARDADDR(14 downto 3) => std_logic_vector(wr_addr),
ADDRARDADDR(2 downto 0) => GND_BUS(2 downto 0),
ADDRBWRADDR(15) => GND,
ADDRBWRADDR(14 downto 3) => std_logic_vector(rd_addr),
ADDRBWRADDR(2 downto 0) => GND_BUS(2 downto 0),
DIADI(31 downto 8) => GND_BUS(23 downto 0),
DIADI(7 downto 0) => wr_data_bram,
DIBDI => GND_BUS,
DIPADIP(3 downto 1) => GND_BUS(2 downto 0),
DIPADIP(0) => wr_eof_bram(0),
DIPBDIP => GND_BUS(3 downto 0),
WEA(3 downto 1) => GND_BUS(2 downto 0),
WEA(0) => wr_en,
WEBWE => GND_BUS(7 downto 0),
CASCADEOUTA => open,
CASCADEOUTB => open,
DOADO => open,
DOBDO => dob_bram,
DOPADOP => open,
DOPBDOP => dopb_bram,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
DBITERR => open
);
rd_data_bram <= dob_bram(7 downto 0);
rd_eof_bram <= dopb_bram(0);
end RTL;
|
gpl-3.0
|
4c364ec06d987c389e194aef3283ef4d
| 0.543537 | 3.74355 | false | false | false | false |
bzero/freezing-spice
|
src/regfile.vhd
| 3 | 1,720 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity regfile is
port (clk : in std_logic;
addra : in std_logic_vector(4 downto 0);
addrb : in std_logic_vector(4 downto 0);
rega : out word;
regb : out word;
addrw : in std_logic_vector(4 downto 0);
dataw : in word;
we : in std_logic);
end entity regfile;
--
-- Note: Because this core is FPGA-targeted, the idea is that these registers
-- will get implemented as dual-port Distributed RAM. Because there is no
-- such thing as triple-port memory in an FPGA (that I know of), and we
-- need 3 ports to support 2 reads and 1 write per cycle, the easiest way
-- to implement that is to have two identical banks of registers that contain
-- the same data. Each uses 2 ports and everybody's happy.
--
architecture rtl of regfile is
type regbank_t is array (0 to 31) of word;
signal regbank0 : regbank_t := (others => (others => '0'));
signal regbank1 : regbank_t := (others => (others => '0'));
begin -- architecture Behavioral
-- purpose: create registers
-- type : sequential
-- inputs : clk
-- outputs:
registers_proc : process (clk) is
begin -- process registers_proc
if rising_edge(clk) then
if (we = '1') then
regbank0(to_integer(unsigned(addrw))) <= dataw;
regbank1(to_integer(unsigned(addrw))) <= dataw;
end if;
end if;
end process registers_proc;
-- asynchronous read
rega <= regbank0(to_integer(unsigned(addra)));
regb <= regbank1(to_integer(unsigned(addrb)));
end architecture rtl;
|
bsd-3-clause
|
f83fbdbb40db21a299b99c68704b5846
| 0.619767 | 3.796909 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/generic_sync_fifo.vhd
| 2 | 4,536 |
-------------------------------------------------------------------------------
-- Title : Parametrizable synchronous FIFO (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_sync_fifo.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-07-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Single-clock FIFO.
-- - configurable data width and size
-- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity generic_sync_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_empty : boolean := true; -- with empty flag
g_with_full : boolean := true; -- with full flag
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false; -- with words counter
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end generic_sync_fifo;
architecture syn of generic_sync_fifo is
component inferred_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer;
g_register_flag_outputs : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin -- syn
U_Inferred_FIFO : inferred_sync_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_show_ahead => g_show_ahead,
g_with_empty => g_with_empty,
g_with_full => g_with_full,
g_with_almost_empty => g_with_almost_empty,
g_with_almost_full => g_with_almost_full,
g_with_count => g_with_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold,
g_register_flag_outputs => g_register_flag_outputs)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => d_i,
we_i => we_i,
q_o => q_o,
rd_i => rd_i,
empty_o => empty_o,
full_o => full_o,
almost_empty_o => almost_empty_o,
almost_full_o => almost_full_o,
count_o => count_o);
end syn;
|
lgpl-3.0
|
93121685febea5cf6d744f2a28594545
| 0.480159 | 3.727198 | false | false | false | false |
huxiaolei/xapp1078_2014.4_zybo
|
design/work/project_2/project_2.srcs/sources_1/ipshared/xilinx.com/fifo_generator_v12_0/255f4893/hdl/fifo_generator_v12_0.vhd
| 1 | 90,319 |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
gpl-2.0
|
2eb1deb83a223f46bd84f7becbf234df
| 0.951848 | 1.836163 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/TESTBENCH_ac97_package.vhd
| 4 | 15,722 |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_package.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-- TESTBENCH_ac97_package.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_package.vhd
--
-- Description: Testbench utitlities for AC97
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package testbench_ac97_package is
procedure write_opb (signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
);
procedure read_opb (signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
);
procedure send_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
variable slot5 : in std_logic_vector(19 downto 0);
variable slot6 : in std_logic_vector(19 downto 0);
variable slot7 : in std_logic_vector(19 downto 0);
variable slot8 : in std_logic_vector(19 downto 0);
variable slot9 : in std_logic_vector(19 downto 0);
variable slot10 : in std_logic_vector(19 downto 0);
variable slot11 : in std_logic_vector(19 downto 0);
variable slot12 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic);
procedure send_basic_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic);
procedure read_ip (signal Bus2IP_Clk : in std_logic;
signal IP2bus_Data : in std_logic_vector(0 to 31);
constant address : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_RdCE : out std_logic;
signal IP_READ : out std_logic_vector(0 to 31)
);
procedure write_ip (signal Bus2IP_Clk : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_Data : out std_logic_vector(0 to 31);
signal Bus2IP_WrCE : out std_logic
);
procedure delay(signal sig : in std_logic; constant cycles : in integer);
constant BIT_CLK_HALF_PERIOD : time := 40.69 ns;
constant FIFO_CTRL_OFFSET : std_logic_vector(0 to 31) := X"00000004";
constant STATUS_OFFSET : std_logic_vector(0 to 31) := X"00000004";
constant IN_FIFO_OFFSET : std_logic_vector(0 to 31) := X"00000000";
constant OUT_FIFO_OFFSET : std_logic_vector(0 to 31) := X"00000000";
constant REG_ADDR_OFFSET : std_logic_vector(0 to 31) := X"0000000C";
constant REG_DATA_OFFSET : std_logic_vector(0 to 31) := X"00000008";
constant REG_DATA_WRITE_OFFSET : std_logic_vector(0 to 31) := X"00000008";
constant FIFO_CLEAR_MASK : std_logic_vector(0 to 31) := X"00000003";
constant ENABLE_PLAY_INT_MASK : std_logic_vector(0 to 31) := X"00000004";
end testbench_ac97_package;
package body testbench_ac97_package is
procedure delay(signal sig : in std_logic; constant cycles : in integer) is
begin
for i in cycles-1 downto 0 loop
wait until sig'event and sig='1';
end loop;
end delay;
procedure write_opb(signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
) is
begin
wait until opb_clk'event and opb_clk='0';
OPB_select <= '1';
OPB_ABus <= address;
OPB_DBus <= data;
OPB_RNW <= '0';
wait until opb_clk'event and opb_clk='1' and xferAck='1';
OPB_select <= '0';
OPB_ABus <= X"0000_0000";
OPB_DBus <= X"0000_0000";
for i in 15 downto 0 loop
wait until opb_clk'event and opb_clk='0';
end loop;
end write_opb;
procedure read_opb (signal OPB_Clk : in std_logic;
signal xferAck : in std_logic;
constant address : in std_logic_vector(0 to 31);
signal OPB_select : out std_logic;
signal OPB_RNW : out std_logic;
signal OPB_ABus : out std_logic_vector(0 to 31);
signal OPB_DBus : out std_logic_vector(0 to 31)
) is
begin
wait until opb_clk'event and opb_clk='0';
OPB_select <= '1';
OPB_ABus <= address;
OPB_DBus <= X"0000_0000";
OPB_RNW <= '1';
wait until opb_clk'event and opb_clk='1' and xferAck='1';
OPB_select <= '0';
OPB_ABus <= X"0000_0000";
OPB_RNW <= '0';
for i in 15 downto 0 loop
wait until opb_clk'event and opb_clk='0';
end loop;
end read_opb;
procedure write_ip (signal Bus2IP_Clk : in std_logic;
constant address : in std_logic_vector(0 to 31);
constant data : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_Data : out std_logic_vector(0 to 31);
signal Bus2IP_WrCE : out std_logic
) is
begin
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
Bus2IP_Addr <= address;
Bus2IP_Data <= data;
Bus2IP_CS <= '1';
Bus2IP_WrCE <= '1';
--wait until Bus2IP_Clk'event and Bus2IP_Clk='1' and IP2Bus_Ack='1';
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
Bus2IP_Addr <= (others => '0');
Bus2IP_CS <= '0';
Bus2IP_Data <= (others => '0');
Bus2IP_WrCE <= '0';
for i in 15 downto 0 loop
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
end loop;
end write_ip;
procedure read_ip (signal Bus2IP_Clk : in std_logic;
signal IP2bus_Data : in std_logic_vector(0 to 31);
constant address : in std_logic_vector(0 to 31);
signal Bus2IP_CS : out std_logic;
signal Bus2IP_Addr : out std_logic_vector(0 to 31);
signal Bus2IP_RdCE : out std_logic;
signal IP_READ : out std_logic_vector(0 to 31)
) is
begin
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
Bus2IP_Addr <= address;
Bus2IP_CS <= '1';
Bus2IP_RdCE <= '1';
--wait until Bus2IP_Clk'event and Bus2IP_Clk='1' and IP2Bus_Ack='1';
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
IP_READ <= IP2Bus_Data;
Bus2IP_Addr <= (others => '0');
Bus2IP_CS <= '0';
Bus2IP_RdCE <= '0';
for i in 15 downto 0 loop
wait until Bus2IP_Clk'event and Bus2IP_Clk='1';
end loop;
end read_ip;
procedure send_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
variable slot5 : in std_logic_vector(19 downto 0);
variable slot6 : in std_logic_vector(19 downto 0);
variable slot7 : in std_logic_vector(19 downto 0);
variable slot8 : in std_logic_vector(19 downto 0);
variable slot9 : in std_logic_vector(19 downto 0);
variable slot10 : in std_logic_vector(19 downto 0);
variable slot11 : in std_logic_vector(19 downto 0);
variable slot12 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic) is
variable shift_16 : std_logic_vector(15 downto 0);
variable shift_20 : std_logic_vector(19 downto 0);
begin
-- Slot 0
shift_16 := slot0;
slot0_loop: for i in 15 downto 0 loop
sdata_in <= shift_16(i);
wait until clk'event and clk='1';
end loop;
-- Slot 1
shift_20 := slot1;
slot1_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 2
shift_20 := slot2;
slot2_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 3
shift_20 := slot3;
slot3_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 4
shift_20 := slot4;
slot4_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 5
shift_20 := slot5;
slot5_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 6
shift_20 := slot6;
slot6_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 7
shift_20 := slot7;
slot7_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 8
shift_20 := slot8;
slot8_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 9
shift_20 := slot9;
slot9_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 10
shift_20 := slot10;
slot10_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 11
shift_20 := slot11;
slot11_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
-- Slot 12
shift_20 := slot12;
slot12_loop: for i in 19 downto 0 loop
sdata_in <= shift_20(i);
wait until clk'event and clk='1';
end loop;
end send_frame;
procedure send_basic_frame (signal clk : in std_logic;
variable slot0 : in std_logic_vector(15 downto 0);
variable slot1 : in std_logic_vector(19 downto 0);
variable slot2 : in std_logic_vector(19 downto 0);
variable slot3 : in std_logic_vector(19 downto 0);
variable slot4 : in std_logic_vector(19 downto 0);
signal SData_In : out std_logic) is
variable slot5 : std_logic_vector(19 downto 0) := X"00000";
variable slot6 : std_logic_vector(19 downto 0) := X"00000";
variable slot7 : std_logic_vector(19 downto 0) := X"00000";
variable slot8 : std_logic_vector(19 downto 0) := X"00000";
variable slot9 : std_logic_vector(19 downto 0) := X"00000";
variable slot10 : std_logic_vector(19 downto 0) := X"00000";
variable slot11 : std_logic_vector(19 downto 0) := X"00000";
variable slot12 : std_logic_vector(19 downto 0) := X"00000";
begin
send_frame(clk, slot0, slot1, slot2, slot3, slot4,
slot5, slot6, slot7, slot8, slot9, slot10, slot11,
slot12,sdata_in);
end send_basic_frame;
end testbench_ac97_package;
|
gpl-3.0
|
f31062e5903ed5c8bf8802b161fdd26e
| 0.492177 | 4.036457 | false | false | false | false |
five-elephants/hw-neural-sampling
|
net_config_pkg.vhdl
| 1 | 2,078 |
library ieee;
use ieee.std_logic_1164.all;
use work.sampling.all;
package net_config is
constant tau : positive := 20;
constant num_samplers : integer := 128;
constant num_observers : natural := 16;
constant seeds : lfsr_state_array_t(1 to num_samplers) := (others => (others => '1'));
constant biases : weight_array_t(1 to num_samplers) := (
others => make_fixed(0.0, weight_width-weight_fraction-1, weight_fraction)
);
constant weights : weight_array2_t(1 to num_samplers, 1 to num_samplers) := (
others => (
others => make_fixed(0.0, weight_width-weight_fraction-1, weight_fraction)
)
);
constant observed_joints : state_array2_t(1 to num_observers, 1 to num_samplers) := (
others => (others => '0')
);
--constant biases : weight_array_t(1 to num_samplers) := (
--make_fixed(-1.0, 2, 1),
--make_fixed(-0.5, 2, 1),
--make_fixed(-2.0, 2, 1),
--make_fixed(-1.5, 2, 1)
--);
--constant weights : weight_array2_t(1 to num_samplers, 1 to num_samplers) := (
--(make_fixed(0.0, 2, 1), make_fixed(1.5, 2, 1), make_fixed(1.0, 2, 1), make_fixed(-1.0, 2, 1)),
--(make_fixed(1.5, 2, 1), make_fixed(0.0, 2, 1), make_fixed(1.0, 2, 1), make_fixed(-1.0, 2, 1)),
--(make_fixed(1.0, 2, 1), make_fixed(1.0, 2, 1), make_fixed(0.0, 2, 1), make_fixed(0.5, 2, 1)),
--(make_fixed(-1.0, 2, 1), make_fixed(-1.0, 2, 1), make_fixed(0.5, 2, 1), make_fixed(0.0, 2, 1))
--);
--constant observed_joints : state_array2_t(1 to num_observers, 1 to num_samplers) := (
--( '0', '0', '0', '0' ),
--( '0', '0', '0', '1' ),
--( '0', '0', '1', '0' ),
--( '0', '0', '1', '1' ),
--( '0', '1', '0', '0' ),
--( '0', '1', '0', '1' ),
--( '0', '1', '1', '0' ),
--( '0', '1', '1', '1' ),
--( '1', '0', '0', '0' ),
--( '1', '0', '0', '1' ),
--( '1', '0', '1', '0' ),
--( '1', '0', '1', '1' ),
--( '1', '1', '0', '0' ),
--( '1', '1', '0', '1' ),
--( '1', '1', '1', '0' ),
--( '1', '1', '1', '1' )
--);
end net_config;
-- vim: set et fenc= ff=unix sts=0 sw=2 ts=2 : --
|
apache-2.0
|
199a0fa6d7e51b3465aac62a392df3cf
| 0.489894 | 2.488623 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/rom/rom_sim_netlist.vhdl
| 1 | 200,148 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sun Jun 5 17:42:57 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/rom/rom_sim_netlist.vhdl
-- Design : rom
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_bindec is
port (
ram_ena : out STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_bindec : entity is "bindec";
end rom_bindec;
architecture STRUCTURE of rom_bindec is
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => addra(0),
I1 => addra(2),
I2 => addra(3),
I3 => addra(1),
O => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC;
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\ : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\ : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\ : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end rom_blk_mem_gen_mux;
architecture STRUCTURE of rom_blk_mem_gen_mux is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \douta[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[0]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[1]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[2]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
Q(0) <= \^q\(0);
\douta[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[0]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
I3 => sel_pipe(3),
I4 => \douta[0]_INST_0_i_3_n_0\,
O => douta(0)
);
\douta[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0),
O => \douta[0]_INST_0_i_1_n_0\
);
\douta[0]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
O => \douta[0]_INST_0_i_3_n_0\
);
\douta[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[1]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\,
I3 => sel_pipe(3),
I4 => \douta[1]_INST_0_i_3_n_0\,
O => douta(1)
);
\douta[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(1),
O => \douta[1]_INST_0_i_1_n_0\
);
\douta[1]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1),
O => \douta[1]_INST_0_i_3_n_0\
);
\douta[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[2]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\,
I3 => sel_pipe(3),
I4 => \douta[2]_INST_0_i_3_n_0\,
O => douta(2)
);
\douta[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(2),
O => \douta[2]_INST_0_i_1_n_0\
);
\douta[2]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2),
O => \douta[2]_INST_0_i_3_n_0\
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[3]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\,
I3 => sel_pipe(3),
I4 => \douta[3]_INST_0_i_3_n_0\,
O => douta(3)
);
\douta[3]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(3),
O => \douta[3]_INST_0_i_1_n_0\
);
\douta[3]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3),
O => \douta[3]_INST_0_i_3_n_0\
);
\douta[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[4]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\,
I3 => sel_pipe(3),
I4 => \douta[4]_INST_0_i_3_n_0\,
O => douta(4)
);
\douta[4]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(4),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(4),
O => \douta[4]_INST_0_i_1_n_0\
);
\douta[4]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4),
O => \douta[4]_INST_0_i_3_n_0\
);
\douta[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[5]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\,
I3 => sel_pipe(3),
I4 => \douta[5]_INST_0_i_3_n_0\,
O => douta(5)
);
\douta[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(5),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(5),
O => \douta[5]_INST_0_i_1_n_0\
);
\douta[5]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5),
O => \douta[5]_INST_0_i_3_n_0\
);
\douta[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[6]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\,
I3 => sel_pipe(3),
I4 => \douta[6]_INST_0_i_3_n_0\,
O => douta(6)
);
\douta[6]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(6),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(6),
O => \douta[6]_INST_0_i_1_n_0\
);
\douta[6]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6),
O => \douta[6]_INST_0_i_3_n_0\
);
\douta[7]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \douta[7]_INST_0_i_1_n_0\,
I1 => sel_pipe(2),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\,
I3 => sel_pipe(3),
I4 => \douta[7]_INST_0_i_3_n_0\,
O => douta(7)
);
\douta[7]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F20"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(7),
I1 => sel_pipe(0),
I2 => \^q\(0),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(7),
O => \douta[7]_INST_0_i_1_n_0\
);
\douta[7]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOADO(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I2 => sel_pipe(2),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
I4 => \^q\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7),
O => \douta[7]_INST_0_i_3_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => \^q\(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(2),
Q => sel_pipe(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(3),
Q => sel_pipe(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_blk_mem_gen_prim_wrapper_init is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end rom_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of rom_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202052525252525252525252525252525252522020202020202020",
INIT_06 => X"6C20202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"20202020202020202020202020202020202020202020202020206C6C6C6C6C6C",
INIT_08 => X"2020202020747474742020202020202020202020202020207474747420202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"202020202020523A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A522020202020202020",
INIT_0B => X"6C20202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"20202020202020202020202020202020202020202020202020206C3A3A3A3A3A",
INIT_0D => X"2020202020743A3A3A747474202020202020202020202020743A3A3A74747420",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020523A3A3A3A3A5252525252523A3A3A3A3A3A522020202020202020",
INIT_10 => X"6C20202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"20202020202020202020202020202020202020202020202020206C3A3A3A3A3A",
INIT_12 => X"2020202020743A3A3A3A3A74202020202020202020202020743A3A3A3A3A7420",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"20202020523A3A3A3A3A522020202020523A3A3A3A3A52522020202020202020",
INIT_15 => X"6C20202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"20202020202020202020202020202020202020202020202020206C3A3A3A3A3A",
INIT_17 => X"2020202020743A3A3A3A3A74202020202020202020202020743A3A3A3A3A7420",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"6F202020523A3A3A3A3A522020202020523A3A3A3A5220202020202020202020",
INIT_1A => X"202020757575757575202020207575757575752020206F6F6F6F6F6F6F6F6F6F",
INIT_1B => X"74747474742020202065656565656565656565656520202020206C3A3A3A3A6C",
INIT_1C => X"7474747474743A3A3A3A3A74747474747474747474747474743A3A3A3A3A7474",
INIT_1D => X"2020202020202020202020656565656565656565656565202020202020202074",
INIT_1E => X"3A6F6F20523A3A3A3A3A522020202020523A3A3A3A5220202020202020202020",
INIT_1F => X"202020753A3A3A3A7520202020753A3A3A3A75206F6F3A3A3A3A3A3A3A3A3A3A",
INIT_20 => X"3A3A3A3A74202065653A3A3A3A3A3A3A3A3A3A3A3A65652020206C3A3A3A3A6C",
INIT_21 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A74743A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_22 => X"20202020202020202065653A3A3A3A3A3A3A3A3A3A3A3A656520202020202074",
INIT_23 => X"3A3A3A6F20523A3A3A3A3A5252525252523A3A3A3A5220202020202020202020",
INIT_24 => X"202020753A3A3A3A7520202020753A3A3A3A756F3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_25 => X"3A3A3A3A7465653A3A3A3A3A65656565653A3A3A3A3A3A6520206C3A3A3A3A6C",
INIT_26 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A74743A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_27 => X"2020202020202065653A3A3A3A3A65656565653A3A3A3A3A3A65202020202074",
INIT_28 => X"3A3A3A6F202052523A3A3A3A3A3A3A3A3A3A3A3A3A5220202020202020202020",
INIT_29 => X"202020753A3A3A3A7520202020753A3A3A3A756F3A3A3A3A3A6F6F6F6F6F3A3A",
INIT_2A => X"7474747474653A3A3A3A3A652020202020653A3A3A3A3A3A65206C3A3A3A3A6C",
INIT_2B => X"74747474743A3A3A3A3A3A3A7474747474747474747474743A3A3A3A3A3A3A74",
INIT_2C => X"20202020202020653A3A3A3A3A652020202020653A3A3A3A3A3A652020202074",
INIT_2D => X"3A3A3A6F20523A3A3A3A3A5252525252523A3A3A3A5220202020202020202020",
INIT_2E => X"202020753A3A3A3A7520202020753A3A3A3A756F3A3A3A3A6F20202020206F3A",
INIT_2F => X"2020202020653A3A3A3A3A3A65656565653A3A3A3A3A3A3A65206C3A3A3A3A6C",
INIT_30 => X"2020202020743A3A3A3A3A74202020202020202020202020743A3A3A3A3A7420",
INIT_31 => X"20202020202020653A3A3A3A3A3A65656565653A3A3A3A3A3A3A652020202020",
INIT_32 => X"3A3A3A6F523A3A3A3A3A522020202020523A3A3A3A5220202020202020202020",
INIT_33 => X"202020753A3A3A3A7520202020753A3A3A3A756F3A3A3A3A6F20202020206F3A",
INIT_34 => X"202020202020653A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A65206C3A3A3A3A6C",
INIT_35 => X"2020202020743A3A3A3A3A74202020202020202020202020743A3A3A3A3A7420",
INIT_36 => X"2020202020202020653A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A652020202020",
INIT_37 => X"3A3A3A6F523A3A3A3A3A522020202020523A3A3A3A5220202020202020202020",
INIT_38 => X"202020753A3A3A3A7520202020753A3A3A3A756F3A3A3A3A6F20202020206F3A",
INIT_39 => X"2020202020202065656565656565656565653A3A3A3A3A3A65206C3A3A3A3A6C",
INIT_3A => X"2020202020743A3A3A3A3A74202020202020202020202020743A3A3A3A3A7420",
INIT_3B => X"20202020202020202065656565656565656565653A3A3A3A3A3A652020202020",
INIT_3C => X"3A3A3A6F523A3A3A3A3A522020202020523A3A3A3A5220202020202020202020",
INIT_3D => X"202020753A3A3A3A3A757575753A3A3A3A3A756F3A3A3A3A6F20202020206F3A",
INIT_3E => X"20202020202020202020202020202020653A3A3A3A3A3A3A65206C3A3A3A3A6C",
INIT_3F => X"7420202020743A3A3A3A3A74202074747474747420202020743A3A3A3A3A7420",
INIT_40 => X"202020202020202020202020202020202020653A3A3A3A3A3A3A657474747474",
INIT_41 => X"3A3A3A6F523A3A3A3A3A522020202020523A3A3A3A3A52522020202020202020",
INIT_42 => X"6C75753A3A3A3A3A3A3A3A3A3A3A3A3A3A3A756F3A3A3A3A3A6F6F6F6F6F3A3A",
INIT_43 => X"202020202020202020202020202020653A3A3A3A3A3A3A3A656C3A3A3A3A3A3A",
INIT_44 => X"3A747474743A3A3A3A3A3A742020743A3A3A3A3A747474743A3A3A3A3A3A7420",
INIT_45 => X"2020202020202020202020202020202020653A3A3A3A3A3A3A3A65743A3A3A3A",
INIT_46 => X"3A3A3A6F523A3A3A3A3A522020202020523A3A3A3A3A3A522020202020202020",
INIT_47 => X"6C753A3A3A3A3A3A3A3A3A3A3A3A3A3A3A75206F3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_48 => X"2020202020202065656565656565653A3A3A3A3A3A3A3A65206C3A3A3A3A3A3A",
INIT_49 => X"3A3A3A3A3A3A3A3A3A3A74742020743A3A3A3A3A3A3A3A3A3A3A3A3A3A747420",
INIT_4A => X"20202020202020202065656565656565653A3A3A3A3A3A3A3A6520743A3A3A3A",
INIT_4B => X"3A6F6F20523A3A3A3A3A522020202020523A3A3A3A3A3A522020202020202020",
INIT_4C => X"6C753A3A3A75753A3A3A3A3A3A3A3A75752020206F6F3A3A3A3A3A3A3A3A3A3A",
INIT_4D => X"20202020202020653A3A3A3A3A3A3A3A3A3A3A3A3A656520206C3A3A3A3A3A3A",
INIT_4E => X"3A3A3A3A3A3A3A3A74742020202074743A3A3A3A3A3A3A3A3A3A3A7474202020",
INIT_4F => X"202020202020202020653A3A3A3A3A3A3A3A3A3A3A3A3A6565202074743A3A3A",
INIT_50 => X"6F20202052525252525252202020202052525252525252522020202020202020",
INIT_51 => X"6C7575757520207575757575757575202020202020206F6F6F6F6F6F6F6F6F6F",
INIT_52 => X"202020202020206565656565656565656565656565202020206C6C6C6C6C6C6C",
INIT_53 => X"7474747474747474202020202020202074747474747474747474742020202020",
INIT_54 => X"2020202020202020206565656565656565656565656565202020202020747474",
INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2B20202020202020",
INIT_5B => X"20202020202B2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D",
INIT_5C => X"2D2D2D2D2D2D2D2B2D2D2D2D2D2D2D2D2D2D2D2D2D2D2B2D2D2D2D2D2D2D2D2B",
INIT_5D => X"2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2B20202020202B2D2D2D2D2D2D2D",
INIT_5E => X"202020202020202B2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D",
INIT_5F => X"202020202020202020202020202020206E69656C50202A207C20202020202020",
INIT_60 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_61 => X"202D2D2D2024207C20202020202030202020202020207C2020202D2D2020207C",
INIT_62 => X"2020202020202020202020202073746542207C20202020207C202D2D2E2D2D2D",
INIT_63 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_64 => X"20202020202020202020207265626D756E20656E4F2020207C20202020202020",
INIT_65 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_66 => X"2D2D2D2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2D2D2D2D2B",
INIT_67 => X"2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2B20202020202B2D2D2D2D2D2B2D",
INIT_68 => X"202020202020202B2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D",
INIT_69 => X"202020202020202020202074756F796170207835332020207C20202020202020",
INIT_6A => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_6B => X"4555514E414D207C202033207C202032207C202031207C20204553534150207C",
INIT_6C => X"2020202020202020202020202020202020207C20202020207C20503231207C20",
INIT_6D => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020207C20202020202020",
INIT_6F => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_70 => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_71 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_72 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020206C6176656843202A207C20202020202020",
INIT_74 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_75 => X"202020202020207C202036207C202035207C202034207C20202020202020207C",
INIT_76 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_77 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_78 => X"202020202020207372756F62686769656E206F77542020207C20202020202020",
INIT_79 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_7A => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_7B => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_7C => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_7D => X"202020202020202020202074756F796170207837312020207C20202020202020",
INIT_7E => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_7F => X"202020202020207C202039207C202038207C202037207C20202020202020207C",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra(12),
I1 => addra(14),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \rom_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_01 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020207C20202020202020",
INIT_03 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_04 => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_05 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_06 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_07 => X"202020202020202020656C6173726576736E617254202A207C20202020202020",
INIT_08 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_09 => X"202020202020207C203231207C203131207C203031207C20202020202020207C",
INIT_0A => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_0B => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_0C => X"202020202020202020656572687420666F20776F522020207C20202020202020",
INIT_0D => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_0E => X"2D2D2D2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2D2D2D2D2B",
INIT_0F => X"2020202020202020202020202020202020207C20202020202B2D2D2D2D2D2B2D",
INIT_10 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_11 => X"202020202020202020202074756F796170207831312020207C20202020202020",
INIT_12 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_13 => X"524941504D49207C203531207C203431207C203331207C20202052494150207C",
INIT_14 => X"2020202020202020202020202020202020207C20202020207C204D3231207C20",
INIT_15 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020207C20202020202020",
INIT_17 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_18 => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_19 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_1A => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_1B => X"2020656C706D697320656C6173726576736E617254202A207C20202020202020",
INIT_1C => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_1D => X"202020202020207C203831207C203731207C203631207C20202020202020207C",
INIT_1E => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_1F => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_20 => X"73776F7220676E6972756F62686769656E206F77542020207C20202020202020",
INIT_21 => X"20202020207C2020202020202020202020202020202020656572687420666F20",
INIT_22 => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_23 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_24 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_25 => X"20202020202020202020202074756F7961702078352020207C20202020202020",
INIT_26 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_27 => X"202020202020207C203132207C203032207C203931207C20202020202020207C",
INIT_28 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_29 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020207C20202020202020",
INIT_2B => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_2C => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_2D => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_2E => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_2F => X"202020202020202020202020202020206572726143202A207C20202020202020",
INIT_30 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_31 => X"202020202020207C203432207C203332207C203232207C20202020202020207C",
INIT_32 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_33 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_34 => X"62686769656E2072756F6620666F206572617571532020207C20202020202020",
INIT_35 => X"20202020207C202020202020202020202020202020202020202020207372756F",
INIT_36 => X"2D2D2D2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2D2D2D2D2B",
INIT_37 => X"2020202020202020202020202020202020207C20202020202B2D2D2D2D2D2B2D",
INIT_38 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_39 => X"20202020202020202020202074756F7961702078382020207C20202020202020",
INIT_3A => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_3B => X"204547554F52207C203732207C203632207C203532207C20202052494F4E207C",
INIT_3C => X"2020202020202020202020202020202020207C20202020207C20443231207C20",
INIT_3D => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_3E => X"2020202020202020202020202020202020202020202020207C20202020202020",
INIT_3F => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_40 => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_41 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_42 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_43 => X"2020202020202020202020202020656E6E6F6C6F43202A207C20202020202020",
INIT_44 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_45 => X"202020202020207C203033207C203932207C203832207C20202020202020207C",
INIT_46 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_47 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_48 => X"202C31522820737265626E6D756E2065766C6577542020207C20202020202020",
INIT_49 => X"20202020207C20202944323120726F204D3231202C503231202C3352202C3252",
INIT_4A => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_4B => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_4C => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_4D => X"20202020202020202020202074756F7961702078322020207C20202020202020",
INIT_4E => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_4F => X"202020202020207C203333207C203233207C203133207C20202020202020207C",
INIT_50 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_51 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_52 => X"2020202020202020202020202020202020202020202020207C20202020202020",
INIT_53 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_54 => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B20202020202020207C",
INIT_55 => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_56 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_57 => X"2020202020202020656C706D69532065636E616843202A207C20202020202020",
INIT_58 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_59 => X"202020202020207C203633207C203533207C203433207C20202020202020207C",
INIT_5A => X"2020202020202020202020202020202020207C20202020207C20202020207C20",
INIT_5B => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_5C => X"6D49202C72696150202C6567756F52202C72696F4E2020207C20202020202020",
INIT_5D => X"20202020207C2020202020657373615020726F206575716E614D202C72696170",
INIT_5E => X"2D2D2D2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2D2D2D2D2B",
INIT_5F => X"2020202020202020202020202020202020207C20202020202B2D2D2D2D2D2B2D",
INIT_60 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_61 => X"20202020202020202020202074756F7961702078312020207C20202020202020",
INIT_62 => X"20202020207C2020202020202020202020202020202020202020202020202020",
INIT_63 => X"202020202020207C203352207C203252207C203152207C202020202020202020",
INIT_64 => X"2020202020202020202020202020202020207C20202020202020202020202020",
INIT_65 => X"202020202020207C202020202020202020202020202020202020202020202020",
INIT_66 => X"2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2B20202020202020",
INIT_67 => X"20202020202B2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D",
INIT_68 => X"202020202020202B2D2D2D2D2B2D2D2D2D2B2D2D2D2D2B202020202020202020",
INIT_69 => X"2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2B20202020202020202020202020",
INIT_6A => X"202020202020202B2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D2D",
INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => addra(12),
I1 => addra(14),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \rom_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020",
INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074",
INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073",
INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_40 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_41 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_42 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_43 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_44 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_45 => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_46 => X"2020202069696969202048484848484848484820202020204848484848484848",
INIT_47 => X"4C4C4C4C4C4C4C20202020202020202020202020202020202020202020202020",
INIT_48 => X"202020202020202020202020202020202020202020202020202020204C4C4C4C",
INIT_49 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4A => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_4B => X"202020693A3A3A3A6920483A3A3A3A3A3A3A482020202020483A3A3A3A3A3A3A",
INIT_4C => X"3A3A3A3A3A3A4C20202020202020202020202020202020202020202020202020",
INIT_4D => X"202020202020202020202020202020202020202020202020202020204C3A3A3A",
INIT_4E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_4F => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_50 => X"20202020696969692020483A3A3A3A3A3A3A482020202020483A3A3A3A3A3A3A",
INIT_51 => X"3A3A3A3A3A3A4C20202020202020202020202020202020202020202020202020",
INIT_52 => X"202020202020202020202020202020202020202020202020202020204C3A3A3A",
INIT_53 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_54 => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_55 => X"2020202020202020202048483A3A3A3A3A3A482020202020483A3A3A3A3A3A48",
INIT_56 => X"3A3A3A3A3A4C4C20202020202020202020202020202020202020202020202020",
INIT_57 => X"202020202020202020202020202020202020202020202020202020204C4C3A3A",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"202020696969696969692020483A3A3A3A3A482020202020483A3A3A3A3A4820",
INIT_5B => X"3A3A3A3A4C202020202020202020202020202020202020202020202020202020",
INIT_5C => X"206F6F6F6F6F6F6F6F6F6F6F2020202020202020202020202020202020204C3A",
INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"202020693A3A3A3A3A692020483A3A3A3A3A482020202020483A3A3A3A3A4820",
INIT_60 => X"3A3A3A3A4C202020202020202020202020202020202020202020202020202020",
INIT_61 => X"6F3A3A3A3A3A3A3A3A3A3A3A6F6F202020202020202020202020202020204C3A",
INIT_62 => X"202020202020202020202020202020202020202020202020202020202020206F",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"202020693A3A3A3A69202020483A3A3A3A3A3A48484848483A3A3A3A3A3A4820",
INIT_65 => X"3A3A3A3A4C202020202020202020202020202020202020202020202020202020",
INIT_66 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A6F2020202020202020202020202020204C3A",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"202020693A3A3A3A69202020483A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4820",
INIT_6A => X"3A3A3A3A4C20202020202020202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020",
INIT_6B => X"3A3A3A3A6F6F6F6F6F3A3A3A3A3A6F2020202020202020202020202020204C3A",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"202020693A3A3A3A69202020483A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4820",
INIT_6F => X"3A3A3A3A4C20202020202020202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D20202020",
INIT_70 => X"3A3A3A6F20202020206F3A3A3A3A6F2020202020202020202020202020204C3A",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"202020693A3A3A3A69202020483A3A3A3A3A3A48484848483A3A3A3A3A3A4820",
INIT_74 => X"3A3A3A3A4C20202020202020202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020",
INIT_75 => X"3A3A3A6F20202020206F3A3A3A3A6F2020202020202020202020202020204C3A",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"202020693A3A3A3A69202020483A3A3A3A3A482020202020483A3A3A3A3A4820",
INIT_79 => X"3A3A3A3A4C202020202020202020202020202020202020202020202020202020",
INIT_7A => X"3A3A3A6F20202020206F3A3A3A3A6F2020202020202020202020202020204C3A",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"202020693A3A3A3A69202020483A3A3A3A3A482020202020483A3A3A3A3A4820",
INIT_7E => X"3A3A3A3A4C202020202020202020202020202020202020202020202020202020",
INIT_7F => X"3A3A3A6F20202020206F3A3A3A3A6F4C4C4C4C4C4C2020202020202020204C3A",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => addra(13),
I1 => addra(12),
I2 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \rom_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_01 => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020693A3A3A3A3A3A6948483A3A3A3A3A3A482020202020483A3A3A3A3A3A48",
INIT_03 => X"3A3A3A3A3A4C4C20202020202020202020202020202020202020202020202020",
INIT_04 => X"3A3A3A3A6F6F6F6F6F3A3A3A3A3A6F4C3A3A3A3A3A4C4C4C4C4C4C4C4C4C3A3A",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_06 => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020693A3A3A3A3A3A69483A3A3A3A3A3A3A482020202020483A3A3A3A3A3A3A",
INIT_08 => X"3A3A3A3A3A3A4C20202020202020202020202020202020202020202020202020",
INIT_09 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A6F4C3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020206F3A",
INIT_0B => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020693A3A3A3A3A3A69483A3A3A3A3A3A3A482020202020483A3A3A3A3A3A3A",
INIT_0D => X"3A3A3A3A3A3A4C20202020202020202020202020202020202020202020202020",
INIT_0E => X"6F3A3A3A3A3A3A3A3A3A3A3A6F6F204C3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A",
INIT_0F => X"202020202020202020202020202020202020202020202020202020202020206F",
INIT_10 => X"4820202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020696969696969696948484848484848484820202020204848484848484848",
INIT_12 => X"4C4C4C4C4C4C4C20202020202020202020202020202020202020202020202020",
INIT_13 => X"206F6F6F6F6F6F6F6F6F6F6F2020204C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C4C",
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IS_RSTREGARSTREG_INVERTED => '0',
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RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
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RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
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WRITE_MODE_B => "WRITE_FIRST",
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WRITE_WIDTH_B => 9
)
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ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => addra(14),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \rom_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
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DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_61 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"6867697279706F43202020202020202020202020202020202020202020202020",
INIT_7D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074",
INIT_7E => X"20202020202020202020202020202020202020202020203E74656E2E37303073",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => addra(14),
I1 => addra(12),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\douta[0]\ : out STD_LOGIC;
\douta[1]\ : out STD_LOGIC;
\douta[2]\ : out STD_LOGIC;
\douta[3]\ : out STD_LOGIC;
\douta[4]\ : out STD_LOGIC;
\douta[5]\ : out STD_LOGIC;
\douta[6]\ : out STD_LOGIC;
\douta[7]\ : out STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \rom_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_48\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_50\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_51\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_52\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \douta[0]_INST_0_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \douta[1]_INST_0_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \douta[2]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \douta[3]_INST_0_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \douta[4]_INST_0_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \douta[5]_INST_0_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \douta[6]_INST_0_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \douta[7]_INST_0_i_2\ : label is "soft_lutpair3";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_48\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49\,
DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_50\,
DOADO(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_51\,
DOADO(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_52\,
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(12),
I1 => addra(14),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__4_n_0\
);
\douta[0]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_52\,
I1 => Q(0),
I2 => DOADO(0),
O => \douta[0]\
);
\douta[1]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_51\,
I1 => Q(0),
I2 => DOADO(1),
O => \douta[1]\
);
\douta[2]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_50\,
I1 => Q(0),
I2 => DOADO(2),
O => \douta[2]\
);
\douta[3]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_49\,
I1 => Q(0),
I2 => DOADO(3),
O => \douta[3]\
);
\douta[4]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_48\,
I1 => Q(0),
I2 => DOADO(4),
O => \douta[4]\
);
\douta[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47\,
I1 => Q(0),
I2 => DOADO(5),
O => \douta[5]\
);
\douta[6]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
I1 => Q(0),
I2 => DOADO(6),
O => \douta[6]\
);
\douta[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
I1 => Q(0),
I2 => DOADO(7),
O => \douta[7]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \rom_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 0) => B"00000000000000000000000000000000",
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5_n_0\,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"0000",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(14),
I1 => addra(13),
I2 => addra(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__5_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ram_ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \rom_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 0) => B"0000000000000000",
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_n_33\,
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_ena,
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_blk_mem_gen_prim_width is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end rom_blk_mem_gen_prim_width;
architecture STRUCTURE of rom_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.rom_blk_mem_gen_prim_wrapper_init
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \rom_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\rom_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \rom_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\rom_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_width__parameterized2\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \rom_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\rom_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(14 downto 0) => addra(14 downto 0),
clka => clka
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_width__parameterized3\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \rom_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\rom_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(14 downto 0) => addra(14 downto 0),
clka => clka
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_width__parameterized4\ is
port (
\douta[0]\ : out STD_LOGIC;
\douta[1]\ : out STD_LOGIC;
\douta[2]\ : out STD_LOGIC;
\douta[3]\ : out STD_LOGIC;
\douta[4]\ : out STD_LOGIC;
\douta[5]\ : out STD_LOGIC;
\douta[6]\ : out STD_LOGIC;
\douta[7]\ : out STD_LOGIC;
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \rom_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\rom_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
Q(0) => Q(0),
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[0]\ => \douta[0]\,
\douta[1]\ => \douta[1]\,
\douta[2]\ => \douta[2]\,
\douta[3]\ => \douta[3]\,
\douta[4]\ => \douta[4]\,
\douta[5]\ => \douta[5]\,
\douta[6]\ => \douta[6]\,
\douta[7]\ => \douta[7]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_width__parameterized5\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \rom_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\rom_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \rom_blk_mem_gen_prim_width__parameterized6\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ram_ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \rom_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \rom_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \rom_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\rom_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
ram_ena => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end rom_blk_mem_gen_generic_cstr;
architecture STRUCTURE of rom_blk_mem_gen_generic_cstr is
signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_ena : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
begin
\bindec_a.bindec_inst_a\: entity work.rom_bindec
port map (
addra(3 downto 0) => addra(14 downto 11),
ram_ena => ram_ena
);
\has_mux_a.A\: entity work.rom_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[2].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[2].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[2].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[2].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[2].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[2].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[1].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_10\ => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7 downto 0) => ram_douta(7 downto 0),
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_4\ => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_5\ => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_6\ => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_7\ => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_8\ => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_9\ => \ramloop[5].ram.r_n_6\,
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
Q(0) => sel_pipe(1),
addra(3 downto 0) => addra(14 downto 11),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
\ramloop[0].ram.r\: entity work.rom_blk_mem_gen_prim_width
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7 downto 0) => ram_douta(7 downto 0)
);
\ramloop[1].ram.r\: entity work.\rom_blk_mem_gen_prim_width__parameterized0\
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7) => \ramloop[1].ram.r_n_0\,
\douta[7]\(6) => \ramloop[1].ram.r_n_1\,
\douta[7]\(5) => \ramloop[1].ram.r_n_2\,
\douta[7]\(4) => \ramloop[1].ram.r_n_3\,
\douta[7]\(3) => \ramloop[1].ram.r_n_4\,
\douta[7]\(2) => \ramloop[1].ram.r_n_5\,
\douta[7]\(1) => \ramloop[1].ram.r_n_6\,
\douta[7]\(0) => \ramloop[1].ram.r_n_7\
);
\ramloop[2].ram.r\: entity work.\rom_blk_mem_gen_prim_width__parameterized1\
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7) => \ramloop[2].ram.r_n_0\,
\douta[7]\(6) => \ramloop[2].ram.r_n_1\,
\douta[7]\(5) => \ramloop[2].ram.r_n_2\,
\douta[7]\(4) => \ramloop[2].ram.r_n_3\,
\douta[7]\(3) => \ramloop[2].ram.r_n_4\,
\douta[7]\(2) => \ramloop[2].ram.r_n_5\,
\douta[7]\(1) => \ramloop[2].ram.r_n_6\,
\douta[7]\(0) => \ramloop[2].ram.r_n_7\
);
\ramloop[3].ram.r\: entity work.\rom_blk_mem_gen_prim_width__parameterized2\
port map (
DOADO(7) => \ramloop[3].ram.r_n_0\,
DOADO(6) => \ramloop[3].ram.r_n_1\,
DOADO(5) => \ramloop[3].ram.r_n_2\,
DOADO(4) => \ramloop[3].ram.r_n_3\,
DOADO(3) => \ramloop[3].ram.r_n_4\,
DOADO(2) => \ramloop[3].ram.r_n_5\,
DOADO(1) => \ramloop[3].ram.r_n_6\,
DOADO(0) => \ramloop[3].ram.r_n_7\,
addra(14 downto 0) => addra(14 downto 0),
clka => clka
);
\ramloop[4].ram.r\: entity work.\rom_blk_mem_gen_prim_width__parameterized3\
port map (
DOADO(7) => \ramloop[4].ram.r_n_0\,
DOADO(6) => \ramloop[4].ram.r_n_1\,
DOADO(5) => \ramloop[4].ram.r_n_2\,
DOADO(4) => \ramloop[4].ram.r_n_3\,
DOADO(3) => \ramloop[4].ram.r_n_4\,
DOADO(2) => \ramloop[4].ram.r_n_5\,
DOADO(1) => \ramloop[4].ram.r_n_6\,
DOADO(0) => \ramloop[4].ram.r_n_7\,
addra(14 downto 0) => addra(14 downto 0),
clka => clka
);
\ramloop[5].ram.r\: entity work.\rom_blk_mem_gen_prim_width__parameterized4\
port map (
DOADO(7) => \ramloop[4].ram.r_n_0\,
DOADO(6) => \ramloop[4].ram.r_n_1\,
DOADO(5) => \ramloop[4].ram.r_n_2\,
DOADO(4) => \ramloop[4].ram.r_n_3\,
DOADO(3) => \ramloop[4].ram.r_n_4\,
DOADO(2) => \ramloop[4].ram.r_n_5\,
DOADO(1) => \ramloop[4].ram.r_n_6\,
DOADO(0) => \ramloop[4].ram.r_n_7\,
Q(0) => sel_pipe(1),
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[0]\ => \ramloop[5].ram.r_n_0\,
\douta[1]\ => \ramloop[5].ram.r_n_1\,
\douta[2]\ => \ramloop[5].ram.r_n_2\,
\douta[3]\ => \ramloop[5].ram.r_n_3\,
\douta[4]\ => \ramloop[5].ram.r_n_4\,
\douta[5]\ => \ramloop[5].ram.r_n_5\,
\douta[6]\ => \ramloop[5].ram.r_n_6\,
\douta[7]\ => \ramloop[5].ram.r_n_7\
);
\ramloop[6].ram.r\: entity work.\rom_blk_mem_gen_prim_width__parameterized5\
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
\douta[7]\(7) => \ramloop[6].ram.r_n_0\,
\douta[7]\(6) => \ramloop[6].ram.r_n_1\,
\douta[7]\(5) => \ramloop[6].ram.r_n_2\,
\douta[7]\(4) => \ramloop[6].ram.r_n_3\,
\douta[7]\(3) => \ramloop[6].ram.r_n_4\,
\douta[7]\(2) => \ramloop[6].ram.r_n_5\,
\douta[7]\(1) => \ramloop[6].ram.r_n_6\,
\douta[7]\(0) => \ramloop[6].ram.r_n_7\
);
\ramloop[7].ram.r\: entity work.\rom_blk_mem_gen_prim_width__parameterized6\
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
\douta[7]\(7) => \ramloop[7].ram.r_n_0\,
\douta[7]\(6) => \ramloop[7].ram.r_n_1\,
\douta[7]\(5) => \ramloop[7].ram.r_n_2\,
\douta[7]\(4) => \ramloop[7].ram.r_n_3\,
\douta[7]\(3) => \ramloop[7].ram.r_n_4\,
\douta[7]\(2) => \ramloop[7].ram.r_n_5\,
\douta[7]\(1) => \ramloop[7].ram.r_n_6\,
\douta[7]\(0) => \ramloop[7].ram.r_n_7\,
ram_ena => ram_ena
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_blk_mem_gen_top : entity is "blk_mem_gen_top";
end rom_blk_mem_gen_top;
architecture STRUCTURE of rom_blk_mem_gen_top is
begin
\valid.cstr\: entity work.rom_blk_mem_gen_generic_cstr
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_blk_mem_gen_v8_3_1_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end rom_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of rom_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.rom_blk_mem_gen_top
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of rom_blk_mem_gen_v8_3_1 : entity is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of rom_blk_mem_gen_v8_3_1 : entity is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of rom_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of rom_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of rom_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of rom_blk_mem_gen_v8_3_1 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of rom_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of rom_blk_mem_gen_v8_3_1 : entity is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of rom_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of rom_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of rom_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of rom_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 2.252613 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of rom_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of rom_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of rom_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of rom_blk_mem_gen_v8_3_1 : entity is "rom.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of rom_blk_mem_gen_v8_3_1 : entity is "rom.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of rom_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of rom_blk_mem_gen_v8_3_1 : entity is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of rom_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of rom_blk_mem_gen_v8_3_1 : entity is 30720;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of rom_blk_mem_gen_v8_3_1 : entity is 30720;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of rom_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of rom_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of rom_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of rom_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of rom_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of rom_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of rom_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of rom_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of rom_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of rom_blk_mem_gen_v8_3_1 : entity is 30720;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of rom_blk_mem_gen_v8_3_1 : entity is 30720;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of rom_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of rom_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of rom_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of rom_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of rom_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of rom_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of rom_blk_mem_gen_v8_3_1 : entity is "yes";
end rom_blk_mem_gen_v8_3_1;
architecture STRUCTURE of rom_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.rom_blk_mem_gen_v8_3_1_synth
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
douta(7 downto 0) => douta(7 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity rom is
port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of rom : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of rom : entity is "rom,blk_mem_gen_v8_3_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of rom : entity is "rom,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=rom.mif,C_INIT_FILE=rom.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=30720,C_READ_DEPTH_A=30720,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=30720,C_READ_DEPTH_B=30720,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.252613 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of rom : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of rom : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end rom;
architecture STRUCTURE of rom is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "7";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.252613 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "rom.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "rom.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 30720;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 30720;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 30720;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 30720;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.rom_blk_mem_gen_v8_3_1
port map (
addra(14 downto 0) => addra(14 downto 0),
addrb(14 downto 0) => B"000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => B"00000000",
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(14 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(14 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(14 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(14 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
|
mit
|
44a06412805766cd808adfe6895f5d07
| 0.72342 | 3.697406 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_range.vhd
| 2 | 2,304 |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_range_pkg.all;
entity range_entity is
port (gen_vals: in std_logic);
end range_entity;
architecture test of range_entity is
type int_array is array (integer range <>) of integer;
signal ascending : int_array(2 to 4);
signal descending : int_array(9 downto 3);
signal ascending_rev : int_array(8 to 13);
signal descending_rev : int_array(15 downto 10);
signal range_pow : int_array(2**4 downto 0);
signal range_rem : int_array(8 rem 3 downto 0);
signal left_asc, right_asc, left_dsc, right_dsc, pow_left, rem_left : integer;
-- There is no limited ranged integer in SystemVerilog, so just see if it compiles
signal int_asc : integer_asc;
signal int_desc : integer_desc;
begin
process(gen_vals) begin
left_asc <= ascending'left;
right_asc <= ascending'right;
left_dsc <= descending'left;
right_dsc <= descending'right;
pow_left <= range_pow'left;
rem_left <= range_rem'left;
-- 'range test
for i in ascending'range loop
ascending(i) <= i * 2;
end loop;
for i in descending'range loop
descending(i) <= i * 3;
end loop;
-- 'reverse_range test
for i in ascending_rev'reverse_range loop
ascending_rev(i) <= i * 4;
end loop;
for i in descending_rev'reverse_range loop
descending_rev(i) <= i * 5;
end loop;
end process;
end test;
|
gpl-2.0
|
7f02dcc174ba46716ed32ef19ab5a0e9
| 0.691406 | 3.657143 | false | true | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_if_pkg.vhd
| 4 | 2,156 |
-------------------------------------------------------------------------------
-- Filename: ac97_if_pkg.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package ac97_if_pkg is
constant AC97_CMD_LENGTH : integer := 25;
-- Command format V R AAAAAAA DDDDDDDD DDDDDDDD
-- V = Valid command (1 = valid, 0 = invalid)
-- R = Read (1=read, 0=write)
-- A = Address (7 bits)
-- D = Data (16 bits)
-- Write 0x0 to 0x0 (reset registers)
constant RESET_REGISTERS_CMD :
std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"000000";
-- Write 0x808 to 0x2 (master volume 0db gain)
constant MASTER_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"020808";
-- Write 0x808 to 0x4 (headphone vol)
constant HEADPHONE_VOLUME_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"040808";
-- Write 0x8000 to 0xa (mute PC beep)
constant MUTE_PC_BEEP_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"0a8000";
-- Write 0x808 to 0x18 pcmoutvol (amp out line)
constant PCMOUT_VOLUME_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"180808";
-- Write 0x404 to 0x1a record source (line in for left and right)
constant RECORD_SOURCE_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1a0404";
-- Write (0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
constant RECORD_GAIN_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '1' & X"1c0008";
constant EMPTY_CMD : std_logic_vector(AC97_CMD_LENGTH-1 downto 0)
:= '0' & X"000000";
end ac97_if_pkg;
package body ac97_if_pkg is
end ac97_if_pkg;
|
gpl-3.0
|
366dc71fd47e5796dc9c1464c8e8fa00
| 0.521336 | 3.208333 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_test3.vhd
| 2 | 1,110 |
--
-- Author: Pawel Szostek ([email protected])
-- Date: 28.07.2011
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dummy is
port (clk : in std_logic;
input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(15 downto 0)
);
end;
architecture behaviour of dummy is
begin
L: process(clk)
variable one : integer; -- mix integers and unsigned
variable a : unsigned (6 downto 0); --
variable b,c,d : unsigned(6 downto 0);
begin
if(clk'event and clk = '1') then
--do some mess around..
a(3 downto 0) := unsigned(input);
a(6 downto 4) := "000";
one := 1;
b := a + one; --unsigned plus integer
b := a + 1; --variable plus constant integer
c := a + a; --
c := c - b; --two assignments in a row to the same variable
d := c + 2;
output(6 downto 0) <= std_logic_vector(d); --signal assignment
output(15 downto 7) <= (others => '0');
end if;
end process;
end;
|
gpl-2.0
|
eec642ec9f12cd069ca1d626a5c3ae58
| 0.538739 | 3.651316 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl
| 1 | 105,072 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri Jun 3 00:16:36 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl
-- Design : FrameBuffer
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
ena : in STD_LOGIC;
clka : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end FrameBuffer_blk_mem_gen_mux;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_mux is
signal \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\ : label is "soft_lutpair0";
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(0),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
O => douta(0)
);
\douta[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(1),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
O => douta(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(2),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
O => douta(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(3),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
O => douta(3)
);
\douta[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(4),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
O => douta(4)
);
\douta[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(5),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
O => douta(5)
);
\douta[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(6),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
O => douta(6)
);
\douta[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOADO(7),
I1 => sel_pipe(0),
I2 => sel_pipe(1),
I3 => sel_pipe(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
O => douta(7)
);
\no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => addra(0),
I1 => ena,
I2 => sel_pipe(0),
O => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => addra(1),
I1 => ena,
I2 => sel_pipe(1),
O => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => addra(2),
I1 => ena,
I2 => sel_pipe(2),
O => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\,
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\,
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\,
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 2 downto 0 );
clkb : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \FrameBuffer_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC;
signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\ : STD_LOGIC;
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\doutb[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(0),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0),
O => doutb(0)
);
\doutb[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(1),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1),
O => doutb(1)
);
\doutb[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(2),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2),
O => doutb(2)
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(3),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3),
O => doutb(3)
);
\doutb[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(4),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4),
O => doutb(4)
);
\doutb[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(5),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5),
O => doutb(5)
);
\doutb[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(6),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6),
O => doutb(6)
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF020F02F00200"
)
port map (
I0 => DOBDO(7),
I1 => sel_pipe_d1(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7),
O => doutb(7)
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\,
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(0),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(1),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\,
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(2),
Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_wrapper_init is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end FrameBuffer_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202B80",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"802B202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"4646464646464646464646464646464646464620202020202020202020202B2B",
INIT_06 => X"4720202020202020202020205050505050505050505050505050505050464646",
INIT_07 => X"2020414141202020202020202020202020202020474747474747474747474747",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2B2B202020202020202020202047474747474747474747474747202020202020",
INIT_0A => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020",
INIT_0B => X"3A47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A",
INIT_0C => X"20413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A474747202020",
INIT_0F => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020",
INIT_10 => X"3A3A3A3A474720202020503A3A3A3A3A5050505050503A3A3A3A3A3A50463A3A",
INIT_11 => X"413A3A3A3A3A4120202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A3A3A3A474720",
INIT_14 => X"3A3A4646464646464646463A3A3A3A3A3A464620202020202020202020202020",
INIT_15 => X"473A3A3A3A3A472020503A3A3A3A3A502020202020503A3A3A3A3A5050463A3A",
INIT_16 => X"3A3A3A3A3A3A3A41202020202020202020202020473A3A3A3A47474747474747",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202041",
INIT_18 => X"20202020202020202020202020473A3A3A3A47474747474747473A3A3A3A3A47",
INIT_19 => X"46464620202020202020463A3A3A3A3A46202020202020202020202020202020",
INIT_1A => X"20473A3A3A3A3A4720503A3A3A3A3A502020202020503A3A3A3A502020464646",
INIT_1B => X"3A3A3A3A3A3A3A3A412020202020202020202020474747474747202020202020",
INIT_1C => X"472020202020202020202020202020202020202020202020202020202020413A",
INIT_1D => X"2020202020202020202020202047474747474720202020202020473A3A3A3A3A",
INIT_1E => X"20202020202020202020463A3A3A3A3A46202020202020202020202020202020",
INIT_1F => X"2020473A3A3A3A3A47503A3A3A3A3A502020202020503A3A3A3A502020202020",
INIT_20 => X"3A3A3A413A3A3A3A3A4120202020202020202020202020202020202020202020",
INIT_21 => X"3A47202020202020202020202020202020202020202020202020202020413A3A",
INIT_22 => X"202020202020202020202020202020202020202020202020202020473A3A3A3A",
INIT_23 => X"464646464646464646463A3A3A3A3A3A46202020202020202020202020202020",
INIT_24 => X"2020473A3A3A3A3A4720503A3A3A3A3A5050505050503A3A3A3A502020202020",
INIT_25 => X"3A3A4120413A3A3A3A3A41202020202020202020202020202020202020202020",
INIT_26 => X"3A472020202020202020202020202020202020202020202020202020413A3A3A",
INIT_27 => X"202020202020202020202020202020202020202020202020202020473A3A3A3A",
INIT_28 => X"463A3A3A3A3A3A3A3A3A3A3A3A3A3A3A46202020202020202020202020202020",
INIT_29 => X"2020473A3A3A3A3A47202050503A3A3A3A3A3A3A3A3A3A3A3A3A502020202020",
INIT_2A => X"3A41202020413A3A3A3A3A412020202020202020474747474747474747472020",
INIT_2B => X"3A47202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D202020202020202020413A3A3A3A",
INIT_2C => X"202020202020202020202020204747474747474747474720202020473A3A3A3A",
INIT_2D => X"463A3A3A3A3A3A3A3A3A3A3A3A3A3A3A46202020202020202020202020202020",
INIT_2E => X"2020473A3A3A3A3A47202020205050505050505050503A3A3A3A502020202020",
INIT_2F => X"412020202020413A3A3A3A3A4120202020202020473A3A3A3A3A3A3A3A472020",
INIT_30 => X"3A47202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D2020202020202020413A3A3A3A3A",
INIT_31 => X"20202020202020202020202020473A3A3A3A3A3A3A3A4720202020473A3A3A3A",
INIT_32 => X"464646464646464646463A3A3A3A3A3A46202020202020202020202020202020",
INIT_33 => X"2020473A3A3A3A3A47202020202020202020202020503A3A3A3A502020202020",
INIT_34 => X"41414141414141413A3A3A3A3A41202020202020473A3A3A3A47474747472020",
INIT_35 => X"3A47202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020202020413A3A3A3A3A41",
INIT_36 => X"20202020202020202020202020473A3A3A3A474747474720202020473A3A3A3A",
INIT_37 => X"20202020202020202020463A3A3A3A3A46202020202020202020202020202020",
INIT_38 => X"2020473A3A3A3A3A47202020202020202020202020503A3A3A3A502020202020",
INIT_39 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A412020202020473A3A3A3A47202020202020",
INIT_3A => X"3A4720202020202020202020202020202020202020202020413A3A3A3A3A3A3A",
INIT_3B => X"20202020202020202020202020473A3A3A3A472020202020202020473A3A3A3A",
INIT_3C => X"20202020202020202020463A3A3A3A3A46202020202020202020202020202020",
INIT_3D => X"20473A3A3A3A3A4720202020202020202020202020503A3A3A3A502020202020",
INIT_3E => X"414141414141414141413A3A3A3A3A4120202020473A3A3A3A47202020202020",
INIT_3F => X"4720202020202020202020202020202020202020202020413A3A3A3A3A414141",
INIT_40 => X"20202020202020202020202020473A3A3A3A4720202020202020473A3A3A3A3A",
INIT_41 => X"202020202020202046463A3A3A3A3A3A3A464620202020202020202020202020",
INIT_42 => X"473A3A3A3A3A4720202020202020202020202050503A3A3A3A3A3A5050202020",
INIT_43 => X"20202020202020202020413A3A3A3A3A41202020473A3A3A3A47474747474747",
INIT_44 => X"20202020202020202020202020202020202020202020413A3A3A3A3A41202020",
INIT_45 => X"20202020202020202020202020473A3A3A3A47474747474747473A3A3A3A3A47",
INIT_46 => X"202020202020202046463A3A3A3A3A3A3A3A4620202020202020202020202020",
INIT_47 => X"3A3A3A3A474720202020202020202020202020503A3A3A3A3A3A3A3A50202020",
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INIT_4C => X"3A474747202020202020202020202020202020503A3A3A3A3A3A3A3A50202020",
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INIT_4E => X"2020202020202020202020202020202020202020413A3A3A3A3A412020202020",
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INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => ena,
I1 => addra(12),
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => addrb(12),
I1 => addrb(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
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DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 8) => B"000000000000000000000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[7]\(7 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[7]\(7 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\,
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\,
ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(12),
I1 => ena,
I2 => addra(13),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => addrb(13),
I1 => addrb(12),
O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC;
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202B2B",
INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020",
INIT_3A => X"2B2B202020202020202020202020202020202020202020202020202020202020",
INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202B80",
INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020",
INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074",
INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073",
INIT_3F => X"802B202020202020202020202020202020202020202020202020202020202020",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(13 downto 3) => addra(10 downto 0),
ADDRARDADDR(2 downto 0) => B"000",
ADDRBWRADDR(13 downto 3) => addrb(10 downto 0),
ADDRBWRADDR(2 downto 0) => B"000",
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 8) => B"00000000",
DIBDI(7 downto 0) => dinb(7 downto 0),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\,
DOPBDOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1),
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\,
ENARDEN => ram_ena,
ENBWREN => ram_enb,
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => addra(12),
I1 => addra(11),
I2 => addra(13),
I3 => ena,
O => ram_ena
);
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addrb(11),
I1 => addrb(13),
I2 => addrb(12),
O => ram_enb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_prim_width is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end FrameBuffer_blk_mem_gen_prim_width;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7 downto 0) => \douta[7]\(7 downto 0),
\doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(7 downto 0) => DOBDO(7 downto 0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end FrameBuffer_blk_mem_gen_generic_cstr;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is
signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_9\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_10\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_11\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_12\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_13\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_14\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_15\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_9\ : STD_LOGIC;
begin
\has_mux_a.A\: entity work.FrameBuffer_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_douta(7 downto 0),
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
addra(2 downto 0) => addra(13 downto 11),
clka => clka,
douta(7 downto 0) => douta(7 downto 0),
ena => ena
);
\has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_9\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_10\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_11\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_12\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_13\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_14\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_15\,
\DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0),
DOBDO(7) => \ramloop[2].ram.r_n_8\,
DOBDO(6) => \ramloop[2].ram.r_n_9\,
DOBDO(5) => \ramloop[2].ram.r_n_10\,
DOBDO(4) => \ramloop[2].ram.r_n_11\,
DOBDO(3) => \ramloop[2].ram.r_n_12\,
DOBDO(2) => \ramloop[2].ram.r_n_13\,
DOBDO(1) => \ramloop[2].ram.r_n_14\,
DOBDO(0) => \ramloop[2].ram.r_n_15\,
addrb(2 downto 0) => addrb(13 downto 11),
clkb => clkb,
doutb(7 downto 0) => doutb(7 downto 0)
);
\ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7 downto 0) => ram_douta(7 downto 0),
\doutb[7]\(7 downto 0) => ram_doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
\douta[7]\(7) => \ramloop[1].ram.r_n_0\,
\douta[7]\(6) => \ramloop[1].ram.r_n_1\,
\douta[7]\(5) => \ramloop[1].ram.r_n_2\,
\douta[7]\(4) => \ramloop[1].ram.r_n_3\,
\douta[7]\(3) => \ramloop[1].ram.r_n_4\,
\douta[7]\(2) => \ramloop[1].ram.r_n_5\,
\douta[7]\(1) => \ramloop[1].ram.r_n_6\,
\douta[7]\(0) => \ramloop[1].ram.r_n_7\,
\doutb[7]\(7) => \ramloop[1].ram.r_n_8\,
\doutb[7]\(6) => \ramloop[1].ram.r_n_9\,
\doutb[7]\(5) => \ramloop[1].ram.r_n_10\,
\doutb[7]\(4) => \ramloop[1].ram.r_n_11\,
\doutb[7]\(3) => \ramloop[1].ram.r_n_12\,
\doutb[7]\(2) => \ramloop[1].ram.r_n_13\,
\doutb[7]\(1) => \ramloop[1].ram.r_n_14\,
\doutb[7]\(0) => \ramloop[1].ram.r_n_15\,
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\
port map (
DOADO(7) => \ramloop[2].ram.r_n_0\,
DOADO(6) => \ramloop[2].ram.r_n_1\,
DOADO(5) => \ramloop[2].ram.r_n_2\,
DOADO(4) => \ramloop[2].ram.r_n_3\,
DOADO(3) => \ramloop[2].ram.r_n_4\,
DOADO(2) => \ramloop[2].ram.r_n_5\,
DOADO(1) => \ramloop[2].ram.r_n_6\,
DOADO(0) => \ramloop[2].ram.r_n_7\,
DOBDO(7) => \ramloop[2].ram.r_n_8\,
DOBDO(6) => \ramloop[2].ram.r_n_9\,
DOBDO(5) => \ramloop[2].ram.r_n_10\,
DOBDO(4) => \ramloop[2].ram.r_n_11\,
DOBDO(3) => \ramloop[2].ram.r_n_12\,
DOBDO(2) => \ramloop[2].ram.r_n_13\,
DOBDO(1) => \ramloop[2].ram.r_n_14\,
DOBDO(0) => \ramloop[2].ram.r_n_15\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top";
end FrameBuffer_blk_mem_gen_top;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is
begin
\valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end FrameBuffer_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.61856 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes";
end FrameBuffer_blk_mem_gen_v8_3_1;
architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
ena => ena,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FrameBuffer is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of FrameBuffer : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end FrameBuffer;
architecture STRUCTURE of FrameBuffer is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 14;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 14;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.61856 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 10240;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 10240;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 10240;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 10240;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => dinb(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
|
mit
|
140c8c49bd4d3cbc1e9feac35f817f6c
| 0.688537 | 3.423433 | false | false | false | false |
luebbers/reconos
|
core/pcores/ppc405_v2_00_d/hdl/vhdl/ppc405_top.vhd
| 1 | 21,910 |
--
-- \file ppc405_top.vhd
--
-- PowerPC wrapper to connect CPU to OSIF
--
-- \author robert Meiche <[email protected]>
-- \date 22.09.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library ppc405_v2_00_c;
use ppc405_v2_00_c.all;
library dcr_v29_v1_00_a;
use dcr_v29_v1_00_a.all;
library cpu_osif_adapter_v1_04_a;
use cpu_osif_adapter_v1_04_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.ALL;
entity ppc405_top is
generic (
C_EXT_RESET_HIGH : integer := 1;
CPU_USE_OTHER_CLK : integer := 0;
CPU_RESET_CYCLES : integer := 8;
CPU_MMU_ENABLE : integer := 1;
CPU_DCR_RESYNC : integer := 0;
C_BOOT_SECT_DATA : std_logic_vector := X"4bffd004"
);
port (
clk : in std_logic; --clock from OSIF
cpu_clk : in std_logic; -- Other clock from extern. Configurable via generic
reset : in std_logic;
--signals to osif
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
--debug signals
debug_idle_state : out std_logic;
debug_busy_state : out std_logic;
debug_reconos_ready : out std_logic;
--signal to/from bram_logic
boot_sect_ready : in std_logic;
set_boot_sect : out std_logic;
boot_sect_data : out std_logic_vector(31 downto 0);
--CPU PLB ports
PLBCLK : in std_logic;
C405PLBICUABUS : out std_logic_vector(0 to 31);
C405PLBICUBE : out std_logic_vector(0 to 7);
C405PLBICURNW : out std_logic;
C405PLBICUABORT : out std_logic;
C405PLBICUBUSLOCK : out std_logic;
C405PLBICUU0ATTR : out std_logic;
C405PLBICUGUARDED : out std_logic;
C405PLBICULOCKERR : out std_logic;
C405PLBICUMSIZE : out std_logic_vector(0 to 1);
C405PLBICUORDERED : out std_logic;
C405PLBICUPRIORITY : out std_logic_vector(0 to 1);
C405PLBICURDBURST : out std_logic;
C405PLBICUREQUEST : out std_logic;
C405PLBICUSIZE : out std_logic_vector(0 to 3);
C405PLBICUTYPE : out std_logic_vector(0 to 2);
C405PLBICUWRBURST : out std_logic;
C405PLBICUWRDBUS : out std_logic_vector(0 to 63);
C405PLBICUCACHEABLE : out std_logic;
PLBC405ICUADDRACK : in std_logic;
PLBC405ICUBUSY : in std_logic;
PLBC405ICUERR : in std_logic;
PLBC405ICURDBTERM : in std_logic;
PLBC405ICURDDACK : in std_logic;
PLBC405ICURDDBUS : in std_logic_vector(0 to 63);
PLBC405ICURDWDADDR : in std_logic_vector(0 to 3);
PLBC405ICUREARBITRATE : in std_logic;
PLBC405ICUWRBTERM : in std_logic;
PLBC405ICUWRDACK : in std_logic;
PLBC405ICUSSIZE : in std_logic_vector(0 to 1);
PLBC405ICUSERR : in std_logic;
PLBC405ICUSBUSYS : in std_logic;
C405PLBDCUABUS : out std_logic_vector(0 to 31);
C405PLBDCUBE : out std_logic_vector(0 to 7);
C405PLBDCURNW : out std_logic;
C405PLBDCUSIZE2 : out std_logic;
C405PLBDCUABORT : out std_logic;
C405PLBDCUBUSLOCK : out std_logic;
C405PLBDCUU0ATTR : out std_logic;
C405PLBDCUGUARDED : out std_logic;
C405PLBDCULOCKERR : out std_logic;
C405PLBDCUMSIZE : out std_logic_vector(0 to 1);
C405PLBDCUORDERED : out std_logic;
C405PLBDCUPRIORITY : out std_logic_vector(0 to 1);
C405PLBDCURDBURST : out std_logic;
C405PLBDCUREQUEST : out std_logic;
C405PLBDCUSIZE : out std_logic_vector(0 to 3);
C405PLBDCUTYPE : out std_logic_vector(0 to 2);
C405PLBDCUWRBURST : out std_logic;
C405PLBDCUWRDBUS : out std_logic_vector(0 to 63);
C405PLBDCUCACHEABLE : out std_logic;
C405PLBDCUWRITETHRU : out std_logic;
PLBC405DCUADDRACK : in std_logic;
PLBC405DCUBUSY : in std_logic;
PLBC405DCUERR : in std_logic;
PLBC405DCURDBTERM : in std_logic;
PLBC405DCURDDACK : in std_logic;
PLBC405DCURDDBUS : in std_logic_vector(0 to 63);
PLBC405DCURDWDADDR : in std_logic_vector(0 to 3);
PLBC405DCUREARBITRATE : in std_logic;
PLBC405DCUWRBTERM : in std_logic;
PLBC405DCUWRDACK : in std_logic;
PLBC405DCUSSIZE : in std_logic_vector(0 to 1);
PLBC405DCUSERR : in std_logic;
PLBC405DCUSBUSYS : in std_logic;
--OCM
BRAMDSOCMCLK : in std_logic;
BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31);
DSARCVALUE : in std_logic_vector(0 to 7);
DSCNTLVALUE : in std_logic_vector(0 to 7);
DSOCMBRAMABUS : out std_logic_vector(8 to 29);
DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3);
DSOCMBRAMEN : out std_logic;
DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
DSOCMBUSY : out std_logic;
BRAMISOCMCLK : in std_logic;
BRAMISOCMRDDBUS : in std_logic_vector(0 to 63);
ISARCVALUE : in std_logic_vector(0 to 7);
ISCNTLVALUE : in std_logic_vector(0 to 7);
ISOCMBRAMEN : out std_logic;
ISOCMBRAMEVENWRITEEN : out std_logic;
ISOCMBRAMODDWRITEEN : out std_logic;
ISOCMBRAMRDABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
--CPU JTAG Interface
C405JTGCAPTUREDR : out std_logic;
C405JTGEXTEST : out std_logic;
C405JTGPGMOUT : out std_logic;
C405JTGSHIFTDR : out std_logic;
C405JTGTDO : out std_logic;
C405JTGTDOEN : out std_logic;
C405JTGUPDATEDR : out std_logic;
MCBJTAGEN : in std_logic;
JTGC405BNDSCANTDO : in std_logic;
JTGC405TCK : in std_logic;
JTGC405TDI : in std_logic;
JTGC405TMS : in std_logic;
JTGC405TRSTNEG : in std_logic
);
end ppc405_top;
architecture structural of ppc405_top is
--constants for DCR
constant C_DCR_AWIDTH : integer := 10;
constant C_DCR_DWIDTH : integer := 32;
--constants for OSIF_ADAPTER
constant COMMANDREG_WIDTH : integer := 5;
constant DATAREG_WIDTH : integer := 32;
constant DONEREG_WIDTH : integer := 1;
constant CPU_DWIDTH : integer := 32;
--BOOTCODE for CPU_Start
--constant C_BOOT_SECT_DATA : std_logic_vector := X"4bffd004";--X"4bffd004";--X"4bfffff0";X"48000000";
--signals --------------------------------------------------------------------
---CPU_DCR -> CPU_HWT_DCR
signal CPU_C405DCRABUS : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal CPU_C405DCRDBUSOUT: std_logic_vector(0 to C_DCR_DWIDTH-1);
signal CPU_DCRC405DBUSIN : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal CPU_C405DCRREAD : std_logic;
signal CPU_C405DCRWRITE : std_logic;
signal CPU_DCRC405ACK : std_logic;
---OSIF_ADPTER -> CPU_HWT_DCR
signal o_dcrDBus : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal i_dcrABus : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal i_dcrDBus : std_logic_vector(0 to C_DCR_DWIDTH-1);
---Connect Ack, Read, Write to DCR
signal o_dcrAck_vec : std_logic_vector(0 to 0);
signal i_dcrRead_vec : std_logic_vector(0 to 0);
signal i_dcrWrite_vec : std_logic_vector(0 to 0);
---OSIF_ADAPTER -> PPC
signal cpu_reset : std_logic;
--OSIF_FLAT / Reset / busylocal
signal o_osif_flat_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal i_osif_flat_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal busy_local : std_logic;
signal i_reset : std_logic;
--clk signal for PowerPC
signal ppc_clk : std_logic;
--CPU signals which are not used
signal CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405TIMERCLKEN, CPMC405TIMERTICK, MCBCPUCLKEN, MCBTIMEREN, MCPPCRST : std_logic;
signal CPMC405CORECLKINACTIVE, RSTC405RESETCHIP, RSTC405RESETSYS : std_logic;
signal C405CPMCORESLEEPREQ,C405CPMMSRCE,C405CPMMSREE,C405CPMTIMERIRQ,C405CPMTIMERRESETREQ,C405XXXMACHINECHECK : std_logic;
signal EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ : std_logic;
signal C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT : std_logic;
signal C405DBGWBIAR : std_logic_vector(0 to 29);
--other sigs
signal net_vcc0 : std_logic;
begin
--other sigs
net_vcc0 <= '1';
--Processess for the GENERICS ---------------------------------------------------
--C_EXT_RESET_HIGH
RSTPROCESS: process(reset)
begin
if C_EXT_RESET_HIGH = 1 then
i_reset <= reset;
else
i_reset <= not reset;
end if;
end process;
--CPU_USE_OTHER_CLK :
--if 1 then use port cpu_clk otherwise use threadclk_port clk
CPU_CLK_PROCESS: process(clk, cpu_clk)
begin
if CPU_USE_OTHER_CLK = 1 then
ppc_clk <= cpu_clk;
else
ppc_clk <= clk;
end if;
end process;
--Process and assignments for OSIF ----------------------------------------------
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
-- overlay busy with local busy signal
--i_osif <= to_osif_os2task_t(i_osif_flat_i);
i_osif <= to_osif_os2task_t(i_osif_flat_i or (X"0000000000" & busy_local & "000000"));
register_osif_ports_proc: process(clk)
begin
if rising_edge(clk) then
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
end if;
end process;
-- infer latch for local busy signal
-- needed for asynchronous communication between thread and OSIF
busy_local_gen : process(i_reset, o_osif.request, i_osif.ack)
begin
if i_reset = '1' then
busy_local <= '0';
elsif o_osif.request = '1' then
busy_local <= '1';
elsif i_osif.ack = '1' then
busy_local <= '0';
end if;
end process;
--------- COMPONENTS ------------------------------------------------------------
cpu_osif_adapter_i : entity cpu_osif_adapter_v1_04_a.cpu_osif_adapter
generic map (
C_BASEADDR => B"0000011000",
C_HIGHADDR => B"0000011111",
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
COMMANDREG_WIDTH => COMMANDREG_WIDTH,
DATAREG_WIDTH => DATAREG_WIDTH,
DONEREG_WIDTH => DONEREG_WIDTH,
CPU_RESET_CYCLES => CPU_RESET_CYCLES,
CPU_DWIDTH => CPU_DWIDTH,
C_BOOT_SECT_DATA => C_BOOT_SECT_DATA
)
port map (
clk => clk,
reset => i_reset,
--dcr signals for Main CPU
o_dcrAck => o_dcrAck_vec(0),
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead_vec(0),
i_dcrWrite => i_dcrWrite_vec(0),
--signals to osif
i_osif => i_osif,
o_osif => o_osif,
cpu_reset => cpu_reset,
--debug signals
debug_idle_state => debug_idle_state,
debug_busy_state => debug_busy_state,
debug_reconos_ready => debug_reconos_ready,
--signal to/from bram_logic
boot_sect_ready => boot_sect_ready,
set_boot_sect => set_boot_sect,
boot_sect_data => boot_sect_data
);
CPU_HWT_DCR_BUS : entity dcr_v29_v1_00_a.dcr_v29
generic map (
C_DCR_NUM_SLAVES => 1,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_USE_LUT_OR => 1
)
port map (
M_dcrABus => CPU_C405DCRABUS,
M_dcrDBus => CPU_C405DCRDBUSOUT,
M_dcrRead => CPU_C405DCRREAD,
M_dcrWrite => CPU_C405DCRWRITE,
DCR_M_DBus => CPU_DCRC405DBUSIN,
DCR_Ack => CPU_DCRC405ACK,
DCR_ABus => i_dcrABus,
DCR_Sl_DBus => i_dcrDBus,
DCR_Read => i_dcrRead_vec,
DCR_Write => i_dcrWrite_vec,
Sl_dcrDBus => o_dcrDBus,
Sl_dcrAck => o_dcrAck_vec
);
CPU_HWT : entity ppc405_v2_00_c.ppc405_top
generic map (
C_ISOCM_DCR_BASEADDR => B"0000010000",
C_ISOCM_DCR_HIGHADDR => B"0000010011",
C_DSOCM_DCR_BASEADDR => B"0000100000",
C_DSOCM_DCR_HIGHADDR => B"0000100011",
C_DISABLE_OPERAND_FORWARDING => 1,
C_DETERMINISTIC_MULT => 0,
C_MMU_ENABLE => CPU_MMU_ENABLE,
C_DCR_RESYNC => CPU_DCR_RESYNC
)
port map (
CPMC405CLOCK => ppc_clk,
DCRCLK => clk,
C405RSTCHIPRESETREQ => open,
C405RSTCORERESETREQ => open,
C405RSTSYSRESETREQ => open,
RSTC405RESETCHIP => '0',--RSTC405RESETCHIP,
RSTC405RESETCORE => cpu_reset,
RSTC405RESETSYS => '0',--RSTC405RESETSYS,
--PLB signals
PLBCLK => PLBCLK,
C405PLBICUABUS => C405PLBICUABUS,
C405PLBICUBE => C405PLBICUBE,
C405PLBICURNW => C405PLBICURNW,
C405PLBICUABORT => C405PLBICUABORT,
C405PLBICUBUSLOCK => C405PLBICUBUSLOCK,
C405PLBICUU0ATTR => C405PLBICUU0ATTR,
C405PLBICUGUARDED => C405PLBICUGUARDED,
C405PLBICULOCKERR => C405PLBICULOCKERR,
C405PLBICUMSIZE => C405PLBICUMSIZE,
C405PLBICUORDERED => C405PLBICUORDERED,
C405PLBICUPRIORITY => C405PLBICUPRIORITY,
C405PLBICURDBURST => C405PLBICURDBURST,
C405PLBICUREQUEST => C405PLBICUREQUEST,
C405PLBICUSIZE => C405PLBICUSIZE,
C405PLBICUTYPE => C405PLBICUTYPE,
C405PLBICUWRBURST => C405PLBICUWRBURST,
C405PLBICUWRDBUS => C405PLBICUWRDBUS,
C405PLBICUCACHEABLE => C405PLBICUCACHEABLE,
PLBC405ICUADDRACK => PLBC405ICUADDRACK,
PLBC405ICUBUSY => PLBC405ICUBUSY,
PLBC405ICUERR => PLBC405ICUERR,
PLBC405ICURDBTERM => PLBC405ICURDBTERM,
PLBC405ICURDDACK => PLBC405ICURDDACK,
PLBC405ICURDDBUS => PLBC405ICURDDBUS,
PLBC405ICURDWDADDR => PLBC405ICURDWDADDR,
PLBC405ICUREARBITRATE => PLBC405ICUREARBITRATE,
PLBC405ICUWRBTERM => PLBC405ICUWRBTERM,
PLBC405ICUWRDACK => PLBC405ICUWRDACK,
PLBC405ICUSSIZE => PLBC405ICUSSIZE,
PLBC405ICUSERR => PLBC405ICUSERR,
PLBC405ICUSBUSYS => PLBC405ICUSBUSYS,
C405PLBDCUABUS => C405PLBDCUABUS,
C405PLBDCUBE => C405PLBDCUBE,
C405PLBDCURNW => C405PLBDCURNW,
C405PLBDCUABORT => C405PLBDCUABORT,
C405PLBDCUBUSLOCK => C405PLBDCUBUSLOCK,
C405PLBDCUU0ATTR => C405PLBDCUU0ATTR,
C405PLBDCUGUARDED => C405PLBDCUGUARDED,
C405PLBDCULOCKERR => C405PLBDCULOCKERR,
C405PLBDCUMSIZE => C405PLBDCUMSIZE,
C405PLBDCUORDERED => C405PLBDCUORDERED,
C405PLBDCUPRIORITY => C405PLBDCUPRIORITY,
C405PLBDCURDBURST => C405PLBDCURDBURST,
C405PLBDCUREQUEST => C405PLBDCUREQUEST,
C405PLBDCUSIZE => C405PLBDCUSIZE,
C405PLBDCUTYPE => C405PLBDCUTYPE,
C405PLBDCUWRBURST => C405PLBDCUWRBURST,
C405PLBDCUWRDBUS => C405PLBDCUWRDBUS,
C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE,
C405PLBDCUWRITETHRU => C405PLBDCUWRITETHRU,
PLBC405DCUADDRACK => PLBC405DCUADDRACK,
PLBC405DCUBUSY => PLBC405DCUBUSY,
PLBC405DCUERR => PLBC405DCUERR,
PLBC405DCURDBTERM => PLBC405DCURDBTERM,
PLBC405DCURDDACK => PLBC405DCURDDACK,
PLBC405DCURDDBUS => PLBC405DCURDDBUS,
PLBC405DCURDWDADDR => PLBC405DCURDWDADDR,
PLBC405DCUREARBITRATE => PLBC405DCUREARBITRATE,
PLBC405DCUWRBTERM => PLBC405DCUWRBTERM,
PLBC405DCUWRDACK => PLBC405DCUWRDACK,
PLBC405DCUSSIZE => PLBC405DCUSSIZE,
PLBC405DCUSERR => PLBC405DCUSERR,
PLBC405DCUSBUSYS => PLBC405DCUSBUSYS,
--ocm signals
BRAMDSOCMCLK => BRAMDSOCMCLK,
BRAMDSOCMRDDBUS => BRAMDSOCMRDDBUS,
DSARCVALUE => DSARCVALUE,
DSCNTLVALUE => DSCNTLVALUE,
DSOCMBRAMABUS => DSOCMBRAMABUS,
DSOCMBRAMBYTEWRITE => DSOCMBRAMBYTEWRITE,
DSOCMBRAMEN => DSOCMBRAMEN,
DSOCMBRAMWRDBUS => DSOCMBRAMWRDBUS,
DSOCMBUSY => DSOCMBUSY,
BRAMISOCMCLK => BRAMISOCMCLK,
BRAMISOCMRDDBUS => BRAMISOCMRDDBUS,
ISARCVALUE => ISARCVALUE,
ISCNTLVALUE => ISCNTLVALUE,
ISOCMBRAMEN => ISOCMBRAMEN,
ISOCMBRAMEVENWRITEEN => ISOCMBRAMEVENWRITEEN,
ISOCMBRAMODDWRITEEN => ISOCMBRAMODDWRITEEN,
ISOCMBRAMRDABUS => ISOCMBRAMRDABUS,
ISOCMBRAMWRABUS => ISOCMBRAMWRABUS,
ISOCMBRAMWRDBUS => ISOCMBRAMWRDBUS,
--DCR signals
C405DCRABUS => CPU_C405DCRABUS,
C405DCRDBUSOUT => CPU_C405DCRDBUSOUT,
C405DCRREAD => CPU_C405DCRREAD,
C405DCRWRITE => CPU_C405DCRWRITE,
DCRC405ACK => CPU_DCRC405ACK,
DCRC405DBUSIN => CPU_DCRC405DBUSIN,
-- JTAG Interface
C405JTGCAPTUREDR => C405JTGCAPTUREDR, -- O
C405JTGEXTEST => C405JTGEXTEST, -- O
C405JTGPGMOUT => C405JTGPGMOUT, -- O
C405JTGSHIFTDR => C405JTGSHIFTDR, -- O
C405JTGTDO => C405JTGTDO, -- O
C405JTGTDOEN => C405JTGTDOEN, -- O
C405JTGUPDATEDR => C405JTGUPDATEDR, -- O
MCBJTAGEN => net_vcc0,--MCBJTAGEN, -- I
JTGC405BNDSCANTDO => JTGC405BNDSCANTDO, -- I
JTGC405TCK => JTGC405TCK, -- I
JTGC405TDI => JTGC405TDI, -- I
JTGC405TMS => JTGC405TMS, -- I
JTGC405TRSTNEG => JTGC405TRSTNEG,
--Ports which are not used -----------------------------------------------
CPMC405CORECLKINACTIVE => '0',--CPMC405CORECLKINACTIVE, -- I
CPMC405CPUCLKEN => net_vcc0, --CPMC405CPUCLKEN, -- I
CPMC405JTAGCLKEN => net_vcc0, --CPMC405JTAGCLKEN, -- I
CPMC405TIMERCLKEN => net_vcc0, --CPMC405TIMERCLKEN, -- I
CPMC405TIMERTICK => net_vcc0, --CPMC405TIMERTICK, -- I
MCBCPUCLKEN => net_vcc0, --MCBCPUCLKEN, -- I
MCBTIMEREN => net_vcc0, --MCBTIMEREN, -- I
MCPPCRST => net_vcc0, --MCPPCRST,
C405CPMCORESLEEPREQ => C405CPMCORESLEEPREQ, -- O
C405CPMMSRCE => C405CPMMSRCE, -- O
C405CPMMSREE => C405CPMMSREE, -- O
C405CPMTIMERIRQ => C405CPMTIMERIRQ, -- O
C405CPMTIMERRESETREQ => C405CPMTIMERRESETREQ, -- O
C405XXXMACHINECHECK => C405XXXMACHINECHECK, -- O
-- Interrupt Controller Interface
EICC405CRITINPUTIRQ => '0',--EICC405CRITINPUTIRQ, -- I
EICC405EXTINPUTIRQ => '0',--EICC405EXTINPUTIRQ, -- I
-- Debug Interface
C405DBGMSRWE => C405DBGMSRWE, -- O
C405DBGSTOPACK => C405DBGSTOPACK, -- O
C405DBGWBCOMPLETE => C405DBGWBCOMPLETE, -- O
C405DBGWBFULL => C405DBGWBFULL, -- O
C405DBGWBIAR => C405DBGWBIAR, -- O [0:29]
DBGC405DEBUGHALT => '0',--DBGC405DEBUGHALT, -- I
DBGC405EXTBUSHOLDACK => '0',--DBGC405EXTBUSHOLDACK, -- I
DBGC405UNCONDDEBUGEVENT => '0',--DBGC405UNCONDDEBUGEVENT,
-- Trace Interface
C405TRCCYCLE => open , -- O
C405TRCEVENEXECUTIONSTATUS => open, -- O [0:1]
C405TRCODDEXECUTIONSTATUS => open, -- O [0:1]
C405TRCTRACESTATUS => open, -- O [0:3]
C405TRCTRIGGEREVENTOUT => open, -- O
C405TRCTRIGGEREVENTTYPE => open, -- O [0:10]
TRCC405TRACEDISABLE => '0', -- I
TRCC405TRIGGEREVENTIN => '0' -- I
);
end structural;
|
gpl-3.0
|
e65a4774415f632c3ca4085560fd511b
| 0.574213 | 4.140212 | false | false | false | false |
bzero/freezing-spice
|
src/pipeline.vhd
| 2 | 19,569 |
-------------------------------------------------------------------------------
-- Title : 5-stage RISCV integer pipeline
-- Project : Freezing Spice
-------------------------------------------------------------------------------
-- File : pipeline.vhd
-- Author : Tim Wawrzynczak
-- Created : 2015-07-07
-- Last update: 2015-07-28
-- Platform : FPGA
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: RV32I 5-stage ("classic MIPS") pipeline:
-- Instruction Fetch
-- Instruction Decode
-- Instruction Execute
-- Memory Access
-- Register File Writeback
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.common.all;
use work.if_pkg.all;
use work.id_pkg.all;
use work.ex_pkg.all;
entity pipeline is
generic (g_initial_pc : unsigned(31 downto 0) := (others => '0');
g_for_sim : boolean := false);
port (clk : in std_logic;
rst_n : in std_logic;
-- Instruction interface
insn_in : in word;
insn_valid : in std_logic;
insn_addr : out word;
-- Data interface
data_in : in word;
data_out : out word;
data_addr : out word;
data_write_en : out std_logic;
data_read_en : out std_logic;
data_in_valid : in std_logic);
end entity pipeline;
architecture Behavioral of pipeline is
-------------------------------------------------
-- IF signals
-------------------------------------------------
signal if_d : if_in;
signal if_q : if_out;
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
signal if_id_ir : word := (others => '0');
signal if_id_pc : word := (others => '0');
-------------------------------------------------
-- ID signals
-------------------------------------------------
signal id_d : id_in;
signal id_q : id_out;
signal rs1_data : word;
signal rs2_data : word;
-------------------------------------------------
-- ID/EX pipeline registers
-------------------------------------------------
signal id_ex_pc : word := (others => '0');
signal id_ex_rs1_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_rs2_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_op1 : word := (others => '0');
signal id_ex_op2 : word := (others => '0');
signal id_ex_ir : word := NOP;
signal id_ex_imm : word := (others => '0');
signal id_ex_insn_type : insn_type_t := OP_ILLEGAL;
signal id_ex_use_imm : std_logic := '0';
signal id_ex_alu_func : alu_func_t := ALU_NONE;
signal id_ex_branch_type : branch_type_t := BRANCH_NONE;
signal id_ex_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal id_ex_load_type : load_type_t := LOAD_NONE;
signal id_ex_store_type : store_type_t := STORE_NONE;
signal id_ex_rf_we : std_logic := '0';
-------------------------------------------------
-- EX signals
-------------------------------------------------
signal ex_d : ex_in;
signal ex_q : ex_out;
signal ex_rf_data : word;
signal ex_load_pc : std_logic;
signal ex_data_addr : word;
-------------------------------------------------
-- EX/MEM pipeline registers
-------------------------------------------------
signal ex_mem_load_pc : std_logic := '0';
signal ex_mem_next_pc : word := (others => '0');
signal ex_mem_rf_data : word := (others => '0');
signal ex_mem_return_addr : word := (others => '0');
signal ex_mem_load_type : load_type_t := LOAD_NONE;
signal ex_mem_store_type : store_type_t := STORE_NONE;
signal ex_mem_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal ex_mem_insn_type : insn_type_t := OP_ILLEGAL;
signal ex_mem_rf_we : std_logic := '0';
signal ex_mem_data_addr : word := (others => '0');
signal ex_mem_data_out : word := (others => '0');
-------------------------------------------------
-- MEM signals
-------------------------------------------------
signal mem_we : std_logic;
signal mem_re : std_logic;
signal mem_data_addr : word;
signal mem_data_out : word;
signal mem_lmd_lh : word;
signal mem_lmd_lb : word;
signal mem_lmd : word;
-------------------------------------------------
-- MEM/WB pipeline registers
-------------------------------------------------
signal mem_wb_rd_addr : std_logic_vector(4 downto 0) := (others => '0');
signal mem_wb_rf_we : std_logic := '0';
signal mem_wb_rf_data : word := (others => '0');
signal mem_wb_insn_type : insn_type_t := OP_ILLEGAL;
signal mem_wb_lmd : word := (others => '0');
-------------------------------------------------
-- WB signals
-------------------------------------------------
signal wb_rf_wr_addr : std_logic_vector(4 downto 0);
signal wb_rf_wr_en : std_logic;
signal wb_rf_wr_data : word;
-------------------------------------------------
-- Stalling
-------------------------------------------------
signal branch_stall : std_logic;
signal hazard_stall : std_logic;
signal if_kill : std_logic;
signal id_kill : std_logic;
signal id_stall : std_logic;
signal full_stall : std_logic;
begin -- architecture Behavioral
-------------------------------------------------
-- Drive module outputs
-------------------------------------------------
-- instruction interface
insn_addr <= if_q.fetch_addr;
-- memory interface
data_read_en <= mem_re;
data_write_en <= mem_we;
data_addr <= mem_data_addr;
data_out <= mem_data_out;
-------------------------------------------------
-- Detect when stalling is necessary
-------------------------------------------------
branch_stall <= '1' when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1')) else '0';
id_stall <= hazard_stall or branch_stall;
if_kill <= ex_mem_load_pc or (not insn_valid);
id_kill <= ex_mem_load_pc;
full_stall <= '1' when (ex_mem_insn_type = OP_LOAD and data_in_valid = '0') else '0';
-- Determine when to stall the pipeline because of structural hazards
hazard_stall <= '1' when (((id_ex_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (id_ex_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((ex_mem_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (ex_mem_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((mem_wb_rd_addr = id_q.rs1) and (id_q.rs1 /= "00000") and (mem_wb_rf_we = '1') and (id_q.rs1_rd = '1'))
or ((id_ex_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (id_ex_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((ex_mem_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (ex_mem_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((mem_wb_rd_addr = id_q.rs2) and (id_q.rs2 /= "00000") and (mem_wb_rf_we = '1') and (id_q.rs2_rd = '1'))
or ((ex_mem_insn_type = OP_LOAD) and (id_ex_rd_addr = id_q.rs1) and (id_ex_rd_addr /= "00000") and (id_q.rs1_rd = '1'))
or ((ex_mem_insn_type = OP_LOAD) and (id_ex_rd_addr = id_q.rs2) and (id_ex_rd_addr /= "00000") and (id_q.rs2_rd = '1')))
else '0';
---------------------------------------------------
-- Instruction fetch
---------------------------------------------------
-- inputs
if_d.stall <= ex_mem_load_pc or hazard_stall or branch_stall;
if_d.load_pc <= ex_mem_load_pc;
if_d.next_pc <= ex_mem_next_pc;
-- instantiation
if_stage : entity work.instruction_fetch(Behavioral)
port map (clk, rst_n, if_d, if_q);
-------------------------------------------------
-- IF/ID pipeline registers
-------------------------------------------------
if_id_reg_proc : process (clk, rst_n) is
begin -- process if_id_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
if_id_ir <= NOP;
if_id_pc <= (others => '0');
elsif (rising_edge(clk)) then
if (id_stall = '0' and full_stall = '0') then
if (if_kill = '1') then
if_id_ir <= NOP;
else
if_id_ir <= insn_in;
end if;
if_id_pc <= if_q.pc;
end if;
end if;
end process if_id_reg_proc;
---------------------------------------------------
-- Instruction decode
---------------------------------------------------
-- register file
register_file : entity work.regfile(rtl)
port map (clk => clk,
addra => id_q.rs1,
addrb => id_q.rs2,
rega => rs1_data,
regb => rs2_data,
addrw => wb_rf_wr_addr,
dataw => wb_rf_wr_data,
we => wb_rf_wr_en);
-- inputs
id_d.instruction <= if_id_ir;
-- instantiation
id_stage : entity work.instruction_decoder(Behavioral)
port map (id_d, id_q);
---------------------------------------------------
-- ID/EX pipeline registers
---------------------------------------------------
-- this is where instructions get issued,
-- controlled by id_stall, full_stall, and id_kill
id_ex_reg_proc : process (clk, rst_n) is
begin -- process id_ex_reg_proc
if (rst_n = '0') then -- asynchronous reset (active low)
id_ex_pc <= (others => '0');
id_ex_rs1_addr <= (others => '0');
id_ex_rs2_addr <= (others => '0');
id_ex_op1 <= (others => '0');
id_ex_op2 <= (others => '0');
id_ex_ir <= NOP;
elsif (rising_edge(clk)) then
if (id_stall = '0' and full_stall = '0') then
id_ex_rs1_addr <= id_q.rs1;
id_ex_rs2_addr <= id_q.rs2;
id_ex_op1 <= rs1_data;
id_ex_op2 <= rs2_data;
id_ex_use_imm <= id_q.use_imm;
if (id_kill = '1') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_ILLEGAL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
else
-- instruction issue
id_ex_pc <= if_id_pc;
id_ex_ir <= if_id_ir;
id_ex_rd_addr <= id_q.rd;
id_ex_insn_type <= id_q.insn_type;
id_ex_rf_we <= id_q.rf_we;
id_ex_use_imm <= id_q.use_imm;
id_ex_imm <= id_q.imm;
id_ex_alu_func <= id_q.alu_func;
id_ex_branch_type <= id_q.branch_type;
id_ex_load_type <= id_q.load_type;
id_ex_store_type <= id_q.store_type;
end if;
elsif (id_stall = '1' and full_stall = '0') then
id_ex_ir <= NOP;
id_ex_rd_addr <= (others => '0');
id_ex_insn_type <= OP_ILLEGAL;
id_ex_rf_we <= '0';
id_ex_use_imm <= '0';
id_ex_imm <= (others => '0');
id_ex_alu_func <= ALU_NONE;
id_ex_branch_type <= BRANCH_NONE;
id_ex_load_type <= LOAD_NONE;
id_ex_store_type <= STORE_NONE;
end if;
end if;
end process id_ex_reg_proc;
---------------------------------------------------
-- print instructions as they are issued
---------------------------------------------------
print_decode : if (g_for_sim = true) generate
print_decode_proc : process (id_ex_ir, id_ex_pc) is
variable l : line;
begin -- process print_decode_proc
write(l, to_integer(unsigned(id_ex_pc)));
write(l, string'(" : "));
write(l, hstr(id_ex_ir));
writeline(output, l);
end process print_decode_proc;
end generate print_decode;
---------------------------------------------------
-- Instruction execution stage
---------------------------------------------------
-- inputs
ex_d.insn_type <= id_ex_insn_type;
ex_d.npc <= id_ex_pc;
ex_d.rs1 <= id_ex_op1;
ex_d.rs2 <= id_ex_op2;
ex_d.use_imm <= id_ex_use_imm;
ex_d.alu_func <= id_ex_alu_func;
ex_d.branch_type <= id_ex_branch_type;
ex_d.imm <= id_ex_imm;
-- instantiation
ex_stage : entity work.instruction_executor(Behavioral)
port map (ex_d, ex_q);
-- multiplexer for Register File write data
ex_rf_data <= ex_q.return_addr when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR) else
id_ex_imm when (id_ex_insn_type = OP_LUI) else
ex_q.alu_result;
-- selecter for loading the PC with a new value
ex_load_pc <= '1' when (id_ex_insn_type = OP_JAL or id_ex_insn_type = OP_JALR or
(id_ex_insn_type = OP_BRANCH and ex_q.compare_result = '1')) else '0';
-- multiplexer for data memory address
ex_data_addr <= ex_q.alu_result when (id_ex_insn_type = OP_LOAD or id_ex_insn_type = OP_STORE) else ex_mem_data_addr;
---------------------------------------------------
-- EX/MEM pipeline registers
---------------------------------------------------
-- purpose: Pipeline data between EX and MEM stages
ex_mem_regs_proc : process (clk, rst_n) is
begin -- process ex_mem_regs_proc
if (rst_n = '0') then -- asynchronous reset (active low)
ex_mem_load_pc <= '0';
ex_mem_next_pc <= (others => '0');
ex_mem_rf_data <= (others => '0');
ex_mem_return_addr <= (others => '0');
ex_mem_load_type <= LOAD_NONE;
ex_mem_store_type <= STORE_NONE;
ex_mem_rd_addr <= (others => '0');
ex_mem_insn_type <= OP_ILLEGAL;
ex_mem_rf_we <= '0';
elsif (rising_edge(clk)) then
if (full_stall = '0') then
ex_mem_next_pc <= ex_q.alu_result;
ex_mem_load_pc <= ex_load_pc;
ex_mem_rf_data <= ex_rf_data;
ex_mem_data_addr <= ex_data_addr;
ex_mem_data_out <= id_ex_op2;
ex_mem_load_type <= id_ex_load_type;
ex_mem_store_type <= id_ex_store_type;
ex_mem_rd_addr <= id_ex_rd_addr;
ex_mem_insn_type <= id_ex_insn_type;
ex_mem_rf_we <= id_ex_rf_we;
end if;
end if;
end process ex_mem_regs_proc;
---------------------------------------------------
-- Memory stage
---------------------------------------------------
-- memory access logic
mem_we <= '1' when ex_mem_insn_type = OP_STORE else '0';
mem_re <= '1' when ex_mem_insn_type = OP_LOAD else '0';
-- data memory interface multiplexers
mem_data_addr <= ex_mem_data_addr;
mem_data_out <= X"0000" & ex_mem_data_out(15 downto 0) when ex_mem_store_type = SH else
X"000000" & ex_mem_data_out(7 downto 0) when ex_mem_store_type = SB else
ex_mem_data_out;
-- if the load is a signed halfword
mem_lmd_lh <= data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) &
data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15) & data_in(15 downto 0);
-- if the load is a signed byte
mem_lmd_lb <= data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7) & data_in(7 downto 0);
-- Load Memory Data register input
with ex_mem_load_type select
mem_lmd <=
X"0000" & data_in(15 downto 0) when LHU,
X"000000" & data_in(7 downto 0) when LBU,
mem_lmd_lh when LH,
mem_lmd_lb when LB,
data_in when others;
---------------------------------------------------
-- MEM/WB pipeline registers
---------------------------------------------------
-- purpose: Create the MEM/WB pipeline registers
mem_wb_regs : process (clk, rst_n) is
begin -- process mem_wb_regs
if (rst_n = '0') then -- asynchronous reset (active low)
mem_wb_rd_addr <= (others => '0');
mem_wb_rf_we <= '0';
mem_wb_rf_data <= (others => '0');
mem_wb_insn_type <= OP_ILLEGAL;
elsif (rising_edge(clk)) then
if (full_stall = '0') then
mem_wb_rd_addr <= ex_mem_rd_addr;
mem_wb_rf_we <= ex_mem_rf_we;
mem_wb_insn_type <= ex_mem_insn_type;
mem_wb_rf_data <= ex_mem_rf_data;
if (data_in_valid = '1') then
mem_wb_lmd <= mem_lmd;
end if;
else
mem_wb_rf_we <= '0';
end if;
end if;
end process mem_wb_regs;
---------------------------------------------------
-- Writeback stage
---------------------------------------------------
wb_rf_wr_addr <= mem_wb_rd_addr;
wb_rf_wr_en <= mem_wb_rf_we;
wb_rf_wr_data <= mem_wb_lmd when (mem_wb_insn_type = OP_LOAD) else mem_wb_rf_data;
end architecture Behavioral;
|
bsd-3-clause
|
46d18e8a0fa1c5cc5a95d02b5d6921a3
| 0.411161 | 3.703444 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/TESTBENCH_ac97_model.vhd
| 4 | 11,271 |
-------------------------------------------------------------------------------
-- $Id: TESTBENCH_ac97_model.vhd,v 1.1 2005/02/18 15:30:21 wirthlin Exp $
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: TESTBENCH_ac97_core.vhd
--
-- Description: Simple testbench for ac97_core
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Mike Wirthlin
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:21 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity TESTBENCH_ac97_core is
end TESTBENCH_ac97_core;
library opb_ac97_v2_00_a;
use opb_ac97_v2_00_a.all;
use opb_ac97_v2_00_a.TESTBENCH_ac97_package.all;
architecture behavioral of TESTBENCH_ac97_core is
component ac97_core
generic (
C_PLAYBACK : integer := 1;
C_RECORD : integer := 1;
C_PCM_DATA_WIDTH : integer := 16
);
port (
Reset : in std_logic;
-- signals attaching directly to AC97 codec
AC97_Bit_Clk : in std_logic;
AC97_Sync : out std_logic;
AC97_SData_Out : out std_logic;
AC97_SData_In : in std_logic;
AC97_Reg_Addr : in std_logic_vector(0 to 6);
AC97_Reg_Write_Data : in std_logic_vector(0 to 15);
AC97_Reg_Read_Data : out std_logic_vector(0 to 15);
AC97_Reg_Read_Data_Valid : out std_logic;
AC97_Reg_Read : in std_logic;
AC97_Reg_Write : in std_logic;
AC97_Reg_Ready : out std_logic;
PCM_Playback_Left: in std_logic_vector(0 to 15);
PCM_Playback_Right: in std_logic_vector(0 to 15);
PCM_Playback_Left_Valid: in std_logic;
PCM_Playback_Right_Valid: in std_logic;
PCM_Record_Left: out std_logic_vector(0 to 15);
PCM_Record_Right: out std_logic_vector(0 to 15);
PCM_Record_Left_Valid: out std_logic;
PCM_Record_Right_Valid: out std_logic;
New_Frame : out std_logic;
CODEC_RDY : out std_logic
);
end component;
component ac97_model is
port (
AC97Reset_n : in std_logic;
Bit_Clk : out std_logic;
Sync : in std_logic;
SData_Out : in std_logic;
SData_In : out std_logic
);
end component;
signal reset : std_logic;
signal ac97_reset : std_logic;
signal clk : std_logic;
signal sync : std_logic;
signal sdata_out : std_logic;
signal sdata_in : std_logic;
signal reg_addr : std_logic_vector(0 to 6);
signal reg_write_data : std_logic_vector(0 to 15);
signal reg_read_data : std_logic_vector(0 to 15);
signal reg_read_data_valid : std_logic;
signal reg_read : std_logic;
signal reg_write : std_logic;
signal reg_ready : std_logic;
signal PCM_Playback_Left: std_logic_vector(0 to 15);
signal PCM_Playback_Right: std_logic_vector(0 to 15);
signal PCM_Playback_Left_Valid: std_logic;
signal PCM_Playback_Right_Valid: std_logic;
signal PCM_Record_Left: std_logic_vector(0 to 15);
signal PCM_Record_Right: std_logic_vector(0 to 15);
signal PCM_Record_Left_Valid: std_logic;
signal PCM_Record_Right_Valid: std_logic;
signal New_Frame : std_logic;
signal CODEC_RDY : std_logic;
signal test_no : integer;
begin -- behavioral
ac97_reset <= not reset;
uut_1 : ac97_model
port map (
AC97Reset_n => ac97_reset,
Bit_Clk => clk,
Sync => sync,
SData_Out => sdata_out,
SData_In => sdata_in
);
uut: ac97_core
generic map (
C_PLAYBACK => 1,
C_RECORD => 1
)
port map (
Reset => reset,
-- signals attaching directly to AC97 codec
AC97_Bit_Clk => clk,
AC97_Sync => sync,
AC97_SData_Out => sdata_out,
AC97_SData_In => sdata_in,
AC97_Reg_Addr => reg_addr,
AC97_Reg_Write_Data => reg_write_data,
AC97_Reg_Read_Data => reg_read_data,
AC97_Reg_Read_Data_Valid => reg_read_data_valid,
AC97_Reg_Read => reg_read,
AC97_Reg_Write => reg_write,
AC97_Reg_Ready => reg_ready,
PCM_Playback_Left => PCM_Playback_Left,
PCM_Playback_Right => PCM_Playback_Right,
PCM_Playback_Left_Valid => PCM_Playback_Left_Valid,
PCM_Playback_Right_Valid => PCM_Playback_Right_Valid,
PCM_Record_Left => PCM_Record_Left,
PCM_Record_Right => PCM_Record_Right,
PCM_Record_Left_Valid => PCM_Record_Left_Valid,
PCM_Record_Right_Valid => PCM_Record_Right_Valid,
New_Frame => New_Frame,
CODEC_RDY => CODEC_RDY
);
-- simulate a reset
opb_rst_gen: process
begin
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process opb_rst_gen;
-- Test process
test_process: process
begin
test_no <= 0;
-- set default values
reg_addr <= (others => '0');
reg_write_data <= (others => '0');
reg_read <= '0';
reg_write <= '0';
PCM_Playback_Left <= (others => '0');
PCM_Playback_Right <= (others => '0');
PCM_Playback_Left_Valid <= '0';
PCM_Playback_Right_Valid <= '0';
-- 1. Wait until CODEC ready before doing anything
wait until CODEC_RDY='1' and clk'event and clk='1';
-- skip some time slots before performing a bus cycle
for i in 300 downto 0 loop
wait until clk'event and clk='1';
end loop;
-- Start at first sync pulse
wait until Sync'event and Sync='1';
--wait until clk'event and clk='1';
wait until clk'event and clk='1';
test_no <= 1;
-- send some playback data
PCM_Playback_Left <= X"8001";
PCM_Playback_Right <= X"0180";
PCM_Playback_Left_Valid <= '1';
PCM_Playback_Right_Valid <= '1';
wait until New_Frame'event and New_Frame='0';
test_no <= 2;
PCM_Playback_Left <= X"4002";
PCM_Playback_Right <= X"0240";
wait until New_Frame'event and New_Frame='0';
test_no <= 3;
-- send a read command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_read <= '1';
wait until New_Frame'event and New_Frame='0';
reg_read <= '0';
wait;
-- send a write command
PCM_Playback_Left <= X"2004";
PCM_Playback_Right <= X"0420";
reg_addr <= "0010001";
reg_write_data <= X"5A5A";
reg_write <= '1';
wait until New_Frame'event and New_Frame='0';
wait;
end process;
-- -- Recording Data
-- sdata_in_proc: process
-- variable slot0 : std_logic_vector(15 downto 0) := "1001100000000000";
-- -- Control address
-- variable slot1 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- Control data
-- variable slot2 : std_logic_vector(19 downto 0) := "10000000000000000000";
-- -- PCM left (0x69696)
-- variable slot3 : std_logic_vector(19 downto 0) := "01101001011010010110";
-- -- PCM right (0x96969)
-- variable slot4 : std_logic_vector(19 downto 0) := "10010110100101101001";
-- begin
-- sdata_in <= '0';
-- -- 1. Wait until CODEC ready before doing anything
-- wait until CODEC_RDY='1' and clk'event and clk='1';
-- -- skip some time slots before performing a bus cycle
-- for i in 300 downto 0 loop
-- wait until clk'event and clk='1';
-- end loop;
-- -- Start at first sync pulse
-- wait until Sync'event and Sync='1';
-- --wait until clk'event and clk='1';
-- wait until clk'event and clk='1';
-- -- (1) record data
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (2) record data
-- slot3 := X"8001_0";
-- slot4 := X"1234_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (3) record data
-- slot3 := X"4002_0";
-- slot4 := X"2345_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (4) record data & some control data
-- slot3 := X"2004_0";
-- slot4 := X"3456_0";
-- slot0 := "1011100000000000";
-- slot2 := X"FEDC_B";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- -- (5) record data
-- slot3 := X"1008_0";
-- slot4 := X"3456_0";
-- send_basic_frame(clk, slot0, slot1, slot2, slot3, slot4, sdata_in);
-- wait;
-- end process;
-- -- Recording Data
-- control_proc: process
-- begin
-- reg_addr <= (others => '0');
-- reg_write_data <= (others => '0');
-- reg_read <= '0';
-- reg_write <= '0';
-- PCM_Playback_Left <= (others => '0');
-- PCM_Playback_Right <= (others => '0');
-- PCM_Playback_Left_Valid <= '0';
-- PCM_Playback_Right_Valid <= '0';
-- -- skip 2 frames
-- for i in 1 downto 0 loop
-- wait until New_Frame'event and New_Frame='0';
-- end loop;
-- -- send some playback data
-- PCM_Playback_Left <= X"8001";
-- PCM_Playback_Right <= X"0180";
-- PCM_Playback_Left_Valid <= '1';
-- PCM_Playback_Right_Valid <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- PCM_Playback_Left <= X"4002";
-- PCM_Playback_Right <= X"0240";
-- wait until New_Frame'event and New_Frame='0';
-- -- send a write command
-- PCM_Playback_Left <= X"2004";
-- PCM_Playback_Right <= X"0420";
-- reg_addr <= "0010001";
-- reg_write_data <= X"5A5A";
-- reg_write <= '1';
-- wait until New_Frame'event and New_Frame='0';
-- reg_write <= '0';
-- PCM_Playback_Left <= X"1008";
-- PCM_Playback_Right <= X"0810";
-- wait;
-- end process;
end behavioral;
|
gpl-3.0
|
99fa8428cc03d22020c71ec0717ff613
| 0.517878 | 3.367493 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.vhdl
| 1 | 8,334 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Fri May 27 23:50:21 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.vhdl
-- Design : ClockDivider
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider_ClockDivider_clk_wiz is
port (
clkIn : in STD_LOGIC;
clk108M : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk2cpu : out STD_LOGIC;
clk6cpu : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz";
end ClockDivider_ClockDivider_clk_wiz;
architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is
signal clk108M_ClockDivider : STD_LOGIC;
signal clk2cpu_ClockDivider : STD_LOGIC;
signal clk6cpu_ClockDivider : STD_LOGIC;
signal clkIn_ClockDivider : STD_LOGIC;
signal clk_cpu_ClockDivider : STD_LOGIC;
signal clkfbout_ClockDivider : STD_LOGIC;
signal clkfbout_buf_ClockDivider : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout4_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ClockDivider,
O => clkfbout_buf_ClockDivider
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clkIn,
O => clkIn_ClockDivider
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk108M_ClockDivider,
O => clk108M
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_cpu_ClockDivider,
O => clk_cpu
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk2cpu_ClockDivider,
O => clk2cpu
);
clkout4_buf: unisim.vcomponents.BUFG
port map (
I => clk6cpu_ClockDivider,
O => clk6cpu
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 54.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 72,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 36,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 12,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ClockDivider,
CLKFBOUT => clkfbout_ClockDivider,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clkIn_ClockDivider,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk108M_ClockDivider,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_cpu_ClockDivider,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk2cpu_ClockDivider,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => clk6cpu_ClockDivider,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider is
port (
clkIn : in STD_LOGIC;
clk108M : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk2cpu : out STD_LOGIC;
clk6cpu : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ClockDivider : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ClockDivider;
architecture STRUCTURE of ClockDivider is
begin
inst: entity work.ClockDivider_ClockDivider_clk_wiz
port map (
clk108M => clk108M,
clk2cpu => clk2cpu,
clk6cpu => clk6cpu,
clkIn => clkIn,
clk_cpu => clk_cpu
);
end STRUCTURE;
|
mit
|
cc5b34e296f266812b262d28b91dacaa
| 0.656947 | 3.558497 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/memory_loader_pkg.vhd
| 1 | 5,646 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.genram_pkg.all;
package memory_loader_pkg is
subtype t_meminit_array is t_generic_ram_init;
function f_hexchar_to_slv (c : character) return std_logic_vector;
function f_hexstring_to_slv (s : string; n_digits : integer) return std_logic_vector;
function f_get_token(s : string; n : integer) return string;
function f_load_mem_from_file
(file_name : string;
mem_size : integer;
mem_width : integer;
fail_if_notfound : boolean)
return t_meminit_array;
end memory_loader_pkg;
package body memory_loader_pkg is
function f_hexchar_to_slv (c : character) return std_logic_vector is
variable t : std_logic_vector(3 downto 0);
begin
case c is
when '0' => t := x"0";
when '1' => t := x"1";
when '2' => t := x"2";
when '3' => t := x"3";
when '4' => t := x"4";
when '5' => t := x"5";
when '6' => t := x"6";
when '7' => t := x"7";
when '8' => t := x"8";
when '9' => t := x"9";
when 'a' => t := x"a";
when 'A' => t := x"a";
when 'b' => t := x"b";
when 'B' => t := x"b";
when 'c' => t := x"c";
when 'C' => t := x"c";
when 'd' => t := x"d";
when 'D' => t := x"d";
when 'e' => t := x"e";
when 'E' => t := x"e";
when 'f' => t := x"f";
when 'F' => t := x"f";
when others =>
report "f_hexchar_to_slv(): unrecognized character '" &c&" in hex text string" severity failure;
end case;
return t;
end f_hexchar_to_slv;
function f_hexstring_to_slv (s : string; n_digits : integer) return std_logic_vector is
variable tmp : std_logic_vector(255 downto 0) := (others => '0');
begin
if s'length > tmp'length then
report "f_hexstring_to_slv(): string length exceeds the limit" severity failure;
end if;
for i in 0 to s'length-1 loop
tmp(4 * (s'length - i) - 1 downto 4 * (s'length - 1 - i)) := f_hexchar_to_slv(s(i+1));
end loop; -- i
return tmp(n_digits * 4 - 1 downto 0);
end f_hexstring_to_slv;
function f_get_token(s : string; n : integer) return string is
variable cur_pos : integer;
variable tmp : string (1 to 128);
variable cur_token : integer;
variable tmp_pos : integer;
begin
cur_pos := 1;
cur_token := 1;
tmp_pos := 1;
loop
if(cur_pos >= s'length) then
return "";
end if;
while cur_pos <= s'length and (s(cur_pos) = ' ' or s(cur_pos) = character'val(9) or s(cur_pos) = character'val(0)) loop
cur_pos := cur_pos + 1;
end loop;
if(cur_pos >= s'length) then
return "";
end if;
while(cur_pos <= s'length and s(cur_pos) /= ' ' and s(cur_pos) /= character'val(9) and s(cur_pos) /= character'val(0)) loop
if(cur_token = n) then
tmp(tmp_pos) := s(cur_pos);
tmp_pos := tmp_pos + 1;
end if;
cur_pos := cur_pos + 1;
end loop;
if(cur_token = n) then
return tmp(1 to tmp_pos-1);
end if;
cur_token := cur_token + 1;
if(cur_pos >= s'length) then
return "";
end if;
end loop;
return "";
end f_get_token;
function f_load_mem_from_file
(file_name : string;
mem_size : integer;
mem_width : integer;
fail_if_notfound : boolean)
return t_meminit_array is
file f_in : text;
variable l : line;
variable ls : string(1 to 128);
variable cmd : string(1 to 128);
variable line_len : integer;
variable status : file_open_status;
variable mem : t_meminit_array(0 to mem_size-1, mem_width-1 downto 0);
variable i : integer;
variable c : character;
variable good : boolean;
variable addr : integer;
variable data_tmp : unsigned(mem_width-1 downto 0);
variable data_int : integer;
begin
if(file_name = "" or file_name = "none") then
mem := (others => (others => '0'));
return mem;
end if;
file_open(status, f_in, file_name, read_mode);
if(status /= open_ok) then
if(fail_if_notfound) then
report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
else
report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
end if;
end if;
while true loop
i := 0;
while (i < 4096) loop
-- stupid ISE restricts the loop length
readline(f_in, l);
line_len := 0;
loop
read(l, ls(line_len+1), good);
exit when good = false;
line_len := line_len + 1;
end loop;
if(line_len /= 0 and f_get_token(ls, 1) = "write") then
addr := to_integer(unsigned(f_hexstring_to_slv(f_get_token(ls, 2), 8)));
data_tmp := resize(unsigned(f_hexstring_to_slv(f_get_token(ls, 3), 8)), mem_width);
data_int := to_integer(data_tmp);
-- report "addr: " & integer'image(addr) & " data: " & integer'image(data_int);
for i in 0 to mem_width-1 loop
mem(addr, i) := std_logic(data_tmp(i));
end loop; -- i in 0 to mem_width-1
-- report "addr: " & integer'image(addr) & " data: " & integer'image(data_int);
end if;
if endfile(f_in) then
file_close(f_in);
return mem;
end if;
i := i+1;
end loop;
end loop;
return mem;
end f_load_mem_from_file;
end memory_loader_pkg;
|
lgpl-3.0
|
bd4225bb8d32042484b300095be28cec
| 0.534715 | 3.15419 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/system.vhd
| 4 | 3,790 |
-- This system does nothing useful
-- It takes input X and this is registered internally
-- It computes x+1 and x+const independently
-- The output is computed as (x+const)-(x+1)=const-1
-- so the higher level modifies C and then C-1 is returned
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity Const_system is
generic (C: in integer := 500);
port (clk, reset: in std_logic;
x: in std_logic_vector (7 downto 0);
y: out std_logic_vector (10 downto 0) );
end Const_system;
library ieee;
use ieee.std_logic_1164.all;
entity Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end Add;
library ieee;
use ieee.std_logic_1164.all;
entity Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end Inc;
library ieee;
use ieee.std_logic_1164.all;
entity Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end Reg_N;
architecture System_rtl of Const_system is
-- Register component
component Reg_N is
generic (n: integer := 4);
port (clk, reset: in std_logic;
a: in std_logic_vector (n-1 downto 0);
a_reg: out std_logic_vector (n-1 downto 0) );
end component;
-- incrementer component
component Inc is
generic (n: integer := 8);
port (a: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0)
);
end component;
-- adder component
component Add is
generic (n: integer := 8);
port (a, b: in std_logic_vector (n-1 downto 0);
sum: out std_logic_vector (n-1 downto 0);
cin: in std_logic );
end component;
signal x_int: std_logic_vector (7 downto 0);
signal x_inc: std_logic_vector (7 downto 0);
signal x_sum: std_logic_vector (10 downto 0);
signal x_ext: std_logic_vector (10 downto 0);
signal x_inv: std_logic_vector (10 downto 0);
signal x_dif: std_logic_vector (10 downto 0);
signal zero, one: std_logic;
signal const: std_logic_vector (10 downto 0);
begin
const <= conv_std_logic_vector (C, 11);
-- connstant bit 0, 1
zero <= '0';
one <= '1';
-- registering input X
RegX: Reg_N generic map (n => 8)
port map ( clk => clk, reset => reset, a => x, a_reg => x_int);
-- Incrementing input x_int
incrementer: Inc generic map (n => 8)
port map (a => x_int, sum => x_inc); -- x + 1
-- forming 1's complement of x+1
x_inv <= "111" & not x_inc;
x_ext <= "000" & x_int;
-- adding constant to x_int
addition: Add generic map (n => 11)
port map (a => x_ext, b => const, cin => zero, sum => x_sum); -- x + 1000
-- this should get x+1000-(x+1) = 1000-1 = 999
subtraction: Add generic map (n => 11)
port map (a => x_sum, b => x_inv, cin => one, sum => x_dif);
-- registering output X
RegY: Reg_N generic map (n => 11)
port map ( clk => clk, reset => reset, a => x_dif, a_reg => y);
end System_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Add_rtl of Add is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + ('0' & b) + cin;
sum <= cx (n-1 downto 0);
end Add_rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture Inc_rtl of Inc is
signal cx: std_logic_vector (n downto 0);
begin
cx <= ('0' & a) + '1';
sum <= cx (n-1 downto 0);
end Inc_rtl;
library ieee;
use ieee.std_logic_1164.all;
architecture Reg_rtl of Reg_N is
begin
My_register: process (clk, reset)
begin
if (reset = '1') then
a_reg <= (others => '0');
elsif (clk'event and clk = '1') then
a_reg <= a;
end if;
end process;
end Reg_rtl;
|
gpl-2.0
|
7f2a8856fc5f9439e0cb47b2af5ff3ef
| 0.635356 | 2.851768 | false | false | false | false |
db-electronics/SMSFlashCart
|
SMSMapper_tb.vhd
| 1 | 1,711 |
library std;
use std.env.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SMSMapper_tb is
end SMSMapper_tb;
architecture rtl of SMSMapper_tb is
--input from sms
signal ADDR : std_logic_vector(15 downto 0);
signal DATA : std_logic_vector(7 downto 0);
signal nRST : std_logic;
signal nWR : std_logic;
signal nCE : std_logic;
--output to ROM
signal nROMWE : std_logic;
signal nROMCE : std_logic;
signal ROMADDR1914 : std_logic_vector(5 downto 0);
--output to serial EEPROM
signal EE_CS : std_logic;
signal EE_SO : std_logic;
signal EE_SI : std_logic;
signal EE_SCK : std_logic;
--output to SRAM
signal nSRAMCE : std_logic;
signal nSRAMWE : std_logic;
signal SRAMADDR14 : std_logic;
begin
SMSMapper_u0: entity work.SMSMapper
port map(
ADDR_p => ADDR,
DATA_p => DATA,
nRST_p => nRST,
nWR_p => nWR,
nCE_p => nCE,
nROMWE_p => nROMWE,
nROMCE_p => nROMCE,
ROMADDR1914_p => ROMADDR1914,
EE_CS_p => EE_CS,
EE_SO_p => EE_SO,
EE_SI_p => EE_SI,
EE_SCK_p => EE_SCK,
nSRAMCE_p => nSRAMCE,
nSRAMWE_p => nSRAMWE,
SRAMADDR14_p => SRAMADDR14
);
sim: process
begin
nRST <= '0';
DATA <= ( others => 'Z');
nROMWE <= 'H';
nROMCE <= 'H';
ROMADDR1914 <= (others => 'H');
ADDR <= ( others => '1');
nCE <= '1';
nWR <= '1';
wait for 10 ns;
nRST <= '1';
DATA <= x"04";
ADDR <= x"FFFD";
wait for 5 ns;
nCE <= '0';
nWR <= '0';
wait for 15 ns;
nCE <= '1';
nWR <= '1';
wait for 5 ns;
ADDR <= x"2000";
wait for 5 ns;
nCE <= '0';
wait for 15 ns;
nCE <= '1';
wait for 5 ns;
stop(0);
end process;
end architecture;
|
gpl-2.0
|
a1e9f44693ce24ff4083e506224ffba1
| 0.565751 | 2.440799 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/new/ClockDivider.vhd
| 1 | 698 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ClockDivider is
Generic (
DEVIDER : integer := 2
);
Port (
clk_in : in STD_LOGIC := '0';
clk_out : out STD_LOGIC := '0'
);
end ClockDivider;
architecture Behavioral of ClockDivider is
signal temp : STD_LOGIC := '0';
signal counter : integer range 0 to DEVIDER := 0;
begin
process(clk_in) begin
if (rising_edge(clk_in)) then
if (counter = DEVIDER) then
counter <= 0;
temp <= NOT(temp);
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temp;
end Behavioral;
|
mit
|
594aa4cd41efd9e4b6dc4118a846debe
| 0.522923 | 4.011494 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_core_v2_01_a/hdl/vhdl/osif_core.vhd
| 1 | 22,731 |
--!
--! \file osif_core.vhd
--!
--! OSIF logic and interface to IPIF
--!
--! The osif_core contains processes for OS request handling. Also, it
--! instantiates the DCR slave module, which manages communication
--! between the CPU and the OSIF.
--!
--! There are two sets of registers, one for each direction (logic to bus
--! and bus to logic). Each set has the a register for command, data,
--! and extended data; the bus to logic set has another handshake register
--! indicating an incoming request from the DCR bus.
--!
--! Communication with the user task goes through the osif_task2os and
--! osif_os2task data structures, which are converted to std_logic_vectors
--! at the module interface, because XPS cannot handle VHDL records. An
--! incoming request from a task to perform an operating system call
--! is signalled by the request line of the task2os record. Requests can be
--! divided into two categories:
--!
--! - those that are handled in hardware without microprocessor
--! involvement (like shared memory accesses), and
--! - those that have to be handled in the microprocessor
--!
--! The first are handled directly within osif_core (and its submodules),
--! whereas the latter cause an interrupt to the microprocessor, preempt
--! any running processes there and wake up a software thread, which then
--! acts on behalf of the hardware thread.
--!
--!
--!
--!
--!
--! Memory bus interface fifo_manager
--! Memory (master/slave)
--! Bus <----------------------------+ ^
--! (e.g. PLB) | |
--! | +----------------+
--! _______|____|____
--! | |
--! clk, reset ------------------>| command_decoder |
--! |_________________|
--! | |
--! | +----------------+
--! Hardware | _____|__________
--! Thread <-----------------------------+ | |
--! Hardware Thread Control Interface | dcr_slave_regs |
--! |________________|
--! ^
--! |
--! V
--! D C R
--! \author Enno Luebbers <[email protected]>
--! \date 08.12.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 01.08.2006 Enno Luebbers File created (from opb_reconos_slot_v1_00_c)
-- 03.08.2006 Enno Luebbers Added PLB bus master (moved to v1.01.a),
-- removed BRAM interface
-- 04.08.2006 Enno Luebbers moved user_logic to toplevel
-- 07.08.2006 Enno Luebbers moved logic to separate modules
-- (bus_master, bus_slave_regs)
-- xx.10.2007 Enno Luebbers added local FIFO manager
-- 23.11.2007 Enno Luebbers moved slave registers to DCR
-- 08.12.2008 Enno Luebbers modularized (moved memory bus controller
-- to separate module)
-- 10.12.2008 Enno Luebbers moved and renamed from user_logic to osif_core
--
--*************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library osif_core_v2_01_a;
use osif_core_v2_01_a.all;
entity osif_core is
generic
(
-- Bus protocol parameters
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_NUM_CE : integer := 2;
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_THREAD_RESET_CYCLES : natural := 10; -- number of cycles the thread reset is held
C_FIFO_DWIDTH : integer := 32;
C_BURSTLEN_WIDTH : integer := 5; -- max 16x64 bit bursts
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_DCR_ILA : integer := 0 -- 0: no debug ILA, 1: include debug chipscope ILA for DCR debugging
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- FIFO manager access signals
-- left (read) FIFO
o_fifomgr_read_remove : out std_logic;
i_fifomgr_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifomgr_read_wait : in std_logic;
-- right (write) FIFO
o_fifomgr_write_add : out std_logic;
o_fifomgr_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifomgr_write_wait : in std_logic;
-- memory access signals
o_mem_singleData : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
i_mem_singleData : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
o_mem_localAddr : out std_logic_vector(0 to C_AWIDTH-1);
o_mem_targetAddr : out std_logic_vector(0 to C_AWIDTH-1);
o_mem_singleRdReq : out std_logic;
o_mem_singleWrReq : out std_logic;
o_mem_burstRdReq : out std_logic;
o_mem_burstWrReq : out std_logic;
o_mem_burstLen : out std_logic_vector(0 to C_BURSTLEN_WIDTH-1);
i_mem_busy : in std_logic;
i_mem_rdDone : in std_logic;
i_mem_wrDone : in std_logic;
-- bus macro control
o_bm_enable : out std_logic;
-- dcr bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0)
);
end entity osif_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of osif_core is
--#################################################################################################################
-------
-- OS signals
-------
-- between os and task
signal osif_os2task : osif_os2task_t;
signal osif_task2os : osif_task2os_t;
-- FIXME: is there a better way than a handshake register?
signal os2task_newcmd : std_logic := '0';
signal request_blocking : std_logic := '0';
signal request_unblocking : std_logic := '0';
-- signal os2task_reset : std_logic := '0';
signal task2os_error : std_logic := '0'; -- FIXME: this is being ignored
-- dirty flag signals indicating unread data in read registers
signal slv_busy : std_logic;
signal post_sw_request : std_logic;
---------
-- slave register signals (put on DCR)
---------
signal slv_bus2osif_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1);
signal slv_bus2osif_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal slv_bus2osif_done : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal slv_osif2bus_command : std_logic_vector(0 to C_OSIF_CMD_WIDTH-1) := (others => '0'); -- task2os command
signal slv_osif2bus_flags : std_logic_vector(0 to C_OSIF_FLAGS_WIDTH-1);
signal slv_osif2bus_saved_state_enc : std_logic_vector(0 to C_OSIF_STATE_ENC_WIDTH-1);
signal slv_osif2bus_saved_step_enc : std_logic_vector(0 to C_OSIF_STEP_ENC_WIDTH-1);
signal slv_osif2bus_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal slv_osif2bus_datax : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- task2os data
signal slv_osif2bus_signature : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0'); -- hwthread signature
---------
-- status registers
---------
signal thread_init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1); -- thread data (passed at initialization)
---------
-- local FIFO handles (used for FIFO message routing)
---------
signal fifo_read_handle : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal fifo_write_handle : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
---------
-- thread reset counter
---------
signal reset_counter : natural range 0 to C_THREAD_RESET_CYCLES-1 := C_THREAD_RESET_CYCLES-1;
signal request_reset : std_logic;
signal thread_reset_i : std_logic;
---------
-- signals for cooperative multithreading
---------
signal thread_is_resuming : std_logic;
signal yield_request : std_logic; -- request from OS to yield
signal yield_flag : std_logic; -- if '!', thread can yield
signal saved_state_enc : reconos_state_enc_t;
signal saved_step_enc : reconos_step_enc_t;
signal resume_state_enc : reconos_state_enc_t;
signal resume_step_enc : reconos_step_enc_t;
begin
-- ################### MODULE INSTANTIATIONS ####################
-----------------------------------------------------------------------
-- dcr_slave_regs_inst: DCR bus slave instatiation
--
-- Handles access to the various registers.
-- NOTE: While slv_bus2osif_* signals are latched by bus_slave_regs,
-- the slv_osif2bus_* signals MUST BE STABLE until the transaction
-- is complete (busy goes low for s/w OS requests or the shm bus
-- bus master transaction completes).
-----------------------------------------------------------------------
dcr_slave_regs_inst : entity osif_core_v2_01_a.dcr_slave_regs
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_NUM_REGS => 4,
C_INCLUDE_ILA => C_DCR_ILA
)
port map (
clk => sys_clk,
reset => thread_reset_i, --sys_reset,
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON,
-- user registers
slv_osif2bus_command => slv_osif2bus_command,
slv_osif2bus_flags => slv_osif2bus_flags,
slv_osif2bus_saved_state_enc => slv_osif2bus_saved_state_enc,
slv_osif2bus_saved_step_enc => slv_osif2bus_saved_step_enc,
slv_osif2bus_data => slv_osif2bus_data,
slv_osif2bus_datax => slv_osif2bus_datax,
slv_osif2bus_signature => slv_osif2bus_signature,
slv_bus2osif_command => slv_bus2osif_command,
slv_bus2osif_data => slv_bus2osif_data,
slv_bus2osif_done => slv_bus2osif_done,
-- additional user interface
o_newcmd => os2task_newcmd,
i_post => post_sw_request,
o_busy => slv_busy,
o_interrupt => interrupt
);
-----------------------------------------------------------------------
-- command_decoder_inst: command decoder instatiation
--
-- Handles decoding the commands from the HW thread.
-- NOTE: the command decoder is completely asynchronous. It also
-- handles the setting and releasing of the osif_os2task.busy
-- and .blocking signals.
-----------------------------------------------------------------------
command_decoder_inst : entity osif_core_v2_01_a.command_decoder
generic map (
C_AWIDTH => C_AWIDTH,
C_DWIDTH => C_DWIDTH,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => C_BURSTLEN_WIDTH)
port map (
i_clk => sys_clk,
i_reset => thread_reset_i, -- Bus2IP_Reset,
i_osif => osif_task2os,
o_osif => osif_os2task,
o_sw_request => post_sw_request,
i_request_blocking => request_blocking,
i_release_blocking => request_unblocking,
i_init_data => thread_init_data,
o_bm_my_addr => o_mem_localAddr,
o_bm_target_addr => o_mem_targetAddr,
o_bm_read_req => o_mem_singleRdReq,
o_bm_write_req => o_mem_singleWrReq,
o_bm_burst_read_req => o_mem_burstRdReq,
o_bm_burst_write_req => o_mem_burstWrReq,
o_bm_burst_length => o_mem_burstLen,
i_bm_busy => i_mem_busy,
i_bm_read_done => i_mem_rdDone,
i_bm_write_done => i_mem_wrDone,
i_slv_busy => slv_busy,
i_slv_bus2osif_command => slv_bus2osif_command,
i_slv_bus2osif_data => slv_bus2osif_data,
i_slv_bus2osif_shm => i_mem_singleData,
o_slv_osif2bus_command => slv_osif2bus_command,
o_slv_osif2bus_data => slv_osif2bus_data,
o_slv_osif2bus_datax => slv_osif2bus_datax,
o_slv_osif2bus_shm => o_mem_singleData,
o_hwthread_signature => slv_osif2bus_signature,
o_fifo_read_remove => o_fifomgr_read_remove,
i_fifo_read_data => i_fifomgr_read_data,
i_fifo_read_wait => i_fifomgr_read_wait,
o_fifo_write_add => o_fifomgr_write_add,
o_fifo_write_data => o_fifomgr_write_data,
i_fifo_write_wait => i_fifomgr_write_wait,
i_fifo_read_handle => fifo_read_handle,
i_fifo_write_handle => fifo_write_handle,
i_resume => thread_is_resuming,
i_yield => yield_request,
o_yield => yield_flag,
o_saved_state_enc => saved_state_enc,
o_saved_step_enc => saved_step_enc,
i_resume_state_enc => resume_state_enc,
i_resume_step_enc => resume_step_enc
);
-- ################### CONCURRENT ASSIGNMENTS ####################
-----------------------------------------------------------------------
-- User task signal routing
--
-- The user task is supplied with a dedicated clock and reset signal,
-- just in case we want to use them later.
-----------------------------------------------------------------------
task_clk <= sys_clk; --Bus2IP_Clk;
thread_reset_i <= '1' when reset_counter > 0 else '0';
task_reset <= thread_reset_i;
-- OSIF record to vector conversion (because EDK cannot handle records)
osif_os2task_vec <= to_std_logic_vector(osif_os2task);
osif_task2os <= to_osif_task2os_t(osif_task2os_vec);
-- FIXME: ignoring task error
task2os_error <= osif_task2os.error;
-- flags and yield control
slv_osif2bus_flags <= yield_flag & "0000000";
slv_osif2bus_saved_state_enc <= saved_state_enc;
slv_osif2bus_saved_step_enc <= saved_step_enc;
-- drive debug signals
busy <= osif_os2task.busy;
blocking <= osif_os2task.blocking;
-- ################### PROCESSES ####################
-----------------------------------------------------------------------
-- handle_os2task_response: Handles incoming OS commands
--
-- Especially the OSIF_CMD_UNBLOCK command, which signals that a
-- blocking OS call has returned.
-----------------------------------------------------------------------
-- FIXME: does this have to be synchronous?
handle_os2task_response : process(sys_clk, sys_reset)
begin
if sys_reset = '1' then
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
o_bm_enable <= '0'; -- bus macros are disabled by default!
thread_init_data <= (others => '0');
thread_is_resuming <= '0'; -- per default, the thread is not resumed, but created/started
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
yield_request <= '0';
elsif rising_edge(sys_clk) then
-- also reset everything on a synchronous thread_reset!
if thread_reset_i = '1' then
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
-- o_bm_enable <= '0'; -- do not disable bus macros on a thread reset (would break signature read)
thread_init_data <= (others => '0');
thread_is_resuming <= '0'; -- per default, the thread is not resumed, but created/started
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
-- yield_request <= '0'; -- yield_request is persistent across resets!
end if;
request_blocking <= '0';
request_unblocking <= '0';
request_reset <= '0';
if os2task_newcmd = '1' then
case slv_bus2osif_command(0 to C_OSIF_CMD_WIDTH-1) is
when OSIF_CMD_UNBLOCK =>
request_unblocking <= '1';
when OSIF_CMD_SET_INIT_DATA =>
thread_init_data <= slv_bus2osif_data;
when OSIF_CMD_RESET =>
request_blocking <= '1';
request_reset <= '1';
when OSIF_CMD_BUSMACRO =>
if slv_bus2osif_data = OSIF_DATA_BUSMACRO_DISABLE then -- disable
o_bm_enable <= '0';
else
o_bm_enable <= '1'; -- enable
end if;
when OSIF_CMD_SET_FIFO_READ_HANDLE =>
fifo_read_handle <= slv_bus2osif_data;
when OSIF_CMD_SET_FIFO_WRITE_HANDLE =>
fifo_write_handle <= slv_bus2osif_data;
when OSIF_CMD_SET_RESUME_STATE =>
resume_state_enc <= slv_bus2osif_data(0 to C_OSIF_STATE_ENC_WIDTH-1);
resume_step_enc <= slv_bus2osif_data(C_OSIF_STATE_ENC_WIDTH to C_OSIF_STATE_ENC_WIDTH+C_OSIF_STEP_ENC_WIDTH-1);
thread_is_resuming <= '1';
-- FIXME: do we need this?
when OSIF_CMD_CLEAR_RESUME_STATE =>
resume_state_enc <= (others => '0');
resume_step_enc <= (others => '0');
thread_is_resuming <= '0';
when OSIF_CMD_REQUEST_YIELD =>
yield_request <= '1';
when OSIF_CMD_CLEAR_YIELD =>
yield_request <= '0';
when others =>
end case;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- reset_proc: handles reset of software thread
-----------------------------------------------------------------------
reset_proc: process(sys_clk, sys_reset)
begin
if sys_reset = '1' then
reset_counter <= C_THREAD_RESET_CYCLES-1;
elsif rising_edge(sys_clk) then
if request_reset = '1' then
reset_counter <= C_THREAD_RESET_CYCLES-1;
elsif reset_counter > 0 then
reset_counter <= reset_counter - 1;
end if;
end if;
end process;
end IMP;
|
gpl-3.0
|
d7c23e16eb4e18670d7500170e4b5dd9
| 0.4881 | 4.119427 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/lm32_dp_ram.vhd
| 2 | 1,256 |
-- Work-alike to lm32_dp_ram.v, but using generic_simple_dpram
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
entity lm32_dp_ram is
generic(
addr_width : natural := 32;
addr_depth : natural := 1024;
data_width : natural := 8);
port(
clk_i : in std_logic;
rst_i : in std_logic;
we_i : in std_logic;
waddr_i : in std_logic_vector(addr_width-1 downto 0);
wdata_i : in std_logic_vector(data_width-1 downto 0);
raddr_i : in std_logic_vector(addr_width-1 downto 0);
rdata_o : out std_logic_vector(data_width-1 downto 0));
end lm32_dp_ram;
architecture syn of lm32_dp_ram is
constant c_addr_width : natural := f_log2_size(addr_depth);
begin
ram : generic_simple_dpram
generic map(
g_data_width => data_width,
g_size => addr_depth,
g_with_byte_enable => false,
g_addr_conflict_resolution => "write_first",
g_dual_clock => false)
port map(
clka_i => clk_i,
wea_i => we_i,
aa_i => waddr_i(c_addr_width-1 downto 0),
da_i => wdata_i,
clkb_i => clk_i,
ab_i => raddr_i(c_addr_width-1 downto 0),
qb_o => rdata_o);
end syn;
|
lgpl-3.0
|
b8f853f9ea9c70889edad64f890d409b
| 0.574045 | 2.948357 | false | false | false | false |
denis4net/hw_design
|
2/altera-project/src/collector.vhd
| 1 | 1,300 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity COLLECTOR is
port(
A: in std_logic_vector(7 downto 0);
B: out std_logic_vector(6 downto 0);
CLK: in std_logic;
NRCO: out std_logic
);
end entity;
architecture COLLECTOR0 of COLLECTOR is
signal collector_bus: std_logic_vector(7 downto 0);
begin
collector_bus <= A;
B(0) <= collector_bus(0) and CLK;
B(1) <= collector_bus(0) and collector_bus(1) and CLK;
B(2) <= collector_bus(0) and collector_bus(1) and collector_bus(2) and CLK;
B(3) <= collector_bus(0) and collector_bus(1) and collector_bus(2) and collector_bus(3) and CLK;
B(4) <= collector_bus(0) and collector_bus(1) and collector_bus(2) and collector_bus(3) and collector_bus(4) and CLK;
B(5) <= collector_bus(0) and collector_bus(1) and collector_bus(2) and collector_bus(3) and collector_bus(4) and collector_bus(5) and CLK;
B(6) <= collector_bus(0) and collector_bus(1) and collector_bus(2) and collector_bus(3) and collector_bus(4) and collector_bus(5) and collector_bus(6) and CLK;
NRCO <= not (
collector_bus(0) and collector_bus(1) and collector_bus(2) and
collector_bus(3) and collector_bus(4) and collector_bus(5) and
collector_bus(6) and collector_bus(7)
);
end architecture;
|
mit
|
1fa8947dce4a4c8c32f8f1d61cd87fc9
| 0.703077 | 2.760085 | false | false | false | false |
makestuff/vhdl
|
serialio/serialio_tb.vhdl
| 1 | 3,251 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity serialio_tb is
end serialio_tb;
architecture behavioural of serialio_tb is
signal reset : std_logic;
signal clk : std_logic;
signal sendData : std_logic_vector(7 downto 0);
signal recvData : std_logic_vector(7 downto 0);
signal load : std_logic;
signal busy : std_logic;
signal sDataOut : std_logic;
signal sDataIn : std_logic;
signal sClk : std_logic;
begin
-- Instantiate the unit under test
uut: entity work.serialio
port map(
reset_in => reset,
clk_in => clk,
data_in => sendData,
data_out => recvData,
load_in => load,
turbo_in => '1',
busy_out => busy,
sData_out => sDataOut,
sData_in => sDataIn,
sClk_out => sClk
);
-- Drive the clock
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
-- Drive the serial interface: send from s/send.txt and receive into r/recv.txt
process
variable inLine, outLine : line;
variable inData, outData : std_logic_vector(7 downto 0);
file inFile : text open read_mode is "stimulus/send.txt";
file outFile : text open write_mode is "results/recv.txt";
begin
sendData <= (others => 'X');
load <= '0';
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 40 ns;
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
sendData <= inData;
load <= '1';
wait for 10 ns;
sendData <= (others => 'X');
load <= '0';
wait until busy = '0';
outData := recvData;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait;
--assert false report "NONE. End of simulation." severity failure;
end process;
-- Mock the serial interface's interlocutor: send from s/recv.txt and receive into r/send.txt
process
variable inLine, outLine : line;
variable inData, outData : std_logic_vector(7 downto 0);
file inFile : text open read_mode is "stimulus/recv.txt";
file outFile : text open write_mode is "results/send.txt";
begin
sDataIn <= 'X';
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
wait until sClk = '0';
sDataIn <= inData(0);
wait until sClk = '1';
outData(0) := sDataOut;
wait until sClk = '0';
sDataIn <= inData(1);
wait until sClk = '1';
outData(1) := sDataOut;
wait until sClk = '0';
sDataIn <= inData(2);
wait until sClk = '1';
outData(2) := sDataOut;
wait until sClk = '0';
sDataIn <= inData(3);
wait until sClk = '1';
outData(3) := sDataOut;
wait until sClk = '0';
sDataIn <= inData(4);
wait until sClk = '1';
outData(4) := sDataOut;
wait until sClk = '0';
sDataIn <= inData(5);
wait until sClk = '1';
outData(5) := sDataOut;
wait until sClk = '0';
sDataIn <= inData(6);
wait until sClk = '1';
outData(6) := sDataOut;
wait until sClk = '0';
sDataIn <= inData(7);
wait until sClk = '1';
outData(7) := sDataOut;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait for 10 ns;
sDataIn <= 'X';
wait;
end process;
end architecture;
|
gpl-3.0
|
ff47831678361c275f1ad7dc275da0fc
| 0.619194 | 3.075686 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/physical/rx_elastic_buffer.vhd
| 1 | 29,427 |
-------------------------------------------------------------------------------
-- Title : SGMII Receiver Elastic Buffer
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : rx_elastic_buffer.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------
-- Description: This is the Receiver Elastic Buffer for the design
-- example of the Virtex-6 Embedded Tri-Mode Ethernet MAC.
--
-- The FIFO is created from distributed memory, is of data
-- width 32 (2 characters wide plus status) and is of depth
-- 64 words. This is twice the size of the elastic buffer
-- in the GTX which has been bypassed,
--
-- When the write clock is a few parts per million faster
-- than the read clock, the occupancy of the FIFO will
-- increase and Idles should be removed.
--
-- When the read clock is a few parts per million faster
-- than the write clock, the occupancy of the FIFO will
-- decrease and Idles should be inserted. The logic in
-- this example design will always insert as many idles as
-- necessary in every Inter-frame Gap period to restore the
-- FIFO occupancy.
--
-- Note: the Idle /I2/ sequence is used as the clock
-- correction character. This is made up from a /K28.5/
-- followed by a /D16.2/ character.
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity rx_elastic_buffer is
port (
-- Signals received from the GTX on RXRECCLK.
rxrecclk : in std_logic;
rxrecreset : in std_logic;
rxchariscomma_rec : in std_logic_vector(1 downto 0);
rxcharisk_rec : in std_logic_vector(1 downto 0);
rxdisperr_rec : in std_logic_vector(1 downto 0);
rxnotintable_rec : in std_logic_vector(1 downto 0);
rxrundisp_rec : in std_logic_vector(1 downto 0);
rxdata_rec : in std_logic_vector(15 downto 0);
-- Signals reclocked onto RXUSRCLK2.
rxusrclk2 : in std_logic;
rxreset : in std_logic;
rxchariscomma_usr : out std_logic;
rxcharisk_usr : out std_logic;
rxdisperr_usr : out std_logic;
rxnotintable_usr : out std_logic;
rxrundisp_usr : out std_logic;
rxclkcorcnt_usr : out std_logic_vector(2 downto 0);
rxbuferr : out std_logic;
rxdata_usr : out std_logic_vector(7 downto 0)
);
end rx_elastic_buffer;
architecture structural of rx_elastic_buffer is
---------------------------------------------------------------------
-- Functions
---------------------------------------------------------------------
-- Convert a binary value into a gray code
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
for i in bin'range loop
if i = bin'left then
gray(i) := bin(i);
else
gray(i) := bin(i+1) xor bin(i);
end if;
end loop; -- i
return gray;
end bin_to_gray;
-- Convert a gray code value into binary
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector is
variable binary : std_logic_vector(gray'range);
begin
for i in gray'high downto gray'low loop
if i = gray'high then
binary(i) := gray(i);
else
binary(i) := binary(i+1) xor gray(i);
end if;
end loop; -- i
return binary;
end gray_to_bin;
---------------------------------------------------------------------
-- Constants to set FIFO thresholds
---------------------------------------------------------------------
-- Upper and Lower thresholds to control clock correction
constant upper_threshold : unsigned := "100001"; -- FIFO occupancy is over this level: clock correction should remove Idles.
constant lower_threshold : unsigned := "011111"; -- FIFO occupancy is less than this level: clock correction should insert Idles.
-- Underflow and Overflow thresholds to control buffer error
constant underflow_threshold : unsigned := "000011"; -- FIFO occupancy is less than this, we consider it to be an underflow.
constant overflow_threshold : unsigned := "111100"; -- FIFO occupancy is greater than this, we consider it to be an overflow.
---------------------------------------------------------------------
-- Signal Declarations
---------------------------------------------------------------------
-- Write domain logic (RXRECCLK)
signal wr_data : std_logic_vector(35 downto 0); -- Formatted the data word from GTX signals.
signal wr_data_reg : std_logic_vector(35 downto 0); -- wr_data registered and formatting completed: to be written to the RAM.
signal wr_addr_plus2 : unsigned(5 downto 0); -- Always ahead of the FIFO write address by 2.
signal wr_addr_plus1 : unsigned(5 downto 0); -- Always ahead of the FIFO write address by 1.
signal wr_addr : unsigned(8 downto 0); -- FIFO write address.
signal addrbwraddr : std_logic_vector(15 downto 0); -- write address organised for RAM input
signal wr_enable : std_logic; -- write enable for FIFO.
signal wr_addr_gray : std_logic_vector(5 downto 0); -- wr_addr is converted to a gray code.
signal wr_rd_addr_gray : std_logic_vector(5 downto 0); -- read address pointer (gray coded) reclocked onto the write clock domain).
signal wr_rd_addr_gray_reg : std_logic_vector(5 downto 0); -- read address pointer (gray coded) registered on write clock for the 2nd time.
signal wr_rd_addr : unsigned(5 downto 0); -- wr_rd_addr_gray converted back to binary (on the write clock domain).
signal wr_occupancy : unsigned(5 downto 0); -- The occupancy of the FIFO in write clock domain.
signal filling : std_logic; -- FIFO is filling up: Idles should be removed.
attribute ASYNC_REG : string;
attribute ASYNC_REG of wr_rd_addr_gray : signal is "TRUE";
signal k28p5_wr : std_logic; -- /K28.5/ character is detected on data prior to FIFO.
signal d16p2_wr : std_logic; -- /D16.2/ character is detected on data prior to FIFO.
signal k28p5_wr_reg : std_logic; -- k28p5_wr registered.
signal d16p2_wr_reg : std_logic; -- d16p2_wr registered.
signal remove_idle : std_logic; -- An Idle is removed before writing it into the FIFO.
-- Read domain logic (RXUSRCLK2)
signal rd_data_ram : std_logic_vector(35 downto 0); -- Date read out of the RAM (before registering).
signal rd_data : std_logic_vector(35 downto 0); -- Date read out of the RAM.
signal rd_data_reg : std_logic_vector(35 downto 0); -- rd_data is registered for logic pipeline.
signal rd_addr_plus2 : unsigned(5 downto 0); -- Always ahead of the FIFO read address by 2.
signal rd_addr_plus1 : unsigned(5 downto 0); -- Always ahead of the FIFO read address by 1.
signal rd_addr : unsigned(8 downto 0); -- FIFO read address.
signal addrardaddr : std_logic_vector(15 downto 0); -- read address organised for RAM input
signal rd_enable : std_logic; -- read enable for FIFO.
signal rd_addr_gray : std_logic_vector(5 downto 0); -- rd_addr is converted to a gray code.
signal rd_wr_addr_gray : std_logic_vector(5 downto 0); -- write address pointer (gray coded) reclocked onto the read clock domain).
signal rd_wr_addr_gray_reg : std_logic_vector(5 downto 0); -- write address pointer (gray coded) registered on read clock for the 2nd time.
signal rd_wr_addr : unsigned(5 downto 0); -- rd_wr_addr_gray converted back to binary (on the read clock domain).
signal rd_occupancy : unsigned(5 downto 0); -- The occupancy of the FIFO in read clock domain.
signal emptying : std_logic; -- FIFO is emptying: Idles should be inserted.
signal overflow : std_logic; -- FIFO has filled up to overflow.
signal underflow : std_logic; -- FIFO has emptied to underflow
attribute ASYNC_REG of rd_wr_addr_gray : signal is "TRUE";
signal even : std_logic; -- To control reading of data from upper or lower half of FIFO word.
signal k28p5_rd : std_logic; -- /K28.5/ character is detected on data post FIFO.
signal d16p2_rd : std_logic; -- /D16.2/ character is detected on data post FIFO.
signal insert_idle : std_logic; -- An Idle is inserted whilst reading it out of the FIFO.
signal insert_idle_reg : std_logic; -- insert_idle is registered.
signal rxclkcorcnt : std_logic_vector(2 downto 0); -- derive RXCLKCORCNT to mimic GTX behaviour.
begin
----------------------------------------------------------------------
-- FIFO write logic (Idles are removed as necessary).
----------------------------------------------------------------------
-- Reclock the GTX data and format for storing in the RAM.
gen_wr_data: process (rxrecclk)
begin
if rxrecclk'event and rxrecclk = '1' then
if rxrecreset = '1' then
wr_data <= (others => '0');
wr_data_reg <= (others => '0');
else
wr_data_reg(35 downto 14) <= wr_data(35 downto 14);
wr_data_reg(13) <= remove_idle;
wr_data_reg(12 downto 0) <= wr_data(12 downto 0);
-- unused parity bits
wr_data(35 downto 32) <= "0000";
-- format the upper word
wr_data(31 downto 29) <= "000"; -- unused
wr_data(28) <= rxchariscomma_rec(0);
wr_data(27) <= rxcharisk_rec(0);
wr_data(26) <= rxdisperr_rec(0);
wr_data(25) <= rxnotintable_rec(0);
wr_data(24) <= rxrundisp_rec(0);
wr_data(23 downto 16) <= rxdata_rec(7 downto 0);
-- format the lower word
wr_data(15 downto 13) <= "000"; -- unused
wr_data(12) <= rxchariscomma_rec(1);
wr_data(11) <= rxcharisk_rec(1);
wr_data(10) <= rxdisperr_rec(1);
wr_data(9) <= rxnotintable_rec(1);
wr_data(8) <= rxrundisp_rec(1);
wr_data(7 downto 0) <= rxdata_rec(15 downto 8);
end if;
end if;
end process gen_wr_data;
-- Detect /K28.5/ character in upper half of the word from GTX
k28p5_wr <= '1' when (wr_data(23 downto 16) = "10111100"
and wr_data(27) = '1') else '0';
-- Detect /D16.2/ character in upper half of the word from GTX
d16p2_wr <= '1' when (wr_data(7 downto 0) = "01010000"
and wr_data(11) = '0') else '0';
-- Create the FIFO write enable: Idles are removed by deasserting the
-- FIFO write_enable whilst an Idle is present on the data.
gen_wr_enable: process (rxrecclk)
begin
if rxrecclk'event and rxrecclk = '1' then
if rxrecreset = '1' then
wr_enable <= '0';
remove_idle <= '0';
k28p5_wr_reg <= '0';
d16p2_wr_reg <= '0';
else
k28p5_wr_reg <= k28p5_wr;
d16p2_wr_reg <= d16p2_wr;
-- Idle removal (always leave the first /I2/ Idle, then every
-- alternate Idle can be removed.
if (k28p5_wr = '1' and d16p2_wr = '1' and
k28p5_wr_reg = '1' and d16p2_wr_reg = '1' and
filling = '1' and remove_idle = '0') then
wr_enable <= '0';
remove_idle <= '1';
-- Else write new word on every clock edge.
else
wr_enable <= '1';
remove_idle <= '0';
end if;
end if;
end if;
end process gen_wr_enable;
-- Create the FIFO write address pointer. Note that wr_addr_plus2
-- will be converted to gray code and passed across the async clock
-- boundary.
gen_wr_addr: process (rxrecclk)
begin
if rxrecclk'event and rxrecclk = '1' then
if rxrecreset = '1' then
wr_addr_plus2 <= "100010";
wr_addr_plus1 <= "100001";
wr_addr(5 downto 0) <= "100000";
else
if wr_enable = '1' then
wr_addr_plus2 <= wr_addr_plus2 + 1;
wr_addr_plus1 <= wr_addr_plus2;
wr_addr(5 downto 0) <= wr_addr_plus1;
end if;
end if;
end if;
end process gen_wr_addr;
-- Not all of the RAM memory is required
wr_addr(8 downto 6) <= "000";
-- Convert look-ahead write address pointer into a gray code
wr_addrgray_bits: process (rxrecclk)
begin
if rxrecclk'event and rxrecclk = '1' then
if rxrecreset = '1' then
wr_addr_gray <= "110001";
else
wr_addr_gray <= bin_to_gray(std_logic_vector(
wr_addr_plus2(5 downto 0)));
end if;
end if;
end process wr_addrgray_bits;
------------------------------------------------------------------------------
-- Instantiate a dual port RAM
------------------------------------------------------------------------------
-- Starting in core version 1.4, the SGMII Fabric Elastic Buffer is now
-- constructed by default using distributed RAM instead of BRAM. This uses
-- extra LUT resources.
-- If a BRAM implementation is prefered, please remove the following code
-- and re-instate the commented out BRAM "RAMB36E1" instantiation which
-- immediately follows.
GEN_FIFO : for I in 35 downto 0 generate
DIST_RAM: RAM64X1D
port map (
D => wr_data_reg(I),
WE => wr_enable,
WCLK => rxrecclk,
A0 => wr_addr(0),
A1 => wr_addr(1),
A2 => wr_addr(2),
A3 => wr_addr(3),
A4 => wr_addr(4),
A5 => wr_addr(5),
DPRA0 => rd_addr(0),
DPRA1 => rd_addr(1),
DPRA2 => rd_addr(2),
DPRA3 => rd_addr(3),
DPRA4 => rd_addr(4),
DPRA5 => rd_addr(5),
SPO => open,
DPO => rd_data_ram(I)
);
-- Register the distributed RAM read data.
reg_rd_data_ram: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rd_data(I) <= '0';
else
rd_data(I) <= rd_data_ram(I);
end if;
end if;
end process reg_rd_data_ram;
end generate;
--addrardaddr <= "00" & std_logic_vector(rd_addr) & "00000";
--addrbwraddr <= "00" & std_logic_vector(wr_addr) & "00000";
--dual_port_block_ram : RAMB36E1
--generic map (
-- DOA_REG => 0,
-- DOB_REG => 0,
-- EN_ECC_READ => FALSE,
-- EN_ECC_WRITE => FALSE,
-- INIT_A => X"000000000",
-- INIT_B => X"000000000",
-- INIT_FILE => "NONE",
-- RAM_EXTENSION_A => "NONE",
-- RAM_EXTENSION_B => "NONE",
-- RAM_MODE => "TDP",
-- READ_WIDTH_A => 36,
-- READ_WIDTH_B => 0,
-- RSTREG_PRIORITY_A => "RSTREG",
-- RSTREG_PRIORITY_B => "RSTREG",
-- SIM_COLLISION_CHECK => "ALL",
-- SRVAL_A => X"000000000",
-- SRVAL_B => X"000000000",
-- WRITE_WIDTH_A => 0,
-- WRITE_WIDTH_B => 36,
-- WRITE_MODE_A => "WRITE_FIRST",
-- WRITE_MODE_B => "WRITE_FIRST"
--)
--port map (
-- CASCADEOUTA => open,
-- CASCADEOUTB => open,
-- DBITERR => open,
-- DOADO => rd_data(31 downto 0),
-- DOBDO => open,
-- DOPADOP => rd_data(35 downto 32),
-- DOPBDOP => open,
-- ECCPARITY => open,
-- RDADDRECC => open,
-- SBITERR => open,
-- ADDRARDADDR => addrardaddr,
-- ADDRBWRADDR => addrbwraddr,
-- CASCADEINA => '0',
-- CASCADEINB => '0',
-- CLKARDCLK => rxusrclk2,
-- CLKBWRCLK => rxrecclk,
-- DIADI => (others => '0'),
-- DIBDI => wr_data_reg(31 downto 0),
-- DIPADIP => (others => '0'),
-- DIPBDIP => wr_data_reg(35 downto 32),
-- ENARDEN => '1',
-- ENBWREN => '1',
-- INJECTDBITERR => '0',
-- INJECTSBITERR => '0',
-- REGCEAREGCE => '0',
-- REGCEB => '0',
-- RSTRAMARSTRAM => '0',
-- RSTRAMB => '0',
-- RSTREGARSTREG => '0',
-- RSTREGB => '0',
-- WEA => "0000",
-- WEBWE(0) => wr_enable,
-- WEBWE(1) => wr_enable,
-- WEBWE(2) => wr_enable,
-- WEBWE(3) => wr_enable,
-- WEBWE(7 downto 4) => "0000"
--);
----------------------------------------------------------------------
-- FIFO read logic (Idles are insterted as necessary).
----------------------------------------------------------------------
-- Register the RAM data.
reg_rd_data: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rd_data_reg <= (others => '0');
elsif rd_enable = '1' then
rd_data_reg <= rd_data;
end if;
end if;
end process reg_rd_data;
-- Detect /K28.5/ character in upper half of the word read from FIFO
k28p5_rd <= '1' when (rd_data(23 downto 16) = "10111100"
and rd_data(27) = '1') else '0';
-- Detect /D16.2/ character in lower half of the word read from FIFO
d16p2_rd <= '1' when (rd_data(7 downto 0) = "01010000"
and rd_data(11) = '0') else '0';
-- Create the FIFO read enable: Idles are inserted by pausing the
-- FIFO read_enable whilst an Idle is present on the data.
gen_rd_enable: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
even <= '1';
rd_enable <= '0';
insert_idle <= '0';
insert_idle_reg <= '0';
else
even <= (not even);
insert_idle_reg <= insert_idle;
-- Repeat as many /I2/ code groups as required if nearly
-- empty by pausing rd_enable.
if (k28p5_rd = '1' and d16p2_rd = '1' and emptying = '1') then
rd_enable <= '0';
insert_idle <= even;
-- Else read out a new word on every alternative clock edge.
else
rd_enable <= even;
insert_idle <= '0';
end if;
end if;
end if;
end process gen_rd_enable;
-- Create the FIFO read address pointer. Note that rd_addr_plus2
-- will be converted to gray code and passed across the async clock
-- boundary.
gen_rd_addr: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rd_addr_plus2 <= "000010";
rd_addr_plus1 <= "000001";
rd_addr(5 downto 0) <= "000000";
elsif rd_enable = '1' then
rd_addr_plus2 <= rd_addr_plus2 + 1;
rd_addr_plus1 <= rd_addr_plus2;
rd_addr(5 downto 0) <= rd_addr_plus1;
end if;
end if;
end process gen_rd_addr;
-- Not all of the RAM memory is required
rd_addr(8 downto 6) <= "000";
-- Convert look-ahead read address pointer into a gray code
rd_addrgray_bits: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rd_addr_gray <= (others => '0');
else
rd_addr_gray <= bin_to_gray(std_logic_vector(
rd_addr_plus2(5 downto 0)));
end if;
end if;
end process rd_addrgray_bits;
-- Multiplex the double width FIFO words to single words.
gen_mux: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rxchariscomma_usr <= '0';
rxcharisk_usr <= '0';
rxdisperr_usr <= '0';
rxnotintable_usr <= '0';
rxrundisp_usr <= '0';
rxdata_usr <= X"00";
else
if even = '1' then
rxchariscomma_usr <= rd_data_reg(28);
rxcharisk_usr <= rd_data_reg(27);
rxdisperr_usr <= rd_data_reg(26);
rxnotintable_usr <= rd_data_reg(25);
rxrundisp_usr <= rd_data_reg(24);
rxdata_usr <= rd_data_reg(23 downto 16);
else
rxchariscomma_usr <= rd_data_reg(12);
rxcharisk_usr <= rd_data_reg(11);
rxdisperr_usr <= rd_data_reg(10);
rxnotintable_usr <= rd_data_reg(9);
rxrundisp_usr <= rd_data_reg(8);
rxdata_usr <= rd_data_reg(7 downto 0);
end if;
end if;
end if;
end process gen_mux;
-- Create GTX style clock correction status when inserting /
-- removing Idles.
gen_rxclkcorcnt: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rxclkcorcnt <= "000";
else
if rd_data_reg(13) = '1' and rxclkcorcnt(0) = '0' then
rxclkcorcnt <= "001";
elsif insert_idle_reg = '1' then
rxclkcorcnt <= "111";
else
rxclkcorcnt <= "000";
end if;
end if;
end if;
end process gen_rxclkcorcnt;
rxclkcorcnt_usr <= rxclkcorcnt;
----------------------------------------------------------------------
-- Create emptying/full thresholds in read clock domain.
----------------------------------------------------------------------
-- Reclock the write address pointer (gray code) onto the read domain.
-- By reclocking the gray code, the worst case senario is that
-- the reclocked value is only in error by -1, since only 1 bit at a
-- time changes between gray code increments.
reclock_wr_addrgray: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rd_wr_addr_gray <= "110001";
rd_wr_addr_gray_reg <= "110000";
else
rd_wr_addr_gray <= wr_addr_gray;
rd_wr_addr_gray_reg <= rd_wr_addr_gray;
end if;
end if;
end process reclock_wr_addrgray;
-- Convert the resync'd Write Address Pointer grey code back to binary
rd_wr_addr <=unsigned(gray_to_bin(std_logic_vector(rd_wr_addr_gray_reg)));
--Determine the occupancy of the FIFO as observed in the read domain.
gen_rd_occupancy: process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rd_occupancy <= "100000";
else
rd_occupancy <= rd_wr_addr - rd_addr(5 downto 0);
end if;
end if;
end process gen_rd_occupancy;
-- Set emptying flag if FIFO occupancy is less than LOWER_THRESHOLD.
gen_emptying : process (rd_occupancy)
begin
if rd_occupancy < lower_threshold then
emptying <= '1';
else
emptying <= '0';
end if;
end process gen_emptying;
-- Set underflow if FIFO occupancy is less than UNDERFLOW_THRESHOLD.
gen_underflow : process (rd_occupancy)
begin
if rd_occupancy < underflow_threshold then
underflow <= '1';
else
underflow <= '0';
end if;
end process gen_underflow;
-- Set overflow if FIFO occupancy is less than OVERFLOW_THRESHOLD.
gen_overflow : process (rd_occupancy)
begin
if rd_occupancy > overflow_threshold then
overflow <= '1';
else
overflow <= '0';
end if;
end process gen_overflow;
-- If either an underflow or overflow, assert the buffer error signal.
-- Like the GTX, this will persist until a reset is issued.
gen_buffer_error : process (rxusrclk2)
begin
if rxusrclk2'event and rxusrclk2 = '1' then
if rxreset = '1' then
rxbuferr <= '0';
elsif (overflow or underflow) = '1' then
rxbuferr <= '1';
end if;
end if;
end process gen_buffer_error;
----------------------------------------------------------------------
-- Create emptying/full thresholds in write clock domain.
----------------------------------------------------------------------
-- Reclock the read address pointer (gray code) onto the write domain.
-- By reclocking the gray code, the worst case senario is that
-- the reclocked value is only in error by -1, since only 1 bit at a
-- time changes between gray code increments.
reclock_rd_addrgray: process (rxrecclk)
begin
if rxrecclk'event and rxrecclk = '1' then
if rxrecreset = '1' then
wr_rd_addr_gray <= (others => '0');
wr_rd_addr_gray_reg <= (others => '0');
else
wr_rd_addr_gray <= rd_addr_gray;
wr_rd_addr_gray_reg <= wr_rd_addr_gray;
end if;
end if;
end process reclock_rd_addrgray;
-- Convert the resync'd Read Address Pointer grey code back to binary
wr_rd_addr <=unsigned(gray_to_bin(std_logic_vector(wr_rd_addr_gray_reg)));
--Determine the occupancy of the FIFO as observed in the write domain.
gen_wr_occupancy: process (rxrecclk)
begin
if rxrecclk'event and rxrecclk = '1' then
if rxrecreset = '1' then
wr_occupancy <= "100000";
else
wr_occupancy <= wr_addr(5 downto 0) - wr_rd_addr;
end if;
end if;
end process gen_wr_occupancy;
-- Set filling flag if FIFO occupancy is greated than UPPER_THRESHOLD.
gen_filling : process (wr_occupancy)
begin
if wr_occupancy > upper_threshold then
filling <= '1';
else
filling <= '0';
end if;
end process gen_filling;
end structural;
|
gpl-3.0
|
b6ca487793cd84b536ac03baac3a2184
| 0.534917 | 4.049959 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/v6_emac_v1_4_locallink.vhd
| 1 | 20,150 |
-------------------------------------------------------------------------------
-- Title : LocalLink-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : v6_emac_v1_4_locallink.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Description: This is the LocalLink-level wrapper for the Virtex-6
-- Embedded Tri-Mode Ethernet MAC. It is intended that this
-- example design can be quickly adapted and downloaded onto an
-- FPGA to provide a hardware test environment.
--
-- The LocalLink-level wrapper:
--
-- * instantiates the EMAC block-level wrapper (the EMAC
-- instance-level wrapper with the physical interface logic);
--
-- * instantiates TX and RX reference design FIFOs with
-- a LocalLink interface.
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
-- further information.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Entity declaration for the LocalLink-level wrapper
-------------------------------------------------------------------------------
entity v6_emac_v1_4_locallink is
port(
-- 125MHz clock output from transceiver
CLK125_OUT : out std_logic;
-- 125MHz clock input from BUFG
CLK125 : in std_logic;
-- LocalLink receiver interface
RX_LL_CLOCK : in std_logic;
RX_LL_RESET : in std_logic;
RX_LL_DATA : out std_logic_vector(7 downto 0);
RX_LL_SOF_N : out std_logic;
RX_LL_EOF_N : out std_logic;
RX_LL_SRC_RDY_N : out std_logic;
RX_LL_DST_RDY_N : in std_logic;
RX_LL_FIFO_STATUS : out std_logic_vector(3 downto 0);
-- LocalLink transmitter interface
TX_LL_CLOCK : in std_logic;
TX_LL_RESET : in std_logic;
TX_LL_DATA : in std_logic_vector(7 downto 0);
TX_LL_SOF_N : in std_logic;
TX_LL_EOF_N : in std_logic;
TX_LL_SRC_RDY_N : in std_logic;
TX_LL_DST_RDY_N : out std_logic;
-- Client receiver interface
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
--EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
EMACANINTERRUPT : out std_logic;
-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
RESETDONE : out std_logic;
-- SGMII transceiver clock buffer input
CLK_DS : in std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end v6_emac_v1_4_locallink;
architecture TOP_LEVEL of v6_emac_v1_4_locallink is
-------------------------------------------------------------------------------
-- Component declarations for lower hierarchial level entities
-------------------------------------------------------------------------------
-- Component declaration for the block-level wrapper
component v6_emac_v1_4_block is
port(
-- 125MHz clock output from transceiver
CLK125_OUT : out std_logic;
-- 125MHz clock input from BUFG
CLK125 : in std_logic;
-- Client receiver interface
EMACCLIENTRXD : out std_logic_vector(7 downto 0);
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXGOODFRAME : out std_logic;
EMACCLIENTRXBADFRAME : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client transmitter interface
CLIENTEMACTXD : in std_logic_vector(7 downto 0);
CLIENTEMACTXDVLD : in std_logic;
EMACCLIENTTXACK : out std_logic;
CLIENTEMACTXFIRSTBYTE : in std_logic;
CLIENTEMACTXUNDERRUN : in std_logic;
EMACCLIENTTXCOLLISION : out std_logic;
EMACCLIENTTXRETRANSMIT : out std_logic;
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
--EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
EMACANINTERRUPT : out std_logic;
-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
RESETDONE : out std_logic;
-- SGMII transceiver clock buffer input
CLK_DS : in std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end component;
-- Component declaration for the client-side FIFO
component eth_fifo_8
generic (
FULL_DUPLEX_ONLY : boolean);
port (
-- EMAC transmitter client interface
tx_clk : in std_logic;
tx_reset : in std_logic;
tx_enable : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
tx_data_valid : out std_logic;
tx_ack : in std_logic;
tx_underrun : out std_logic;
tx_collision : in std_logic;
tx_retransmit : in std_logic;
-- Transmitter LocalLink interface
tx_ll_clock : in std_logic;
tx_ll_reset : in std_logic;
tx_ll_data_in : in std_logic_vector(7 downto 0);
tx_ll_sof_in_n : in std_logic;
tx_ll_eof_in_n : in std_logic;
tx_ll_src_rdy_in_n : in std_logic;
tx_ll_dst_rdy_out_n : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_overflow : out std_logic;
-- EMAC receiver client interface
rx_clk : in std_logic;
rx_reset : in std_logic;
rx_enable : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_data_valid : in std_logic;
rx_good_frame : in std_logic;
rx_bad_frame : in std_logic;
rx_overflow : out std_logic;
-- Receiver LocalLink interface
rx_ll_clock : in std_logic;
rx_ll_reset : in std_logic;
rx_ll_data_out : out std_logic_vector(7 downto 0);
rx_ll_sof_out_n : out std_logic;
rx_ll_eof_out_n : out std_logic;
rx_ll_src_rdy_out_n : out std_logic;
rx_ll_dst_rdy_in_n : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0)
);
end component;
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
-- Global asynchronous reset
signal reset_i : std_logic;
-- Client interface clocking signals
signal tx_clk_i : std_logic;
signal rx_clk_i : std_logic;
-- Internal client interface connections
-- Transmitter interface
signal tx_data_i : std_logic_vector(7 downto 0);
signal tx_data_valid_i : std_logic;
signal tx_underrun_i : std_logic;
signal tx_ack_i : std_logic;
signal tx_collision_i : std_logic;
signal tx_retransmit_i : std_logic;
-- Receiver interface
signal rx_data_i : std_logic_vector(7 downto 0);
signal rx_data_valid_i : std_logic;
signal rx_good_frame_i : std_logic;
signal rx_bad_frame_i : std_logic;
-- Registers for the EMAC receiver output
signal rx_data_r : std_logic_vector(7 downto 0);
signal rx_data_valid_r : std_logic;
signal rx_good_frame_r : std_logic;
signal rx_bad_frame_r : std_logic;
-- Synchronous reset registers in the transmitter clock domain
signal tx_pre_reset_i : std_logic_vector(5 downto 0);
signal tx_reset_i : std_logic;
-- Synchronous reset registers in the receiver clock domain
signal rx_pre_reset_i : std_logic_vector(5 downto 0);
signal rx_reset_i : std_logic;
attribute async_reg : string;
attribute async_reg of rx_pre_reset_i : signal is "true";
attribute async_reg of tx_pre_reset_i : signal is "true";
attribute keep : string;
attribute keep of tx_data_i : signal is "true";
attribute keep of tx_data_valid_i : signal is "true";
attribute keep of tx_ack_i : signal is "true";
attribute keep of rx_data_i : signal is "true";
attribute keep of rx_data_valid_i : signal is "true";
-- Reset signals from the transceiver
signal resetdone_i : std_logic;
signal resetdone_tx_r : std_logic;
signal resetdone_rx_r : std_logic;
attribute async_reg of resetdone_tx_r : signal is "true";
attribute async_reg of resetdone_rx_r : signal is "true";
-------------------------------------------------------------------------------
-- Main body of code
-------------------------------------------------------------------------------
begin
-- Asynchronous reset input
reset_i <= RESET;
--------------------------------------------------------------------------
-- Instantiate the block-level wrapper (v6_emac_v1_4_block.vhd)
--------------------------------------------------------------------------
v6_emac_v1_4_block_inst : v6_emac_v1_4_block
port map (
-- 125MHz clock output from transceiver
CLK125_OUT => CLK125_OUT,
-- 125MHz clock input from BUFG
CLK125 => CLK125,
-- Client receiver interface
EMACCLIENTRXD => rx_data_i,
EMACCLIENTRXDVLD => rx_data_valid_i,
EMACCLIENTRXGOODFRAME => rx_good_frame_i,
EMACCLIENTRXBADFRAME => rx_bad_frame_i,
EMACCLIENTRXFRAMEDROP => EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS => EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD => EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD => EMACCLIENTRXSTATSBYTEVLD,
-- Client transmitter interface
CLIENTEMACTXD => tx_data_i,
CLIENTEMACTXDVLD => tx_data_valid_i,
EMACCLIENTTXACK => tx_ack_i,
CLIENTEMACTXFIRSTBYTE => '0',
CLIENTEMACTXUNDERRUN => tx_underrun_i,
EMACCLIENTTXCOLLISION => tx_collision_i,
EMACCLIENTTXRETRANSMIT => tx_retransmit_i,
CLIENTEMACTXIFGDELAY => CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS => EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD => EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD => EMACCLIENTTXSTATSBYTEVLD,
-- MAC control interface
CLIENTEMACPAUSEREQ => CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL => CLIENTEMACPAUSEVAL,
--EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS => EMACCLIENTSYNCACQSTATUS,
EMACANINTERRUPT => EMACANINTERRUPT,
-- SGMII interface
TXP => TXP,
TXN => TXN,
RXP => RXP,
RXN => RXN,
PHYAD => PHYAD,
RESETDONE => resetdone_i,
-- SGMII transceiver clock buffer input
CLK_DS => CLK_DS,
-- Asynchronous reset
RESET => reset_i
);
----------------------------------------------------------------------
-- Instantiate the client-side FIFO
----------------------------------------------------------------------
client_side_FIFO : eth_fifo_8
generic map (
FULL_DUPLEX_ONLY => false)
port map (
-- EMAC transmitter client interface
tx_clk => tx_clk_i,
tx_reset => tx_reset_i,
tx_enable => '1',
tx_data => tx_data_i,
tx_data_valid => tx_data_valid_i,
tx_ack => tx_ack_i,
tx_underrun => tx_underrun_i,
tx_collision => tx_collision_i,
tx_retransmit => tx_retransmit_i,
-- Transmitter LocalLink interface
tx_ll_clock => TX_LL_CLOCK,
tx_ll_reset => TX_LL_RESET,
tx_ll_data_in => TX_LL_DATA,
tx_ll_sof_in_n => TX_LL_SOF_N,
tx_ll_eof_in_n => TX_LL_EOF_N,
tx_ll_src_rdy_in_n => TX_LL_SRC_RDY_N,
tx_ll_dst_rdy_out_n => TX_LL_DST_RDY_N,
tx_fifo_status => open,
tx_overflow => open,
-- EMAC receiver client interface
rx_clk => rx_clk_i,
rx_reset => rx_reset_i,
rx_enable => '1',
rx_data => rx_data_r,
rx_data_valid => rx_data_valid_r,
rx_good_frame => rx_good_frame_r,
rx_bad_frame => rx_bad_frame_r,
rx_overflow => open,
-- Receiver LocalLink interface
rx_ll_clock => RX_LL_CLOCK,
rx_ll_reset => RX_LL_RESET,
rx_ll_data_out => RX_LL_DATA,
rx_ll_sof_out_n => RX_LL_SOF_N,
rx_ll_eof_out_n => RX_LL_EOF_N,
rx_ll_src_rdy_out_n => RX_LL_SRC_RDY_N,
rx_ll_dst_rdy_in_n => RX_LL_DST_RDY_N,
rx_fifo_status => RX_LL_FIFO_STATUS
);
---------------------------------------------------------------------
-- Additional synchronization, pipelining, and clock assignments
---------------------------------------------------------------------
-- Synchronize resetdone_i from the GT in the transmitter clock domain
gen_resetdone_tx_r : process(tx_clk_i, reset_i)
begin
if (reset_i = '1') then
resetdone_tx_r <= '0';
elsif tx_clk_i'event and tx_clk_i = '1' then
resetdone_tx_r <= resetdone_i;
end if;
end process gen_resetdone_tx_r;
-- Synchronize resetdone_i from the GT in the receiver clock domain
gen_resetdone_rx_r : process(rx_clk_i, reset_i)
begin
if (reset_i = '1') then
resetdone_rx_r <= '0';
elsif rx_clk_i'event and rx_clk_i = '1' then
resetdone_rx_r <= resetdone_i;
end if;
end process gen_resetdone_rx_r;
-- Create synchronous reset in the transmitter clock domain
gen_tx_reset : process (tx_clk_i, reset_i)
begin
if reset_i = '1' then
tx_pre_reset_i <= (others => '1');
tx_reset_i <= '1';
elsif tx_clk_i'event and tx_clk_i = '1' then
if resetdone_tx_r = '1' then
tx_pre_reset_i(0) <= '0';
tx_pre_reset_i(5 downto 1) <= tx_pre_reset_i(4 downto 0);
tx_reset_i <= tx_pre_reset_i(5);
end if;
end if;
end process gen_tx_reset;
-- Create synchronous reset in the receiver clock domain
gen_rx_reset : process (rx_clk_i, reset_i)
begin
if reset_i = '1' then
rx_pre_reset_i <= (others => '1');
rx_reset_i <= '1';
elsif rx_clk_i'event and rx_clk_i = '1' then
if resetdone_rx_r = '1' then
rx_pre_reset_i(0) <= '0';
rx_pre_reset_i(5 downto 1) <= rx_pre_reset_i(4 downto 0);
rx_reset_i <= rx_pre_reset_i(5);
end if;
end if;
end process gen_rx_reset;
-- Register the receiver outputs before routing to the FIFO
regipgen : process(rx_clk_i, reset_i)
begin
if reset_i = '1' then
rx_data_r <= (others => '0');
rx_data_valid_r <= '0';
rx_good_frame_r <= '0';
rx_bad_frame_r <= '0';
elsif rx_clk_i'event and rx_clk_i = '1' then
if resetdone_rx_r = '1' then
rx_data_r <= rx_data_i;
rx_data_valid_r <= rx_data_valid_i;
rx_good_frame_r <= rx_good_frame_i;
rx_bad_frame_r <= rx_bad_frame_i;
end if;
end if;
end process regipgen;
EMACCLIENTRXDVLD <= rx_data_valid_i;
-- Clocking assignments
tx_clk_i <= CLK125;
rx_clk_i <= CLK125;
RESETDONE <= resetdone_i;
end TOP_LEVEL;
|
gpl-3.0
|
a54c0b9ccb8d21d76a65e639aceee6a2
| 0.534491 | 4.211957 | false | false | false | false |
makestuff/vhdl
|
package/toplevel.vhdl
| 1 | 1,143 |
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use work.gate_pkg.all;
entity toplevel is
port(
op_in : in std_logic;
a_in : in std_logic;
b_in : in std_logic;
x_out : out std_logic
);
end entity;
architecture structural of toplevel is
signal op : Operation;
begin
u1: entity work.gate
port map(
op_in => op,
a_in => a_in,
b_in => b_in,
x_out => x_out
);
op <=
OP_AND when op_in = '1' else
OP_OR;
end architecture;
|
gpl-3.0
|
2d2da51736d87aad4735e0cb6a8f02a4
| 0.693788 | 3.265714 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/GPIO/src/hdl/GPIO_Demo.vhd
| 1 | 17,247 |
----------------------------------------------------------------------------
-- GPIO_Demo.vhd -- Nexys4DDR GPIO/UART Demonstration Project
----------------------------------------------------------------------------
-- Author: Marshall Wingerson Adapted from Sam Bobrowicz
-- Copyright 2013 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- The GPIO/UART Demo project demonstrates a simple usage of the Nexys4DDR's
-- GPIO and UART. The behavior is as follows:
--
-- *The 16 User LEDs are tied to the 16 User Switches. While the center
-- User button is pressed, the LEDs are instead tied to GND
-- *The 7-Segment display counts from 0 to 9 on each of its 8
-- digits. This count is reset when the center button is pressed.
-- Also, single anodes of the 7-Segment display are blanked by
-- holding BTNU, BTNL, BTND, or BTNR. Holding the center button
-- blanks all the 7-Segment anodes.
-- *An introduction message is sent across the UART when the device
-- is finished being configured, and after the center User button
-- is pressed.
-- *A message is sent over UART whenever BTNU, BTNL, BTND, or BTNR is
-- pressed.
-- *The Tri-Color LEDs cycle through several colors in a ~4 second loop
-- *Data from the microphone is collected and transmitted over the mono
-- audio out port.
-- *Note that the center user button behaves as a user reset button
-- and is referred to as such in the code comments below
--
-- All UART communication can be captured by attaching the UART port to a
-- computer running a Terminal program with 9600 Baud Rate, 8 data bits, no
-- parity, and 1 stop bit.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
-- 08/27/2013(MarshallW): Modified for the Nexys4 with Xilinx ISE 14.4\
-- --added RGB and microphone
-- 12/10/2014(SamB): Ported to Nexys4DDR and updated to Vivado 2014.4
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--The IEEE.std_logic_unsigned contains definitions that allow
--std_logic_vector types to be used with the + operator to instantiate a
--counter.
use IEEE.std_logic_unsigned.all;
entity GPIO_demo is
Port ( SW : in STD_LOGIC_VECTOR (15 downto 0);
BTN : in STD_LOGIC_VECTOR (4 downto 0);
CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (15 downto 0);
SSEG_CA : out STD_LOGIC_VECTOR (7 downto 0);
SSEG_AN : out STD_LOGIC_VECTOR (7 downto 0);
UART_TXD : out STD_LOGIC;
RGB1_Red : out STD_LOGIC;
RGB1_Green : out STD_LOGIC;
RGB1_Blue : out STD_LOGIC;
RGB2_Red : out STD_LOGIC;
RGB2_Green : out STD_LOGIC;
RGB2_Blue : out STD_LOGIC;
micClk : out STD_LOGIC;
micLRSel : out STD_LOGIC;
micData : in STD_LOGIC;
ampPWM : out STD_LOGIC;
ampSD : out STD_LOGIC
);
end GPIO_demo;
architecture Behavioral of GPIO_demo is
component UART_TX_CTRL
Port(
SEND : in std_logic;
DATA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
READY : out std_logic;
UART_TX : out std_logic
);
end component;
component debouncer
Generic(
DEBNC_CLOCKS : integer;
PORT_WIDTH : integer);
Port(
SIGNAL_I : in std_logic_vector(4 downto 0);
CLK_I : in std_logic;
SIGNAL_O : out std_logic_vector(4 downto 0)
);
end component;
component RGB_controller
Port(
GCLK : in std_logic;
RGB_LED_1_O : out std_logic_vector(2 downto 0);
RGB_LED_2_O : out std_logic_vector(2 downto 0)
);
end component;
--The type definition for the UART state machine type. Here is a description of what
--occurs during each state:
-- RST_REG -- Do Nothing. This state is entered after configuration or a user reset.
-- The state is set to LD_INIT_STR.
-- LD_INIT_STR -- The Welcome String is loaded into the sendStr variable and the strIndex
-- variable is set to zero. The welcome string length is stored in the StrEnd
-- variable. The state is set to SEND_CHAR.
-- SEND_CHAR -- uartSend is set high for a single clock cycle, signaling the character
-- data at sendStr(strIndex) to be registered by the UART_TX_CTRL at the next
-- cycle. Also, strIndex is incremented (behaves as if it were post
-- incremented after reading the sendStr data). The state is set to RDY_LOW.
-- RDY_LOW -- Do nothing. Wait for the READY signal from the UART_TX_CTRL to go low,
-- indicating a send operation has begun. State is set to WAIT_RDY.
-- WAIT_RDY -- Do nothing. Wait for the READY signal from the UART_TX_CTRL to go high,
-- indicating a send operation has finished. If READY is high and strEnd =
-- StrIndex then state is set to WAIT_BTN, else if READY is high and strEnd /=
-- StrIndex then state is set to SEND_CHAR.
-- WAIT_BTN -- Do nothing. Wait for a button press on BTNU, BTNL, BTND, or BTNR. If a
-- button press is detected, set the state to LD_BTN_STR.
-- LD_BTN_STR -- The Button String is loaded into the sendStr variable and the strIndex
-- variable is set to zero. The button string length is stored in the StrEnd
-- variable. The state is set to SEND_CHAR.
type UART_STATE_TYPE is (RST_REG, LD_INIT_STR, SEND_CHAR, RDY_LOW, WAIT_RDY, WAIT_BTN, LD_BTN_STR);
--The CHAR_ARRAY type is a variable length array of 8 bit std_logic_vectors.
--Each std_logic_vector contains an ASCII value and represents a character in
--a string. The character at index 0 is meant to represent the first
--character of the string, the character at index 1 is meant to represent the
--second character of the string, and so on.
type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0);
constant TMR_CNTR_MAX : std_logic_vector(26 downto 0) := "101111101011110000100000000"; --100,000,000 = clk cycles per second
constant TMR_VAL_MAX : std_logic_vector(3 downto 0) := "1001"; --9
constant RESET_CNTR_MAX : std_logic_vector(17 downto 0) := "110000110101000000";-- 100,000,000 * 0.002 = 200,000 = clk cycles per 2 ms
constant MAX_STR_LEN : integer := 31;
constant WELCOME_STR_LEN : natural := 31;
constant BTN_STR_LEN : natural := 24;
--Welcome string definition. Note that the values stored at each index
--are the ASCII values of the indicated character.
constant WELCOME_STR : CHAR_ARRAY(0 to 30) := (X"0A", --\n
X"0D", --\r
X"4E", --N
X"45", --E
X"58", --X
X"59", --Y
X"53", --S
X"34", --4
X"20", --
X"44", --D
X"44", --D
X"52", --R
X"20", --
X"47", --G
X"50", --P
X"49", --I
X"4F", --O
X"2F", --/
X"55", --U
X"41", --A
X"52", --R
X"54", --T
X"20", --
X"44", --D
X"45", --E
X"4D", --M
X"4F", --O
X"21", --!
X"0A", --\n
X"0A", --\n
X"0D"); --\r
--Button press string definition.
constant BTN_STR : CHAR_ARRAY(0 to 23) := (X"42", --B
X"75", --u
X"74", --t
X"74", --t
X"6F", --o
X"6E", --n
X"20", --
X"70", --p
X"72", --r
X"65", --e
X"73", --s
X"73", --s
X"20", --
X"64", --d
X"65", --e
X"74", --t
X"65", --e
X"63", --c
X"74", --t
X"65", --e
X"64", --d
X"21", --!
X"0A", --\n
X"0D"); --\r
--This is used to determine when the 7-segment display should be
--incremented
signal tmrCntr : std_logic_vector(26 downto 0) := (others => '0');
--This counter keeps track of which number is currently being displayed
--on the 7-segment.
signal tmrVal : std_logic_vector(3 downto 0) := (others => '0');
--Contains the current string being sent over uart.
signal sendStr : CHAR_ARRAY(0 to (MAX_STR_LEN - 1));
--Contains the length of the current string being sent over uart.
signal strEnd : natural;
--Contains the index of the next character to be sent over uart
--within the sendStr variable.
signal strIndex : natural;
--Used to determine when a button press has occured
signal btnReg : std_logic_vector (3 downto 0) := "0000";
signal btnDetect : std_logic;
--UART_TX_CTRL control signals
signal uartRdy : std_logic;
signal uartSend : std_logic := '0';
signal uartData : std_logic_vector (7 downto 0):= "00000000";
signal uartTX : std_logic;
--Current uart state signal
signal uartState : UART_STATE_TYPE := RST_REG;
--Debounced btn signals used to prevent single button presses
--from being interpreted as multiple button presses.
signal btnDeBnc : std_logic_vector(4 downto 0);
signal clk_cntr_reg : std_logic_vector (4 downto 0) := (others=>'0');
signal pwm_val_reg : std_logic := '0';
--this counter counts the amount of time paused in the UART reset state
signal reset_cntr : std_logic_vector (17 downto 0) := (others=>'0');
begin
----------------------------------------------------------
------ LED Control -------
----------------------------------------------------------
with BTN(4) select
LED <= SW when '0',
"0000000000000000" when others;
----------------------------------------------------------
------ 7-Seg Display Control -------
----------------------------------------------------------
--Digits are incremented every second, and are blanked in
--response to button presses.
--Individual and reset blanking of Anodes
with BTN(4) select
SSEG_AN(3 downto 0) <= btnDeBnc(3 downto 0) when '0',
"1111" when others;
with BTN(4) select
SSEG_AN(7 downto 4) <= btnDeBnc(3 downto 0) when '0',
"1111" when others;
--This process controls the counter that triggers the 7-segment
--to be incremented. It counts 100,000,000 and then resets.
timer_counter_process : process (CLK)
begin
if (rising_edge(CLK)) then
if ((tmrCntr = TMR_CNTR_MAX) or (BTN(4) = '1')) then
tmrCntr <= (others => '0');
else
tmrCntr <= tmrCntr + 1;
end if;
end if;
end process;
--This process increments the digit being displayed on the
--7-segment display every second.
timer_inc_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (BTN(4) = '1') then
tmrVal <= (others => '0');
elsif (tmrCntr = TMR_CNTR_MAX) then
if (tmrVal = TMR_VAL_MAX) then
tmrVal <= (others => '0');
else
tmrVal <= tmrVal + 1;
end if;
end if;
end if;
end process;
--This select statement encodes the value of tmrVal to the necessary
--cathode signals to display it on the 7-segment
with tmrVal select
SSEG_CA <= "11000000" when "0000",
"11111001" when "0001",
"10100100" when "0010",
"10110000" when "0011",
"10011001" when "0100",
"10010010" when "0101",
"10000010" when "0110",
"11111000" when "0111",
"10000000" when "1000",
"10010000" when "1001",
"11111111" when others;
----------------------------------------------------------
------ Button Control -------
----------------------------------------------------------
--Buttons are debounced and their rising edges are detected
--to trigger UART messages
--Debounces btn signals
Inst_btn_debounce: debouncer
generic map(
DEBNC_CLOCKS => (2**16),
PORT_WIDTH => 5)
port map(
SIGNAL_I => BTN,
CLK_I => CLK,
SIGNAL_O => btnDeBnc
);
--Registers the debounced button signals, for edge detection.
btn_reg_process : process (CLK)
begin
if (rising_edge(CLK)) then
btnReg <= btnDeBnc(3 downto 0);
end if;
end process;
--btnDetect goes high for a single clock cycle when a btn press is
--detected. This triggers a UART message to begin being sent.
btnDetect <= '1' when ((btnReg(0)='0' and btnDeBnc(0)='1') or
(btnReg(1)='0' and btnDeBnc(1)='1') or
(btnReg(2)='0' and btnDeBnc(2)='1') or
(btnReg(3)='0' and btnDeBnc(3)='1') ) else
'0';
----------------------------------------------------------
------ UART Control -------
----------------------------------------------------------
--Messages are sent on reset and when a button is pressed.
--This counter holds the UART state machine in reset for ~2 milliseconds. This
--will complete transmission of any byte that may have been initiated during
--FPGA configuration due to the UART_TX line being pulled low, preventing a
--frame shift error from occuring during the first message.
process(CLK)
begin
if (rising_edge(CLK)) then
if ((reset_cntr = RESET_CNTR_MAX) or (uartState /= RST_REG)) then
reset_cntr <= (others=>'0');
else
reset_cntr <= reset_cntr + 1;
end if;
end if;
end process;
--Next Uart state logic (states described above)
next_uartState_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (btnDeBnc(4) = '1') then
uartState <= RST_REG;
else
case uartState is
when RST_REG =>
if (reset_cntr = RESET_CNTR_MAX) then
uartState <= LD_INIT_STR;
end if;
when LD_INIT_STR =>
uartState <= SEND_CHAR;
when SEND_CHAR =>
uartState <= RDY_LOW;
when RDY_LOW =>
uartState <= WAIT_RDY;
when WAIT_RDY =>
if (uartRdy = '1') then
if (strEnd = strIndex) then
uartState <= WAIT_BTN;
else
uartState <= SEND_CHAR;
end if;
end if;
when WAIT_BTN =>
if (btnDetect = '1') then
uartState <= LD_BTN_STR;
end if;
when LD_BTN_STR =>
uartState <= SEND_CHAR;
when others=> --should never be reached
uartState <= RST_REG;
end case;
end if ;
end if;
end process;
--Loads the sendStr and strEnd signals when a LD state is
--is reached.
string_load_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (uartState = LD_INIT_STR) then
sendStr <= WELCOME_STR;
strEnd <= WELCOME_STR_LEN;
elsif (uartState = LD_BTN_STR) then
sendStr(0 to 23) <= BTN_STR;
strEnd <= BTN_STR_LEN;
end if;
end if;
end process;
--Conrols the strIndex signal so that it contains the index
--of the next character that needs to be sent over uart
char_count_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (uartState = LD_INIT_STR or uartState = LD_BTN_STR) then
strIndex <= 0;
elsif (uartState = SEND_CHAR) then
strIndex <= strIndex + 1;
end if;
end if;
end process;
--Controls the UART_TX_CTRL signals
char_load_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (uartState = SEND_CHAR) then
uartSend <= '1';
uartData <= sendStr(strIndex);
else
uartSend <= '0';
end if;
end if;
end process;
--Component used to send a byte of data over a UART line.
Inst_UART_TX_CTRL: UART_TX_CTRL port map(
SEND => uartSend,
DATA => uartData,
CLK => CLK,
READY => uartRdy,
UART_TX => uartTX
);
UART_TXD <= uartTX;
----------------------------------------------------------
------ RGB LED Control -------
----------------------------------------------------------
RGB_Core: RGB_controller port map(
GCLK => CLK,
RGB_LED_1_O(0) => RGB1_Green,
RGB_LED_1_O(1) => RGB1_Blue,
RGB_LED_1_O(2) => RGB1_Red,
RGB_LED_2_O(0) => RGB2_Green,
RGB_LED_2_O(1) => RGB2_Blue,
RGB_LED_2_O(2) => RGB2_Red
);
----------------------------------------------------------
------ MIC Control -------
----------------------------------------------------------
--PDM data from the microphone is registered on the rising
--edge of every micClk, converting it to PWM. The PWM data
--is then connected to the mono audio out circuit, causing
--the sound captured by the microphone to be played over
--the audio out port.
process(CLK)
begin
if (rising_edge(CLK)) then
clk_cntr_reg <= clk_cntr_reg + 1;
end if;
end process;
--micClk = 100MHz / 32 = 3.125 MHz
micClk <= clk_cntr_reg(4);
process(CLK)
begin
if (rising_edge(CLK)) then
if (clk_cntr_reg = "01111") then
pwm_val_reg <= micData;
end if;
end if;
end process;
micLRSel <= '0';
ampPWM <= pwm_val_reg;
ampSD <= '1';
end Behavioral;
|
gpl-3.0
|
ecbf46562b08c1e5fc377b38f7893aab
| 0.552154 | 3.693939 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/LedBar.vhd
| 1 | 3,414 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Mihaita Nagy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:23:44 04/02/2013
-- Design Name:
-- Module Name: LedBar - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- This module generates a progressbar on the Nexys4 onboard LEDs. The progressbar moves to left
-- when recording is in progress and moves to right when playback is in progress
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity LedBar is
generic(
C_SYS_CLK_FREQ_MHZ : integer := 100; -- system clock frequency in MHz
C_SECONDS_TO_RECORD : integer := 3 -- number of seconds to record
);
port(
clk_i : in std_logic; -- system clock
en_i : in std_logic; -- active-high enable
rnl_i : in std_logic; -- Right/Left shift select
leds_o : out std_logic_vector(15 downto 0) -- output LED bus
);
end LedBar;
architecture Behavioral of LedBar is
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
constant CLK_DIV_RATIO : integer := (((C_SECONDS_TO_RECORD * C_SYS_CLK_FREQ_MHZ * 1000000)/16) - 1);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- Clock divider counter
signal cnt_clk : integer := 0;
signal clk_div : std_logic;
--Shift register to hold the Led data
signal tmp_sig : std_logic_vector(15 downto 0) := (others => '0');
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- shift register
SHFT: process(clk_i)
begin
if rising_edge(clk_i) then
if en_i = '1' then
if clk_div = '1' then
-- shift left
if rnl_i = '0' then
tmp_sig <= tmp_sig(14 downto 0) & '1';
-- shift right
else
tmp_sig <= '1' & tmp_sig(15 downto 1);
end if;
end if;
else
tmp_sig <= (others => '0');
end if;
end if;
end process SHFT;
leds_o <= tmp_sig;
-- Generate shift clock
CLK_CNT: process(clk_i)
begin
if rising_edge(clk_i) then
if en_i = '0' or cnt_clk = CLK_DIV_RATIO then
cnt_clk <= 0;
clk_div <= '1';
else
cnt_clk <= cnt_clk + 1;
clk_div <= '0';
end if;
end if;
end process CLK_CNT;
end Behavioral;
|
gpl-3.0
|
3de2ed3f192ed931130d40c8dc2e2766
| 0.463972 | 4.462745 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/new/Vga.vhd
| 1 | 3,873 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.Font.all;
-- Information from http://tinyvga.com/vga-timing/1280x1024@60Hz
entity Vga is
Generic (
H_PIX : integer := 1280; -- Horizontal frame size
H_FP : integer := 48; -- Horizontal Front Porch
H_SY : integer := 112; -- Horizontal Sync
H_BP : integer := 248; -- Horizontal Back Porch
H_POL : std_logic := '1'; -- Horizontal Sync Polarity
V_PIX : integer := 1024; -- Vertical frame size
V_FP : integer := 1; -- Vertical Front Porch
V_SY : integer := 3; -- Vertical Sync
V_BP : integer := 36; -- Vertical Back Porch
V_POL : std_logic := '1' -- Vertical Sync Polarity
);
Port
(
clk : in std_logic;
hSync : out std_logic;
vSync : out std_logic;
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
fbOutAddr : out std_logic_vector(13 downto 0);
fbOutDat : in std_logic_vector(7 downto 0)
);
end Vga;
architecture Behavioral of Vga is
constant H_MAX : integer := H_PIX + H_FP + H_SY + H_BP; -- 1688 for 1280x1024@60Hz
constant V_MAX : integer := V_PIX + V_FP + V_SY + V_BP; -- 1066 for 1280x1024@60Hz
--------------------------------------------------------
begin -- BEGIN
--------------------------------------------------------
process(clk)
variable h_count : integer range 0 to H_MAX - 1 := 0; --horizontal counter (counts the columns)
variable v_count : integer range 0 to V_MAX - 1 := 0; --vertical counter (counts the rows)
variable char : std_logic_vector(7 downto 0);
--variable nextChar : std_logic_vector(7 downto 0);
variable charX : integer range 0 to 8;
variable charY : integer range 0 to 16;
begin
if (rising_edge(clk)) then
--counters
if (h_count < H_MAX - 1) then
h_count := h_count + 1;
else
h_count := 0;
if (v_count < V_MAX - 1) then
v_count := v_count + 1;
else
v_count := 0;
end if;
end if;
--horizontal sync signal
if (h_count < H_PIX + H_FP or h_count > H_PIX + H_FP + H_SY) then
hSync <= not H_POL;
else
hSync <= H_POL;
end if;
--vertical sync signal
if (v_count < V_PIX + V_FP or v_count > V_PIX + V_FP + V_SY) then
vSync <= not V_POL;
else
vSync <= V_POL;
end if;
--text display
if (h_count < H_PIX AND v_count < V_PIX) then
charX := h_count mod 8;
charY := v_count mod 16;
if (charX = 0) then -- Set up next character
char := fbOutDat;
elsif (charX = 1) then
fbOutAddr <= std_logic_vector(to_unsigned(1 + (h_count / 8) + ((v_count / 16) * 160), fbOutAddr'LENGTH));
end if;
-- char[7] = invert bit
if (char(7) = '1' xor draw_char(charX, charY, to_integer(unsigned(char and "01111111")))) then
vgaRed <= "1111";
vgaGreen <= "1111";
vgaBlue <= "1111";
else
vgaRed <= "0000";
vgaGreen <= "0000";
vgaBlue <= "0000";
end if;
else
fbOutAddr <= std_logic_vector(to_unsigned(((v_count / 16) * 160), fbOutAddr'LENGTH));
vgaRed <= "0000";
vgaGreen <= "0000";
vgaBlue <= "0000";
end if;
end if;
end process;
--------------------------------------------------------
end Behavioral; -- END
--------------------------------------------------------
|
mit
|
b221e262cf1bc72307b9ba4bfea64709
| 0.484121 | 3.900302 | false | false | false | false |
luebbers/reconos
|
core/pcores/osif_tlb_v2_01_a/hdl/vhdl/osif_tlb.vhd
| 1 | 2,855 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library proc_common_v1_00_b;
--use proc_common_v1_00_b.proc_common_pkg.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
library osif_tlb_v2_01_a;
use osif_tlb_v2_01_a.all;
entity osif_tlb is
generic
(
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_TLB_TAG_WIDTH : integer := 20;
C_TLB_DATA_WIDTH : integer := 21
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
-- tlb interface
o_tlb_rdata : out std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
i_tlb_wdata : in std_logic_vector(C_TLB_DATA_WIDTH - 1 downto 0);
i_tlb_tag : in std_logic_vector(C_TLB_TAG_WIDTH - 1 downto 0);
o_tlb_match : out std_logic;
i_tlb_we : in std_logic;
o_tlb_busy : out std_logic;
--o_tlb_wdone : out std_logic;
-- dcr bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrABus : in std_logic_vector(C_DCR_AWIDTH - 1 downto 0);
i_dcrDBus : in std_logic_vector(C_DCR_DWIDTH - 1 downto 0);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic
);
end entity;
architecture imp of osif_tlb is
signal tlb_invalidate : std_logic;
begin
i_tlb : entity osif_tlb_v2_01_a.tlb
port map
(
clk => sys_clk,
rst => sys_reset,
i_tag => i_tlb_tag,
i_data => i_tlb_wdata,
o_data => o_tlb_rdata,
i_we => i_tlb_we,
o_busy => o_tlb_busy,
--o_wdone => o_tlb_wdone,
o_match => o_tlb_match,
i_invalidate => tlb_invalidate
);
i_tlb_dcr : entity osif_tlb_v2_01_a.tlb_dcr
generic map
(
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH
)
port map
(
clk => sys_clk,
rst => sys_reset,
o_invalidate => tlb_invalidate,
-- dcr bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite
);
end architecture;
|
gpl-3.0
|
ab283d5c521cb0537197c53773e3f2e6
| 0.498424 | 3.26659 | false | false | false | false |
luebbers/reconos
|
tests/simulation/plb/condvar/test_condvar.vhd
| 1 | 3,337 |
-- condition variable test
-- modeled after the eCos condvar example
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test_condvar is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end test_condvar;
architecture Behavioral of test_condvar is
constant C_MY_MUTEX : std_logic_vector(0 to 31) := X"00000000";
constant C_MY_CONDVAR : std_logic_vector(0 to 31) := X"00000001";
type t_state is (STATE_INIT, STATE_LOCK, STATE_READ, STATE_WAIT, STATE_WRITE, STATE_UNLOCK);
signal state : t_state := STATE_INIT;
signal res_count : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
-- burst ram interface is not used
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= STATE_INIT;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data); -- get address of res_count
if done then
state <= STATE_LOCK;
end if;
when STATE_LOCK =>
reconos_mutex_lock (done, success, o_osif, i_osif, C_MY_MUTEX);
if done and success then
state <= STATE_READ;
end if;
when STATE_READ =>
reconos_read_s(done, o_osif, i_osif, init_data, res_count);
if done then
state <= STATE_WAIT;
end if;
when STATE_WAIT =>
if res_count = X"00000000" then
reconos_cond_wait(done, success, o_osif, i_osif, C_MY_CONDVAR);
if done and success then
state <= STATE_READ;
end if;
else
state <= STATE_WRITE;
end if;
when STATE_WRITE =>
reconos_write(done, o_osif, i_osif, init_data, res_count - 1);
if done then
state <= STATE_UNLOCK;
end if;
when STATE_UNLOCK =>
reconos_mutex_unlock (o_osif, i_osif, C_MY_MUTEX);
state <= STATE_LOCK;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
dc66da5af7f7b9b65fd7206edd014be4
| 0.567875 | 3.534958 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_pipebuf.vhd
| 1 | 3,869 |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_pipebuf
-- Architectures: lipif_pipebuf_rtl
-- Description:
-- This module provides a buffer for the acknowledge-request flow within
-- a pipeline. In effect it is a FIFO with a fixed depth of two.
--
-- Dependencies:
--
-- Revision:
-- 13.3.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity lipif_mst_pipebuf is
generic (
C_DATA_WIDTH : integer := 64;
C_EN_SRL16 : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
-- Previous (input) stage I/O
prevReq_i : in std_logic;
prevRdy_o : out std_logic;
prevData_i : in std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Next (output) stage I/O
nextReq_o : out std_logic;
nextRdy_i : in std_logic;
nextData_o : out std_logic_vector(C_DATA_WIDTH-1 downto 0)
);
end lipif_mst_pipebuf;
architecture lipif_mst_pipebuf_rtl of lipif_mst_pipebuf is
-- Primary and secondary valid signals indicate if data is valid
signal valid_prim : std_logic;
signal valid_sec : std_logic;
begin
prevRdy_o <= not valid_sec;
nextReq_o <= valid_prim;
EN_SRL16: if(C_EN_SRL16) generate
signal srl_ce : std_logic;
begin
srl_ce <= prevReq_i and not valid_sec;
SRL_FIFO: for i in 0 to C_DATA_WIDTH-1 generate
SRL16E_I: SRL16E
generic map (
INIT => X"0000"
)
port map (
CLK => clk,
CE => srl_ce,
D => prevData_i(i),
Q => nextData_o(i),
A0 => valid_sec,
A1 => '0',
A2 => '0',
A3 => '0'
);
end generate SRL_FIFO;
end generate EN_SRL16;
NEN_SRL16: if(not C_EN_SRL16) generate
-- Registers for primary and secondary data
signal data_prim : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal data_prim_nxt : std_logic_vector(C_DATA_WIDTH-1 downto 0);
signal data_sec : std_logic_vector(C_DATA_WIDTH-1 downto 0);
begin
nextData_o <= data_prim;
data_prim_nxt <= data_sec when(valid_sec='1') else prevData_i;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
data_prim <= (others=>'0');
data_sec <= (others=>'0');
else
-- Handle Primary Stage
if(nextRdy_i='1' or valid_prim='0') then
data_prim <= data_prim_nxt;
end if;
-- Handle Secondary Stage
if(nextRdy_i='1' or valid_sec='0') then
data_sec <= prevData_i;
end if;
end if;
end if;
end process;
end generate NEN_SRL16;
-- Generate valid signals
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
valid_prim <= '0';
valid_sec <= '0';
else
-- Handle Primary Stage
if(nextRdy_i='1' or valid_prim='0') then
valid_prim <= valid_sec or prevReq_i;
end if;
-- Handle Secondary Stage
if(nextRdy_i='1' or valid_sec='0') then
valid_sec <= valid_prim and prevReq_i and not nextRdy_i;
end if;
end if;
end if;
end process;
end lipif_mst_pipebuf_rtl;
|
gpl-3.0
|
63b839d80a10e98769915899cf401a1a
| 0.510209 | 3.759961 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/when_else.vhd
| 2 | 612 |
library ieee;
use ieee.std_logic_1164.all;
entity foo_entity is
port(
data_i : in std_logic_vector(1 downto 0);
data_o, data_o2, data_o3 : out std_logic_vector(3 downto 0)
);
end foo_entity;
architecture behaviour of foo_entity is
begin
data_o <= "0001" when ( data_i="00" ) else
"0010" when ( data_i="01" ) else
"0100" when ( data_i="10" ) else
"1000";
-- test cases without the final 'else' statement
data_o2 <= "0101" when ( data_i="01" );
data_o3 <= "1100" when ( data_i="10" ) else
"0011" when ( data_i="01" );
end behaviour;
|
gpl-2.0
|
d2339147bf34451a0d72b19f4dc1e934
| 0.575163 | 2.942308 | false | false | false | false |
zhangry868/MultiCycleCPU
|
Multiple_Cycles_CPU/simulation/modelsim/rtl_work/@controller/_primary.vhd
| 1 | 2,817 |
library verilog;
use verilog.vl_types.all;
entity Controller is
generic(
S0 : integer := 0;
S1 : integer := 1;
S2 : integer := 2;
S3 : integer := 3;
S4 : integer := 4;
S5 : integer := 5;
S6 : integer := 6;
S7 : integer := 7;
S8 : integer := 8;
S9 : integer := 9;
S10 : integer := 10;
S11 : integer := 11;
S12 : integer := 12;
S13 : integer := 13
);
port(
Clk : in vl_logic;
Overflow : in vl_logic;
IR : in vl_logic_vector(31 downto 0);
WBType : in vl_logic_vector(1 downto 0);
condition : out vl_logic_vector(2 downto 0);
ALU_SrcB : out vl_logic_vector(2 downto 0);
ALU_op : out vl_logic_vector(3 downto 0);
Rd_write_byte_en: out vl_logic_vector(3 downto 0);
Mem_byte_write : out vl_logic_vector(3 downto 0);
RegDst : out vl_logic_vector(1 downto 0);
MemtoReg : out vl_logic_vector(1 downto 0);
PC_source : out vl_logic_vector(1 downto 0);
Shift_op : out vl_logic_vector(1 downto 0);
ALU_SrcA : out vl_logic;
Ex_top : out vl_logic;
Shift_amountSrc : out vl_logic;
ALUShift_Sel : out vl_logic;
PC_write_cond : out vl_logic;
PC_write : out vl_logic;
IorD : out vl_logic;
IR_write_en : out vl_logic;
Addreg_write_en : out vl_logic;
RegDt0 : out vl_logic;
state_out : out vl_logic_vector(3 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of S0 : constant is 1;
attribute mti_svvh_generic_type of S1 : constant is 1;
attribute mti_svvh_generic_type of S2 : constant is 1;
attribute mti_svvh_generic_type of S3 : constant is 1;
attribute mti_svvh_generic_type of S4 : constant is 1;
attribute mti_svvh_generic_type of S5 : constant is 1;
attribute mti_svvh_generic_type of S6 : constant is 1;
attribute mti_svvh_generic_type of S7 : constant is 1;
attribute mti_svvh_generic_type of S8 : constant is 1;
attribute mti_svvh_generic_type of S9 : constant is 1;
attribute mti_svvh_generic_type of S10 : constant is 1;
attribute mti_svvh_generic_type of S11 : constant is 1;
attribute mti_svvh_generic_type of S12 : constant is 1;
attribute mti_svvh_generic_type of S13 : constant is 1;
end Controller;
|
gpl-3.0
|
3f0f4402ea816024a8b12cf2d0d39f06
| 0.512602 | 3.682353 | false | false | false | false |
five-elephants/hw-neural-sampling
|
observer.vhdl
| 1 | 994 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sampling.all;
entity observer is
generic (
num_samplers : integer;
counter_width : positive := 32
);
port (
clk, reset : in std_ulogic;
state, observe_state : in state_array_t(1 to num_samplers);
count : out unsigned(counter_width-1 downto 0);
saturated : out std_ulogic
);
end observer;
architecture rtl of observer is
subtype counter_t is unsigned(counter_width-1 downto 0);
signal count_i : counter_t;
begin
count <= count_i;
------------------------------------------------------------
counter_process: process ( clk, reset )
begin
if reset = '1' then
count_i <= to_unsigned(0, count_i'length);
elsif rising_edge(clk) then
if (state = observe_state) and not (count_i = 2**counter_width-1) then
count_i <= count_i + 1;
end if;
end if;
end process;
------------------------------------------------------------
end rtl;
|
apache-2.0
|
34908d593e0e91cf6603d6f1313dc7b5
| 0.565392 | 3.695167 | false | false | false | false |
luebbers/reconos
|
core/pcores/xps_osif_v2_01_a/hdl/vhdl/fifo_mgr.vhd
| 3 | 3,729 |
--!
--! \file fifo_mgr.vhd
--!
--! Protocol converter between FIFO channels, command decoder, and memory
--! interface (TODO).
--!
--! \author Enno Luebbers <[email protected]>
--! \date 04.10.2007
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 04.10.2007 Enno Luebbers File created
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fifo_mgr is
generic (
C_FIFO_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- local FIFO access signals
i_local_read_remove : in std_logic;
o_local_read_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
o_local_read_wait : out std_logic; -- either empty or busy
i_local_write_add : in std_logic;
i_local_write_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
o_local_write_wait : out std_logic; -- either full or busy
-- "real" FIFO access signals
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic
-- TODO: signal to communicate with the bus_slave_regs module
);
end fifo_mgr;
architecture behavioral of fifo_mgr is
signal local_read_remove_d1 : std_logic := '0';
begin
-- delay read_remove for 1 clock cycle
process(clk, reset)
begin
if reset = '1' then
local_read_remove_d1 <= '0';
elsif rising_edge(clk) then
local_read_remove_d1 <= i_local_read_remove;
end if;
end process;
-- for now, the FIFO manager only services local accesses.
-- so we just need to pass the local access signals straight
-- through to the "real" FIFOs
o_fifo_read_en <= local_read_remove_d1; -- hack to fit slow OSIF request/busy handshake
-- this will be obsoleted once we connect the HW
-- FIFO to the burst RAM interface (mq)
o_local_read_data <= i_fifo_read_data;
o_local_read_wait <= not i_fifo_read_ready;
o_fifo_write_en <= i_local_write_add;
o_fifo_write_data <= i_local_write_data;
o_local_write_wait <= not i_fifo_write_ready;
end behavioral;
|
gpl-3.0
|
39a27cf82129635c2102fe257f55a2a6
| 0.600429 | 3.736473 | false | false | false | false |
bzero/freezing-spice
|
src/compare_unit.vhd
| 2 | 2,313 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.decode_pkg.all;
entity compare_unit is
port (
branch_type : in branch_type_t;
op1 : in word;
op2 : in word;
compare_result : out std_logic);
end entity compare_unit;
architecture behavioral of compare_unit is
signal compare : std_logic;
begin -- architecture behavioral
-- assign output
compare_result <= compare;
-- purpose: compares two numbers according to branch_type
-- type : combinational
-- inputs : branch_type, op1, op2
-- outputs: compare_result
compare_proc: process (branch_type, op1, op2) is
variable ou1, ou2 : unsigned(31 downto 0);
variable os1, os2 : signed(31 downto 0);
begin -- process compare_proc
ou1 := unsigned(op1);
os1 := signed(op1);
ou2 := unsigned(op2);
os2 := signed(op2);
compare <= '0';
case (branch_type) is
when BEQ =>
if op1 = op2 then
compare <= '1';
else
compare <= '0';
end if;
when BNE =>
if op1 /= op2 then
compare <= '1';
else
compare <= '0';
end if;
when BLT =>
if os1 < os2 then
compare <= '1';
else
compare <= '0';
end if;
when BGE =>
if os1 >= os2 then
compare <= '1';
else
compare <= '0';
end if;
when BLTU =>
if ou1 < ou2 then
compare <= '1';
else
compare <= '0';
end if;
when BGEU =>
if ou1 >= ou2 then
compare <= '1';
else
compare <= '0';
end if;
when others => compare <= '0';
end case;
end process compare_proc;
end architecture behavioral;
|
bsd-3-clause
|
6571ae91b61389ba7f2e0dd09fae4c6d
| 0.410722 | 4.710794 | false | false | false | false |
luebbers/reconos
|
core/pcores/plb_osif_v2_03_a/hdl/vhdl/bus_slave_regs.vhd
| 2 | 5,775 |
--!
--! \file bus_slave_regs.vhd
--!
--! PLB bus slave logic for ReconOS OSIF (user_logic)
--!
--! Contains the bus access logic for the single memory access register.
--!
--! \author Enno Luebbers <[email protected]>
--! \date 07.08.2006
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Major changes
-- 07.08.2006 Enno Luebbers File created
-- 25.09.2007 Enno Luebbers added slv_osif2bus_datax
-- 04.07.2008 Enno Luebbers trimmed deprecated PLB registers
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity bus_slave_regs is
generic (
C_DWIDTH : integer := 32;
C_NUM_REGS : integer := 1 -- number of standard osif registers
);
port (
clk : in std_logic;
reset : in std_logic; -- high active synchronous
-- bus slave signals
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REGS-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REGS-1);
IP2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
-- user registers
slv_osif2bus_shm : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
slv_bus2osif_shm : out std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end bus_slave_regs;
architecture behavioral of bus_slave_regs is
constant C_NUM_CE_TOTAL : integer := C_NUM_REGS;
-- Bus signalling helper signals
signal slv_reg_write_select : std_logic_vector(0 to C_NUM_REGS-1);
signal slv_reg_read_select : std_logic_vector(0 to C_NUM_REGS-1);
signal slv_ip2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
-- Actual bus2osif registers
signal slv_bus2osif_shm_reg : std_logic_vector(0 to C_DWIDTH-1) := (others => '0');
begin
-- ### CHECK GENERICS ###
assert C_NUM_REGS = 1
report "bus_slave_regs does not support more than one register (shm)."
severity failure;
-- ######################### CONCURRENT ASSIGNMENTS #######################
-- connect registers to outputs
slv_bus2osif_shm <= slv_bus2osif_shm_reg;
-- drive IP to Bus signals
IP2Bus_Data <= slv_ip2bus_data;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_WrAck <= slv_write_ack;
-- connect bus signalling
slv_reg_write_select <= Bus2IP_WrCE(0 to C_NUM_REGS-1);
slv_reg_read_select <= Bus2IP_RdCE(0 to C_NUM_REGS-1);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
-- FIXME: reduce_or?
-- ############################### PROCESSES ############################
-------------------------------------------------------------
-- slave_reg_write_proc: implement bus write access to slave
-- registers
-------------------------------------------------------------
slave_reg_write_proc : process(clk) is
begin
if clk'event and clk = '1' then
if reset = '1' then
slv_bus2osif_shm_reg <= (others => '0');
else
case slv_reg_write_select(0 to 0) is
when "1" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_bus2osif_shm_reg(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-------------------------------------------------------------
-- slave_reg_read_proc: implement bus read access to slave
-- registers
-------------------------------------------------------------
slave_reg_read_proc : process(slv_reg_read_select, slv_osif2bus_shm) is
begin
slv_ip2bus_data <= (others => '0');
case slv_reg_read_select(0 to 0) is
when "1" => slv_ip2bus_data <= slv_osif2bus_shm;
-- when others => slv_ip2bus_data <= (others => '0');
when others =>
end case;
end process SLAVE_REG_READ_PROC;
end behavioral;
|
gpl-3.0
|
02f03ecdd822b51c153b20ab9365d614
| 0.522251 | 3.868051 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/vector_heater_a_v1_00_a/hdl/vhdl/big_register.vhd
| 1 | 1,139 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
entity big_register is
generic
(
C_REGISTER_LENGTH : integer := 10000
);
port
(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic; -- clock enable
xor_sig : out std_logic -- xor of all register bits
);
end entity big_register;
architecture behavioral of big_register is
signal vector : std_logic_vector(0 to C_REGISTER_LENGTH-1);
begin
-- for active heater: invert vector and write number of 1s vector into output signal
change_vector : process (rst, clk) is
variable bit_temp : std_logic;
begin
if rst = '1' then
vector(1 to C_REGISTER_LENGTH-1) <= (others=>'0');
vector(0) <= '1';
xor_sig <= '0';
elsif rising_edge(clk) then
if ce = '1' then
vector <= not vector;
bit_temp := '0';
for i in 0 to C_REGISTER_LENGTH-1 loop
bit_temp := bit_temp xor vector(i);
end loop;
xor_sig <= bit_temp;
end if;
end if;
end process;
end behavioral;
|
gpl-3.0
|
85675998c1b878e34b31f5dd4e864d60
| 0.622476 | 3.272989 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/dynamic_src/user_processes/uf_resampling.vhd
| 1 | 13,265 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : R E S A M P L I N G
--
-- In many cases, this function does not have to be changed.
-- Only if you want/need to change/adjust the resampling algorithm
-- you can change it here.
--
-- Here the Residual Systematic Resampling Algorithm is used.
-- It is not easy to change to a complete other resampling algorithm,
-- because the framework is adjusted to use a algorithm, which
-- only uses one cycle of iterations and so without any correction cycle.
--
-- Some basic information about the resampling user function:
--
-- The particle weights are loaded into the local RAM by the Framework
-- The first 63 * 128 bytes (of 64 * 128 bytes) are filled with
-- all the particle weights needed. There will not be any space
-- between the particle weights.
--
-- The last 128 bytes are used for the resampling.
-- The user has to store two values for every particle.
-- 1. the index of the particle (as integer)
-- 2. the replication factor of the particle (as integer)
-- The ordering of this two values must not be changed,
-- because it is used later for the sampling step.
--
-- The two integer values (also known as index_type) are written
-- into the last 128 byte. Since two integer values need 8 bytes,
-- information about 16 particles can be written into the last 128 bytes
-- of the local ram before they have to be written by the Framework.
--
-- The outgoing signal write_burst has to be '1', if the the indexes
-- and replication factors should be written into the Main Memory.
-- This should only happen, if the information about 16
-- particles is resampled or the last particle has been resampled.
--
-- The incoming signal write_burst_done is equal to '1', if the
-- Framework has written the information to the Main Memory
--
-- If resampling is finished the outgoing signal finish has to be set to '1'.
-- A new run of the resampling will be started if the next particles are
-- loaded into local RAM. This is the case when the incoming signal
-- particles_loaded is equal to '1'.
--
------------------------------------------------------------------------------------
entity uf_resampling is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- additional incoming signals
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the resampling user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- number of particles in total
number_of_particles_in_total : in integer;
-- index of first particles (the particles are sorted increasingly)
start_particle_index : in integer;
-- resampling function init
U_init : in integer;
-- address of the last 128 byte burst in local RAM
write_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
-- information if a write burst has been handled by the Framework
write_burst_done : in std_logic;
-- additional outgoing signals
-- this signal has to be set to '1', if the Framework should write
-- the last burst from local RAM into Maim Memory
write_burst : out std_logic;
-- write burst done acknowledgement
write_burst_done_ack : out std_logic;
-- number of currently written particles
written_values : out integer;
-- if every particle is resampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_resampling;
architecture Behavioral of uf_resampling is
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- local RAM read/write address
signal local_ram_read_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_write_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- particle counter for allready resampled particles at all
signal counter_resampled_particles : integer := 0;
-- write counter (used bytes)
signal write_counter :integer := 0;
-- current particle weight
signal current_particle_weight : integer := 0;
-- signals needed for residual systematic resampling
signal temp : integer := 0;
signal fact : integer := 0; -- replication factor
signal U : integer := 0;
-- states
type t_state1 is (STATE_INIT,
STATE_LOAD_PARTICLE_1, STATE_LOAD_PARTICLE_2, STATE_LOAD_WEIGHT,
STATE_CALCULATE_REPLICATION_FACTOR_1, STATE_CALCULATE_REPLICATION_FACTOR_2,
STATE_CALCULATE_REPLICATION_FACTOR_3, STATE_CALCULATE_REPLICATION_FACTOR_4,
STATE_CALCULATE_REPLICATION_FACTOR_5, STATE_CALCULATE_REPLICATION_FACTOR_6,
STATE_WRITE_PARTICLE_INDEX, STATE_WRITE_PARTICLE_REPLICATION,
STATE_WRITE_BURST_DECISION, STATE_WRITE_BURST, STATE_WRITE_BURST_DONE_ACK,
STATE_WRITE_BURST_DONE_ACK_2, STATE_FINISH);
-- current state
signal state1 : t_state1 := STATE_INIT;
begin
-- burst ram interface is not used
-- o_RAMAddr <= (others => '0');
-- o_RAMData <= (others => '0');
-- o_RAMWE <= '0';
o_RAMClk <= clk;
state_proc : process(clk, reset)
begin
if (reset = '1') then
state1 <= STATE_INIT;
elsif rising_edge(clk) then
if init = '1' then
state1 <= STATE_INIT;
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
U <= U_init;
elsif enable = '1' then
case state1 is
when STATE_INIT =>
--! init data
local_ram_read_address <= (others => '0');
local_ram_write_address <= write_address;
counter_resampled_particles <= 0;
counter <= start_particle_index;
current_particle_weight <= 0;
temp <= 0;
fact <= 0;
--U <= U_init;
write_counter <= 0;
written_values <= 0;
write_burst <= '0';
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
state1 <= STATE_LOAD_PARTICLE_1;
end if;
-- 0) INIT
--
-- i = 0; // current particle
-- j = 0; // current replication factor
-- k = 0; // current number of cloned particles
-- finished = 0;
--
--
-- 1) LOAD_PARTICLE_1/2, LOAD_WEIGHT
--
-- load weight of i-th particle from local memory
-- i ++;
--
--
-- 2) CALCULATE_REPLICATION_FACTOR_1-8
--
-- calculate replication factor
--
--
-- 3) WRITE_PARTICLE_INDEX, WRITE_PARTICLE_REPLICATION
--
-- write particle index + replicationfactor to local ram
--
--
-- 4) WRITE_BURST
--
-- write_burst = 1;
-- if (write_burst_done)
--
-- write_burst = 0;
-- go to step 4
--
--
-- 5) FINISHED
--
-- finished = 1;
-- if (particles_loaded)
-- go to step 0;
when STATE_LOAD_PARTICLE_1 =>
--! load a particle
write_burst <= '0';
if (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_WRITE_BURST_DECISION;
else
o_RAMAddr <= local_ram_read_address;
state1 <= STATE_LOAD_PARTICLE_2;
end if;
when STATE_LOAD_PARTICLE_2 =>
--!needed because reading from local RAM needs two clock steps
state1 <= STATE_LOAD_WEIGHT;
when STATE_LOAD_WEIGHT =>
--! load particle weight
current_particle_weight <= TO_INTEGER(SIGNED(i_RAMData));
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_1;
when STATE_CALCULATE_REPLICATION_FACTOR_1 =>
--! calculate replication factor (step 2/6)
temp <= current_particle_weight * number_of_particles_in_total;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_2;
when STATE_CALCULATE_REPLICATION_FACTOR_2 =>
--! calculate replication factor (step 2/6)
temp <= temp - U;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_3;
when STATE_CALCULATE_REPLICATION_FACTOR_3 =>
--! calculate replication factor (step 3/6)
fact <= temp + GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_4;
when STATE_CALCULATE_REPLICATION_FACTOR_4 =>
--! calculate replication factor (step 4/6)
fact <= fact / GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_5;
when STATE_CALCULATE_REPLICATION_FACTOR_5 =>
--! calculate replication factor (step 5/6)
U <= fact * GRANULARITY;
state1 <= STATE_CALCULATE_REPLICATION_FACTOR_6;
when STATE_CALCULATE_REPLICATION_FACTOR_6 =>
--! calculate replication factor (step 6/6)
U <= U - temp;
state1 <= STATE_WRITE_PARTICLE_INDEX;
-- todo: change back
--state1 <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_PARTICLE_INDEX =>
--! read particle from local ram
-- copy particle_size / 32 from local RAM to local RAM
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(counter, C_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
state1 <= STATE_WRITE_PARTICLE_REPLICATION;
when STATE_WRITE_PARTICLE_REPLICATION =>
--! needed because reading takes 2 clock steps
o_RAMWE <= '1';
o_RAMAddr <= local_ram_write_address;
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(fact, C_BURST_DWIDTH));
local_ram_write_address <= local_ram_write_address + 1;
write_counter <= write_counter + 1;
state1 <= STATE_WRITE_BURST_DECISION;
when STATE_WRITE_BURST_DECISION =>
--! write burst to main memory
o_RAMWE <= '0';
if (16 <= write_counter) then
-- write burst
state1 <= STATE_WRITE_BURST;
-- todo change back
--state1 <= STATE_WRITE_BURST_DECISION;
write_counter <= 0;
local_ram_write_address <= write_address;
written_values <= 16;
elsif (number_of_particles <= counter_resampled_particles and write_counter > 0) then
-- write burst
state1 <= STATE_WRITE_BURST;
--todo: changed back
--state1 <= STATE_WRITE_BURST_DECISION;
write_counter <= 0;
--write_burst <= '1';
written_values <= write_counter;
elsif (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_FINISH;
else
-- get next particle
counter <= counter + 1;
counter_resampled_particles <= counter_resampled_particles + 1;
local_ram_read_address <= local_ram_read_address + 1;
state1 <= STATE_LOAD_PARTICLE_1;
end if;
when STATE_WRITE_BURST =>
--! write burst to main memory
--write_burst <= '1';
--written_values <= write_counter;
--if (rising_edge (write_burst_done)) then
write_burst <= '1';
write_burst_done_ack <= '0';
--change back
--write_counter <= 0;
if (write_burst_done = '1') then
write_burst <= '0';
state1 <= STATE_WRITE_BURST_DONE_ACK;
end if;
when STATE_WRITE_BURST_DONE_ACK =>
--! write burst to main memory
write_burst_done_ack <= '1';
write_counter <= 0;
write_burst <= '0';
if (write_burst_done = '0') then
state1 <= STATE_WRITE_BURST_DONE_ACK_2;
end if;
-- if (number_of_particles <= counter_resampled_particles) then
--
-- state1 <= STATE_FINISH;
-- else
-- --todo: changed for hopefully good
-- --state1 <= STATE_LOAD_PARTICLE_1;
-- state1 <= STATE_WRITE_BURST_DECISION;
-- end if;
when STATE_WRITE_BURST_DONE_ACK_2 =>
--! write burst to main memory
write_burst_done_ack <= '0';
if (number_of_particles <= counter_resampled_particles) then
state1 <= STATE_FINISH;
else
--todo: changed for hopefully good
--state1 <= STATE_LOAD_PARTICLE_1;
state1 <= STATE_WRITE_BURST_DECISION;
end if;
when STATE_FINISH =>
--! write finished signal
write_burst <= '0';
finished <= '1';
if (particles_loaded = '1') then
state1 <= STATE_INIT;
end if;
when others =>
state1 <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
b7a44713b769c303aec8faf99444b815
| 0.592537 | 3.888889 | false | false | false | false |
luebbers/reconos
|
support/templates/coregen/fifo/fifo_async.vhd
| 1 | 5,403 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_async.vhd when simulating
-- the core, fifo_async. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_async IS
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
END fifo_async;
ARCHITECTURE fifo_async_a OF fifo_async IS
-- synthesis translate_off
component wrapped_fifo_async
port (
din: IN std_logic_VECTOR(31 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
valid: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_async use entity XilinxCoreLib.fifo_generator_v3_2(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_implementation_type => 2,
c_family => "virtex2p",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 509,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 510,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_async
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
valid => valid);
-- synthesis translate_on
END fifo_async_a;
|
gpl-3.0
|
4edf05758e0289be05b63f176a519dc6
| 0.562095 | 3.578146 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/test/testbench/vhdl/ll_fifo_tb.vhd
| 1 | 22,679 |
-------------------------------------------------------------------------------
--
-- Module : ll_fifo_tb.vhd
--
-- Version : 1.2
--
-- Last Update : 2005-06-29
--
-- Project : Parameterizable LocalLink FIFO
--
-- Description : Testbench of LocalLink FIFO
--
-- Designer : Wen Ying Wei, Davy Huang
--
-- Company : Xilinx, Inc.
--
-- Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- Testbench Block Diagram:
--
--
-- +---------+ +---------+
-- | | | |
-- | Tester | ==> | Egress | ====+
-- | (TX) | | LL_FIFO | |
-- | | | | +----------+
-- +---------+ +---------+ |Pipeline/ |
-- +---------+ +---------+ |Throttle |
-- | | | | +----------+
-- | Tester | <== | Ingress | |
-- | (RX) | | LL_FIFO |<====+
-- | | | |
-- +---------+ +---------+
-- ^ ^
-- | |
-- TESTER I/F LOOPBACK I/F
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.TESTER_pkg.all;
use work.ll_fifo_pkg.all;
entity ll_fifo_tb is
generic (
-- Set memory type and depth
MEM_TYPE : integer :=0; -- Select memory type(0: BRAM, 1: Distributed RAM)
BRAM_MACRO_NUM : integer :=16; -- Set memory depth if use BRAM
DRAM_DEPTH : integer :=16; -- Set memory depth if use Distributed RAM
-- Set clock rate, data width at the tester interface
TESTER_CLK_HALF_PERIOD : time :=12.50 ns; -- Set Tester clock speed
TESTER_DWIDTH : integer :=64; -- Set Tester data width:8, 16, 32, 64, 128
TESTER_REM_WIDTH : integer :=3; -- Set Tester remainder width:1, 1, 2, 3, 4
TESTER_REM_VECTOR_WIDTH : integer :=3; -- Set rem width in test vector file
-- Use 3 if TESTER_DWIDTH <= 64
-- Use 7 if TESTER_DWIDTH = 128
TESTER_FIFO_DEPTH : integer :=8192; -- Set Tester FIFO depth (FIFO to buffer the traffic data)
-- Set clock rate, data width at the loopback interface
LOOPBACK_CLK_HALF_PERIOD: time :=12.50 ns; -- Set Loopback clock speed
LOOPBACK_DWIDTH : integer :=8; -- Set Tester data width:8, 16, 32, 64, 128
LOOPBACK_REM_WIDTH : integer :=1; -- Set Loopback remainder width:1, 1, 2, 3, 4
-- Other LocalLink FIFO options
EGRESS_USE_LENGTH : boolean :=true; -- Set if use Length Option on Egress FIFO
INGRESS_USE_LENGTH : boolean :=true; -- Set if use Length Option on Ingress FIFO
-- Global timing delay
glbtm : time :=0.5 ns );-- Set global timing delay
end ll_fifo_tb;
architecture ll_fifo_tb_arch of ll_fifo_tb is
signal rst : std_logic;
signal tester_clk : std_logic;
-- Loopback Interface signals
signal loopback_clk : std_logic;
signal Eloopback_data : std_logic_vector(0 to LOOPBACK_DWIDTH-1);
signal Eloopback_rem : std_logic_vector(0 to LOOPBACK_REM_WIDTH-1);
signal Eloopback_sof_n : std_logic;
signal Eloopback_eof_n : std_logic;
signal Eloopback_src_rdy_n : std_logic;
signal Eloopback_dst_rdy_n : std_logic;
signal Iloopback_data : std_logic_vector(0 to LOOPBACK_DWIDTH-1);
signal Iloopback_rem : std_logic_vector(0 to LOOPBACK_REM_WIDTH-1);
signal Iloopback_sof_n : std_logic;
signal Iloopback_eof_n : std_logic;
signal Iloopback_src_rdy_n : std_logic;
signal Iloopback_dst_rdy_n : std_logic;
signal loopback_throttle_cnt : std_logic_vector(10 downto 0);
signal loopback_throttle_th : std_logic_vector(13 downto 0);
signal loopback_throttle : std_logic;
signal Sloopback : std_logic;
-- Tester interface signals
signal tx_d : std_logic_vector(0 to TESTER_DWIDTH-1);
signal tx_rem : std_logic_vector(0 to TESTER_REM_WIDTH-1);
signal tx_sof_n : std_logic;
signal tx_eof_n : std_logic;
signal tx_src_rdy_n : std_logic;
signal tx_dst_rdy_n : std_logic;
signal tx_dst_rdy_n_i : std_logic;
signal rx_d : std_logic_vector(0 to TESTER_DWIDTH-1);
signal rx_rem : std_logic_vector(0 to TESTER_REM_WIDTH-1);
signal rx_sof_n : std_logic;
signal rx_eof_n : std_logic;
signal rx_src_rdy_n : std_logic;
-- Other LocalLink FIFO signals
signal egress_fifostatus : std_logic_vector(0 to 3);
signal egress_len_rdy_out: std_logic;
signal egress_len_out: std_logic_vector(15 downto 0);
signal egress_len_err_out: std_logic;
signal ingress_fifostatus : std_logic_vector(0 to 3);
signal ingress_len_rdy_out: std_logic;
signal ingress_len_out: std_logic_vector(15 downto 0);
signal ingress_len_err_out: std_logic;
--Reference Signals
signal src_rdy_n_ref_i : std_logic;
-- Tester signals
signal WORKING: std_logic;
signal COMPARING: std_logic;
signal OVERFLOW: std_logic;
signal RESULT_GOOD: std_logic;
signal RESULT_GOOD_PDU: std_logic;
signal TV: std_logic_vector(0 to 7);
-- Other signals
signal GND: std_logic;
signal VCC: std_logic;
signal ufc_rx_d : std_logic_vector(0 to TESTER_DWIDTH-1);
signal ufc_rx_rem : std_logic_vector(0 to TESTER_REM_WIDTH-1);
begin
GND <= '0';
VCC <= '1';
ufc_rx_d <= (others => '0');
ufc_rx_rem <= (others => '0');
TV(0) <= not rst; -- first test vector is reset
TV(1) <= not tx_dst_rdy_n;
tx_dst_rdy_n <= tx_dst_rdy_n_i when tx_src_rdy_n = '0'
else '1' when egress_fifostatus >= "0000" and loopback_throttle_th(11 downto 9) = "111" and loopback_throttle_th(4) = '1'
else tx_dst_rdy_n_i;
-- second test vector is the destination ready signal
-- from the Egress FIFO to the Tester
TV(2 to 7) <= (others => '0'); -- other test vectors not used
---------------------------------------------------------------------------
-- Instantiate the DUT : Egress FIFO and Ingress FIFO
---------------------------------------------------------------------------
Egress_FIFO: ll_fifo
generic map (
MEM_TYPE => MEM_TYPE,
BRAM_MACRO_NUM => BRAM_MACRO_NUM,
DRAM_DEPTH => DRAM_DEPTH,
WR_DWIDTH => TESTER_DWIDTH,
WR_REM_WIDTH => TESTER_REM_WIDTH,
RD_DWIDTH => LOOPBACK_DWIDTH,
RD_REM_WIDTH => LOOPBACK_REM_WIDTH,
USE_LENGTH => EGRESS_USE_LENGTH,
glbtm => glbtm )
port map (
-- Reset
areset_in => rst,
-- clocks
write_clock_in => tester_clk,
read_clock_in => loopback_clk,
-- Tester Interface
data_in => tx_d,
rem_in => tx_rem,
sof_in_n => tx_sof_n,
eof_in_n => tx_eof_n,
src_rdy_in_n => tx_src_rdy_n,
dst_rdy_out_n => tx_dst_rdy_n_i,
-- Loopback Interface
data_out => Eloopback_data,
rem_out => Eloopback_rem,
sof_out_n => Eloopback_sof_n,
eof_out_n => Eloopback_eof_n,
src_rdy_out_n => Eloopback_src_rdy_n,
dst_rdy_in_n => Eloopback_dst_rdy_n,
-- FIFO status signals
fifostatus_out => egress_fifostatus,
-- Length Status
len_rdy_out => egress_len_rdy_out,
len_out => egress_len_out,
len_err_out => egress_len_err_out);
Ingress_FIFO: ll_fifo
generic map (
MEM_TYPE => MEM_TYPE,
BRAM_MACRO_NUM => BRAM_MACRO_NUM,
DRAM_DEPTH => DRAM_DEPTH,
WR_DWIDTH => LOOPBACK_DWIDTH,
WR_REM_WIDTH => LOOPBACK_REM_WIDTH,
RD_DWIDTH => TESTER_DWIDTH,
RD_REM_WIDTH => TESTER_REM_WIDTH,
USE_LENGTH => INGRESS_USE_LENGTH,
glbtm => glbtm )
port map (
-- Reset
areset_in => rst,
-- clocks
write_clock_in => loopback_clk,
read_clock_in => tester_clk,
-- Loopback Interface
data_in => Iloopback_data,
rem_in => Iloopback_rem,
sof_in_n => Iloopback_sof_n,
eof_in_n => Iloopback_eof_n,
src_rdy_in_n => Iloopback_src_rdy_n,
dst_rdy_out_n => Iloopback_dst_rdy_n,
-- Tester Interface
data_out => rx_d,
rem_out => rx_rem,
sof_out_n => rx_sof_n,
eof_out_n => rx_eof_n,
src_rdy_out_n => rx_src_rdy_n,
dst_rdy_in_n => GND, -- Tester always ready to accept data
-- FIFO status signals
fifostatus_out => ingress_fifostatus,
-- Length Status
len_rdy_out => ingress_len_rdy_out,
len_out => ingress_len_out,
len_err_out => ingress_len_err_out);
---------------------------------------------------------------------------
-- Loopback I/F
---------------------------------------------------------------------------
loopback_throttle_cnt_proc: process (rst, loopback_clk)
begin
if rst = '1' then
loopback_throttle_cnt <= (others => '0') after glbtm;
elsif loopback_clk'event and loopback_clk = '1' then
if loopback_throttle_cnt = loopback_throttle_th(13 downto 3) then
loopback_throttle_cnt <= (others => '0') after glbtm;
else
loopback_throttle_cnt <= loopback_throttle_cnt + 1 after glbtm;
end if;
end if;
end process;
loopback_throttle_proc : process (rst, loopback_clk)
begin
if rst = '1' then
loopback_throttle <= '0' after glbtm;
loopback_throttle_th <= "00011000000000" after glbtm;
elsif loopback_clk'event and loopback_clk = '1' then
if loopback_throttle_cnt = loopback_throttle_th(13 downto 3) then
loopback_throttle <= not loopback_throttle after glbtm;
end if;
if loopback_throttle_cnt = loopback_throttle_th(13 downto 3) and loopback_throttle = '0' then
loopback_throttle_th <= loopback_throttle_th - 73 after glbtm;
end if;
end if;
end process;
loopback_if_proc: process (rst, loopback_clk)
begin
if rst = '1' then
Iloopback_data <= (others => '0') after glbtm;
Iloopback_rem <= (others => '0') after glbtm;
Iloopback_sof_n <= '1' after glbtm;
Iloopback_eof_n <= '1' after glbtm;
Iloopback_src_rdy_n <= '1' after glbtm;
Eloopback_dst_rdy_n <= '1' after glbtm;
Sloopback <= '0' after glbtm;
elsif loopback_clk'event and loopback_clk = '1' then
if Iloopback_dst_rdy_n = '1' and Sloopback = '1' then -- Ingress FIFO not ready, storage is occupied
-- latch the data, do nothing else
else
Iloopback_data <= Eloopback_data after glbtm;
Iloopback_rem <= Eloopback_rem after glbtm;
Iloopback_sof_n <= Eloopback_sof_n after glbtm;
Iloopback_eof_n <= Eloopback_eof_n after glbtm;
Iloopback_src_rdy_n <= Eloopback_src_rdy_n or Eloopback_dst_rdy_n after glbtm;
Sloopback <= not (Eloopback_src_rdy_n or Eloopback_dst_rdy_n) after glbtm;
end if;
if loopback_throttle = '0' then
Eloopback_dst_rdy_n <= Iloopback_dst_rdy_n or Sloopback after glbtm; -- hold off Egress FIFO when
-- there's data in the storage.
else
Eloopback_dst_rdy_n <= '1' after glbtm;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Instantiate the Tester TX: FILEREAD_TESTER
---------------------------------------------------------------------------
src_rdy_n_ref_i <= not (not tx_src_rdy_n and not tx_dst_rdy_n);
fileread_tester_i: FILEREAD_TESTER
generic map
( GLOBALDLY => 1,
TV_WIDTH => 8,
CV_WIDTH => 4,
LL_DAT_BIT_WIDTH => TESTER_DWIDTH,
LL_REM_BIT_WIDTH => TESTER_REM_WIDTH,
REM_VECTOR_WIDTH => TESTER_REM_VECTOR_WIDTH)
port map
(
--Global Signals
CLK => tester_clk,
TV => TV,
--LocalLink Interface
TX_SOF_N => tx_sof_n, --O
TX_EOF_N => tx_eof_n, --O
TX_D => tx_d, --O
TX_REM => tx_rem, --O
TX_SRC_RDY_N => tx_src_rdy_n, --O
--Native Flow Control Interface (Not used)
NFC_NB => open, --O
NFC_REQ_N => open, --O
--User Flow Control Interface (Not used)
UFC_TX_REQ_N => open, --O
UFC_TX_MS => open, --O
--Other User Signals
CTRL => open
);
---------------------------------------------------------------------------
-- Instantiate the Tester RX: OUTPUT_TESTER
---------------------------------------------------------------------------
err_det_proc: process (rst, tester_clk)
begin
if rst = '1' then
elsif tester_clk'event and tester_clk = '1' then
assert (RESULT_GOOD = '1' or OVERFLOW = '1' )
report "ERROR DETECTED!" severity Error;
assert (OVERFLOW = '0')
report "TESTER OVERFLOW DETECTED!" severity Error;
end if;
end process;
DW_Sel_gen1: if TESTER_DWIDTH > 8 generate
output_tester_i: OUTPUT_TESTER
generic map
( GLOBALDLY => 1,
LL_DAT_BIT_WIDTH => TESTER_DWIDTH,
LL_REM_BIT_WIDTH => TESTER_REM_WIDTH,
FIFO_DEPTH => TESTER_FIFO_DEPTH)
port map
(
CLK => tester_clk, --I
RST => rst, --I
--Dut LocalLink Interface
RX_D => rx_d, --I --0:63
RX_REM => rx_rem, --I --0:2
RX_SOF_N => rx_sof_n, --I
RX_EOF_N => rx_eof_n, --I
RX_SRC_RDY_N => rx_src_rdy_n, --I
--Dut UFC Interface (not used)
UFC_RX_DATA => ufc_rx_d, --I
UFC_RX_REM => ufc_rx_rem, --I
UFC_RX_SOF_N => VCC, --I
UFC_RX_EOF_N => VCC, --I
UFC_RX_SRC_RDY_N => VCC, --I
--Reference LocalLink Interface
RX_SOF_N_REF => tx_sof_n, --I
RX_EOF_N_REF => tx_eof_n, --I
RX_REM_REF => tx_rem, --I
RX_DATA_REF => tx_d, --I
RX_SRC_RDY_N_REF => src_rdy_n_ref_i, --I
--Reference UFC Interface (not used)
UFC_RX_DATA_REF => ufc_rx_d, --I
UFC_RX_REM_REF => ufc_rx_rem, --I
UFC_RX_SOF_N_REF => VCC, --I
UFC_RX_EOF_N_REF => VCC, --I
UFC_RX_SRC_RDY_N_REF => VCC, --I
--Comparison result
WORKING => WORKING, --O
COMPARING => COMPARING,
OVERFLOW => OVERFLOW,
RESULT_GOOD => RESULT_GOOD, --O
RESULT_GOOD_PDU => RESULT_GOOD_PDU, --O
RESULT_GOOD_UFC => open --O
);
end generate DW_Sel_gen1;
DW_Sel_gen2: if TESTER_DWIDTH = 8 generate
output_tester_i: OUTPUT_TESTER_8_BIT
generic map
( GLOBALDLY => 1,
LL_DAT_BIT_WIDTH => TESTER_DWIDTH,
LL_REM_BIT_WIDTH => 0,
FIFO_DEPTH => TESTER_FIFO_DEPTH)
port map
(
CLK => tester_clk, --I
RST => rst, --I
--Dut LocalLink Interface
RX_D => rx_d, --I --0:63
RX_REM => rx_rem(0), --I --0:2
RX_SOF_N => rx_sof_n, --I
RX_EOF_N => rx_eof_n, --I
RX_SRC_RDY_N => rx_src_rdy_n, --I
--Dut UFC Interface (to tie)
UFC_RX_DATA => ufc_rx_d, --I
UFC_RX_REM => ufc_rx_rem(0), --I
UFC_RX_SOF_N => VCC, --I
UFC_RX_EOF_N => VCC, --I
UFC_RX_SRC_RDY_N => VCC, --I
--Reference LocalLink Interface (don't touch)
RX_SOF_N_REF => tx_sof_n, --I
RX_EOF_N_REF => tx_eof_n, --I
RX_REM_REF => tx_rem(0), --I
RX_DATA_REF => tx_d, --I
RX_SRC_RDY_N_REF => src_rdy_n_ref_i, --I
--Reference UFC Interface (to tie)
UFC_RX_DATA_REF => ufc_rx_d, --I
UFC_RX_REM_REF => ufc_rx_rem(0), --I
UFC_RX_SOF_N_REF => VCC, --I
UFC_RX_EOF_N_REF => VCC, --I
UFC_RX_SRC_RDY_N_REF => VCC, --I
--Comparison result
WORKING => WORKING, --O
COMPARING => COMPARING,
OVERFLOW => OVERFLOW,
RESULT_GOOD => RESULT_GOOD, --O
RESULT_GOOD_PDU => RESULT_GOOD_PDU, --O
RESULT_GOOD_UFC => open --O
);
end generate DW_Sel_gen2;
---------------------------------------------------------------------------
-- Generate Tester clock and Loopback clock
---------------------------------------------------------------------------
loopback_clkgen: process
begin
loopback_clk <= '0';
wait for LOOPBACK_CLK_HALF_PERIOD;
loopback_clk <= '1';
wait for LOOPBACK_CLK_HALF_PERIOD;
end process loopback_clkgen;
tester_clkgen: process
begin
tester_clk <= '0';
wait for TESTER_CLK_HALF_PERIOD;
tester_clk <= '1';
wait for TESTER_CLK_HALF_PERIOD;
end process tester_clkgen;
---------------------------------------------------------------------------
-- Generate Global Reset
---------------------------------------------------------------------------
reset_gen : process
begin
rst <= '1';
wait for 55 ns;
rst <= '0';
wait; -- will wait forever
end process reset_gen;
END ll_fifo_tb_arch;
|
gpl-3.0
|
665748104ded5086564ff4575126df4a
| 0.419992 | 4.283906 | false | true | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/xwb_crossbar.vhd
| 1 | 14,946 |
-------------------------------------------------------------------------------
-- Title : An MxS Wishbone crossbar switch
-- Project : General Cores Library (gencores)
-------------------------------------------------------------------------------
-- File : xwb_crossbar.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2011-06-08
-- Last update: 2011-09-22
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- An MxS Wishbone crossbar switch
--
-- All masters, slaves, and the crossbar itself must share the same WB clock.
-- All participants must support the same data bus width.
--
-- If a master raises STB_O with an address not mapped by the crossbar,
-- ERR_I will be raised. If two masters address the same slave
-- simultaneously, the lowest numbered master is granted access.
--
-- The implementation of this crossbar locks a master to a slave so long as
-- CYC_O is held high.
--
-- Synthesis/timing relevant facts:
-- (m)asters, (s)laves, masked (a)ddress bits
--
-- Area required = O(ms log(ma))
-- Arbitration depth = O(log(msa))
-- Master->Slave depth = O(log(m))
-- Slave->Master depth = O(log(s))
--
-- If g_registered = false, arbitration depth is added to M->S and S->M.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 GSI / Wesley W. Terpstra
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-05 3.0 wterpstra made address generic and check overlap
-- 2011-11-04 2.0 wterpstra timing improvements
-- 2011-06-08 1.0 wterpstra import from SVN
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity xwb_crossbar is
generic(
g_num_masters : integer := 2;
g_num_slaves : integer := 1;
g_registered : boolean := false;
-- Address of the slaves connected
g_address : t_wishbone_address_array;
g_mask : t_wishbone_address_array);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Master connections (INTERCON is a slave)
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
-- Slave connections (INTERCON is a master)
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0));
end xwb_crossbar;
architecture rtl of xwb_crossbar is
alias c_address : t_wishbone_address_array(g_num_slaves-1 downto 0) is g_address;
alias c_mask : t_wishbone_address_array(g_num_slaves-1 downto 0) is g_mask;
-- Confirm that no address ranges overlap
function f_ranges_ok
return boolean
is
constant zero : t_wishbone_address := (others => '0');
begin
for i in 0 to g_num_slaves-2 loop
for j in i+1 to g_num_slaves-1 loop
assert not (((c_mask(i) and c_mask(j)) and (c_address(i) xor c_address(j))) = zero) or
((c_mask(i) or not c_address(i)) = zero) or -- disconnected slave?
((c_mask(j) or not c_address(j)) = zero) -- disconnected slave?
report "Address ranges must be distinct (slaves " &
Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
f_bits2string(c_mask(i)) & "] & " &
Integer'image(j) & "[" & f_bits2string(c_address(j)) & "/" &
f_bits2string(c_mask(j)) & "])"
severity Failure;
end loop;
end loop;
for i in 0 to g_num_slaves-1 loop
report "Mapping slave #" &
Integer'image(i) & "[" & f_bits2string(c_address(i)) & "/" &
f_bits2string(c_mask(i)) & "]"
severity Note;
end loop;
return true;
end f_ranges_ok;
constant c_ok : boolean := f_ranges_ok;
-- Crossbar connection matrix
type matrix is array (g_num_masters-1 downto 0, g_num_slaves downto 0) of std_logic;
-- Add an 'error' device to the list of slaves
signal master_ie : t_wishbone_master_in_array(g_num_slaves downto 0);
signal master_oe : t_wishbone_master_out_array(g_num_slaves downto 0);
signal virtual_ERR : std_logic;
signal matrix_old : matrix; -- Registered connection matrix
signal matrix_new : matrix; -- The new values of the matrix
-- Either matrix_old or matrix_new, depending on g_registered
signal granted : matrix;
-- 1 => 0 2 => 1 3..4 => 2 5..8 => 3
function log2(i : natural) return natural is
begin
if i <= 1
then return 0;
else return log2((i+1)/2) + 1;
end if;
end log2;
-- 0 => 1 1 => 2 2 => 4 3 => 8
function pow2(i : natural) return natural is
begin
if i = 0
then return 1;
else return pow2(i-1)*2;
end if;
end pow2;
-- If any of the bits are '1', the whole thing is '1'
-- This function makes the check explicitly have logarithmic depth.
function vector_OR(x : std_logic_vector)
return std_logic
is
constant len : integer := x'length;
constant mid : integer := len / 2;
alias y : std_logic_vector(len-1 downto 0) is x;
begin
if len = 1
then return y(0);
else return vector_OR(y(len-1 downto mid)) or
vector_OR(y(mid-1 downto 0));
end if;
end vector_OR;
-- Kogge-Stone network of ORs.
-- A log(n) deep, n-wide circuit where:
-- output(i) = OR_{j<=i} input(j)
function ks_OR(input : std_logic_vector)
return std_logic_vector
is
constant width : natural := input'length;
constant stages : natural := log2(width);
variable prev : std_logic_vector(width-1 downto 0);
variable output : std_logic_vector(width-1 downto 0);
begin
prev := input;
if stages = 0 then
output := prev;
else
for l in 0 to stages-1 loop
for i in 0 to width-1 loop
if i >= pow2(l)
then output(i) := prev(i) or prev(i-pow2(l));
else output(i) := prev(i);
end if;
end loop;
prev := output;
end loop;
end if;
return output;
end ks_OR;
-- Impure because it accesses c_{address, mask}
function matrix_logic(
matrix_old : matrix;
slave_i : t_wishbone_slave_in_array(g_num_masters-1 downto 0))
return matrix
is
subtype row is std_logic_vector(g_num_masters-1 downto 0);
subtype column is std_logic_vector(g_num_slaves downto 0);
variable tmp : std_logic;
variable tmp_column : column;
variable tmp_row : row;
variable request : matrix; -- Which slaves do the masters address log(S)
variable selected : matrix; -- Which master wins arbitration log(M) request
variable sbusy : column; -- Does the slave's previous connection persist?
variable mbusy : row; -- Does the master's previous connection persist?
variable matrix_new : matrix;
begin
-- A slave is busy iff it services an in-progress cycle
for slave in g_num_slaves downto 0 loop
for master in g_num_masters-1 downto 0 loop
tmp_row(master) := matrix_old(master, slave) and slave_i(master).CYC;
end loop;
sbusy(slave) := vector_OR(tmp_row);
end loop;
-- A master is busy iff it services an in-progress cycle
for master in g_num_masters-1 downto 0 loop
for slave in g_num_slaves downto 0 loop
tmp_column(slave) := matrix_old(master, slave);
end loop;
mbusy(master) := vector_OR(tmp_column) and slave_i(master).CYC;
end loop;
-- Decode the request address to see if master wants access
for master in g_num_masters-1 downto 0 loop
for slave in g_num_slaves-1 downto 0 loop
tmp := not vector_OR((slave_i(master).ADR and c_mask(slave)) xor c_address(slave));
tmp_column(slave) := tmp;
request(master, slave) := slave_i(master).CYC and slave_i(master).STB and tmp;
end loop;
tmp_column(g_num_slaves) := '0';
-- If no slaves match request, bind to 'error device'
request(master, g_num_slaves) := slave_i(master).CYC and slave_i(master).STB and not vector_OR(tmp_column);
end loop;
-- Arbitrate among the requesting masters
-- Policy: lowest numbered master first
for slave in g_num_slaves downto 0 loop
-- OR together all the requests by higher priority masters
for master in 0 to g_num_masters-1 loop
tmp_row(master) := request(master, slave);
end loop;
tmp_row := ks_OR(tmp_row);
-- Grant to highest priority master
selected(0, slave) := request(0, slave); -- master 0 always wins
if g_num_masters > 1 then
for master in 1 to g_num_masters-1 loop
selected(master, slave) := -- only if requested and no lower requests
not tmp_row(master-1) and request(master, slave);
end loop;
end if;
end loop;
-- Determine the master granted access
-- Policy: if cycle still in progress, preserve the previous choice
for slave in g_num_slaves downto 0 loop
for master in g_num_masters-1 downto 0 loop
if sbusy(slave) = '1' or mbusy(master) = '1' then
matrix_new(master, slave) := matrix_old(master, slave);
else
matrix_new(master, slave) := selected(master, slave);
end if;
end loop;
end loop;
return matrix_new;
end matrix_logic;
subtype slave_row is std_logic_vector(g_num_masters-1 downto 0);
type slave_matrix is array (natural range <>) of slave_row;
function slave_matrix_OR(x : slave_matrix)
return std_logic_vector is
variable result : std_logic_vector(x'LENGTH-1 downto 0);
begin
for i in x'LENGTH-1 downto 0 loop
result(i) := vector_OR(x(i));
end loop;
return result;
end slave_matrix_OR;
-- Select the master pins the slave will receive
function slave_logic(slave : integer;
granted : matrix;
slave_i : t_wishbone_slave_in_array(g_num_masters-1 downto 0))
return t_wishbone_master_out
is
variable CYC_row : slave_row;
variable STB_row : slave_row;
variable ADR_matrix : slave_matrix(c_wishbone_address_width-1 downto 0);
variable SEL_matrix : slave_matrix((c_wishbone_address_width/8)-1 downto 0);
variable WE_row : slave_row;
variable DAT_matrix : slave_matrix(c_wishbone_data_width-1 downto 0);
begin
-- Rename all the signals ready for big_or
for master in g_num_masters-1 downto 0 loop
CYC_row(master) := slave_i(master).CYC and granted(master, slave);
STB_row(master) := slave_i(master).STB and granted(master, slave);
for bit in c_wishbone_address_width-1 downto 0 loop
ADR_matrix(bit)(master) := slave_i(master).ADR(bit) and granted(master, slave);
end loop;
for bit in (c_wishbone_address_width/8)-1 downto 0 loop
SEL_matrix(bit)(master) := slave_i(master).SEL(bit) and granted(master, slave);
end loop;
WE_row(master) := slave_i(master).WE and granted(master, slave);
for bit in c_wishbone_data_width-1 downto 0 loop
DAT_matrix(bit)(master) := slave_i(master).DAT(bit) and granted(master, slave);
end loop;
end loop;
return (
CYC => vector_OR(CYC_row),
STB => vector_OR(STB_row),
ADR => slave_matrix_OR(ADR_matrix),
SEL => slave_matrix_OR(SEL_matrix),
WE => vector_OR(WE_row),
DAT => slave_matrix_OR(DAT_matrix));
end slave_logic;
subtype master_row is std_logic_vector(g_num_slaves downto 0);
type master_matrix is array (natural range <>) of master_row;
function master_matrix_OR(x : master_matrix)
return std_logic_vector is
variable result : std_logic_vector(x'LENGTH-1 downto 0);
begin
for i in x'LENGTH-1 downto 0 loop
result(i) := vector_OR(x(i));
end loop;
return result;
end master_matrix_OR;
-- Select the slave pins the master will receive
function master_logic(master : integer;
granted : matrix;
master_ie : t_wishbone_master_in_array(g_num_slaves downto 0))
return t_wishbone_slave_out
is
variable ACK_row : master_row;
variable ERR_row : master_row;
variable RTY_row : master_row;
variable STALL_row : master_row;
variable DAT_matrix : master_matrix(c_wishbone_data_width-1 downto 0);
begin
-- We use inverted logic on STALL so that if no slave granted => stall
for slave in g_num_slaves downto 0 loop
ACK_row(slave) := master_ie(slave).ACK and granted(master, slave);
ERR_row(slave) := master_ie(slave).ERR and granted(master, slave);
RTY_row(slave) := master_ie(slave).RTY and granted(master, slave);
STALL_row(slave) := not master_ie(slave).STALL and granted(master, slave);
for bit in c_wishbone_data_width-1 downto 0 loop
DAT_matrix(bit)(slave) := master_ie(slave).DAT(bit) and granted(master, slave);
end loop;
end loop;
return (
ACK => vector_OR(ACK_row),
ERR => vector_OR(ERR_row),
RTY => vector_OR(RTY_row),
STALL => not vector_OR(STALL_row),
DAT => master_matrix_OR(DAT_matrix),
INT => '0');
end master_logic;
begin
-- The virtual error slave is pretty straight-forward:
master_o <= master_oe(g_num_slaves-1 downto 0);
master_ie(g_num_slaves-1 downto 0) <= master_i;
master_ie(g_num_slaves) <= (
ACK => '0',
ERR => virtual_ERR,
RTY => '0',
STALL => '0',
DAT => (others => '0'),
INT => '0');
virtual_error_slave : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
virtual_ERR <= master_oe(g_num_slaves).CYC and master_oe(g_num_slaves).STB;
end if;
end process virtual_error_slave;
-- Copy the matrix to a register:
matrix_new <= matrix_logic(matrix_old, slave_i);
main : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
matrix_old <= (others => (others => '0'));
else
matrix_old <= matrix_new;
end if;
end if;
end process main;
-- Is the crossbar combinatorial or registered
granted <= matrix_old when g_registered else matrix_new;
-- Make the slave connections
slave_matrixs : for slave in g_num_slaves downto 0 generate
master_oe(slave) <= slave_logic(slave, granted, slave_i);
end generate;
-- Make the master connections
master_matrixs : for master in g_num_masters-1 downto 0 generate
slave_o(master) <= master_logic(master, granted, master_ie);
end generate;
end rtl;
|
lgpl-3.0
|
80d60fb289d1408eef77226c8a1ec944
| 0.601365 | 3.583313 | false | false | false | false |
luebbers/reconos
|
support/threads/dummy_ul.vhd
| 1 | 2,810 |
--
-- \file dummy_ul.vhd
--
-- Dummy hardware thread
--
-- Does not do ANYTHING. What a life.
--
-- \author Enno Luebbers <[email protected]>
-- \date 27.01.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dummy_ul is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end dummy_ul;
architecture Behavioral of dummy_ul is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
type t_state is ( STATE_WAIT );
signal state : t_state := STATE_WAIT;
begin
state_proc: process( clk, reset )
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_WAIT;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_WAIT =>
-- wiggle pins to prevent being optimized away
o_RAMData <= not i_RAMData;
when others =>
state <= STATE_WAIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
72e4393d9d7c0c60d03fe3f04bfd153b
| 0.624911 | 3.552465 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/lisipif_master_v1_00_c/hdl/vhdl/lipif_mst_write.vhd
| 1 | 8,664 |
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_slv_write
-- Architectures: lipif_slv_write_rtl
-- Description:
--
-- Dependencies:
--
-- Revision:
-- 11.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lipif_mst_write is
generic (
C_NUM_WIDTH : integer := 5;
C_EN_SRL16 : boolean := true;
C_EN_FAST_ABORT : boolean := false
);
port (
clk : in std_logic;
reset : in std_logic;
-- Control Signals to/from Arbiter
xfer_rdy_o : out std_logic;
xfer_init_i : in std_logic;
xfer_ack_i : in std_logic;
xfer_rearb_i : in std_logic;
xfer_retry_o : out std_logic;
xfer_abort_o : out std_logic;
-- LIS-IPIC Transfer Signals
M_wrNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_wrRearb_o : out std_logic;
M_wrAbort_i : in std_logic;
M_wrError_o : out std_logic;
M_wrData_i : in std_logic_vector(63 downto 0);
M_wrRdy_o : out std_logic;
M_wrAck_o : out std_logic;
M_wrComp_o : out std_logic;
-- PLB Signals
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63)
);
end lipif_mst_write;
architecture lipif_mst_write_rtl of lipif_mst_write is
signal prim_valid : std_logic;
signal prim_ack : std_logic;
signal prim_num : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal prim_num_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal prim_comp : std_logic;
signal prim_last : std_logic;
signal prim_last_n : std_logic;
-- Transfer termination requests from IP/PLB
signal mst_term : std_logic;
signal mst_term_r : std_logic; -- Track until transfer complete
signal plb_term : std_logic;
signal data_num : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal data_num_n : std_logic_vector(C_NUM_WIDTH-1 downto 0);
signal data_done : std_logic;
signal data_req : std_logic;
signal data_rdy : std_logic;
signal data_flush : std_logic;
begin
-- Signals to load new data into data buffer
data_done <= '1' when (data_num=0) else '0';
data_req <= data_rdy and (not data_done or xfer_init_i);
M_wrRdy_o <= data_req;
-- Flush data buffer if transfer aborted prematurely
data_flush <= reset or (prim_comp and not prim_last);
-- Pipelining not possible due to the inability of inserting a
-- latency after a slave-initiated transfer termination.
xfer_rdy_o <= not prim_valid;
-- Pass rearbitration signal to IP
M_wrRearb_o <= xfer_rearb_i and not prim_ack;
-- Control signals to arbiter (Affect arbiter only!)
xfer_retry_o <= xfer_rearb_i and not prim_ack;
xfer_abort_o <= mst_term and prim_valid and not prim_ack;
-- Next IP data count, subtraction and ce occur below
data_num_n <= M_wrNum_i when (xfer_init_i='1') else data_num;
-- Assert prim_comp to complete transfer:
-- * with last d-ack of transfer
-- * with next d-ack when plb_term or mst_term are asserted
-- * with mst_term when primary transfer not acknowledged
process(PLB_MWrDAck, prim_last, plb_term, mst_term, prim_ack) begin
if(PLB_MWrDAck='1') then
prim_comp <= prim_last or plb_term or mst_term;
else
prim_comp <= mst_term and not prim_ack;
end if;
end process;
-- Generate PLB remaining transfer counter signals (M_wrBurst, prim_num, prim_last)
-- TIMING(18%) M_wrBurst is a register, so no problem
-- TODO: When C_EN_FAST_ABORT, M_wrBurst must respond with M_wrAbort
prim_num_n <= M_wrNum_i when(xfer_init_i='1') else prim_num - 1;
prim_last_n <= '1' when (prim_num_n(C_NUM_WIDTH-1 downto 1)=0) else '0';
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
M_wrBurst <= '0';
prim_last <= '0';
prim_num <= (others=>'0');
else
-- Burst must go low in response to PLB/IP abort
if(PLB_MWrBTerm='1' or M_wrAbort_i='1') then
M_wrBurst <= '0';
-- Update burst signal at start of transfer, or with each data ack
elsif(xfer_init_i='1' or PLB_MWrDAck='1') then
M_wrBurst <= not prim_last_n;
end if;
-- Update transfer counter at start of transfer, or with each data ack
if(xfer_init_i='1' or PLB_MWrDAck='1') then
prim_last <= prim_last_n;
prim_num <= prim_num_n;
end if;
end if;
end if;
end process;
-- Latch IP termination request until completion of transfer
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
mst_term_r <= '0';
else
if(prim_comp='1') then
mst_term_r <= '0';
elsif(M_wrAbort_i='1') then
mst_term_r <= '1';
end if;
end if;
end if;
end process;
-- When not C_EN_FAST_ABORT, assert terminate signal immediately only if rearbitrating
-- TODO: Remove resulting combinatorial dependance of M_abort on M_wrAbort_i
NEN_FAST_ABORT: if(not C_EN_FAST_ABORT) generate
mst_term <= M_wrAbort_i when(xfer_rearb_i='1') else mst_term_r;
end generate NEN_FAST_ABORT;
-- When C_EN_FAST_ABORT, always pass M_wrAbort_i through
EN_FAST_ABORT: if(C_EN_FAST_ABORT) generate
mst_term <= '1' when(mst_term_r='1') else M_wrAbort_i;
end generate EN_FAST_ABORT;
-- Various registers
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
prim_valid <= '0';
prim_ack <= '0';
data_num <= (others=>'0');
M_wrError_o <= '0';
M_wrComp_o <= '0';
M_wrAck_o <= '0';
plb_term <= '0';
else
-- Primary transfer valid
if(xfer_init_i='1') then
prim_valid <= '1';
elsif(prim_comp='1') then
prim_valid <= '0';
end if;
-- Primary transfer acknowledged by slave
if(xfer_ack_i='1') then
prim_ack <= '1';
elsif(prim_comp='1') then
prim_ack <= '0';
end if;
-- Remaining IP required data count
if(prim_comp='1') then
data_num <= (others=>'0');
elsif(data_req='1') then
data_num <= data_num_n - 1;
else
data_num <= data_num_n;
end if;
-- Error occurred if transfer completes before all data was transferred,
-- or if transfer was never acknowledged
M_wrError_o <= prim_comp and (not prim_last or (not prim_ack and not xfer_ack_i));
-- IPIC's complete signal is pipeliner's complete signal delayed
M_wrComp_o <= prim_comp;
-- Data acknowledge to IP
M_wrAck_o <= PLB_MWrDAck;
-- Previous termination request by slave
if(prim_comp='1') then
plb_term <= '0';
elsif(PLB_MWrBTerm='1') then
plb_term <= '1';
end if;
end if;
end if;
end process;
-- Instantiate data buffer
pipebuf_0: entity lisipif_master_v1_00_c.lipif_mst_pipebuf
generic map (
C_DATA_WIDTH => 64,
-- Since SRL outputs are slow (>3ns after clk), must use registers
-- to meet PLB timings.
C_EN_SRL16 => false
)
port map (
clk => clk,
reset => data_flush,
-- Previous (input) stage I/O
prevReq_i => data_req,
prevRdy_o => data_rdy,
prevData_i => M_wrData_i,
-- Next (output) stage I/O
nextReq_o => open,
nextRdy_i => PLB_MWrDAck,
nextData_o => M_wrDBus
);
end lipif_mst_write_rtl;
|
gpl-3.0
|
7ea8bbfea18b337f892a091f3c3166db
| 0.548476 | 3.596513 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/GPIO/src/hdl/RGB_controller.vhd
| 1 | 5,183 |
----------------------------------------------------------------------------
-- RGB_controller.vhd -- Nexys4 RGB LED controller
----------------------------------------------------------------------------
-- Author: Marshall Wingerson
-- Copyright 2013 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2013(MarshallW): Created
-- 08/30/2013(SamB): Modified RGB pattern
-- Added comments
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
entity RGB_controller is
port(
GCLK : in std_logic;
RGB_LED_1_O : out std_logic_vector(2 downto 0);
RGB_LED_2_O : out std_logic_vector(2 downto 0)
);
end RGB_controller;
architecture Behavioral of RGB_controller is
--counter signals
constant window: std_logic_vector(7 downto 0) := "11111111";
signal windowcount: std_logic_vector(7 downto 0) := (others => '0');
constant deltacountMax: std_logic_vector(19 downto 0) := std_logic_vector(to_unsigned(1000000, 20));
signal deltacount: std_logic_vector(19 downto 0) := (others => '0');
constant valcountMax: std_logic_vector(8 downto 0) := "101111111";
signal valcount: std_logic_vector(8 downto 0) := (others => '0');
--color intensity signals
signal incVal: std_logic_vector(7 downto 0);
signal decVal: std_logic_vector(7 downto 0);
signal redVal: std_logic_vector(7 downto 0);
signal greenVal: std_logic_vector(7 downto 0);
signal blueVal: std_logic_vector(7 downto 0);
signal redVal2: std_logic_vector(7 downto 0);
signal greenVal2: std_logic_vector(7 downto 0);
signal blueVal2: std_logic_vector(7 downto 0);
--PWM registers
signal rgbLedReg1: std_logic_vector(2 downto 0);
signal rgbLedReg2: std_logic_vector(2 downto 0);
begin
window_counter:process(GCLK)
begin
if(rising_edge(GCLK)) then
if windowcount < (window) then
windowcount <= windowcount + 1;
else
windowcount <= (others => '0');
end if;
end if;
end process;
color_change_counter:process(GCLK)
begin
if(rising_edge(GCLK)) then
if(deltacount < deltacountMax) then
deltacount <= deltacount + 1;
else
deltacount <= (others => '0');
end if;
end if;
end process;
color_intensity_counter:process(GCLK)
begin
if(rising_edge(GCLK)) then
if(deltacount = 0) then
if(valcount < valcountMax) then
valcount <= valcount + 1;
else
valcount <= (others => '0');
end if;
end if;
end if;
end process;
incVal <= "0" & valcount(6 downto 0);
--The folowing code sets decVal to (128 - incVal)
decVal(7) <= '0';
decVal(6) <= not(valcount(6));
decVal(5) <= not(valcount(5));
decVal(4) <= not(valcount(4));
decVal(3) <= not(valcount(3));
decVal(2) <= not(valcount(2));
decVal(1) <= not(valcount(1));
decVal(0) <= not(valcount(0));
redVal <= incVal when (valcount(8 downto 7) = "00") else
decVal when (valcount(8 downto 7) = "01") else
(others => '0');
greenVal <= decVal when (valcount(8 downto 7) = "00") else
(others => '0') when (valcount(8 downto 7) = "01") else
incVal;
blueVal <= (others => '0') when (valcount(8 downto 7) = "00") else
incVal when (valcount(8 downto 7) = "01") else
decVal;
redVal2 <= incVal when (valcount(8 downto 7) = "00") else
decVal when (valcount(8 downto 7) = "01") else
(others => '0');
greenVal2 <= decVal when (valcount(8 downto 7) = "00") else
(others => '0') when (valcount(8 downto 7) = "01") else
incVal;
blueVal2 <= (others => '0') when (valcount(8 downto 7) = "00") else
incVal when (valcount(8 downto 7) = "01") else
decVal;
--red processes
red_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((redVal) > windowcount) then
rgbLedReg1(2) <= '1';
else
rgbLedReg1(2) <= '0';
end if;
end if;
end process;
--green processes
green_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((greenVal) > windowcount) then
rgbLedReg1(1) <= '1';
else
rgbLedReg1(1) <= '0';
end if;
end if;
end process;
--blue processes
blue_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((blueVal) > windowcount) then
rgbLedReg1(0) <= '1';
else
rgbLedReg1(0) <= '0';
end if;
end if;
end process;
--RGB2 processes---
--red2 processes
red2_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((redVal2) > windowcount) then
rgbLedReg2(2) <= '1';
else
rgbLedReg2(2) <= '0';
end if;
end if;
end process;
--green2 processes
green2_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((greenVal2) > windowcount) then
rgbLedReg2(1) <= '1';
else
rgbLedReg2(1) <= '0';
end if;
end if;
end process;
--blue2 processes
blue2_comp:process(GCLK)
begin
if(rising_edge(GCLK)) then
if((blueVal2) > windowcount) then
rgbLedReg2(0) <= '1';
else
rgbLedReg2(0) <= '0';
end if;
end if;
end process;
RGB_LED_1_O <= rgbLedReg1;
RGB_LED_2_O <= rgbLedReg2;
end Behavioral;
|
gpl-3.0
|
0cfa31006a75b23fa4d986f995cfe0fa
| 0.594057 | 3.15076 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/uart_async_rx.vhd
| 1 | 5,479 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_async_rx is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baud8_tick_i: in std_logic;
rxd_i : in std_logic;
rx_ready_o : out std_logic;
rx_error_o : out std_logic;
rx_data_o : out std_logic_vector(7 downto 0)
);
end uart_async_rx;
architecture behavioral of uart_async_rx is
signal Baud8Tick : std_logic;
signal RxD_sync_inv : std_logic_vector(1 downto 0);
signal RxD_cnt_inv : unsigned(1 downto 0);
signal RxD_bit_inv : std_logic;
signal state : std_logic_vector(3 downto 0);
signal bit_spacing : std_logic_vector(3 downto 0);
signal next_bit : std_logic;
signal RxD_data : std_logic_vector(7 downto 0);
signal RxD_data_ready : std_logic;
signal RxD_data_error : std_logic;
begin -- behavioral
Baud8Tick <= baud8_tick_i;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
RxD_sync_inv <= (others => '0');
else
if(Baud8Tick = '1') then
RxD_sync_inv <= RxD_sync_inv(0) & (not rxd_i);
end if;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
RxD_bit_inv <= '0';
RxD_cnt_inv <= (others => '0');
else
if(Baud8Tick = '1') then
if(RxD_sync_inv(1) = '1' and RxD_cnt_inv /= "11") then
RxD_cnt_inv <= RxD_cnt_inv + 1;
elsif (RxD_sync_inv(1) = '0' and RxD_cnt_inv /= "00") then
RxD_cnt_inv <= RxD_cnt_inv - 1;
end if;
if(RxD_cnt_inv = "00") then
RxD_bit_inv <= '0';
elsif(RxD_cnt_inv = "11") then
RxD_bit_inv <= '1';
end if;
end if;
end if;
end if;
end process;
next_bit <= '1' when (bit_spacing = x"a") else '0';
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
bit_spacing <= (others => '0');
else
if(state = x"0") then
bit_spacing <= "0000";
elsif(Baud8Tick = '1') then
-- bit_spacing <= std_logic_vector(resize((unsigned(bit_spacing(2 downto 0)) + 1), 4))
bit_spacing <= std_logic_vector(unsigned('0' & bit_spacing(2 downto 0)) + 1)
or (bit_spacing(3) & "000");
end if;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= (others => '0');
else
if(Baud8Tick = '1') then
case state is
when "0000" =>
if(RxD_bit_inv = '1') then -- start bit
state <= "1000";
end if;
when "1000" =>
if(next_bit = '1') then
state <= "1001"; -- bit 0
end if;
when "1001" =>
if(next_bit = '1') then
state <= "1010"; -- bit 1
end if;
when "1010" =>
if(next_bit = '1') then
state <= "1011"; -- bit 2
end if;
when "1011" =>
if(next_bit = '1') then
state <= "1100"; -- bit 3
end if;
when "1100" =>
if(next_bit = '1') then
state <= "1101"; -- bit 4
end if;
when "1101" =>
if(next_bit = '1') then
state <= "1110"; -- bit 5
end if;
when "1110" =>
if(next_bit = '1') then
state <= "1111"; -- bit 6
end if;
when "1111" =>
if(next_bit = '1') then
state <= "0001"; -- bit 7
end if;
when "0001" =>
if(next_bit = '1') then
state <= "0000"; -- bit stop
end if;
when others => state <= "0000";
end case;
end if;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
RxD_data <= (others => '0');
else
if(Baud8Tick = '1' and next_bit = '1' and state(3) = '1') then
RxD_data <= (not RxD_bit_inv) & RxD_data(7 downto 1);
end if;
end if;
end if;
end process;
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
RxD_data_error <= '0';
RxD_data_ready <= '0';
else
if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '0') then
RxD_data_ready <= '1';
else
RxD_data_ready <= '0';
end if;
if(Baud8Tick = '1' and next_bit = '1' and state = "0001" and RxD_bit_inv = '1') then
RxD_data_error <= '1';
else
RxD_data_error <= '0';
end if;
end if;
end if;
end process;
rx_data_o <= RxD_data;
rx_ready_o <= RxD_data_ready;
rx_error_o <= RxD_data_error;
end behavioral;
|
lgpl-3.0
|
1653c771069f8cedf70f0c633e5887b7
| 0.444059 | 3.39257 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/xup/opb_eth_tft_cf/pcores/opb_ac97_v2_00_a/hdl/vhdl/command_fifo.vhd
| 4 | 28,636 |
-------------------------------------------------------------------------------
-- $Id: command_fifo.vhd,v 1.1 2005/02/18 15:30:22 wirthlin Exp $
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename:
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2005/02/18 15:30:22 $
--
-- History:
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
use UNISIM.vcomponents.all;
entity command_fifo is
port (
Clk : in std_logic;
Reset : in std_logic;
NextCommand : in std_logic;
CommandNum : out std_logic_vector(8 downto 0);
Data : out std_logic_vector(15 downto 0);
Address : out std_logic_vector(6 downto 0);
ValidCommand: out std_logic
);
end entity command_fifo;
-- Commands for AC97:
-- WriteAC97Reg(0x0,0x0); // reset registers
-- WriteAC97Reg(0x2,0x808); // master volume (0db gain)
-- WriteAC97Reg(0xa,0x8000); // mute PC beep
-- WriteAC97Reg(0x4,0x808); // headphone vol (aux out)
-- WriteAC97Reg(0x18,0x808); // pcmoutvol (amp out line)
-- WriteAC97Reg(0x1a,0x404); // record source (line in for left and right)
-- WriteAC97Reg(0x1c,0x008); // record gain (8 steps of 1.5 dB = +12.0 dB)
-- WriteAC97Reg(0x20,0x1); // bypass 3d sound
-- 80000000
-- 80020808
-- 800a8000
-- 80040808
-- 80180808
-- 801a0404
-- 801c0008
-- 80200001
-- 80200001801c0008801a04048018080880040808800a80008002080880000000
architecture IMP of command_fifo is
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0a : string;
attribute INIT_0b : string;
attribute INIT_0c : string;
attribute INIT_0d : string;
attribute INIT_0e : string;
attribute INIT_0f : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1a : string;
attribute INIT_1b : string;
attribute INIT_1c : string;
attribute INIT_1d : string;
attribute INIT_1e : string;
attribute INIT_1f : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2a : string;
attribute INIT_2b : string;
attribute INIT_2c : string;
attribute INIT_2d : string;
attribute INIT_2e : string;
attribute INIT_2f : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3a : string;
attribute INIT_3b : string;
attribute INIT_3c : string;
attribute INIT_3d : string;
attribute INIT_3e : string;
attribute INIT_3f : string;
attribute INIT_00 of u1 : label is
"80200001801c0008801a04048018080880040808800a80008002080880000000";
attribute INIT_01 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3a of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3b of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3c of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3d of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3e of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3f of u1 : label is
"0000000000000000000000000000000000000000000000000000000000000000";
component RAMB16_S36
generic (
INIT : bit_vector := X"000000000";
SRVAL : bit_vector := X"000000000";
write_mode : string := "WRITE_FIRST";
INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"
);
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
signal xram_di : std_logic_vector(31 downto 0); -- BlockRAM data in (zero)
signal command_addr : unsigned(8 downto 0); -- BlockRAM data in (zero)
signal xram_addr : std_logic_vector(8 downto 0); -- BlockRAM data in (zero)
signal xram_dip : std_logic_vector(3 downto 0); -- BlockRAM data in (zero)
signal xram_dop : std_logic_vector(3 downto 0); -- BlockRAM data out
signal xram_en : std_logic; -- BlockRAM enable (always on)
signal xram_we : std_logic; -- BlockRAM write enable (zero)
signal xram_reset : std_logic; -- BlockRAM reset (zero)
signal xram_do : std_logic_vector(31 downto 0);
begin
-- address (need to define)
block_ram_address_PROCESS : process (Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
command_addr <= (others => '0');
elsif NextCommand = '1' then
command_addr <= command_addr + 1;
end if;
end if;
end process;
-- Define input signals to BlockRam
xram_di <= (others => '0'); -- no data in
xram_dip <= (others => '0'); -- 2-bit data (not used)
xram_en <= '1'; -- always enabled
xram_we <= '0'; -- do not need to write
xram_reset <= '0';
Data <= xram_do(15 downto 0);
Address <= xram_do(22 downto 16);
ValidCommand <= xram_do(31);
-- Instance the BlockRam
u1: RAMB16_S36
--translate_off
-- Note that the these generic map values are used for simulation
-- only. To insure that the simulation matches the actual ram values,
-- make sure that the attributes used above are the same as the
-- generics used below.
generic map (
INIT_00 =>
X"80200001801c0008801a04048018080880040808800a80008002080880000000",
INIT_01 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2f =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3a =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3b =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3c =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3d =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3e =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3f =>
X"0000000000000000000000000000000000000000000000000000000000000000"
)
--translate_on
port map(
di => xram_di,
dip => xram_dip,
addr => xram_addr,
do => xram_do,
dop => xram_dop,
clk => clk,
SSR => xram_reset,
EN => xram_en,
WE => xram_we
);
xram_addr <= CONV_STD_LOGIC_VECTOR(command_addr, command_addr'length);
CommandNum <= xram_addr;
end architecture IMP;
|
gpl-3.0
|
be259067659a3318e30979e44453cc0c
| 0.709457 | 5.921423 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/uart_baud_gen.vhd
| 1 | 1,475 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_baud_gen is
generic (
g_baud_acc_width : integer := 16);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
baudrate_i : in std_logic_vector(g_baud_acc_width downto 0);
baud_tick_o : out std_logic;
baud8_tick_o : out std_logic);
end uart_baud_gen;
architecture behavioral of uart_baud_gen is
signal Baud8GeneratorInc : unsigned(g_baud_acc_width downto 0);
signal Baud8GeneratorAcc : unsigned(g_baud_acc_width downto 0);
signal Baud8Tick : std_logic;
signal Baud_sreg : std_logic_vector(7 downto 0) := "10000000";
begin -- behavioral
Baud8GeneratorInc <= unsigned(baudrate_i);
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
Baud8GeneratorAcc <= (others => '0');
else
Baud8GeneratorAcc <= ('0' & Baud8GeneratorAcc(Baud8GeneratorAcc'high-1 downto 0)) + Baud8GeneratorInc;
end if;
end if;
end process;
Baud8Tick <= std_logic(Baud8GeneratorAcc(g_baud_acc_width));
process(clk_sys_i, rst_n_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
Baud_sreg <= "10000000";
elsif Baud8Tick = '1' then
Baud_sreg <= Baud_sreg(0) & Baud_sreg(7 downto 1);
end if;
end if;
end process;
baud_tick_o <= Baud_sreg(0) and Baud8Tick;
baud8_tick_o <= Baud8Tick;
end behavioral;
|
lgpl-3.0
|
c78ecf494fd7477e9eabf96bfc11c639
| 0.634576 | 3.034979 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/vhdl_case_multi.vhd
| 2 | 1,354 |
-- Copyright (c) 2014 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for multiple choices in case alternative statements.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_case_multi is
port ( inp: in std_logic_vector (0 to 2);
parity: out std_logic );
end vhdl_case_multi;
architecture vhdl_case_multi_rtl of vhdl_case_multi is
begin
process (inp)
begin
case inp is
when "000"|"011"|"101"|"110" => parity <= "0";
when "001"|"010"|"100"|"111" => parity <= "1";
when others => parity <= "Z";
end case;
end process;
end vhdl_case_multi_rtl;
|
gpl-2.0
|
5c0bb919c8be2dd573a85ddf356e2028
| 0.697932 | 3.814085 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/RamCntrl.vhd
| 1 | 14,263 |
-----------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2013, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : RamCtrl.vhd
-- MODULE NAME : Static Random Access Memory Controller
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2011-12-08 Mihaita Nagy Created
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements the state machine to control the
-- basic read and write procedures of a RAM memory.
-- It is also capable of 32-bit access using two consecutive
-- 16-bit accesses and 8-bit access as well, using the UB/LB pins.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RamCntrl is
generic (
-- read/write cycle (ns)
C_RW_CYCLE_NS : integer := 100
);
port (
-- Control interface
clk_i : in std_logic; -- 100 MHz system clock
rst_i : in std_logic; -- active high system reset
rnw_i : in std_logic; -- read/write
be_i : in std_logic_vector(3 downto 0); -- byte enable
addr_i : in std_logic_vector(31 downto 0); -- address input
data_i : in std_logic_vector(31 downto 0); -- data input
cs_i : in std_logic; -- active high chip select
data_o : out std_logic_vector(31 downto 0); -- data output
rd_ack_o : out std_logic; -- read acknowledge flag
wr_ack_o : out std_logic; -- write acknowledge flag
-- RAM Memory signals
Mem_A : out std_logic_vector(26 downto 0); -- Address
Mem_DQ_O : out std_logic_vector(15 downto 0); -- Data Out
Mem_DQ_I : in std_logic_vector(15 downto 0); -- Data In
Mem_DQ_T : out std_logic_vector(15 downto 0); -- Data Tristate Enable, used for a bidirectional data bus only
Mem_CEN : out std_logic; -- Chip Enable
Mem_OEN : out std_logic; -- Output Enable
Mem_WEN : out std_logic; -- Write Enable
Mem_UB : out std_logic; -- Upper Byte
Mem_LB : out std_logic -- Lower Byte
);
end RamCntrl;
architecture Behavioral of RamCntrl is
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- State machine state names
type States is(Idle, AssertCen, AssertOenWen, Waitt, Deassert, SendData,
Ack, Done);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- State machine signals
signal State, NState: States := Idle;
-- For a 32-bit access, two cycles are needed
signal TwoCycle: std_logic := '0';
-- Memory LSB
signal AddrLsb: std_logic;
-- RnW registerred signal
signal RnwInt: std_logic;
-- Byte enable internal bus
signal BeInt: std_logic_vector(3 downto 0);
-- Internal registerred Bus2IP_Addr bus
signal AddrInt: std_logic_vector(31 downto 0);
-- Internal registerred Bus2IP_Data bus
signal Data2WrInt: std_logic_vector(31 downto 0);
-- Internal registerred IP2_Bus bus
signal DataRdInt: std_logic_vector(31 downto 0);
-- Integer for the counter of the rd/wr cycle time
signal CntCycleTime: integer range 0 to 255;
signal RstInt : std_logic;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Register internal signals
------------------------------------------------------------------------
REGISTER_INT: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Idle then
RnwInt <= rnw_i;
BeInt <= be_i;
AddrInt <= addr_i;
Data2WrInt <= data_i;
RstInt <=rst_i;
end if;
end if;
end process REGISTER_INT;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Initialize the state machine
FSM_REGISTER_STATES: process(clk_i)
begin
if rising_edge(clk_i) then
if RstInt = '1' then
State <= Idle;
else
State <= NState;
end if;
end if;
end process FSM_REGISTER_STATES;
-- State machine transitions
FSM_TRANSITIONS: process(cs_i, TwoCycle, CntCycleTime, State)
begin
case State is
when Idle =>
if cs_i = '1' then
NState <= AssertCen;
else
NState <= Idle;
end if;
when AssertCen => NState <= AssertOenWen;
when AssertOenWen => NState <= Waitt;
when Waitt =>
if CntCycleTime = ((C_RW_CYCLE_NS/10) - 2) then
NState <= Deassert;
else
NState <= Waitt;
end if;
when Deassert => NState <= SendData;
when SendData =>
if TwoCycle = '1' then
NState <= AssertCen;
else
NState <= Ack;
end if;
when Ack => NState <= Done;
when Done => NState <= Idle;
when others => Nstate <= Idle;
end case;
end process FSM_TRANSITIONS;
------------------------------------------------------------------------
-- Counter for the write/read cycle time
------------------------------------------------------------------------
CYCLE_COUNTER: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Waitt then
CntCycleTime <= CntCycleTime + 1;
else
CntCycleTime <= 0;
end if;
end if;
end process CYCLE_COUNTER;
------------------------------------------------------------------------
-- Assert CEN
------------------------------------------------------------------------
ASSERT_CEN: process(clk_i)
begin
if rising_edge(clk_i) then
if State = AssertOenWen or
State = Waitt or
State = Deassert then
Mem_CEN <= '0';
else
Mem_CEN <= '1';
end if;
end if;
end process ASSERT_CEN;
------------------------------------------------------------------------
-- Assert WEN/OEN
------------------------------------------------------------------------
ASSERT_WENOEN: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Waitt or State = Deassert then
if RnwInt = '1' then
Mem_OEN <= '0';
Mem_WEN <= '1';
else
Mem_OEN <= '1';
Mem_WEN <= '0';
end if;
else
Mem_OEN <= '1';
Mem_WEN <= '1';
end if;
end if;
end process ASSERT_WENOEN;
------------------------------------------------------------------------
-- When a 32-bit access mode has to be performed, assert the TwoCycle
-- signal
------------------------------------------------------------------------
ASSIGN_TWOCYCLE: process(clk_i)
begin
if rising_edge(clk_i) then
if RstInt = '1' then
TwoCycle <= '0';
elsif State = AssertCen and be_i = "1111" then -- 32-bit access
TwoCycle <= not TwoCycle;
end if;
end if;
end process ASSIGN_TWOCYCLE;
------------------------------------------------------------------------
-- Assign AddrLsb signal
------------------------------------------------------------------------
ASSIGN_ADDR_LSB: process(clk_i)
begin
if rising_edge(clk_i) then
if RstInt = '1' then
AddrLsb <= '0';
elsif State = AssertCen then
case BeInt is
-- In 32-bit access: first the lowest address then the highest
-- address is written
when "1111" => AddrLsb <= not TwoCycle;
-- Higher address
when "1100"|"0100"|"1000" => AddrLsb <= '1';
-- Lower address
when "0011"|"0010"|"0001" => AddrLsb <= '0';
when others => null;
end case;
end if;
end if;
end process ASSIGN_ADDR_LSB;
------------------------------------------------------------------------
-- Assign Mem_A
------------------------------------------------------------------------
ASSIGN_ADDRESS: process(clk_i)
begin
if rising_edge(clk_i) then
if RstInt = '1' then
Mem_A <= (others => '0');
elsif State = AssertOenWen or
State = Waitt or
State = Deassert then
Mem_A <= AddrInt(26 downto 1) & AddrLsb;
end if;
end if;
end process ASSIGN_ADDRESS;
------------------------------------------------------------------------
-- Assign Mem_DQ_O and Mem_DQ_T
------------------------------------------------------------------------
ASSIGN_DATA: process(clk_i)
begin
if rising_edge(clk_i) then
if ((State = AssertOenWen or State = Waitt or State = Deassert) and RnwInt = '0') then
case BeInt is
when "1111" =>
if TwoCycle = '1' then
-- Write lowest address with MSdata
Mem_DQ_O <= Data2WrInt(15 downto 0);
else
-- Write highest address with LSdata
Mem_DQ_O <= Data2WrInt(31 downto 16);
end if;
when "0011"|"0010"|"0001" => Mem_DQ_O <= Data2WrInt(15 downto 0);
when "1100"|"1000"|"0100" => Mem_DQ_O <= Data2WrInt(31 downto 16);
when others => null;
end case;
else
Mem_DQ_O <= (others => '0');
end if;
end if;
end process ASSIGN_DATA;
Mem_DQ_T <= (others => '1') when RnwInt = '1' else (others => '0');
------------------------------------------------------------------------
-- Read data from the memory
------------------------------------------------------------------------
READ_DATA: process(clk_i)
begin
if rising_edge(clk_i) then
if RstInt = '1' then
DataRdInt <= (others => '0');
elsif State = Deassert then
case BeInt is
when "1111" =>
if TwoCycle = '1' then
-- Read lowest address with MSdata
DataRdInt(15 downto 0) <= Mem_DQ_I;
else
-- Read highest address with LSdata
DataRdInt(31 downto 16) <= Mem_DQ_I;
end if;
-- Perform data mirroring
when "0011"|"1100" =>
DataRdInt(15 downto 0) <= Mem_DQ_I;
DataRdInt(31 downto 16) <= Mem_DQ_I;
when "0100"|"0001" =>
DataRdInt(7 downto 0) <= Mem_DQ_I(7 downto 0);
DataRdInt(15 downto 8) <= Mem_DQ_I(7 downto 0);
DataRdInt(23 downto 16) <= Mem_DQ_I(7 downto 0);
DataRdInt(31 downto 24) <= Mem_DQ_I(7 downto 0);
when "1000"|"0010" =>
DataRdInt(7 downto 0) <= Mem_DQ_I(15 downto 8);
DataRdInt(15 downto 8) <= Mem_DQ_I(15 downto 8);
DataRdInt(23 downto 16) <= Mem_DQ_I(15 downto 8);
DataRdInt(31 downto 24) <= Mem_DQ_I(15 downto 8);
when others => null;
end case;
end if;
end if;
end process READ_DATA;
------------------------------------------------------------------------
-- Send data to AXI bus
------------------------------------------------------------------------
REGISTER_DREAD: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Ack then
data_o <= DataRdInt;
end if;
end if;
end process REGISTER_DREAD;
------------------------------------------------------------------------
-- Assign acknowledge signals
------------------------------------------------------------------------
REGISTER_ACK: process(clk_i)
begin
if rising_edge(clk_i) then
if State = Ack and TwoCycle = '0' then
if RnwInt = '1' then -- read
rd_ack_o <= '1';
wr_ack_o <= '0';
else -- write
rd_ack_o <= '0';
wr_ack_o <= '1';
end if;
else
rd_ack_o <= '0';
wr_ack_o <= '0';
end if;
end if;
end process REGISTER_ACK;
------------------------------------------------------------------------
-- Assign UB, LB (used in 8-bit write mode)
------------------------------------------------------------------------
ASSIGN_UB_LB: process(clk_i)
begin
if rising_edge(clk_i) then
if RnwInt = '0' then
if State = AssertOenWen or
State = Waitt or
State = Deassert then
case BeInt is
-- Disable lower byte when MSByte is written
when "1000"|"0010" =>
Mem_UB <= '0';
Mem_LB <= '1';
-- Disable upper byte when LSByte is written
when "0100"|"0001" =>
Mem_UB <= '1';
Mem_LB <= '0';
-- Enable both bytes in other modes
when others =>
Mem_UB <= '0';
Mem_LB <= '0';
end case;
end if;
else -- Enable both when reading
Mem_UB <= '0';
Mem_LB <= '0';
end if;
end if;
end process ASSIGN_UB_LB;
end Behavioral;
|
gpl-3.0
|
6578cbcff81b7cd4a6b8be272203cbc7
| 0.412536 | 4.933587 | false | false | false | false |
luebbers/reconos
|
demos/beat_tracker/hw/src/framework/importance.vhd
| 1 | 27,063 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- --
-- ////// ///////// /////// /////// --
-- // // // // // // --
-- // // // // // // --
-- ///// // // // /////// --
-- // // // // // --
-- // // // // // --
-- ////// // /////// // --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- --
-- -- --
-- !!! THIS IS PART OF THE HARDWARE FRAMEWORK !!! --
-- --
-- DO NOT CHANGE THIS ENTITY/FILE UNLESS YOU WANT TO CHANGE THE FRAMEWORK --
-- --
-- USERS OF THE FRAMEWORK SHALL ONLY MODIFY USER FUNCTIONS/PROCESSES, --
-- WHICH ARE ESPECIALLY MARKED (e.g by the prefix "uf_" in the filename) --
-- --
-- --
-- Author: Markus Happe --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity importance is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic--;
-- time base
--i_timeBase : in std_logic_vector( 0 to C_OSIF_DATA_WIDTH-1 )
);
end importance;
architecture Behavioral of importance is
component uf_likelihood is
Port( clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
init : in std_logic;
enable : in std_logic;
observation_loaded : in std_logic;
ref_data_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_address : in std_logic_vector(0 to C_BURST_AWIDTH-1);
observation_size : in integer;
finished : out std_logic;
likelihood_value : out integer
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral : architecture is "true";
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
constant C_MB_MEASUREMENT : std_logic_vector(0 to 31) := X"00000002";
-- states
type t_state is (initialize, read_particle_address,
read_number_of_particles, read_particle_size, read_block_size,
wait_one_cycle, read_observation_size, needed_bursts, needed_bursts_2,
needed_reads_1, needed_reads_2, read_observation_address,
read_ref_data_address, wait_for_message,
calculate_remaining_observations_1, calculate_remaining_observations_2,
calculate_remaining_observations_3, calculate_remaining_observations_4,
calculate_remaining_observations_5, calculate_remaining_observations_6,
calculate_remaining_observations_7, calculate_remaining_observations_8,
calculate_remaining_observations_9, calculate_remaining_observations_10,
calculate_remaining_observations_11, calculate_remaining_observations_12,
load_observation,
load_burst_decision, load_burst, load_read_decision,
load_read, load_read_wait, write_to_ram, wait_after_write,
wait_after_write_2, wait_after_write_3, load_last_burst,
load_observation_data_decision, load_observation_data_decision_2,
load_observation_data_decision_3, load_observation_data_decision_4,
load_observation_data_decision_5, --load_observation_data_decision_6,
--load_observation_data_decision_7,
likelihood, likelihood_done, write_likelihood,
send_message, send_measurement_1, send_measurement_2
);
-- current state
signal state : t_state := initialize;
-- particle array
signal particle_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal particle_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- observation array
signal observation_array_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal observation_array_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- reference data
signal reference_data_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- load address, either reference data address or an observation array address
signal load_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM address
signal local_ram_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
signal local_ram_start_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- local RAM data
signal ram_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- information struct containing array addresses and other information like observation size
signal information_struct : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- number of particles / observations (set by message box, default = 100)
signal N : integer := 10;
-- number of observations
signal remaining_observations : integer := 10;
-- number of needed bursts
signal number_of_bursts : integer := 0;
-- number of needed bursts to be remembered
signal number_of_bursts_remember : integer := 0;
-- size of a particle
signal particle_size : integer := 4;
-- size of a observation
signal observation_size : integer := 40;
-- temporary integer signals
signal temp : integer := 0;
signal temp2 : integer := 0;
signal temp3 : integer := 0;
signal temp4 : integer := 0;
signal temp5 : integer := 0;
signal offset : integer := 0;
-- start observation index
--signal start_observation_index : integer := 0;
-- number of reads
signal number_of_reads : integer := 0;
-- number of needed reads to be remembered
signal number_of_reads_remember : integer := 0;
-- set to '1', if after the first run the reference data + the first observation is loaded
signal second_run : std_logic := '0';
-- local ram address for interface
signal local_ram_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal local_ram_start_address_if : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- number of particles in a particle block
signal block_size : integer := 10;
-- message m, m stands for the m-th number of particle block
signal message : integer := 1;
-- message2 is message minus one
signal message2 : integer := 0;
-- number of observations, where importance has to be calculated (max = block size)
signal number_of_calculations : integer := 10;
-- offset for observation array
signal observation_offset : integer := 0;
-- time values for start, stop and the difference of both
signal time_start : integer := 0;
signal time_stop : integer := 0;
signal time_measurement : integer := 0;
-----------------------------------------------------------
-- NEEDED FOR USER ENTITY INSTANCE
-----------------------------------------------------------
-- for likelihood user process
-- init
signal init : std_logic := '1';
-- enable
signal enable : std_logic := '0';
-- start signal for the likelihood user process
signal observation_loaded : std_logic := '0';
-- size of one observation
signal observation_size_2 : integer := 0;
-- reference data address
signal ref_data_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- observation data address
signal observation_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- if the likelihood value is calculated, this signal is set to '1'
signal finished : std_logic := '0';
-- likelihood value
signal likelihood_value : integer;-- := 5;
-- for switch 1: corrected local ram address. the least bit is inverted,
-- because else the local ram will be used incorrect
signal o_RAMAddrLikelihood : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 1:corrected local ram address for this importance thread
signal o_RAMAddrImportance : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- for switch 2: Write enable, user process
signal o_RAMWELikelihood : std_logic := '0';
-- for switch 2: Write enable, importance
signal o_RAMWEImportance : std_logic := '0';
-- for switch 3: output ram data, user process
signal o_RAMDataLikelihood : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
-- for switch 3: output ram data, importance
signal o_RAMDataImportance : std_logic_vector(0 to C_BURST_DWIDTH-1) := (others => '0');
begin
-- entity of user process
user_process : uf_likelihood
port map (reset=>reset, clk=>clk, o_RAMAddr=>o_RAMAddrLikelihood, o_RAMData=>o_RAMDataLikelihood,
i_RAMData=>i_RAMData, o_RAMWE=>o_RAMWELikelihood, o_RAMClk=>o_RAMClk,
init=>init, enable=>enable, observation_loaded=>observation_loaded,
ref_data_address=>ref_data_address, observation_address=>observation_address,
observation_size=>observation_size_2, finished=>finished, likelihood_value=>likelihood_value);
-- switch 1: address, correction is needed to avoid wrong addressing
o_RAMAddr <= o_RAMAddrLikelihood(0 to C_BURST_AWIDTH-2) & not o_RAMAddrLikelihood(C_BURST_AWIDTH-1)
when enable = '1' else o_RAMAddrImportance(0 to C_BURST_AWIDTH-2) & not o_RAMAddrImportance(C_BURST_AWIDTH-1);
-- switch 2: write enable
o_RAMWE <= o_RAMWELikelihood when enable = '1' else o_RAMWEImportance;
-- switch 3: output ram data
o_RAMData <= o_RAMDataLikelihood when enable = '1' else o_RAMDataImportance;
observation_size_2 <= observation_size / 4;
-----------------------------------------------------------------------------
--
-- Reconos State Machine for Importance:
--
-- 1) Information are set (like particle array address and
-- particle and observation size)
--
--
-- 2) Waiting for Message m (Start of a Importance run)
-- Calculate likelihood values for particles of m-th particle block
-- i = 0
--
--
-- 3) Calculate if block size particles should be calculated
-- or less (iff last particle block)
--
--
-- 4) The Reference Histogram ist copied to the local ram
--
--
-- 5) If there is still a observation left (i < counter) then
-- go to step 6;
-- else
-- go to step 9;
-- end if
--
--
-- 6) The observation is copied into the local ram
--
--
-- 7) Start and run likelihood user process
-- i++;
--
--
-- 8) After likelihood user process is finished,
-- write back the weight to particle array
-- go to step 5;
--
--
-- 9) Send Message m (Stop of a Importance run)
-- Likelihood values for particles of m-th particle block calculated
--
------------------------------------------------------------------------------
state_proc : process(clk, reset)
-- done signal for Reconos methods
variable done : boolean;
-- success signal for Reconos method, which gets a message box
variable success : boolean;
-- signals for N, particle_size and observation size
variable N_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable particle_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable observation_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable message_var : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
state <= initialize;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
when initialize =>
--! init state, receive information struct
reconos_get_init_data_s (done, o_osif, i_osif, information_struct);
-- CHANGE BACK (1 of 6) !!!
--reconos_get_init_data_s (done, o_osif, i_osif, particle_array_start_address);
if done then
enable <= '0';
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
init <= '1';
observation_loaded <= '0';
state <= read_particle_address;
-- CHANGE BACK (2 of 6) !!!
--state <= needed_bursts;
end if;
when read_particle_address =>
--! read particle array address
reconos_read_s (done, o_osif, i_osif, information_struct, particle_array_start_address);
if done then
state <= read_number_of_particles;
end if;
when read_number_of_particles =>
--! read number of particles N
reconos_read (done, o_osif, i_osif, information_struct+4, N_var);
if done then
N <= TO_INTEGER(SIGNED(N_var));
state <= read_particle_size;
end if;
when read_particle_size =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+8, particle_size_var);
if done then
particle_size <= TO_INTEGER(SIGNED(particle_size_var));
state <= read_block_size;
end if;
when read_block_size =>
--! read particle size
reconos_read (done, o_osif, i_osif, information_struct+12, block_size_var);
if done then
block_size <= TO_INTEGER(SIGNED(block_size_var));
state <= wait_one_cycle;
end if;
when wait_one_cycle =>
--! wait one cycle
state <= read_observation_size;
when read_observation_size =>
--! read observation size
reconos_read (done, o_osif, i_osif, information_struct+16, observation_size_var);
if done then
observation_size <= TO_INTEGER(SIGNED(observation_size_var));
state <= needed_bursts;
end if;
when needed_bursts =>
--! calculate needed bursts
--number_of_bursts_remember <= observation_size / 128;
temp4 <= observation_size / 4;
state <= needed_bursts_2;
when needed_bursts_2 =>
--! calculate needed bursts
observation_address <= local_ram_address_if + temp4;
state <= needed_reads_1;
when needed_reads_1 =>
--! calculate number of reads (1 of 2)
--number_of_reads_remember <= observation_size mod 128;
-- changed (new) [2 lines]
number_of_reads_remember <= observation_size;
number_of_bursts_remember <= 0;
state <= needed_reads_2;
when needed_reads_2 =>
--! calculate number of reads (2 of 2)
--number_of_reads_remember <= number_of_reads_remember / 8;
number_of_reads_remember <= number_of_reads_remember / 4;
state <= read_observation_address;
when read_observation_address =>
--! read observation array address
reconos_read_s (done,o_osif,i_osif,information_struct+20,observation_array_start_address);
if done then
state <= read_ref_data_address;
end if;
-- CHANGE BACK (3 of 6) !!!
--observation_array_start_address <= X"10000000";
--state <= read_ref_data_address;
when read_ref_data_address =>
--! read reference data address
reconos_read_s (done, o_osif, i_osif, information_struct+24, reference_data_address);
if done then
state <= wait_for_message;
end if;
-- CHANGE BACK (4 of 6) !!!
--reference_data_address <= X"10000040";
--state <= wait_for_message;
when wait_for_message =>
--! wait for semaphore to start resampling
reconos_mbox_get(done, success, o_osif, i_osif, C_MB_START, message_var);
if done and success then
message <= TO_INTEGER(SIGNED(message_var));
-- init signals
local_ram_address <= (others => '0');
local_ram_address_if <= (others => '0');
observation_loaded <= '0';
enable <= '0';
init <= '1';
second_run <= '0';
--time_start <= TO_INTEGER(SIGNED(i_timebase));
--observation_array_start_address <= X"10000000"; -- TODO: ONLY FOR SIMULATION
--reference_data_address <= X"20000000"; -- TODO: ONLY FOR SIMULATION
--observation_address <= local_ram_start_address_if + 14 + 2; -- TODO: ONLY FOR SIMULATION
--observation_size <= 56; -- TODO: ONLY FOR SIMULATION
--block_size <= 2; -- TODO: ONLY FOR SIMULATION
--number_of_bursts_remember <= 0; -- TODO: ONLY FOR SIMULATION
--number_of_reads_remember <= 14; -- TODO: ONLY FOR SIMULATION
state <= calculate_remaining_observations_1;
--state <= send_message;
end if;
when calculate_remaining_observations_1 =>
--! calculates particle array address and number of particles to sample
message2 <= message-1;
temp <= 0;
state <= calculate_remaining_observations_2;
when calculate_remaining_observations_2 =>
--! wait
if (message2 > 0) then
temp <= temp + block_size;
state <= calculate_remaining_observations_3;
else
state <= calculate_remaining_observations_4;
end if;
when calculate_remaining_observations_3 =>
--! calculates particle array address and number of particles to sample
--temp <= message2 * block_size;
message2 <= message2 - 1;
state <= calculate_remaining_observations_2;
when calculate_remaining_observations_4 =>
--! wait
temp5 <= temp;
temp3 <= 0;
state <= calculate_remaining_observations_5;
when calculate_remaining_observations_5 =>
--! calculates particle array address and number of particles to sample
temp2 <= temp * particle_size;
state <= calculate_remaining_observations_6;
when calculate_remaining_observations_6 =>
--! wait
state <= calculate_remaining_observations_7;
when calculate_remaining_observations_7 =>
--! calculate offset
--temp3 <= temp * observation_size;
if (temp5 > 0) then
temp3 <= temp3 + observation_size;
state <= calculate_remaining_observations_8;
else
state <= calculate_remaining_observations_9;
end if;
when calculate_remaining_observations_8 =>
--! wait
temp5 <= temp5 - 1;
state <= calculate_remaining_observations_7;
when calculate_remaining_observations_9 =>
--! calculates particle array address and number of particles to sample
remaining_observations <= N - temp;
state <= calculate_remaining_observations_10;
when calculate_remaining_observations_10 =>
--! calculates particle array address and number of particles to sample
particle_array_address <= particle_array_start_address + temp2;
state <= calculate_remaining_observations_11;
when calculate_remaining_observations_11 =>
--! calculates particle array address and number of particles to sample
observation_array_address <= observation_array_start_address + temp3;
state <= calculate_remaining_observations_12;
when calculate_remaining_observations_12 =>
--! calculates particle array address and number of particles to sample
if (remaining_observations > block_size) then
remaining_observations <= block_size;
number_of_calculations <= block_size;
else
number_of_calculations <= remaining_observations;
end if;
state <= load_observation;
when load_observation =>
--! prepare to load an observation to local ram
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
load_address <= reference_data_address;
state <= load_burst_decision;
when load_burst_decision =>
--! decision if a burst is needed
if (number_of_bursts > 0) then
state <= load_burst;
number_of_bursts <= number_of_bursts - 1;
else
state <= load_read_decision;
end if;
when load_burst =>
--! load bursts of observation
reconos_read_burst(done, o_osif, i_osif, local_ram_address, load_address);
if done then
local_ram_address <= local_ram_address + 128;
load_address <= load_address + 128;
local_ram_address_if <= local_ram_address_if + 32;
state <= load_burst_decision;
end if;
when load_read_decision =>
--! decision if a read into local ram is needed
o_RAMWEImportance <= '0';
if (number_of_reads > 0) then
state <= load_read;
--state <= load_last_burst;
elsif (second_run = '1') then
state <= likelihood;
else
second_run <= '1';
state <= load_observation_data_decision;
end if;
when load_last_burst =>
--! load last burst
-- reconos_read_burst_l(done,o_osif,i_osif,local_ram_address,load_address,number_of_reads);
-- if done then
-- local_ram_address <= local_ram_address + (number_of_reads * 8);
-- load_address <= load_address + (number_of_reads * 8);
-- local_ram_address_if <= local_ram_address_if + (number_of_reads * 2);
-- number_of_reads <= 0;
state <= load_read_decision;
--end if;
when load_read =>
--! load reads of observation
reconos_read_s(done, o_osif, i_osif, load_address, ram_data);
if done then
load_address <= load_address + 4;
number_of_reads <= number_of_reads - 1;
state <= load_read_wait;
end if;
when load_read_wait =>
--! wait
state <= write_to_ram;
when write_to_ram =>
--! write value to ram
o_RAMWEImportance<= '1';
o_RAMAddrImportance <= local_ram_address_if;
o_RAMDataImportance <= ram_data;
local_ram_address_if <= local_ram_address_if + 1;
state <= wait_after_write;
when wait_after_write =>
-- wait
o_RAMWEImportance<= '0';
state <= wait_after_write_2;
when wait_after_write_2 =>
-- wait
state <= wait_after_write_3;
when wait_after_write_3 =>
-- wait
state <= load_read_decision;
when load_observation_data_decision =>
--! first step of calculation of observation address
observation_offset <= number_of_calculations - remaining_observations;
state <= load_observation_data_decision_2;
when load_observation_data_decision_2 =>
--! wait
state <= load_observation_data_decision_3;
when load_observation_data_decision_3 =>
--! decide, if there is another observation to be handled, else post semaphore
local_ram_address <= local_ram_start_address + observation_size;
local_ram_address_if <= observation_address;
number_of_bursts <= number_of_bursts_remember;
number_of_reads <= number_of_reads_remember;
offset <= observation_offset * observation_size ;
state <= load_observation_data_decision_4;
when load_observation_data_decision_4 =>
--! wait
state <= load_observation_data_decision_5;
when load_observation_data_decision_5 =>
--! decide, if there is another observation to be handled, else post semaphore
load_address <= observation_array_address + offset;
if (remaining_observations > 0) then
state <= load_burst_decision;
else
--time_stop <= TO_INTEGER(SIGNED(i_timeBase));
state <= send_message;
end if;
when likelihood =>
--! start and run likelihood user process
--init <= '0';
--enable <= '1';
observation_loaded <= '1';
state <= likelihood_done;
when likelihood_done =>
--! wait until the likelihood user process is finished
observation_loaded <= '0';
--if (finished = '1') then
enable <= '0';
init <= '1';
state <= write_likelihood;
remaining_observations <= remaining_observations - 1;
--end if;
when write_likelihood =>
--! write likelihood value into the particle array
reconos_write(done, o_osif, i_osif, particle_array_address,
STD_LOGIC_VECTOR(TO_SIGNED(likelihood_value, C_OSIF_DATA_WIDTH)));
if done and success then
particle_array_address <= particle_array_address + particle_size;
state <= load_observation_data_decision;
end if;
when send_message =>
--! post semaphore (importance is finished)
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE,
STD_LOGIC_VECTOR(TO_SIGNED(message, C_OSIF_DATA_WIDTH)));
if done and success then
enable <= '0';
init <= '1';
observation_loaded <= '0';
state <= send_measurement_1;
end if;
when send_measurement_1 =>
--! sends time measurement to message box
-- send only, if time start < time stop. Else ignore this measurement
--if (time_start < time_stop) then
--time_measurement <= time_stop - time_start;
--state <= send_measurement_2;
--else
state <= wait_for_message;
--end if;
-- when send_measurement_2 =>
-- --! sends time measurement to message box
-- -- send message
-- reconos_mbox_put(done, success, o_osif, i_osif, C_MB_MEASUREMENT,
-- STD_LOGIC_VECTOR(TO_SIGNED(time_measurement, C_OSIF_DATA_WIDTH)));
-- if (done and success) then
-- state <= wait_for_message;
-- end if;
when others =>
state <= wait_for_message;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
bdfa0cd45ffdf993290965238c433514
| 0.594428 | 3.66459 | false | false | false | false |
luebbers/reconos
|
core/pcores/cpu_osif_adapter_v1_04_a/hdl/vhdl/osif_cmd_decoder.vhd
| 1 | 11,785 |
--
-- \file osif_cmd_decoder.vhd
--
-- Decodes OSIF commands for the CPU-OSIF adapter
--
-- \author Robert Meiche <[email protected]>
-- \date 22.09.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity osif_cmd_decoder is
generic (
COMMANDREG_WIDTH : integer := 5;
DATAREG_WIDTH : integer := 32;
DONEREG_WIDTH : integer := 1
);
port (
clk : in std_logic;
reset : in std_logic;
--cpu2os registers
cpu2os_commandreg : in std_logic_vector(COMMANDREG_WIDTH-1 downto 0);
cpu2os_datareg : in std_logic_vector(DATAREG_WIDTH-1 downto 0);
cpu2os_addrreg : in std_logic_vector(DATAREG_WIDTH-1 downto 0);
cpu2os_donereg : in std_logic_vector(DONEREG_WIDTH-1 downto 0);
toCPU_newcommand : out std_logic;
toCPU_debugreg : out std_logic_vector(DATAREG_WIDTH-1 downto 0);
os2cpu_datareg : out std_logic_vector(DATAREG_WIDTH-1 downto 0);
cpu_boot_ready : out std_logic;
cpu_sw_reset : out std_logic;
--signal to osif
cpu2os_osif_cmd : out osif_task2os_t;
os2cpu_osif_cmd : in osif_os2task_t;
--debug signals
debug_idle_state : out std_logic;
debug_busy_state : out std_logic;
debug_reconos_ready : out std_logic
);
end osif_cmd_decoder;
architecture synth of osif_cmd_decoder is
function bool_to_logic(boolval : boolean) return std_logic is
begin
if boolval then
return '1';
else
return '0';
end if;
end;
--------------- state machine states
type SM_TYPE is (IDLE, BUSY, WAIT_FOR_DONEREG);
signal state : SM_TYPE;
--------------- help signals
signal to_osif_command : osif_task2os_t;
signal from_osif_command : osif_os2task_t;
--------------- data signals
signal init_data : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
begin
os2cpu_datareg <= init_data;
cpu2os_osif_cmd <= to_osif_command;
from_osif_command <= os2cpu_osif_cmd;
---------------------------- PROCESSES ---------------------------------------------
readCommand: process(clk, reset)
variable data : std_logic_vector(DATAREG_WIDTH-1 downto 0);
variable addr : std_logic_vector(DATAREG_WIDTH-1 downto 0);
variable command : std_logic_vector((COMMANDREG_WIDTH-1) downto 0);
variable done : boolean:= true;
variable success : boolean:= true;
variable reconos_state : reconos_state_enc_t;
begin
if reset = '1' then
reconos_reset(to_osif_command, from_osif_command);
toCPU_newcommand <= '1';
cpu_boot_ready <= '0';
cpu_sw_reset <= '0';
toCPU_debugreg <= (others => '0');
debug_idle_state <= '0';
debug_busy_state <= '0';
debug_reconos_ready <= '0';
state <= IDLE;
elsif rising_edge(clk) then
reconos_begin(to_osif_command, from_osif_command);
if reconos_ready(from_osif_command) then
debug_reconos_ready <= '1';
case state is
when IDLE =>
debug_idle_state <= '1';
debug_busy_state <= '0';
toCPU_debugreg <= X"dead0"& '0' & to_osif_command.error & to_osif_command.request &from_osif_command.blocking & from_osif_command.busy & from_osif_command.ack & bool_to_logic(done) & bool_to_logic(success) & "0001";
cpu_boot_ready <= '0';
cpu_sw_reset <= '0';
if cpu2os_donereg = "1" then
data := cpu2os_datareg;
command := cpu2os_commandreg;
addr:= cpu2os_addrreg;
toCPU_newcommand <= '0';
state <= BUSY;
-- test for direct commands without handshake(set donereg='1', wait until toCPU_newcommand, set donereg='0')
elsif cpu2os_commandreg = "00110" then
--BOOT_READY which indicates that the CPU has arrived the main
-- function. Now the cpu_boot_ready signal is set to signal this to the bram_logic
cpu_boot_ready <= '1';
state <= IDLE;
elsif cpu2os_commandreg = "00111" then
cpu_sw_reset <= '1';
state <= IDLE;
else
toCPU_newcommand <= '1';
state <= IDLE;
end if;
when BUSY =>
debug_idle_state <= '0';
debug_busy_state <= '1';
cpu_boot_ready <= '0';
cpu_sw_reset <= '0';
--check which command
case command(4 downto 0) is
when STD_LOGIC_VECTOR(TO_UNSIGNED(1, COMMANDREG_WIDTH)) =>
reconos_get_init_data_s (done, to_osif_command, from_osif_command, init_data);
when STD_LOGIC_VECTOR(TO_UNSIGNED(2, COMMANDREG_WIDTH)) =>
--reconos_write(done, to_osif_command, from_osif_command, addr, data);
reconos_mutex_release(to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(3, COMMANDREG_WIDTH)) =>
--reconos_read_s(done, to_osif_command, from_osif_command, addr, init_data);
reconos_mutex_trylock(done, success, to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(4, COMMANDREG_WIDTH)) =>
reconos_mutex_lock (done, success, to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(5, COMMANDREG_WIDTH)) =>
reconos_mutex_unlock (to_osif_command, from_osif_command, addr);
-- 6 is reserved for BOOT_READY
-- 7 is reserved for CPU_HWT softwarereset
when STD_LOGIC_VECTOR(TO_UNSIGNED(8, COMMANDREG_WIDTH)) =>
reconos_sem_post(to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(9, COMMANDREG_WIDTH)) =>
reconos_sem_wait(to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(10, COMMANDREG_WIDTH)) =>
reconos_cond_signal(to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(11, COMMANDREG_WIDTH)) =>
reconos_cond_broadcast(to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(12, COMMANDREG_WIDTH)) =>
reconos_cond_wait(done, success, to_osif_command, from_osif_command, addr);
when STD_LOGIC_VECTOR(TO_UNSIGNED(13, COMMANDREG_WIDTH)) =>
reconos_mbox_get_s(done, success, to_osif_command, from_osif_command, addr, init_data);
when STD_LOGIC_VECTOR(TO_UNSIGNED(14, COMMANDREG_WIDTH)) =>
reconos_mbox_put(done, success, to_osif_command, from_osif_command, addr, data);
when STD_LOGIC_VECTOR(TO_UNSIGNED(15, COMMANDREG_WIDTH)) =>
reconos_mbox_tryget_s(done, success, to_osif_command, from_osif_command, addr, init_data);
when STD_LOGIC_VECTOR(TO_UNSIGNED(16, COMMANDREG_WIDTH)) =>
reconos_mbox_tryput(done, success, to_osif_command, from_osif_command, addr, data);
when STD_LOGIC_VECTOR(TO_UNSIGNED(17, COMMANDREG_WIDTH)) =>
reconos_thread_resume(done, success, to_osif_command, from_osif_command, reconos_state);
when STD_LOGIC_VECTOR(TO_UNSIGNED(18, COMMANDREG_WIDTH)) =>
reconos_thread_exit(to_osif_command, from_osif_command, data);
when STD_LOGIC_VECTOR(TO_UNSIGNED(19, COMMANDREG_WIDTH)) =>
reconos_thread_delay(to_osif_command, from_osif_command, data);
when STD_LOGIC_VECTOR(TO_UNSIGNED(20, COMMANDREG_WIDTH)) =>
reconos_thread_yield(to_osif_command, from_osif_command, data);
when others => NULL;
end case; --command
if done and success then
toCPU_debugreg <= X"dead0"& '0' & to_osif_command.error & to_osif_command.request &from_osif_command.blocking & from_osif_command.busy & from_osif_command.ack& bool_to_logic(done) & bool_to_logic(success) & "0011";
state <= WAIT_FOR_DONEREG;
else
toCPU_debugreg <= X"dead0"& '0' & to_osif_command.error & to_osif_command.request &from_osif_command.blocking & from_osif_command.busy & from_osif_command.ack & bool_to_logic(done) & bool_to_logic(success) & "0100";
toCPU_newcommand <= '0';
state <= BUSY;
end if;
--CPU reads the toCPU_newcommand and then sets the donereg to '0'
--After that the statemachine goes to IDLE state to be ready for
--new commands
when WAIT_FOR_DONEREG =>
cpu_boot_ready <= '0';
cpu_sw_reset <= '0';
debug_idle_state <= '0';
debug_busy_state <= '0';
toCPU_debugreg <= X"dead0"& '0' & to_osif_command.error & to_osif_command.request &from_osif_command.blocking & from_osif_command.busy & from_osif_command.ack & bool_to_logic(done) & bool_to_logic(success) & "1000";
toCPU_newcommand <= '1';
if cpu2os_donereg = "0" then
state <= IDLE;
else
state <= WAIT_FOR_DONEREG;
end if;
when others =>
--null;
toCPU_debugreg <= X"deadffff";
end case; --state
else
debug_reconos_ready <= '0';
end if; --reconos_ready
end if; --reset or rising_edge
end process;
end synth;
|
gpl-3.0
|
f6442675361fe52f1ea66bb09c5b14d1
| 0.523971 | 4.106272 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/xwb_register_link.vhd
| 1 | 2,416 |
-------------------------------------------------------------------------------
-- Title : An Wishbone delay buffer
-- Project : General Cores Library (gencores)
-------------------------------------------------------------------------------
-- File : xwb_crossbar.vhd
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-12-16
-- Last update: 2013-12-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- Adds a register between two wishbone interfaces.
-- Useful to improve timing closure when placed between crossbars.
-- Be warned: it reduces the available bandwidth by a half.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 GSI / Wesley W. Terpstra
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-12-16 1.0 wterpstra V1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity xwb_register_link is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in;
master_o : out t_wishbone_master_out);
end xwb_register_link;
architecture rtl of xwb_register_link is
signal r_slave : t_wishbone_slave_out;
signal r_master : t_wishbone_master_out;
begin
slave_o <= r_slave;
master_o <= r_master;
main : process(clk_sys_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_slave <= cc_dummy_slave_out;
r_master <= cc_dummy_master_out;
r_slave.stall <= '0';
elsif rising_edge(clk_sys_i) then
-- no flow control on ack/err
r_slave <= master_i;
-- either we are accepting data (stb=0) or pushing data (stb=1)
if r_master.stb = '0' then
r_master <= slave_i;
r_master.stb <= slave_i.cyc and slave_i.stb;
r_slave.stall <= slave_i.cyc and slave_i.stb;
else
r_master.stb <= r_master.stb and master_i.stall;
r_slave.stall <= r_master.stb and master_i.stall;
end if;
end if;
end process;
end rtl;
|
lgpl-3.0
|
d15a028e640366c3d77f2053678f3076
| 0.493791 | 3.816746 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/AccelDisplay.vhd
| 1 | 8,023 |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz, Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 17:20:44 03/19/2013
-- Design Name:
-- Module Name: AccelDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AccelDisplay is
Generic
(
X_XY_WIDTH : natural := 511; -- Width of the Accelerometer frame X-Y region
X_MAG_WIDTH : natural := 50; -- Width of the Accelerometer frame Magnitude region
Y_HEIGHT : natural := 511; -- Height of the Accelerometer frame
X_START : natural := 385; -- Accelerometer frame X-Y region starting horizontal location
Y_START : natural := 80; -- Accelerometer frame starting vertical location
BG_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"FFF"; -- Background color - white
ACTIVE_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"0F0"; -- Green when inside the threshold box
WARNING_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"F00" -- Red when outside the threshold box
);
Port
(
CLK_I : IN std_logic;
H_COUNT_I : IN std_logic_vector(11 downto 0);
V_COUNT_I : IN std_logic_vector(11 downto 0);
ACCEL_X_I : IN std_logic_vector(8 downto 0); -- X acceleration input data
ACCEL_Y_I : IN std_logic_vector(8 downto 0); -- Y acceleration input data
ACCEL_MAG_I : IN std_logic_vector(8 downto 0); -- Acceleration magnitude input data
ACCEL_RADIUS : IN STD_LOGIC_VECTOR (11 downto 0); -- Size of the box moving according to acceleration data
LEVEL_THRESH : IN STD_LOGIC_VECTOR (11 downto 0); -- Size of the threshold box
-- Accelerometer Red, Green and Blue signals
RED_O : OUT std_logic_vector(3 downto 0);
BLUE_O : OUT std_logic_vector(3 downto 0);
GREEN_O : OUT std_logic_vector(3 downto 0)
);
end AccelDisplay;
architecture Behavioral of AccelDisplay is
--dependent constants
constant X_WIDTH: natural := X_XY_WIDTH + X_MAG_WIDTH; -- width of the entire Accelerometer frame
-- Horizontal midpoint location of the Accelerometer frame X-Y region
constant FR_XY_H_MID : natural := natural(round(real(X_XY_WIDTH/2)));
-- Vertical midpoint location of the Accelerometer X-Y region
constant FR_XY_V_MID : natural := natural(round(real(Y_HEIGHT/2)));
-- Starting horizontal position of the Magnitude column
constant X_MAG_START : natural := X_START + X_XY_WIDTH;
-- End horizontal position of the Magnitude column
constant X_MAG_END : integer := (X_START + X_WIDTH) - 1;
-- End vertical position of the Accelerometer frame
constant Y_END : integer := (Y_HEIGHT + Y_START) - 1;
-- Moving box limits
signal MOVING_BOX_LEFT : natural;
signal MOVING_BOX_RIGHT : natural;
signal MOVING_BOX_TOP : natural;
signal MOVING_BOX_BOTTOM : natural;
--Threshold box limits
signal THRESHOLD_BOX_LEFT : natural;
signal THRESHOLD_BOX_RIGHT : natural;
signal THRESHOLD_BOX_TOP : natural;
signal THRESHOLD_BOX_BOTTOM : natural;
-- Signals showing when to send moving box or magnitude level
-- or threshold box data
signal draw_moving_box : std_logic;
signal draw_magnitude_level : std_logic;
signal draw_threshold_box : std_logic;
-- Moving box color value
signal level_color : std_logic_vector(11 downto 0);
-- Magnitude column color value
signal magnitude_color : std_logic_vector(11 downto 0);
-- Output RGB signal, 4 bits Red, 4 bits Green and 4 bits Blue
signal color_out_reg : std_logic_vector(11 downto 0) := (others=>'0');
begin
-- Set the limit signals
-- Moving box limits
MOVING_BOX_LEFT <= X_START - conv_integer(ACCEL_RADIUS) - 1;
MOVING_BOX_RIGHT <= X_START + conv_integer(ACCEL_RADIUS) + 1;
MOVING_BOX_TOP <= Y_START - conv_integer(ACCEL_RADIUS) - 1;
MOVING_BOX_BOTTOM <= Y_START + conv_integer(ACCEL_RADIUS) + 1;
--Threshold box limits
THRESHOLD_BOX_LEFT <= FR_XY_H_MID + X_START - conv_integer(LEVEL_THRESH) - 1;
THRESHOLD_BOX_RIGHT <= FR_XY_H_MID + X_START + conv_integer(LEVEL_THRESH) + 1;
THRESHOLD_BOX_TOP <= FR_XY_V_MID + Y_START - conv_integer(LEVEL_THRESH) - 1;
THRESHOLD_BOX_BOTTOM <= FR_XY_V_MID + Y_START + conv_integer(LEVEL_THRESH) + 1;
-- Create the moving box signal
-- Note that the accelerometer on the Nexys4 board is turned 90 degrees,
-- therefore such as X axis is perpendicular to the board text,
-- so the X axis data will be displayed on the vertical axis
-- Using comparison on 12 bits
draw_moving_box <= '1' when H_COUNT_I > (("000" & ACCEL_Y_I) + MOVING_BOX_LEFT)
and H_COUNT_I < (("000" & ACCEL_Y_I) + MOVING_BOX_RIGHT)
and V_COUNT_I > (("000" & ACCEL_X_I) + MOVING_BOX_TOP)
and V_COUNT_I < (("000" & ACCEL_X_I) + MOVING_BOX_BOTTOM)
else '0';
--Create the magnitude level signal
draw_magnitude_level <= '1' when H_COUNT_I >= (X_MAG_START - 1)
and H_COUNT_I <= X_MAG_END
and (V_COUNT_I + ("000" & ACCEL_MAG_I)) >= Y_END
and V_COUNT_I <= Y_END
else '0';
--Create the threshold box signal
draw_threshold_box <= '1' when ((H_COUNT_I = THRESHOLD_BOX_LEFT or H_COUNT_I = THRESHOLD_BOX_RIGHT) -- Left and Right vertical lines
and V_COUNT_I >= THRESHOLD_BOX_TOP
and V_COUNT_I <= THRESHOLD_BOX_BOTTOM )
or
((V_COUNT_I = THRESHOLD_BOX_TOP or V_COUNT_I = THRESHOLD_BOX_BOTTOM) -- Top and Bottom Horizontal Lines
and H_COUNT_I >= THRESHOLD_BOX_LEFT
and H_COUNT_I <= THRESHOLD_BOX_RIGHT)
else '0';
-- The moving box is green when inside the threshold box and red when outside
level_color <= ACTIVE_COLOR when ACCEL_Y_I >= (FR_XY_V_MID - LEVEL_THRESH) -- Upper boundary
and ACCEL_Y_I <= (FR_XY_V_MID + LEVEL_THRESH) -- Lower boundary
and ACCEL_X_I >= (FR_XY_H_MID - LEVEL_THRESH) -- Left boundary
and ACCEL_X_I <= (FR_XY_H_MID + LEVEL_THRESH) -- Right boundary
else WARNING_COLOR;
magnitude_color <= ACTIVE_COLOR;
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (draw_threshold_box = '1') then -- Threshold box is black
color_out_reg <= x"000";
elsif (draw_moving_box = '1') then -- Moving box is either green or red
color_out_reg <= level_color;
elsif (draw_magnitude_level = '1') then -- Magnitude color will be the same as the active color
color_out_reg <= magnitude_color;
else
color_out_reg <= BG_COLOR;
end if;
end if;
end process;
-- Assign Outputs
RED_O <= color_out_reg(11 downto 8);
GREEN_O <= color_out_reg(7 downto 4);
BLUE_O <= color_out_reg(3 downto 0);
end Behavioral;
|
gpl-3.0
|
ddccd2b8f7544e67b6c1215ef9885b09
| 0.584569 | 3.835086 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/9.2/ml403/ml403_light_pr/pcores/IcapCTRL_v1_00_d/hdl/vhdl/icapCTRL_mod.vhd
| 1 | 12,172 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:05 07/20/2006
-- Design Name:
-- Module Name: icapCTRL - icapCTRL_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity icapCTRL is
generic (
C_FAMILY : string := "virtex2P";
C_ICAP_DWIDTH : integer:= 8;
C_BURST_SIZE : natural := 32; -- Number of DWords
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := b"10_0000_0000"; --DCR_BaseAddr
C_DCR_HIGHADDR : std_logic_vector(9 downto 0) := b"00_0000_0011"; --DCR_HighAddr, not used
C_COUNT_ADDR : std_logic_vector(31 downto 0) := X"00000010"
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic_vector(1 downto 0);
M_rdAddr_o : out std_logic_vector(31 downto 0);
M_rdReq_o : out std_logic;
M_rdNum_o : out std_logic_vector(4 downto 0);
M_rdAccept_i : in std_logic;
M_rdData_i : in std_logic_vector(63 downto 0);
M_rdAck_i : in std_logic;
M_rdComp_i : in std_logic;
M_wrAddr_o : out std_logic_vector(31 downto 0);
M_wrReq_o : out std_logic;
M_wrNum_o : out std_logic_vector(4 downto 0);
M_wrAccept_i : in std_logic;
M_wrData_o : out std_logic_vector(63 downto 0);
M_wrRdy_i : in std_logic;
M_wrAck_i : in std_logic;
M_wrComp_i : in std_logic;
--- Interrupt
done_int : out std_logic;
--- DCR signals
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
-- chipscope output
BUSY : out std_ulogic;
O : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
CE : out std_ulogic;
I : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
WRITE : out std_ulogic;
DCR_ABus_o : out std_logic_vector(9 downto 0);
DCR_Write_o : out std_logic;
DCR_Din_o : out std_logic_vector(31 downto 0)
);
end icapCTRL;
architecture icapCTRL_rtl of icapCTRL is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then
return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
component ICAP_VIRTEX2
port (
BUSY : out std_ulogic;
O : out std_logic_vector(7 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(7 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX4
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component icapFIFO
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end component;
component dcr_if is
generic (
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := B"00_0000_0000";
C_ON_INIT : std_logic := '0'
);
port (
clk : in std_logic;
rst : in std_logic;
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
ctrl_reg : out std_logic_vector(31 downto 0)
);
end component;
type state_type is (IDLE, INIT, ACTIVE, BURSTING, WRITE_COUNT, DONE);
signal state : state_type;
--signal addr : std_logic_vector(14 downto 0);
--signal addr : std_logic_vector(13 downto 0);
signal addr : std_logic_vector(18-(log2(C_BURST_SIZE)) downto 0);
signal addr_tail : std_logic_vector(2+(log2(C_BURST_SIZE)) downto 0);
signal base_addr : std_logic_vector(31 downto 22);
signal base_lngth : std_logic_vector(15 downto 0);
signal icap_busy : std_logic;
signal icap_dout : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din_r : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_en_l : std_logic;
signal icap_rnw : std_logic;
signal fifo_rEn : std_logic;
signal fifo_wEn : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal count : std_logic_vector(31 downto 0);
signal debounce : std_logic_vector(1 downto 0);
signal dcr_reg : std_logic_vector(31 downto 0);
signal dcr_start_w : std_logic;
signal dcr_start_w_n : std_logic;
signal dcr_start_r : std_logic;
signal dcr_addr : std_logic_vector(31 downto 0);
signal ctrl_reg : std_logic_vector(31 downto 0);
signal Sl_dcrAck_sig : std_logic;
signal done_int_i : std_logic;
begin
addr_tail <= (others => '0');
-- if virtex2P or Virtex2 use ICAP_Virtex2 and invert input bits
V2_GEN : if (C_FAMILY = "virtex2p" or C_FAMILY = "virtex2") generate
V2_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_0 : ICAP_VIRTEX2
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
-- WARNING!!!
-- The ICAP's data signals are reversed in V2P!
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V2_GEN_8;
end generate V2_GEN;
V4_GEN : if (C_FAMILY = "virtex4") generate
V4_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_1 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X8") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V4_GEN_8;
V4_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
ICAP_2 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X32") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
icap_din_r <= icap_din;
end generate V4_GEN_32;
end generate V4_GEN;
-- dcr interface instantiation
dcr_control: dcr_if
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR)
port map (
clk => clk,
rst => reset,
DCR_ABus => DCR_ABus,
DCR_Sl_DBus => DCR_Sl_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
Sl_dcrAck => Sl_dcrAck_sig,
Sl_dcrDBus => Sl_dcrDBus,
ctrl_reg => ctrl_reg
);
icapFIFO_0 : icapFIFO
generic map (
C_FIFO_DEPTH => 64,
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => C_ICAP_DWIDTH
)
port map (
clk => clk,
reset => reset,
wEn_i => fifo_wEn,
wData_i => M_rdData_i,
rEn_i => fifo_rEn,
rData_o => icap_din,
full_o => fifo_full,
empty_o => fifo_empty
);
-- fifo_empty is active high. If Fifo is not empty (fifo_empty = '0') rnw and ce gow low!
icap_rnw <= fifo_empty;
icap_en_l <= fifo_empty;
fifo_rEn <= not icap_busy;
dcr_start_w <= Sl_dcrAck_sig and DCR_Write;
Sl_dcrAck <= Sl_dcrAck_sig;
-- Make DCR signals available to chipscope at output
DCR_ABus_o <= DCR_ABus;
DCR_Write_o <= DCR_Write;
DCR_Din_o <= ctrl_reg;
-- Make icap signals available to chipscope at output
BUSY <= icap_busy; -- Busy output
O <= icap_dout; -- 8-bit data output
CE <= icap_en_l; -- Clock enable input
I <= icap_din; -- 8-bit data input
WRITE <= icap_rnw; -- Write input
fifo_wEn <= M_rdAck_i when(state=BURSTING) else '0';
-- Generate the read address
--M_rdAddr_o <= base_addr & addr & b"0000000";
--M_rdAddr_o <= base_addr & addr & b"00000000";
M_rdAddr_o <= base_addr & addr & addr_tail;
done_int <= done_int_i;
-- delay start signal by one cycle
process(clk) begin
if(clk='1' and clk'event) then
dcr_start_w_n <= dcr_start_w;
end if;
end process;
process(state, fifo_full, fifo_empty) begin
-- don't request data
M_rdReq_o <= '0';
M_rdNum_o <= "10000";
M_wrReq_o <= '0';
if(state=ACTIVE) then
M_rdReq_o <= not fifo_full;
elsif(state=WRITE_COUNT) then
M_wrReq_o <= fifo_empty;
end if;
end process;
M_wrAddr_o <= C_COUNT_ADDR;
M_wrNum_o <= "00001";
M_wrData_o(63 downto 32) <= (others=>'0');
M_wrData_o(31 downto 0) <= count;
process(clk) begin
if(clk='1' and clk'event) then
if(state=IDLE) then
count <= (others=>'0');
else
if(fifo_empty='0') then -- if Fifo is not empty increase counter
count <= count+1;
end if;
end if;
end if;
end process;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
state <= IDLE;
addr <= (others=>'0');
base_addr <= (others=>'0');
base_lngth <= (others=>'0');
dcr_reg <= (others => '0');
done_int_i <= '0';
else
done_int_i <= '0';
case(state) is
when IDLE =>
addr <= (others=>'0');
-- initialize base addr and base_lngth with the data from DCR bus once!
base_addr <= ctrl_reg(31 downto 22);
base_lngth <= ctrl_reg(15 downto 0);
if(dcr_start_w_n='1') then
state <= ACTIVE;
end if;
when ACTIVE =>
if(M_rdAccept_i='1') then
addr <= addr + 1;
--dcr_reg(21 downto 7) <= dcr_reg(21 downto 7) + 1;
state <= BURSTING;
end if;
when BURSTING =>
if(M_rdComp_i='1') then
if(addr=base_lngth) then
state <= WRITE_COUNT;
else
state <= ACTIVE;
end if;
end if;
when WRITE_COUNT =>
if(M_wrAccept_i='1') then
state <= DONE;
end if;
when DONE =>
--if(fifo_empty = '1') then
done_int_i <= '1';
state <= IDLE;
--end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
end icapCTRL_rtl;
|
gpl-3.0
|
8d9d62b7f38fd9a9ac8660abc7adff9d
| 0.536477 | 3.146033 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/FiFo/FiFo_sim_netlist.vhdl
| 1 | 151,764 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Wed Apr 13 17:20:50 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FiFo/FiFo_sim_netlist.vhdl
-- Design : FiFo
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end FiFo_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of FiFo_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13 downto 11) => B"000",
ADDRARDADDR(10 downto 5) => \gc0.count_d1_reg[5]\(5 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13 downto 11) => B"000",
ADDRBWRADDR(10 downto 5) => Q(5 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CLKARDCLK => clk,
CLKBWRCLK => clk,
DIADI(15 downto 10) => B"000000",
DIADI(9 downto 8) => din(3 downto 2),
DIADI(7 downto 2) => B"000000",
DIADI(1 downto 0) => din(1 downto 0),
DIBDI(15 downto 10) => B"000000",
DIBDI(9 downto 8) => din(7 downto 6),
DIBDI(7 downto 2) => B"000000",
DIBDI(1 downto 0) => din(5 downto 4),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_1\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_2\,
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_3\,
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_4\,
DOADO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_5\,
DOADO(9 downto 8) => dout(3 downto 2),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_9\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_10\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_11\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_12\,
DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_13\,
DOADO(1 downto 0) => dout(1 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_20\,
DOBDO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_21\,
DOBDO(9 downto 8) => dout(7 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_28\,
DOBDO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_29\,
DOBDO(1 downto 0) => dout(5 downto 4),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => E(0),
ENBWREN => ram_full_fb_i_reg(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3) => ram_full_fb_i_reg(0),
WEBWE(2) => ram_full_fb_i_reg(0),
WEBWE(1) => ram_full_fb_i_reg(0),
WEBWE(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_rd_bin_cntr is
port (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_comb : out STD_LOGIC;
\gc0.count_d1_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_2_out : in STD_LOGIC;
\gc0.count_reg[0]_0\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_rd_bin_cntr : entity is "rd_bin_cntr";
end FiFo_rd_bin_cntr;
architecture STRUCTURE of FiFo_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gc0.count_d1_reg[5]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_3_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_5_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal ram_full_i_i_7_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair0";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5 downto 0);
\gc0.count_d1_reg[5]_0\(5 downto 0) <= \^gc0.count_d1_reg[5]_0\(5 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gc0.count_d1_reg[5]_0\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gc0.count_d1_reg[5]_0\(0),
I1 => \^gc0.count_d1_reg[5]_0\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gc0.count_d1_reg[5]_0\(0),
I1 => \^gc0.count_d1_reg[5]_0\(1),
I2 => \^gc0.count_d1_reg[5]_0\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^gc0.count_d1_reg[5]_0\(3),
I1 => \^gc0.count_d1_reg[5]_0\(0),
I2 => \^gc0.count_d1_reg[5]_0\(1),
I3 => \^gc0.count_d1_reg[5]_0\(2),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^gc0.count_d1_reg[5]_0\(4),
I1 => \^gc0.count_d1_reg[5]_0\(2),
I2 => \^gc0.count_d1_reg[5]_0\(1),
I3 => \^gc0.count_d1_reg[5]_0\(0),
I4 => \^gc0.count_d1_reg[5]_0\(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^gc0.count_d1_reg[5]_0\(5),
I1 => \^gc0.count_d1_reg[5]_0\(3),
I2 => \^gc0.count_d1_reg[5]_0\(0),
I3 => \^gc0.count_d1_reg[5]_0\(1),
I4 => \^gc0.count_d1_reg[5]_0\(2),
I5 => \^gc0.count_d1_reg[5]_0\(4),
O => plusOp(5)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gc0.count_d1_reg[5]_0\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
R => '0'
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gc0.count_d1_reg[5]_0\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
R => '0'
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gc0.count_d1_reg[5]_0\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
R => '0'
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gc0.count_d1_reg[5]_0\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
R => '0'
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gc0.count_d1_reg[5]_0\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
R => '0'
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gc0.count_d1_reg[5]_0\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
R => '0'
);
\gc0.count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => plusOp(0),
Q => \^gc0.count_d1_reg[5]_0\(0),
R => '0'
);
\gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(1),
Q => \^gc0.count_d1_reg[5]_0\(1),
R => '0'
);
\gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(2),
Q => \^gc0.count_d1_reg[5]_0\(2),
R => '0'
);
\gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(3),
Q => \^gc0.count_d1_reg[5]_0\(3),
R => '0'
);
\gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(4),
Q => \^gc0.count_d1_reg[5]_0\(4),
R => '0'
);
\gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => plusOp(5),
Q => \^gc0.count_d1_reg[5]_0\(5),
R => '0'
);
ram_empty_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"4F444F4F"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => p_2_out,
I2 => \gc0.count_reg[0]_0\,
I3 => p_1_out,
I4 => wr_en,
O => ram_empty_fb_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"4F444F4F"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => p_1_out,
I2 => ram_full_i_i_3_n_0,
I3 => p_2_out,
I4 => rd_en,
O => ram_full_comb
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000009009"
)
port map (
I0 => \gcc0.gc0.count_d1_reg[5]\(4),
I1 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I2 => \gcc0.gc0.count_d1_reg[5]\(5),
I3 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I4 => ram_full_i_i_4_n_0,
I5 => ram_full_i_i_5_n_0,
O => ram_full_i_i_2_n_0
);
ram_full_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000BFFB0000FFFF"
)
port map (
I0 => ram_full_i_i_6_n_0,
I1 => ram_full_i_i_7_n_0,
I2 => Q(0),
I3 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I4 => p_1_out,
I5 => wr_en,
O => ram_full_i_i_3_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => \gcc0.gc0.count_d1_reg[5]\(1),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I3 => \gcc0.gc0.count_d1_reg[5]\(0),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => \gcc0.gc0.count_d1_reg[5]\(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I3 => \gcc0.gc0.count_d1_reg[5]\(2),
O => ram_full_i_i_5_n_0
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => Q(5),
I2 => Q(2),
I3 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I4 => Q(1),
I5 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
O => ram_full_i_i_6_n_0
);
ram_full_i_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => Q(3),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I3 => Q(4),
O => ram_full_i_i_7_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_rd_status_flags_ss is
port (
\gc0.count_d1_reg[5]\ : out STD_LOGIC;
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg_0 : in STD_LOGIC;
clk : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_rd_status_flags_ss : entity is "rd_status_flags_ss";
end FiFo_rd_status_flags_ss;
architecture STRUCTURE of FiFo_rd_status_flags_ss is
signal \^gc0.count_d1_reg[5]\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\gc0.count_d1_reg[5]\ <= \^gc0.count_d1_reg[5]\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^gc0.count_d1_reg[5]\,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
Q => \^gc0.count_d1_reg[5]\,
R => '0'
);
ram_empty_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => ram_empty_fb_i_reg_0,
Q => empty,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_reset_blk_ramfifo is
port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end FiFo_reset_blk_ramfifo;
architecture STRUCTURE of FiFo_reset_blk_ramfifo is
signal inverted_reset : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
begin
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => inverted_reset,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => inverted_reset,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => inverted_reset
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_wr_bin_cntr is
port (
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gcc0.gc0.count_d1_reg[5]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gc0.count_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
p_2_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_wr_bin_cntr : entity is "wr_bin_cntr";
end FiFo_wr_bin_cntr;
architecture STRUCTURE of FiFo_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^gcc0.gc0.count_d1_reg[5]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gcc0.gc0.count[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gcc0.gc0.count[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gcc0.gc0.count[4]_i_1\ : label is "soft_lutpair2";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\gcc0.gc0.count_d1_reg[5]_0\(5 downto 0) <= \^gcc0.gc0.count_d1_reg[5]_0\(5 downto 0);
\gcc0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gcc0.gc0.count_d1_reg[5]_0\(0),
O => \plusOp__0\(0)
);
\gcc0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gcc0.gc0.count_d1_reg[5]_0\(0),
I1 => \^gcc0.gc0.count_d1_reg[5]_0\(1),
O => \plusOp__0\(1)
);
\gcc0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^gcc0.gc0.count_d1_reg[5]_0\(0),
I1 => \^gcc0.gc0.count_d1_reg[5]_0\(1),
I2 => \^gcc0.gc0.count_d1_reg[5]_0\(2),
O => \plusOp__0\(2)
);
\gcc0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^gcc0.gc0.count_d1_reg[5]_0\(3),
I1 => \^gcc0.gc0.count_d1_reg[5]_0\(0),
I2 => \^gcc0.gc0.count_d1_reg[5]_0\(1),
I3 => \^gcc0.gc0.count_d1_reg[5]_0\(2),
O => \plusOp__0\(3)
);
\gcc0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^gcc0.gc0.count_d1_reg[5]_0\(4),
I1 => \^gcc0.gc0.count_d1_reg[5]_0\(2),
I2 => \^gcc0.gc0.count_d1_reg[5]_0\(1),
I3 => \^gcc0.gc0.count_d1_reg[5]_0\(0),
I4 => \^gcc0.gc0.count_d1_reg[5]_0\(3),
O => \plusOp__0\(4)
);
\gcc0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^gcc0.gc0.count_d1_reg[5]_0\(5),
I1 => \^gcc0.gc0.count_d1_reg[5]_0\(3),
I2 => \^gcc0.gc0.count_d1_reg[5]_0\(0),
I3 => \^gcc0.gc0.count_d1_reg[5]_0\(1),
I4 => \^gcc0.gc0.count_d1_reg[5]_0\(2),
I5 => \^gcc0.gc0.count_d1_reg[5]_0\(4),
O => \plusOp__0\(5)
);
\gcc0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gcc0.gc0.count_d1_reg[5]_0\(0),
Q => \^q\(0),
R => '0'
);
\gcc0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gcc0.gc0.count_d1_reg[5]_0\(1),
Q => \^q\(1),
R => '0'
);
\gcc0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gcc0.gc0.count_d1_reg[5]_0\(2),
Q => \^q\(2),
R => '0'
);
\gcc0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gcc0.gc0.count_d1_reg[5]_0\(3),
Q => \^q\(3),
R => '0'
);
\gcc0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gcc0.gc0.count_d1_reg[5]_0\(4),
Q => \^q\(4),
R => '0'
);
\gcc0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \^gcc0.gc0.count_d1_reg[5]_0\(5),
Q => \^q\(5),
R => '0'
);
\gcc0.gc0.count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(0),
Q => \^gcc0.gc0.count_d1_reg[5]_0\(0),
R => '0'
);
\gcc0.gc0.count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(1),
Q => \^gcc0.gc0.count_d1_reg[5]_0\(1),
R => '0'
);
\gcc0.gc0.count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(2),
Q => \^gcc0.gc0.count_d1_reg[5]_0\(2),
R => '0'
);
\gcc0.gc0.count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(3),
Q => \^gcc0.gc0.count_d1_reg[5]_0\(3),
R => '0'
);
\gcc0.gc0.count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(4),
Q => \^gcc0.gc0.count_d1_reg[5]_0\(4),
R => '0'
);
\gcc0.gc0.count_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \plusOp__0\(5),
Q => \^gcc0.gc0.count_d1_reg[5]_0\(5),
R => '0'
);
ram_empty_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF7DFF"
)
port map (
I0 => ram_empty_i_i_3_n_0,
I1 => \gc0.count_reg[5]\(0),
I2 => \^q\(0),
I3 => rd_en,
I4 => ram_empty_i_i_4_n_0,
I5 => p_2_out,
O => ram_empty_fb_i_reg
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^q\(5),
I1 => \gc0.count_reg[5]\(5),
I2 => \^q\(4),
I3 => \gc0.count_reg[5]\(4),
O => ram_empty_i_i_3_n_0
);
ram_empty_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^q\(3),
I1 => \gc0.count_reg[5]\(3),
I2 => \gc0.count_reg[5]\(2),
I3 => \^q\(2),
I4 => \gc0.count_reg[5]\(1),
I5 => \^q\(1),
O => ram_empty_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_wr_status_flags_ss is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_wr_status_flags_ss : entity is "wr_status_flags_ss";
end FiFo_wr_status_flags_ss;
architecture STRUCTURE of FiFo_wr_status_flags_ss is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
Q => \^p_1_out\,
R => '0'
);
ram_full_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => ram_full_comb,
Q => full,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end FiFo_blk_mem_gen_prim_width;
architecture STRUCTURE of FiFo_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.FiFo_blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[5]\(5 downto 0) => \gc0.count_d1_reg[5]\(5 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_rd_logic is
port (
p_2_out : out STD_LOGIC;
empty : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_full_comb : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
p_1_out : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_reg[0]\ : in STD_LOGIC;
rd_en : in STD_LOGIC;
\gcc0.gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_rd_logic : entity is "rd_logic";
end FiFo_rd_logic;
architecture STRUCTURE of FiFo_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_2_out\ : STD_LOGIC;
signal rpntr_n_6 : STD_LOGIC;
begin
E(0) <= \^e\(0);
p_2_out <= \^p_2_out\;
\grss.rsts\: entity work.FiFo_rd_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[5]\ => \^p_2_out\,
ram_empty_fb_i_reg_0 => rpntr_n_6,
rd_en => rd_en
);
rpntr: entity work.FiFo_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5 downto 0),
E(0) => \^e\(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
\gc0.count_d1_reg[5]_0\(5 downto 0) => \gc0.count_d1_reg[5]\(5 downto 0),
\gc0.count_reg[0]_0\ => \gc0.count_reg[0]\,
\gcc0.gc0.count_d1_reg[5]\(5 downto 0) => \gcc0.gc0.count_d1_reg[5]\(5 downto 0),
p_1_out => p_1_out,
p_2_out => \^p_2_out\,
ram_empty_fb_i_reg => rpntr_n_6,
ram_full_comb => ram_full_comb,
rd_en => rd_en,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_wr_logic is
port (
p_1_out : out STD_LOGIC;
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gcc0.gc0.count_d1_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
ram_full_comb : in STD_LOGIC;
clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
\gc0.count_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
rd_en : in STD_LOGIC;
p_2_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_wr_logic : entity is "wr_logic";
end FiFo_wr_logic;
architecture STRUCTURE of FiFo_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gwss.wsts\: entity work.FiFo_wr_status_flags_ss
port map (
E(0) => \^e\(0),
clk => clk,
full => full,
p_1_out => p_1_out,
ram_full_comb => ram_full_comb,
wr_en => wr_en
);
wpntr: entity work.FiFo_wr_bin_cntr
port map (
E(0) => \^e\(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
\gc0.count_reg[5]\(5 downto 0) => \gc0.count_reg[5]\(5 downto 0),
\gcc0.gc0.count_d1_reg[5]_0\(5 downto 0) => \gcc0.gc0.count_d1_reg[5]\(5 downto 0),
p_2_out => p_2_out,
ram_empty_fb_i_reg => ram_empty_fb_i_reg,
rd_en => rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end FiFo_blk_mem_gen_generic_cstr;
architecture STRUCTURE of FiFo_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.FiFo_blk_mem_gen_prim_width
port map (
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[5]\(5 downto 0) => \gc0.count_d1_reg[5]\(5 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_blk_mem_gen_top : entity is "blk_mem_gen_top";
end FiFo_blk_mem_gen_top;
architecture STRUCTURE of FiFo_blk_mem_gen_top is
begin
\valid.cstr\: entity work.FiFo_blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[5]\(5 downto 0) => \gc0.count_d1_reg[5]\(5 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_blk_mem_gen_v8_3_1_synth is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end FiFo_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of FiFo_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.FiFo_blk_mem_gen_top
port map (
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[5]\(5 downto 0) => \gc0.count_d1_reg[5]\(5 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_blk_mem_gen_v8_3_1 is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
end FiFo_blk_mem_gen_v8_3_1;
architecture STRUCTURE of FiFo_blk_mem_gen_v8_3_1 is
begin
inst_blk_mem_gen: entity work.FiFo_blk_mem_gen_v8_3_1_synth
port map (
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[5]\(5 downto 0) => \gc0.count_d1_reg[5]\(5 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_memory is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
din : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_memory : entity is "memory";
end FiFo_memory;
architecture STRUCTURE of FiFo_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.FiFo_blk_mem_gen_v8_3_1
port map (
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[5]\(5 downto 0) => \gc0.count_d1_reg[5]\(5 downto 0),
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end FiFo_fifo_generator_ramfifo;
architecture STRUCTURE of FiFo_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal \gwss.wsts/ram_full_comb\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_10_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_11_out : STD_LOGIC_VECTOR ( 5 downto 0 );
signal p_16_out : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
\gntv_or_sync_fifo.gl0.rd\: entity work.FiFo_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(5 downto 0) => p_0_out(5 downto 0),
E(0) => ram_rd_en_i,
Q(5 downto 0) => p_11_out(5 downto 0),
clk => clk,
empty => empty,
\gc0.count_d1_reg[5]\(5 downto 0) => rd_pntr_plus1(5 downto 0),
\gc0.count_reg[0]\ => \gntv_or_sync_fifo.gl0.wr_n_3\,
\gcc0.gc0.count_d1_reg[5]\(5 downto 0) => p_10_out(5 downto 0),
p_1_out => p_1_out,
p_2_out => p_2_out,
ram_full_comb => \gwss.wsts/ram_full_comb\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.FiFo_wr_logic
port map (
E(0) => p_16_out,
Q(5 downto 0) => p_10_out(5 downto 0),
clk => clk,
full => full,
\gc0.count_reg[5]\(5 downto 0) => rd_pntr_plus1(5 downto 0),
\gcc0.gc0.count_d1_reg[5]\(5 downto 0) => p_11_out(5 downto 0),
p_1_out => p_1_out,
p_2_out => p_2_out,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
ram_full_comb => \gwss.wsts/ram_full_comb\,
rd_en => rd_en,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.FiFo_memory
port map (
E(0) => ram_rd_en_i,
Q(5 downto 0) => p_10_out(5 downto 0),
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
\gc0.count_d1_reg[5]\(5 downto 0) => p_0_out(5 downto 0),
ram_full_fb_i_reg(0) => p_16_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_fifo_generator_top : entity is "fifo_generator_top";
end FiFo_fifo_generator_top;
architecture STRUCTURE of FiFo_fifo_generator_top is
begin
\grf.rf\: entity work.FiFo_fifo_generator_ramfifo
port map (
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_fifo_generator_v13_0_1_synth is
port (
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_aclk : in STD_LOGIC;
rd_en : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_fifo_generator_v13_0_1_synth : entity is "fifo_generator_v13_0_1_synth";
end FiFo_fifo_generator_v13_0_1_synth;
architecture STRUCTURE of FiFo_fifo_generator_v13_0_1_synth is
begin
\gconvfifo.rf\: entity work.FiFo_fifo_generator_top
port map (
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
wr_en => wr_en
);
\reset_gen_cc.rstblk_cc\: entity work.FiFo_reset_blk_ramfifo
port map (
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo_fifo_generator_v13_0_1 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 5 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of FiFo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 8;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of FiFo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of FiFo_fifo_generator_v13_0_1 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of FiFo_fifo_generator_v13_0_1 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of FiFo_fifo_generator_v13_0_1 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of FiFo_fifo_generator_v13_0_1 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of FiFo_fifo_generator_v13_0_1 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of FiFo_fifo_generator_v13_0_1 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of FiFo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of FiFo_fifo_generator_v13_0_1 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of FiFo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of FiFo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of FiFo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of FiFo_fifo_generator_v13_0_1 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of FiFo_fifo_generator_v13_0_1 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of FiFo_fifo_generator_v13_0_1 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of FiFo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of FiFo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of FiFo_fifo_generator_v13_0_1 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of FiFo_fifo_generator_v13_0_1 : entity is 62;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of FiFo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of FiFo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of FiFo_fifo_generator_v13_0_1 : entity is 61;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of FiFo_fifo_generator_v13_0_1 : entity is 64;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 6;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of FiFo_fifo_generator_v13_0_1 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of FiFo_fifo_generator_v13_0_1 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of FiFo_fifo_generator_v13_0_1 : entity is 64;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of FiFo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of FiFo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of FiFo_fifo_generator_v13_0_1 : entity is 6;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of FiFo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of FiFo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of FiFo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of FiFo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of FiFo_fifo_generator_v13_0_1 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of FiFo_fifo_generator_v13_0_1 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of FiFo_fifo_generator_v13_0_1 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of FiFo_fifo_generator_v13_0_1 : entity is "fifo_generator_v13_0_1";
end FiFo_fifo_generator_v13_0_1;
architecture STRUCTURE of FiFo_fifo_generator_v13_0_1 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.FiFo_fifo_generator_v13_0_1_synth
port map (
clk => clk,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
rd_en => rd_en,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity FiFo is
port (
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of FiFo : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of FiFo : entity is "FiFo,fifo_generator_v13_0_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of FiFo : entity is "FiFo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of FiFo : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of FiFo : entity is "fifo_generator_v13_0_1,Vivado 2015.4";
end FiFo;
architecture STRUCTURE of FiFo is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 1;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 8;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 8;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 0;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 62;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 61;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 64;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 6;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 6;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 64;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 6;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.FiFo_fifo_generator_v13_0_1
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9 downto 0) => B"0000000000",
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9 downto 0) => B"0000000000",
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9 downto 0) => B"0000000000",
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => clk,
data_count(5 downto 0) => NLW_U0_data_count_UNCONNECTED(5 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1 downto 0) => B"00",
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1 downto 0) => B"00",
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(5 downto 0) => B"000000",
prog_empty_thresh_assert(5 downto 0) => B"000000",
prog_empty_thresh_negate(5 downto 0) => B"000000",
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(5 downto 0) => B"000000",
prog_full_thresh_assert(5 downto 0) => B"000000",
prog_full_thresh_negate(5 downto 0) => B"000000",
rd_clk => '0',
rd_data_count(5 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(5 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => B"000",
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => B"000",
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(0) => '0',
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(3 downto 0) => B"0000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => B"000",
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7 downto 0) => B"00000000",
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => '0',
wr_data_count(5 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(5 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
mit
|
72f5b10fe9a2dbdec131f094b7d232cd
| 0.646471 | 2.861366 | false | false | false | false |
luebbers/reconos
|
demos/shared_tlb_demo/hw_task_v1_01_b/hdl/vhdl/hw_task.vhd
| 1 | 6,337 |
------------
-- pcore top level wrapper
-- generated at 2008-08-02 04:42:39.703698 by 'mkhwthread.py hwt_mbox 1 hwt_mbox.vhd'
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.ALL;
library burst_ram_v2_01_a;
use burst_ram_v2_01_a.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hw_task is
generic (
C_BUS_BURST_AWIDTH : integer := 14; -- Note: This addresses bytes
C_BUS_BURST_DWIDTH : integer := 64;
C_TASK_BURST_AWIDTH : integer := 12; -- this addresses 32Bit words
C_TASK_BURST_DWIDTH : integer := 32;
C_REGISTER_OSIF_PORTS : integer := 0; -- insert registers into OSIF ports
C_DEDICATED_CLK : integer := 0 -- use dedicated clock input (i_threadClk) for hardware thread
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
-- burst mem interface
i_burstAddr : in std_logic_vector(0 to C_BUS_BURST_AWIDTH-1);
i_burstData : in std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
o_burstData : out std_logic_vector(0 to C_BUS_BURST_DWIDTH-1);
i_burstWE : in std_logic;
i_burstBE : in std_logic_vector(0 to C_BUS_BURST_DWIDTH/8-1);
i_threadClk : in std_logic
);
end hw_task;
architecture structural of hw_task is
constant C_GND_TASK_DATA : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1) := (others => '0');
constant C_GND_TASK_ADDR : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal o_osif_flat_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal i_osif_flat_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal task2burst_Addr : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
signal task2burst_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal burst2task_Data : std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
signal task2burst_WE : std_logic;
signal task2burst_Clk : std_logic;
signal busy_local : std_logic;
signal threadClk : std_logic;
attribute keep_hierarchy : string;
attribute keep_hierarchy of structural: architecture is "true";
begin
dont_use_separate_clock : if C_DEDICATED_CLK = 0 generate
threadClk <= clk;
end generate;
use_separate_clock : if C_DEDICATED_CLK /= 0 generate
threadClk <= i_threadClk;
end generate;
-- connect top level signals
dont_register_osif_ports : if C_REGISTER_OSIF_PORTS = 0 generate
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
end generate;
register_osif_ports : if C_REGISTER_OSIF_PORTS /= 0 generate
register_osif_ports_proc: process(clk)
begin
if rising_edge(clk) then
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
end if;
end process;
end generate;
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
-- overlay busy with local busy signal
i_osif <= to_osif_os2task_t(i_osif_flat_i or (X"0000000000" & busy_local & "000000"));
-- instantiate user task
hwt_i : entity hwt
generic map (
C_BURST_AWIDTH => C_TASK_BURST_AWIDTH,
C_BURST_DWIDTH => C_TASK_BURST_DWIDTH
)
port map (
clk => threadClk,
reset => reset,
i_osif => i_osif,
o_osif => o_osif,
o_RAMAddr => task2burst_Addr,
o_RAMData => task2burst_Data,
i_RAMData => burst2task_Data,
o_RAMWE => task2burst_WE,
o_RAMClk => task2burst_Clk
);
burst_ram_i : entity burst_ram_v2_01_a.burst_ram
generic map (
G_PORTA_AWIDTH => C_TASK_BURST_AWIDTH,
G_PORTA_DWIDTH => C_TASK_BURST_DWIDTH,
G_PORTA_PORTS => 1,
G_PORTB_AWIDTH => C_BUS_BURST_AWIDTH-3,
G_PORTB_DWIDTH => C_BUS_BURST_DWIDTH,
G_PORTB_USE_BE => 1
)
port map (
addra => task2burst_Addr,
addrax => C_GND_TASK_ADDR,
addrb => i_burstAddr(0 to C_BUS_BURST_AWIDTH-1 -3), -- RAM is addressing 64Bit values
clka => task2burst_Clk,
clkax => '0',
clkb => clk,
dina => task2burst_Data,
dinax => C_GND_TASK_DATA,
dinb => i_burstData,
douta => burst2task_Data,
doutax => open,
doutb => o_burstData,
wea => task2burst_WE,
weax => '0',
web => i_burstWE,
ena => '1',
enax => '0',
enb => '1',
beb => i_burstBE
);
-- infer latch for local busy signal
-- needed for asynchronous communication between thread and OSIF
busy_local_gen : process(reset, o_osif.request, i_osif.ack)
begin
if reset = '1' then
busy_local <= '0';
elsif o_osif.request = '1' then
busy_local <= '1';
elsif i_osif.ack = '1' then
busy_local <= '0';
end if;
end process;
end structural;
|
gpl-3.0
|
05285b4649e190a54d04026c413c97a5
| 0.498027 | 3.960625 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/User_Demo/src/hdl/MicDisplay.vhd
| 1 | 10,206 |
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz, Albert Fazakas
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
-- Design Name:
-- Module Name: MicDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MicDisplay is
Generic (
X_WIDTH : integer := 1000;
Y_HEIGHT : integer := 375;
X_START : integer range 2 to (Integer'high) := 25;
Y_START : integer := 512;
PXLCLK_FREQ_HZ : integer := 108000000;
H_MAX : integer := 1688;
SAMPLE_RATE_DIV : integer := 4096;
BG_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"FFF";
ACTIVE_COLOR : STD_LOGIC_VECTOR (11 downto 0) := x"008"
);
Port ( CLK_I : in STD_LOGIC;
SYSCLK : in STD_LOGIC;
MIC_M_DATA_I : in STD_LOGIC;
MIC_M_CLK_RISING : IN STD_LOGIC;
H_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
V_COUNT_I : in STD_LOGIC_VECTOR (11 downto 0);
RED_O : out STD_LOGIC_VECTOR (3 downto 0);
GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
BLUE_O : out STD_LOGIC_VECTOR (3 downto 0)
);
end MicDisplay;
architecture Behavioral of MicDisplay is
--SAMPLE_OFFSET accounts for the offset from center caused by scaling the microphone sensitivity
--Calculated for HEIGHT=375 and sensitivy=3x, accounts for overflow in sample_reg
constant SAMPLE_OFFSET : integer := 105; --95
-- Microphone display frame limits
constant MIC_LEFT : natural := X_START - 1;
constant MIC_RIGHT : natural := X_START + X_WIDTH + 1;
constant MIC_TOP : natural := Y_START - 1;
constant MIC_BOTTOM : natural := Y_START + Y_HEIGHT + 1;
-----------------------------------------------------------------------------------------------------------
--dependent constants
-----------------------------------------------------------------------------------------------------------
-- Number of bits needed to store the samples
constant SAMPLE_WIDTH : integer := natural(ceil(LOG2(real(Y_HEIGHT))));
constant SR_WIDTH : integer := (Y_HEIGHT);
-- The time needed to draw the microphone display window is Y_HEIGHT * (H_MAX / PXLCLK_FREQ_HZ)
-- in our case 375 * (1688/108000000) = 5.861mS
-- The sample frequency is PXLCLK_FREQ_HZ/SAMPLE_RATE_DIV = 26367.18 Hz, therefore the sample period
-- is 37.92 uS.
-- While the microphone display is active, the samples should be stored in a buffer region which is not
-- read during the microphone display. Therefore we need an extra buffer size called padding.
-- The needed padding size therefore is the time needed to draw the microphone window diwided by
-- the sample time, i.e. (Y_HEIGHT * H_MAX)/SAMPLE_RATE_DIV = 154.54 ~ 155
constant BUF_PADDING_NEEDED : natural := natural(ceil((real(Y_HEIGHT) * real(H_MAX))/(real(SAMPLE_RATE_DIV))));
-- Total buffer size needed
constant BUF_DEPTH_NEEDED : natural := X_WIDTH + BUF_PADDING_NEEDED;
-- The sample buffer will be implemented in a BRAM, therefore the buffer size will be a power of two
constant BUF_ADDR_WIDTH : natural := natural(ceil(LOG2(real(BUF_DEPTH_NEEDED))));
-- Size of the whole buffer
constant BUF_DEPTH : integer := 2**BUF_ADDR_WIDTH;
-- Extra buffer size used as buffer padding
constant BUF_PADDING : integer := (BUF_DEPTH - X_WIDTH) ;
-- Create a BRAM to store and display samples
type SAMPLE_MEM_TYPE is array ((BUF_DEPTH - 1) downto 0) of std_logic_vector((SAMPLE_WIDTH - 1) downto 0);
signal sample_buf_ram : SAMPLE_MEM_TYPE;
-- Force BRAM implementation for sample_buf_ram
attribute RAM_STYLE : string;
attribute RAM_STYLE of sample_buf_ram: signal is "BLOCK";
-- RAM Write Enable
signal en_wr_sample_buf_ram : std_logic;
-- Data read from the memory
signal rd_data : std_logic_vector (SAMPLE_WIDTH - 1 downto 0);
-- Memory write address
signal wr_addr_reg : natural range 0 to (BUF_DEPTH - 1) := 0;
-- Memory read current address
signal rd_addr_reg : natural range 0 to (BUF_DEPTH - 1) := 0;
-- Memory read starting address
-- This will be set at BUF_PADDING distance from the write address value
-- at the beginning of drawing the audio frame
signal rd_frame_start_reg : natural range 0 to (BUF_DEPTH - 1) := 0;
-- Synchronize the MIC_M_CLK_RISING signal, coming from the 100MHz Clock Domain
signal mic_m_clk_rising_sync1, mic_m_clk_rising_sync0, mic_m_clk_rising_sync : std_logic;
-- The MIC_M_CLK_RISING signal legth is two SYSCLK (100MHz) periods length,
-- therefore create a one-shot signal
signal mic_m_clk_rising_os : std_logic;
-- Sample window register - shift register for the microphone data
signal mic_sr_reg : std_logic_vector (SR_WIDTH - 1 downto 0) := (others=>'0');
-- Sample register data
signal sample_reg : std_logic_vector (SAMPLE_WIDTH - 1 downto 0) := (others=>'0');
-- Counter for the sample rate
signal clk_cntr_reg : integer range 0 to SAMPLE_RATE_DIV - 1 := 0;
-- R, G and B output signal, each on 4 bits
signal color_out : std_logic_vector (11 downto 0);
begin
-------------------------------------------
------------ MIC ------------------
-------------------------------------------
-- sinchronize MIC_M_CLK_RISING
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
mic_m_clk_rising_sync1 <= MIC_M_CLK_RISING;
mic_m_clk_rising_sync0 <= mic_m_clk_rising_sync1;
mic_m_clk_rising_sync <= mic_m_clk_rising_sync0;
end if;
end process;
-- create the one-shot signal for MIC_M_CLK_RISING
mic_m_clk_rising_os <= mic_m_clk_rising_sync0 AND (NOT mic_m_clk_rising_sync);
--Create the sample rate counter
--mclk = 2 MHz, sample rate = 108MHz / 4096 = ~26.367 KHz
process(SYSCLK)
begin
if (rising_edge(SYSCLK)) then
if clk_cntr_reg = SAMPLE_RATE_DIV - 1 then
clk_cntr_reg <= 0;
else
clk_cntr_reg <= clk_cntr_reg + 1;
end if;
end if;
end process;
--Enable write sample to RAM (triggered every 1/26367 seconds)
en_wr_sample_buf_ram <= '1' when clk_cntr_reg = SAMPLE_RATE_DIV - 1 else '0';
-------------------------------------------
-- Shift in Microphone data
-------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if MIC_M_CLK_RISING_OS = '1' then
--Shift new data into the sample window
mic_sr_reg(0) <= MIC_M_DATA_I;
mic_sr_reg(SR_WIDTH - 1 downto 1) <= mic_sr_reg((SR_WIDTH - 2) downto 0);
--Monitor the sample window by updating the value of the sample reg each
--time data is shifted.
if ((mic_sr_reg(SR_WIDTH - 1) = '0') and (MIC_M_DATA_I = '1')) then
sample_reg <= sample_reg + 3;
elsif ((mic_sr_reg(SR_WIDTH - 1) = '1') and (MIC_M_DATA_I = '0')) then
sample_reg <= sample_reg - 3;
end if;
end if;
end if;
end process;
-------------------------------------------
-- Increment and wrap around write address
-------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if en_wr_sample_buf_ram = '1' then
if (wr_addr_reg = (BUF_DEPTH - 1)) then
wr_addr_reg <= 0;
else
wr_addr_reg <= wr_addr_reg + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- Set the starting RAM read address for this frame.
-- This is done at the beginning of the first line on which the window is drawn.
-- This mechanism prevents tearing of the frame that would occur
-- if a new audio sample was captured while the frame is being drawn.
--------------------------------------------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (H_COUNT_I = 0 and V_COUNT_I = Y_START) then
--Wrap the address if necessary
if ((wr_addr_reg + BUF_PADDING) >= BUF_DEPTH) then
rd_frame_start_reg <= (wr_addr_reg + BUF_PADDING) - BUF_DEPTH;
else
rd_frame_start_reg <= (wr_addr_reg + BUF_PADDING);
end if;
end if;
end if;
end process;
-------------------------------------------
-- Increment and wrap around read address
-------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (H_COUNT_I = (X_START - 1)) then
rd_addr_reg <= rd_frame_start_reg;
elsif (rd_addr_reg = (BUF_DEPTH - 1)) then
rd_addr_reg <= 0;
else
rd_addr_reg <= rd_addr_reg + 1;
end if;
end if;
end process;
------------------------------------------
-- Dual-Port BRAM read and write process
------------------------------------------
process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if en_wr_sample_buf_ram = '1' then
sample_buf_ram(wr_addr_reg) <= sample_reg + SAMPLE_OFFSET;
end if;
rd_data <= sample_buf_ram(rd_addr_reg);
end if;
end process;
color_out <= ACTIVE_COLOR when ((((V_COUNT_I - Y_START) - rd_data) <= 3) or (((rd_data + Y_START) - V_COUNT_I) <= 3)) else
BG_COLOR;
--
-- Assign Outputs
RED_O <= color_out(11 downto 8) when (H_COUNT_I > MIC_LEFT and H_COUNT_I < MIC_RIGHT)
and (V_COUNT_I < MIC_BOTTOM and V_COUNT_I > MIC_TOP)
else x"F";
GREEN_O <= color_out(7 downto 4) when (H_COUNT_I > MIC_LEFT and H_COUNT_I < MIC_RIGHT)
and (V_COUNT_I < MIC_BOTTOM and V_COUNT_I > MIC_TOP)
else x"F";
BLUE_O <= color_out(3 downto 0) when (H_COUNT_I > MIC_LEFT and H_COUNT_I < MIC_RIGHT)
and (V_COUNT_I < MIC_BOTTOM and V_COUNT_I > MIC_TOP)
else x"F";
end Behavioral;
|
gpl-3.0
|
7169eca2b3de47e3807dcbb3ac50bdb4
| 0.579267 | 3.58231 | false | false | false | false |
luebbers/reconos
|
core/pcores/xps_osif_v2_01_a/hdl/vhdl/xps_osif.vhd
| 1 | 46,708 |
------------------------------------------------------------------------------
--
-- \file xps_osif.vhd
--
-- Wrapper to connect OSIF to PLBv46
--
-- Mostly generated using Xilinx tools.
--
-- \author Enno Luebbers <[email protected]>
-- \date 11.08.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
-- Original Xilinx header follows:
--
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: xps_osif.vhd
-- Version: 2.01.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Wed May 27 14:11:08 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_master_burst_v1_01_a;
use plbv46_master_burst_v1_01_a.plbv46_master_burst;
library osif_core_v2_01_a;
use osif_core_v2_01_a.all;
library xps_osif_v2_01_a;
use xps_osif_v2_01_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
-- C_MEM1_BASEADDR -- User memory space 1 base address
-- C_MEM1_HIGHADDR -- User memory space 1 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity xps_osif is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
C_BURST_AWIDTH : integer := 13; -- 1024 x 64 Bit = 8192 Bytes = 2^13 Bytes
C_FIFO_DWIDTH : integer := 32;
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32;
C_DCR_ILA : integer := 0;
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
-- C_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_HIGHADDR : std_logic_vector := X"00000000";
-- C_SPLB_AWIDTH : integer := 32;
-- C_SPLB_DWIDTH : integer := 128;
-- C_SPLB_NUM_MASTERS : integer := 8;
-- C_SPLB_MID_WIDTH : integer := 3;
-- C_SPLB_NATIVE_DWIDTH : integer := 32;
-- C_SPLB_P2P : integer := 0;
-- C_SPLB_SUPPORT_BURSTS : integer := 0;
-- C_SPLB_SMALLEST_MASTER : integer := 32;
-- C_SPLB_CLK_PERIOD_PS : integer := 10000;
-- C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 64;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
-- C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_MEM0_HIGHADDR : std_logic_vector := X"00000000";
-- C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
-- C_MEM1_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
sys_clk : in std_logic;
sys_reset : in std_logic;
interrupt : out std_logic;
busy : out std_logic;
blocking : out std_logic;
-- task interface
task_clk : out std_logic;
task_reset : out std_logic;
osif_os2task_vec : out std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
osif_task2os_vec : in std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
-- burst mem interface
burstAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
burstWrData : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
burstRdData : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
burstWE : out std_logic;
burstBE : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
-- FIFO access signals
o_fifo_clk : out std_logic;
o_fifo_reset : out std_logic;
-- left (read) FIFO
o_fifo_read_en : out std_logic;
i_fifo_read_data : in std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_read_ready : in std_logic;
-- right (write) FIFO
o_fifo_write_en : out std_logic;
o_fifo_write_data : out std_logic_vector(0 to C_FIFO_DWIDTH-1);
i_fifo_write_ready : in std_logic;
-- bus macro control
bmEnable : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DCR Bus protocol ports
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
i_dcrICON : in std_logic_vector(35 downto 0); -- chipscope
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
-- sys_clk : in std_logic;
-- sys_reset : in std_logic;
-- SPLB_Clk : in std_logic;
-- SPLB_Rst : in std_logic;
-- PLB_ABus : in std_logic_vector(0 to 31);
-- PLB_UABus : in std_logic_vector(0 to 31);
-- PLB_PAValid : in std_logic;
-- PLB_SAValid : in std_logic;
-- PLB_rdPrim : in std_logic;
-- PLB_wrPrim : in std_logic;
-- PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
-- PLB_abort : in std_logic;
-- PLB_busLock : in std_logic;
-- PLB_RNW : in std_logic;
-- PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
-- PLB_MSize : in std_logic_vector(0 to 1);
-- PLB_size : in std_logic_vector(0 to 3);
-- PLB_type : in std_logic_vector(0 to 2);
-- PLB_lockErr : in std_logic;
-- PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
-- PLB_wrBurst : in std_logic;
-- PLB_rdBurst : in std_logic;
-- PLB_wrPendReq : in std_logic;
-- PLB_rdPendReq : in std_logic;
-- PLB_wrPendPri : in std_logic_vector(0 to 1);
-- PLB_rdPendPri : in std_logic_vector(0 to 1);
-- PLB_reqPri : in std_logic_vector(0 to 1);
-- PLB_TAttribute : in std_logic_vector(0 to 15);
-- Sl_addrAck : out std_logic;
-- Sl_SSize : out std_logic_vector(0 to 1);
-- Sl_wait : out std_logic;
-- Sl_rearbitrate : out std_logic;
-- Sl_wrDAck : out std_logic;
-- Sl_wrComp : out std_logic;
-- Sl_wrBTerm : out std_logic;
-- Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
-- Sl_rdWdAddr : out std_logic_vector(0 to 3);
-- Sl_rdDAck : out std_logic;
-- Sl_rdComp : out std_logic;
-- Sl_rdBTerm : out std_logic;
-- Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
-- Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
-- attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of MPLB_Clk : signal is "CLK";
-- attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of MPLB_Rst : signal is "RST";
end entity xps_osif;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of xps_osif is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
--constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
--constant USER_MST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
--constant USER_MST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
--USER_LOGIC needs this parameter
--constant BURST_BASEADDR : std_logic_vector := C_BASEADDR or X"00004000";
--constant BURST_HIGHADDR : std_logic_vector := C_BASEADDR or X"00007FFF";
--constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
--(
--ZERO_ADDR_PAD & USER_MST_BASEADDR, -- user logic master space base address
--ZERO_ADDR_PAD & USER_MST_HIGHADDR, -- user logic master space high address
--ZERO_ADDR_PAD & BURST_BASEADDR, -- user logic memory space 0 base address
--ZERO_ADDR_PAD & BURST_HIGHADDR -- user logic memory space 0 high address
--ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address
--ZERO_ADDR_PAD & C_MEM1_HIGHADDR -- user logic memory space 1 high address
-- );
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
-- constant USER_MST_NUM_REG : integer := 1;
-- constant USER_NUM_REG : integer := USER_MST_NUM_REG;
-- constant USER_NUM_MEM : integer := 1;
-- constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
-- (
--0 => pad_power2(USER_MST_NUM_REG), -- number of ce for user logic master space
-- 0 => 1
--1 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
--2 => 1 -- number of ce for user logic memory space 1 (always 1 chip enable)
-- );
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
--constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
--constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of the master data bus (32, 64, or 128)
------------------------------------------
constant USER_MST_DWIDTH : integer := C_MPLB_DWIDTH;
constant IPIF_MST_DWIDTH : integer := C_MPLB_DWIDTH;
------------------------------------------
-- Inhibit the automatic inculsion of the Conversion Cycle and Burst Length Expansion logic
-- 0 = allow automatic inclusion of the CC and BLE logic
-- 1 = inhibit automatic inclusion of the CC and BLE logic
------------------------------------------
constant IPIF_INHIBIT_CC_BLE_INCLUSION : integer := 0;
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
--constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Width of the master address bus (32 only)
------------------------------------------
constant USER_MST_AWIDTH : integer := C_MPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
--constant USER_MST_CS_INDEX : integer := 0;
--constant USER_MST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_MST_CS_INDEX);
--constant USER_MEM0_CS_INDEX : integer := 1;
--constant USER_MEM0_CS_INDEX : integer := 0;
--constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
--constant USER_CE_INDEX : integer := USER_MST_CE_INDEX;
--constant USER_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_CS_INDEX);
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
-- signal ipif_Bus2IP_Clk : std_logic;
-- signal ipif_Bus2IP_Reset : std_logic;
-- signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_MST_DWIDTH-1);
-- signal ipif_IP2Bus_WrAck : std_logic;
-- signal ipif_IP2Bus_RdAck : std_logic;
-- signal ipif_IP2Bus_AddrAck : std_logic;
-- signal ipif_IP2Bus_Error : std_logic;
-- signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
-- signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_MST_DWIDTH-1);
-- signal ipif_Bus2IP_RNW : std_logic;
-- signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
-- signal ipif_Bus2IP_Burst : std_logic;
-- signal ipif_Bus2IP_BurstLength : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
-- signal ipif_Bus2IP_WrReq : std_logic;
-- signal ipif_Bus2IP_RdReq : std_logic;
-- signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
-- signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
-- signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_IP2Bus_MstRd_Req : std_logic;
signal ipif_IP2Bus_MstWr_Req : std_logic;
signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
signal ipif_IP2Bus_Mst_Length : std_logic_vector(0 to 11);
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_Mst_Type : std_logic;
signal ipif_IP2Bus_Mst_Lock : std_logic;
signal ipif_IP2Bus_Mst_Reset : std_logic;
signal ipif_Bus2IP_Mst_CmdAck : std_logic;
signal ipif_Bus2IP_Mst_Cmplt : std_logic;
signal ipif_Bus2IP_Mst_Error : std_logic;
signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_Bus2IP_MstRd_sof_n : std_logic;
signal ipif_Bus2IP_MstRd_eof_n : std_logic;
signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
signal ipif_Bus2IP_MstRd_src_dsc_n : std_logic;
signal ipif_IP2Bus_MstRd_dst_rdy_n : std_logic;
signal ipif_IP2Bus_MstRd_dst_dsc_n : std_logic;
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_IP2Bus_MstWr_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_MstWr_sof_n : std_logic;
signal ipif_IP2Bus_MstWr_eof_n : std_logic;
signal ipif_IP2Bus_MstWr_src_rdy_n : std_logic;
signal ipif_IP2Bus_MstWr_src_dsc_n : std_logic;
signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
signal ipif_Bus2IP_MstWr_dst_dsc_n : std_logic;
-- signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
-- signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
-- signal user_Bus2IP_BurstLength : std_logic_vector(0 to 8) := (others => '0');
-- signal user_Bus2IP_Data : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_Bus2IP_DataX : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_Data : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_DataX : std_logic_vector(0 to USER_MST_DWIDTH-1);
-- signal user_IP2Bus_RdAck : std_logic;
-- signal user_IP2Bus_WrAck : std_logic;
-- signal user_IP2Bus_Error : std_logic;
signal task_clk_internal : std_logic;
signal task_reset_internal : std_logic;
-- single word data input/output
signal mem2osif_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
signal osif2mem_singleData : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1);
-- addresses for master transfers
signal mem_localAddr : std_logic_vector(0 to USER_MST_AWIDTH-1);
signal mem_targetAddr : std_logic_vector(0 to USER_MST_AWIDTH-1);
-- single word transfer requests
signal mem_singleRdReq : std_logic;
signal mem_singleWrReq : std_logic;
-- burst transfer requests
signal mem_burstRdReq : std_logic;
signal mem_burstWrReq : std_logic;
signal mem_burstLen : std_logic_vector(0 to 11);
-- status outputs
signal mem_busy : std_logic;
signal mem_rdDone : std_logic;
signal mem_wrDone : std_logic;
---------
-- local FIFO control and data lines
---------
signal fifomgr_read_remove : std_logic;
signal fifomgr_read_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_read_wait : std_logic;
signal fifomgr_write_add : std_logic;
signal fifomgr_write_data : std_logic_vector(0 to C_FIFO_DWIDTH-1);
signal fifomgr_write_wait : std_logic;
-- bus macro control signal
signal bmEnable_i : std_logic;
-- incoming task signals (can be disabled via bmEnable_i)
signal osif_task2os_vec_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal burstRdData_i : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
begin
---------
-- set task clock/reset
---------
task_clk <= task_clk_internal;
task_reset <= task_reset_internal;
-- propagate bus macro enable signal (COMPATIBILITY with older tool chains)
bmEnable <= bmEnable_i;
-- gate incoming task signals with bmEnable_i
gate_incoming : process(bmEnable_i, osif_task2os_vec, burstRdData)
begin
if bmEnable_i = '1' then
osif_task2os_vec_i <= osif_task2os_vec;
burstRdData_i <= burstRdData;
else
osif_task2os_vec_i <= (others => '0');
burstRdData_i <= (others => '0');
end if;
end process;
--------------------------------------
-- memory bus controller core
--
-- PLBv46
---------------------------------------
mem_plb46_i : entity xps_osif_v2_01_a.mem_plb46
generic map
(
-- Bus protocol parameters
C_AWIDTH => C_MPLB_AWIDTH,
C_DWIDTH => 32,
C_PLB_AWIDTH => C_MPLB_AWIDTH,
C_PLB_DWIDTH => C_MPLB_NATIVE_DWIDTH,
--C_NUM_CE => USER_MST_NUM_REG,
C_BURST_AWIDTH => C_BURST_AWIDTH
)
port map
(
clk => task_clk_internal,
reset => task_reset_internal,
-- data interface ---------------------------
-- burst mem interface
o_burstAddr => burstAddr,
o_burstData => burstWrData,
i_burstData => burstRdData_i,
o_burstWE => burstWE,
o_burstBE => burstBE,
-- single word data input/output
i_singleData => osif2mem_singleData,
o_singleData => mem2osif_singleData,
-- control interface ------------------------
-- addresses for master transfers
i_localAddr => mem_localAddr,
i_targetAddr => mem_targetAddr,
-- single word transfer requests
i_singleRdReq => mem_singleRdReq,
i_singleWrReq => mem_singleWrReq,
-- burst transfer requests
i_burstRdReq => mem_burstRdReq,
i_burstWrReq => mem_burstWrReq,
i_burstLen => mem_burstLen,
-- status outputs
o_busy => mem_busy,
o_rdDone => mem_rdDone,
o_wrDone => mem_wrDone,
-- PLBv46 bus interface -----------------------------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk => MPLB_Clk,
Bus2IP_Reset => MPLB_Rst,
Bus2IP_MstError => ipif_Bus2IP_Mst_Error,
Bus2IP_MstLastAck => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_MstRdAck => PLB_MRdDAck,
Bus2IP_MstWrAck => PLB_MWrDAck,
Bus2IP_MstRetry => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_MstTimeOut => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
IP2Bus_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_MstBE => ipif_IP2Bus_Mst_BE,
IP2Bus_MstBurst => ipif_IP2Bus_Mst_Type,
IP2Bus_MstBusReset => ipif_IP2Bus_Mst_Reset,
IP2Bus_MstBusLock => ipif_IP2Bus_Mst_Lock,
IP2Bus_MstNum => ipif_IP2Bus_Mst_Length,
IP2Bus_MstRdReq => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWrReq => ipif_IP2Bus_MstWr_Req,
-- Ports for Local Link
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem,
Bus2IP_MstRd_sof_n => ipif_Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => ipif_Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => ipif_Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => ipif_IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => ipif_IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => ipif_IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => ipif_IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => ipif_IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => ipif_IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => ipif_Bus2IP_MstWr_dst_dsc_n
);
------------------------------------------
-- instantiate plbv46_master_burst
------------------------------------------
PLBV46_MASTER_BURST_I : entity plbv46_master_burst_v1_01_a.plbv46_master_burst
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_INHIBIT_CC_BLE_INCLUSION => IPIF_INHIBIT_CC_BLE_INCLUSION,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => ipif_IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => ipif_IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => ipif_IP2Bus_Mst_Addr,
IP2Bus_Mst_Length => ipif_IP2Bus_Mst_Length,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE,
IP2Bus_Mst_Type => ipif_IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => ipif_IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => ipif_IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => ipif_Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => ipif_Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => ipif_Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => ipif_Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => ipif_Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d,
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem,
Bus2IP_MstRd_sof_n => ipif_Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => ipif_Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => ipif_Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => ipif_Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => ipif_IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => ipif_IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d,
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem,
IP2Bus_MstWr_sof_n => ipif_IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => ipif_IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => ipif_IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => ipif_IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => ipif_Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => ipif_Bus2IP_MstWr_dst_dsc_n
);
-- instantiate the User Logic
------------------------------------------
USER_LOGIC_I : entity osif_core_v2_01_a.osif_core
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
C_BURST_AWIDTH => C_BURST_AWIDTH,
C_FIFO_DWIDTH => C_FIFO_DWIDTH,
C_BURSTLEN_WIDTH => 12,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_AWIDTH => C_MPLB_AWIDTH,
C_DWIDTH => 32,
C_PLB_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_NUM_CE => 2, --isnt used in USER_LOGIC
C_DCR_BASEADDR => C_DCR_BASEADDR,
C_DCR_HIGHADDR => C_DCR_HIGHADDR,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_DCR_ILA => C_DCR_ILA
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
interrupt => interrupt,
busy => busy,
blocking => blocking,
-- task interface
task_clk => task_clk_internal,
task_reset => task_reset_internal,
osif_os2task_vec => osif_os2task_vec,
osif_task2os_vec => osif_task2os_vec_i,
-- FIFO manager access signals
o_fifomgr_read_remove => fifomgr_read_remove,
i_fifomgr_read_data => fifomgr_read_data,
i_fifomgr_read_wait => fifomgr_read_wait,
o_fifomgr_write_add => fifomgr_write_add,
o_fifomgr_write_data => fifomgr_write_data,
i_fifomgr_write_wait => fifomgr_write_wait,
-- memory access signals
o_mem_singleData => osif2mem_singleData,
i_mem_singleData => mem2osif_singleData,
o_mem_localAddr => mem_localAddr,
o_mem_targetAddr => mem_targetAddr,
o_mem_singleRdReq => mem_singleRdReq,
o_mem_singleWrReq => mem_singleWrReq,
o_mem_burstRdReq => mem_burstRdReq,
o_mem_burstWrReq => mem_burstWrReq,
o_mem_burstLen => mem_burstLen,
i_mem_busy => mem_busy,
i_mem_rdDone => mem_rdDone,
i_mem_wrDone => mem_wrDone,
-- bus macro control
o_bm_enable => bmEnable_i,
-- MAP USER PORTS ABOVE THIS LINE ------------------
sys_clk => MPLB_Clk,--sys_clk,
sys_reset => MPLB_Rst,--sys_reset,
-- DCR Bus protocol ports
o_dcrAck => o_dcrAck,
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead,
i_dcrWrite => i_dcrWrite,
i_dcrICON => i_dcrICON
);
-----------------------------------------------------------------------
-- fifo_mgr_inst: FIFO manager instantiation
--
-- The FIFO manager handles incoming push/pop requests to the two
-- hardware FIFOs attached to the OSIF. It arbitrates between
-- local hardware-thread-initiated requests and indirect bus accesses
-- by other hardware threads.
-----------------------------------------------------------------------
fifo_mgr_inst : entity xps_osif_v2_01_a.fifo_mgr
generic map (
C_FIFO_DWIDTH => C_FIFO_DWIDTH
)
port map (
clk => sys_clk,
reset => sys_reset, -- we don't want a thread reset command to flush
-- the FIFOs, therefore no thread_reset_i!
-- local FIFO access signals
i_local_read_remove => fifomgr_read_remove,
o_local_read_data => fifomgr_read_data,
o_local_read_wait => fifomgr_read_wait,
i_local_write_add => fifomgr_write_add,
i_local_write_data => fifomgr_write_data,
o_local_write_wait => fifomgr_write_wait,
-- "real" FIFO access signals
o_fifo_read_en => o_fifo_read_en,
i_fifo_read_data => i_fifo_read_data,
i_fifo_read_ready => i_fifo_read_ready,
o_fifo_write_en => o_fifo_write_en,
o_fifo_write_data => o_fifo_write_data,
i_fifo_write_ready => i_fifo_write_ready
);
--------
-- set FIFO clock/reset
--------
o_fifo_clk <= sys_clk;
o_fifo_reset <= sys_reset;
------------------------------------------
-- connect internal signals
------------------------------------------
-- IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, user_IP2Bus_DataX ) is
-- begin
-- case ipif_Bus2IP_CS is
-- when "1" => ipif_IP2Bus_Data <= user_IP2Bus_Data & user_IP2Bus_DataX;
-- when "010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when "001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
-- when others => ipif_IP2Bus_Data <= (others => '0');
-- end case;
-- end process IP2BUS_DATA_MUX_PROC;
-- user_Bus2IP_Data <= ipif_Bus2IP_Data(0 to USER_MST_DWIDTH-1);
-- user_Bus2IP_DataX <= iBus2IP_Data(USER_MST_DWIDTH to C_MPLB_DWIDTH-1);
-- ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
-- ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
-- ipif_IP2Bus_Error <= user_IP2Bus_Error;
-- user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
-- user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
gpl-3.0
|
85c136d3d2df95dd45525547bea96880
| 0.491458 | 3.968394 | false | false | false | false |
BenBoZ/realtimestagram
|
src/gamma_tb.vhd
| 2 | 4,094 |
-- This file is part of Realtimestagram.
--
-- Realtimestagram is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- Realtimestagram is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with Realtimestagram. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.config_const_pkg.all;
use work.curves_pkg.all;
--======================================================================================--
entity gamma_tb is
generic (
input_file: string := "tst/input/amersfoort_gray.pgm"; --! Input file of test
output_file: string := "tst/output/gamma_output.pgm"; --! Output file of test
gamma: real := 0.5; --! Amount of contrast adjustment
c_factor: real := 1.0 --! Amount of contrast adjustment
);
end entity;
--======================================================================================--
architecture structural of gamma_tb is
--===================component declaration===================--
component test_bench_driver is
generic (
wordsize: integer := const_wordsize;
input_file: string := input_file;
output_file: string := output_file;
clk_period_ns: time := 1 ns;
rst_after: time := 9 ns;
rst_duration: time := 8 ns;
dut_delay: integer := 3
);
port (
clk: out std_logic;
rst: out std_logic;
enable: out std_logic;
pixel_from_file: out std_logic_vector((wordsize-1) downto 0);
pixel_to_file: in std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
component lookup_table is
generic (
wordsize: integer := const_wordsize;
lut: array_pixel := create_gamma_lut(2**const_wordsize, gamma, c_factor)
);
port (
clk: in std_logic;
rst: in std_logic;
enable: in std_logic;
pixel_i: in std_logic_vector((wordsize-1) downto 0);
pixel_o: out std_logic_vector((wordsize-1) downto 0)
);
end component;
----------------------------------------------------------------------------------------------
--===================signal declaration===================--
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal enable: std_logic := '0';
signal pixel_from_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
signal pixel_to_file: std_logic_vector((const_wordsize-1) downto 0) := (others => '0');
begin
--===================component instantiation===================--
tst_driver: test_bench_driver
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_from_file => pixel_from_file,
pixel_to_file => pixel_to_file
);
device_under_test: lookup_table
port map(
clk => clk,
rst => rst,
enable => enable,
pixel_i => pixel_from_file,
pixel_o => pixel_to_file
);
end architecture;
|
gpl-2.0
|
4fe4aa88f3515b3f864a2b94e10a4c94
| 0.464094 | 4.700344 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/my_core_wrapper.vhd
| 1 | 8,558 |
-------------------------------------------------------------------------------
-- my_core_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library osif_tb_v1_00_c;
use osif_tb_v1_00_c.All;
entity my_core_wrapper is
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MErr : out std_logic_vector(0 to 1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 63);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to 7);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to 63);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to 7);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to 63);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end my_core_wrapper;
architecture STRUCTURE of my_core_wrapper is
component osif_tb is
generic (
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_PLB_AWIDTH : integer;
C_PLB_DWIDTH : integer;
C_PLB_NUM_MASTERS : integer;
C_PLB_MID_WIDTH : integer;
C_FAMILY : string
);
port (
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1));
Sl_MErr : out std_logic_vector(0 to (C_PLB_NUM_MASTERS-1));
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
Sl_rdWdAddr : out std_logic_vector(0 to (3));
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to (1));
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to (C_PLB_AWIDTH-1));
PLB_BE : in std_logic_vector(0 to (C_PLB_DWIDTH/8-1));
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_PLB_MID_WIDTH-1));
PLB_MSize : in std_logic_vector(0 to (1));
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to (1));
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to (1));
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to (3));
PLB_type : in std_logic_vector(0 to (2));
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to (C_PLB_AWIDTH-1));
M_BE : out std_logic_vector(0 to (C_PLB_DWIDTH/8-1));
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to (1));
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to (1));
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to (3));
M_type : out std_logic_vector(0 to (2));
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to ((C_PLB_DWIDTH-1)));
PLB_MRdWdAddr : in std_logic_vector(0 to (3));
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to (1));
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
begin
my_core : osif_tb
generic map (
C_BASEADDR => X"30000000",
C_HIGHADDR => X"3000ffff",
C_PLB_AWIDTH => 32,
C_PLB_DWIDTH => 64,
C_PLB_NUM_MASTERS => 2,
C_PLB_MID_WIDTH => 1,
C_FAMILY => "virtex2p"
)
port map (
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize,
SYNCH_IN => SYNCH_IN,
SYNCH_OUT => SYNCH_OUT
);
end architecture STRUCTURE;
|
gpl-3.0
|
93b0aa182f70a7fa2250ce6b08615777
| 0.577355 | 3.167283 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sim_4/new/SystemTest.vhd
| 1 | 1,924 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity SystemTest is
end SystemTest;
architecture Behavioral of SystemTest is
component top is
Port (
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
Hsync : out std_logic;
Vsync : out std_logic;
led : out std_logic_vector (15 downto 0);
sw : in std_logic_vector (15 downto 0);
clk : in std_logic;
btnC : in std_logic;
btnU : in std_logic;
btnL : in std_logic;
btnR : in std_logic;
btnD : in std_logic;
PS2Clk : in std_logic;
PS2Data : in std_logic;
RsRx : inout std_logic;
RsTx : inout std_logic
);
end component;
constant clk_period : time := 1 ns;
signal vgaRed : std_logic_vector (3 downto 0);
signal vgaGreen :std_logic_vector (3 downto 0);
signal vgaBlue :std_logic_vector (3 downto 0);
signal Hsync :std_logic;
signal Vsync :std_logic;
signal led :std_logic_vector (15 downto 0);
signal sw :std_logic_vector (15 downto 0);
signal clk :std_logic := '0';
signal btnC :std_logic;
signal btnU :std_logic;
signal btnL :std_logic;
signal btnR :std_logic;
signal btnD :std_logic;
signal PS2Clk :std_logic;
signal PS2Data :std_logic;
signal RsRx : std_logic;
signal RsTx : std_logic;
begin
top0: top
port map (
vgaRed => vgaRed,
vgaGreen => vgaGreen,
vgaBlue => vgaBlue,
Hsync => Hsync,
sw => sw,
clk => clk,
btnC => btnC,
btnU => btnU,
btnL => btnL,
btnR => btnR,
btnD => btnD,
PS2Clk => PS2Clk,
PS2Data => PS2Data,
RsRx => RsRx,
RsTx => RsTx
);
process
begin
clk <= not clk;
wait for clk_period/2;
end process;
end Behavioral;
|
mit
|
48b29486db23a04f1c0ad6aa0fc178c1
| 0.628378 | 3.305842 | false | false | false | false |
denis4net/hw_design
|
1/altera-project/src/buses.vhd
| 1 | 1,559 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity busgate4 is
port(
in_bus: in std_logic_vector(3 downto 0);
is_enabled: in std_logic;
out_bus: out std_logic_vector(3 downto 0)
);
end;
architecture logic of busgate4 is
signal tmp_enabled: std_logic_vector(3 downto 0);
begin
tmp_enabled <= (others => is_enabled);
out_bus <= in_bus and tmp_enabled;
end;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity busmux4x4 is
port (
in_bus: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(3 downto 0);
out_bus: out std_logic_vector(3 downto 0)
);
end;
architecture logic of busmux4x4 is
component busgate4
port(
in_bus: in std_logic_vector(3 downto 0);
is_enabled: in std_logic;
out_bus: out std_logic_vector(3 downto 0)
);
end component;
signal internal_bus: std_logic_vector(15 downto 0);
begin
cell1: busgate4 port map (in_bus=>in_bus(3 downto 0), is_enabled=>sel(0), out_bus=>internal_bus(3 downto 0));
cell2: busgate4 port map (in_bus=>in_bus(7 downto 4), is_enabled=>sel(1), out_bus=>internal_bus(7 downto 4));
cell3: busgate4 port map (in_bus=>in_bus(11 downto 8), is_enabled=>sel(2), out_bus=>internal_bus(11 downto 8));
cell4: busgate4 port map (in_bus=>in_bus(15 downto 12), is_enabled=>sel(3), out_bus=>internal_bus(15 downto 12));
out_bus <= internal_bus(3 downto 0) or internal_bus(7 downto 4) or internal_bus(11 downto 8) or internal_bus(15 downto 12);
end logic;
|
mit
|
2c1c0dc4082ea91fac9cbdb941e5a95a
| 0.704298 | 2.697232 | false | false | false | false |
iti-luebeck/RTeasy1
|
src/main/resources/vhdltmpl/demux.vhd
| 1 | 2,446 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY demux IS
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END demux;
ARCHITECTURE recursive OF demux IS
SIGNAL subdemux_0_IN, subdemux_1_IN : std_logic_vector(line_width-1 DOWNTO 0);
COMPONENT demux
GENERIC(
select_width, line_width : positive;
default_out : std_logic
);
PORT(
INPUT : IN std_logic_vector(line_width-1 DOWNTO 0);
SEL : IN std_logic_vector(select_width-1 DOWNTO 0);
FLOOD : IN std_logic; -- FLOOD=1 causes all bits of OUTPUT to be set to 1
OUTPUT : OUT std_logic_vector(2**select_width*line_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : demux USE ENTITY WORK.demux(recursive);
BEGIN
demux1to2: IF select_width=1 GENERATE
OUTPUT(line_width-1 DOWNTO 0) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="0" ELSE (OTHERS => default_out);
OUTPUT(2*line_width-1 DOWNTO line_width) <= (OTHERS => '1') WHEN FLOOD='1'
ELSE INPUT WHEN SEL="1" ELSE (OTHERS => default_out);
END GENERATE;
demux1toN: IF select_width>1 GENERATE
subdemux_0: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_0_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**(select_width-1)*line_width-1 DOWNTO 0));
subdemux_1: demux
GENERIC MAP(select_width => select_width-1, line_width => line_width,
default_out => default_out)
PORT MAP(INPUT => subdemux_1_IN,
SEL => SEL(select_width-2 DOWNTO 0),
FLOOD => FLOOD,
OUTPUT => OUTPUT(2**select_width*line_width-1
DOWNTO 2**(select_width-1)*line_width));
subdemux_0_IN <= INPUT WHEN SEL(select_width-1)='0'
ELSE (OTHERS => default_out);
subdemux_1_IN <= INPUT WHEN SEL(select_width-1)='1'
ELSE (OTHERS => default_out);
END GENERATE;
END recursive;
|
bsd-3-clause
|
c2a94d9f469ff8ebe9a0f235092d87fe
| 0.591578 | 3.565598 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sim_3/new/test3.vhd
| 1 | 3,300 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity test3 is
end test3;
architecture Behavioral of test3 is
component Ram is
Port
(
clk : in std_logic;
re : in std_logic_vector (1 downto 0);
we : in std_logic_vector (1 downto 0);
addr : in integer range 0 to 16#1FFFF#;
dat_r : out std_logic_vector (15 downto 0);
dat_w : in std_logic_vector (15 downto 0)
);
end component;
constant clk_period : time := 20 ns;
signal clk_1 : std_logic := '0';
signal clk_4 : std_logic := '0';
signal re : std_logic_vector (1 downto 0) := "00";
signal we : std_logic_vector (1 downto 0) := "00";
signal addr : integer range 0 to 16#1FFFF# := 0;
signal dat_r : std_logic_vector (15 downto 0) := (others => 'U');
signal dat_w : std_logic_vector (15 downto 0) := (others => 'U');
begin
ram0: Ram
port map (
clk => clk_4,
re => re,
we => we,
addr => addr,
dat_r => dat_r,
dat_w => dat_w
);
process
begin
clk_1 <= not clk_1;
clk_4 <= not clk_4;
wait for clk_period;
clk_4 <= not clk_4;
wait for clk_period;
clk_4 <= not clk_4;
wait for clk_period;
clk_4 <= not clk_4;
wait for clk_period;
clk_4 <= not clk_4;
wait for clk_period;
clk_4 <= not clk_4;
wait for clk_period;
end process;
process(clk_1)
variable i : integer range 0 to 12 := 1;
file outfile : text is out "out.txt"; --declare output file
variable outline : line; --line number declaration
begin
if rising_edge(clk_1) then
addr <= addr + 5;
dat_w(7 downto 0) <= conv_std_logic_vector(addr + (i * 8), 8);
dat_w(15 downto 8) <= conv_std_logic_vector((i * 8) - addr, 8);
if addr >= 25 then
addr <= 0;
case i is
when 0 =>
re <= "00";
we <= "01";
when 1 =>
re <= "01";
we <= "00";
when 2 =>
re <= "10";
we <= "00";
when 3 =>
re <= "11";
we <= "00";
when 4 =>
re <= "00";
we <= "10";
when 5 =>
re <= "01";
we <= "00";
when 6 =>
re <= "10";
we <= "00";
when 7 =>
re <= "11";
we <= "00";
when 8 =>
re <= "00";
we <= "11";
when 9 =>
re <= "01";
we <= "00";
when 10 =>
re <= "10";
we <= "00";
when 11 =>
re <= "11";
we <= "00";
when others =>
re <= "UU";
we <= "UU";
end case;
i := i + 1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
e06af8a30fd1881520960ac1e0c7d58d
| 0.405758 | 3.767123 | false | false | false | false |
ayaovi/yoda
|
nexys4_DDR_projects/Music_Looper_Demo/src/hdl/Ram2Ddr.vhd
| 1 | 23,714 |
-------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2014, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : ram2ddr.vhd
-- MODULE NAME : RAM to DDR2 Interface Converter with internal XADC
-- instantiation
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2014-02-04 Mihaita Nagy Created
-- 1.1 2014-04-04 Mihaita Nagy Fixed double registering write bug
-------------------------------------------------------------------------------
-- DESCRIPTION : This module implements a simple Static RAM to DDR2 interface
-- converter designed to be used with Digilent Nexys4-DDR board
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity Ram2Ddr is
port (
-- Common
clk_200MHz_i : in std_logic; -- 200 MHz system clock
rst_i : in std_logic; -- active high system reset
device_temp_i : in std_logic_vector(11 downto 0);
-- RAM interface
ram_a : in std_logic_vector(26 downto 0);
ram_dq_i : in std_logic_vector(15 downto 0);
ram_dq_o : out std_logic_vector(15 downto 0);
ram_cen : in std_logic;
ram_oen : in std_logic;
ram_wen : in std_logic;
ram_ub : in std_logic;
ram_lb : in std_logic;
-- DDR2 interface
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end Ram2Ddr;
architecture Behavioral of Ram2Ddr is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component mig_7series_0
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
sys_clk_i : in std_logic;
sys_rst : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(127 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(15 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(127 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_sr_active : out std_logic;
app_ref_req : in std_logic;
app_ref_ack : out std_logic;
app_zq_req : in std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
device_temp_i : in std_logic_vector(11 downto 0);
init_calib_complete : out std_logic);
end component;
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
-- FSM
type state_type is (stIdle, stPreset, stSendData, stSetCmdRd, stSetCmdWr,
stWaitCen);
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
-- ddr commands
constant CMD_WRITE : std_logic_vector(2 downto 0) := "000";
constant CMD_READ : std_logic_vector(2 downto 0) := "001";
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
-- state machine
signal cState, nState : state_type;
-- global signals
signal mem_ui_clk : std_logic;
signal mem_ui_rst : std_logic;
signal rst : std_logic;
signal rstn : std_logic;
signal sreg : std_logic_vector(1 downto 0);
-- ram internal signals
signal ram_a_int : std_logic_vector(26 downto 0);
signal ram_dq_i_int : std_logic_vector(15 downto 0);
signal ram_cen_int : std_logic;
signal ram_oen_int : std_logic;
signal ram_wen_int : std_logic;
signal ram_ub_int : std_logic;
signal ram_lb_int : std_logic;
-- ddr user interface signals
signal mem_addr : std_logic_vector(26 downto 0); -- address for current request
signal mem_cmd : std_logic_vector(2 downto 0); -- command for current request
signal mem_en : std_logic; -- active-high strobe for 'cmd' and 'addr'
signal mem_rdy : std_logic;
signal mem_wdf_rdy : std_logic; -- write data FIFO is ready to receive data (wdf_rdy = 1 & wdf_wren = 1)
signal mem_wdf_data : std_logic_vector(127 downto 0);
signal mem_wdf_end : std_logic; -- active-high last 'wdf_data'
signal mem_wdf_mask : std_logic_vector(15 downto 0);
signal mem_wdf_wren : std_logic;
signal mem_rd_data : std_logic_vector(127 downto 0);
signal mem_rd_data_end : std_logic; -- active-high last 'rd_data'
signal mem_rd_data_valid : std_logic; -- active-high 'rd_data' valid
signal calib_complete : std_logic; -- active-high calibration complete
------------------------------------------------------------------------
-- Signal attributes (debugging)
------------------------------------------------------------------------
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of cState : signal is "GRAY";
attribute ASYNC_REG : string;
attribute ASYNC_REG of sreg : signal is "TRUE";
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Registering the active-low reset for the MIG component
------------------------------------------------------------------------
RSTSYNC: process(clk_200MHz_i)
begin
if rising_edge(clk_200MHz_i) then
sreg <= sreg(0) & rst_i;
rstn <= not sreg(1);
end if;
end process RSTSYNC;
------------------------------------------------------------------------
-- DDR controller instance
------------------------------------------------------------------------
Inst_DDR: mig_7series_0
port map (
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Inputs
sys_clk_i => clk_200MHz_i,
sys_rst => rstn,
-- user interface signals
app_addr => mem_addr,
app_cmd => mem_cmd,
app_en => mem_en,
app_wdf_data => mem_wdf_data,
app_wdf_end => mem_wdf_end,
app_wdf_mask => mem_wdf_mask,
app_wdf_wren => mem_wdf_wren,
app_rd_data => mem_rd_data,
app_rd_data_end => mem_rd_data_end,
app_rd_data_valid => mem_rd_data_valid,
app_rdy => mem_rdy,
app_wdf_rdy => mem_wdf_rdy,
app_sr_req => '0',
app_sr_active => open,
app_ref_req => '0',
app_ref_ack => open,
app_zq_req => '0',
app_zq_ack => open,
ui_clk => mem_ui_clk,
ui_clk_sync_rst => mem_ui_rst,
device_temp_i => device_temp_i,
init_calib_complete => calib_complete);
------------------------------------------------------------------------
-- Registering all inputs of the state machine to 'mem_ui_clk' domain
------------------------------------------------------------------------
REG_IN: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
ram_a_int <= ram_a;
ram_dq_i_int <= ram_dq_i;
ram_cen_int <= ram_cen;
ram_oen_int <= ram_oen;
ram_wen_int <= ram_wen;
ram_ub_int <= ram_ub;
ram_lb_int <= ram_lb;
end if;
end process REG_IN;
------------------------------------------------------------------------
-- State Machine
------------------------------------------------------------------------
-- Register states
SYNC_PROCESS: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if mem_ui_rst = '1' then
cState <= stIdle;
else
cState <= nState;
end if;
end if;
end process SYNC_PROCESS;
-- Next state logic
NEXT_STATE_DECODE: process(cState, calib_complete, ram_cen_int,
mem_rdy, mem_wdf_rdy, ram_wen_int, ram_oen_int)
begin
nState <= cState;
case(cState) is
-- If calibration is done successfully and CEN is
-- deasserted then start a new transaction
when stIdle =>
if ram_cen_int = '0' and
calib_complete = '1' then
nState <= stPreset;
end if;
-- In this state we store the address and data to
-- be written or the address to read from. We need
-- this additional state to make sure that all input
-- transitions are fully settled and registered
when stPreset =>
if ram_wen_int = '0' then
nState <= stSendData;
elsif ram_oen_int = '0' then
nState <= stSetCmdRd;
end if;
-- In a write transaction the data it written first
-- giving higher priority to 'mem_wdf_rdy' frag over
-- 'mem_rdy'
when stSendData =>
if mem_wdf_rdy = '1' then
nState <= stSetCmdWr;
end if;
-- Sending the read command and wait for the 'mem_rdy'
-- frag to be asserted (in case it's not)
when stSetCmdRd =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- Sending the write command after the data has been
-- written to the controller FIFO and wait ro the
-- 'mem_rdy' frag to be asserted (in case it's not)
when stSetCmdWr =>
if mem_rdy = '1' then
nState <= stWaitCen;
end if;
-- After sending all the control signals and data, we
-- wait for the external CEN to signal transaction
-- end
when stWaitCen =>
if ram_cen_int = '1' then
nState <= stIdle;
end if;
when others => nState <= stIdle;
end case;
end process;
------------------------------------------------------------------------
-- Generating the FIFO control and command signals according to the
-- current state of the FSM
------------------------------------------------------------------------
MEM_WR_CTL: process(cState)
begin
if cState = stSendData then
mem_wdf_wren <= '1';
mem_wdf_end <= '1';
else
mem_wdf_wren <= '0';
mem_wdf_end <= '0';
end if;
end process MEM_WR_CTL;
MEM_CTL: process(cState)
begin
if cState = stSetCmdRd then
mem_en <= '1';
mem_cmd <= CMD_READ;
elsif cState = stSetCmdWr then
mem_en <= '1';
mem_cmd <= CMD_WRITE;
else
mem_en <= '0';
mem_cmd <= (others => '0');
end if;
end process MEM_CTL;
------------------------------------------------------------------------
-- Decoding the least significant 3 bits of the address and creating
-- accordingly the 'mem_wdf_mask'
------------------------------------------------------------------------
WR_DATA_MSK: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
case(ram_a_int(2 downto 0)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111111101";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111110";
else -- 16-bit
mem_wdf_mask <= "1111111111111100";
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111110111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111111011";
else -- 16-bit
mem_wdf_mask <= "1111111111110011";
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111111011111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111111101111";
else -- 16-bit
mem_wdf_mask <= "1111111111001111";
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111111101111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111110111111";
else -- 16-bit
mem_wdf_mask <= "1111111100111111";
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111110111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111111011111111";
else -- 16-bit
mem_wdf_mask <= "1111110011111111";
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1111011111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1111101111111111";
else -- 16-bit
mem_wdf_mask <= "1111001111111111";
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "1101111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1110111111111111";
else -- 16-bit
mem_wdf_mask <= "1100111111111111";
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
mem_wdf_mask <= "0111111111111111";
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
mem_wdf_mask <= "1011111111111111";
else -- 16-bit
mem_wdf_mask <= "0011111111111111";
end if;
when others => null;
end case;
end if;
end if;
end process WR_DATA_MSK;
------------------------------------------------------------------------
-- Registering write data and read/write address
------------------------------------------------------------------------
WR_DATA_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_wdf_data <= ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int & ram_dq_i_int &
ram_dq_i_int & ram_dq_i_int;
end if;
end if;
end process WR_DATA_ADDR;
WR_ADDR: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stPreset then
mem_addr <= ram_a_int(26 downto 3) & "000";
end if;
end if;
end process WR_ADDR;
------------------------------------------------------------------------
-- Mask and output the read data from the FIFO
------------------------------------------------------------------------
RD_DATA: process(mem_ui_clk)
begin
if rising_edge(mem_ui_clk) then
if cState = stWaitCen and mem_rd_data_valid = '1' and
mem_rd_data_end = '1' then
case(ram_a_int(2 downto 0)) is
when "000" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(15 downto 8) &
mem_rd_data(15 downto 8);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(7 downto 0) &
mem_rd_data(7 downto 0);
else -- 16-bit
ram_dq_o <= mem_rd_data(15 downto 0);
end if;
when "001" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(31 downto 24) &
mem_rd_data(31 downto 24);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(23 downto 16) &
mem_rd_data(23 downto 16);
else -- 16-bit
ram_dq_o <= mem_rd_data(31 downto 16);
end if;
when "010" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(47 downto 40) &
mem_rd_data(47 downto 40);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(39 downto 32) &
mem_rd_data(39 downto 32);
else -- 16-bit
ram_dq_o <= mem_rd_data(47 downto 32);
end if;
when "011" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(63 downto 56) &
mem_rd_data(63 downto 56);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(55 downto 48) &
mem_rd_data(55 downto 48);
else -- 16-bit
ram_dq_o <= mem_rd_data(63 downto 48);
end if;
when "100" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(79 downto 72) &
mem_rd_data(79 downto 72);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(71 downto 64) &
mem_rd_data(71 downto 64);
else -- 16-bit
ram_dq_o <= mem_rd_data(79 downto 64);
end if;
when "101" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(95 downto 88) &
mem_rd_data(95 downto 88);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(87 downto 80) &
mem_rd_data(87 downto 80);
else -- 16-bit
ram_dq_o <= mem_rd_data(95 downto 80);
end if;
when "110" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(111 downto 104) &
mem_rd_data(111 downto 104);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(103 downto 96) &
mem_rd_data(103 downto 96);
else -- 16-bit
ram_dq_o <= mem_rd_data(111 downto 96);
end if;
when "111" =>
if ram_ub_int = '0' and ram_lb_int = '1' then -- UB
ram_dq_o <= mem_rd_data(127 downto 120) &
mem_rd_data(127 downto 120);
elsif ram_ub_int = '1' and ram_lb_int = '0' then -- LB
ram_dq_o <= mem_rd_data(119 downto 112) &
mem_rd_data(119 downto 112);
else -- 16-bit
ram_dq_o <= mem_rd_data(127 downto 112);
end if;
when others => null;
end case;
end if;
end if;
end process RD_DATA;
end Behavioral;
|
gpl-3.0
|
90efd5b7366d05d0b44ce174c70e95bb
| 0.419752 | 4.126327 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/user_processes/pseudo_random.vhd
| 3 | 2,013 |
----------------------------------------------------------------------------------
-- Company: University of Paderborn
-- Engineer: Markus Happe
--
-- Create Date: 11:55:17 02/11/2008
-- Design Name:
-- Module Name: pseudo_random - Behavioral
-- Project Name: Parallelization and HW/SW Codesign of Particle Filters
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-----------------------------------------------------------------
--
-- PSEUDO RANDOM NUMBER GENERATOR
--
-- source: 'VHDL - Eine Einfuehrung' by P. Molitor and J. Ritter,
-- Pearson Studium, 2004, Munich
--
------------------------------------------------------------------
entity pseudo_random is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
load : in STD_LOGIC;
seed : in STD_LOGIC_VECTOR(31 downto 0);
pseudoR : out STD_LOGIC_VECTOR(31 downto 0));
begin
-- synthesis off
assert seed /= X"ffffffff"
report "pseudoRandom: Startwert darf nicht nur aus Einsen bestehen"
severity failure;
-- synthesis on
end pseudo_random;
architecture Structure of pseudo_random is
signal sreg : STD_LOGIC_VECTOR(31 downto 0);
begin
pseudoRandomNumbers: process(reset, clk)
begin
if reset = '1' then
sreg<=(others=>'0');
elsif rising_edge(clk) then
if enable='1' then
if load='1' then
sreg<=seed;
else
sreg<=(sreg(1) xnor sreg(0)) & sreg(31 downto 1);
end if;
end if;
end if;
end process;
pseudoR <= sreg;
end Structure;
|
gpl-3.0
|
09fc5b7317cda2199f9ec2952cf675bd
| 0.5539 | 3.871154 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/dcr_timebase_v1_00_b/hdl/vhdl/dcr_timebase.vhd
| 9 | 6,380 |
--
-- \file dcr_timebase.vhd
--
-- Timebase pcore for measuring latencies between HW and SW
--
-- register at offset 0 is timebase. read- and writeable
-- reguster at offset 1 is control register. not yet used.
--
-- \author Enno Luebbers <[email protected]>
-- \date 06.05.2008
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_v2_00_a;
--use proc_common_v2_00_a.proc_common_pkg.all;
--use proc_common_v2_00_a.ipif_pkg.all;
--library opb_ipif_v3_01_c;
--use opb_ipif_v3_01_c.all;
entity dcr_timebase is
generic (
C_DCR_BASEADDR : std_logic_vector := "1111111111";
C_DCR_HIGHADDR : std_logic_vector := "0000000000";
C_DCR_AWIDTH : integer := 10;
C_DCR_DWIDTH : integer := 32
);
port (
i_clk : in std_logic;
i_reset : in std_logic;
o_dcrAck : out std_logic;
o_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
i_dcrDBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
i_dcrRead : in std_logic;
i_dcrWrite : in std_logic;
o_timeBase : out std_logic_vector(0 to C_DCR_DWIDTH-1);
o_irq : out std_logic
);
end dcr_timebase;
architecture implementation of dcr_timebase is
constant C_NUM_REGS : natural := 2;
signal dcrDBus : std_logic_vector( 0 to C_DCR_DWIDTH-1 );
signal dcrAck : std_logic;
signal dcrAddrHit : std_logic;
signal regAddr : std_logic_vector(0 to 0); -- FIXME: hardcoded
signal readCE : std_logic_vector(0 to C_NUM_REGS-1);
signal writeCE : std_logic_vector(0 to C_NUM_REGS-1);
signal slv_reg0 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal timebase : std_logic_vector(0 to C_DCR_DWIDTH-1) := (others => '0');
signal set_timebase : std_logic := '0'; -- loads slv_reg0 into timebase when '1'
begin
-- generate outputs
o_dcrAck <= dcrAck;
o_dcrDBus <= dcrDBus;
-- 2 registers = 1 LSBs FIXME: hardcoded. Use log2 instead!
dcrAddrHit <= '1' when i_dcrABus(0 to C_DCR_AWIDTH-2) = C_DCR_BASEADDR(0 to C_DCR_AWIDTH-2)
else '0';
regAddr <= i_dcrABus(C_DCR_AWIDTH-1 to C_DCR_AWIDTH-1);
--
-- decode read and write accesses into chip enable signals
-- ASYNCHRONOUS
--
ce_gen : process(dcrAddrHit, i_dcrRead, i_dcrWrite,
regAddr)
begin
-- clear all chip enables by default
for i in 0 to C_NUM_REGS-1 loop
readCE(i) <= '0';
writeCE(i) <= '0';
end loop;
-- decode register address and set
-- corresponding chip enable signal
if dcrAddrHit = '1' then
if i_dcrRead = '1' then
readCE(TO_INTEGER(unsigned(regAddr))) <= '1';
elsif i_dcrWrite = '1' then
writeCE(TO_INTEGER(unsigned(regAddr))) <= '1';
end if;
end if;
end process;
--
-- generate DCR slave acknowledge signal
-- SYNCHRONOUS
--
gen_ack_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
dcrAck <= '0';
elsif rising_edge(i_clk) then
dcrAck <= ( i_dcrRead or i_dcrWrite ) and
dcrAddrHit;
end if;
end process;
--
-- update slave registers on write access
-- SYNCHRONOUS
--
reg_write_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
set_timebase <= '0';
elsif rising_edge(i_clk) then
set_timebase <= '0';
if dcrAck = '0' then -- register values only ONCE per write select
case writeCE is
when "01" =>
slv_reg0 <= i_dcrDBus;
set_timebase <= '1';
when "10" =>
slv_reg1 <= i_dcrDBus;
when others => null;
end case;
end if;
end if;
end process;
--
-- output slave registers on data bus on read access
-- ASYNCHRONOUS
--
reg_read_proc: process(readCE, timebase, slv_reg1,
i_dcrDBus)
begin
dcrDBus <= i_dcrDBus;
case readCE is
when "01" =>
dcrDBus <= timebase;
when "10" =>
dcrDBus <= slv_reg1;
when others =>
dcrDBus <= i_dcrDBus;
end case;
end process;
--
-- timebase register implementation
--
timebase_proc : process(i_clk, i_reset)
begin
if i_reset = '1' then
timebase <= (others => '0');
elsif rising_edge(i_clk) then
if set_timebase = '1' then
timebase <= slv_reg0;
else
timebase <= STD_LOGIC_VECTOR(UNSIGNED(timebase) + 1);
end if;
end if;
end process;
o_timeBase <= timebase;
o_irq <= '1' when timebase = X"FFFFFFFF" else '0';
end implementation;
|
gpl-3.0
|
f1640eeb14e0afbcb7baf90609ccaf09
| 0.537461 | 3.83644 | false | false | false | false |
luebbers/reconos
|
demos/particle_filter_framework/hw/src/user_processes/uf_likelihood.vhd
| 1 | 13,359 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.MATH_REAL.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : L I K E L I H O O D
--
--
-- One observation and the reference data are loaded into the
-- local RAM by the framework. The start addresses of this
-- observations will be set as input from the Framework.
--
-- The user of the framework knows how a observation is defined.
-- The user defines how to calculate the likelihood between the
-- observation and the reference data.
--
-- If the likelihood is calculated, the finished signal has to
-- be set to '1' and the likelihood value has to be set as ouput.
--
------------------------------------------------------------------------------------
entity uf_likelihood is
generic (
C_TASK_BURST_AWIDTH : integer := 11;
C_TASK_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_TASK_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the likelihood user process
observation_loaded : in std_logic;
-- address of reference data
ref_data_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- address of observation
observation_address : in std_logic_vector(0 to C_TASK_BURST_AWIDTH-1);
-- size of one observation
observation_size : in integer;
-- if the likelihood is calculated, this signal has to be set to '1'
finished : out std_logic;
likelihood_value : out integer
);
end uf_likelihood;
architecture Behavioral of uf_likelihood is
component square_root_component
port (
x_in : in std_logic_VECTOR(31 downto 0);
nd : in std_logic;
x_out : out std_logic_VECTOR(16 downto 0);
rdy : out std_logic;
rfd : out std_logic;
clk : in std_logic;
ce : in std_logic);
end component;
-- GRANULARITY
constant GRANULARITY : integer := 16384;
-- type for likelihood look up table
type likelihood_function is array ( 0 to 128) of integer;
-- likelihood look up table
-- constant likelihood_values : likelihood_function := (
-- 1, 1, 1, 1, 1, 1, 2, 2, 2, 3,
-- 3, 3, 4, 5, 5, 6, 7, 8, 9, 10,
-- 12, 13, 15, 17, 20, 22, 25, 29, 33, 37,
-- 42, 48, 54, 61, 70, 79, 90, 102, 115, 130,
-- 148, 168, 190, 215, 244, 277, 314, 356, 403, 457,
-- 518, 586, 665, 753, 854, 967, 1096, 1242, 1408, 1595,
-- 1808, 2048, 2321, 2630, 2980, 3377, 3827, 4337, 4914, 5569,
-- 6310, 7150, 8103, 9181, 10404, 11789, 13359, 15138, 17154, 19438,
-- 22026, 24959, 28282, 32048, 36315, 41150, 46630, 52838, 59874, 67846,
-- 76879, 87116, 98715, 111859, 126753, 143630, 162754, 184425, 208981, 236806,
-- 268337, 304065, 344551, 390428, 442413, 501320, 568070, 643707, 729416, 826537,
-- 936589, 1061294, 1202604, 1362729, 1544174, 1749778, 1982759, 2246760, 2545913, 2884897,
-- 3269017, 3704281, 4197501, 4756392, 5389698, 6107328, 6920509, 7841965, 8886110);
constant likelihood_values : likelihood_function := (
1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
2, 2, 2, 2, 3, 3, 3, 4, 4, 4,
5, 5, 6, 6, 7, 8, 8, 9, 10, 11,
12, 13, 14, 15, 17, 18, 20, 21, 23, 25,
28, 30, 33, 35, 39, 42, 46, 50, 54, 59,
64, 70, 76, 82, 90, 97, 106, 115, 125, 136,
148, 161, 175, 190, 207, 225, 244, 265, 289, 314,
341, 371, 403, 438, 476, 518, 563, 611, 665, 722,
785, 854, 928, 1008, 1096, 1191, 1295, 1408, 1530, 1663,
1808, 1965, 2135, 2321, 2523, 2742, 2980, 3240, 3521, 3827,
4160, 4521, 4914, 5341, 5806, 6310, 6859, 7455, 8103, 8807,
9572, 10404, 11308, 12291, 13359, 14520, 15782, 17154, 18644, 20265,
22026, 23940, 26021, 28282, 30740, 33411, 36315, 39471, 42901 );
-- LAMBDA
--constant LAMBDA : integer := 16.0;
-- local RAM addresses
signal current_ref_data_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
signal current_observation_address : std_logic_vector(0 to C_TASK_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- signals for histogram values
signal ref_value : integer := 0;
signal observation_value : integer := 0;
-- sum of all values
signal sum : integer := 0;
-- root of sum
signal sum_root : integer := 0;
--signal pow : integer := 0;
signal sum_update : integer := 0;
signal likelihood : integer := 0;
-- states
type t_state is (STATE_INIT, STATE_LOAD_VALUES_DECISION, STATE_LOAD_VALUES_1,
STATE_LOAD_VALUES_2, STATE_LOAD_HIST_1, STATE_LOAD_HIST_2,
STATE_CALCULATE_SUM_UPDATE_1, STATE_CALCULATE_SUM_UPDATE_2,
STATE_CALCULATE_SUM_UPDATE_3, STATE_CALCULATE_SUM_UPDATE_4,
STATE_CALCULATE_SUM_UPDATE_5, STATE_CALCULATE_SUM_UPDATE_6,
STATE_UPDATE_SUM, STATE_CALCULATE_LIKELIHOOD_1,
STATE_CALCULATE_LIKELIHOOD_2, STATE_CALCULATE_LIKELIHOOD_3,
STATE_CALCULATE_LIKELIHOOD_4, STATE_CALCULATE_LIKELIHOOD_5,
STATE_CALCULATE_LIKELIHOOD_6, STATE_CALCULATE_LIKELIHOOD_7,
STATE_FINISH);
-- current state
signal state : t_state := STATE_INIT;
-- signals for square root component
signal x_in2 : natural := 0;
signal x_in3 : natural := 0;
signal x_in : std_logic_vector(31 downto 0) := (others => '0');
signal x_out : std_logic_vector(16 downto 0) := (others => '0');
signal x_out2: natural := 0;
signal x_out3: natural := 0;
signal nd : std_logic := '0';
signal rdy : std_logic := '1';
signal rfd : std_logic := '1';
signal ce : std_logic := '1';
begin
--! square root calculation
square_root: square_root_component
port map (x_in => x_in, nd => nd, x_out => x_out,
rdy => rdy, rfd => rfd, clk => clk, ce => ce);
-- burst ram interface
o_RAMWE <= '0';
o_RAMClk <= clk;
--
-- Likelihood calculation
--
-- 0) i = 0;
-- sum = 0.0;
--
-- 1) if ( i < 110 ) then
-- go to step 2
-- else
-- go to step 6
-- end if
--
-- 2) hist1 = reference_histogram[i]
--
-- 3) hist2 = observation_histogram[i]
--
-- 4) sum_update = sqrt ((hist1 * hist2) / GRANULARITY)
--
-- 5) sum += sum_update
-- i++
-- go to step 1
--
-- 6) likelihood = exp (- LAMBDA * (1.0 - sum))
--
ce <= enable;
state_proc : process(clk, reset)
begin
if (reset = '1') then
state <= STATE_INIT;
finished <= '0';
elsif rising_edge(clk) then
if init = '1' then
state <= STATE_INIT;
finished <= '0';
o_RAMData <= (others=>'0');
o_RAMAddr <= (others => '0');
elsif enable = '1' then
case state is
--! init data
when STATE_INIT =>
counter <= 0;
finished <= '0';
current_ref_data_address <= ref_data_address;
--sum <= 0.0;
sum <= 0;
current_observation_address <= observation_address;
if (observation_loaded = '1') then
state <= STATE_LOAD_VALUES_DECISION;
end if;
--! if not all histogram values are loaded and calculated, then do it.
-- Else calculate likelihood
when STATE_LOAD_VALUES_DECISION =>
if (counter < observation_size) then
state <= STATE_LOAD_VALUES_1;
else
state <= STATE_CALCULATE_LIKELIHOOD_1;
end if;
--! load histogram value 1 of 2
when STATE_LOAD_VALUES_1 =>
o_RAMAddr <= current_ref_data_address;
state <= STATE_LOAD_VALUES_2;
--! load histogram value 2 of 2
when STATE_LOAD_VALUES_2 =>
o_RAMAddr <= current_observation_address;
state <= STATE_LOAD_HIST_1;
--! load reference histogram value
when STATE_LOAD_HIST_1 =>
ref_value <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_HIST_2;
--! load observation histogram value
when STATE_LOAD_HIST_2 =>
observation_value <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_CALCULATE_SUM_UPDATE_1;
--! calculate sum update (1 of 6): product = ref_hist * observation_hist
when STATE_CALCULATE_SUM_UPDATE_1 =>
--sum_update <= ref_value * observation_value;
--state <= STATE_UPDATE_SUM;
--! TODO: CHANGE BACK (1 of 1)
ref_value <= ref_value * observation_value;
state <= STATE_CALCULATE_SUM_UPDATE_2;
--! calculate sum update (2 of 6): sum_update = product
when STATE_CALCULATE_SUM_UPDATE_2 =>
--sum_update <= real(ref_value);
--sum_update <= ref_value;
x_in2 <= ref_value;
--if (rfd = '1') then
state <= STATE_CALCULATE_SUM_UPDATE_3;
--end if;
--! calculate sum update (3 of 6): get sqrt (1/3)
when STATE_CALCULATE_SUM_UPDATE_3 =>
--sum_update <= sum_update / GRANULARITY;
--sum_update <= sum_update / 512;
--state <= STATE_UPDATE_SUM;
x_in <= STD_LOGIC_VECTOR(TO_UNSIGNED(x_in2, 32));
nd <= '1';
state <= STATE_CALCULATE_SUM_UPDATE_4;
--! calculate sum update (4 of 6): get sqrt (2/3)
when STATE_CALCULATE_SUM_UPDATE_4 =>
--sum_update <= sqrt(sum_update);
nd <= '0';
if (rdy = '1') then
state <= STATE_CALCULATE_SUM_UPDATE_5;
end if;
--! calculate sum update (5 of 6): get sqrt (3/3)
when STATE_CALCULATE_SUM_UPDATE_5 =>
--sum_update <= sqrt(sum_update);
x_out2 <= TO_INTEGER(UNSIGNED(x_out));
state <= STATE_CALCULATE_SUM_UPDATE_6;
--! calculate sum update (6 of 6): sum_update = sqrt (ref_value * observation_value)
when STATE_CALCULATE_SUM_UPDATE_6 =>
--sum_update <= sqrt(sum_update);
-- needs correction
--sum_update <= ref_value;
-- CHANGE BACK (5 of 6) !!!
sum_update <= x_out2;
state <= STATE_UPDATE_SUM;
--! update sum (+= sum_update) and update counter and current addresses
when STATE_UPDATE_SUM =>
--sum <= sum + sum_update;
sum <= sum + sum_update;
counter <= counter + 1;
current_ref_data_address <= current_ref_data_address + 1;
current_observation_address <= current_observation_address + 1;
state <= STATE_LOAD_VALUES_DECISION;
--! calculate likelihood (1 of 7):
when STATE_CALCULATE_LIKELIHOOD_1 =>
x_in3 <= sum;
--pow <= sum / 2048;
--CHANGE BACK (6 of 6) !!!
--pow <= sum / 32;
state <= STATE_CALCULATE_LIKELIHOOD_2;
--! calculate likelihood (2 of 7):
when STATE_CALCULATE_LIKELIHOOD_2 =>
-------likelihood <= - LAMBDA * likelihood;
x_in <= STD_LOGIC_VECTOR(TO_UNSIGNED(x_in3, 32));
nd <= '1';
-- if (pow > 20) then
-- pow <= 20;
-- elsif (pow < 0) then
-- pow <= 0;
-- end if;
-- likelihood <= 1;
state <= STATE_CALCULATE_LIKELIHOOD_3;
--! calculate likelihood (3 of 7):
when STATE_CALCULATE_LIKELIHOOD_3 =>
nd <= '0';
if (rdy = '1') then
state <= STATE_CALCULATE_LIKELIHOOD_4;
end if;
-- if (pow > 0) then
--
-- likelihood <= likelihood * 3;
-- pow <= pow - 1;
-- else
--
-- state <= STATE_FINISH;
-- end if;
--likelihood <= exp(likelihood);
--likelihood <= 3**(likelihood/2048);
--state <= STATE_FINISH;
--! calculate likelihood (4 of 7):
when STATE_CALCULATE_LIKELIHOOD_4 =>
x_out3 <= TO_INTEGER(UNSIGNED(x_out));
state <= STATE_CALCULATE_LIKELIHOOD_5;
--! calculate likelihood (5 of 7):
when STATE_CALCULATE_LIKELIHOOD_5 =>
sum_root <= x_out3;
state <= STATE_CALCULATE_LIKELIHOOD_6;
--! calculate likelihood (6 of 7):
when STATE_CALCULATE_LIKELIHOOD_6 =>
if (sum_root > 128) then
sum_root <= 128;
elsif (sum_root < 0) then
sum_root <= 0;
end if;
state <= STATE_CALCULATE_LIKELIHOOD_7;
--! calculate likelihood (7 of 7):
when STATE_CALCULATE_LIKELIHOOD_7 =>
likelihood <= likelihood_values(sum_root);
state <= STATE_FINISH;
--! write finished signal and likelihood value
when STATE_FINISH =>
finished <= '1';
--likelihood_value <= integer(GRANULARITY * likelihood);
likelihood_value <= likelihood;
--likelihood_value <= 12;
if (observation_loaded = '1') then
state <= STATE_INIT;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
2e55dc061a65004e78e18357f63bf99d
| 0.557452 | 3.440381 | false | false | false | false |
steveicarus/iverilog
|
ivtest/ivltests/br943_944.vhd
| 3 | 532 |
library ieee;
use ieee.std_logic_1164.all;
entity e is
port (
clk : in std_logic;
rst : in std_logic;
q : out std_logic);
end e;
architecture a of e is
type t is (one, zero);
signal r : t;
begin
q <= '1' when r = one else '0';
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
r <= zero;
else
case r is
when zero => r <= one;
when others => r <= zero;
end case;
end if;
end if;
end process;
end a;
|
gpl-2.0
|
461d56f5860b6a8df27013af9f706c3e
| 0.5 | 3.204819 | false | false | false | false |
dries007/Basys3
|
VGA_text/VGA_text.srcs/sources_1/ip/FiFo/synth/FiFo.vhd
| 1 | 38,522 |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_0_1;
USE fifo_generator_v13_0_1.fifo_generator_v13_0_1;
ENTITY FiFo IS
PORT (
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END FiFo;
ARCHITECTURE FiFo_arch OF FiFo IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FiFo_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_0_1 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_0_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FiFo_arch: ARCHITECTURE IS "fifo_generator_v13_0_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FiFo_arch : ARCHITECTURE IS "FiFo,fifo_generator_v13_0_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FiFo_arch: ARCHITECTURE IS "FiFo,fifo_generator_v13_0_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=6,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=8,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=8,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=62,C_PROG_FULL_THRESH_NEGATE_VAL=61,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=6,C_RD_DEPTH=64,C_RD_FREQ=1,C_RD_PNTR_WIDTH=6,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=0,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=6,C_WR_DEPTH=64,C_WR_FREQ=1,C_WR_PNTR_WIDTH=6,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 8,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 8,
C_ENABLE_RLOCS => 0,
C_FAMILY => "artix7",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 0,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END FiFo_arch;
|
mit
|
eeef68ada1339db6344d1ea8977d15a3
| 0.627434 | 2.913478 | false | false | false | false |
whitef0x0/EECE353-Lab5
|
fsm_line.vhd
| 1 | 3,535 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY WORK;
USE WORK.ALL;
ENTITY fsm_line IS
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
clr_xin : IN STD_LOGIC_VECTOR(7 downto 0);
clr_yin : IN STD_LOGIC_VECTOR(6 downto 0);
draw : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, plot, initl, drawl : OUT STD_LOGIC;
colour_in : IN STD_LOGIC_VECTOR(2 downto 0);
colour_out : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
);
END fsm_line;
ARCHITECTURE behavioural OF fsm_line IS
TYPE state_types is (CLEAR_START, CLEAR_NEXTROW, CLEAR_NEXTCOL, LOAD_INPUT, INIT_LINE, DRAW_LINE, DONE_LINE);
SIGNAL curr_state, next_state : state_types := CLEAR_START;
BEGIN
PROCESS(clock, resetb)
--VARIABLE next_state : state_types;
BEGIN
IF (resetb = '0') THEN
curr_state <= CLEAR_START;
ELSIF rising_edge(clock) THEN
curr_state <= next_state;
END IF;
END PROCESS;
PROCESS(curr_state, next_state)
BEGIN
CASE curr_state IS
WHEN CLEAR_START =>
resetx <= '1';
resety <= '1';
incr_y <= '1';
incr_x <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
colour_out <= "000";
next_state <= CLEAR_NEXTCOL;
--Clear next row
WHEN CLEAR_NEXTROW =>
resetx <= '1';
resety <= '0';
incr_y <= '1';
incr_x <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= CLEAR_NEXTCOL;
--Clear next column
WHEN CLEAR_NEXTCOL =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '1';
INITL <= '0';
DRAWL <= '0';
PLOT <= '1';
IF (XDONE = '0') THEN
next_state <= CLEAR_NEXTCOL;
ELSIF (XDONE = '1' AND YDONE = '0') THEN
next_state <= CLEAR_NEXTROW;
ELSE
next_state <= LOAD_INPUT;
END IF;
when LOAD_INPUT =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
--When draw signal is low, initialize line with input
IF (draw = '0') THEN
x <= clr_xin;
y <= clr_yin;
--Clip input to within bounds
IF (unsigned(clr_xin) > 159) THEN
x <= "10011111";
END IF;
IF (unsigned(clr_yin) > 119) THEN
y <= "1110111";
END IF;
next_state <= INIT_LINE;
ELSE
next_state <= LOAD_INPUT;
END IF;
WHEN INIT_LINE =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '1';
DRAWL <= '0';
PLOT <= '0';
--colour <= "000";
colour <= colour_out;
next_state <= DRAW_LINE;
WHEN DRAW_LINE =>
colour <= sw(2 downto 0);
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '1';
PLOT <= '1';
--If line is done drawing, move to finished line (DONE_LINE) state
IF (LDONE = '1') THEN
next_state <= DONE_LINE;
ELSE
next_state <= DRAW_LINE;
END IF;
WHEN DONE_LINE =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= LOAD_INPUT;
WHEN others =>
resetx <= '0';
resety <= '0';
incr_y <= '0';
incr_x <= '0';
INITL <= '0';
DRAWL <= '0';
PLOT <= '0';
next_state <= DONE_LINE;
END CASE;
END PROCESS;
END behavioural;
|
mit
|
3f7a3e47a701446f847e18482efbac1a
| 0.521924 | 2.855412 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/client/fifo/rx_client_fifo_8.vhd
| 1 | 32,933 |
-------------------------------------------------------------------------------
-- Title : 8-bit Client-to-LocalLink Receiver FIFO
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : rx_client_fifo_8.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Description: This is the receive-side LocalLink FIFO for the example design
-- of the Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper core.
--
-- The FIFO is created from a Block RAM of size 4096
-- words by 8 bits per word.
--
-- Frame data received from the MAC receiver is written into the
-- FIFO on the wr_clk. An End Of Frame marker is written to the
-- BRAM parity bit on the last byte of data stored for a frame.
-- This acts as frame deliniation.
--
-- The rx_good_frame and rx_bad_frame signals are used to
-- qualify the frame. A frame for which rx_bad_frame was
-- asserted will cause the FIFO write address pointer to be
-- reset to the base address of that frame. In this way
-- the bad frame will be overwritten with the next received
-- frame and is therefore dropped from the FIFO.
--
-- Frames will also be dropped from the FIFO if an overflow occurs.
-- If there is not enough memory capacity in the FIFO to store the
-- whole of an incoming frame, the write address pointer will be
-- reset and the overflow signal asserted.
--
-- When there is at least one complete frame in the FIFO,
-- the 8-bit LocalLink read interface will be enabled allowing
-- data to be read from the fifo.
--
-- The FIFO has been designed to operate with different clocks
-- on the write and read sides. The read clock (LocalLink clock)
-- should always operate at an equal or faster frequency
-- than the write clock (client clock).
--
-- The FIFO is designed to work with a minimum frame length of 8 bytes.
--
-- The FIFO memory size can be increased by expanding the rd_addr
-- and wr_addr signal widths, to address further BRAMs.
--
-- Requirements :
-- * Minimum frame size of 8 bytes
-- * Spacing between good/bad frame flags is at least 32 clock cycles
-- * Wr clock is 125MHz downto 1.25MHz
-- * Rd clock is downto 20MHz
--
---------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity rx_client_fifo_8 is
port (
-- LocalLink Interface
rd_clk : in std_logic;
rd_sreset : in std_logic;
rd_data_out : out std_logic_vector(7 downto 0);
rd_sof_n : out std_logic;
rd_eof_n : out std_logic;
rd_src_rdy_n : out std_logic;
rd_dst_rdy_n : in std_logic;
-- Client Interface
wr_sreset : in std_logic;
wr_clk : in std_logic;
wr_enable : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_data_valid : in std_logic;
rx_good_frame : in std_logic;
rx_bad_frame : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
overflow : out std_logic
);
end rx_client_fifo_8;
architecture RTL of rx_client_fifo_8 is
signal GND : std_logic;
signal VCC : std_logic;
signal GND_BUS : std_logic_vector(31 downto 0);
-- Encode rd state machine
type rd_state_typ is (WAIT_s, QUEUE1_s, QUEUE2_s, QUEUE3_s, QUEUE_SOF_s, SOF_s, DATA_s, EOF_s);
signal rd_state : rd_state_typ;
signal rd_nxt_state : rd_state_typ;
-- Encode wr state machine
type wr_state_typ is (IDLE_s, FRAME_s, END_s, GF_s, BF_s, OVFLOW_s);
signal wr_state : wr_state_typ;
signal wr_nxt_state : wr_state_typ;
type data_pipe is array (0 to 1) of std_logic_vector(7 downto 0);
type cntl_pipe is array(0 to 1) of std_logic;
signal wr_en : std_logic;
signal wr_addr : unsigned(11 downto 0);
signal wr_addr_inc : std_logic;
signal wr_start_addr_load : std_logic;
signal wr_addr_reload : std_logic;
signal wr_start_addr : unsigned(11 downto 0);
signal wr_data_bram : std_logic_vector(7 downto 0);
signal wr_data_pipe : data_pipe;
signal wr_eof_bram : std_logic_vector(0 downto 0);
signal wr_dv_pipe : cntl_pipe;
signal wr_gf_pipe : cntl_pipe;
signal wr_bf_pipe : cntl_pipe;
signal frame_in_fifo : std_logic;
signal rd_addr : unsigned(11 downto 0);
signal rd_addr_inc : std_logic;
signal rd_addr_reload : std_logic;
signal rd_data_bram : std_logic_vector(7 downto 0);
signal rd_data_pipe : std_logic_vector(7 downto 0);
signal rd_en : std_logic;
signal rd_pull_frame : std_logic;
signal rd_eof : std_logic;
signal dob_bram : std_logic_vector(31 downto 0);
signal dopb_bram : std_logic_vector(3 downto 0);
signal wr_store_frame_tog : std_logic;
signal rd_store_frame_tog : std_logic;
signal rd_store_frame_sync : std_logic;
signal rd_store_frame_delay : std_logic;
signal rd_store_frame : std_logic;
signal rd_frames : std_logic_vector(8 downto 0);
signal wr_fifo_full : std_logic;
signal rd_addr_gray : unsigned(11 downto 0);
signal wr_rd_addr_gray_sync : unsigned(11 downto 0);
signal wr_rd_addr_gray : unsigned(11 downto 0);
signal wr_rd_addr : unsigned(11 downto 0);
signal wr_addr_diff : unsigned(11 downto 0);
signal wr_fifo_status : unsigned(3 downto 0);
signal rd_sof_n_int : std_logic := '1';
signal rd_eof_n_int : std_logic := '1';
signal rd_src_rdy_n_int : std_logic := '1';
signal rd_valid_pipe : std_logic_vector(2 downto 0);
-----------------------------------------------------------------------------
-- Attributes for FIFO simulation and synthesis
-----------------------------------------------------------------------------
-- ASYNC_REG attributes added to simulate actual behaviour under
-- asynchronous operating conditions.
attribute ASYNC_REG : string;
attribute ASYNC_REG of rd_store_frame_tog : signal is "TRUE";
attribute ASYNC_REG of wr_rd_addr_gray_sync : signal is "TRUE";
-----------------------------------------------------------------------------
-- Functions for gray code conversion
-----------------------------------------------------------------------------
function gray_to_bin (
gray : std_logic_vector)
return std_logic_vector is
variable binary : std_logic_vector(gray'range);
begin
for i in gray'high downto gray'low loop
if i = gray'high then
binary(i) := gray(i);
else
binary(i) := binary(i+1) xor gray(i);
end if;
end loop; -- i
return binary;
end gray_to_bin;
function bin_to_gray (
bin : std_logic_vector)
return std_logic_vector is
variable gray : std_logic_vector(bin'range);
begin
for i in bin'range loop
if i = bin'left then
gray(i) := bin(i);
else
gray(i) := bin(i+1) xor bin(i);
end if;
end loop; -- i
return gray;
end bin_to_gray;
-----------------------------------------------------------------------------
-- Begin FIFO architecture
-----------------------------------------------------------------------------
begin
GND <= '0';
VCC <= '1';
GND_BUS <= (others => '0');
-----------------------------------------------------------------------------
-- Read State machines and control
-----------------------------------------------------------------------------
-- LocalLink state machine
-- states are WAIT, QUEUE1, QUEUE2, QUEUE3, SOF, DATA, EOF
-- clock state to next state
clock_rds_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_state <= WAIT_s;
else
rd_state <= rd_nxt_state;
end if;
end if;
end process clock_rds_p;
rd_eof_n <= rd_eof_n_int;
-- decode next state, combinatorial
next_rds_p : process(rd_state, frame_in_fifo, rd_eof, rd_eof_n_int, rd_dst_rdy_n, rd_valid_pipe(1))
begin
case rd_state is
when WAIT_s =>
-- wait till there is a full frame in the fifo
-- then start to load the pipeline
if frame_in_fifo = '1' and rd_eof_n_int = '1' then
rd_nxt_state <= QUEUE1_s;
else
rd_nxt_state <= WAIT_s;
end if;
when QUEUE1_s =>
-- load the output pipeline
-- this takes three clocks
rd_nxt_state <= QUEUE2_s;
when QUEUE2_s =>
rd_nxt_state <= QUEUE3_s;
when QUEUE3_s =>
rd_nxt_state <= QUEUE_SOF_s;
when QUEUE_SOF_s =>
-- used to mark sof at end of queue
rd_nxt_state <= DATA_s; -- move straight to frame.
when SOF_s =>
-- used to mark sof when following straight from eof
if rd_dst_rdy_n = '0' then
rd_nxt_state <= DATA_s;
else
rd_nxt_state <= SOF_s;
end if;
when DATA_s =>
-- When the eof marker is detected from the BRAM output
-- move to EOF state
if rd_dst_rdy_n = '0' and rd_eof = '1' then
rd_nxt_state <= EOF_s;
else
rd_nxt_state <= DATA_s;
end if;
when EOF_s =>
-- hold in this state until dst rdy is low
-- and eof bit is accepted on interface
-- If there is a frame in the fifo, then the next frame
-- will already be queued into the pipe line so move straight
-- to sof state.
if rd_dst_rdy_n = '0' then
if rd_valid_pipe(1) = '1' then
rd_nxt_state <= SOF_s;
else
rd_nxt_state <= WAIT_s;
end if;
else
rd_nxt_state <= EOF_s;
end if;
when others =>
rd_nxt_state <= WAIT_s;
end case;
end process next_rds_p;
-- detect if frame in fifo was high 3 reads ago
-- this is used to ensure we only treat data in the pipeline as valid if
-- frame in fifo goes high at or before the eof of the current frame
-- It may be that there is valid data (i.e a partial packet has been written)
-- but until the end of that packet we do not know if it is a good packet
rd_valid_pipe_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if (rd_dst_rdy_n = '0') then
rd_valid_pipe <= rd_valid_pipe(1) &
rd_valid_pipe(0) &
frame_in_fifo;
end if;
end if;
end process rd_valid_pipe_p;
-- decode the output signals depending on current state.
-- decode sof signal.
rd_ll_sof_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_sof_n_int <= '1';
else
case rd_state is
when QUEUE_SOF_s =>
-- no need to wait for dst rdy to be low, as there is valid data
rd_sof_n_int <= '0';
when SOF_s =>
-- needed to wait till rd_dst_rdy is low to ensure eof signal has
-- been accepted onto the interface before asserting sof.
if rd_dst_rdy_n = '0' then
rd_sof_n_int <= '0';
end if;
when others =>
-- needed to wait till rd_dst_rdy is low to ensure sof signal has
-- been accepted onto the interface.
if rd_dst_rdy_n = '0' then
rd_sof_n_int <= '1';
end if;
end case;
end if;
end if;
end process rd_ll_sof_p;
-- assign to rd_sof_n output
rd_sof_n <= rd_sof_n_int;
-- decode eof signal
-- check init value of this reg is 1.
rd_ll_decode_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_eof_n_int <= '1';
elsif rd_dst_rdy_n = '0' then
-- needed to wait till rd_dst_rdy is low to ensure penultimate byte of frame has
-- been accepted onto the interface before asserting eof and that
-- eof is accepted before moving on
case rd_state is
when EOF_s =>
rd_eof_n_int <= '0';
when others =>
rd_eof_n_int <= '1';
end case;
end if;
end if;
end process rd_ll_decode_p;
-- register data outputs
-- no reset to allow for SRL target
rd_ll_data_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_en = '1' then
rd_data_out <= rd_data_pipe;
rd_data_pipe <= rd_data_bram;
end if;
end if;
end process rd_ll_data_p;
-- decode the output scr_rdy signal
-- want to remove the dependancy of src_rdy from dst rdy
-- check init value of this reg is '1'
rd_ll_src_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_src_rdy_n_int <= '1';
else
case rd_state is
when QUEUE_SOF_s =>
rd_src_rdy_n_int <= '0';
when SOF_s =>
rd_src_rdy_n_int <= '0';
when DATA_s =>
rd_src_rdy_n_int <= '0';
when EOF_s =>
rd_src_rdy_n_int <= '0';
when others =>
if rd_dst_rdy_n = '0' then
rd_src_rdy_n_int <= '1';
end if;
end case;
end if;
end if;
end process rd_ll_src_p;
-- assign to rd_src_rd_n output
rd_src_rdy_n <= rd_src_rdy_n_int;
-- decode internal control signals
-- rd_en is used to enable the BRAM read and load the output pipe
rd_en_p : process(rd_state, rd_dst_rdy_n)
begin
case rd_state is
when WAIT_s =>
rd_en <= '0';
when QUEUE1_s =>
rd_en <= '1';
when QUEUE2_s =>
rd_en <= '1';
when QUEUE3_s =>
rd_en <= '1';
when QUEUE_SOF_s =>
rd_en <= '1';
when others =>
rd_en <= not rd_dst_rdy_n;
end case;
end process rd_en_p;
-- rd_addr_inc is used to enable the BRAM read address to increment
rd_addr_inc <= rd_en;
-- When the current frame is output, if there is no frame in the fifo, then
-- the fifo must wait until a new frame is written in. This requires the read
-- address to be moved back to where the new frame will be written. The pipe
-- is then reloaded using the QUEUE states
rd_addr_reload <= '1' when rd_state = EOF_s and rd_nxt_state = WAIT_s else '0';
-- frame in fifo signal is required on the rd side, need to convert wr
-- address to rd clock domain.
-- Data is available if there is at least one frame stored in the FIFO.
p_rd_avail : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
frame_in_fifo <= '0';
else
if rd_frames /= (rd_frames'range => '0') then
frame_in_fifo <= '1';
else
frame_in_fifo <= '0';
end if;
end if;
end if;
end process p_rd_avail;
-- when a frame has been stored need to convert to rd clock domain for frame
-- count store.
p_sync_rd_store : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_store_frame_tog <= '0';
rd_store_frame_sync <= '0';
rd_store_frame_delay <= '0';
rd_store_frame <= '0';
else
rd_store_frame_tog <= wr_store_frame_tog;
rd_store_frame_sync <= rd_store_frame_tog;
rd_store_frame_delay <= rd_store_frame_sync;
-- edge detector
if (rd_store_frame_delay xor rd_store_frame_sync) = '1' then
rd_store_frame <= '1';
else
rd_store_frame <= '0';
end if;
end if;
end if;
end process p_sync_rd_store;
rd_pull_frame <= '1' when rd_state = SOF_s and rd_nxt_state /= SOF_s else
'1' when rd_state = QUEUE_SOF_s and rd_nxt_state /= QUEUE_SOF_s else
'0';
-- Up/Down counter to monitor the number of frames stored within the
-- the FIFO. Note:
-- * decrements at the beginning of a frame read cycle
-- * increments at the end of a frame write cycle
p_rd_frames : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_frames <= (others => '0');
else
-- A frame is written to the fifo in this cycle, and no frame is being
-- read out on the same cycle
if rd_store_frame = '1' and rd_pull_frame = '0' then
rd_frames <= rd_frames + 1;
-- A frame is being read out on this cycle and no frame is being
-- written on the same cycle
elsif rd_store_frame = '0' and rd_pull_frame = '1' then
rd_frames <= rd_frames - 1;
end if;
end if;
end if;
end process p_rd_frames;
-----------------------------------------------------------------------------
-- Write state machines and control
-----------------------------------------------------------------------------
-- write state machine
-- states are IDLE, FRAME, EOF, GF, BF, OVFLOW
-- clock state to next state
clock_wrs_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_state <= IDLE_s;
elsif wr_enable = '1' then
wr_state <= wr_nxt_state;
end if;
end if;
end process clock_wrs_p;
-- decode next state, combinatorial
next_wrs_p : process(wr_state, wr_dv_pipe(1), wr_gf_pipe(1), wr_bf_pipe(1), wr_eof_bram(0), wr_fifo_full)
begin
case wr_state is
when IDLE_s =>
-- there is data in the incoming pipeline when dv_pipe(1) goes high
if wr_dv_pipe(1) = '1' then
wr_nxt_state <= FRAME_s;
else
wr_nxt_state <= IDLE_s;
end if;
when FRAME_s =>
-- if fifo is full then go to overflow state.
-- if the good or bad flag is detected the end
-- of the frame has been reached!
-- this transistion occurs when the gb flag
-- is on the clock edge immediately following
-- the end of the frame.
-- if the eof_bram signal is detected then data valid has
-- fallen low and the end of frame has been detected.
if wr_fifo_full = '1' then
wr_nxt_state <= OVFLOW_s;
elsif wr_gf_pipe(1) = '1' then
wr_nxt_state <= GF_s;
elsif wr_bf_pipe(1) = '1' then
wr_nxt_state <= BF_s;
elsif wr_eof_bram(0) = '1' then
wr_nxt_state <= END_s;
else
wr_nxt_state <= FRAME_s;
end if;
when END_s =>
-- wait until the good or bad flag has been received.
if wr_gf_pipe(1) = '1' then
wr_nxt_state <= GF_s;
elsif wr_bf_pipe(1) = '1' then
wr_nxt_state <= BF_s;
else
wr_nxt_state <= END_s;
end if;
when GF_s =>
-- wait for next frame
wr_nxt_state <= IDLE_s;
when BF_s =>
-- wait for next frame
wr_nxt_state <= IDLE_s;
when OVFLOW_s =>
-- wait until the good or bad flag received.
if wr_gf_pipe(1) = '1' or wr_bf_pipe(1) = '1' then
wr_nxt_state <= IDLE_s;
else
wr_nxt_state <= OVFLOW_s;
end if;
when others =>
wr_nxt_state <= IDLE_s;
end case;
end process next_wrs_p;
-- decode control signals
-- wr_en is used to enable the BRAM write and loading of the input pipeline
wr_en <= '1' when wr_state = FRAME_s else '0';
-- increment the write address when we are receiving a frame
wr_addr_inc <= '1' when wr_state = FRAME_s else '0';
-- if the fifo overflows or a frame is to be dropped, we need to move the
-- write address back to the start of the frame. This allows the data to be
-- overwritten.
wr_addr_reload <= '1' when wr_state = BF_s or wr_state = OVFLOW_s else '0';
-- the start address is saved when in the WAIT state
wr_start_addr_load <= '1' when wr_state = IDLE_s else '0';
-- we need to know when a frame is stored, in order to increment the count of
-- frames stored in the fifo.
p_wr_store_tog : process (wr_clk)
begin -- process
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_store_frame_tog <= '0';
elsif wr_enable = '1' then
if wr_state = GF_s then
wr_store_frame_tog <= not wr_store_frame_tog;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Address counters
-----------------------------------------------------------------------------
-- write address is incremented when write enable signal has been asserted
wr_addr_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_addr <= (others => '0');
elsif wr_enable = '1' then
if wr_addr_reload = '1' then
wr_addr <= wr_start_addr;
elsif wr_addr_inc = '1' then
wr_addr <= wr_addr + 1;
end if;
end if;
end if;
end process wr_addr_p;
-- store the start address
wr_staddr_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_sreset = '1' then
wr_start_addr <= (others => '0');
elsif wr_enable = '1' then
if wr_start_addr_load = '1' then
wr_start_addr <= wr_addr;
end if;
end if;
end if;
end process wr_staddr_p;
-- read address is incremented when read enable signal has been asserted
rd_addr_p : process(rd_clk)
begin
if (rd_clk'event and rd_clk = '1') then
if rd_sreset = '1' then
rd_addr <= (others => '0');
else
if rd_addr_reload = '1' then
rd_addr <= rd_addr - 2;
elsif rd_addr_inc = '1' then
rd_addr <= rd_addr + 1;
end if;
end if;
end if;
end process rd_addr_p;
-----------------------------------------------------------------------------
-- Data pipelines
-----------------------------------------------------------------------------
-- register data inputs to bram
-- no reset to allow srl16 target
reg_din_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_enable = '1' then
wr_data_pipe(0) <= rx_data;
wr_data_pipe(1) <= wr_data_pipe(0);
wr_data_bram <= wr_data_pipe(1);
end if;
end if;
end process reg_din_p;
-- no reset to allow srl16 target
reg_eof_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_enable = '1' then
wr_dv_pipe(0) <= rx_data_valid;
wr_dv_pipe(1) <= wr_dv_pipe(0);
wr_eof_bram(0) <= wr_dv_pipe(1) and not wr_dv_pipe(0);
end if;
end if;
end process reg_eof_p;
-- no reset to allow srl16 target
reg_gf_p : process(wr_clk)
begin
if (wr_clk'event and wr_clk = '1') then
if wr_enable = '1' then
wr_gf_pipe(0) <= rx_good_frame;
wr_gf_pipe(1) <= wr_gf_pipe(0);
wr_bf_pipe(0) <= rx_bad_frame;
wr_bf_pipe(1) <= wr_bf_pipe(0);
end if;
end if;
end process reg_gf_p;
-----------------------------------------------------------------------------
-- Overflow functionality
-----------------------------------------------------------------------------
-- Take the Read Address Pointer and convert it into a gray code
p_reg_rd_addr_gray : process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
if rd_sreset = '1' then
rd_addr_gray <= (others => '0');
else
rd_addr_gray <= unsigned(bin_to_gray(std_logic_vector(rd_addr)));
end if;
end if;
end process p_reg_rd_addr_gray;
-- Resync the Read Address Pointer gray code onto the write clock
-- NOTE: rd_addr_gray signal crosses clock domains
p_sync_rd_addr : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_rd_addr_gray_sync <= (others => '0');
wr_rd_addr_gray <= (others => '0');
elsif wr_enable = '1' then
wr_rd_addr_gray_sync <= rd_addr_gray;
wr_rd_addr_gray <= wr_rd_addr_gray_sync;
end if;
end if;
end process p_sync_rd_addr;
-- Convert the resync'd Read Address Pointer grey code back to binary
wr_rd_addr <= unsigned(gray_to_bin(std_logic_vector(wr_rd_addr_gray)));
-- Obtain the difference between write and read pointers
p_addr_diff : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_addr_diff <= (others => '0');
elsif wr_enable = '1' then
wr_addr_diff <= wr_rd_addr - wr_addr;
end if;
end if;
end process p_addr_diff;
-- Detect when the FIFO is full
-- The FIFO is considered to be full if the write address
-- pointer is within 4 to 15 of the read address pointer.
p_wr_full : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_fifo_full <= '0';
elsif wr_enable = '1' then
if wr_addr_diff(11 downto 4) = 0 and wr_addr_diff(3 downto 2) /= "00" then
wr_fifo_full <= '1';
else
wr_fifo_full <= '0';
end if;
end if;
end if;
end process p_wr_full;
overflow <= '1' when wr_state = OVFLOW_s else '0';
----------------------------------------------------------------------
-- FIFO Status Signals
----------------------------------------------------------------------
-- The FIFO status signal is four bits which represents the occupancy
-- of the FIFO in 16'ths. To generate this signal we therefore only
-- need to compare the 4 most significant bits of the write address
-- pointer with the 4 most significant bits of the read address
-- pointer.
-- already have fifo status on write side through wr_addr_diff.
-- calculate fifo status here and output on the wr clock domain.
p_wr_fifo_status : process (wr_clk)
begin
if wr_clk'event and wr_clk = '1' then
if wr_sreset = '1' then
wr_fifo_status <= "0000";
elsif wr_enable = '1' then
if wr_addr_diff = (wr_addr_diff'range => '0') then
wr_fifo_status <= "0000";
else
wr_fifo_status(3) <= not wr_addr_diff(11);
wr_fifo_status(2) <= not wr_addr_diff(10);
wr_fifo_status(1) <= not wr_addr_diff(9);
wr_fifo_status(0) <= not wr_addr_diff(8);
end if;
end if;
end if;
end process p_wr_fifo_status;
rx_fifo_status <= std_logic_vector(wr_fifo_status);
-----------------------------------------------------------------------------
-- Memory
-----------------------------------------------------------------------------
ramgen : RAMB36E1
generic map (
DOB_REG => 1,
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SRVAL_B => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9)
port map (
ENARDEN => VCC,
CLKARDCLK => wr_clk,
RSTRAMARSTRAM => wr_sreset,
RSTREGARSTREG => GND,
CASCADEINA => GND,
REGCEAREGCE => GND,
ENBWREN => rd_en,
CLKBWRCLK => rd_clk,
RSTRAMB => rd_sreset,
RSTREGB => rd_sreset,
CASCADEINB => GND,
REGCEB => rd_en,
INJECTDBITERR => GND,
INJECTSBITERR => GND,
ADDRARDADDR(15) => GND,
ADDRARDADDR(14 downto 3) => std_logic_vector(wr_addr),
ADDRARDADDR(2 downto 0) => GND_BUS(2 downto 0),
ADDRBWRADDR(15) => GND,
ADDRBWRADDR(14 downto 3) => std_logic_vector(rd_addr),
ADDRBWRADDR(2 downto 0) => GND_BUS(2 downto 0),
DIADI(31 downto 8) => GND_BUS(23 downto 0),
DIADI(7 downto 0) => wr_data_bram,
DIBDI => GND_BUS,
DIPADIP(3 downto 1) => GND_BUS(2 downto 0),
DIPADIP(0) => wr_eof_bram(0),
DIPBDIP => GND_BUS(3 downto 0),
WEA(3 downto 1) => GND_BUS(2 downto 0),
WEA(0) => wr_en,
WEBWE => GND_BUS(7 downto 0),
CASCADEOUTA => open,
CASCADEOUTB => open,
DOADO => open,
DOBDO => dob_bram,
DOPADOP => open,
DOPBDOP => dopb_bram,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
DBITERR => open
);
rd_data_bram <= dob_bram(7 downto 0);
rd_eof <= dopb_bram(0);
end RTL;
|
gpl-3.0
|
01cbd6c1e2e5e2dbd2245b9b899d4549
| 0.519115 | 3.854969 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/bfm_processor_wrapper.vhd
| 1 | 4,686 |
-------------------------------------------------------------------------------
-- bfm_processor_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_master_bfm_v1_00_a;
use plb_master_bfm_v1_00_a.All;
entity bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 63);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_compress : out std_logic;
M_guarded : out std_logic;
M_ordered : out std_logic;
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 63);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end bfm_processor_wrapper;
architecture STRUCTURE of bfm_processor_wrapper is
component plb_master_bfm is
generic (
PLB_MASTER_SIZE : std_logic_vector(0 to 1);
PLB_MASTER_NUM : std_logic_vector(0 to 3);
PLB_MASTER_ADDR_LO_0 : std_logic_vector(0 to 31);
PLB_MASTER_ADDR_HI_0 : std_logic_vector(0 to 31);
PLB_MASTER_ADDR_LO_1 : std_logic_vector(0 to 31);
PLB_MASTER_ADDR_HI_1 : std_logic_vector(0 to 31);
C_PLB_DWIDTH : integer
);
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to ((C_PLB_DWIDTH/8)-1));
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_compress : out std_logic;
M_guarded : out std_logic;
M_ordered : out std_logic;
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to (C_PLB_DWIDTH-1));
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
begin
bfm_processor : plb_master_bfm
generic map (
PLB_MASTER_SIZE => "01",
PLB_MASTER_NUM => "0000",
PLB_MASTER_ADDR_LO_0 => X"00000000",
PLB_MASTER_ADDR_HI_0 => X"00000000",
PLB_MASTER_ADDR_LO_1 => X"00000000",
PLB_MASTER_ADDR_HI_1 => X"00000000",
C_PLB_DWIDTH => 64
)
port map (
PLB_CLK => PLB_CLK,
PLB_RESET => PLB_RESET,
SYNCH_OUT => SYNCH_OUT,
SYNCH_IN => SYNCH_IN,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSsize => PLB_MSsize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrBTerm => PLB_MWrBTerm,
M_request => M_request,
M_priority => M_priority,
M_buslock => M_buslock,
M_RNW => M_RNW,
M_BE => M_BE,
M_msize => M_msize,
M_size => M_size,
M_type => M_type,
M_compress => M_compress,
M_guarded => M_guarded,
M_ordered => M_ordered,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst
);
end architecture STRUCTURE;
|
gpl-3.0
|
1b0dda5585f8f895867fdbb9f18f151f
| 0.575971 | 3.194274 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/fifo/src/vhdl/BRAM/BRAM_S8_S72.vhd
| 1 | 6,537 |
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S8_S72.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (8 and 64) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S8_S72 is
port (ADDRA : in STD_LOGIC_VECTOR (11 downto 0);
ADDRB : in STD_LOGIC_VECTOR (8 downto 0);
DIA : in STD_LOGIC_VECTOR (7 downto 0);
DIB : in STD_LOGIC_VECTOR (63 downto 0);
DIPB : in STD_LOGIC_VECTOR (7 downto 0);
WEA : in STD_LOGIC;
WEB : in STD_LOGIC;
CLKA : in STD_LOGIC;
CLKB : in STD_LOGIC;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
DOA : out STD_LOGIC_VECTOR (7 downto 0);
DOB : out STD_LOGIC_VECTOR (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
end entity BRAM_S8_S72;
architecture BRAM_S8_S72_arch of BRAM_S8_S72 is
component RAMB16_S4_S36
port (
ADDRA: IN std_logic_vector(11 downto 0);
ADDRB: IN std_logic_vector(8 downto 0);
DIA: IN std_logic_vector(3 downto 0);
DIB: IN std_logic_vector(31 downto 0);
DIPB: IN std_logic_vector(3 downto 0);
WEA: IN std_logic;
WEB: IN std_logic;
CLKA: IN std_logic;
CLKB: IN std_logic;
SSRA: IN std_logic;
SSRB: IN std_logic;
ENA: IN std_logic;
ENB: IN std_logic;
DOA: OUT std_logic_vector(3 downto 0);
DOB: OUT std_logic_vector(31 downto 0);
DOPB: OUT std_logic_vector(3 downto 0));
END component;
signal doa1 : std_logic_vector (3 downto 0);
signal dob1 : std_logic_vector (31 downto 0);
signal doa2 : std_logic_vector (3 downto 0);
signal dob2 : std_logic_vector (31 downto 0);
signal dia1 : std_logic_vector (3 downto 0);
signal dib1 : std_logic_vector (31 downto 0);
signal dia2 : std_logic_vector (3 downto 0);
signal dib2 : std_logic_vector (31 downto 0);
begin
dia2 <= DIA(3 downto 0);
dia1 <= DIA(7 downto 4);
dib2(3 downto 0) <= DIB(3 downto 0);
dib1(3 downto 0) <= DIB(7 downto 4);
dib2(7 downto 4) <= DIB(11 downto 8);
dib1(7 downto 4) <= DIB(15 downto 12);
dib2(11 downto 8) <= DIB(19 downto 16);
dib1(11 downto 8) <= DIB(23 downto 20);
dib2(15 downto 12) <= DIB(27 downto 24);
dib1(15 downto 12) <= DIB(31 downto 28);
dib2(19 downto 16) <= DIB(35 downto 32);
dib1(19 downto 16) <= DIB(39 downto 36);
dib2(23 downto 20) <= DIB(43 downto 40);
dib1(23 downto 20) <= DIB(47 downto 44);
dib2(27 downto 24) <= DIB(51 downto 48);
dib1(27 downto 24) <= DIB(55 downto 52);
dib2(31 downto 28) <= DIB(59 downto 56);
dib1(31 downto 28) <= DIB(63 downto 60);
DOA(3 downto 0) <= doa2;
DOA(7 downto 4) <= doa1;
DOB(3 downto 0) <= dob2(3 downto 0);
DOB(7 downto 4) <= dob1(3 downto 0);
DOB(11 downto 8) <= dob2(7 downto 4);
DOB(15 downto 12) <= dob1(7 downto 4);
DOB(19 downto 16) <= dob2(11 downto 8);
DOB(23 downto 20) <= dob1(11 downto 8);
DOB(27 downto 24) <= dob2(15 downto 12);
DOB(31 downto 28) <= dob1(15 downto 12);
DOB(35 downto 32) <= dob2(19 downto 16);
DOB(39 downto 36) <= dob1(19 downto 16);
DOB(43 downto 40) <= dob2(23 downto 20);
DOB(47 downto 44) <= dob1(23 downto 20);
DOB(51 downto 48) <= dob2(27 downto 24);
DOB(55 downto 52) <= dob1(27 downto 24);
DOB(59 downto 56) <= dob2(31 downto 28);
DOB(63 downto 60) <= dob1(31 downto 28);
bram1: RAMB16_S4_S36
port map (
ADDRA => addra(11 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIB => dib1,
DIPB => dipb(3 downto 0),
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOB => dob1,
DOPB => dopb(3 downto 0));
bram2: RAMB16_S4_S36
port map (
ADDRA => addra(11 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIB => dib2,
DIPB => dipb(7 downto 4),
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOB => dob2,
DOPB => dopb(7 downto 4));
end BRAM_S8_S72_arch;
|
gpl-3.0
|
e1f2e372b172dc684e4429467cb99db1
| 0.441028 | 4.037678 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/new/top.vhd
| 1 | 65,851 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity top is
Port (
clk : in STD_LOGIC;
vgaRed : out STD_LOGIC_VECTOR(3 downto 0);
vgaBlue : out STD_LOGIC_VECTOR(3 downto 0);
vgaGreen : out STD_LOGIC_VECTOR(3 downto 0);
Hsync : out STD_LOGIC;
Vsync : out STD_LOGIC;
sw : in STD_LOGIC_VECTOR(15 downto 0);
led : out STD_LOGIC_VECTOR(15 downto 0);
btnC : in STD_LOGIC;
btnU : in STD_LOGIC;
btnL : in STD_LOGIC;
btnR : in STD_LOGIC;
btnD : in STD_LOGIC
);
end top;
architecture Behavioral of top is
signal btn_cnt : natural range 0 to 1000000;
signal posX : natural range 0 to 1280 := 640;
signal posY : natural range 0 to 1024 := 512;
signal X : natural range 0 to 1280;
signal Y : natural range 0 to 1024;
signal R : natural range 0 to 15;
signal G : natural range 0 to 15;
signal B : natural range 0 to 15;
signal scan_clk : std_logic;
signal btnC_DB : std_logic;
signal btnU_DB : std_logic;
signal btnD_DB : std_logic;
signal btnL_DB : std_logic;
signal btnR_DB : std_logic;
function draw_char(X : natural; Y : natural; char : character) return boolean is
constant ADDR_WIDTH: integer:=11;
constant DATA_WIDTH: integer:=8;
type rom_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
-- ROM definition
constant ROM: rom_type:=( -- 2^11-by-8
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 ?
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 ?
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 ?
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a ?
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b ?
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c ?
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d ?
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e ?
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 ?
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 ?
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 ?
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 ¶
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 §
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 ' '
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 !
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 "
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 #
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 $
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 %
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 &
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 '
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 (
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 )
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a *
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b +
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c ,
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d -
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e .
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f /
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a :
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b ;
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c <
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d =
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e >
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f ?
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 @
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b {
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c |
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d }
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e ~
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
--return X <= 8 and Y <= 16 and ROM((char * 16) + Y)(9 - X) = '1';
return ROM((CHARACTER'POS(char) * 16) + Y)(9 - X) = '1';
end draw_char;
function is_in_circle(X : natural; Y : natural; R : natural) return boolean is
begin
return X ** 2 + Y ** 2 <= R ** 2;
end is_in_circle;
function is_on_circle(X : natural; Y : natural; R : natural; T : natural) return boolean is
begin
return is_in_circle(X, Y, R + T) and not is_in_circle(X, Y, R - T);
end is_on_circle;
function draw_string(scanX : natural; scanY : natural; posX : natural; posY : natural; s : string; center : boolean; size : natural) return boolean is
constant charW : natural := 8 * size;
constant charWsp : natural := charW + 2;
constant charH : natural := 16 * size;
constant width : natural := charWsp * s'LENGTH;
constant height : natural := charH;
variable x : natural := posX;
variable y : natural := posY;
variable char : natural;
variable subX : natural;
begin
if (center) then
x := x - (width / 2);
y := y - (height / 2);
end if;
if (scanX < x or scanY < y) then
return false;
end if;
if (scanX - x > width or scanY - y > height) then
return false;
end if;
x := scanX - x;
y := scanY - y;
subX := x mod charWsp;
char := (x / charWsp) + 1;
return draw_char(subX / size, y / size, s(char));
end draw_string;
begin
VGA: entity work.vga
port map (
CLK_I => clk,
VGA_RED_O => vgaRed,
VGA_BLUE_O => vgaBlue,
VGA_GREEN_O => vgaGreen,
VGA_HS_O => Hsync,
VGA_VS_O => Vsync,
X => X,
Y => Y,
R => R,
G => G,
B => B
);
DB_C: entity work.debounce
port map (
clk => clk,
button => btnC,
result => btnC_DB
);
led(0) <= btnC;
led(1) <= btnC_DB;
DB_U: entity work.debounce
port map (
clk => clk,
button => btnU,
result => btnU_DB
);
led(2) <= btnU;
led(3) <= btnU_DB;
DB_D: entity work.debounce
port map (
clk => clk,
button => btnD,
result => btnD_DB
);
led(4) <= btnD;
led(5) <= btnD_DB;
DB_L: entity work.debounce
port map (
clk => clk,
button => btnL,
result => btnL_DB
);
led(6) <= btnL;
led(7) <= btnL_DB;
DB_R: entity work.debounce
port map (
clk => clk,
button => btnR,
result => btnR_DB
);
led(8) <= btnR;
led(9) <= btnR_DB;
process (clk, btnC_DB, btnU_DB, btnL_DB, btnR_DB, btnD_DB)
begin
if (rising_edge(clk)) then
btn_cnt <= btn_cnt + 1;
if (btn_cnt = 1000000) then
btn_cnt <= 0;
if (btnC_DB = '1') then
posX <= 640;
posY <= 512;
end if;
if (btnL_DB = '1' and posX > 0) then
posX <= posX - 1;
end if;
if (btnR_DB = '1' and posX < 1280) then
posX <= posX + 1;
end if;
if (btnU_DB = '1' and posY > 0) then
posY <= posY - 1;
end if;
if (btnD_DB = '1' and posY < 1024) then
posY <= posY + 1;
end if;
end if;
end if;
end process;
process (X, Y, sw)
begin
if (sw(15) = '1') then
if (is_in_circle(X - posX, Y - posY, conv_integer(unsigned(sw(14 downto 0))))) then
R <= 15;
G <= 0;
B <= 0;
else
R <= 0;
G <= 0;
B <= 0;
end if;
else
if (is_on_circle(X - posX, Y - posY, conv_integer(unsigned(sw(9 downto 0))), conv_integer(unsigned(sw(14 downto 10))))) then
R <= 15;
G <= 0;
B <= 0;
else
R <= 0;
G <= 0;
B <= 0;
end if;
end if;
if (draw_string(X, Y, posX, posY - 32, "World: My finger is on the button.", true, 1)) then
R <= 15;
G <= 15;
B <= 15;
elsif (draw_string(X, Y, posX, posY, "Push the button!", true, 2)) then
R <= 0;
G <= 15;
B <= 15;
elsif (draw_string(X, Y, posX, posY + 64, "JUST DO IT!", true, 3)) then
R <= 0;
G <= 15;
B <= 0;
end if;
end process;
end Behavioral;
|
mit
|
79b94ece2377bc6dd68a98f27db774f0
| 0.338355 | 3.799827 | false | false | false | false |
luebbers/reconos
|
support/threads/fifo_rank/hwt_fifo_rank.vhd
| 1 | 8,818 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v1_03_a;
use reconos_v1_03_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hwt_fifo_rank is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_fifo_rank is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant FRAME_SIZE : natural := 320*240*4;
constant C_PIX_AWIDTH : natural := 9;
constant C_LINE_AWIDTH : natural := 9;
constant C_PIX_PER_LINE : natural := 320;
constant C_MODE_PASSTHROUGH : std_logic_vector(6 downto 0)
:= B"0000001";
constant C_MODE_MEDIAN : std_logic_vector(6 downto 0)
:= B"0000010";
constant C_MODE_RED : std_logic_vector(6 downto 0)
:= B"0000100";
constant C_MODE_GREEN : std_logic_vector(6 downto 0)
:= B"0001000";
constant C_MODE_BLUE : std_logic_vector(6 downto 0)
:= B"0010000";
-- os ressources
constant C_FIFO_GET_HANDLE : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
:= X"00000000";
constant C_FIFO_PUT_HANDLE : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
:= X"00000001";
type t_state is (
STATE_INIT,
STATE_PREPARE_PUT_LINE,
STATE_LOAD_A,
STATE_LOAD_B,
STATE_LOAD_C,
STATE_DISPATCH,
STATE_PUT_LINE,
STATE_GET_LINE,
STATE_READY,
STATE_PUT_MEDIAN,
STATE_PUT_PASSTHROUGH,
STATE_PUT_RED,
STATE_PUT_GREEN,
STATE_PUT_BLUE,
STATE_GET,
STATE_FINAL);
signal state : t_state;
signal next_line : std_logic;
signal line_sel : std_logic_vector(1 downto 0);
signal pix_sel : std_logic_vector(C_PIX_AWIDTH - 1 downto 0);
signal local_addr : std_logic_vector(C_BURST_AWIDTH - 1 downto 0);
signal last_line : std_logic;
signal ready : std_logic;
--signal frame_offset : std_logic_vector(C_PIX_AWIDTH + C_LINE_AWIDTH - 1 downto 0); -- not used
signal frame_addr : std_logic_vector(31 downto 0);
signal init_data : std_logic_vector(31 downto 0);
signal filter_mode : std_logic_vector(6 downto 0);
signal r24 : std_logic_vector(23 downto 0);
signal g24 : std_logic_vector(23 downto 0);
signal b24 : std_logic_vector(23 downto 0);
signal r8 : std_logic_vector(7 downto 0);
signal g8 : std_logic_vector(7 downto 0);
signal b8 : std_logic_vector(7 downto 0);
signal pix_out : std_logic_vector(31 downto 0);
signal rank_ien : std_logic;
begin
lag : entity WORK.line_addr_generator
port map (
rst => reset,
next_line => next_line,
line_sel => line_sel,
frame_offset => open,
pix_sel => pix_sel,
bram_addr => local_addr,
last_line => last_line,
ready => ready
);
rank_r : entity WORK.rank_filter3x3
port map(
clk => clk,
rst => reset,
shift_in => r24,
shift_out => r8,
ien => rank_ien,
rank => init_data(3 downto 0)
);
rank_g : entity WORK.rank_filter3x3
port map(
clk => clk,
rst => reset,
shift_in => g24,
shift_out => g8,
ien => rank_ien,
rank => init_data(3 downto 0)
);
rank_b : entity WORK.rank_filter3x3
port map(
clk => clk,
rst => reset,
shift_in => b24,
shift_out => b8,
ien => rank_ien,
rank => init_data(3 downto 0)
);
pix_out <= X"00" & b8 & g8 & r8;
filter_mode <= init_data(30 downto 24);
o_RAMAddr <= local_addr(C_BURST_AWIDTH-1 downto 1) & not local_addr(0);
o_RAMClk <= clk;
state_proc: process( clk, reset )
variable done : boolean;
variable success : boolean;
variable burst_counter : integer;
variable pix_a : std_logic_vector(31 downto 0);
variable pix_b : std_logic_vector(31 downto 0);
variable pix_c : std_logic_vector(31 downto 0);
variable invert : std_logic_vector(31 downto 0);
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_INIT;
frame_addr <= (others => '0');
next_line <= '0';
line_sel <= (others => '0');
pix_sel <= (others => '0');
burst_counter := 0;
rank_ien <= '0';
init_data <= (others => '0');
invert := (others => '0');
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_INIT =>
reconos_get_init_data_s (done, o_osif, i_osif, init_data);
next_line <= '1';
if done then state <= STATE_GET_LINE; end if;
when STATE_GET_LINE =>
o_RAMWE <= '0';
if pix_sel = C_PIX_PER_LINE - 1 then
pix_sel <= (others => '0');
next_line <= '0';
state <= STATE_READY;
else
pix_sel <= pix_sel + 1;
state <= STATE_GET;
end if;
when STATE_GET =>
o_RAMwe <= '1';
reconos_mbox_get_s(done,success,o_osif,i_osif,C_FIFO_GET_HANDLE,o_RAMData);
if done then
state <= STATE_GET_LINE;
end if;
when STATE_READY =>
if last_line = '1' then
state <= STATE_FINAL;
elsif ready = '0' then
next_line <= '1';
state <= STATE_GET_LINE;
else
next_line <= '1';
state <= STATE_PREPARE_PUT_LINE;
end if;
when STATE_PREPARE_PUT_LINE =>
state <= STATE_PUT_LINE;
when STATE_PUT_LINE =>
-- handle output invert
if init_data(31) = '1' then
invert := X"FFFFFFFF";
else
invert := X"00000000";
end if;
o_RAMwe <= '0';
line_sel <= B"00"; -- keep addr -> 0 (default)
if pix_sel = C_PIX_PER_LINE - 1 then
pix_sel <= (others => '0');
state <= STATE_GET_LINE;
else
line_sel <= B"01"; -- addr -> 1
pix_sel <= pix_sel + 1;
state <= STATE_LOAD_A;
end if;
when STATE_LOAD_A =>
line_sel <= B"10"; -- addr -> 2
pix_a := i_RAMData; -- load -> 0
state <= STATE_LOAD_B;
when STATE_LOAD_B =>
pix_b := i_RAMData; -- addr -> 0
line_sel <= B"00"; -- load -> 1
state <= STATE_LOAD_C;
when STATE_LOAD_C =>
pix_c := i_RAMData; -- load -> 2
--line_sel <= B"00";
state <= STATE_DISPATCH;
when STATE_DISPATCH =>
r24 <= pix_a(7 downto 0) & pix_b(7 downto 0) & pix_c(7 downto 0);
g24 <= pix_a(15 downto 8) & pix_b(15 downto 8) & pix_c(15 downto 8);
b24 <= pix_a(23 downto 16) & pix_b(23 downto 16) & pix_c(23 downto 16);
rank_ien <= '1';
case filter_mode is
when C_MODE_MEDIAN =>
state <= STATE_PUT_MEDIAN;
when C_MODE_PASSTHROUGH =>
state <= STATE_PUT_PASSTHROUGH;
when C_MODE_RED =>
state <= STATE_PUT_RED;
when C_MODE_GREEN =>
state <= STATE_PUT_GREEN;
when C_MODE_BLUE =>
state <= STATE_PUT_BLUE;
when others =>
state <= STATE_PUT_PASSTHROUGH;
end case;
when STATE_PUT_MEDIAN =>
rank_ien <= '0';
reconos_mbox_put(done,success,o_osif,i_osif,C_FIFO_PUT_HANDLE,
invert xor pix_out);
if done then
state <= STATE_PUT_LINE;
end if;
when STATE_PUT_PASSTHROUGH =>
reconos_mbox_put(done,success,o_osif,i_osif,C_FIFO_PUT_HANDLE,
invert xor pix_b);
if done then
state <= STATE_PUT_LINE;
end if;
when STATE_PUT_RED =>
reconos_mbox_put(done,success,o_osif,i_osif,C_FIFO_PUT_HANDLE,
invert xor (X"00" & r24));
if done then
state <= STATE_PUT_LINE;
end if;
when STATE_PUT_GREEN =>
reconos_mbox_put(done,success,o_osif,i_osif,C_FIFO_PUT_HANDLE,
invert xor (X"00" & g24));
if done then
state <= STATE_PUT_LINE;
end if;
when STATE_PUT_BLUE =>
reconos_mbox_put(done,success,o_osif,i_osif,C_FIFO_PUT_HANDLE,
invert xor (X"00" & b24));
if done then
state <= STATE_PUT_LINE;
end if;
when STATE_FINAL =>
state <= STATE_FINAL;
end case;
end if;
end if;
end process;
end architecture;
|
gpl-3.0
|
683f0dec15509f765c5baa5029628666
| 0.564073 | 3.00034 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_sync_register.vhd
| 1 | 1,324 |
library ieee;
use ieee.std_logic_1164.all;
entity gc_sync_register is
generic (
g_width : integer);
port (
clk_i : in std_logic;
rst_n_a_i : in std_logic;
d_i : in std_logic_vector(g_width-1 downto 0);
q_o : out std_logic_vector(g_width-1 downto 0));
end gc_sync_register;
architecture rtl of gc_sync_register is
signal gc_sync_register_in : std_logic_vector(g_width-1 downto 0);
signal sync0, sync1 : std_logic_vector(g_width-1 downto 0);
attribute shreg_extract : string;
attribute shreg_extract of gc_sync_register_in : signal is "no";
attribute shreg_extract of sync0 : signal is "no";
attribute shreg_extract of sync1 : signal is "no";
attribute keep : string;
attribute keep of gc_sync_register_in : signal is "true";
attribute keep of sync0 : signal is "true";
attribute keep of sync1 : signal is "true";
begin
process(clk_i, rst_n_a_i)
begin
if(rst_n_a_i = '0') then
sync1 <= (others => '0');
sync0 <= (others => '0');
elsif rising_edge(clk_i) then
sync0 <= gc_sync_register_in;
sync1 <= sync0;
end if;
end process;
gc_sync_register_in <= d_i;
q_o <= sync1;
end rtl;
|
lgpl-3.0
|
70d1ca67c92724229f2f954f8b544287
| 0.574018 | 3.28536 | false | false | false | false |
luebbers/reconos
|
support/refdesigns/12.3/ml605/ml605_light_thermal/pcores/plbv46_dcr_bridge_v9_00_a/hdl/vhdl/plbv46_dcr_bridge_core.vhd
| 7 | 14,236 |
-------------------------------------------------------------------------------
-- plbv46_dcr_bridge_core - entity / architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2006, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************--
--
-------------------------------------------------------------------------------
-- Filename: plbv46_dcr_bridge_core.vhd
-- Version: v1.01.a
-- Description: plbv46_dcr_bridge core
--
-------------------------------------------------------------------------------
-- Structure:
-- plbv46_dcr_bridge.vhd
-- -- plbv46_dcr_bridge_core.vhd
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : SK
-- History:
-- Initial version of plbv46_dcr_Bridge
-- ~~~~~~
-- SK 2006/09/19 -- Initial version
-- ^^^^^^
-- ~~~~~~
-- SK 2008/12/15 -- Updated version v1_01_a, based upon v1_00_a core.
-- -- updated proc_common_v3_00_a and plbv46_slave_
-- -- single_v1_01_a core libraries.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Definition of Ports:
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
----------------------------------------
-- IPIC INTERFACE
----------------------------------------
-- Bus2IP_Clk - IPIC clock
-- Bus2IP_Reset - IPIC reset
-- Bus2IP_CS - IPIC chip select signals
-- Bus2IP_RdCE - IPIC read transaction chip enables
-- Bus2IP_WrCE - IPIC write transaction chip enables
-- Bus2IP_Addr - IPIC address
-- Bus2IP_RNW - IPIC read/write indication
-- Bus2IP_BE - IPIC byte enables
-- Bus2IP_Data - IPIC write data
-- IP2Bus_Data - Read data from IP to IPIC interface
-- IP2Bus_WrAck - Write Data acknowledgment from IP to IPIC interface
-- IP2Bus_RdAck - Read Data acknowledgment from IP to IPIC interface
-- IP2Bus_Error - Error indication from IP to IPIC interface
----------------------------------------
-- PERIPHERAL INTERFACE
----------------------------------------
-- DCR_plbDBusIn - DCR data bus input
-- DCR_plbAck - DCR Ack signals
-- PLB_dcrABus - PLB address bus to DCR
-- PLB_dcrDBusOut - Data bus to the PLB
-- PLB_dcrRead - PLB read signal to DCR
-- PLB_dcrWrite - PLB write signal to DCR
-- PLB_dcrClk - PLB to DCR clk
-- PLB_dcrRst - PLB to DCR reset
-----------------------------------------------------------------------------
-- Definition of Generics
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned."+";
entity plbv46_dcr_bridge_core is
port (
-- PLBv46_IPIF Signals
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_CS : in std_logic;
Bus2IP_RdCE : in std_logic;
Bus2IP_WrCE : in std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_Data : out std_logic_vector(0 to 31);
-- DCR Master Signals
-- core signals
DCR_plbDBusIn : in std_logic_vector(0 to 31);
DCR_plbAck : in std_logic;
PLB_dcrABus : out std_logic_vector(0 to 9);
PLB_dcrDBusOut : out std_logic_vector(0 to 31);
PLB_dcrRead : out std_logic;
PLB_dcrWrite : out std_logic;
PLB_dcrClk : out std_logic;
PLB_dcrRst : out std_logic
);
end entity plbv46_dcr_bridge_core;
-------------------------------------------------------------------------------
architecture implemented of plbv46_dcr_bridge_core is
-------------------------------------------------------------------------------
-- local signal declaration section
signal plb_dcrRead_i : std_logic;
signal plb_dcrWrite_i : std_logic;
signal ip2Bus_RdAck_i : std_logic;
signal ip2Bus_WrAck_i : std_logic;
signal dcr_ack_posedge : std_logic;
signal dcr_plbAck_d1 : std_logic;
signal timeout : std_logic;
signal ip2Bus_Error_i : std_logic;
signal timeout_cnt : std_logic_vector(0 to 3);
-------------------------------------------------------------------------------
begin -- architecture implemented
-------------------------------------------------------------------------------
--////////////////////////////////////////////////////////////////////////////
-- Main Body of Code
--////////////////////////////////////////////////////////////////////////////
-- NOTE: This design is supporting DCR reads and writes bridged from
-- PLBV46. Since DCR reads and writes are defined on words only, the
-- incoming PLBV46 reads and writes that are to be retargetted to the DCR bus
-- must also be for words only. If the PLBV46 byte enables do not correspond
-- to a word transfer, an error will be returned.
-- DCR signals just pass through from IPIF/PLBv46, but are renamed
-- to DCR names to help make it clear how to hook things up.
PLB_dcrClk <= Bus2IP_Clk;
PLB_dcrRst <= Bus2IP_Reset;
-------------------------------------------------------------------------------
-- PLB_DCRREAD_I_PROC
-- latch and hold read request strobe
-- synchronous reset (active high)
PLB_DCRREAD_I_PROC: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if (Bus2IP_CS = '0' or IP2Bus_RdAck_i = '1' or
Bus2IP_Reset = '1' or timeout = '1') then
plb_dcrRead_i <= '0';
elsif (Bus2IP_RdCE = '1' and DCR_plbAck = '0') then
plb_dcrRead_i <= '1';
end if;
end if;
end process PLB_DCRREAD_I_PROC;
PLB_dcrRead <= plb_dcrRead_i;
-------------------------------------------------------------------------------
-- PLB_DCRWRITE_I_PROC
-- latch and hold write request strobe
-- synchronous reset (active high)
PLB_DCRWRITE_I_PROC: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if (Bus2IP_CS = '0' or IP2Bus_WrAck_i = '1' or
Bus2IP_Reset = '1' or timeout = '1') then
plb_dcrWrite_i <= '0';
elsif (Bus2IP_WrCE = '1' and DCR_plbAck = '0')then
plb_dcrWrite_i <= '1';
end if;
end if;
end process PLB_DCRWRITE_I_PROC;
PLB_dcrWrite <= plb_dcrWrite_i;
-------------------------------------------------------------------------------
-- process REG_DCR_ABUS_PROC
-- DCR address bus is 10 bits and points to 32 bit words, so pick up the
-- corresponding address bits from PLBv46
REG_DCR_ABUS_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
PLB_dcrABus <= Bus2IP_Addr(20 to 29);
end if;
end process REG_DCR_ABUS_PROC;
-------------------------------------------------------------------------------
-- process DCR_DBUS_OUT_PROC
-- PLB_dcrDBusOut is set to 0xFFFF_FFFF during reads operations so it
-- will return 0xFFFF_FFFF when read times out. DCR specifies that timeout
-- errors are ignored back to the CPU so setting the default read to all
-- 1's will help identify timeouts. Data bus out drives 00000000 during
-- reset as required by DCR spec.
DCR_DBUS_OUT_PROC: process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
PLB_dcrDBusOut <= (others => '0');
elsif (plb_dcrRead_i = '1' or Bus2IP_RdCE = '1') then
PLB_dcrDBusOut <= (others => '1');
else
PLB_dcrDBusOut <= Bus2IP_Data;
end if;
end if;
end process DCR_DBUS_OUT_PROC;
-------------------------------------------------------------------------------
-- connect input data lines to ip2bus_data, so that it will be returned to ipif
IP2Bus_Data <= DCR_plbDBusIn;
-------------------------------------------------------------------------------
-- process TIMOUT_CNT_PROC
-- Generate timeouts after 16 cycles. The timeout counter is enabled during
-- DCR operations and is reset during system reset or when an ack is sent
-- back to the IPIF. Note that an ack is sent back to the IPIF after a timeout
-- has been issued or if a DCR slave responds.
TIMOUT_CNT_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
if (Bus2IP_CS = '0' or IP2Bus_RdAck_i = '1' or IP2Bus_WrAck_i = '1'
or Bus2IP_Reset = '1') then
timeout_cnt <= "0000";
elsif (plb_dcrRead_i = '1' or plb_dcrWrite_i = '1') then
timeout_cnt <= timeout_cnt + 1;
end if;
end if;
end process TIMOUT_CNT_PROC;
-------------------------------------------------------------------------------
timeout <= '1' when timeout_cnt = "1111" else '0';
-------------------------------------------------------------------------------
-- process DCR_plbAck_PROC
-- detect only the posedge of DCR slave acks since the DCR slave may run
-- on a slower clock and thus its ack would be seen asserted for more than
-- 1 cycle
DCR_plbAck_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
dcr_plbAck_d1 <= DCR_plbAck;
end if;
end process DCR_plbAck_PROC;
dcr_ack_posedge <= DCR_plbAck and (not dcr_plbAck_d1);
-------------------------------------------------------------------------------
-- generate an ack back to the IPIF when a DCR slave responds or if a timeout
-- occurs
IP2Bus_RdAck_i <= plb_dcrRead_i and (dcr_ack_posedge or timeout);
IP2Bus_RdAck <= IP2Bus_RdAck_i;
IP2Bus_WrAck_i <= plb_dcrWrite_i and (dcr_ack_posedge or timeout);
IP2Bus_WrAck <= IP2Bus_WrAck_i;
-------------------------------------------------------------------------------
-- Generate a PLB error on DCR timeout or if less than a full
-- word of data is transferred (BE not 1111)
ip2Bus_Error_i <= '1' when (
(timeout = '1' and dcr_ack_posedge = '0')
or
((Bus2IP_BE /= "1111") and Bus2IP_CS = '1')
) else '0';
-------------------------------------------------------------------------------
--DCR_Error_REG_PROC
--this process is to register the error signal.
-----------------------------------------------
DCR_Error_REG_PROC : process (Bus2IP_Clk) is
begin
if Bus2IP_Clk'EVENT and Bus2IP_Clk = '1' then
IP2Bus_Error <= ip2Bus_Error_i;
end if;
end process DCR_Error_REG_PROC;
-------------------------------------------------------------------------------
end architecture implemented;
|
gpl-3.0
|
edff2baf063b39defca24dce05c26f40
| 0.49719 | 4.415633 | false | false | false | false |
dries007/Basys3
|
FPGA-Z/FPGA-Z.srcs/sources_1/new/Top.vhd
| 1 | 85,213 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.Font.all;
entity top is
Port (
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
Hsync : out std_logic;
Vsync : out std_logic;
led : out std_logic_vector (15 downto 0);
sw : in std_logic_vector (15 downto 0);
clk : in std_logic;
btnC : in std_logic;
btnU : in std_logic;
btnL : in std_logic;
btnR : in std_logic;
btnD : in std_logic;
PS2Clk : in std_logic;
PS2Data : in std_logic;
RsRx : inout std_logic;
RsTx : inout std_logic
);
end top;
architecture Behavioral of top is
-- CONSTANTS ----------------------------------------------------
constant COLS : integer := 160;
constant ROWS : integer := 64;
constant CHARS : integer := COLS * ROWS;
constant CPU_FREQ : integer := 15_000_000;
constant BLINKDATA : string := "Press any key to continue...";
constant TYPE_LRG_CNT : std_logic_vector := "00";
constant TYPE_SML_CNT : std_logic_vector := "01";
constant TYPE_VAR : std_logic_vector := "10";
constant TYPE_OMITTED : std_logic_vector := "11";
type alphabets_type is array (0 to 2, 6 to 31) of character;
constant alphabets: alphabets_type := (
('a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z'),
('A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z'),
(character'val(255), character'val(10), '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '.', ',', '!', '?', '_', '#', character'val(39), character'val(34), '/', '\', '-', ':', '(', ')')
);
-- CLOCK --------------------------------------------------------
component ClockDivider
port (
clkIn : in std_logic;
clk108M : out std_logic;
clk_cpu : out std_logic;
clk2cpu : out std_logic;
clk6cpu : out std_logic
);
end component;
signal clk_vga : std_logic := '0';
signal clk_cpu : std_logic := '0';
signal clk_2cpu : std_logic := '0';
signal clk_6cpu : std_logic := '0';
signal clk_10 : std_logic := '0';
signal clk_2 : std_logic := '0';
signal clk_1 : std_logic := '0';
signal clk_1k : std_logic := '0';
-- VGA controller -----------------------------------------------
component Vga
Port (
clk : in std_logic;
hSync : out std_logic;
vSync : out std_logic;
vgaRed : out std_logic_vector (3 downto 0);
vgaGreen : out std_logic_vector (3 downto 0);
vgaBlue : out std_logic_vector (3 downto 0);
fbOutAddr : out std_logic_vector(13 downto 0);
fbOutDat : in std_logic_vector(7 downto 0)
);
end component;
signal vga_addr : std_logic_vector(13 downto 0) := (others =>'0');
signal vga_dat : std_logic_vector(7 downto 0) := (others =>'0');
-- FRAMEBUFFER --------------------------------------------------
-- NEEDS to run at 2x CPU freq, for 1 CPU cycle mem access
component Framebuffer is
port (
clka : in std_logic;
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(13 downto 0);
dina : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(13 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end component;
signal fb_a_we : std_logic_vector(0 downto 0) := (others =>'0');
signal fb_a_addr : std_logic_vector(13 downto 0) := (others =>'0');
signal fb_a_dat_in : std_logic_vector(7 downto 0) := (others =>'0');
signal fb_a_dat_out : std_logic_vector(7 downto 0) := (others =>'0');
signal fb_a_en : std_logic := '0';
-- RNG ----------------------------------------------------------
component Prng is
Generic
(
BITS : integer := 16
);
Port
(
seed : in std_logic_vector (16-1 downto 0);
seed_en : in std_logic;
clk : in std_logic;
rnd : out std_logic_vector (16-1 downto 0)
);
end component;
signal rng_seed : std_logic_vector(15 downto 0) := (others =>'0');
signal rng_seed_en : std_logic := '0';
signal rng_clk : std_logic := '0';
signal rng_out : std_logic_vector(15 downto 0) := (others =>'0');
-- KEYBOARD CONTROLLER ------------------------------------------
-- NEEDS to be at CPU freq
component ps2_keyboard_to_ascii is
Generic
(
CLK_FREQ : integer := CPU_FREQ
);
Port
(
clk : in std_logic; --system clock input
ps2_clk : in std_logic; --clock signal from ps2 keyboard
ps2_data : in std_logic; --data signal from ps2 keyboard
ascii_new : out std_logic; --output flag indicating new ascii value
ascii_code : out std_logic_vector(6 downto 0) --ascii value
);
end component;
signal kb_event : std_logic := '0';
signal kb_acsii : std_logic_vector(6 downto 0) := (others => '0');
-- RAM ----------------------------------------------------------
-- NEEDS to run at 6x CPU freq, for 1 CPU cycle mem access
component Ram is
Port
(
clk : in std_logic;
re : in std_logic_vector (1 downto 0);
we : in std_logic_vector (1 downto 0);
addr : in integer range 0 to 16#1FFFF#;
dat_r : out std_logic_vector (15 downto 0);
dat_w : in std_logic_vector (15 downto 0)
);
end component;
signal ram_re : std_logic_vector(1 downto 0) := (others => '0');
signal ram_we : std_logic_vector(1 downto 0) := (others => '0');
signal ram_addr : integer range 0 to 16#1FFFF# := 0;
signal ram_dat_r : std_logic_vector(15 downto 0) := (others => '0');
signal ram_dat_w : std_logic_vector(15 downto 0) := (others => '0');
-- STACK --------------------------------------------------------
component Stack is
port (
a : in std_logic_vector(9 downto 0);
d : in std_logic_vector(15 downto 0);
clk : in std_logic;
we : in std_logic;
spo : out std_logic_vector(15 downto 0)
);
end component;
signal stack_addr : std_logic_vector(9 downto 0) := (others => '0');
signal stack_dat_w : std_logic_vector(15 downto 0) := (others => '0');
signal stack_we : std_logic := '0';
signal stack_dat_r : std_logic_vector(15 downto 0) := (others => '0');
-- MISC ---------------------------------------------------------
-- runtime in ms
signal runtime : unsigned(32 downto 0) := (others => '0');
-- FUNCTIONS ----------------------------------------------------
function cursor_delta(current : integer range 0 to CHARS; delta : integer range -CHARS to CHARS := 1; modulo : integer range 0 to CHARS := CHARS) return integer is
begin
return (current + delta) mod modulo;
end cursor_delta;
function pad_string(input : string; size : positive; hex : std_logic_vector := "") return string is
variable tmp: string(1 to size) := (others => NUL);
begin
if hex'length = 0 then
if input'length >= size then
tmp := input(1 to size);
else
tmp(1 to input'length) := input;
tmp(input'length + 1 to size) := (others => ' ');
end if;
else
if input'length >= (size - (hex'length / 4) - 1) then
tmp(1 to (size - (hex'length / 4)) - 1) := input(1 to (size - (hex'length / 4)) - 1); -- copy over as much as will fit
tmp(size - (hex'length / 4)) := ' '; -- add space
for i in 0 to (hex'length / 4) - 1 loop -- per 4 bits
case to_integer(unsigned(hex(hex'length - (4 * i) to hex'length - (4 * i) - 4))) is
when 0 => tmp(size - (hex'length / 4) + i) := '0';
when 1 => tmp(size - (hex'length / 4) + i) := '1';
when 2 => tmp(size - (hex'length / 4) + i) := '2';
when 3 => tmp(size - (hex'length / 4) + i) := '3';
when 4 => tmp(size - (hex'length / 4) + i) := '4';
when 5 => tmp(size - (hex'length / 4) + i) := '5';
when 6 => tmp(size - (hex'length / 4) + i) := '6';
when 7 => tmp(size - (hex'length / 4) + i) := '7';
when 8 => tmp(size - (hex'length / 4) + i) := '8';
when 9 => tmp(size - (hex'length / 4) + i) := '9';
when 10 => tmp(size - (hex'length / 4) + i) := 'A';
when 11 => tmp(size - (hex'length / 4) + i) := 'B';
when 12 => tmp(size - (hex'length / 4) + i) := 'D';
when 13 => tmp(size - (hex'length / 4) + i) := 'D';
when 14 => tmp(size - (hex'length / 4) + i) := 'E';
when 15 => tmp(size - (hex'length / 4) + i) := 'F';
when others => tmp(size - (hex'length / 4) + i) := '?';
end case;
end loop;
else
tmp(1 to input'length) := input;
tmp(input'length + 1 to size) := (others => ' ');
end if;
end if;
return tmp;
end pad_string;
function ascii_c(char : character; inverted : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := (others => '0');
begin
if inverted then
tmp(7) := '1';
end if;
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos(char), 7));
return tmp;
end ascii_c;
function ascii_b(b : std_logic; inverted : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := '0' & std_logic_vector(to_unsigned(character'pos('0'), 7));
begin
if inverted then
tmp(7) := '1';
end if;
tmp(0) := b;
return tmp;
end ascii_b;
function ascii_i(i : integer range -999_999 to 999_999; didget : integer range 0 to 10 := 0; inverted : boolean := false; sign : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := (others => '0');
begin
if inverted then
tmp(7) := '1';
end if;
if sign then
if i > 0 then
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('+'), 7));
else
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('-'), 7));
end if;
else
tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('0') + ((i mod (10 ** (didget + 1))) / (10 ** didget)), 7));
end if;
return tmp;
end ascii_i;
function ascii_x(i : integer range 0 to 16#FF_FFFF#; didget : integer range 0 to 10 := 0; inverted : boolean := false) return std_logic_vector(7 downto 0) is
variable tmp : std_logic_vector(7 downto 0) := (others => '0');
begin
if inverted then
tmp(7) := '1';
end if;
case to_integer(shift_right(to_unsigned(i, 6 * 4), 4 * didget) and "000000000000000000001111") is
when 0 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('0'), 7));
when 1 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('1'), 7));
when 2 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('2'), 7));
when 3 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('3'), 7));
when 4 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('4'), 7));
when 5 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('5'), 7));
when 6 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('6'), 7));
when 7 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('7'), 7));
when 8 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('8'), 7));
when 9 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('9'), 7));
when 10 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('A'), 7));
when 11 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('B'), 7));
when 12 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('C'), 7));
when 13 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('D'), 7));
when 14 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('E'), 7));
when 15 => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('F'), 7));
when others => tmp(6 downto 0) := std_logic_vector(to_unsigned(character'pos('?'), 7));
end case;
return tmp;
end ascii_x;
--------------------------------------------------------
begin -- BEGIN
--------------------------------------------------------
-- CLOCK --------------------------------------------------------
clock0: ClockDivider
port map (
clkIn => clk,
clk108M => clk_vga,
clk_cpu => clk_cpu,
clk2cpu => clk_2cpu,
clk6cpu => clk_6cpu
);
-- Slow clock devider
process (clk_cpu)
constant MAX : integer := CPU_FREQ/2;
variable i : integer range 0 to MAX := 0;
begin
if rising_edge(clk_cpu) then
if i < MAX then
i := i + 1;
else
i := 0;
end if;
if i = 0 then
clk_1 <= not(clk_1);
end if;
if i mod (MAX / 2) = 0 then
clk_2 <= not(clk_2);
end if;
if i mod (MAX / 1000) = 0 then
clk_1k <= not(clk_1k);
end if;
if i mod (MAX / 10) = 0 then
clk_10 <= not(clk_10);
end if;
end if;
end process;
-- VGA controller -----------------------------------------------
vga0: Vga
port map (
clk => clk_vga,
hSync => Hsync,
vSync => Vsync,
vgaRed => vgaRed,
vgaGreen => vgaGreen,
vgaBlue => vgaBlue,
fbOutAddr => vga_addr,
fbOutDat => vga_dat
);
-- FRAMEBUFFER --------------------------------------------------
frameBuffer0: Framebuffer
port map (
clka => clk_2cpu,
ena => fb_a_en,
wea => fb_a_we,
addra => fb_a_addr,
dina => fb_a_dat_in,
douta => fb_a_dat_out,
clkb => clk_vga,
web => "0",
addrb => vga_addr,
dinb => x"00",
doutb => vga_dat
);
-- RNG ----------------------------------------------------------
prng0: Prng
port map (
seed => rng_seed,
seed_en => rng_seed_en,
clk => rng_clk,
rnd => rng_out
);
-- KEYBOARD CONTROLLER ------------------------------------------
keyboard0: ps2_keyboard_to_ascii
port map (
clk => clk_cpu,
ps2_clk => PS2Clk,
ps2_data => PS2Data,
ascii_new => kb_event,
ascii_code => kb_acsii
);
-- RAM ----------------------------------------------------------
ram0: Ram
port map (
clk => clk_6cpu,
re => ram_re,
we => ram_we,
addr => ram_addr,
dat_r => ram_dat_r,
dat_w => ram_dat_w
);
-- STACK --------------------------------------------------------
stack0: Stack
port map (
a => stack_addr,
d => stack_dat_w,
clk => clk_cpu,
we => stack_we,
spo => stack_dat_r
);
-- MISC ---------------------------------------------------------
-- runtime cursor
process (clk_1k)
begin
if rising_edge(clk_1k) then
runtime <= runtime + 1;
end if;
end process;
---- PRNG test
--rng_seed <= sw;
--led <= rng_out;
--process (clk_10)
--begin
-- if rising_edge(clk_10) then
-- if btnL = '1' then
-- rng_seed_en <= '1';
-- rng_clk <= not(rng_clk);
-- else
-- rng_seed_en <= '0';
-- end if;
-- if btnR = '1' then
-- rng_clk <= not(rng_clk);
-- end if;
-- end if;
--end process;
---- debug info
-- led <= (clk_1, clk_2, runtime(13 downto 0));
-- led <= clk_1 & clk_2 & std_logic_vector(runtime(17 downto 4));
-- MAIN ---------------------------------------------------------
-- CPU control state machine, not a proper FSM!
process (clk_cpu)
type state_type is
(
RESET, BLANK, SCROLL, SCROLL_W, LOAD, LOAD_ABBR, DEBUG, DEBUG_KB, ERROR, -- Background states, used for 'interpreter' stuff
FETCH, FETCH_OP, DECODE, EXEC -- Z machine states
);
variable state : state_type := RESET;-- LOAD;-- The current/next state
variable next_state : state_type := RESET; -- The state to go to, after finishing the current one.
type instuction_type is
(
OP_NOP, OP_PRINT, OP_POP, OP_PRINT_NL, OP_STATUS, OP_VERIFY, OP_COMP_ZERO, OP_GET_SIBLING, OP_GET_CHILD, OP_GET_PARENT, OP_GET_PROP_LEN,
OP_INC, OP_DEC, OP_PRINT_ADDR, OP_REMOVE_OBJ, OP_PRINT_OBJ, OP_JUMP, OP_PRINT_PADDR, OP_LOAD, OP_NOT_BW, OP_COMP_EQ, OP_COMP_LT,
OP_COMP_GT, OP_DEC_CHK, OP_INC_CHK, OP_JIN, OP_TEST, OP_OR_BW, OP_AND_BW, OP_TEST_ATTR, OP_SET_ATTR, OP_CLEAR_ATTR, OP_STORE,
OP_INSERT_OBJ, OP_LOADW, OP_LOADB, OP_GET_PROP, OP_GET_PROP_ADDR, OP_GET_NEXT_PROP, OP_ADD, OP_SUB, OP_MUL, OP_DIV, OP_MOD, OP_CALL,
OP_STOREW, OP_STOREB, OP_PUT_PROP, OP_SREAD, OP_PRINT_CHAR, OP_PRINT_NUM, OP_RND, OP_PUSH, OP_PULL, OP_SPLIT_WINDOW, OP_SET_WINDOW
);
variable instruction : instuction_type := OP_NOP;
variable instruction_raw : std_logic_vector(7 downto 0) := (others => '0');
variable ret : boolean := false;
variable string_fetch : boolean := false;
variable string_buffer : string(1 to COLS);
variable string_pointer : integer range 0 to COLS := 0;
variable string_back : integer range 0 to 16#1FFFF# := 0;
variable string_back_inner : integer range 0 to 2 := 0;
variable string_in_abbr : boolean := false;
variable string_alphabet : integer range 0 to 2 := 0;
variable string_current_z : integer range 0 to 31 := 0;
variable string_abbreviation : integer range 0 to 3 := 0; -- if not 0, do an abbreviation next
variable string_zscii : integer range 0 to 2 := 0; -- if not 0, do a zscii character of 2x 5 bits. 2 = upper bits, 1 = lower bits
variable branch : boolean := false;
variable branch_on_true : boolean := false;
variable branch_fetch : boolean := false;
variable branch_offset : integer range -8192 to 8191;
variable store : boolean := false;
variable store_fetch : boolean := false;
variable store_var : std_logic_vector(7 downto 0) := (others => '0');
variable op0_fetch : boolean := false;
variable op0_type : std_logic_vector(1 downto 0) := "00";
variable op0 : std_logic_vector(15 downto 0) := (others => '0');
variable op1_fetch : boolean := false;
variable op1_type : std_logic_vector(1 downto 0) := "00";
variable op1 : std_logic_vector(15 downto 0) := (others => '0');
variable op2_fetch : boolean := false;
variable op2_type : std_logic_vector(1 downto 0) := "00";
variable op2 : std_logic_vector(15 downto 0) := (others => '0');
variable op3_fetch : boolean := false;
variable op3_type : std_logic_vector(1 downto 0) := "00";
variable op3 : std_logic_vector(15 downto 0) := (others => '0');
variable delay : boolean := false;-- Delay 1 clock tick
variable cursor : integer range 0 to CHARS := 0;
variable message : string(1 to COLS);
variable flags1 : std_logic_vector(15 downto 0) := (others => '0');
variable flags2 : std_logic_vector(15 downto 0) := (others => '0');
variable high : integer range 0 to 16#FFFF# := 0;
variable pc : integer range 0 to 16#1FFFF# := 0;
variable dict : integer range 0 to 16#FFFF# := 0;
variable objtab : integer range 0 to 16#FFFF# := 0;
variable globals : integer range 0 to 16#FFFF# := 0;
variable static : integer range 0 to 16#FFFF# := 0;
variable abbreviations_start : integer range 0 to 16#FFFF# := 0;
variable length : integer range 0 to 16#FF_FFFF# := 0;
variable checksum : integer range 0 to 16#FFFF# := 0;
-- Table of abbreviation addresses, for reduced access time.
-- It could be left in ram and accessed when required, but that would require more stare registers and clock cycles.
type abbreviations_type is array(95 downto 0) of integer range 0 to 16#1FFFF#;
variable abbreviations : abbreviations_type;
begin
if rising_edge(clk_cpu) then
fb_a_en <= '0';
fb_a_we <= "0";
ram_re <= "00";
ram_we <= "00";
if delay then
delay := false;
elsif kb_event = '1' and kb_acsii = "0011011" then
cursor := 0;
state := BLANK;
next_state := LOAD;
else
case state is
---------------------------------------------
-- Z STATES
---------------------------------------------------------------------------------------------------------------------------------------
when EXEC =>
state := ERROR;
message := pad_string("Debug", message'LENGTH, ram_dat_r);
ret := false;
string_buffer := pad_string("-", string_buffer'LENGTH);
string_pointer := 0;
string_back := 0;
string_back_inner := 0;
string_in_abbr := false;
string_alphabet := 0;
string_current_z := 0;
string_abbreviation := 0;
string_zscii := 0;
branch := false;
branch_on_true := false;
branch_offset := 0;
store := false;
store_var := (others => '0');
op0_type := "11";
op0 := "0000000000000000";
op1_type := "11";
op1 := "0000000000000000";
op2_type := "11";
op2 := "0000000000000000";
op3_type := "11";
op3 := "0000000000000000";
-- state := FETCH;
when FETCH_OP =>
pc := pc + 1;
if op0_fetch then
op0_fetch := false;
case op0_type is
when TYPE_LRG_CNT =>
op0 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op0 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op0 := (others => '0');
end case;
elsif op1_fetch then
op1_fetch := false;
case op1_type is
when TYPE_LRG_CNT =>
op1 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op1 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op1 := (others => '0');
end case;
elsif op2_fetch then
op2_fetch := false;
case op2_type is
when TYPE_LRG_CNT =>
op2 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op2 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op2 := (others => '0');
end case;
elsif op3_fetch then
op3_fetch := false;
case op3_type is
when TYPE_LRG_CNT =>
op3 := ram_dat_r;
pc := pc + 1;
when TYPE_SML_CNT | TYPE_VAR =>
op3 := "00000000" & ram_dat_r(15 downto 8);
when TYPE_OMITTED =>
op3 := (others => '0');
end case;
elsif store_fetch then
store_fetch := false;
store_var := ram_dat_r(15 downto 8);
elsif branch_fetch then
branch_fetch := false;
if ram_dat_r(15) = '1' then -- true or false?
branch_on_true := true;
else
branch_on_true := false;
end if;
if ram_dat_r(14) = '1' then -- short format, 0 to 63)
branch_offset := to_integer(unsigned(ram_dat_r(13 downto 8)));
else -- long format, !!signed!! -8192 to 8191
branch_offset := to_integer(signed(ram_dat_r(13 downto 0)));
pc := pc + 1;
end if;
elsif string_fetch then
pc := pc + 2; -- string is always word alligned
-- bit 15 only set when last 3 characters.
if ram_dat_r(15) = '1' then
if string_in_abbr then -- go back to main string
string_in_abbr := false;
pc := string_back;
else -- string is done
string_fetch := false;
end if;
end if;
------------------------
-- -- z char 1 (bits 14 to 10)
-- string_current_z := to_integer(unsigned(ram_dat_r(14 downto 10)));
-- if string_abbreviation /= 0 then -- prev char was abbreviation char
-- string_back := pc;
-- string_in_abbr := true;
-- pc := abbreviations(32 * (string_abbreviation - 1) + string_current_z); -- address of the "32(z-1)+n"th abbreviation
-- string_abbreviation := 0;
-- elsif string_zscii = 2 then -- part 1 of zscii
-- -- string_buffer(string_pointer)(8 downto 6) := std_logic_vector(to_unsigned(string_current_z, 3));
-- string_zscii := 1;
-- elsif string_zscii = 1 then -- part 2 of zscii
-- -- string_buffer(string_pointer)(5 downto 0) := std_logic_vector(to_unsigned(string_current_z, 5));
-- string_buffer(string_pointer) := character'val(254); -- todo
-- string_zscii := 0;
-- string_pointer := string_pointer + 1;
-- else -- not escaped
-- case string_current_z is
-- when 0 => -- space
-- string_buffer(string_pointer) := ' ';
-- string_pointer := string_pointer + 1;
-- when 1 to 3 => -- abbreviation character
-- if string_in_abbr then
-- state := ERROR;
-- message := pad_string("Abbreviation inside abbreviation.", message'LENGTH);
-- end if;
-- string_abbreviation := string_current_z;
-- when 4 => -- alphabet shift to 1
-- string_alphabet := 1;
-- when 5 => -- alphabet shift to 2
-- string_alphabet := 2;
-- when 6 to 31 =>
-- if string_alphabet = 2 and string_current_z = 6 then -- zscii escape char
-- string_zscii := 2;
-- else -- regular character
-- string_buffer(string_pointer) := alphabets(string_alphabet, string_current_z);
-- string_pointer := string_pointer + 1;
-- end if;
-- end case;
-- end if;
------------------------
-- -- z char 2 (bits 9 to 5)
-- string_current_z := to_integer(unsigned(ram_dat_r(9 downto 5)));
-- if string_abbreviation /= 0 then -- prev char was abbreviation char
-- string_back := pc;
-- string_in_abbr := true;
-- pc := abbreviations(32 * (string_abbreviation - 1) + string_current_z); -- address of the "32(z-1)+n"th abbreviation
-- string_abbreviation := 0;
-- else
-- case string_current_z is
-- when 0 => -- space
-- string_buffer(string_pointer) = ' '
-- string_pointer := string_pointer + 1;
-- when 1 to 3 => -- abbreviation character
-- if string_in_abbr then
-- state := ERROR;
-- message := pad_string("Abbreviation inside abbreviation.", message'LENGTH);
-- end if;
-- string_abbreviation := string_current_z;
-- when 4 => -- alphabet shift to 1
-- string_alphabet := 1;
-- when 5 => -- alphabet shift to 2
-- string_alphabet := 2;
-- when 6 to 31 => -- regular character
-- if string_alphabet = 2 and z = 6 then
-- string_zscii = 2;
-- end if;
-- string_buffer(string_pointer) = alphabets(string_alphabet, string_current_z);
-- string_pointer := string_pointer + 1;
-- end case;
-- end if;
-- ---------------------------------------------------------------------------------------------------------
-- z := to_integer(unsigned(ram_dat_r(14 downto 10)))
-- z := to_integer(unsigned(ram_dat_r(9 downto 5)))
-- z := to_integer(unsigned(ram_dat_r(4 downto 0)))
-- if string_abbreviation /= 0 then -- prev char was abbreviation char
-- string_back := pc;
-- string_back_inner := 1;
-- string_in_abbr := true;
-- pc := abbreviations(32 * (string_abbreviation - 1) + z); -- set pc to the address of the "32(z-1)+n"th abbreviation
-- string_abbreviation := 0;
-- else -- previous char was normal
-- case z is
-- when 0 => -- space
-- string_buffer(string_pointer) = ' '
-- string_pointer := string_pointer + 1;
-- when 1 to 3 => -- abbreviation character
-- if string_in_abbr then
-- state := ERROR;
-- message := pad_string("Abbreviation inside abbreviation.", message'LENGTH);
-- end if;
-- string_abbreviation := z;
-- when 4 => -- alphabet shift to 1
-- string_alphabet := 1;
-- when 5 => -- alphabet shift to 2
-- string_alphabet := 2;
-- when 6 to 31 => -- regular character
-- if string_alphabet = 2 and z = 6 then
-- string_zscii = 2;
-- end if;
-- string_buffer(string_pointer) = alphabets(string_alphabet, z);
-- string_pointer := string_pointer + 1;
-- end case;
-- end if;
-- if z > 6 then
-- string_buffer(string_pointer) = alphabets(string_alphabet, z);
-- string_pointer := string_pointer + 1;
-- else if z == 1 then
-- end if;
-- string_alphabet := 0;
-- ram_dat_r(14 downto 10) -- z char 1
end if;
ram_re <= "11";
ram_addr <= pc;
-- if no more fetch steps will follow, go to the next stage, don't need to check op0
if not (op1_fetch or op2_fetch or op3_fetch or store_fetch or branch_fetch or string_fetch) then
state := EXEC;
end if;
---------------------------------------------
when FETCH =>
ram_re <= "11";
ram_addr <= pc;
state := DECODE;
if pc > length then
cursor := 0;
state := ERROR;
message := pad_string("PC > length?", message'LENGTH);
end if;
---------------------------------------------
when DECODE =>
state := FETCH_OP;
pc := pc + 1;
ram_re <= "11";
ram_addr <= pc;
instruction_raw := ram_dat_r(15 downto 8);
-- Short form ------------------------
if ram_dat_r(15 downto 14) = "10" then
-- 0OP ------------------------------
if ram_dat_r(13 downto 12) = "11" then
case to_integer(unsigned(ram_dat_r(11 downto 9))) is
when 0 => -- rtrue
instruction := OP_NOP;
ret := true;
op0 := "0000000000000001";
op0_type := TYPE_SML_CNT;
when 1 => -- rfalse
instruction := OP_NOP;
ret := true;
op0 := "0000000000000000";
op0_type := TYPE_SML_CNT;
when 2 => -- print (literal-string)
instruction := OP_PRINT;
string_fetch := true;
when 3 => -- print_ret (literal-string)
instruction := OP_PRINT;
string_fetch := true;
ret := true;
op0 := "0000000000000001";
op0_type := TYPE_SML_CNT;
when 4 => -- nop
instruction := OP_NOP;
when 5 => -- save ?(label) -- TODO
instruction := OP_NOP;
branch := true;
branch_fetch := true;
-- branch_on_true := ram_dat_r(7) = '1';
-- branch_fetch := ram_dat_r(6) = '0';
-- branch_offset := "0000000000" & ram_dat_r(5 downto 0);
when 6 => -- save ?(label) -- TODO
instruction := OP_NOP;
branch := true;
branch_fetch := true;
-- branch_on_true := ram_dat_r(7) = '1';
-- branch_fetch := ram_dat_r(6) = '0';
-- branch_offset := "0000000000" & ram_dat_r(5 downto 0);
when 7 => -- restart -- TODO
instruction := OP_NOP;
state := ERROR;
message := pad_string("Power cycling is the restart in this universe!", message'LENGTH, ram_dat_r);
when 8 => -- ret_popped
instruction := OP_POP;
ret := true;
when 9 => -- pop
instruction := OP_POP;
when 10 =>
instruction := OP_NOP;
state := ERROR;
message := pad_string("It is now safe to power off your computer.", message'LENGTH, ram_dat_r);
when 11 =>
instruction := OP_PRINT_NL;
when 12 =>
instruction := OP_STATUS;
when 13 =>
instruction := OP_VERIFY;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Short, 0OP", message'LENGTH, ram_dat_r);
end case;
-- 1OP ------------------------------
else
op0_type := ram_dat_r(11 downto 10);
if op0_type /= TYPE_LRG_CNT then -- NOT Lage constant that will require later fetching, BUT Variable or small constant
op0 := "00000000" & ram_dat_r(7 downto 0);
pc := pc + 1; -- Increment PC again, since the 2nd byte of the word we got is (part of) the operand
else
op0_fetch := true;
end if;
ram_re <= "11";
ram_addr <= pc;
case to_integer(unsigned(ram_dat_r(9 downto 8))) is
when 0 =>
instruction := OP_COMP_ZERO;
branch := true;
when 1 =>
instruction := OP_GET_SIBLING;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 2 =>
instruction := OP_GET_CHILD;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 3 =>
instruction := OP_GET_PARENT;
store := true;
store_fetch := true;
when 4 =>
instruction := OP_GET_PROP_LEN;
store := true;
store_fetch := true;
when 5 =>
instruction := OP_INC;
when 6 =>
instruction := OP_DEC;
when 7 =>
instruction := OP_PRINT_ADDR;
when 9 =>
instruction := OP_REMOVE_OBJ;
when 10 =>
instruction := OP_PRINT_OBJ;
when 11 =>
instruction := OP_NOP;
ret := true;
when 12 =>
instruction := OP_JUMP;
when 13 =>
instruction := OP_PRINT_PADDR;
when 14 =>
instruction := OP_LOAD;
store := true;
store_fetch := true;
when 15 =>
instruction := OP_NOT_BW;
store := true;
store_fetch := true;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Short, 1OP", message'LENGTH, ram_dat_r);
end case;
end if;
-- Variable form ---------------------
elsif ram_dat_r(15 downto 14) = "11" then
pc := pc + 1; -- second byte was type info, inc again
ram_re <= "11";
ram_addr <= pc;
op0_type := ram_dat_r(7 downto 6);
op1_type := ram_dat_r(5 downto 4);
op2_type := ram_dat_r(3 downto 2);
op3_type := ram_dat_r(1 downto 0);
if op0_type /= TYPE_OMITTED then
op0_fetch := true;
end if;
if op1_type /= TYPE_OMITTED then
op1_fetch := true;
end if;
if op2_type /= TYPE_OMITTED then
op2_fetch := true;
end if;
if op3_type /= TYPE_OMITTED then
op3_fetch := true;
end if;
-- VAR ------------------------------
if ram_dat_r(13) = '1' then
case to_integer(unsigned(ram_dat_r(12 downto 8))) is
when 0 => -- call routine ...0 to 3 args... -> (result)
instruction := OP_CALL;
store := true;
store_fetch := true;
when 1 => -- storew array word-index value
instruction := OP_STOREW;
when 2 => -- storeb array byte-index value
instruction := OP_STOREB;
when 3 => -- put_prop object property value
instruction := OP_PUT_PROP;
when 4 => -- sread text parse
instruction := OP_SREAD;
when 5 => -- print_char output-character-code
instruction := OP_PRINT_CHAR;
when 6 => -- print_num value
instruction := OP_PRINT_NUM;
when 7 => -- random range -> (result)
instruction := OP_RND;
store := true;
store_fetch := true;
when 8 => -- push value
instruction := OP_PUSH;
when 9 => -- pull (variable)
instruction := OP_PULL;
when 10 => -- split_window lines
instruction := OP_SPLIT_WINDOW;
when 11 => -- set_window window
instruction := OP_SET_WINDOW;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Variable, VAR", message'LENGTH, ram_dat_r);
end case;
-- 2OP ------------------------------
else
-- TODO ??? Is this correct ??
case to_integer(unsigned(ram_dat_r(12 downto 8))) is
when 0 =>
instruction := OP_COMP_ZERO;
branch := true;
when 1 =>
instruction := OP_GET_SIBLING;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 2 =>
instruction := OP_GET_CHILD;
store := true;
store_fetch := true;
branch := true;
branch_fetch := true;
when 3 =>
instruction := OP_GET_PARENT;
store := true;
store_fetch := true;
when 4 =>
instruction := OP_GET_PROP_LEN;
store := true;
store_fetch := true;
when 5 =>
instruction := OP_INC;
when 6 =>
instruction := OP_DEC;
when 7 =>
instruction := OP_PRINT_ADDR;
when 9 =>
instruction := OP_REMOVE_OBJ;
when 10 =>
instruction := OP_PRINT_OBJ;
when 11 =>
instruction := OP_NOP;
ret := true;
when 12 =>
instruction := OP_JUMP;
when 13 =>
instruction := OP_PRINT_PADDR;
when 14 =>
instruction := OP_LOAD;
store := true;
store_fetch := true;
when 15 =>
instruction := OP_NOT_BW;
store := true;
store_fetch := true;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Variable, 2OP", message'LENGTH, ram_dat_r);
end case;
end if;
-- Long form -------------------------
else -- Always 2OP
op0_fetch := true;
op1_fetch := true;
-- Type OP 1
if ram_dat_r(14) = '0' then
op0_type := "01";
else
op0_type := "10";
end if;
-- Type OP 2
if ram_dat_r(13) = '0' then
op1_type := "01";
else
op1_type := "10";
end if;
case to_integer(unsigned(ram_dat_r(12 downto 8))) is
when 1 => -- je a b ?(label)
instruction := OP_COMP_EQ;
branch := true;
branch_fetch := true;
when 2 => -- jl a b ?(label)
instruction := OP_COMP_LT;
branch := true;
branch_fetch := true;
when 3 => -- jg a b ?(label)
instruction := OP_COMP_GT;
branch := true;
branch_fetch := true;
when 4 => -- dec_chk (variable) value ?(label)
instruction := OP_DEC_CHK;
branch := true;
branch_fetch := true;
when 5 => -- inc_chk (variable) value ?(label)
instruction := OP_INC_CHK;
branch := true;
branch_fetch := true;
when 6 => -- jin obj1 obj2 ?(label)
instruction := OP_JIN;
branch := true;
branch_fetch := true;
when 7 => -- test bitmap flags ?(label)
instruction := OP_TEST;
branch := true;
branch_fetch := true;
when 8 => -- or a b -> (result)
instruction := OP_OR_BW;
store := true;
store_fetch := true;
when 9 => -- and a b -> (result)
instruction := OP_AND_BW;
store := true;
store_fetch := true;
when 10 => -- test_attr object attribute ?(label)
instruction := OP_TEST_ATTR;
branch := true;
branch_fetch := true;
when 11 => -- set_attr object attribute
instruction := OP_SET_ATTR;
when 12 => -- set_attr object attribute
instruction := OP_CLEAR_ATTR;
when 13 => -- set_attr object attribute
instruction := OP_STORE;
when 14 => -- insert_obj object destination
instruction := OP_INSERT_OBJ;
when 15 => -- loadw array word-index -> (result)
instruction := OP_LOADW;
store := true;
store_fetch := true;
when 16 => -- loadb array byte-index -> (result)
instruction := OP_LOADB;
store := true;
store_fetch := true;
when 17 => -- get_prop object property -> (result)
instruction := OP_GET_PROP;
store := true;
store_fetch := true;
when 18 => -- get_prop_addr object property -> (result)
instruction := OP_GET_PROP_ADDR;
store := true;
store_fetch := true;
when 19 => -- get_next_prop object property -> (result)
instruction := OP_GET_NEXT_PROP;
store := true;
store_fetch := true;
when 20 => -- add a b -> (result)
instruction := OP_ADD;
store := true;
store_fetch := true;
when 21 => -- sub a b -> (result)
instruction := OP_SUB;
store := true;
store_fetch := true;
when 22 => -- mul a b -> (result)
instruction := OP_MUL;
store := true;
store_fetch := true;
when 23 => -- div a b -> (result)
instruction := OP_DIV;
store := true;
store_fetch := true;
when 24 => -- mod a b -> (result)
instruction := OP_MOD;
store := true;
store_fetch := true;
when others =>
cursor := 0;
state := ERROR;
message := pad_string("Instruction undecodable. Long", message'LENGTH, ram_dat_r);
end case;
end if;
---------------------------------------------------------------------------------------------------------------------------------------
-- INTERPRETER STATES
---------------------------------------------
when RESET => -- splash screen
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_dat_in <= clk_1 & std_logic_vector(to_unsigned(character'pos(blinkData(cursor + 1)), 7));
fb_a_addr <= std_logic_vector(to_unsigned(cursor + COLS * 21 + 66, 14));
cursor := cursor_delta(cursor, modulo => blinkData'LENGTH);
if kb_event = '1' then
cursor := 0;
state := BLANK;
next_state := LOAD;
end if;
---------------------------------------------
when BLANK => -- erase all of the screen
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
fb_a_dat_in <= x"00";
cursor := cursor_delta(cursor);
if cursor = 0 then
state := next_state;
next_state := RESET;
end if;
---------------------------------------------
when ERROR =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_dat_in <= '1' & std_logic_vector(to_unsigned(character'pos(message(cursor + 1)), 7));
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
cursor := cursor_delta(cursor, modulo => message'LENGTH);
if cursor = 0 then
cursor := COLS;
state := DEBUG;
end if;
---------------------------------------------
when LOAD =>
cursor := cursor_delta(cursor);
ram_re <= "11";
case cursor is
when 1 =>
ram_re <= "10";
ram_addr <= 16#00#;
when 2 =>
if ram_dat_r(15 downto 8) /= x"03" then
cursor := 0;
state := ERROR;
message := pad_string("Version != 3", message'LENGTH);
end if;
ram_addr <= 16#01#; -- Flags 1
when 3 =>
ram_re <= "00";
flags1 := ram_dat_r;
-- SET FLAGS 1 BITS
flags1(4) := '0';
flags1(5) := '0';
flags1(6) := '0';
ram_dat_w <= flags1;
ram_we <= "11";
when 4 =>
ram_addr <= 16#04#; -- Base of high memory (byte address)
when 5 =>
high := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#06#; -- Initial value of program counter (byte address)
when 6 =>
pc := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#08#; -- Location of dictionary (byte address)
when 7 =>
dict := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#0A#; -- Location of object table (byte address)
when 8 =>
objtab := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#0C#; -- Location of global variables table (byte address)
when 9 =>
globals := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#0E#; -- Base of static memory (byte address)
when 10 =>
static := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#10#; -- Flags 2
when 11 =>
flags2 := ram_dat_r;
ram_addr <= 16#18#; -- Location of abbreviations table (byte address)
when 12 =>
abbreviations_start := to_integer(unsigned(ram_dat_r));
ram_addr <= 16#1A#; -- Length of file, Not always available
when 13 =>
length := 2 * to_integer(unsigned(ram_dat_r));
ram_addr <= 16#1C#; -- Checksum, Not always available
when 14 =>
checksum := to_integer(unsigned(ram_dat_r));
when 15 => -- HEADER LOADED
ram_addr <= abbreviations_start;
state := LOAD_ABBR;
cursor := 0;
-- ram_re <= "00";
-- cursor := 0;
-- state := FETCH;
when others =>
ram_re <= "00";
cursor := 0;
state := ERROR;
message := pad_string("Illegal load state.", message'LENGTH);
end case;
---------------------------------------------
when LOAD_ABBR =>
ram_re <= "11";
-- because the abbreviations are always 2n bytes long, they devided the address by 2.
abbreviations(cursor) := 2 * to_integer(unsigned(ram_dat_r));
if cursor = 96 then
ram_re <= "00";
cursor := 0;
state := FETCH;
else
ram_addr <= ram_addr + 2;
cursor := cursor_delta(cursor);
end if;
---------------------------------------------
when SCROLL => -- move all of the screen up one row, read part
fb_a_en <= '1';
-- Read next line's char
fb_a_addr <= std_logic_vector(to_unsigned((cursor + COLS) mod CHARS, 14));
state := SCROLL_W;
when SCROLL_W => -- Write part of scroll state
fb_a_en <= '1';
-- Write current char
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
-- Last line is special
if cursor > COLS * (ROWS - 1) then
fb_a_dat_in <= x"00";
-- Last character is the exit condition
if cursor = CHARS - 1 then
-- Wrap cursor to fist col, last line
cursor := (ROWS - 1) * COLS;
state := next_state;
next_state := RESET;
-- Last line doesn't need to go back to read the mem
else
cursor := cursor_delta(cursor);
state := SCROLL_W;
end if;
-- Copy data
else
cursor := cursor_delta(cursor);
fb_a_dat_in <= fb_a_dat_out;
state := SCROLL;
end if;
---------------------------------------------
when DEBUG =>
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
fb_a_dat_in <= (others => '0');
case cursor is
when 0 to COLS - 1 => -- Leave top line
fb_a_en <= '0';
fb_a_we <= "0";
when COLS + 0 => fb_a_dat_in <= ascii_c('F');
when COLS + 1 => fb_a_dat_in <= ascii_c('l');
when COLS + 2 => fb_a_dat_in <= ascii_c('a');
when COLS + 3 => fb_a_dat_in <= ascii_c('g');
when COLS + 4 => fb_a_dat_in <= ascii_c('s');
when COLS + 5 => fb_a_dat_in <= ascii_c('1');
when COLS + 6 => fb_a_dat_in <= ascii_c(':');
when COLS + 16 => fb_a_dat_in <= ascii_b(flags1(15));
when COLS + 17 => fb_a_dat_in <= ascii_b(flags1(14));
when COLS + 18 => fb_a_dat_in <= ascii_b(flags1(13));
when COLS + 19 => fb_a_dat_in <= ascii_b(flags1(12));
when COLS + 20 => fb_a_dat_in <= ascii_b(flags1(11));
when COLS + 21 => fb_a_dat_in <= ascii_b(flags1(10));
when COLS + 22 => fb_a_dat_in <= ascii_b(flags1(9));
when COLS + 23 => fb_a_dat_in <= ascii_b(flags1(8));
when COLS + 24 => fb_a_dat_in <= ascii_b(flags1(7));
when COLS + 25 => fb_a_dat_in <= ascii_b(flags1(6));
when COLS + 26 => fb_a_dat_in <= ascii_b(flags1(5));
when COLS + 27 => fb_a_dat_in <= ascii_b(flags1(4));
when COLS + 28 => fb_a_dat_in <= ascii_b(flags1(3));
when COLS + 29 => fb_a_dat_in <= ascii_b(flags1(2));
when COLS + 30 => fb_a_dat_in <= ascii_b(flags1(1));
when COLS + 31 => fb_a_dat_in <= ascii_b(flags1(0));
when 2 * COLS + 0 => fb_a_dat_in <= ascii_c('F');
when 2 * COLS + 1 => fb_a_dat_in <= ascii_c('l');
when 2 * COLS + 2 => fb_a_dat_in <= ascii_c('a');
when 2 * COLS + 3 => fb_a_dat_in <= ascii_c('g');
when 2 * COLS + 4 => fb_a_dat_in <= ascii_c('s');
when 2 * COLS + 5 => fb_a_dat_in <= ascii_c('2');
when 2 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 2 * COLS + 16 => fb_a_dat_in <= ascii_b(flags2(15));
when 2 * COLS + 17 => fb_a_dat_in <= ascii_b(flags2(14));
when 2 * COLS + 18 => fb_a_dat_in <= ascii_b(flags2(13));
when 2 * COLS + 19 => fb_a_dat_in <= ascii_b(flags2(12));
when 2 * COLS + 20 => fb_a_dat_in <= ascii_b(flags2(11));
when 2 * COLS + 21 => fb_a_dat_in <= ascii_b(flags2(10));
when 2 * COLS + 22 => fb_a_dat_in <= ascii_b(flags2(9));
when 2 * COLS + 23 => fb_a_dat_in <= ascii_b(flags2(8));
when 2 * COLS + 24 => fb_a_dat_in <= ascii_b(flags2(7));
when 2 * COLS + 25 => fb_a_dat_in <= ascii_b(flags2(6));
when 2 * COLS + 26 => fb_a_dat_in <= ascii_b(flags2(5));
when 2 * COLS + 27 => fb_a_dat_in <= ascii_b(flags2(4));
when 2 * COLS + 28 => fb_a_dat_in <= ascii_b(flags2(3));
when 2 * COLS + 29 => fb_a_dat_in <= ascii_b(flags2(2));
when 2 * COLS + 30 => fb_a_dat_in <= ascii_b(flags2(1));
when 2 * COLS + 31 => fb_a_dat_in <= ascii_b(flags2(0));
when 3 * COLS + 0 => fb_a_dat_in <= ascii_c('H');
when 3 * COLS + 1 => fb_a_dat_in <= ascii_c('i');
when 3 * COLS + 2 => fb_a_dat_in <= ascii_c('g');
when 3 * COLS + 3 => fb_a_dat_in <= ascii_c('h');
when 3 * COLS + 4 => fb_a_dat_in <= ascii_c(':');
when 3 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 3 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 3 * COLS + 18 => fb_a_dat_in <= ascii_x(high, 3);
when 3 * COLS + 19 => fb_a_dat_in <= ascii_x(high, 2);
when 3 * COLS + 20 => fb_a_dat_in <= ascii_x(high, 1);
when 3 * COLS + 21 => fb_a_dat_in <= ascii_x(high, 0);
when 4 * COLS + 0 => fb_a_dat_in <= ascii_c('P');
when 4 * COLS + 1 => fb_a_dat_in <= ascii_c('C');
when 4 * COLS + 2 => fb_a_dat_in <= ascii_c(':');
when 4 * COLS + 3 => fb_a_dat_in <= ascii_c(' ');
when 4 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 4 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 4 * COLS + 18 => fb_a_dat_in <= ascii_x(pc, 3);
when 4 * COLS + 19 => fb_a_dat_in <= ascii_x(pc, 2);
when 4 * COLS + 20 => fb_a_dat_in <= ascii_x(pc, 1);
when 4 * COLS + 21 => fb_a_dat_in <= ascii_x(pc, 0);
when 5 * COLS + 0 => fb_a_dat_in <= ascii_c('D');
when 5 * COLS + 1 => fb_a_dat_in <= ascii_c('i');
when 5 * COLS + 2 => fb_a_dat_in <= ascii_c('c');
when 5 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 5 * COLS + 4 => fb_a_dat_in <= ascii_c(':');
when 5 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 5 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 5 * COLS + 18 => fb_a_dat_in <= ascii_x(dict, 3);
when 5 * COLS + 19 => fb_a_dat_in <= ascii_x(dict, 2);
when 5 * COLS + 20 => fb_a_dat_in <= ascii_x(dict, 1);
when 5 * COLS + 21 => fb_a_dat_in <= ascii_x(dict, 0);
when 6 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 6 * COLS + 1 => fb_a_dat_in <= ascii_c('b');
when 6 * COLS + 2 => fb_a_dat_in <= ascii_c('j');
when 6 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 6 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 6 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 6 * COLS + 18 => fb_a_dat_in <= ascii_x(objtab, 3);
when 6 * COLS + 19 => fb_a_dat_in <= ascii_x(objtab, 2);
when 6 * COLS + 20 => fb_a_dat_in <= ascii_x(objtab, 1);
when 6 * COLS + 21 => fb_a_dat_in <= ascii_x(objtab, 0);
when 7 * COLS + 0 => fb_a_dat_in <= ascii_c('G');
when 7 * COLS + 1 => fb_a_dat_in <= ascii_c('l');
when 7 * COLS + 2 => fb_a_dat_in <= ascii_c('o');
when 7 * COLS + 3 => fb_a_dat_in <= ascii_c('b');
when 7 * COLS + 4 => fb_a_dat_in <= ascii_c('a');
when 7 * COLS + 5 => fb_a_dat_in <= ascii_c('l');
when 7 * COLS + 6 => fb_a_dat_in <= ascii_c('s');
when 7 * COLS + 7 => fb_a_dat_in <= ascii_c(':');
when 7 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 7 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 7 * COLS + 18 => fb_a_dat_in <= ascii_x(globals, 3);
when 7 * COLS + 19 => fb_a_dat_in <= ascii_x(globals, 2);
when 7 * COLS + 20 => fb_a_dat_in <= ascii_x(globals, 1);
when 7 * COLS + 21 => fb_a_dat_in <= ascii_x(globals, 0);
when 8 * COLS + 0 => fb_a_dat_in <= ascii_c('S');
when 8 * COLS + 1 => fb_a_dat_in <= ascii_c('t');
when 8 * COLS + 2 => fb_a_dat_in <= ascii_c('a');
when 8 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 8 * COLS + 4 => fb_a_dat_in <= ascii_c('i');
when 8 * COLS + 5 => fb_a_dat_in <= ascii_c('c');
when 8 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 8 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 8 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 8 * COLS + 18 => fb_a_dat_in <= ascii_x(static, 3);
when 8 * COLS + 19 => fb_a_dat_in <= ascii_x(static, 2);
when 8 * COLS + 20 => fb_a_dat_in <= ascii_x(static, 1);
when 8 * COLS + 21 => fb_a_dat_in <= ascii_x(static, 0);
when 9 * COLS + 0 => fb_a_dat_in <= ascii_c('A');
when 9 * COLS + 1 => fb_a_dat_in <= ascii_c('b');
when 9 * COLS + 2 => fb_a_dat_in <= ascii_c('b');
when 9 * COLS + 3 => fb_a_dat_in <= ascii_c('r');
when 9 * COLS + 4 => fb_a_dat_in <= ascii_c('e');
when 9 * COLS + 5 => fb_a_dat_in <= ascii_c('v');
when 9 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 9 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 9 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 9 * COLS + 18 => fb_a_dat_in <= ascii_x(abbreviations_start, 3);
when 9 * COLS + 19 => fb_a_dat_in <= ascii_x(abbreviations_start, 2);
when 9 * COLS + 20 => fb_a_dat_in <= ascii_x(abbreviations_start, 1);
when 9 * COLS + 21 => fb_a_dat_in <= ascii_x(abbreviations_start, 0);
when 10 * COLS + 0 => fb_a_dat_in <= ascii_c('L');
when 10 * COLS + 1 => fb_a_dat_in <= ascii_c('e');
when 10 * COLS + 2 => fb_a_dat_in <= ascii_c('n');
when 10 * COLS + 3 => fb_a_dat_in <= ascii_c('g');
when 10 * COLS + 4 => fb_a_dat_in <= ascii_c('t');
when 10 * COLS + 5 => fb_a_dat_in <= ascii_c('h');
when 10 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 10 * COLS + 16 => fb_a_dat_in <= ascii_i(length, 4);
when 10 * COLS + 17 => fb_a_dat_in <= ascii_i(length, 3);
when 10 * COLS + 18 => fb_a_dat_in <= ascii_i(length, 2);
when 10 * COLS + 19 => fb_a_dat_in <= ascii_i(length, 1);
when 10 * COLS + 20 => fb_a_dat_in <= ascii_i(length, 0);
when 11 * COLS + 0 => fb_a_dat_in <= ascii_c('C');
when 11 * COLS + 1 => fb_a_dat_in <= ascii_c('h');
when 11 * COLS + 2 => fb_a_dat_in <= ascii_c('e');
when 11 * COLS + 3 => fb_a_dat_in <= ascii_c('c');
when 11 * COLS + 4 => fb_a_dat_in <= ascii_c('k');
when 11 * COLS + 5 => fb_a_dat_in <= ascii_c('s');
when 11 * COLS + 6 => fb_a_dat_in <= ascii_c('u');
when 11 * COLS + 7 => fb_a_dat_in <= ascii_c('m');
when 11 * COLS + 8 => fb_a_dat_in <= ascii_c(':');
when 11 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 11 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 11 * COLS + 18 => fb_a_dat_in <= ascii_x(checksum, 3);
when 11 * COLS + 19 => fb_a_dat_in <= ascii_x(checksum, 2);
when 11 * COLS + 20 => fb_a_dat_in <= ascii_x(checksum, 1);
when 11 * COLS + 21 => fb_a_dat_in <= ascii_x(checksum, 0);
when 12 * COLS + 0 => fb_a_dat_in <= ascii_c('R');
when 12 * COLS + 1 => fb_a_dat_in <= ascii_c('A');
when 12 * COLS + 2 => fb_a_dat_in <= ascii_c('M');
when 12 * COLS + 3 => fb_a_dat_in <= ascii_c(' ');
when 12 * COLS + 4 => fb_a_dat_in <= ascii_c('R');
when 12 * COLS + 5 => fb_a_dat_in <= ascii_c('e');
when 12 * COLS + 6 => fb_a_dat_in <= ascii_c('a');
when 12 * COLS + 7 => fb_a_dat_in <= ascii_c('d');
when 12 * COLS + 8 => fb_a_dat_in <= ascii_c(':');
when 12 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 12 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 12 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 3);
when 12 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 2);
when 12 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 1);
when 12 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(ram_dat_r)), 0);
when 12 * COLS + 32 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 4);
when 12 * COLS + 33 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 3);
when 12 * COLS + 34 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 2);
when 12 * COLS + 35 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 1);
when 12 * COLS + 36 => fb_a_dat_in <= ascii_i(to_integer(unsigned(ram_dat_r)), 0);
when 13 * COLS + 0 => fb_a_dat_in <= ascii_c('I');
when 13 * COLS + 1 => fb_a_dat_in <= ascii_c('n');
when 13 * COLS + 2 => fb_a_dat_in <= ascii_c('s');
when 13 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 13 * COLS + 4 => fb_a_dat_in <= ascii_c('r');
when 13 * COLS + 5 => fb_a_dat_in <= ascii_c('u');
when 13 * COLS + 6 => fb_a_dat_in <= ascii_c('c');
when 13 * COLS + 7 => fb_a_dat_in <= ascii_c('t');
when 13 * COLS + 8 => fb_a_dat_in <= ascii_c('i');
when 13 * COLS + 9 => fb_a_dat_in <= ascii_c('o');
when 13 * COLS + 10 => fb_a_dat_in <= ascii_c('n');
when 13 * COLS + 11 => fb_a_dat_in <= ascii_c(':');
when 13 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 13 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 13 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(instruction_raw)), 1);
when 13 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(instruction_raw)), 0);
when 14 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 14 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 14 * COLS + 2 => fb_a_dat_in <= ascii_c('0');
when 14 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 14 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 14 * COLS + 5 => fb_a_dat_in <= ascii_b(op0_type(1));
when 14 * COLS + 6 => fb_a_dat_in <= ascii_b(op0_type(0));
when 14 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 14 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 14 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 3);
when 14 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 2);
when 14 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 1);
when 14 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op0)), 0);
when 15 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 15 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 15 * COLS + 2 => fb_a_dat_in <= ascii_c('1');
when 15 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 15 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 15 * COLS + 5 => fb_a_dat_in <= ascii_b(op1_type(1));
when 15 * COLS + 6 => fb_a_dat_in <= ascii_b(op1_type(0));
when 15 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 15 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 15 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 3);
when 15 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 2);
when 15 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 1);
when 15 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op1)), 0);
when 16 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 16 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 16 * COLS + 2 => fb_a_dat_in <= ascii_c('2');
when 16 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 16 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 16 * COLS + 5 => fb_a_dat_in <= ascii_b(op2_type(1));
when 16 * COLS + 6 => fb_a_dat_in <= ascii_b(op2_type(0));
when 16 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 16 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 16 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 3);
when 16 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 2);
when 16 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 1);
when 16 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op2)), 0);
when 17 * COLS + 0 => fb_a_dat_in <= ascii_c('O');
when 17 * COLS + 1 => fb_a_dat_in <= ascii_c('P');
when 17 * COLS + 2 => fb_a_dat_in <= ascii_c('3');
when 17 * COLS + 3 => fb_a_dat_in <= ascii_c(':');
when 17 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 17 * COLS + 5 => fb_a_dat_in <= ascii_b(op3_type(1));
when 17 * COLS + 6 => fb_a_dat_in <= ascii_b(op3_type(0));
when 17 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 17 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 17 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 3);
when 17 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 2);
when 17 * COLS + 20 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 1);
when 17 * COLS + 21 => fb_a_dat_in <= ascii_x(to_integer(unsigned(op3)), 0);
when 18 * COLS + 0 => fb_a_dat_in <= ascii_c('S');
when 18 * COLS + 1 => fb_a_dat_in <= ascii_c('t');
when 18 * COLS + 2 => fb_a_dat_in <= ascii_c('o');
when 18 * COLS + 3 => fb_a_dat_in <= ascii_c('r');
when 18 * COLS + 4 => fb_a_dat_in <= ascii_c('e');
when 18 * COLS + 5 => fb_a_dat_in <= ascii_c(':');
when 18 * COLS + 6 => fb_a_dat_in <= ascii_c(' ');
when 18 * COLS + 16 => fb_a_dat_in <= ascii_c('0');
when 18 * COLS + 17 => fb_a_dat_in <= ascii_c('x');
when 18 * COLS + 18 => fb_a_dat_in <= ascii_x(to_integer(unsigned(store_var)), 1);
when 18 * COLS + 19 => fb_a_dat_in <= ascii_x(to_integer(unsigned(store_var)), 0);
when 19 * COLS + 0 => fb_a_dat_in <= ascii_c('B');
when 19 * COLS + 1 => fb_a_dat_in <= ascii_c('r');
when 19 * COLS + 2 => fb_a_dat_in <= ascii_c('a');
when 19 * COLS + 3 => fb_a_dat_in <= ascii_c('n');
when 19 * COLS + 4 => fb_a_dat_in <= ascii_c('c');
when 19 * COLS + 5 => fb_a_dat_in <= ascii_c('h');
when 19 * COLS + 6 => fb_a_dat_in <= ascii_c(':');
when 19 * COLS + 7 => fb_a_dat_in <= ascii_c(' ');
when 19 * COLS + 16 => fb_a_dat_in <= ascii_i(branch_offset, 6, false, true);
when 19 * COLS + 17 => fb_a_dat_in <= ascii_i(branch_offset, 5);
when 19 * COLS + 18 => fb_a_dat_in <= ascii_i(branch_offset, 4);
when 19 * COLS + 19 => fb_a_dat_in <= ascii_i(branch_offset, 3);
when 19 * COLS + 20 => fb_a_dat_in <= ascii_i(branch_offset, 2);
when 19 * COLS + 21 => fb_a_dat_in <= ascii_i(branch_offset, 1);
when 19 * COLS + 22 => fb_a_dat_in <= ascii_i(branch_offset, 0);
when 20 * COLS + 0 => fb_a_dat_in <= ascii_c('T');
when 20 * COLS + 1 => fb_a_dat_in <= ascii_c('e');
when 20 * COLS + 2 => fb_a_dat_in <= ascii_c('x');
when 20 * COLS + 3 => fb_a_dat_in <= ascii_c('t');
when 20 * COLS + 4 => fb_a_dat_in <= ascii_c(' ');
when 20 * COLS + 5 => fb_a_dat_in <= ascii_c('s');
when 20 * COLS + 6 => fb_a_dat_in <= ascii_c('i');
when 20 * COLS + 7 => fb_a_dat_in <= ascii_c('z');
when 20 * COLS + 8 => fb_a_dat_in <= ascii_c('e');
when 20 * COLS + 10 => fb_a_dat_in <= ascii_i(string_pointer, 4);
when 20 * COLS + 11 => fb_a_dat_in <= ascii_i(string_pointer, 3);
when 20 * COLS + 12 => fb_a_dat_in <= ascii_i(string_pointer, 2);
when 20 * COLS + 13 => fb_a_dat_in <= ascii_i(string_pointer, 1);
when 20 * COLS + 14 => fb_a_dat_in <= ascii_i(string_pointer, 0);
when 21 * COLS to (22 * COLS) - 1 => fb_a_dat_in <= ascii_c(string_buffer(cursor - (21 * COLS)));
when others =>
-- Nothing
end case;
cursor := cursor_delta(cursor);
if cursor = 0 then
state := DEBUG_KB;
cursor := 32 * COLS;
end if;
when DEBUG_KB =>
if kb_event = '1' then
-- By default, we want to write a space to the current position
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
fb_a_dat_in <= "00100000"; -- space
-- IF Backspace
if kb_acsii = "0001000" then
cursor := cursor_delta(cursor, -1);
-- ELSE IF Enter (treated like carage return, not line feed)
elsif kb_acsii = "0001101" then
if cursor / COLS = (ROWS - 1) then
state := SCROLL;
next_state := DEBUG_KB;
cursor := 0;
else
cursor := cursor_delta(cursor, COLS - (cursor mod COLS));
end if;
-- ELSE IF NULL Continue
elsif kb_acsii = "0000000" then
state := FETCH;
-- ELSE IF Delete (wipe whole screen)
elsif kb_acsii = "1111111" then
fb_a_en <= '0';
fb_a_we <= "0";
cursor := 0;
state := BLANK;
next_state := DEBUG_KB;
-- OTHERWISE print character to screen
else
fb_a_dat_in <= '0' & kb_acsii;
cursor := cursor_delta(cursor);
end if;
-- No kb event, blink cursors
else
fb_a_en <= '1';
fb_a_we <= "1";
fb_a_addr <= std_logic_vector(to_unsigned(cursor, 14));
if clk_2 = '1' then
fb_a_dat_in <= "00100000"; -- space
else
fb_a_dat_in <= "01011111"; -- underscore
end if;
end if;
---------------------------------------------
when others => -- WTF?
cursor := 0;
state := ERROR;
message := pad_string("Illegal state", message'LENGTH);
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
dc32ed98cb4c3f22803029d8ad549c54
| 0.395444 | 4.142385 | false | false | false | false |
dries007/Basys3
|
VGA/VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
| 1 | 7,660 |
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Wed Mar 02 15:28:43 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0_clk_wiz_0_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
end clk_wiz_0_clk_wiz_0_clk_wiz;
architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 9.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_0 : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v5_2_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_0;
architecture STRUCTURE of clk_wiz_0 is
begin
inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
reset => reset
);
end STRUCTURE;
|
mit
|
c9f223eb4107657de6d0009b6c53e0bd
| 0.64517 | 3.291792 | false | false | false | false |
twlostow/dsi-shield
|
hdl/ip_cores/local/gc_i2c_slave.vhd
| 1 | 17,824 |
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C slave core
--==============================================================================
--
-- author: Theodor Stana ([email protected])
--
-- date of creation: 2013-03-13
--
-- version: 1.0
--
-- description:
--
-- Simple I2C slave interface, providing the basic low-level functionality
-- of the I2C protocol.
--
-- The gc_i2c_slave module waits for a master to initiate a transfer via
-- a start condition. The address is sent next and if the address matches
-- the slave address set via the i2c_addr_i input, the addr_good_p_o output
-- is set. Based on the eighth bit of the first I2C transfer byte, the module
-- then starts shifting in or out each byte in the transfer, setting the
-- r/w_done_p_o output after each received/sent byte.
--
-- For master write (slave read) transfers, the received byte can be read at
-- the rx_byte_o output when the r_done_p_o pin is high. For master read (slave
-- write) transfers, the slave sends the byte at the tx_byte_i input, which
-- should be set when the w_done_p_o output is high, either after I2C address
-- reception, or a successful send of a previous byte.
--
-- dependencies:
-- OHWR general-cores library
--
-- references:
-- [1] The I2C bus specification, version 2.1, NXP Semiconductor, Jan. 2000
-- http://www.nxp.com/documents/other/39340011.pdf
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-13 Theodor Stana File created
-- 2013-11-22 Theodor Stana Changed to sampling SDA on SCL rising edge
--==============================================================================
-- TODO:
-- - Stop condition
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity gc_i2c_slave is
generic
(
-- Length of glitch filter
-- 0 - SCL and SDA lines are passed only through synchronizer
-- 1 - one clk_i glitches filtered
-- 2 - two clk_i glitches filtered
g_gf_len : natural := 0
);
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
ack_i : in std_logic;
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_p_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Pulse outputs signaling various I2C actions
-- Start and stop conditions
i2c_sta_p_o : out std_logic;
i2c_sto_p_o : out std_logic;
-- Received address corresponds i2c_addr_i
addr_good_p_o : out std_logic;
-- Read and write done
r_done_p_o : out std_logic;
w_done_p_o : out std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic
);
end entity gc_i2c_slave;
architecture behav of gc_i2c_slave is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
IDLE, -- idle
ADDR, -- shift in I2C address bits
ADDR_ACK, -- ACK/NACK to I2C address
RD, -- shift in byte to read
RD_ACK, -- ACK/NACK to received byte
WR_LOAD_TXSR, -- load byte to send via I2C
WR, -- shift out byte
WR_ACK -- get ACK/NACK from master
);
--============================================================================
-- Signal declarations
--============================================================================
-- Deglitched signals and delays for SCL and SDA lines
signal scl_synced : std_logic;
signal scl_deglitched : std_logic;
signal scl_deglitched_d0 : std_logic;
signal sda_synced : std_logic;
signal sda_deglitched : std_logic;
signal sda_deglitched_d0 : std_logic;
signal scl_r_edge_p : std_logic;
signal scl_f_edge_p : std_logic;
signal sda_f_edge_p : std_logic;
signal sda_r_edge_p : std_logic;
-- FSM signals
signal state : t_state;
signal inhibit : std_logic;
-- RX and TX shift registers
signal txsr : std_logic_vector(7 downto 0);
signal rxsr : std_logic_vector(7 downto 0);
-- Bit counter on RX & TX
signal bit_cnt : unsigned(2 downto 0);
-- Start and stop condition pulse signals
signal sta_p, sto_p : std_logic;
-- Master ACKed after it has read a byte from the slave
signal mst_acked : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- I/O logic
--============================================================================
-- No clock stretching implemented, always disable SCL line
scl_o <= '0';
scl_en_o <= '0';
-- SDA line driven low; SDA_EN line controls when the tristate buffer is enabled
sda_o <= '0';
-- Assign RX byte output
rx_byte_o <= rxsr;
--============================================================================
-- Deglitching logic
--============================================================================
-- First, synchronize the SCL signal in the clk_i domain
cmp_sync_scl : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => scl_i,
synced_o => scl_synced
);
-- Generate deglitched SCL signal
cmp_scl_deglitch : gc_glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => scl_synced,
dat_o => scl_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling-edge detection signal
p_scl_degl_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
scl_deglitched_d0 <= '0';
scl_f_edge_p <= '0';
scl_r_edge_p <= '0';
else
scl_deglitched_d0 <= scl_deglitched;
scl_f_edge_p <= (not scl_deglitched) and scl_deglitched_d0;
scl_r_edge_p <= scl_deglitched and (not scl_deglitched_d0);
end if;
end if;
end process p_scl_degl_d0;
-- Synchronize SDA signal in clk_i domain
cmp_sda_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => sda_i,
synced_o => sda_synced
);
-- Generate deglitched SDA signal
cmp_sda_deglitch : gc_glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => sda_synced,
dat_o => sda_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling- and rising-edge detection signals
p_sda_deglitched_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sda_deglitched_d0 <= '0';
sda_f_edge_p <= '0';
sda_r_edge_p <= '0';
else
sda_deglitched_d0 <= sda_deglitched;
sda_f_edge_p <= (not sda_deglitched) and sda_deglitched_d0;
sda_r_edge_p <= sda_deglitched and (not sda_deglitched_d0);
end if;
end if;
end process p_sda_deglitched_d0;
--============================================================================
-- Start and stop condition outputs
--============================================================================
-- First the process to set the start and stop conditions as per I2C standard
p_sta_sto : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sta_p <= '0';
sto_p <= '0';
else
sta_p <= sda_f_edge_p and scl_deglitched;
sto_p <= sda_r_edge_p and scl_deglitched;
end if;
end if;
end process p_sta_sto;
-- Finally, set the outputs
i2c_sta_p_o <= sta_p;
i2c_sto_p_o <= sto_p;
--============================================================================
-- FSM logic
--============================================================================
p_fsm: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
inhibit <= '0';
bit_cnt <= (others => '0');
rxsr <= (others => '0');
txsr <= (others => '0');
mst_acked <= '0';
sda_en_o <= '0';
r_done_p_o <= '0';
w_done_p_o <= '0';
addr_good_p_o <= '0';
op_o <= '0';
-- start and stop conditions are followed by I2C address, so any byte
-- following would be an address byte; therefore, it is safe to deinhibit
-- the FSM
elsif (sta_p = '1') or (sto_p = '1') then
state <= IDLE;
inhibit <= '0';
-- state machine logic
else
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
when IDLE =>
-- clear outputs and bit counter
bit_cnt <= (others => '0');
sda_en_o <= '0';
mst_acked <= '0';
r_done_p_o <= '0';
w_done_p_o <= '0';
addr_good_p_o <= '0';
if (scl_f_edge_p = '1') and (inhibit = '0') then
state <= ADDR;
end if;
---------------------------------------------------------------------
-- ADDR
---------------------------------------------------------------------
when ADDR =>
-- Shifting in is done on rising edge of SCL
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
end if;
--
-- Checking the bit counter is done on the falling edge of SCL
--
-- If 8 bits have been shifted in, the received address is checked
-- and the slave goes in the ADDR_ACK state.
--
-- If the address is not ours, go back to IDLE and set inhibit bits
-- so bytes sent to or received from another slave that happen to
-- coincide to the address of this slave don't get interpreted
-- as accesses to this slave.
--
if (scl_f_edge_p = '1') then
if (bit_cnt = 0) then
if (rxsr(7 downto 1) = i2c_addr_i) then
op_o <= rxsr(0);
addr_good_p_o <= '1';
state <= ADDR_ACK;
else
inhibit <= '1';
state <= IDLE;
end if;
end if;
end if;
---------------------------------------------------------------------
-- ADDR_ACK
---------------------------------------------------------------------
when ADDR_ACK =>
-- clear addr_good pulse
addr_good_p_o <= '0';
-- send ACK from input, check the ACK on falling edge and go to
-- loading of the TXSR if the OP bit is a write, or read otherwise
sda_en_o <= ack_i;
if (scl_f_edge_p = '1') then
if (ack_i = '1') then
if (rxsr(0) = '0') then
state <= RD;
else
state <= WR_LOAD_TXSR;
end if;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- RD
---------------------------------------------------------------------
-- Shift in bits sent by the master
---------------------------------------------------------------------
when RD =>
-- not controlling SDA, clear enable signal
sda_en_o <= '0';
-- shift in on rising-edge
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
end if;
if (scl_f_edge_p = '1') then
-- Received 8 bits, go to RD_ACK and signal external module
if (bit_cnt = 0) then
state <= RD_ACK;
r_done_p_o <= '1';
end if;
end if;
---------------------------------------------------------------------
-- RD_ACK
---------------------------------------------------------------------
when RD_ACK =>
-- Clear done pulse
r_done_p_o <= '0';
-- we write the ACK bit, so control sda_en_o signal to send ACK/NACK
sda_en_o <= ack_i;
-- based on the ACK received by external command, we read the next
-- bit (ACK) or go back to idle state (NACK)
if (scl_f_edge_p = '1') then
if (ack_i = '1') then
state <= RD;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- WR_LOAD_TXSR
---------------------------------------------------------------------
when WR_LOAD_TXSR =>
txsr <= tx_byte_i;
state <= WR;
---------------------------------------------------------------------
-- WR
---------------------------------------------------------------------
when WR =>
-- slave writes, SDA output enable is the negated value of the bit
-- to send (since on I2C, '1' is a release of the bus)
sda_en_o <= not txsr(7);
-- increment bit counter on rising edge
if (scl_r_edge_p = '1') then
bit_cnt <= bit_cnt + 1;
end if;
-- Shift TXSR on falling edge of SCL
if (scl_f_edge_p = '1') then
txsr <= txsr(6 downto 0) & '0';
-- Eight bits sent, disable SDA and go to WR_ACK
if (bit_cnt = 0) then
state <= WR_ACK;
w_done_p_o <= '1';
end if;
end if;
---------------------------------------------------------------------
-- WR_ACK
---------------------------------------------------------------------
when WR_ACK =>
-- master controls SDA, clear sda_en_o
sda_en_o <= '0';
-- clear done pulse
w_done_p_o <= '0';
-- sample in ACK from master on rising edge
if (scl_r_edge_p = '1') then
if (sda_deglitched = '0') then
mst_acked <= '1';
else
mst_acked <= '0';
end if;
end if;
-- and check it on falling edge
if (scl_f_edge_p = '1') then
if (mst_acked = '1') then
state <= WR_LOAD_TXSR;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- Any other state: go back to IDLE
---------------------------------------------------------------------
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
|
lgpl-3.0
|
8f6f75ade6301fb3a28f280f50971279
| 0.421174 | 4.328315 | false | false | false | false |
luebbers/reconos
|
demos/demo_multibus_ethernet/hw/hwthreads/third/physical/v6_gtxwizard.vhd
| 1 | 16,310 |
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 1.5
-- \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
-- / / Filename : v6_gtxwizard.vhd
-- /___/ /\ Timestamp :
-- \ \ / \
-- \___\/\___\
--
--
-- Module V6_GTXWIZARD (a GTX Wrapper)
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of,
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--***************************** Entity Declaration ****************************
entity V6_GTXWIZARD is
generic
(
-- Simulation attributes
WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 0 -- Set to 1 to speed up sim reset
);
port
(
--_________________________________________________________________________
--_________________________________________________________________________
--GTX0 (X0Y8)
------------------------ Loopback and Powerdown Ports ----------------------
GTX0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
GTX0_RXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
GTX0_TXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
GTX0_RXCHARISCOMMA_OUT : out std_logic;
GTX0_RXCHARISK_OUT : out std_logic;
GTX0_RXDISPERR_OUT : out std_logic;
GTX0_RXNOTINTABLE_OUT : out std_logic;
GTX0_RXRUNDISP_OUT : out std_logic;
------------------- Receive Ports - Clock Correction Ports -----------------
GTX0_RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
GTX0_RXENMCOMMAALIGN_IN : in std_logic;
GTX0_RXENPCOMMAALIGN_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
GTX0_RXRECCLK_OUT : out std_logic;
GTX0_RXRESET_IN : in std_logic;
GTX0_RXUSRCLK2_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GTX0_RXELECIDLE_OUT : out std_logic;
GTX0_RXN_IN : in std_logic;
GTX0_RXP_IN : in std_logic;
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GTX0_RXBUFRESET_IN : in std_logic;
GTX0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
------------------------ Receive Ports - RX PLL Ports ----------------------
GTX0_GTXRXRESET_IN : in std_logic;
GTX0_MGTREFCLKRX_IN : in std_logic;
GTX0_PLLRXRESET_IN : in std_logic;
GTX0_RXPLLLKDET_OUT : out std_logic;
GTX0_RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GTX0_TXCHARDISPMODE_IN : in std_logic;
GTX0_TXCHARDISPVAL_IN : in std_logic;
GTX0_TXCHARISK_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
GTX0_TXOUTCLK_OUT : out std_logic;
GTX0_TXRESET_IN : in std_logic;
GTX0_TXUSRCLK2_IN : in std_logic;
---------------- Transmit Ports - TX Driver and OOB signaling --------------
GTX0_TXN_OUT : out std_logic;
GTX0_TXP_OUT : out std_logic;
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
GTX0_TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTX0_GTXTXRESET_IN : in std_logic;
GTX0_TXRESETDONE_OUT : out std_logic
);
end V6_GTXWIZARD;
architecture RTL of V6_GTXWIZARD is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of RTL : architecture is "V6_GTXWIZARD,v6_gtxwizard_v1_5,{protocol_file=gigabit_ethernet}";
--***************************** Signal Declarations *****************************
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
signal tied_to_vcc_i : std_logic;
signal gtx0_share_rxpll_i : std_logic_vector(1 downto 0);
signal gtx0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
--*************************** Component Declarations **************************
component V6_GTXWIZARD_GTX
generic
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP : integer := 0;
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE : string := "TXPLL";
-- Save power parameter
GTX_POWER_SAVE : bit_vector := "0000000000"
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN : in std_logic_vector(2 downto 0);
RXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
TXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT : out std_logic;
RXCHARISK_OUT : out std_logic;
RXDISPERR_OUT : out std_logic;
RXNOTINTABLE_OUT : out std_logic;
RXRUNDISP_OUT : out std_logic;
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN_IN : in std_logic;
RXENPCOMMAALIGN_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT : out std_logic_vector(7 downto 0);
RXRECCLK_OUT : out std_logic;
RXRESET_IN : in std_logic;
RXUSRCLK2_IN : in std_logic;
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXELECIDLE_OUT : out std_logic;
RXN_IN : in std_logic;
RXP_IN : in std_logic;
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET_IN : in std_logic;
RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN : in std_logic;
MGTREFCLKRX_IN : in std_logic_vector(1 downto 0);
PLLRXRESET_IN : in std_logic;
RXPLLLKDET_OUT : out std_logic;
RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARDISPMODE_IN : in std_logic;
TXCHARDISPVAL_IN : in std_logic;
TXCHARISK_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN : in std_logic_vector(7 downto 0);
TXOUTCLK_OUT : out std_logic;
TXRESET_IN : in std_logic;
TXUSRCLK2_IN : in std_logic;
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT : out std_logic;
TXP_OUT : out std_logic;
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN : in std_logic;
MGTREFCLKTX_IN : in std_logic_vector(1 downto 0);
PLLTXRESET_IN : in std_logic;
TXPLLLKDET_OUT : out std_logic;
TXRESETDONE_OUT : out std_logic
);
end component;
--********************************* Main Body of Code**************************
begin
tied_to_ground_i <= '0';
tied_to_ground_vec_i(63 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
gtx0_mgtrefclkrx_i <= (tied_to_ground_i & GTX0_MGTREFCLKRX_IN);
--------------------------- GTX Instances -------------------------------
--_________________________________________________________________________
--_________________________________________________________________________
--GTX0 (X0Y8)
gtx0_v6_gtxwizard_i : V6_GTXWIZARD_GTX
generic map
(
-- Simulation attributes
GTX_SIM_GTXRESET_SPEEDUP => WRAPPER_SIM_GTXRESET_SPEEDUP,
-- Share RX PLL parameter
GTX_TX_CLK_SOURCE => "RXPLL",
-- Save power parameter
GTX_POWER_SAVE => "0000110100"
)
port map
(
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK_IN => GTX0_LOOPBACK_IN,
RXPOWERDOWN_IN => GTX0_RXPOWERDOWN_IN,
TXPOWERDOWN_IN => GTX0_TXPOWERDOWN_IN,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA_OUT => GTX0_RXCHARISCOMMA_OUT,
RXCHARISK_OUT => GTX0_RXCHARISK_OUT,
RXDISPERR_OUT => GTX0_RXDISPERR_OUT,
RXNOTINTABLE_OUT => GTX0_RXNOTINTABLE_OUT,
RXRUNDISP_OUT => GTX0_RXRUNDISP_OUT,
------------------- Receive Ports - Clock Correction Ports -----------------
RXCLKCORCNT_OUT => GTX0_RXCLKCORCNT_OUT,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXENMCOMMAALIGN_IN => GTX0_RXENMCOMMAALIGN_IN,
RXENPCOMMAALIGN_IN => GTX0_RXENPCOMMAALIGN_IN,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT => GTX0_RXDATA_OUT,
RXRECCLK_OUT => GTX0_RXRECCLK_OUT,
RXRESET_IN => GTX0_RXRESET_IN,
RXUSRCLK2_IN => GTX0_RXUSRCLK2_IN,
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
RXELECIDLE_OUT => GTX0_RXELECIDLE_OUT,
RXN_IN => GTX0_RXN_IN,
RXP_IN => GTX0_RXP_IN,
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET_IN => GTX0_RXBUFRESET_IN,
RXBUFSTATUS_OUT => GTX0_RXBUFSTATUS_OUT,
------------------------ Receive Ports - RX PLL Ports ----------------------
GTXRXRESET_IN => GTX0_GTXRXRESET_IN,
MGTREFCLKRX_IN => gtx0_mgtrefclkrx_i,
PLLRXRESET_IN => GTX0_PLLRXRESET_IN,
RXPLLLKDET_OUT => GTX0_RXPLLLKDET_OUT,
RXRESETDONE_OUT => GTX0_RXRESETDONE_OUT,
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
TXCHARDISPMODE_IN => GTX0_TXCHARDISPMODE_IN,
TXCHARDISPVAL_IN => GTX0_TXCHARDISPVAL_IN,
TXCHARISK_IN => GTX0_TXCHARISK_IN,
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATA_IN => GTX0_TXDATA_IN,
TXOUTCLK_OUT => GTX0_TXOUTCLK_OUT,
TXRESET_IN => GTX0_TXRESET_IN,
TXUSRCLK2_IN => GTX0_TXUSRCLK2_IN,
---------------- Transmit Ports - TX Driver and OOB signaling --------------
TXN_OUT => GTX0_TXN_OUT,
TXP_OUT => GTX0_TXP_OUT,
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS_OUT => GTX0_TXBUFSTATUS_OUT,
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTXTXRESET_IN => GTX0_GTXTXRESET_IN,
MGTREFCLKTX_IN => gtx0_mgtrefclkrx_i,
PLLTXRESET_IN => tied_to_ground_i,
TXPLLLKDET_OUT => open,
TXRESETDONE_OUT => GTX0_TXRESETDONE_OUT
);
end RTL;
|
gpl-3.0
|
03ee406a700f236d6f58e4eb5adea210
| 0.464132 | 4.835458 | false | false | false | false |
luebbers/reconos
|
support/templates/bfmsim_plb_osif_v2_01_a/simulation/behavioral/plb_bus_wrapper.vhd
| 1 | 13,044 |
-------------------------------------------------------------------------------
-- plb_bus_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v34_v1_02_a;
use plb_v34_v1_02_a.All;
entity plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 15);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_compress : in std_logic_vector(0 to 1);
M_guarded : in std_logic_vector(0 to 1);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_ordered : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : in std_logic_vector(0 to 1);
Sl_MErr : in std_logic_vector(0 to 3);
Sl_MBusy : in std_logic_vector(0 to 3);
Sl_rdBTerm : in std_logic_vector(0 to 1);
Sl_rdComp : in std_logic_vector(0 to 1);
Sl_rdDAck : in std_logic_vector(0 to 1);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 7);
Sl_rearbitrate : in std_logic_vector(0 to 1);
Sl_SSize : in std_logic_vector(0 to 3);
Sl_wait : in std_logic_vector(0 to 1);
Sl_wrBTerm : in std_logic_vector(0 to 1);
Sl_wrComp : in std_logic_vector(0 to 1);
Sl_wrDAck : in std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 127);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_compress : out std_logic;
PLB_guarded : out std_logic;
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_ordered : out std_logic;
PLB_pendPri : out std_logic_vector(0 to 1);
PLB_pendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic;
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic;
PLB_SaddrAck : out std_logic;
PLB_SMErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 1);
ArbAddrVldReg : out std_logic;
Bus_Error_Det : out std_logic
);
end plb_bus_wrapper;
architecture STRUCTURE of plb_bus_wrapper is
component plb_v34 is
generic (
C_PLB_NUM_MASTERS : integer;
C_PLB_NUM_SLAVES : integer;
C_PLB_MID_WIDTH : integer;
C_PLB_AWIDTH : integer;
C_PLB_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_NUM_OPBCLK_PLB2OPB_REARB : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1);
M_BE : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*(C_PLB_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_compress : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_guarded : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_lockErr : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*2)-1);
M_ordered : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_priority : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLB_NUM_MASTERS*C_PLB_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_MErr : in std_logic_vector(0 to (C_PLB_NUM_SLAVES*C_PLB_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLB_NUM_SLAVES*C_PLB_NUM_MASTERS - 1);
Sl_rdBTerm : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLB_NUM_SLAVES*C_PLB_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLB_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLB_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
PLB_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : out std_logic_vector(0 to (C_PLB_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLB_NUM_MASTERS*C_PLB_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLB_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLB_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_compress : out std_logic;
PLB_guarded : out std_logic;
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_ordered : out std_logic;
PLB_pendPri : out std_logic_vector(0 to 1);
PLB_pendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic;
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : out std_logic;
PLB_SaddrAck : out std_logic;
PLB_SMErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to C_PLB_NUM_SLAVES-1);
ArbAddrVldReg : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
plb_bus : plb_v34
generic map (
C_PLB_NUM_MASTERS => 2,
C_PLB_NUM_SLAVES => 2,
C_PLB_MID_WIDTH => 1,
C_PLB_AWIDTH => 32,
C_PLB_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 0,
C_IRQ_ACTIVE => '1',
C_NUM_OPBCLK_PLB2OPB_REARB => 5
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MErr => Sl_MErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMErr => PLB_SMErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
PLB2OPB_rearb => PLB2OPB_rearb,
ArbAddrVldReg => ArbAddrVldReg,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
gpl-3.0
|
3e8a93f6318e25fbbb9decb350732338
| 0.602269 | 3.049088 | false | false | false | false |
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